|
|
@@ -0,0 +1,32676 @@
|
|
|
+/*
|
|
|
+ * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
|
|
|
+ *
|
|
|
+ * SPDX-License-Identifier: Apache-2.0
|
|
|
+ *
|
|
|
+ * Licensed under the Apache License, Version 2.0 (the License); you may
|
|
|
+ * not use this file except in compliance with the License.
|
|
|
+ * You may obtain a copy of the License at
|
|
|
+ *
|
|
|
+ * http://www.apache.org/licenses/LICENSE-2.0
|
|
|
+ *
|
|
|
+ * Unless required by applicable law or agreed to in writing, software
|
|
|
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
|
|
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
|
+ * See the License for the specific language governing permissions and
|
|
|
+ * limitations under the License.
|
|
|
+ *
|
|
|
+ * @file ./out/R7FA8M1AH.h
|
|
|
+ * @brief CMSIS HeaderFile
|
|
|
+ * @version 1.2
|
|
|
+ */
|
|
|
+
|
|
|
+/** @addtogroup Renesas
|
|
|
+ * @{
|
|
|
+ */
|
|
|
+
|
|
|
+/** @addtogroup R7FA8M1AH
|
|
|
+ * @{
|
|
|
+ */
|
|
|
+
|
|
|
+#ifndef R7FA8M1AH_H
|
|
|
+ #define R7FA8M1AH_H
|
|
|
+
|
|
|
+ #ifdef __cplusplus
|
|
|
+extern "C" {
|
|
|
+ #endif
|
|
|
+
|
|
|
+/** @addtogroup Configuration_of_CMSIS
|
|
|
+ * @{
|
|
|
+ */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ Interrupt Number Definition ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ Processor and Core Peripheral Section ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================== Configuration of the ARM Cortex-M85 Processor and Core Peripherals =========================== */
|
|
|
+ #define __CM85_REV 0x0000U /*!< CM85 Core Revision */
|
|
|
+ #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */
|
|
|
+ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
|
|
+ #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
|
|
|
+ #define __MPU_PRESENT 1 /*!< MPU present */
|
|
|
+ #define __FPU_PRESENT 1 /*!< FPU present */
|
|
|
+ #define __FPU_DP 0 /*!< Double Precision FPU */
|
|
|
+ #define __DSP_PRESENT 1 /*!< DSP extension present */
|
|
|
+ #define __ICACHE_PRESENT 1 /*!< Instruction Cache present */
|
|
|
+ #define __DCACHE_PRESENT 1 /*!< Data Cache present */
|
|
|
+ #define __SAUREGION_PRESENT 1 /*!< SAU region present */
|
|
|
+ #define __PMU_PRESENT 0 /*!< PMU present */
|
|
|
+ #define __PMU_NUM_EVENTCNT 0 /*!< PMU Event Counters */
|
|
|
+
|
|
|
+/** @} */ /* End of group Configuration_of_CMSIS */
|
|
|
+
|
|
|
+ #include "core_cm85.h" /*!< ARM Cortex-M85 processor and core peripherals */
|
|
|
+ #include "system.h" /*!< R7FA8M1AH System */
|
|
|
+
|
|
|
+ #ifndef __IM /*!< Fallback for older CMSIS versions */
|
|
|
+ #define __IM __I
|
|
|
+ #endif
|
|
|
+ #ifndef __OM /*!< Fallback for older CMSIS versions */
|
|
|
+ #define __OM __O
|
|
|
+ #endif
|
|
|
+ #ifndef __IOM /*!< Fallback for older CMSIS versions */
|
|
|
+ #define __IOM __IO
|
|
|
+ #endif
|
|
|
+
|
|
|
+/* ======================================== Start of section using anonymous unions ======================================== */
|
|
|
+ #if defined(__CC_ARM)
|
|
|
+ #pragma push
|
|
|
+ #pragma anon_unions
|
|
|
+ #elif defined(__ICCARM__)
|
|
|
+ #pragma language=extended
|
|
|
+ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
|
|
+ #pragma clang diagnostic push
|
|
|
+ #pragma clang diagnostic ignored "-Wc11-extensions"
|
|
|
+ #pragma clang diagnostic ignored "-Wreserved-id-macro"
|
|
|
+ #pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
|
|
|
+ #pragma clang diagnostic ignored "-Wnested-anon-types"
|
|
|
+ #elif defined(__GNUC__)
|
|
|
+
|
|
|
+/* anonymous unions are enabled by default */
|
|
|
+ #elif defined(__TMS470__)
|
|
|
+
|
|
|
+/* anonymous unions are enabled by default */
|
|
|
+ #elif defined(__TASKING__)
|
|
|
+ #pragma warning 586
|
|
|
+ #elif defined(__CSMC__)
|
|
|
+
|
|
|
+/* anonymous unions are enabled by default */
|
|
|
+ #else
|
|
|
+ #warning Not supported compiler type
|
|
|
+ #endif
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ Device Specific Cluster Section ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/** @addtogroup Device_Peripheral_clusters
|
|
|
+ * @{
|
|
|
+ */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief R_BUS_CSa [CSa] (CS Registers)
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IM uint16_t RESERVED;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */
|
|
|
+ uint16_t : 4;
|
|
|
+ __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */
|
|
|
+ __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */
|
|
|
+ uint16_t : 5;
|
|
|
+ __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */
|
|
|
+ } MOD_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select */
|
|
|
+ uint32_t : 5;
|
|
|
+ __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select */
|
|
|
+ uint32_t : 5;
|
|
|
+ __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */
|
|
|
+ uint32_t : 3;
|
|
|
+ } WCR1_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */
|
|
|
+ uint32_t : 1;
|
|
|
+ } WCR2_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED1;
|
|
|
+} R_BUS_CSa_Type; /*!< Size = 16 (0x10) */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief R_BUS_CSb [CSb] (CS Registers)
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IM uint16_t RESERVED;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */
|
|
|
+ uint16_t : 3;
|
|
|
+ __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */
|
|
|
+ uint16_t : 3;
|
|
|
+ __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */
|
|
|
+ uint16_t : 3;
|
|
|
+ } CR_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED1[3];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */
|
|
|
+ uint16_t : 4;
|
|
|
+ __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */
|
|
|
+ uint16_t : 4;
|
|
|
+ } REC_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED2[2];
|
|
|
+} R_BUS_CSb_Type; /*!< Size = 16 (0x10) */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers)
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SDCCR; /*!< (@ 0x00000000) SDC Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t EXENB : 1; /*!< [0..0] Operation Enable */
|
|
|
+ uint8_t : 3;
|
|
|
+ __IOM uint8_t BSIZE : 2; /*!< [5..4] SDRAM Bus Width Select */
|
|
|
+ uint8_t : 2;
|
|
|
+ } SDCCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SDCMOD; /*!< (@ 0x00000001) SDC Mode Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t EMODE : 1; /*!< [0..0] Endian Mode */
|
|
|
+ uint8_t : 7;
|
|
|
+ } SDCMOD_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SDAMOD; /*!< (@ 0x00000002) SDRAM Access Mode Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t BE : 1; /*!< [0..0] Continuous Access Enable */
|
|
|
+ uint8_t : 7;
|
|
|
+ } SDAMOD_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED;
|
|
|
+ __IM uint32_t RESERVED1[3];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SDSELF; /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t SFEN : 1; /*!< [0..0] SDRAM Self-Refresh Enable */
|
|
|
+ uint8_t : 7;
|
|
|
+ } SDSELF_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED2;
|
|
|
+ __IM uint16_t RESERVED3;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t SDRFCR; /*!< (@ 0x00000014) SDRAM Refresh Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t RFC : 12; /*!< [11..0] Auto-Refresh Request Interval Setting */
|
|
|
+ __IOM uint16_t REFW : 4; /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count
|
|
|
+ * Setting. ( REFW+1 Cycles ) */
|
|
|
+ } SDRFCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SDRFEN; /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t RFEN : 1; /*!< [0..0] Auto-Refresh Operation Enable */
|
|
|
+ uint8_t : 7;
|
|
|
+ } SDRFEN_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED4;
|
|
|
+ __IM uint32_t RESERVED5[2];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SDICR; /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t INIRQ : 1; /*!< [0..0] Initialization Sequence Start */
|
|
|
+ uint8_t : 7;
|
|
|
+ } SDICR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED6;
|
|
|
+ __IM uint16_t RESERVED7;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t SDIR; /*!< (@ 0x00000024) SDRAM Initialization Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t ARFI : 4; /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles ) */
|
|
|
+ __IOM uint16_t ARFC : 4; /*!< [7..4] Initialization Auto-Refresh Count */
|
|
|
+ __IOM uint16_t PRC : 3; /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles
|
|
|
+ * ) */
|
|
|
+ uint16_t : 5;
|
|
|
+ } SDIR_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED8;
|
|
|
+ __IM uint32_t RESERVED9[6];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SDADR; /*!< (@ 0x00000040) SDRAM Address Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t MXC : 2; /*!< [1..0] Address Multiplex Select */
|
|
|
+ uint8_t : 6;
|
|
|
+ } SDADR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED10;
|
|
|
+ __IM uint16_t RESERVED11;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SDTR; /*!< (@ 0x00000044) SDRAM Timing Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CL : 3; /*!< [2..0] SDRAMC Column Latency */
|
|
|
+ uint32_t : 5;
|
|
|
+ __IOM uint32_t WR : 1; /*!< [8..8] Write Recovery Interval */
|
|
|
+ __IOM uint32_t RP : 3; /*!< [11..9] Row Precharge Interval ( RP+1 cycles ) */
|
|
|
+ __IOM uint32_t RCD : 2; /*!< [13..12] Row Column Latency ( RCD+1 cycles ) */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t RAS : 3; /*!< [18..16] Row Active Interval */
|
|
|
+ uint32_t : 13;
|
|
|
+ } SDTR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t SDMOD; /*!< (@ 0x00000048) SDRAM Mode Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t MR : 15; /*!< [14..0] Mode Register Setting */
|
|
|
+ uint16_t : 1;
|
|
|
+ } SDMOD_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED12;
|
|
|
+ __IM uint32_t RESERVED13;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint8_t SDSR; /*!< (@ 0x00000050) SDRAM Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint8_t MRSST : 1; /*!< [0..0] Mode Register Setting Status */
|
|
|
+ uint8_t : 2;
|
|
|
+ __IM uint8_t INIST : 1; /*!< [3..3] Initialization Status */
|
|
|
+ __IM uint8_t SRFST : 1; /*!< [4..4] Self-Refresh Transition/Recovery Status */
|
|
|
+ uint8_t : 3;
|
|
|
+ } SDSR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED14;
|
|
|
+ __IM uint16_t RESERVED15;
|
|
|
+} R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers)
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error Address */
|
|
|
+ } ADD_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status */
|
|
|
+ uint8_t : 6;
|
|
|
+ __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status */
|
|
|
+ } STAT_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint8_t RW; /*!< (@ 0x00000004) Bus Error Read Write */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status */
|
|
|
+ uint8_t : 7;
|
|
|
+ } RW_b;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED;
|
|
|
+ __IM uint16_t RESERVED1;
|
|
|
+ __IM uint32_t RESERVED2[2];
|
|
|
+} R_BUS_BUSERRa_Type; /*!< Size = 16 (0x10) */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers)
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t ADD; /*!< (@ 0x00000000) BUS TZF Error Address */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address */
|
|
|
+ } ADD_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint8_t RW; /*!< (@ 0x00000004) BUS TZF Error Read Write */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter error access Read/Write Status */
|
|
|
+ uint8_t : 7;
|
|
|
+ } RW_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED;
|
|
|
+ __IM uint16_t RESERVED1;
|
|
|
+ __IM uint32_t RESERVED2[2];
|
|
|
+} R_BUS_BTZFERR_Type; /*!< Size = 16 (0x10) */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers)
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint8_t STAT; /*!< (@ 0x00000000) Bus Error Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status. */
|
|
|
+ __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status. */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status. */
|
|
|
+ __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status. */
|
|
|
+ __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status. */
|
|
|
+ uint8_t : 2;
|
|
|
+ } STAT_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED[7];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t CLR; /*!< (@ 0x00000008) Bus Error Clear Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear. */
|
|
|
+ __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status. */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear. */
|
|
|
+ __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear. */
|
|
|
+ __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear. */
|
|
|
+ uint8_t : 2;
|
|
|
+ } CLR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED1[7];
|
|
|
+} R_BUS_BUSERRb_Type; /*!< Size = 16 (0x10) */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers)
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IM uint8_t RESERVED[36];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint8_t STAT; /*!< (@ 0x00000024) DMAC/DTC Error Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */
|
|
|
+ uint8_t : 7;
|
|
|
+ } STAT_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED1[7];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t CLR; /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */
|
|
|
+ uint8_t : 7;
|
|
|
+ } CLR_b;
|
|
|
+ };
|
|
|
+} R_BUS_DMACDTCERR_Type; /*!< Size = 45 (0x2d) */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers)
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IM uint32_t RESERVED[2];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t MRE0BI; /*!< (@ 0x00000008) Bus Slave Arbitration Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */
|
|
|
+ uint32_t : 31;
|
|
|
+ } MRE0BI_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED1;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t FLBI; /*!< (@ 0x00000010) Bus Slave Arbitration Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */
|
|
|
+ uint32_t : 31;
|
|
|
+ } FLBI_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED2[3];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t S0BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */
|
|
|
+ uint32_t : 31;
|
|
|
+ } S0BI_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED3;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t S1BI; /*!< (@ 0x00000028) Bus Slave Arbitration Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */
|
|
|
+ uint32_t : 31;
|
|
|
+ } S1BI_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED4;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t S2BI; /*!< (@ 0x00000030) Bus Slave Arbitration Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */
|
|
|
+ uint32_t : 31;
|
|
|
+ } S2BI_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED5;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t S3BI; /*!< (@ 0x00000038) Bus Slave Arbitration Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */
|
|
|
+ uint32_t : 31;
|
|
|
+ } S3BI_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED6[3];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t STBYSBI; /*!< (@ 0x00000048) Bus Slave Arbitration Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */
|
|
|
+ uint32_t : 31;
|
|
|
+ } STBYSBI_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED7;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t ECBI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */
|
|
|
+ uint32_t : 31;
|
|
|
+ } ECBI_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SPI0BI; /*!< (@ 0x00000050) Bus Slave Arbitration Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */
|
|
|
+ uint32_t : 31;
|
|
|
+ } SPI0BI_b;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED8;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t EOBI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */
|
|
|
+ uint32_t : 31;
|
|
|
+ } EOBI_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SPI1BI; /*!< (@ 0x00000058) Bus Slave Arbitration Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */
|
|
|
+ uint32_t : 31;
|
|
|
+ } SPI1BI_b;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED9;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t PBBI; /*!< (@ 0x00000060) Bus Slave Arbitration Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */
|
|
|
+ uint32_t : 31;
|
|
|
+ } PBBI_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED10;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t PABI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */
|
|
|
+ uint32_t : 31;
|
|
|
+ } PABI_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CPU0SAHBI; /*!< (@ 0x00000068) Bus Slave Arbitration Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */
|
|
|
+ uint32_t : 31;
|
|
|
+ } CPU0SAHBI_b;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED11;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t PIBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */
|
|
|
+ uint32_t : 31;
|
|
|
+ } PIBI_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CPU1TCMBI; /*!< (@ 0x00000070) Bus Slave Arbitration Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */
|
|
|
+ uint32_t : 31;
|
|
|
+ } CPU1TCMBI_b;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED12;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t PSBI; /*!< (@ 0x00000078) Bus Slave Arbitration Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave. */
|
|
|
+ uint32_t : 31;
|
|
|
+ } PSBI_b;
|
|
|
+ };
|
|
|
+} R_BUS_BUSSABT0_Type; /*!< Size = 124 (0x7c) */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers)
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t FHBI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */
|
|
|
+ uint32_t : 30;
|
|
|
+ } FHBI_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t MRC0BI; /*!< (@ 0x00000000) Bus Slave Arbitration Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */
|
|
|
+ uint32_t : 30;
|
|
|
+ } MRC0BI_b;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED[5];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t S0BI; /*!< (@ 0x00000018) Bus Slave Arbitration Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */
|
|
|
+ uint32_t : 30;
|
|
|
+ } S0BI_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED1;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t S1BI; /*!< (@ 0x00000020) Bus Slave Arbitration Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave. */
|
|
|
+ uint32_t : 30;
|
|
|
+ } S1BI_b;
|
|
|
+ };
|
|
|
+} R_BUS_BUSSABT1_Type; /*!< Size = 36 (0x24) */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.)
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address. */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address. */
|
|
|
+ } ADD_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint8_t RW; /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read
|
|
|
+ * Write. */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write
|
|
|
+ * Status. */
|
|
|
+ uint8_t : 7;
|
|
|
+ } RW_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED;
|
|
|
+ __IM uint16_t RESERVED1;
|
|
|
+ __IM uint32_t RESERVED2[2];
|
|
|
+} R_BUS_BMSAERR_Type; /*!< Size = 16 (0x10) */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers)
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t BUSOAD; /*!< (@ 0x00000000) Bus Operation After Detection Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection. */
|
|
|
+ __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection. */
|
|
|
+ __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection. */
|
|
|
+ uint16_t : 13;
|
|
|
+ } BUSOAD_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t BUSOADPT; /*!< (@ 0x00000004) BUS Operation After Detection Protect Register. */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register. */
|
|
|
+ uint16_t : 7;
|
|
|
+ __OM uint16_t KEY : 8; /*!< [15..8] Key code */
|
|
|
+ } BUSOADPT_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED1[5];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t MSAOAD; /*!< (@ 0x00000010) Master Security Attribution Operation After Detection
|
|
|
+ * Register. */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t OAD : 1; /*!< [0..0] Master Security Attribution operation after detection. */
|
|
|
+ uint16_t : 7;
|
|
|
+ __OM uint16_t KEY : 8; /*!< [15..8] Key Code. */
|
|
|
+ } MSAOAD_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED2;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t MSAPT; /*!< (@ 0x00000014) Master Security Attribution Protect Register. */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register. */
|
|
|
+ uint16_t : 7;
|
|
|
+ __OM uint16_t KEY : 8; /*!< [15..8] Key code */
|
|
|
+ } MSAPT_b;
|
|
|
+ };
|
|
|
+} R_BUS_OAD_Type; /*!< Size = 22 (0x16) */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers)
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t STAT; /*!< (@ 0x00000000) Bufferable Write Error Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error in 0. */
|
|
|
+ __IM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error in 1. */
|
|
|
+ __IM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error in 2. */
|
|
|
+ __IM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error in 3. */
|
|
|
+ __IM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error in 4. */
|
|
|
+ __IM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error in 5. */
|
|
|
+ __IM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error in 6. */
|
|
|
+ __IM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error in 7. */
|
|
|
+ __IM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error in 8. */
|
|
|
+ __IM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error in 9. */
|
|
|
+ __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10. */
|
|
|
+ __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11. */
|
|
|
+ __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12. */
|
|
|
+ __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13. */
|
|
|
+ __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14. */
|
|
|
+ __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15. */
|
|
|
+ __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16. */
|
|
|
+ __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17. */
|
|
|
+ __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18. */
|
|
|
+ __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19. */
|
|
|
+ __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20. */
|
|
|
+ __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21. */
|
|
|
+ __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22. */
|
|
|
+ __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23. */
|
|
|
+ __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24. */
|
|
|
+ __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25. */
|
|
|
+ __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26. */
|
|
|
+ __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27. */
|
|
|
+ __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28. */
|
|
|
+ __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29. */
|
|
|
+ __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30. */
|
|
|
+ __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31. */
|
|
|
+ } STAT_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CLR; /*!< (@ 0x00000008) Bufferable Write Error Clear Register. */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t BWERR0 : 1; /*!< [0..0] Bufferable Write Error Clear for 0. */
|
|
|
+ __IOM uint32_t BWERR1 : 1; /*!< [1..1] Bufferable Write Error Clear for 1. */
|
|
|
+ __IOM uint32_t BWERR2 : 1; /*!< [2..2] Bufferable Write Error Clear for 2. */
|
|
|
+ __IOM uint32_t BWERR3 : 1; /*!< [3..3] Bufferable Write Error Clear for 3. */
|
|
|
+ __IOM uint32_t BWERR4 : 1; /*!< [4..4] Bufferable Write Error Clear for 4. */
|
|
|
+ __IOM uint32_t BWERR5 : 1; /*!< [5..5] Bufferable Write Error Clear for 5. */
|
|
|
+ __IOM uint32_t BWERR6 : 1; /*!< [6..6] Bufferable Write Error Clear for 6. */
|
|
|
+ __IOM uint32_t BWERR7 : 1; /*!< [7..7] Bufferable Write Error Clear for 7. */
|
|
|
+ __IOM uint32_t BWERR8 : 1; /*!< [8..8] Bufferable Write Error Clear for 8. */
|
|
|
+ __IOM uint32_t BWERR9 : 1; /*!< [9..9] Bufferable Write Error Clear for 9. */
|
|
|
+ __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10. */
|
|
|
+ __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11. */
|
|
|
+ __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12. */
|
|
|
+ __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13. */
|
|
|
+ __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14. */
|
|
|
+ __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15. */
|
|
|
+ __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16. */
|
|
|
+ __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17. */
|
|
|
+ __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18. */
|
|
|
+ __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19. */
|
|
|
+ __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20. */
|
|
|
+ __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21. */
|
|
|
+ __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22. */
|
|
|
+ __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23. */
|
|
|
+ __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24. */
|
|
|
+ __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25. */
|
|
|
+ __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26. */
|
|
|
+ __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27. */
|
|
|
+ __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28. */
|
|
|
+ __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29. */
|
|
|
+ __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30. */
|
|
|
+ __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31. */
|
|
|
+ } CLR_b;
|
|
|
+ };
|
|
|
+} R_BUS_MBWERR_Type; /*!< Size = 12 (0xc) */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers)
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint16_t : 15;
|
|
|
+ __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */
|
|
|
+ } CNT_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED;
|
|
|
+} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array)
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method */
|
|
|
+ uint16_t : 10;
|
|
|
+ } CNT_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED;
|
|
|
+} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief R_CANFD_CFDC [CFDC] (Channel Control/Status)
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t NCFG; /*!< (@ 0x00000000) Channel Nominal Bitrate Configuration Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t NBRP : 10; /*!< [9..0] Channel Nominal Baud Rate Prescaler */
|
|
|
+ __IOM uint32_t NSJW : 7; /*!< [16..10] Resynchronization Jump Width */
|
|
|
+ __IOM uint32_t NTSEG1 : 8; /*!< [24..17] Timing Segment 1 */
|
|
|
+ __IOM uint32_t NTSEG2 : 7; /*!< [31..25] Timing Segment 2 */
|
|
|
+ } NCFG_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CTR; /*!< (@ 0x00000004) Channel Control Registers */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CHMDC : 2; /*!< [1..0] Channel Mode Control */
|
|
|
+ __IOM uint32_t CSLPR : 1; /*!< [2..2] Channel Sleep Request */
|
|
|
+ __IOM uint32_t RTBO : 1; /*!< [3..3] Return from Bus-Off */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t BEIE : 1; /*!< [8..8] Bus Error Interrupt Enable */
|
|
|
+ __IOM uint32_t EWIE : 1; /*!< [9..9] Error Warning Interrupt Enable */
|
|
|
+ __IOM uint32_t EPIE : 1; /*!< [10..10] Error Passive Interrupt Enable */
|
|
|
+ __IOM uint32_t BOEIE : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable */
|
|
|
+ __IOM uint32_t BORIE : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable */
|
|
|
+ __IOM uint32_t OLIE : 1; /*!< [13..13] Overload Interrupt Enable */
|
|
|
+ __IOM uint32_t BLIE : 1; /*!< [14..14] Bus Lock Interrupt Enable */
|
|
|
+ __IOM uint32_t ALIE : 1; /*!< [15..15] Arbitration Lost Interrupt Enable */
|
|
|
+ __IOM uint32_t TAIE : 1; /*!< [16..16] Transmission abort Interrupt Enable */
|
|
|
+ __IOM uint32_t EOCOIE : 1; /*!< [17..17] Error occurrence counter overflow Interrupt enable */
|
|
|
+ __IOM uint32_t SOCOIE : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt enable */
|
|
|
+ __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt
|
|
|
+ * enable */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t BOM : 2; /*!< [22..21] Channel Bus-Off Mode */
|
|
|
+ __IOM uint32_t ERRD : 1; /*!< [23..23] Channel Error Display */
|
|
|
+ __IOM uint32_t CTME : 1; /*!< [24..24] Channel Test Mode Enable */
|
|
|
+ __IOM uint32_t CTMS : 2; /*!< [26..25] Channel Test Mode Select */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t CRCT : 1; /*!< [30..30] CRC Error Test */
|
|
|
+ __IOM uint32_t ROM : 1; /*!< [31..31] Restricted Operation Mode */
|
|
|
+ } CTR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t STS; /*!< (@ 0x00000008) Channel Status Registers */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t CRSTSTS : 1; /*!< [0..0] Channel RESET Status */
|
|
|
+ __IM uint32_t CHLTSTS : 1; /*!< [1..1] Channel HALT Status */
|
|
|
+ __IM uint32_t CSLPSTS : 1; /*!< [2..2] Channel SLEEP Status */
|
|
|
+ __IM uint32_t EPSTS : 1; /*!< [3..3] Channel Error Passive Status */
|
|
|
+ __IM uint32_t BOSTS : 1; /*!< [4..4] Channel Bus-Off Status */
|
|
|
+ __IM uint32_t TRMSTS : 1; /*!< [5..5] Channel Transmit Status */
|
|
|
+ __IM uint32_t RECSTS : 1; /*!< [6..6] Channel Receive Status */
|
|
|
+ __IM uint32_t COMSTS : 1; /*!< [7..7] Channel Communication Status */
|
|
|
+ __IOM uint32_t ESIF : 1; /*!< [8..8] Error State Indication Flag */
|
|
|
+ uint32_t : 7;
|
|
|
+ __IM uint32_t REC : 8; /*!< [23..16] Reception Error Count */
|
|
|
+ __IOM uint32_t TEC : 8; /*!< [31..24] Transmission Error Count */
|
|
|
+ } STS_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t ERFL; /*!< (@ 0x0000000C) Channel Error Flag Registers */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t BEF : 1; /*!< [0..0] Bus Error Flag */
|
|
|
+ __IOM uint32_t EWF : 1; /*!< [1..1] Error Warning Flag */
|
|
|
+ __IOM uint32_t EPF : 1; /*!< [2..2] Error Passive Flag */
|
|
|
+ __IOM uint32_t BOEF : 1; /*!< [3..3] Bus-Off Entry Flag */
|
|
|
+ __IOM uint32_t BORF : 1; /*!< [4..4] Bus-Off Recovery Flag */
|
|
|
+ __IOM uint32_t OVLF : 1; /*!< [5..5] Overload Flag */
|
|
|
+ __IOM uint32_t BLF : 1; /*!< [6..6] Bus Lock Flag */
|
|
|
+ __IOM uint32_t ALF : 1; /*!< [7..7] Arbitration Lost Flag */
|
|
|
+ __IOM uint32_t SERR : 1; /*!< [8..8] Stuff Error */
|
|
|
+ __IOM uint32_t FERR : 1; /*!< [9..9] Form Error */
|
|
|
+ __IOM uint32_t AERR : 1; /*!< [10..10] Acknowledge Error */
|
|
|
+ __IOM uint32_t CERR : 1; /*!< [11..11] CRC Error */
|
|
|
+ __IOM uint32_t B1ERR : 1; /*!< [12..12] Bit 1 Error */
|
|
|
+ __IOM uint32_t B0ERR : 1; /*!< [13..13] Bit 0 Error */
|
|
|
+ __IOM uint32_t ADERR : 1; /*!< [14..14] Acknowledge Delimiter Error */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Register value */
|
|
|
+ uint32_t : 1;
|
|
|
+ } ERFL_b;
|
|
|
+ };
|
|
|
+} R_CANFD_CFDC_Type; /*!< Size = 16 (0x10) */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief R_CANFD_CFDC2 [CFDC2] (Channel Configuration Registers)
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t DCFG; /*!< (@ 0x00000000) Channel Data Bitrate Configuration Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t DBRP : 8; /*!< [7..0] Channel Data Baud Rate Prescaler */
|
|
|
+ __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Timing Segment 1 */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Timing Segment 2 */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t DSJW : 4; /*!< [27..24] Resynchronization Jump Width */
|
|
|
+ uint32_t : 4;
|
|
|
+ } DCFG_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t FDCFG; /*!< (@ 0x00000004) Channel CAN-FD Configuration Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration */
|
|
|
+ uint32_t : 5;
|
|
|
+ __IOM uint32_t TDCOC : 1; /*!< [8..8] Transceiver Delay Compensation Offset Configuration */
|
|
|
+ __IOM uint32_t TDCE : 1; /*!< [9..9] Transceiver Delay Compensation Enable */
|
|
|
+ __IOM uint32_t ESIC : 1; /*!< [10..10] Error State Indication Configuration */
|
|
|
+ uint32_t : 5;
|
|
|
+ __IOM uint32_t TDCO : 8; /*!< [23..16] Transceiver Delay Compensation Offset */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t FDOE : 1; /*!< [28..28] FD only enable */
|
|
|
+ __IOM uint32_t REFE : 1; /*!< [29..29] RX edge filter enable */
|
|
|
+ __IOM uint32_t CLOE : 1; /*!< [30..30] Classical CAN only enable */
|
|
|
+ uint32_t : 1;
|
|
|
+ } FDCFG_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t FDCTR; /*!< (@ 0x00000008) Channel CAN-FD Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear */
|
|
|
+ __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear */
|
|
|
+ uint32_t : 30;
|
|
|
+ } FDCTR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t FDSTS; /*!< (@ 0x0000000C) Channel CAN-FD Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t TDCR : 8; /*!< [7..0] Transceiver Delay Compensation Result */
|
|
|
+ __IOM uint32_t EOCO : 1; /*!< [8..8] Error occurrence counter overflow */
|
|
|
+ __IOM uint32_t SOCO : 1; /*!< [9..9] Successful occurrence counter overflow */
|
|
|
+ uint32_t : 5;
|
|
|
+ __IOM uint32_t TDCVF : 1; /*!< [15..15] Transceiver Delay Compensation Violation Flag */
|
|
|
+ __IM uint32_t EOC : 8; /*!< [23..16] Error occurrence counter register */
|
|
|
+ __IM uint32_t SOC : 8; /*!< [31..24] Successful occurrence counter register */
|
|
|
+ } FDSTS_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t FDCRC; /*!< (@ 0x00000010) Channel CAN-FD CRC Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register value */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IM uint32_t SCNT : 4; /*!< [27..24] Stuff bit count */
|
|
|
+ uint32_t : 4;
|
|
|
+ } FDCRC_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED[3];
|
|
|
+} R_CANFD_CFDC2_Type; /*!< Size = 32 (0x20) */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief R_CANFD_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers)
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t ID; /*!< (@ 0x00000000) Global Acceptance Filter List ID Registers */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t GAFLID : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field */
|
|
|
+ __IOM uint32_t GAFLLB : 1; /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration */
|
|
|
+ __IOM uint32_t GAFLRTR : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Field */
|
|
|
+ __IOM uint32_t GAFLIDE : 1; /*!< [31..31] Global Acceptance Filter List Entry IDE Field */
|
|
|
+ } ID_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t M; /*!< (@ 0x00000004) Global Acceptance Filter List Mask Registers */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t GAFLIDM : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field */
|
|
|
+ __IOM uint32_t GAFLIFL1 : 1; /*!< [29..29] Global Acceptance Filter List Information Label 1 */
|
|
|
+ __IOM uint32_t GAFLRTRM : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Mask */
|
|
|
+ __IOM uint32_t GAFLIDEM : 1; /*!< [31..31] Global Acceptance Filter List IDE Mask */
|
|
|
+ } M_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t P0; /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Registers */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t GAFLDLC : 4; /*!< [3..0] Global Acceptance Filter List DLC Field */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0 */
|
|
|
+ __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction
|
|
|
+ * Pointer */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t GAFLRMV : 1; /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid */
|
|
|
+ __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer Field */
|
|
|
+ } P0_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t P1; /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Registers */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t GAFLFDP : 9; /*!< [8..0] Global Acceptance Filter List FIFO Direction Pointer */
|
|
|
+ uint32_t : 23;
|
|
|
+ } P1_b;
|
|
|
+ };
|
|
|
+} R_CANFD_CFDGAFL_Type; /*!< Size = 16 (0x10) */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief R_CANFD_CFDTHL [CFDTHL] (Channel TX History List)
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t ACC0; /*!< (@ 0x00000000) Channel TX History List Access Registers 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t BT : 3; /*!< [2..0] Buffer Type */
|
|
|
+ __IM uint32_t BN : 7; /*!< [9..3] Buffer No. */
|
|
|
+ uint32_t : 6;
|
|
|
+ __IM uint32_t TMTS : 16; /*!< [31..16] Transmit Timestamp */
|
|
|
+ } ACC0_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t ACC1; /*!< (@ 0x00000004) Channel TX History List Access Registers 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t TID : 16; /*!< [15..0] Transmit ID */
|
|
|
+ __IM uint32_t TIFL : 2; /*!< [17..16] Transmit Information Label */
|
|
|
+ uint32_t : 14;
|
|
|
+ } ACC1_b;
|
|
|
+ };
|
|
|
+} R_CANFD_CFDTHL_Type; /*!< Size = 8 (0x8) */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief R_CANFD_CFDRF [CFDRF] (RX FIFO Access Registers)
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t ID; /*!< (@ 0x00000000) RX FIFO Access ID Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t RFID : 29; /*!< [28..0] RX FIFO Buffer ID Field */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IM uint32_t RFRTR : 1; /*!< [30..30] RX FIFO Buffer RTR Frame */
|
|
|
+ __IM uint32_t RFIDE : 1; /*!< [31..31] RX FIFO Buffer IDE Bit */
|
|
|
+ } ID_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t PTR; /*!< (@ 0x00000004) RX FIFO Access Pointer Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t RFTS : 16; /*!< [15..0] RX FIFO Timestamp Field */
|
|
|
+ uint32_t : 12;
|
|
|
+ __IM uint32_t RFDLC : 4; /*!< [31..28] RX FIFO Buffer DLC Field */
|
|
|
+ } PTR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t RFESI : 1; /*!< [0..0] Error State Indicator bit */
|
|
|
+ __IM uint32_t RFBRS : 1; /*!< [1..1] Bit Rate Switch bit */
|
|
|
+ __IM uint32_t RFFDF : 1; /*!< [2..2] CAN FD Format bit */
|
|
|
+ uint32_t : 5;
|
|
|
+ __IM uint32_t RFIFL : 2; /*!< [9..8] RX FIFO Buffer Information Label Field */
|
|
|
+ uint32_t : 6;
|
|
|
+ __IM uint32_t RFPTR : 16; /*!< [31..16] RX FIFO Buffer Pointer Field */
|
|
|
+ } FDSTS_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX FIFO Access Data Field Registers */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint8_t RFDB : 8; /*!< [7..0] RX FIFO Buffer Data Byte */
|
|
|
+ } DF_b[64];
|
|
|
+ };
|
|
|
+} R_CANFD_CFDRF_Type; /*!< Size = 76 (0x4c) */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief R_CANFD_CFDCF [CFDCF] (Common FIFO Access Registers)
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t ID; /*!< (@ 0x00000000) Common FIFO Access ID Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFID : 29; /*!< [28..0] Common FIFO Buffer ID Field */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t CFRTR : 1; /*!< [30..30] Common FIFO Buffer RTR Frame */
|
|
|
+ __IOM uint32_t CFIDE : 1; /*!< [31..31] Common FIFO Buffer IDE Bit */
|
|
|
+ } ID_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t PTR; /*!< (@ 0x00000004) Common FIFO Access Pointer Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFTS : 16; /*!< [15..0] Common FIFO Timestamp Field */
|
|
|
+ uint32_t : 12;
|
|
|
+ __IOM uint32_t CFDLC : 4; /*!< [31..28] Common FIFO Buffer DLC Field */
|
|
|
+ } PTR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t FDSTS; /*!< (@ 0x00000008) Common FIFO Access CAN-FD Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFESI : 1; /*!< [0..0] Error State Indicator bit */
|
|
|
+ __IOM uint32_t CFBRS : 1; /*!< [1..1] Bit Rate Switch bit */
|
|
|
+ __IOM uint32_t CFFDF : 1; /*!< [2..2] CAN FD Format bit */
|
|
|
+ uint32_t : 5;
|
|
|
+ __IOM uint32_t CFIFL : 2; /*!< [9..8] Common FIFO Buffer Information Label Field */
|
|
|
+ uint32_t : 6;
|
|
|
+ __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field */
|
|
|
+ } FDSTS_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) Common FIFO Access Data Field Registers */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t CFDB : 8; /*!< [7..0] Common FIFO Buffer Data Byte */
|
|
|
+ } DF_b[64];
|
|
|
+ };
|
|
|
+} R_CANFD_CFDCF_Type; /*!< Size = 76 (0x4c) */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief R_CANFD_CFDTM [CFDTM] (TX Message Buffer Access Registers)
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t ID; /*!< (@ 0x00000000) TX Message Buffer ID Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t TMID : 29; /*!< [28..0] TX Message Buffer ID Field */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t TMRTR : 1; /*!< [30..30] TX Message Buffer RTR Frame */
|
|
|
+ __IOM uint32_t TMIDE : 1; /*!< [31..31] TX Message Buffer IDE Bit */
|
|
|
+ } ID_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t PTR; /*!< (@ 0x00000004) TX Message Buffer Pointer Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t TMTS : 16; /*!< [15..0] TX Message Buffer Timestamp Field */
|
|
|
+ uint32_t : 12;
|
|
|
+ __IOM uint32_t TMDLC : 4; /*!< [31..28] TX Message Buffer DLC Field */
|
|
|
+ } PTR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t FDCTR; /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t TMESI : 1; /*!< [0..0] Error State Indicator bit */
|
|
|
+ __IOM uint32_t TMBRS : 1; /*!< [1..1] Bit Rate Switch bit */
|
|
|
+ __IOM uint32_t TMFDF : 1; /*!< [2..2] CAN FD Format bit */
|
|
|
+ uint32_t : 5;
|
|
|
+ __IOM uint32_t TMIFL : 2; /*!< [9..8] TX Message Buffer Information Label Field */
|
|
|
+ uint32_t : 6;
|
|
|
+ __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field */
|
|
|
+ } FDCTR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) TX Message Buffer Data Field Registers */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t TMDB : 8; /*!< [7..0] TX Message Buffer Data Byte */
|
|
|
+ } DF_b[64];
|
|
|
+ };
|
|
|
+} R_CANFD_CFDTM_Type; /*!< Size = 76 (0x4c) */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief R_CANFD_CFDRM_RM [RM] (RX Message Buffer Access Registers)
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t ID; /*!< (@ 0x00000000) RX Message Buffer ID Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t RMID : 29; /*!< [28..0] RX Message Buffer ID Field */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IM uint32_t RMRTR : 1; /*!< [30..30] RX Message Buffer RTR Frame */
|
|
|
+ __IM uint32_t RMIDE : 1; /*!< [31..31] RX Message Buffer IDE Bit */
|
|
|
+ } ID_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t PTR; /*!< (@ 0x00000004) RX Message Buffer Pointer Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t RMTS : 16; /*!< [15..0] RX Message Buffer Timestamp Field */
|
|
|
+ uint32_t : 12;
|
|
|
+ __IM uint32_t RMDLC : 4; /*!< [31..28] RX Message Buffer DLC Field */
|
|
|
+ } PTR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t RMESI : 1; /*!< [0..0] Error State Indicator bit */
|
|
|
+ __IM uint32_t RMBRS : 1; /*!< [1..1] Bit Rate Switch bit */
|
|
|
+ __IM uint32_t RMFDF : 1; /*!< [2..2] CAN FD Format bit */
|
|
|
+ uint32_t : 5;
|
|
|
+ __IM uint32_t RMIFL : 2; /*!< [9..8] RX Message Buffer Information Label Field */
|
|
|
+ uint32_t : 6;
|
|
|
+ __IM uint32_t RMPTR : 16; /*!< [31..16] RX Message Buffer Pointer Field */
|
|
|
+ } FDSTS_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX Message Buffer Data Field Registers */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint8_t RMDB : 8; /*!< [7..0] RX Message Buffer Data Byte */
|
|
|
+ } DF_b[64];
|
|
|
+ };
|
|
|
+} R_CANFD_CFDRM_RM_Type; /*!< Size = 76 (0x4c) */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief R_CANFD_CFDRM [CFDRM] (RX Message Buffer Access Clusters)
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IOM R_CANFD_CFDRM_RM_Type RM[8]; /*!< (@ 0x00000000) RX Message Buffer Access Registers */
|
|
|
+ __IM uint32_t RESERVED[104];
|
|
|
+} R_CANFD_CFDRM_Type; /*!< Size = 1024 (0x400) */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register)
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */
|
|
|
+ uint8_t : 5;
|
|
|
+ __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */
|
|
|
+ __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */
|
|
|
+ } BY_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED;
|
|
|
+} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..30])
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */
|
|
|
+ uint16_t : 7;
|
|
|
+ } HA_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED;
|
|
|
+} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief R_IIC0_SAR [SAR] (Slave Address Registers)
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit
|
|
|
+ * Address = { SVA9,SVA8,SVA[7:0] } */
|
|
|
+ } L_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */
|
|
|
+ __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */
|
|
|
+ __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */
|
|
|
+ uint8_t : 5;
|
|
|
+ } U_b;
|
|
|
+ };
|
|
|
+} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief R_MPU_MMPU_GROUP_REGION [REGION] (Address region control)
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t AC; /*!< (@ 0x00000000) Access Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable */
|
|
|
+ __IOM uint16_t RP : 1; /*!< [1..1] Read protection */
|
|
|
+ __IOM uint16_t WP : 1; /*!< [2..2] Write protection */
|
|
|
+ __IOM uint16_t PP : 1; /*!< [3..3] Privilege protection */
|
|
|
+ uint16_t : 12;
|
|
|
+ } AC_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t S; /*!< (@ 0x00000004) Start Address Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination.
|
|
|
+ * NOTE: Some low-order bits are fixed to 0. */
|
|
|
+ } S_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t E; /*!< (@ 0x00000008) End Address Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region
|
|
|
+ * end, for use in region determination. NOTE: Some low-order
|
|
|
+ * bits are fixed to 1. */
|
|
|
+ } E_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED1;
|
|
|
+} R_MPU_MMPU_GROUP_REGION_Type; /*!< Size = 16 (0x10) */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..NPU] MMPU Registers)
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t EN; /*!< (@ 0x00000000) MMPU enable register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t ENABLE : 1; /*!< [0..0] Bus master MPU of DMAC enable */
|
|
|
+ uint16_t : 7;
|
|
|
+ __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not
|
|
|
+ * stored. */
|
|
|
+ } EN_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t ENPT; /*!< (@ 0x00000004) MMPU enable protect register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register EN */
|
|
|
+ uint16_t : 7;
|
|
|
+ __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not
|
|
|
+ * stored. */
|
|
|
+ } ENPT_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED1;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t RPT; /*!< (@ 0x00000008) MMPU Regions Protect Register Non-Secure */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */
|
|
|
+ uint16_t : 7;
|
|
|
+ __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not
|
|
|
+ * stored. */
|
|
|
+ } RPT_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED2;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t RPT_SEC; /*!< (@ 0x0000000C) MMPU Regions Protect Register Secure (DMAC only) */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */
|
|
|
+ uint16_t : 7;
|
|
|
+ __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not
|
|
|
+ * stored. */
|
|
|
+ } RPT_SEC_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED3;
|
|
|
+ __IM uint32_t RESERVED4[60];
|
|
|
+ __IOM R_MPU_MMPU_GROUP_REGION_Type REGION[8]; /*!< (@ 0x00000100) Address region control */
|
|
|
+ __IM uint32_t RESERVED5[32];
|
|
|
+} R_MPU_MMPU_GROUP_Type; /*!< Size = 512 (0x200) */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor)
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection
|
|
|
+ * Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */
|
|
|
+ uint16_t : 7;
|
|
|
+ __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not
|
|
|
+ * stored. */
|
|
|
+ } OAD_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */
|
|
|
+ uint16_t : 7;
|
|
|
+ __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */
|
|
|
+ uint16_t : 7;
|
|
|
+ } CTL_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */
|
|
|
+ uint16_t : 7;
|
|
|
+ __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not
|
|
|
+ * stored. */
|
|
|
+ } PT_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region
|
|
|
+ * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF
|
|
|
+ * The low-order 2 bits are fixed to 0. */
|
|
|
+ } SA_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region
|
|
|
+ * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF
|
|
|
+ * The low-order 2 bits are fixed to 1. */
|
|
|
+ } EA_b;
|
|
|
+ };
|
|
|
+} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects)
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */
|
|
|
+ __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */
|
|
|
+ __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */
|
|
|
+ __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Event on Rising. */
|
|
|
+ __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */
|
|
|
+ __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */
|
|
|
+ __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */
|
|
|
+ uint32_t : 7;
|
|
|
+ __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral
|
|
|
+ * function. For individual pin functions, see the MPC table */
|
|
|
+ uint32_t : 3;
|
|
|
+ } PmnPFS_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000000) Pin Function Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */
|
|
|
+ __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */
|
|
|
+ __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */
|
|
|
+ uint16_t : 3;
|
|
|
+ __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */
|
|
|
+ __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Event on Rising. */
|
|
|
+ __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */
|
|
|
+ __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */
|
|
|
+ } PmnPFS_HA_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000000) Pin Function Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */
|
|
|
+ __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */
|
|
|
+ __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */
|
|
|
+ uint8_t : 1;
|
|
|
+ } PmnPFS_BY_b;
|
|
|
+ };
|
|
|
+ };
|
|
|
+} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief R_PFS_PORT [PORT] (Port [0..14])
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */
|
|
|
+} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register)
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */
|
|
|
+ __IM uint16_t RESERVED;
|
|
|
+} R_PMISC_PMSAR_Type; /*!< Size = 4 (0x4) */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register)
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */
|
|
|
+ __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t TCEN : 1; /*!< [7..7] Time Capture Event Input Pin Enable */
|
|
|
+ } RTCCR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED;
|
|
|
+} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief R_RTC_CP [CP] (Capture registers)
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IM uint8_t RESERVED[2];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of
|
|
|
+ * seconds */
|
|
|
+ __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of
|
|
|
+ * seconds */
|
|
|
+ uint8_t : 1;
|
|
|
+ } RSEC_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0
|
|
|
+ * value when a time capture event is detected. */
|
|
|
+ } BCNT0_b;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED1;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of
|
|
|
+ * minutes */
|
|
|
+ __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of
|
|
|
+ * minutes */
|
|
|
+ uint8_t : 1;
|
|
|
+ } RMIN_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1
|
|
|
+ * value when a time capture event is detected. */
|
|
|
+ } BCNT1_b;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED2;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of
|
|
|
+ * minutes */
|
|
|
+ __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of
|
|
|
+ * minutes */
|
|
|
+ __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */
|
|
|
+ uint8_t : 1;
|
|
|
+ } RHR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2
|
|
|
+ * value when a time capture event is detected. */
|
|
|
+ } BCNT2_b;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED3[3];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */
|
|
|
+ __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */
|
|
|
+ uint8_t : 2;
|
|
|
+ } RDAY_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3
|
|
|
+ * value when a time capture event is detected. */
|
|
|
+ } BCNT3_b;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED4;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */
|
|
|
+ __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of
|
|
|
+ * months */
|
|
|
+ uint8_t : 3;
|
|
|
+ } RMON_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED5[3];
|
|
|
+} R_RTC_CP_Type; /*!< Size = 16 (0x10) */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers)
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint16_t : 8;
|
|
|
+ __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */
|
|
|
+ __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */
|
|
|
+ uint16_t : 6;
|
|
|
+ } E_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */
|
|
|
+ } N_b;
|
|
|
+ };
|
|
|
+} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief R_USB_HS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers)
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t E; /*!< (@ 0x00000000) PIPE Transaction Counter Enable Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint16_t : 8;
|
|
|
+ __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter ClearSetting this bit to 1 allows
|
|
|
+ * clearing the transaction counter to 0. */
|
|
|
+ __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter EnableEnables or disables the transaction
|
|
|
+ * counter function. */
|
|
|
+ uint16_t : 6;
|
|
|
+ } E_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t N; /*!< (@ 0x00000002) PIPE Transaction Counter Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction CounterWhen writing to: Specify the number
|
|
|
+ * of total packets (number of transactions) to be received
|
|
|
+ * by the relevant PIPE.When read from: When TRENB = 0: Indicate
|
|
|
+ * the specified number of transactions.When TRENB = 1: Indicate
|
|
|
+ * the number of currently counted transactions. */
|
|
|
+ } N_b;
|
|
|
+ };
|
|
|
+} R_USB_HS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief R_XSPI_CMCFGCS [CMCFGCS] (xSPI Command Map Configuration registers)
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CMCFG0; /*!< (@ 0x00000000) xSPI Command Map Configuration register 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t FFMT : 2; /*!< [1..0] Frame format */
|
|
|
+ __IOM uint32_t ADDSIZE : 2; /*!< [3..2] Address size */
|
|
|
+ __IOM uint32_t WPBSTMD : 1; /*!< [4..4] Wrapping burst mode */
|
|
|
+ __IOM uint32_t ARYAMD : 1; /*!< [5..5] Array address mode */
|
|
|
+ uint32_t : 10;
|
|
|
+ __IOM uint32_t ADDRPEN : 8; /*!< [23..16] Address Replace Enable */
|
|
|
+ __IOM uint32_t ADDRPCD : 8; /*!< [31..24] Address Replace Code */
|
|
|
+ } CMCFG0_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CMCFG1; /*!< (@ 0x00000004) xSPI Command Map Configuration register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t RDCMD : 16; /*!< [15..0] Read command */
|
|
|
+ __IOM uint32_t RDLATE : 5; /*!< [20..16] Read latency cycle */
|
|
|
+ uint32_t : 11;
|
|
|
+ } CMCFG1_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CMCFG2; /*!< (@ 0x00000008) xSPI Command Map Configuration register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t WRCMD : 16; /*!< [15..0] Write command */
|
|
|
+ __IOM uint32_t WRLATE : 5; /*!< [20..16] Write latency cycle */
|
|
|
+ uint32_t : 11;
|
|
|
+ } CMCFG2_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED;
|
|
|
+} R_XSPI_CMCFGCS_Type; /*!< Size = 16 (0x10) */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief R_XSPI_CDBUF [CDBUF] (xSPI BUF register)
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CDT; /*!< (@ 0x00000000) xSPI Command Manual Type buf */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CMDSIZE : 2; /*!< [1..0] Command Size */
|
|
|
+ __IOM uint32_t ADDSIZE : 3; /*!< [4..2] Address size */
|
|
|
+ __IOM uint32_t DATASIZE : 4; /*!< [8..5] Write/Read Data Size */
|
|
|
+ __IOM uint32_t LATE : 5; /*!< [13..9] Latency cycle */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t TRTYPE : 1; /*!< [15..15] Transaction Type */
|
|
|
+ __IOM uint32_t CMD : 16; /*!< [31..16] Command (1-2byte) */
|
|
|
+ } CDT_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CDA; /*!< (@ 0x00000004) xSPI Command Manual Address buf */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t ADD : 32; /*!< [31..0] Address */
|
|
|
+ } CDA_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CDD0; /*!< (@ 0x00000008) xSPI Command Manual Data 0 buf */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t DATA : 32; /*!< [31..0] Write/Read Data */
|
|
|
+ } CDD0_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CDD1; /*!< (@ 0x0000000C) xSPI Command Manual Data 1 buf */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t DATA : 32; /*!< [31..0] Write/Read Data */
|
|
|
+ } CDD1_b;
|
|
|
+ };
|
|
|
+} R_XSPI_CDBUF_Type; /*!< Size = 16 (0x10) */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief R_XSPI_CCCTLCS [CCCTLCS] (xSPI CS register)
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CCCTL0; /*!< (@ 0x00000000) xSPI Command Calibration Control register 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CAEN : 1; /*!< [0..0] Automatic Calibration Enable */
|
|
|
+ __IOM uint32_t CANOWR : 1; /*!< [1..1] Calibration no write mode */
|
|
|
+ uint32_t : 6;
|
|
|
+ __IOM uint32_t CAITV : 5; /*!< [12..8] Calibration interval */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t CASFTSTA : 5; /*!< [20..16] Calibration DS shift start value */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t CASFTEND : 5; /*!< [28..24] Calibration DS shift end value */
|
|
|
+ uint32_t : 3;
|
|
|
+ } CCCTL0_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CCCTL1; /*!< (@ 0x00000004) xSPI Command Calibration Control register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CACMDSIZE : 2; /*!< [1..0] Command Size */
|
|
|
+ __IOM uint32_t CAADDSIZE : 3; /*!< [4..2] Address size */
|
|
|
+ __IOM uint32_t CADATASIZE : 4; /*!< [8..5] Write/Read Data Size */
|
|
|
+ uint32_t : 7;
|
|
|
+ __IOM uint32_t CAWRLATE : 5; /*!< [20..16] Write Latency cycle */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t CARDLATE : 5; /*!< [28..24] Read Latency cycle */
|
|
|
+ uint32_t : 3;
|
|
|
+ } CCCTL1_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CCCTL2; /*!< (@ 0x00000008) xSPI Command Calibration Control register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CAWRCMD : 16; /*!< [15..0] Calibration pattern write command */
|
|
|
+ __IOM uint32_t CARDCMD : 16; /*!< [31..16] Calibration pattern read command */
|
|
|
+ } CCCTL2_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CCCTL3; /*!< (@ 0x0000000C) xSPI Command Calibration Control register 3 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CAADD : 32; /*!< [31..0] Calibration pattern address */
|
|
|
+ } CCCTL3_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CCCTL4; /*!< (@ 0x00000010) xSPI Command Calibration Control register 4 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data */
|
|
|
+ } CCCTL4_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CCCTL5; /*!< (@ 0x00000014) xSPI Command Calibration Control register 5 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data */
|
|
|
+ } CCCTL5_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CCCTL6; /*!< (@ 0x00000018) xSPI Command Calibration Control register 6 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data */
|
|
|
+ } CCCTL6_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CCCTL7; /*!< (@ 0x0000001C) xSPI Command Calibration Control register 7 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data */
|
|
|
+ } CCCTL7_b;
|
|
|
+ };
|
|
|
+} R_XSPI_CCCTLCS_Type; /*!< Size = 32 (0x20) */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL)
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t AGTCR; /*!< (@ 0x00000000) AGT Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */
|
|
|
+ __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */
|
|
|
+ __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */
|
|
|
+ __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */
|
|
|
+ __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */
|
|
|
+ __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */
|
|
|
+ } AGTCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t AGTMR1; /*!< (@ 0x00000001) AGT Mode Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */
|
|
|
+ __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */
|
|
|
+ __IOM uint8_t TCK : 3; /*!< [6..4] Count source */
|
|
|
+ uint8_t : 1;
|
|
|
+ } AGTMR1_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t AGTMR2; /*!< (@ 0x00000002) AGT Mode Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
|
|
|
+ * ratio */
|
|
|
+ uint8_t : 4;
|
|
|
+ __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */
|
|
|
+ } AGTMR2_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t AGTIOSEL_ALT; /*!< (@ 0x00000003) AGT Pin Select Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */
|
|
|
+ uint8_t : 2;
|
|
|
+ __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */
|
|
|
+ uint8_t : 3;
|
|
|
+ } AGTIOSEL_ALT_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t AGTIOC; /*!< (@ 0x00000004) AGT I/O Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
|
|
|
+ * mode. */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */
|
|
|
+ __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */
|
|
|
+ } AGTIOC_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t AGTISR; /*!< (@ 0x00000005) AGT Event Pin Select Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint8_t : 2;
|
|
|
+ __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */
|
|
|
+ uint8_t : 5;
|
|
|
+ } AGTISR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t AGTCMSR; /*!< (@ 0x00000006) AGT Compare Match Function Select Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */
|
|
|
+ __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */
|
|
|
+ __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */
|
|
|
+ __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */
|
|
|
+ __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */
|
|
|
+ uint8_t : 1;
|
|
|
+ } AGTCMSR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t AGTIOSEL; /*!< (@ 0x00000007) AGT Pin Select Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */
|
|
|
+ uint8_t : 2;
|
|
|
+ __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */
|
|
|
+ uint8_t : 3;
|
|
|
+ } AGTIOSEL_b;
|
|
|
+ };
|
|
|
+} R_AGTX0_AGT16_CTRL_Type; /*!< Size = 8 (0x8) */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers)
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is
|
|
|
+ * written to the TSTOP bit in the AGTCRn register, the 16-bit
|
|
|
+ * counter is forcibly stopped and set to FFFFH. */
|
|
|
+ } AGT_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
|
|
|
+ * written to the TSTOP bit in the AGTCRn register, set to
|
|
|
+ * FFFFH */
|
|
|
+ } AGTCMA_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
|
|
|
+ * written to the TSTOP bit in the AGTCR register, set to
|
|
|
+ * FFFFH */
|
|
|
+ } AGTCMB_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED;
|
|
|
+ __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL */
|
|
|
+} R_AGTX0_AGT16_Type; /*!< Size = 16 (0x10) */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers)
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t AGT; /*!< (@ 0x00000000) AGT 32-bit Counter Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t AGT : 32; /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is
|
|
|
+ * written to the TSTOP bit in the AGTCRn register, the 16-bit
|
|
|
+ * counter is forcibly stopped and set to FFFFH. */
|
|
|
+ } AGT_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t AGTCMA; /*!< (@ 0x00000004) AGT Compare Match A Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is
|
|
|
+ * written to the TSTOP bit in the AGTCRn register, set to
|
|
|
+ * FFFFH */
|
|
|
+ } AGTCMA_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t AGTCMB; /*!< (@ 0x00000008) AGT Compare Match B Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is
|
|
|
+ * written to the TSTOP bit in the AGTCR register, set to
|
|
|
+ * FFFFH */
|
|
|
+ } AGTCMB_b;
|
|
|
+ };
|
|
|
+ __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL */
|
|
|
+} R_AGTX0_AGT32_Type; /*!< Size = 20 (0x14) */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief R_OFS_DATAFLASH_CFGDLOCK_CFGD [CFGD] (Configuration Data [0..1] Lock Bits)
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t CFGD_L; /*!< (@ 0x00000000) Configuration Data Lock Bits Lower Word */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t CDLK0 : 1; /*!< [0..0] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK1 : 1; /*!< [1..1] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK2 : 1; /*!< [2..2] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK3 : 1; /*!< [3..3] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK4 : 1; /*!< [4..4] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK5 : 1; /*!< [5..5] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK6 : 1; /*!< [6..6] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK7 : 1; /*!< [7..7] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK8 : 1; /*!< [8..8] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK9 : 1; /*!< [9..9] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK10 : 1; /*!< [10..10] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK11 : 1; /*!< [11..11] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK12 : 1; /*!< [12..12] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK13 : 1; /*!< [13..13] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK14 : 1; /*!< [14..14] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK15 : 1; /*!< [15..15] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK16 : 1; /*!< [16..16] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK17 : 1; /*!< [17..17] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK18 : 1; /*!< [18..18] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK19 : 1; /*!< [19..19] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK20 : 1; /*!< [20..20] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK21 : 1; /*!< [21..21] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK22 : 1; /*!< [22..22] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK23 : 1; /*!< [23..23] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK24 : 1; /*!< [24..24] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK25 : 1; /*!< [25..25] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK26 : 1; /*!< [26..26] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK27 : 1; /*!< [27..27] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK28 : 1; /*!< [28..28] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK29 : 1; /*!< [29..29] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK30 : 1; /*!< [30..30] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK31 : 1; /*!< [31..31] Configuration Data Lock Bit */
|
|
|
+ } CFGD_L_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t CFGD_H; /*!< (@ 0x00000004) Configuration Data Lock Bits Higher Word */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t CDLK32 : 1; /*!< [0..0] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK33 : 1; /*!< [1..1] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK34 : 1; /*!< [2..2] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK35 : 1; /*!< [3..3] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK36 : 1; /*!< [4..4] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK37 : 1; /*!< [5..5] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK38 : 1; /*!< [6..6] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK39 : 1; /*!< [7..7] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK40 : 1; /*!< [8..8] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK41 : 1; /*!< [9..9] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK42 : 1; /*!< [10..10] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK43 : 1; /*!< [11..11] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK44 : 1; /*!< [12..12] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK45 : 1; /*!< [13..13] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK46 : 1; /*!< [14..14] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK47 : 1; /*!< [15..15] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK48 : 1; /*!< [16..16] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK49 : 1; /*!< [17..17] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK50 : 1; /*!< [18..18] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK51 : 1; /*!< [19..19] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK52 : 1; /*!< [20..20] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK53 : 1; /*!< [21..21] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK54 : 1; /*!< [22..22] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK55 : 1; /*!< [23..23] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK56 : 1; /*!< [24..24] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK57 : 1; /*!< [25..25] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK58 : 1; /*!< [26..26] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK59 : 1; /*!< [27..27] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK60 : 1; /*!< [28..28] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK61 : 1; /*!< [29..29] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK62 : 1; /*!< [30..30] Configuration Data Lock Bit */
|
|
|
+ __IM uint32_t CDLK63 : 1; /*!< [31..31] Configuration Data Lock Bit */
|
|
|
+ } CFGD_H_b;
|
|
|
+ };
|
|
|
+} R_OFS_DATAFLASH_CFGDLOCK_CFGD_Type; /*!< Size = 8 (0x8) */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief R_OFS_DATAFLASH_CFGDLOCK [CFGDLOCK] (Configuration Data Lock Bits)
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IOM R_OFS_DATAFLASH_CFGDLOCK_CFGD_Type CFGD0; /*!< (@ 0x00000000) Configuration Data 0 Lock Bits */
|
|
|
+ __IOM R_OFS_DATAFLASH_CFGDLOCK_CFGD_Type CFGD1; /*!< (@ 0x00000008) Configuration Data 1 Lock Bits */
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint16_t CFGD2; /*!< (@ 0x00000010) Configuration Data 2 Lock Bit */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t CDLK0 : 1; /*!< [0..0] Configuration Data Lock Bit */
|
|
|
+ __IM uint16_t CDLK1 : 1; /*!< [1..1] Configuration Data Lock Bit */
|
|
|
+ __IM uint16_t CDLK2 : 1; /*!< [2..2] Configuration Data Lock Bit */
|
|
|
+ __IM uint16_t CDLK3 : 1; /*!< [3..3] Configuration Data Lock Bit */
|
|
|
+ __IM uint16_t CDLK4 : 1; /*!< [4..4] Configuration Data Lock Bit */
|
|
|
+ __IM uint16_t CDLK5 : 1; /*!< [5..5] Configuration Data Lock Bit */
|
|
|
+ __IM uint16_t CDLK6 : 1; /*!< [6..6] Configuration Data Lock Bit */
|
|
|
+ __IM uint16_t CDLK7 : 1; /*!< [7..7] Configuration Data Lock Bit */
|
|
|
+ __IM uint16_t CDLK8 : 1; /*!< [8..8] Configuration Data Lock Bit */
|
|
|
+ __IM uint16_t CDLK9 : 1; /*!< [9..9] Configuration Data Lock Bit */
|
|
|
+ __IM uint16_t CDLK10 : 1; /*!< [10..10] Configuration Data Lock Bit */
|
|
|
+ __IM uint16_t CDLK11 : 1; /*!< [11..11] Configuration Data Lock Bit */
|
|
|
+ __IM uint16_t CDLK12 : 1; /*!< [12..12] Configuration Data Lock Bit */
|
|
|
+ __IM uint16_t CDLK13 : 1; /*!< [13..13] Configuration Data Lock Bit */
|
|
|
+ __IM uint16_t CDLK14 : 1; /*!< [14..14] Configuration Data Lock Bit */
|
|
|
+ __IM uint16_t CDLK15 : 1; /*!< [15..15] Configuration Data Lock Bit */
|
|
|
+ } CFGD2_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED;
|
|
|
+} R_OFS_DATAFLASH_CFGDLOCK_Type; /*!< Size = 20 (0x14) */
|
|
|
+
|
|
|
+/** @} */ /* End of group Device_Peripheral_clusters */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ Device Specific Peripheral Section ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/** @addtogroup Device_Peripheral_peripherals
|
|
|
+ * @{
|
|
|
+ */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_ACMPHS0 ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief High-Speed Analog Comparator (R_ACMPHS0)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x40236000) R_ACMPHS0 Structure */
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t CMPCTL; /*!< (@ 0x00000000) Comparator Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t CINV : 1; /*!< [0..0] Comparator output polarity selection */
|
|
|
+ __IOM uint8_t COE : 1; /*!< [1..1] Comparator output enable */
|
|
|
+ __IOM uint8_t CSTEN : 1; /*!< [2..2] Interrupt Select */
|
|
|
+ __IOM uint8_t CEG : 2; /*!< [4..3] Selection of valid edge (Edge selector) */
|
|
|
+ __IOM uint8_t CDFS : 2; /*!< [6..5] Noise filter selection */
|
|
|
+ __IOM uint8_t HCMPON : 1; /*!< [7..7] Comparator operation control */
|
|
|
+ } CMPCTL_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED[3];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t CMPSEL0; /*!< (@ 0x00000004) Comparator Input Select Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t CMPSEL : 4; /*!< [3..0] Comparator Input Selection */
|
|
|
+ uint8_t : 4;
|
|
|
+ } CMPSEL0_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED1[3];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t CMPSEL1; /*!< (@ 0x00000008) Comparator Reference Voltage Select Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t CRVS : 6; /*!< [5..0] Reference Voltage Selection */
|
|
|
+ uint8_t : 2;
|
|
|
+ } CMPSEL1_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED2[3];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint8_t CMPMON; /*!< (@ 0x0000000C) Comparator Output Monitor Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint8_t CMPMON : 1; /*!< [0..0] Comparator output monitor */
|
|
|
+ uint8_t : 7;
|
|
|
+ } CMPMON_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED3[3];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t CPIOC; /*!< (@ 0x00000010) Comparator Output Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t CPOE : 1; /*!< [0..0] Comparator output selection */
|
|
|
+ uint8_t : 6;
|
|
|
+ __IOM uint8_t VREFEN : 1; /*!< [7..7] Internal Vref enable */
|
|
|
+ } CPIOC_b;
|
|
|
+ };
|
|
|
+} R_ACMPHS0_Type; /*!< Size = 17 (0x11) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_ADC0 ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief A/D Converter (R_ADC0)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x40332000) R_ADC0 Structure */
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog
|
|
|
+ * input channel for double triggered operation. The setting
|
|
|
+ * is only effective while double trigger mode is selected. */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */
|
|
|
+ __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */
|
|
|
+ __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */
|
|
|
+ __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */
|
|
|
+ __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */
|
|
|
+ __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */
|
|
|
+ __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */
|
|
|
+ } ADCSR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes
|
|
|
+ * '1' while scanning. */
|
|
|
+ uint8_t : 6;
|
|
|
+ __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */
|
|
|
+ } ADREF_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */
|
|
|
+ uint8_t : 7;
|
|
|
+ } ADEXREF_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */
|
|
|
+ __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */
|
|
|
+ __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */
|
|
|
+ __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */
|
|
|
+ __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */
|
|
|
+ __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */
|
|
|
+ __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */
|
|
|
+ __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */
|
|
|
+ __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */
|
|
|
+ __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */
|
|
|
+ __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */
|
|
|
+ __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */
|
|
|
+ __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */
|
|
|
+ __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */
|
|
|
+ __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */
|
|
|
+ __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */
|
|
|
+ } ADANSA_b[2];
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel
|
|
|
+ * Select Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */
|
|
|
+ __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */
|
|
|
+ __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */
|
|
|
+ __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */
|
|
|
+ __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */
|
|
|
+ __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */
|
|
|
+ __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */
|
|
|
+ __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */
|
|
|
+ __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */
|
|
|
+ __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */
|
|
|
+ __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */
|
|
|
+ __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */
|
|
|
+ __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */
|
|
|
+ __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */
|
|
|
+ __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */
|
|
|
+ __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */
|
|
|
+ } ADADS_b[2];
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select
|
|
|
+ * Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid
|
|
|
+ * at the only setting of ADC[2:0] bits = 001b or 011b. When
|
|
|
+ * average mode is selected by setting the ADADC.AVEE bit
|
|
|
+ * to 1, do not set the addition count to three times (ADADC.ADC[2:0]
|
|
|
+ * = 010b) */
|
|
|
+ uint8_t : 4;
|
|
|
+ __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected
|
|
|
+ * by setting the ADADC.AVEE bit to 0, set the addition count
|
|
|
+ * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion
|
|
|
+ * can only be used with 12-bit accuracy selected. NOTE: AVEE
|
|
|
+ * bit is valid at the only setting of ADC[2:0] bits = 001b
|
|
|
+ * or 011b. When average mode is selected by setting the ADADC.AVEE
|
|
|
+ * bit to 1, do not set the addition count to three times
|
|
|
+ * (ADADC.ADC[2:0] = 010b) */
|
|
|
+ } ADADC_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */
|
|
|
+ __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */
|
|
|
+ __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */
|
|
|
+ __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */
|
|
|
+ __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */
|
|
|
+ } ADCER_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect
|
|
|
+ * the A/D conversion start trigger for group B in group scan
|
|
|
+ * mode. */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion
|
|
|
+ * start trigger in single scan mode and continuous mode.
|
|
|
+ * In group scan mode, the A/D conversion start trigger for
|
|
|
+ * group A is selected. */
|
|
|
+ uint16_t : 2;
|
|
|
+ } ADSTRGR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average
|
|
|
+ * Mode Select */
|
|
|
+ __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average
|
|
|
+ * Mode Select */
|
|
|
+ uint16_t : 6;
|
|
|
+ __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */
|
|
|
+ __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */
|
|
|
+ __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for
|
|
|
+ * Group B in group scan mode. */
|
|
|
+ __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for
|
|
|
+ * Group B in group scan mode. */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */
|
|
|
+ __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */
|
|
|
+ } ADEXICR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */
|
|
|
+ __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */
|
|
|
+ __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */
|
|
|
+ __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */
|
|
|
+ __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */
|
|
|
+ __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */
|
|
|
+ __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */
|
|
|
+ __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */
|
|
|
+ __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */
|
|
|
+ __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */
|
|
|
+ __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */
|
|
|
+ __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */
|
|
|
+ __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */
|
|
|
+ __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */
|
|
|
+ __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */
|
|
|
+ __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */
|
|
|
+ } ADANSB_b[2];
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the
|
|
|
+ * result of A/D conversion in response to the second trigger
|
|
|
+ * in double trigger mode. */
|
|
|
+ } ADDBLDR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the
|
|
|
+ * A/D conversion result of temperature sensor output. */
|
|
|
+ } ADTSDR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the
|
|
|
+ * A/D result of internal reference voltage. */
|
|
|
+ } ADOCDR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for
|
|
|
+ * data determine ADCER.ADRFMT and ADCER.ADPRC. */
|
|
|
+ __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */
|
|
|
+ } ADRD_RIGHT_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */
|
|
|
+ __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for
|
|
|
+ * data determine ADCER.ADRFMT and ADCER.ADPRC. */
|
|
|
+ } ADRD_LEFT_b;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint16_t ADDR[29]; /*!< (@ 0x00000020) A/D Data Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for
|
|
|
+ * storing the result of A/D conversion. */
|
|
|
+ } ADDR_b[29];
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED1;
|
|
|
+ __IM uint32_t RESERVED2;
|
|
|
+ __IM uint16_t RESERVED3;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */
|
|
|
+ } ADAMPOFF_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */
|
|
|
+ __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */
|
|
|
+ uint8_t : 6;
|
|
|
+ } ADTSTPR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t WRION : 5; /*!< [4..0] WRION */
|
|
|
+ uint16_t : 3;
|
|
|
+ __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */
|
|
|
+ } ADDDACER_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time
|
|
|
+ * Setting Set the sampling time (4 to 255 states) */
|
|
|
+ __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */
|
|
|
+ __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */
|
|
|
+ __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */
|
|
|
+ uint16_t : 5;
|
|
|
+ } ADSHCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit
|
|
|
+ * only for channel. */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit
|
|
|
+ * for adjustment to hardening of process. */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator
|
|
|
+ * power save bit for A/D hard macro to hardening of process. */
|
|
|
+ __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim
|
|
|
+ * bit for A/D hard macro to hardening of process. */
|
|
|
+ __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim
|
|
|
+ * bit for A/D hard macro to hardening of process. */
|
|
|
+ } ADEXTSTR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */
|
|
|
+ __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit
|
|
|
+ * amplifier test.Refreshing the pressure switch that opens
|
|
|
+ * for the DAC output voltage charge period when the amplifier
|
|
|
+ * of the S&H circuit is tested only for the channel is set. */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control
|
|
|
+ * bit. */
|
|
|
+ __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control
|
|
|
+ * bit */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog
|
|
|
+ * module Details are described to the bit explanation. */
|
|
|
+ __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the
|
|
|
+ * bit explanation. */
|
|
|
+ } ADTSTRA_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It
|
|
|
+ * corresponds to ADVAL 14:0 input of A/D analog module. */
|
|
|
+ uint16_t : 1;
|
|
|
+ } ADTSTRB_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D
|
|
|
+ * analog module. */
|
|
|
+ uint16_t : 4;
|
|
|
+ __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */
|
|
|
+ uint16_t : 3;
|
|
|
+ } ADTSTRC_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It
|
|
|
+ * corresponds to ADVAL 16 input of A/D analog module. */
|
|
|
+ uint16_t : 15;
|
|
|
+ } ADTSTRD_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */
|
|
|
+ __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */
|
|
|
+ __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */
|
|
|
+ __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */
|
|
|
+ __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */
|
|
|
+ __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */
|
|
|
+ uint16_t : 10;
|
|
|
+ } ADSWTSTR0_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */
|
|
|
+ __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */
|
|
|
+ __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */
|
|
|
+ __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */
|
|
|
+ __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */
|
|
|
+ __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */
|
|
|
+ uint16_t : 10;
|
|
|
+ } ADSWTSTR1_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit
|
|
|
+ * (ANEX0 switch) */
|
|
|
+ __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit
|
|
|
+ * (ANEX1 switch). */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */
|
|
|
+ __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */
|
|
|
+ __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */
|
|
|
+ __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */
|
|
|
+ __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */
|
|
|
+ __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */
|
|
|
+ __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */
|
|
|
+ uint16_t : 3;
|
|
|
+ } ADSWTSTR2_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED4;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */
|
|
|
+ __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */
|
|
|
+ uint8_t : 3;
|
|
|
+ } ADDISCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing
|
|
|
+ * the pressure switch in A/D analog module is set. */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */
|
|
|
+ uint8_t : 1;
|
|
|
+ } ADSWCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode
|
|
|
+ * Select */
|
|
|
+ uint8_t : 7;
|
|
|
+ } ADSHMSR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */
|
|
|
+ uint8_t : 6;
|
|
|
+ } ADICR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */
|
|
|
+ uint8_t : 6;
|
|
|
+ } ADACSR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED5;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS
|
|
|
+ * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be
|
|
|
+ * set to 01b (group scan mode). If the bits are set to any
|
|
|
+ * other values, proper operation is not guaranteed. */
|
|
|
+ __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved
|
|
|
+ * when PGS = 0.) */
|
|
|
+ uint16_t : 6;
|
|
|
+ __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */
|
|
|
+ uint16_t : 6;
|
|
|
+ __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when
|
|
|
+ * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit
|
|
|
+ * has been set to 1, single scan is performed continuously
|
|
|
+ * for group B regardless of the setting of the GBRSCN bit. */
|
|
|
+ } ADGSPCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group
|
|
|
+ * Scan) */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */
|
|
|
+ __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */
|
|
|
+ } ADGSCS_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing
|
|
|
+ * the result of A/D conversion in response to the respective
|
|
|
+ * triggers during extended operation in double trigger mode. */
|
|
|
+ } ADDBLDRA_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing
|
|
|
+ * the result of A/D conversion in response to the respective
|
|
|
+ * triggers during extended operation in double trigger mode. */
|
|
|
+ } ADDBLDRB_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint8_t : 7;
|
|
|
+ __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */
|
|
|
+ } ADSER_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED6;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage
|
|
|
+ * Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */
|
|
|
+ uint8_t : 2;
|
|
|
+ __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */
|
|
|
+ uint8_t : 2;
|
|
|
+ __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */
|
|
|
+ } ADHVREFCNT_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED7;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor
|
|
|
+ * Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination
|
|
|
+ * result.This bit is valid when both window A operation and
|
|
|
+ * window B operation are enabled. */
|
|
|
+ uint8_t : 3;
|
|
|
+ __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */
|
|
|
+ __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */
|
|
|
+ uint8_t : 2;
|
|
|
+ } ADWINMON_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED8;
|
|
|
+ __IM uint16_t RESERVED9;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits
|
|
|
+ * are valid when both window A and window B are enabled (CMPAE
|
|
|
+ * = 1 and CMPBE = 1). */
|
|
|
+ uint16_t : 7;
|
|
|
+ __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */
|
|
|
+ __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */
|
|
|
+ __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */
|
|
|
+ } ADCMPCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input
|
|
|
+ * Select Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */
|
|
|
+ __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */
|
|
|
+ uint8_t : 6;
|
|
|
+ } ADCMPANSER_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input
|
|
|
+ * Comparison Condition Setting Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison
|
|
|
+ * Condition Select */
|
|
|
+ __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition
|
|
|
+ * Select */
|
|
|
+ uint8_t : 6;
|
|
|
+ } ADCMPLER_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select
|
|
|
+ * Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */
|
|
|
+ __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */
|
|
|
+ __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */
|
|
|
+ __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */
|
|
|
+ __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */
|
|
|
+ __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */
|
|
|
+ __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */
|
|
|
+ __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */
|
|
|
+ __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */
|
|
|
+ __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */
|
|
|
+ __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */
|
|
|
+ __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */
|
|
|
+ __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */
|
|
|
+ __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */
|
|
|
+ __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */
|
|
|
+ __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */
|
|
|
+ } ADCMPANSR_b[2];
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition
|
|
|
+ * Setting Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */
|
|
|
+ __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */
|
|
|
+ __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */
|
|
|
+ __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */
|
|
|
+ __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */
|
|
|
+ __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */
|
|
|
+ __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */
|
|
|
+ __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */
|
|
|
+ __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */
|
|
|
+ __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */
|
|
|
+ __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */
|
|
|
+ __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */
|
|
|
+ __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */
|
|
|
+ __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */
|
|
|
+ __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */
|
|
|
+ __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */
|
|
|
+ } ADCMPLR_b[2];
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level
|
|
|
+ * Setting Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the
|
|
|
+ * compare window A function is used. ADCMPDR0 sets the lower-side
|
|
|
+ * level of window A. */
|
|
|
+ } ADCMPDR0_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level
|
|
|
+ * Setting Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the
|
|
|
+ * compare window A function is used. ADCMPDR1 sets the upper-side
|
|
|
+ * level of window A.. */
|
|
|
+ } ADCMPDR1_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status
|
|
|
+ * Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */
|
|
|
+ __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */
|
|
|
+ __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */
|
|
|
+ __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */
|
|
|
+ __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */
|
|
|
+ __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */
|
|
|
+ __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */
|
|
|
+ __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */
|
|
|
+ __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */
|
|
|
+ __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */
|
|
|
+ __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */
|
|
|
+ __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */
|
|
|
+ __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */
|
|
|
+ __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */
|
|
|
+ __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */
|
|
|
+ __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */
|
|
|
+ } ADCMPSR_b[2];
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input
|
|
|
+ * Channel Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag
|
|
|
+ * When window A operation is enabled (ADCMPCR.CMPAE = 1b),
|
|
|
+ * this bit indicates the temperature sensor output comparison
|
|
|
+ * result. When window A operation is disabled (ADCMPCR.CMPAE
|
|
|
+ * = 0b), comparison conditions for CMPSTTSA are not met any
|
|
|
+ * time. */
|
|
|
+ __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag
|
|
|
+ * When window A operation is enabled (ADCMPCR.CMPAE = 1b),
|
|
|
+ * this bit indicates the temperature sensor output comparison
|
|
|
+ * result. When window A operation is disabled (ADCMPCR.CMPAE
|
|
|
+ * = 0b), comparison conditions for CMPSTTSA are not met any
|
|
|
+ * time. */
|
|
|
+ uint8_t : 6;
|
|
|
+ } ADCMPSER_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED10;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection
|
|
|
+ * Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that
|
|
|
+ * compares it on the condition of compare window B is selected. */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */
|
|
|
+ } ADCMPBNSR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED11;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level
|
|
|
+ * Setting Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is
|
|
|
+ * used to set the lower level of the window B. */
|
|
|
+ } ADWINLLB_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level
|
|
|
+ * Setting Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is
|
|
|
+ * used to set the higher level of the window B. */
|
|
|
+ } ADWINULB_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows
|
|
|
+ * the comparative result of CH (AN000-AN027, temperature
|
|
|
+ * sensor, and internal reference voltage) made the object
|
|
|
+ * of window B relation condition. */
|
|
|
+ uint8_t : 7;
|
|
|
+ } ADCMPBSR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED12;
|
|
|
+ __IM uint16_t RESERVED13;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
|
|
|
+ * registers that sequentially store all A/D converted values.
|
|
|
+ * The automatic clear function is not applied to these registers. */
|
|
|
+ } ADBUF0_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
|
|
|
+ * registers that sequentially store all A/D converted values.
|
|
|
+ * The automatic clear function is not applied to these registers. */
|
|
|
+ } ADBUF1_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
|
|
|
+ * registers that sequentially store all A/D converted values.
|
|
|
+ * The automatic clear function is not applied to these registers. */
|
|
|
+ } ADBUF2_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
|
|
|
+ * registers that sequentially store all A/D converted values.
|
|
|
+ * The automatic clear function is not applied to these registers. */
|
|
|
+ } ADBUF3_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
|
|
|
+ * registers that sequentially store all A/D converted values.
|
|
|
+ * The automatic clear function is not applied to these registers. */
|
|
|
+ } ADBUF4_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
|
|
|
+ * registers that sequentially store all A/D converted values.
|
|
|
+ * The automatic clear function is not applied to these registers. */
|
|
|
+ } ADBUF5_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
|
|
|
+ * registers that sequentially store all A/D converted values.
|
|
|
+ * The automatic clear function is not applied to these registers. */
|
|
|
+ } ADBUF6_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
|
|
|
+ * registers that sequentially store all A/D converted values.
|
|
|
+ * The automatic clear function is not applied to these registers. */
|
|
|
+ } ADBUF7_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
|
|
|
+ * registers that sequentially store all A/D converted values.
|
|
|
+ * The automatic clear function is not applied to these registers. */
|
|
|
+ } ADBUF8_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
|
|
|
+ * registers that sequentially store all A/D converted values.
|
|
|
+ * The automatic clear function is not applied to these registers. */
|
|
|
+ } ADBUF9_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
|
|
|
+ * registers that sequentially store all A/D converted values.
|
|
|
+ * The automatic clear function is not applied to these registers. */
|
|
|
+ } ADBUF10_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
|
|
|
+ * registers that sequentially store all A/D converted values.
|
|
|
+ * The automatic clear function is not applied to these registers. */
|
|
|
+ } ADBUF11_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
|
|
|
+ * registers that sequentially store all A/D converted values.
|
|
|
+ * The automatic clear function is not applied to these registers. */
|
|
|
+ } ADBUF12_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
|
|
|
+ * registers that sequentially store all A/D converted values.
|
|
|
+ * The automatic clear function is not applied to these registers. */
|
|
|
+ } ADBUF13_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
|
|
|
+ * registers that sequentially store all A/D converted values.
|
|
|
+ * The automatic clear function is not applied to these registers. */
|
|
|
+ } ADBUF14_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
|
|
|
+ * registers that sequentially store all A/D converted values.
|
|
|
+ * The automatic clear function is not applied to these registers. */
|
|
|
+ } ADBUF15_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */
|
|
|
+ uint8_t : 7;
|
|
|
+ } ADBUFEN_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED14;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of
|
|
|
+ * data buffer to which the next A/D converted data is transferred. */
|
|
|
+ __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */
|
|
|
+ uint8_t : 3;
|
|
|
+ } ADBUFPTR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED15;
|
|
|
+ __IM uint32_t RESERVED16[2];
|
|
|
+ __IM uint8_t RESERVED17;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */
|
|
|
+ } ADSSTRL_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */
|
|
|
+ } ADSSTRT_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */
|
|
|
+ } ADSSTRO_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */
|
|
|
+ } ADSSTR_b[16];
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */
|
|
|
+ __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */
|
|
|
+ __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */
|
|
|
+ __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */
|
|
|
+ uint16_t : 12;
|
|
|
+ } ADANIM_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint8_t : 6;
|
|
|
+ __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */
|
|
|
+ __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */
|
|
|
+ } ADCALEXE_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED18;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control
|
|
|
+ * Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */
|
|
|
+ __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */
|
|
|
+ __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */
|
|
|
+ __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */
|
|
|
+ uint8_t : 2;
|
|
|
+ __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */
|
|
|
+ } VREFAMPCNT_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED19;
|
|
|
+ __IM uint16_t RESERVED20;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */
|
|
|
+ } ADRD_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */
|
|
|
+ uint8_t : 6;
|
|
|
+ } ADRST_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED21;
|
|
|
+ __IM uint32_t RESERVED22[41];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */
|
|
|
+ __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */
|
|
|
+ __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */
|
|
|
+ __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */
|
|
|
+ __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */
|
|
|
+ __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */
|
|
|
+ __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */
|
|
|
+ __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */
|
|
|
+ __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */
|
|
|
+ __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */
|
|
|
+ __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */
|
|
|
+ __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */
|
|
|
+ __IOM uint16_t P003SEL0 : 1; /*!< [12..12] A through amplifier is enable for PGA P003 */
|
|
|
+ __IOM uint16_t P003SEL1 : 1; /*!< [13..13] The amplifier passing is enable for PGA P003 */
|
|
|
+ __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003 */
|
|
|
+ __IOM uint16_t P003GEN : 1; /*!< [15..15] PGA P003 gain setting and enable bit */
|
|
|
+ } ADPGACR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting
|
|
|
+ * Register 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN=
|
|
|
+ * b) when the shingle end is input and each PGA P000 is set.
|
|
|
+ * When the differential motion is input, (ADPGSDCR0.P000GEN=1b)
|
|
|
+ * sets the gain magnification when the differential motion
|
|
|
+ * is input by the combination with ADPGSDCR0.P000DG 1:0. */
|
|
|
+ __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN=
|
|
|
+ * b) when the shingle end is input and each PGA P001 is set.
|
|
|
+ * When the differential motion is input, (ADPGSDCR0.P001GEN=1b)
|
|
|
+ * sets the gain magnification when the differential motion
|
|
|
+ * is input by the combination with ADPGSDCR0.P001DG 1:0. */
|
|
|
+ __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of
|
|
|
+ * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and
|
|
|
+ * each PGA P002 is set. When the differential motion is input,
|
|
|
+ * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when
|
|
|
+ * the differential motion is input by the combination with
|
|
|
+ * ADPGSDCR0.P002DG 1:0. */
|
|
|
+ __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of
|
|
|
+ * (ADPGSDCR0.P003GEN=0b) when the shingle end is input and
|
|
|
+ * each PGA P003 is set. When the differential motion is input,
|
|
|
+ * (ADPGSDCR0.P003GEN=1b) sets the gain magnification when
|
|
|
+ * the differential motion is input by the combination with
|
|
|
+ * ADPGSDCR0.P003DG 1:0. */
|
|
|
+ } ADPGAGS0_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED23[3];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential
|
|
|
+ * Input Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these
|
|
|
+ * bits are used, set {P000DEN, P000GEN} to 11b. */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */
|
|
|
+ __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these
|
|
|
+ * bits are used, set {P001DEN, P001GEN} to 11b. */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */
|
|
|
+ __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these
|
|
|
+ * bits are used, set {P002DEN, P002GEN} to 11b. */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */
|
|
|
+ __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these
|
|
|
+ * bits are used, set {P003DEN, P003GEN} to 11b. */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable */
|
|
|
+ } ADPGADCR0_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED24;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ADPGADBS0; /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential
|
|
|
+ * Input Bias Select Register 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t P0BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage
|
|
|
+ * SelectNOTE: This bit selects the input bias voltage value
|
|
|
+ * when differential inputs are used. */
|
|
|
+ uint8_t : 7;
|
|
|
+ } ADPGADBS0_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ADPGADBS1; /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential
|
|
|
+ * Input Bias Select Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t P3BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE:
|
|
|
+ * This bit selects the input bias voltage value when differential
|
|
|
+ * inputs are used. */
|
|
|
+ uint8_t : 7;
|
|
|
+ } ADPGADBS1_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED25;
|
|
|
+ __IM uint32_t RESERVED26[10];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t ADREFMON; /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable */
|
|
|
+ uint32_t : 13;
|
|
|
+ __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit. */
|
|
|
+ uint32_t : 12;
|
|
|
+ } ADREFMON_b;
|
|
|
+ };
|
|
|
+} R_ADC0_Type; /*!< Size = 484 (0x1e4) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_PSCU ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Peripheral Security Control Unit (R_PSCU)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x40204000) R_PSCU Structure */
|
|
|
+{
|
|
|
+ __IM uint32_t RESERVED;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t PSARB4 : 1; /*!< [4..4] I3C Bus Interface 2 Security Attribution */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t PSARB8 : 1; /*!< [8..8] I2C Bus Interface 1 Security Attribution */
|
|
|
+ __IOM uint32_t PSARB9 : 1; /*!< [9..9] I2C Bus Interface 0 Security Attribution */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t PSARB11 : 1; /*!< [11..11] Universal Serial Bus 2.0 FS Interface 0 Security Attribution */
|
|
|
+ __IOM uint32_t PSARB12 : 1; /*!< [12..12] Universal Serial Bus 2.0 HS Interface 0 Security Attribution */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t PSARB15 : 1; /*!< [15..15] ETHER0/EDMAC0 Controller Security Attribution */
|
|
|
+ __IOM uint32_t PSARB16 : 1; /*!< [16..16] Octa Memory Controller Security Attribution */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t PSARB18 : 1; /*!< [18..18] Serial Peripheral Interface 1 Security Attribution */
|
|
|
+ __IOM uint32_t PSARB19 : 1; /*!< [19..19] Serial Peripheral Interface 0 Security Attribution */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t PSARB22 : 1; /*!< [22..22] Serial Communication Interface 9 Security Attribution */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t PSARB27 : 1; /*!< [27..27] Serial Communication Interface 4 Security Attribution */
|
|
|
+ __IOM uint32_t PSARB28 : 1; /*!< [28..28] Serial Communication Interface 3 Security Attribution */
|
|
|
+ __IOM uint32_t PSARB29 : 1; /*!< [29..29] Serial Communication Interface 2 Security Attribution */
|
|
|
+ __IOM uint32_t PSARB30 : 1; /*!< [30..30] Serial Communication Interface 1 Security Attribution */
|
|
|
+ __IOM uint32_t PSARB31 : 1; /*!< [31..31] Serial Communication Interface 0 Security Attribution */
|
|
|
+ } PSARB_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t PSARC; /*!< (@ 0x00000008) Peripheral Security Attribution Register C */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t PSARC0 : 1; /*!< [0..0] Clock Frequency Accuracy Measurement Circuit Security
|
|
|
+ * Attribution */
|
|
|
+ __IOM uint32_t PSARC1 : 1; /*!< [1..1] Cyclic Redundancy Check Calculator Security Attribution */
|
|
|
+ uint32_t : 5;
|
|
|
+ __IOM uint32_t PSARC7 : 1; /*!< [7..7] Serial Sound Interface Enhanced (channel 1) Security
|
|
|
+ * Attribution */
|
|
|
+ __IOM uint32_t PSARC8 : 1; /*!< [8..8] Serial Sound Interface Enhanced (channel 0) Security
|
|
|
+ * Attribution */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t PSARC11 : 1; /*!< [11..11] Secure Digital Host IF 1 Security Attribution */
|
|
|
+ __IOM uint32_t PSARC12 : 1; /*!< [12..12] Secure Digital Host IF 0 Security Attribution */
|
|
|
+ __IOM uint32_t PSARC13 : 1; /*!< [13..13] Data Operation Circuit Security Attribution */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t PSARC15 : 1; /*!< [15..15] Graph-ic(GLCDC,MIPI,DRW,JPEG) Security Attribution */
|
|
|
+ __IOM uint32_t PSARC16 : 1; /*!< [16..16] CEU Security Attribution */
|
|
|
+ uint32_t : 9;
|
|
|
+ __IOM uint32_t PSARC26 : 1; /*!< [26..26] Controller Area Network with Flexible Data-Rate 1 Security
|
|
|
+ * Attribution */
|
|
|
+ __IOM uint32_t PSARC27 : 1; /*!< [27..27] Controller Area Network with Flexible Data-Rate 0 Security
|
|
|
+ * Attribution */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t PSARC31 : 1; /*!< [31..31] SHIP Security Attribution */
|
|
|
+ } PSARC_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t PSARD; /*!< (@ 0x0000000C) Peripheral Security Attribution Register D */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t PSARD4 : 1; /*!< [4..4] Asynchronous General Purpose Timer 1 Security Attribution */
|
|
|
+ __IOM uint32_t PSARD5 : 1; /*!< [5..5] Asynchronous General Purpose Timer 0 Security Attribution */
|
|
|
+ uint32_t : 5;
|
|
|
+ __IOM uint32_t PSARD11 : 1; /*!< [11..11] Port Output Enable for GPT Group 3 Security Attribution */
|
|
|
+ __IOM uint32_t PSARD12 : 1; /*!< [12..12] Port Output Enable for GPT Group 2 Security Attribution */
|
|
|
+ __IOM uint32_t PSARD13 : 1; /*!< [13..13] Port Output Enable for GPT Group 1 Security Attribution */
|
|
|
+ __IOM uint32_t PSARD14 : 1; /*!< [14..14] Port Output Enable for GPT Group 0 Security Attribution */
|
|
|
+ __IOM uint32_t PSARD15 : 1; /*!< [15..15] 12-Bit A/D 1 Converter Security Attribution */
|
|
|
+ __IOM uint32_t PSARD16 : 1; /*!< [16..16] 12-Bit A/D 0 Converter Security Attribution */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t PSARD20 : 1; /*!< [20..20] 12-Bit D/A Converter Security Attribution */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t PSARD22 : 1; /*!< [22..22] Temperature Sensor Security Attribution */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t PSARD27 : 1; /*!< [27..27] High speed analog Comparator 1 Security Attribution */
|
|
|
+ __IOM uint32_t PSARD28 : 1; /*!< [28..28] High speed analog Comparator 0 Security Attribution */
|
|
|
+ uint32_t : 3;
|
|
|
+ } PSARD_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t PSARE; /*!< (@ 0x00000010) Peripheral Security Attribution Register E */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t PSARE1 : 1; /*!< [1..1] WDT0 Security Attribution */
|
|
|
+ __IOM uint32_t PSARE2 : 1; /*!< [2..2] Independent Watchdog Timer Security Attribution */
|
|
|
+ __IOM uint32_t PSARE3 : 1; /*!< [3..3] Real Time Clock Security Attribution */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t PSARE8 : 1; /*!< [8..8] ULPT1 Security Attribution */
|
|
|
+ __IOM uint32_t PSARE9 : 1; /*!< [9..9] ULPT0 Security Attribution */
|
|
|
+ uint32_t : 8;
|
|
|
+ __IOM uint32_t PSARE18 : 1; /*!< [18..18] General PWM Timer channel13 Security Attribution */
|
|
|
+ __IOM uint32_t PSARE19 : 1; /*!< [19..19] General PWM Timer channel12 Security Attribution */
|
|
|
+ __IOM uint32_t PSARE20 : 1; /*!< [20..20] General PWM Timer channel11 Security Attribution */
|
|
|
+ __IOM uint32_t PSARE21 : 1; /*!< [21..21] General PWM Timer channel10 Security Attribution */
|
|
|
+ __IOM uint32_t PSARE22 : 1; /*!< [22..22] General PWM Timer channel9 Security Attribution */
|
|
|
+ __IOM uint32_t PSARE23 : 1; /*!< [23..23] General PWM Timer channel8 Security Attribution */
|
|
|
+ __IOM uint32_t PSARE24 : 1; /*!< [24..24] General PWM Timer channel7 Security Attribution */
|
|
|
+ __IOM uint32_t PSARE25 : 1; /*!< [25..25] General PWM Timer channel6 Security Attribution */
|
|
|
+ __IOM uint32_t PSARE26 : 1; /*!< [26..26] General PWM Timer channel5 Security Attribution */
|
|
|
+ __IOM uint32_t PSARE27 : 1; /*!< [27..27] General PWM Timer channel4 Security Attribution */
|
|
|
+ __IOM uint32_t PSARE28 : 1; /*!< [28..28] General PWM Timer channel3 Security Attribution */
|
|
|
+ __IOM uint32_t PSARE29 : 1; /*!< [29..29] General PWM Timer channel2 Security Attribution */
|
|
|
+ __IOM uint32_t PSARE30 : 1; /*!< [30..30] General PWM Timer channel1 Security Attribution */
|
|
|
+ __IOM uint32_t PSARE31 : 1; /*!< [31..31] General PWM Timer channel0 Security Attribution */
|
|
|
+ } PSARE_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t MSSAR; /*!< (@ 0x00000014) Module Stop Security Attribution Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t MSSAR0 : 1; /*!< [0..0] SRAM0 Clock Stop Security Attribution */
|
|
|
+ __IOM uint32_t MSSAR1 : 1; /*!< [1..1] SRAM1 Clock Stop Security Attribution */
|
|
|
+ uint32_t : 9;
|
|
|
+ __IOM uint32_t MSSAR11 : 1; /*!< [11..11] CTCM0 Security Attribution */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t MSSAR13 : 1; /*!< [13..13] STCM0 Security Attribution */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t MSSAR15 : 1; /*!< [15..15] Standby RAM Clock Stop Security Attribution */
|
|
|
+ uint32_t : 6;
|
|
|
+ __IOM uint32_t MSSAR22 : 1; /*!< [22..22] DMAC0/DTC0 Clock Stop Security Attribution */
|
|
|
+ uint32_t : 8;
|
|
|
+ __IOM uint32_t MSSAR31 : 1; /*!< [31..31] ELC clock stop Security Attribution */
|
|
|
+ } MSSAR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED1;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t PPARB; /*!< (@ 0x0000001C) Peripheral Privilege Attribution Register B */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t PPARB4 : 1; /*!< [4..4] I3C Bus Interface 2 Privilege Attribution */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t PPARB8 : 1; /*!< [8..8] I2C Bus Interface 1 Privilege Attribution */
|
|
|
+ __IOM uint32_t PPARB9 : 1; /*!< [9..9] I2C Bus Interface 0 Privilege Attribution */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t PPARB11 : 1; /*!< [11..11] Universal Serial Bus 2.0 FS Interface 0 Privilege Attribution */
|
|
|
+ __IOM uint32_t PPARB12 : 1; /*!< [12..12] Universal Serial Bus 2.0 HS Interface 0 Privilege Attribution */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t PPARB15 : 1; /*!< [15..15] ETHER0/EDMAC0 Controller Privilege Attribution */
|
|
|
+ __IOM uint32_t PPARB16 : 1; /*!< [16..16] Octa Memory Controller Privilege Attribution */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t PPARB18 : 1; /*!< [18..18] Serial Peripheral Interface 1 Privilege Attribution */
|
|
|
+ __IOM uint32_t PPARB19 : 1; /*!< [19..19] Serial Peripheral Interface 0 Privilege Attribution */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t PPARB22 : 1; /*!< [22..22] Serial Communication Interface 9 Privilege Attribution */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t PPARB27 : 1; /*!< [27..27] Serial Communication Interface 4 Privilege Attribution */
|
|
|
+ __IOM uint32_t PPARB28 : 1; /*!< [28..28] Serial Communication Interface 3 Privilege Attribution */
|
|
|
+ __IOM uint32_t PPARB29 : 1; /*!< [29..29] Serial Communication Interface 2 Privilege Attribution */
|
|
|
+ __IOM uint32_t PPARB30 : 1; /*!< [30..30] Serial Communication Interface 1 Privilege Attribution */
|
|
|
+ __IOM uint32_t PPARB31 : 1; /*!< [31..31] Serial Communication Interface 0 Privilege Attribution */
|
|
|
+ } PPARB_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t PPARC; /*!< (@ 0x00000020) Peripheral Privilege Attribution Register C */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t PPARC0 : 1; /*!< [0..0] Clock Frequency Accuracy Measurement Circuit Privilege
|
|
|
+ * Attribution */
|
|
|
+ __IOM uint32_t PPARC1 : 1; /*!< [1..1] Cyclic Redundancy Check Calculator Privilege Attribution */
|
|
|
+ uint32_t : 5;
|
|
|
+ __IOM uint32_t PPARC7 : 1; /*!< [7..7] Serial Sound Interface Enhanced (channel 1) Privilege
|
|
|
+ * Attribution */
|
|
|
+ __IOM uint32_t PPARC8 : 1; /*!< [8..8] Serial Sound Interface Enhanced (channel 0) Privilege
|
|
|
+ * Attribution */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t PPARC11 : 1; /*!< [11..11] Privilege Digital Host IF 1 Privilege Attribution */
|
|
|
+ __IOM uint32_t PPARC12 : 1; /*!< [12..12] Privilege Digital Host IF 0 Privilege Attribution */
|
|
|
+ __IOM uint32_t PPARC13 : 1; /*!< [13..13] Data Operation Circuit Privilege Attribution */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t PPARC15 : 1; /*!< [15..15] Graph-ic(GLCDC,MIPI,DRW,JPEG) Privilege Attribution */
|
|
|
+ __IOM uint32_t PPARC16 : 1; /*!< [16..16] CEU Privilege Attribution */
|
|
|
+ uint32_t : 9;
|
|
|
+ __IOM uint32_t PPARC26 : 1; /*!< [26..26] Controller Area Network with Flexible Data-Rate 1 Privilege
|
|
|
+ * Attribution */
|
|
|
+ __IOM uint32_t PPARC27 : 1; /*!< [27..27] Controller Area Network with Flexible Data-Rate 0 Privilege
|
|
|
+ * Attribution */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t PPARC31 : 1; /*!< [31..31] SHIP Privilege Attribution */
|
|
|
+ } PPARC_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t PPARD; /*!< (@ 0x00000024) Peripheral Privilege Attribution Register D */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t PPARD4 : 1; /*!< [4..4] Asynchronous General Purpose Timer 1 Privilege Attribution */
|
|
|
+ __IOM uint32_t PPARD5 : 1; /*!< [5..5] Asynchronous General Purpose Timer 0 Privilege Attribution */
|
|
|
+ uint32_t : 5;
|
|
|
+ __IOM uint32_t PPARD11 : 1; /*!< [11..11] Port Output Enable for GPT Group 3 Privilege Attribution */
|
|
|
+ __IOM uint32_t PPARD12 : 1; /*!< [12..12] Port Output Enable for GPT Group 2 Privilege Attribution */
|
|
|
+ __IOM uint32_t PPARD13 : 1; /*!< [13..13] Port Output Enable for GPT Group 1 Privilege Attribution */
|
|
|
+ __IOM uint32_t PPARD14 : 1; /*!< [14..14] Port Output Enable for GPT Group 0 Privilege Attribution */
|
|
|
+ __IOM uint32_t PPARD15 : 1; /*!< [15..15] 12-Bit A/D 1 Converter Privilege Attribution */
|
|
|
+ __IOM uint32_t PPARD16 : 1; /*!< [16..16] 12-Bit A/D 0 Converter Privilege Attribution */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t PPARD20 : 1; /*!< [20..20] 12-Bit D/A Converter Privilege Attribution */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t PPARD22 : 1; /*!< [22..22] Temperature Sensor Privilege Attribution */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t PPARD27 : 1; /*!< [27..27] High speed analog Comparator 1 Privilege Attribution */
|
|
|
+ __IOM uint32_t PPARD28 : 1; /*!< [28..28] High speed analog Comparator 0 Privilege Attribution */
|
|
|
+ uint32_t : 3;
|
|
|
+ } PPARD_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t PPARE; /*!< (@ 0x00000028) Peripheral Privilege Attribution Register E */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t PPARE1 : 1; /*!< [1..1] Watchdog Timer0 Privilege Attribution */
|
|
|
+ __IOM uint32_t PPARE2 : 1; /*!< [2..2] Independent Watchdog Timer Privilege Attribution */
|
|
|
+ __IOM uint32_t PPARE3 : 1; /*!< [3..3] Real Time Clock Privilege Attribution */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t PPARE8 : 1; /*!< [8..8] ULPT1 Privilege Attribution */
|
|
|
+ __IOM uint32_t PPARE9 : 1; /*!< [9..9] ULPT0 Privilege Attribution */
|
|
|
+ uint32_t : 8;
|
|
|
+ __IOM uint32_t PPARE18 : 1; /*!< [18..18] General PWM Timer channel13 Privilege Attribution */
|
|
|
+ __IOM uint32_t PPARE19 : 1; /*!< [19..19] General PWM Timer channel12 Privilege Attribution */
|
|
|
+ __IOM uint32_t PPARE20 : 1; /*!< [20..20] General PWM Timer channel11 Privilege Attribution */
|
|
|
+ __IOM uint32_t PPARE21 : 1; /*!< [21..21] General PWM Timer channel10 Privilege Attribution */
|
|
|
+ __IOM uint32_t PPARE22 : 1; /*!< [22..22] General PWM Timer channel9 Privilege Attribution */
|
|
|
+ __IOM uint32_t PPARE23 : 1; /*!< [23..23] General PWM Timer channel8 Privilege Attribution */
|
|
|
+ __IOM uint32_t PPARE24 : 1; /*!< [24..24] General PWM Timer channel7 Privilege Attribution */
|
|
|
+ __IOM uint32_t PPARE25 : 1; /*!< [25..25] General PWM Timer channel6 Privilege Attribution */
|
|
|
+ __IOM uint32_t PPARE26 : 1; /*!< [26..26] General PWM Timer channel5 Privilege Attribution */
|
|
|
+ __IOM uint32_t PPARE27 : 1; /*!< [27..27] General PWM Timer channel4 Privilege Attribution */
|
|
|
+ __IOM uint32_t PPARE28 : 1; /*!< [28..28] General PWM Timer channel3 Privilege Attribution */
|
|
|
+ __IOM uint32_t PPARE29 : 1; /*!< [29..29] General PWM Timer channel2 Privilege Attribution */
|
|
|
+ __IOM uint32_t PPARE30 : 1; /*!< [30..30] General PWM Timer channel1 Privilege Attribution */
|
|
|
+ __IOM uint32_t PPARE31 : 1; /*!< [31..31] General PWM Timer channel0 Privilege Attribution */
|
|
|
+ } PPARE_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t MSPAR; /*!< (@ 0x0000002C) Module Stop Privilege Attribution Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 31;
|
|
|
+ __IOM uint32_t MSPAR31 : 1; /*!< [31..31] ELC clock stop Privilege Attribution */
|
|
|
+ } MSPAR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t CFSAMONA; /*!< (@ 0x00000030) Code Flash Security Attribution Monitor Register
|
|
|
+ * A */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 15;
|
|
|
+ __IM uint32_t CFS2 : 9; /*!< [23..15] Code Flash Secure area */
|
|
|
+ uint32_t : 8;
|
|
|
+ } CFSAMONA_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t DFSAMON; /*!< (@ 0x00000034) Data Flash Security Attribution Monitor Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 10;
|
|
|
+ __IM uint32_t DFS : 6; /*!< [15..10] Data flash Secure area */
|
|
|
+ uint32_t : 16;
|
|
|
+ } DFSAMON_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t DLMMON; /*!< (@ 0x00000038) Device Lifecycle Management State Monitor Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t DLMMON : 4; /*!< [3..0] Device Lifecycle Management State Monitor */
|
|
|
+ uint32_t : 28;
|
|
|
+ } DLMMON_b;
|
|
|
+ };
|
|
|
+} R_PSCU_Type; /*!< Size = 60 (0x3c) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_BUS ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Bus Interface (R_BUS)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x40003000) R_BUS Structure */
|
|
|
+{
|
|
|
+ __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */
|
|
|
+ __IM uint32_t RESERVED[480];
|
|
|
+ __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */
|
|
|
+ __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */
|
|
|
+ __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */
|
|
|
+ __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */
|
|
|
+ __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */
|
|
|
+ __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */
|
|
|
+ __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */
|
|
|
+ __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */
|
|
|
+ __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */
|
|
|
+ __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */
|
|
|
+ __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */
|
|
|
+ __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */
|
|
|
+ __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */
|
|
|
+ __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */
|
|
|
+ __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */
|
|
|
+ __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */
|
|
|
+ } CSRECEN_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED1;
|
|
|
+ __IM uint32_t RESERVED2[223];
|
|
|
+ __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */
|
|
|
+ __IM uint32_t RESERVED3[235];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM R_BUS_OAD_Type OAD; /*!< (@ 0x00001000) Bus Operation After Detection Registers */
|
|
|
+ __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers */
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED4[58];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t BUSMABT; /*!< (@ 0x00001100) Bus Master Arbitration Control Register. */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI. */
|
|
|
+ uint32_t : 31;
|
|
|
+ } BUSMABT_b;
|
|
|
+ };
|
|
|
+ __IOM R_BUS_BUSS_Type BUSS[18]; /*!< (@ 0x00001100) Slave Bus Control Register Array */
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED5[46];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers */
|
|
|
+ __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers */
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED6[33];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t BUSDIVBYP; /*!< (@ 0x00001300) Bus Divider Bypass Register. */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t EDMABPE : 1; /*!< [0..0] Divider for EDMACBI bypass enable. */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t GDSSBPE : 1; /*!< [3..3] Divider for GDSSBI bypass enable. */
|
|
|
+ uint32_t : 12;
|
|
|
+ __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable. */
|
|
|
+ uint32_t : 15;
|
|
|
+ } BUSDIVBYP_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED7[319];
|
|
|
+ __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers */
|
|
|
+ __IM uint32_t RESERVED8[16];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */
|
|
|
+ __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address
|
|
|
+ * and Read/Write Status registers. */
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED9[28];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM R_BUS_BUSERRb_Type BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers */
|
|
|
+ __IOM R_BUS_DMACDTCERR_Type DMACDTCERR; /*!< (@ 0x00001A00) DMAC/DTC Error Registers */
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED10[16];
|
|
|
+ __IOM R_BUS_MBWERR_Type MBWERR; /*!< (@ 0x00001B00) Master Bufferable Write Error Registers */
|
|
|
+ __IM uint32_t RESERVED11[5];
|
|
|
+ __IOM R_BUS_MBWERR_Type SBWERR; /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers */
|
|
|
+} R_BUS_Type; /*!< Size = 6956 (0x1b2c) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_CAC ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x40202400) R_CAC Structure */
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */
|
|
|
+ uint8_t : 7;
|
|
|
+ } CACR0_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */
|
|
|
+ __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */
|
|
|
+ __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */
|
|
|
+ __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */
|
|
|
+ } CACR1_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */
|
|
|
+ __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */
|
|
|
+ __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio
|
|
|
+ * Select */
|
|
|
+ __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */
|
|
|
+ } CACR2_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */
|
|
|
+ __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */
|
|
|
+ __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */
|
|
|
+ uint8_t : 1;
|
|
|
+ __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */
|
|
|
+ __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */
|
|
|
+ __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */
|
|
|
+ uint8_t : 1;
|
|
|
+ } CAICR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */
|
|
|
+ __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */
|
|
|
+ __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */
|
|
|
+ uint8_t : 5;
|
|
|
+ } CASTR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores
|
|
|
+ * the upper-limit value of the frequency. */
|
|
|
+ } CAULVR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores
|
|
|
+ * the lower-limit value of the frequency. */
|
|
|
+ } CALLVR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains
|
|
|
+ * the counter value at the time a valid reference signal
|
|
|
+ * edge is input */
|
|
|
+ } CACNTBR_b;
|
|
|
+ };
|
|
|
+} R_CAC_Type; /*!< Size = 12 (0xc) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_CANFD0 ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Controller Area Network - Flexible Data (CAN-FD) Module (R_CANFD0)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x40380000) R_CANFD0 Structure */
|
|
|
+{
|
|
|
+ __IOM R_CANFD_CFDC_Type CFDC[1]; /*!< (@ 0x00000000) Channel Control/Status */
|
|
|
+ __IM uint32_t RESERVED;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFDGCFG; /*!< (@ 0x00000014) Global Configuration Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t TPRI : 1; /*!< [0..0] Transmission Priority */
|
|
|
+ __IOM uint32_t DCE : 1; /*!< [1..1] DLC Check Enable */
|
|
|
+ __IOM uint32_t DRE : 1; /*!< [2..2] DLC Replacement Enable */
|
|
|
+ __IOM uint32_t MME : 1; /*!< [3..3] Mirror Mode Enable */
|
|
|
+ __IOM uint32_t DCS : 1; /*!< [4..4] Data Link Controller Clock Select */
|
|
|
+ __IOM uint32_t CMPOC : 1; /*!< [5..5] CAN-FD message Payload overflow configuration */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t TSP : 4; /*!< [11..8] Timestamp Prescaler */
|
|
|
+ __IOM uint32_t TSSS : 1; /*!< [12..12] Timestamp Source Select */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t ITRCP : 16; /*!< [31..16] Interval Timer Reference Clock Prescaler */
|
|
|
+ } CFDGCFG_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFDGCTR; /*!< (@ 0x00000018) Global Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t GMDC : 2; /*!< [1..0] Global Mode Control */
|
|
|
+ __IOM uint32_t GSLPR : 1; /*!< [2..2] Global Sleep Request */
|
|
|
+ uint32_t : 5;
|
|
|
+ __IOM uint32_t DEIE : 1; /*!< [8..8] DLC check Interrupt Enable */
|
|
|
+ __IOM uint32_t MEIE : 1; /*!< [9..9] Message lost Error Interrupt Enable */
|
|
|
+ __IOM uint32_t THLEIE : 1; /*!< [10..10] TX History List Entry Lost Interrupt Enable */
|
|
|
+ __IOM uint32_t CMPOFIE : 1; /*!< [11..11] CAN-FD message payload overflow Flag Interrupt enable */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t TSRST : 1; /*!< [16..16] Timestamp Reset */
|
|
|
+ uint32_t : 15;
|
|
|
+ } CFDGCTR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFDGSTS; /*!< (@ 0x0000001C) Global Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t GRSTSTS : 1; /*!< [0..0] Global Reset Status */
|
|
|
+ __IM uint32_t GHLTSTS : 1; /*!< [1..1] Global Halt Status */
|
|
|
+ __IM uint32_t GSLPSTS : 1; /*!< [2..2] Global Sleep Status */
|
|
|
+ __IM uint32_t GRAMINIT : 1; /*!< [3..3] Global RAM Initialisation */
|
|
|
+ uint32_t : 28;
|
|
|
+ } CFDGSTS_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFDGERFL; /*!< (@ 0x00000020) Global Error Flag Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t DEF : 1; /*!< [0..0] DLC Error Flag */
|
|
|
+ __IM uint32_t MES : 1; /*!< [1..1] Message Lost Error Status */
|
|
|
+ __IM uint32_t THLES : 1; /*!< [2..2] TX History List Entry Lost Error Status */
|
|
|
+ __IOM uint32_t CMPOF : 1; /*!< [3..3] CAN-FD message payload overflow Flag */
|
|
|
+ uint32_t : 12;
|
|
|
+ __IOM uint32_t EEF0 : 1; /*!< [16..16] ECC Error Flag for Channel 0 */
|
|
|
+ uint32_t : 15;
|
|
|
+ } CFDGERFL_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFDGTSC; /*!< (@ 0x00000024) Global Timestamp Counter Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t TS : 16; /*!< [15..0] Timestamp Value */
|
|
|
+ uint32_t : 16;
|
|
|
+ } CFDGTSC_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFDGAFLECTR; /*!< (@ 0x00000028) Global Acceptance Filter List Entry Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t AFLPN : 4; /*!< [3..0] Acceptance Filter List Page Number */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t AFLDAE : 1; /*!< [8..8] Acceptance Filter List Data Access Enable */
|
|
|
+ uint32_t : 23;
|
|
|
+ } CFDGAFLECTR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFDGAFLCFG0; /*!< (@ 0x0000002C) Global Acceptance Filter List Configuration Register
|
|
|
+ * 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t RNC1 : 9; /*!< [8..0] Rule Number for Channel 1 */
|
|
|
+ uint32_t : 7;
|
|
|
+ __IOM uint32_t RNC0 : 9; /*!< [24..16] Rule Number for Channel 0 */
|
|
|
+ uint32_t : 7;
|
|
|
+ } CFDGAFLCFG0_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFDRMNB; /*!< (@ 0x00000030) RX Message Buffer Number Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t NRXMB : 8; /*!< [7..0] Number of RX Message Buffers */
|
|
|
+ __IOM uint32_t RMPLS : 3; /*!< [10..8] Reception Message Buffer Payload Data Size */
|
|
|
+ uint32_t : 21;
|
|
|
+ } CFDRMNB_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFDRMND0; /*!< (@ 0x00000034) RX Message Buffer New Data Register 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t RMNSu : 32; /*!< [31..0] RX Message Buffer New Data Status */
|
|
|
+ } CFDRMND0_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFDRMIEC; /*!< (@ 0x00000038) RX Message Buffer Interrupt Enable Configuration
|
|
|
+ * Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t RMIE : 32; /*!< [31..0] RX Message Buffer Interrupt Enable */
|
|
|
+ } CFDRMIEC_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFDRFCC[2]; /*!< (@ 0x0000003C) RX FIFO Configuration / Control Registers */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t RFE : 1; /*!< [0..0] RX FIFO Enable */
|
|
|
+ __IOM uint32_t RFIE : 1; /*!< [1..1] RX FIFO Interrupt Enable */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t RFPLS : 3; /*!< [6..4] Rx FIFO Payload Data Size configuration */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t RFDC : 3; /*!< [10..8] RX FIFO Depth Configuration */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t RFIM : 1; /*!< [12..12] RX FIFO Interrupt Mode */
|
|
|
+ __IOM uint32_t RFIGCV : 3; /*!< [15..13] RX FIFO Interrupt Generation Counter Value */
|
|
|
+ uint32_t : 16;
|
|
|
+ } CFDRFCC_b[2];
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFDRFSTS[2]; /*!< (@ 0x00000044) RX FIFO Status Registers */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t RFEMP : 1; /*!< [0..0] RX FIFO Empty */
|
|
|
+ __IM uint32_t RFFLL : 1; /*!< [1..1] RX FIFO Full */
|
|
|
+ __IOM uint32_t RFMLT : 1; /*!< [2..2] RX FIFO Message Lost */
|
|
|
+ __IOM uint32_t RFIF : 1; /*!< [3..3] RX FIFO Interrupt Flag */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IM uint32_t RFMC : 8; /*!< [15..8] RX FIFO Message Count */
|
|
|
+ uint32_t : 16;
|
|
|
+ } CFDRFSTS_b[2];
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFDRFPCTR[2]; /*!< (@ 0x0000004C) RX FIFO Pointer Control Registers */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __OM uint32_t RFPC : 8; /*!< [7..0] RX FIFO Pointer Control */
|
|
|
+ uint32_t : 24;
|
|
|
+ } CFDRFPCTR_b[2];
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFDCFCC[1]; /*!< (@ 0x00000054) Common FIFO Configuration / Control Registers */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFE : 1; /*!< [0..0] Common FIFO Enable */
|
|
|
+ __IOM uint32_t CFRXIE : 1; /*!< [1..1] Common FIFO RX Interrupt Enable */
|
|
|
+ __IOM uint32_t CFTXIE : 1; /*!< [2..2] Common FIFO TX Interrupt Enable */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t CFPLS : 3; /*!< [6..4] Common FIFO Payload Data size configuration */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t CFM : 2; /*!< [9..8] Common FIFO Mode */
|
|
|
+ __IOM uint32_t CFITSS : 1; /*!< [10..10] Common FIFO Interval Timer Source Select */
|
|
|
+ __IOM uint32_t CFITR : 1; /*!< [11..11] Common FIFO Interval Timer Resolution */
|
|
|
+ __IOM uint32_t CFIM : 1; /*!< [12..12] Common FIFO Interrupt Mode */
|
|
|
+ __IOM uint32_t CFIGCV : 3; /*!< [15..13] Common FIFO Interrupt Generation Counter Value */
|
|
|
+ __IOM uint32_t CFTML : 5; /*!< [20..16] Common FIFO TX Message Buffer Link */
|
|
|
+ __IOM uint32_t CFDC : 3; /*!< [23..21] Common FIFO Depth Configuration */
|
|
|
+ __IOM uint32_t CFITT : 8; /*!< [31..24] Common FIFO Interval Transmission Time */
|
|
|
+ } CFDCFCC_b[1];
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFDCFSTS[1]; /*!< (@ 0x00000058) Common FIFO Status Registers */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t CFEMP : 1; /*!< [0..0] Common FIFO Empty */
|
|
|
+ __IM uint32_t CFFLL : 1; /*!< [1..1] Common FIFO Full */
|
|
|
+ __IOM uint32_t CFMLT : 1; /*!< [2..2] Common FIFO Message Lost */
|
|
|
+ __IOM uint32_t CFRXIF : 1; /*!< [3..3] Common RX FIFO Interrupt Flag */
|
|
|
+ __IOM uint32_t CFTXIF : 1; /*!< [4..4] Common TX FIFO Interrupt Flag */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IM uint32_t CFMC : 8; /*!< [15..8] Common FIFO Message Count */
|
|
|
+ uint32_t : 16;
|
|
|
+ } CFDCFSTS_b[1];
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFDCFPCTR[1]; /*!< (@ 0x0000005C) Common FIFO Pointer Control Registers */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __OM uint32_t CFPC : 8; /*!< [7..0] Common FIFO Pointer Control */
|
|
|
+ uint32_t : 24;
|
|
|
+ } CFDCFPCTR_b[1];
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t CFDFESTS; /*!< (@ 0x00000060) FIFO Empty Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t RFXEMP : 2; /*!< [1..0] RX FIF0 Empty Status */
|
|
|
+ uint32_t : 6;
|
|
|
+ __IM uint32_t CFXEMP : 1; /*!< [8..8] Common FIF0 Empty Status */
|
|
|
+ uint32_t : 23;
|
|
|
+ } CFDFESTS_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t CFDFFSTS; /*!< (@ 0x00000064) FIFO Full Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t RFXFLL : 2; /*!< [1..0] RX FIF0 Full Status */
|
|
|
+ uint32_t : 6;
|
|
|
+ __IM uint32_t CFXFLL : 1; /*!< [8..8] Common FIF0 Full Status */
|
|
|
+ uint32_t : 23;
|
|
|
+ } CFDFFSTS_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t CFDFMSTS; /*!< (@ 0x00000068) FIFO Message Lost Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t RFXMLT : 2; /*!< [1..0] RX FIFO Msg Lost Status */
|
|
|
+ uint32_t : 6;
|
|
|
+ __IM uint32_t CFXMLT : 1; /*!< [8..8] Common FIFO Msg Lost Status */
|
|
|
+ uint32_t : 23;
|
|
|
+ } CFDFMSTS_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFDRFISTS; /*!< (@ 0x0000006C) RX FIFO Interrupt Flag Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t RFXIF : 1; /*!< [0..0] RX FIFO[x] Interrupt Flag Status */
|
|
|
+ uint32_t : 31;
|
|
|
+ } CFDRFISTS_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t CFDTMC[4]; /*!< (@ 0x00000070) TX Message Buffer Control Registers */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t TMTR : 1; /*!< [0..0] TX Message Buffer Transmission Request */
|
|
|
+ __IOM uint8_t TMTAR : 1; /*!< [1..1] TX Message Buffer Transmission abort Request */
|
|
|
+ __IOM uint8_t TMOM : 1; /*!< [2..2] TX Message Buffer One-shot Mode */
|
|
|
+ uint8_t : 5;
|
|
|
+ } CFDTMC_b[4];
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t CFDTMSTS[4]; /*!< (@ 0x00000074) TX Message Buffer Status Registers */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint8_t TMTSTS : 1; /*!< [0..0] TX Message Buffer Transmission Status */
|
|
|
+ __IOM uint8_t TMTRF : 2; /*!< [2..1] TX Message Buffer Transmission Result Flag */
|
|
|
+ __IM uint8_t TMTRM : 1; /*!< [3..3] TX Message Buffer Transmission Request Mirrored */
|
|
|
+ __IM uint8_t TMTARM : 1; /*!< [4..4] TX Message Buffer Transmission abort Request Mirrored */
|
|
|
+ uint8_t : 3;
|
|
|
+ } CFDTMSTS_b[4];
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t CFDTMTRSTS[1]; /*!< (@ 0x00000078) TX Message Buffer Transmission Request Status
|
|
|
+ * Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t CFDTMTRSTSg : 4; /*!< [3..0] TX Message Buffer Transmission Request Status */
|
|
|
+ uint32_t : 28;
|
|
|
+ } CFDTMTRSTS_b[1];
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t CFDTMTARSTS[1]; /*!< (@ 0x0000007C) TX Message Buffer Transmission Abort Request
|
|
|
+ * Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t CFDTMTARSTSg : 4; /*!< [3..0] TX Message Buffer Transmission abort Request Status */
|
|
|
+ uint32_t : 28;
|
|
|
+ } CFDTMTARSTS_b[1];
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t CFDTMTCSTS[1]; /*!< (@ 0x00000080) TX Message Buffer Transmission Completion Status
|
|
|
+ * Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t CFDTMTCSTSg : 4; /*!< [3..0] TX Message Buffer Transmission Completion Status */
|
|
|
+ uint32_t : 28;
|
|
|
+ } CFDTMTCSTS_b[1];
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t CFDTMTASTS[1]; /*!< (@ 0x00000084) TX Message Buffer Transmission Abort Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t CFDTMTASTSg : 4; /*!< [3..0] TX Message Buffer Transmission abort Status */
|
|
|
+ uint32_t : 28;
|
|
|
+ } CFDTMTASTS_b[1];
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFDTMIEC[1]; /*!< (@ 0x00000088) TX Message Buffer Interrupt Enable Configuration
|
|
|
+ * Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t TMIEg : 4; /*!< [3..0] TX Message Buffer Interrupt Enable */
|
|
|
+ uint32_t : 28;
|
|
|
+ } CFDTMIEC_b[1];
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFDTXQCC0[1]; /*!< (@ 0x0000008C) TX Queue Configuration / Control Registers 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */
|
|
|
+ __IOM uint32_t TXQDC : 2; /*!< [9..8] TX Queue Depth Configuration */
|
|
|
+ uint32_t : 22;
|
|
|
+ } CFDTXQCC0_b[1];
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFDTXQSTS0[1]; /*!< (@ 0x00000090) TX Queue Status Registers 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */
|
|
|
+ __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */
|
|
|
+ __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */
|
|
|
+ uint32_t : 5;
|
|
|
+ __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */
|
|
|
+ uint32_t : 18;
|
|
|
+ } CFDTXQSTS0_b[1];
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFDTXQPCTR0[1]; /*!< (@ 0x00000094) TX Queue Pointer Control Registers 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */
|
|
|
+ uint32_t : 24;
|
|
|
+ } CFDTXQPCTR0_b[1];
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFDTHLCC[1]; /*!< (@ 0x00000098) TX History List Configuration / Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t THLE : 1; /*!< [0..0] TX History List Enable */
|
|
|
+ uint32_t : 7;
|
|
|
+ __IOM uint32_t THLIE : 1; /*!< [8..8] TX History List Interrupt Enable */
|
|
|
+ __IOM uint32_t THLIM : 1; /*!< [9..9] TX History List Interrupt Mode */
|
|
|
+ __IOM uint32_t THLDTE : 1; /*!< [10..10] TX History List Dedicated TX Enable */
|
|
|
+ uint32_t : 21;
|
|
|
+ } CFDTHLCC_b[1];
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFDTHLSTS[1]; /*!< (@ 0x0000009C) TX History List Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t THLEMP : 1; /*!< [0..0] TX History List Empty */
|
|
|
+ __IM uint32_t THLFLL : 1; /*!< [1..1] TX History List Full */
|
|
|
+ __IOM uint32_t THLELT : 1; /*!< [2..2] TX History List Entry Lost */
|
|
|
+ __IOM uint32_t THLIF : 1; /*!< [3..3] TX History List Interrupt Flag */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IM uint32_t THLMC : 6; /*!< [13..8] TX History List Message Count */
|
|
|
+ uint32_t : 18;
|
|
|
+ } CFDTHLSTS_b[1];
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFDTHLPCTR[1]; /*!< (@ 0x000000A0) TX History List Pointer Control Registers */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __OM uint32_t THLPC : 8; /*!< [7..0] TX History List Pointer Control */
|
|
|
+ uint32_t : 24;
|
|
|
+ } CFDTHLPCTR_b[1];
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFDGTINTSTS0; /*!< (@ 0x000000A4) Global TX Interrupt Status Register 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t TSIF0 : 1; /*!< [0..0] TX Successful Interrupt Flag Channel 0 */
|
|
|
+ __IM uint32_t TAIF0 : 1; /*!< [1..1] TX Abort Interrupt Flag Channel 0 */
|
|
|
+ __IM uint32_t TQIF0 : 1; /*!< [2..2] TX Queue Interrupt Flag Channel 0 */
|
|
|
+ __IM uint32_t CFTIF0 : 1; /*!< [3..3] COM FIFO TX/GW Mode Interrupt Flag Channel 0 */
|
|
|
+ __IM uint32_t THIF0 : 1; /*!< [4..4] TX History List Interrupt Channel 0 */
|
|
|
+ uint32_t : 27;
|
|
|
+ } CFDGTINTSTS0_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFDGTSTCFG; /*!< (@ 0x000000A8) Global Test Configuration Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 16;
|
|
|
+ __IOM uint32_t RTMPS : 10; /*!< [25..16] RAM Test Mode Page Select */
|
|
|
+ uint32_t : 6;
|
|
|
+ } CFDGTSTCFG_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFDGTSTCTR; /*!< (@ 0x000000AC) Global Test Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t RTME : 1; /*!< [2..2] RAM Test Mode Enable */
|
|
|
+ uint32_t : 29;
|
|
|
+ } CFDGTSTCTR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFDGFDCFG; /*!< (@ 0x000000B0) Global FD Configuration register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t RPED : 1; /*!< [0..0] RES bit Protocol exception disable */
|
|
|
+ uint32_t : 7;
|
|
|
+ __IOM uint32_t TSCCFG : 2; /*!< [9..8] Timestamp capture configuration */
|
|
|
+ uint32_t : 22;
|
|
|
+ } CFDGFDCFG_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED1;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFDGLOCKK; /*!< (@ 0x000000B8) Global Lock Key Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __OM uint32_t LOCK : 16; /*!< [15..0] Lock Key */
|
|
|
+ uint32_t : 16;
|
|
|
+ } CFDGLOCKK_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED2;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFDGAFLIGNENT; /*!< (@ 0x000000C0) Global AFL Ignore Entry Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t IRN : 5; /*!< [4..0] Ignore Rule Number */
|
|
|
+ uint32_t : 27;
|
|
|
+ } CFDGAFLIGNENT_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFDGAFLIGNCTR; /*!< (@ 0x000000C4) Global AFL Ignore Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t IREN : 1; /*!< [0..0] Ignore Rule Enable */
|
|
|
+ uint32_t : 7;
|
|
|
+ __OM uint32_t KEY : 8; /*!< [15..8] Key code */
|
|
|
+ uint32_t : 16;
|
|
|
+ } CFDGAFLIGNCTR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFDCDTCT; /*!< (@ 0x000000C8) DMA Transfer Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t RFDMAE0 : 1; /*!< [0..0] DMA Transfer Enable for RXFIFO 0 */
|
|
|
+ __IOM uint32_t RFDMAE1 : 1; /*!< [1..1] DMA Transfer Enable for RXFIFO 1 */
|
|
|
+ uint32_t : 6;
|
|
|
+ __IOM uint32_t CFDMAE0 : 1; /*!< [8..8] DMA Transfer Enable for Common FIFO 0 of channel 0 */
|
|
|
+ uint32_t : 23;
|
|
|
+ } CFDCDTCT_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t CFDCDTSTS; /*!< (@ 0x000000CC) DMA Transfer Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t RFDMASTS0 : 1; /*!< [0..0] DMA Transfer Status for RX FIFO 0 */
|
|
|
+ __IM uint32_t RFDMASTS1 : 1; /*!< [1..1] DMA Transfer Status for RX FIFO 1 */
|
|
|
+ uint32_t : 6;
|
|
|
+ __IM uint32_t CFDMASTS0 : 1; /*!< [8..8] DMA Transfer Status only for Common FIFO 0 of channel
|
|
|
+ * 0 */
|
|
|
+ uint32_t : 23;
|
|
|
+ } CFDCDTSTS_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED3[2];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFDGRSTC; /*!< (@ 0x000000D8) Global SW reset Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t SRST : 1; /*!< [0..0] SW reset */
|
|
|
+ uint32_t : 7;
|
|
|
+ __OM uint32_t KEY : 8; /*!< [15..8] Key code */
|
|
|
+ uint32_t : 16;
|
|
|
+ } CFDGRSTC_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED4[9];
|
|
|
+ __IOM R_CANFD_CFDC2_Type CFDC2[1]; /*!< (@ 0x00000100) Channel Configuration Registers */
|
|
|
+ __IOM R_CANFD_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00000120) Global Acceptance Filter List Registers */
|
|
|
+ __IM uint32_t RESERVED5[24];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFDRPGACC[64]; /*!< (@ 0x00000280) RAM Test Page Access Registers */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t RDTA : 32; /*!< [31..0] RAM Data Test Access */
|
|
|
+ } CFDRPGACC_b[64];
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED6[104];
|
|
|
+ __IOM R_CANFD_CFDRF_Type CFDRF[2]; /*!< (@ 0x00000520) RX FIFO Access Registers */
|
|
|
+ __IOM R_CANFD_CFDCF_Type CFDCF[1]; /*!< (@ 0x000005B8) Common FIFO Access Registers */
|
|
|
+ __IOM R_CANFD_CFDTM_Type CFDTM[4]; /*!< (@ 0x00000604) TX Message Buffer Access Registers */
|
|
|
+ __IM uint32_t RESERVED7[3];
|
|
|
+ __IOM R_CANFD_CFDTHL_Type CFDTHL[1]; /*!< (@ 0x00000740) Channel TX History List */
|
|
|
+ __IM uint32_t RESERVED8[118];
|
|
|
+ __IOM R_CANFD_CFDRM_Type CFDRM[4]; /*!< (@ 0x00000920) RX Message Buffer Access Clusters */
|
|
|
+} R_CANFD_Type; /*!< Size = 6432 (0x1920) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_CRC ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x40310000) R_CRC Structure */
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */
|
|
|
+ uint8_t : 3;
|
|
|
+ __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */
|
|
|
+ __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */
|
|
|
+ } CRCCR0_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint8_t : 6;
|
|
|
+ __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */
|
|
|
+ __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */
|
|
|
+ } CRCCR1_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */
|
|
|
+ } CRCDIR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT
|
|
|
+ * ) */
|
|
|
+ } CRCDIR_BY_b;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */
|
|
|
+ } CRCDOR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT
|
|
|
+ * ) */
|
|
|
+ } CRCDOR_HA_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */
|
|
|
+ } CRCDOR_BY_b;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */
|
|
|
+ uint16_t : 2;
|
|
|
+ } CRCSAR_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED1;
|
|
|
+} R_CRC_Type; /*!< Size = 16 (0x10) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_DAC ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief D/A Converter (R_DAC)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x40333000) R_DAC Structure */
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t DADR[2]; /*!< (@ 0x00000000) D/A Data Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t DADR : 16; /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order
|
|
|
+ * 4 bits are fixed to 0: right justified format. When DADPR.DPSEL
|
|
|
+ * = 1, the low-order 4 bits are fixed to 0: left justified
|
|
|
+ * format. */
|
|
|
+ } DADR_b[2];
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t DACR; /*!< (@ 0x00000004) D/A Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint8_t : 5;
|
|
|
+ __IOM uint8_t DAE : 1; /*!< [5..5] D/A Enable */
|
|
|
+ __IOM uint8_t DAOE0 : 1; /*!< [6..6] D/A Output Enable 0 */
|
|
|
+ __IOM uint8_t DAOE1 : 1; /*!< [7..7] D/A Output Enable 0 */
|
|
|
+ } DACR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t DADPR; /*!< (@ 0x00000005) DADR0 Format Select Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint8_t : 7;
|
|
|
+ __IOM uint8_t DPSEL : 1; /*!< [7..7] DADRm Format Select */
|
|
|
+ } DADPR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t DAADSCR; /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint8_t : 7;
|
|
|
+ __IOM uint8_t DAADST : 1; /*!< [7..7] D/A-A/D Synchronous Conversion */
|
|
|
+ } DAADSCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t DAVREFCR; /*!< (@ 0x00000007) D/A VREF Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t REF : 3; /*!< [2..0] D/A Reference Voltage Select */
|
|
|
+ uint8_t : 5;
|
|
|
+ } DAVREFCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t DAAMPCR; /*!< (@ 0x00000008) D/A Output Amplifier Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint8_t : 6;
|
|
|
+ __IOM uint8_t DAAMP0 : 1; /*!< [6..6] Amplifier Control */
|
|
|
+ __IOM uint8_t DAAMP1 : 1; /*!< [7..7] Amplifier Control */
|
|
|
+ } DAAMPCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t DAPC; /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge Pump Enable */
|
|
|
+ uint8_t : 7;
|
|
|
+ } DAPC_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED[9];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t DAASWCR; /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint8_t : 6;
|
|
|
+ __IOM uint8_t DAASW0 : 1; /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure
|
|
|
+ * to wait for stabilization of the output amplifier of D/A
|
|
|
+ * channel 0. When DAASW0 is set to 1, D/A conversion operates,
|
|
|
+ * but the conversion result D/A is not output from channel
|
|
|
+ * 0. When the DAASW0 bit is 0, the stabilization wait time
|
|
|
+ * stops, and the D/A conversion result of channel 0 is output
|
|
|
+ * through the output amplifier. */
|
|
|
+ __IOM uint8_t DAASW1 : 1; /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure
|
|
|
+ * to wait for stabilization of the output amplifier of D/A
|
|
|
+ * channel 1. When DAASW1 is set to 1, D/A conversion operates,
|
|
|
+ * but the conversion result D/A is not output from channel
|
|
|
+ * 1. When the DAASW1 bit is 0, the stabilization wait time
|
|
|
+ * stops, and the D/A conversion result of channel 1 is output
|
|
|
+ * through the output amplifier. */
|
|
|
+ } DAASWCR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED1;
|
|
|
+ __IM uint16_t RESERVED2[2129];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t AMADSEL0 : 1; /*!< [0..0] The DAADUSR register selects the target ADC12 unit for
|
|
|
+ * D/A and A/D synchronous conversions. Set bit [0] to 1 to
|
|
|
+ * select unit 0 as the target synchronous unit for the MCU.
|
|
|
+ * When setting the DAADSCR.DAADST bit to 1 for synchronous
|
|
|
+ * conversions, select the target unit in this register in
|
|
|
+ * advance. Only set the DAADUSR register while the ADCSR.ADST
|
|
|
+ * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit
|
|
|
+ * is set to 0. */
|
|
|
+ __IOM uint8_t AMADSEL1 : 1; /*!< [1..1] The DAADUSR register selects the target ADC12 unit for
|
|
|
+ * D/A and A/D synchronous conversions. Set bit [1] to 1 to
|
|
|
+ * select unit 1 as the target synchronous unit for the MCU.
|
|
|
+ * When setting the DAADSCR.DAADST bit to 1 for synchronous
|
|
|
+ * conversions, select the target unit in this register in
|
|
|
+ * advance. Only set the DAADUSR register while the ADCSR.ADST
|
|
|
+ * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit
|
|
|
+ * is set to 0. */
|
|
|
+ uint8_t : 6;
|
|
|
+ } DAADUSR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED3;
|
|
|
+ __IM uint16_t RESERVED4;
|
|
|
+} R_DAC_Type; /*!< Size = 4292 (0x10c4) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_DEBUG ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Debug Function (R_DEBUG)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 28;
|
|
|
+ __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */
|
|
|
+ __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */
|
|
|
+ uint32_t : 2;
|
|
|
+ } DBGSTR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED[3];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */
|
|
|
+ __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */
|
|
|
+ uint32_t : 14;
|
|
|
+ __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */
|
|
|
+ __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */
|
|
|
+ __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */
|
|
|
+ uint32_t : 5;
|
|
|
+ __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */
|
|
|
+ __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */
|
|
|
+ uint32_t : 5;
|
|
|
+ __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */
|
|
|
+ } DBGSTOPCR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED1[123];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t FSBLSTAT; /*!< (@ 0x00000200) First Stage Boot Loader Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CS : 1; /*!< [0..0] FSBL completion status. */
|
|
|
+ __IOM uint32_t RS : 1; /*!< [1..1] FSBL result status. */
|
|
|
+ uint32_t : 6;
|
|
|
+ __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution */
|
|
|
+ uint32_t : 21;
|
|
|
+ } FSBLSTAT_b;
|
|
|
+ };
|
|
|
+} R_DEBUG_Type; /*!< Size = 516 (0x204) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_DMA ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief DMA Controller Common (R_DMA)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x4000A800) R_DMA Structure */
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t DMAST; /*!< (@ 0x00000000) DMAC Module Activation Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t DMST : 1; /*!< [0..0] DMAC Operation Enable */
|
|
|
+ uint8_t : 7;
|
|
|
+ } DMAST_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED;
|
|
|
+ __IM uint16_t RESERVED1;
|
|
|
+ __IM uint32_t RESERVED2[15];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t DMECHR; /*!< (@ 0x00000040) DMAC Error Channel Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */
|
|
|
+ uint32_t : 5;
|
|
|
+ __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */
|
|
|
+ uint32_t : 7;
|
|
|
+ __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */
|
|
|
+ uint32_t : 15;
|
|
|
+ } DMECHR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED3[15];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t DELSR[8]; /*!< (@ 0x00000080) DMAC Event Link Setting Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t DELS : 9; /*!< [8..0] DMAC Event Link Select */
|
|
|
+ uint32_t : 7;
|
|
|
+ __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the
|
|
|
+ * IR flag is prohibited. */
|
|
|
+ uint32_t : 15;
|
|
|
+ } DELSR_b[8];
|
|
|
+ };
|
|
|
+} R_DMA_Type; /*!< Size = 160 (0xa0) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_DMAC0 ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief DMA Controller (R_DMAC0)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x4000A000) R_DMAC0 Structure */
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t DMSAR; /*!< (@ 0x00000000) DMA Source Address Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address. */
|
|
|
+ } DMSAR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t DMDAR; /*!< (@ 0x00000004) DMA Destination Address Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address. */
|
|
|
+ } DMDAR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t DMCRA; /*!< (@ 0x00000008) DMA Transfer Count Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count */
|
|
|
+ __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count */
|
|
|
+ uint32_t : 6;
|
|
|
+ } DMCRA_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t DMCRB; /*!< (@ 0x0000000C) DMA Block Transfer Count Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t DMCRBL : 16; /*!< [15..0] Functions as a number of block, repeat or repeat-block
|
|
|
+ * transfer counter. */
|
|
|
+ __IOM uint32_t DMCRBH : 16; /*!< [31..16] Specifies the number of block transfer operations or
|
|
|
+ * repeat transfer operations. */
|
|
|
+ } DMCRB_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t DMTMD; /*!< (@ 0x00000010) DMA Transfer Mode Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t DCTG : 2; /*!< [1..0] Transfer Request Source Select */
|
|
|
+ uint16_t : 6;
|
|
|
+ __IOM uint16_t SZ : 2; /*!< [9..8] Transfer Data Size Select */
|
|
|
+ __IOM uint16_t TKP : 1; /*!< [10..10] Transfer Keeping */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t DTS : 2; /*!< [13..12] Repeat Area Select */
|
|
|
+ __IOM uint16_t MD : 2; /*!< [15..14] Transfer Mode Select */
|
|
|
+ } DMTMD_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t DMINT; /*!< (@ 0x00000013) DMA Interrupt Setting Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t DARIE : 1; /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt
|
|
|
+ * Enable */
|
|
|
+ __IOM uint8_t SARIE : 1; /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt
|
|
|
+ * Enable */
|
|
|
+ __IOM uint8_t RPTIE : 1; /*!< [2..2] Repeat Size End Interrupt Enable */
|
|
|
+ __IOM uint8_t ESIE : 1; /*!< [3..3] Transfer Escape End Interrupt Enable */
|
|
|
+ __IOM uint8_t DTIE : 1; /*!< [4..4] Transfer End Interrupt Enable */
|
|
|
+ uint8_t : 3;
|
|
|
+ } DMINT_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t DMAMD; /*!< (@ 0x00000014) DMA Address Mode Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the
|
|
|
+ * extended repeat area on the destination address. For details
|
|
|
+ * on the settings. */
|
|
|
+ __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */
|
|
|
+ __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */
|
|
|
+ __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended
|
|
|
+ * repeat area on the source address. For details on the settings. */
|
|
|
+ __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */
|
|
|
+ __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */
|
|
|
+ } DMAMD_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED1;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t DMOFR; /*!< (@ 0x00000018) DMA Offset Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected
|
|
|
+ * as the address update mode for transfer source or destination. */
|
|
|
+ } DMOFR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t DMCNT; /*!< (@ 0x0000001C) DMA Transfer Enable Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t DTE : 1; /*!< [0..0] DMA Transfer Enable */
|
|
|
+ uint8_t : 7;
|
|
|
+ } DMCNT_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t DMREQ; /*!< (@ 0x0000001D) DMA Software Start Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t SWREQ : 1; /*!< [0..0] DMA Software Start */
|
|
|
+ uint8_t : 3;
|
|
|
+ __IOM uint8_t CLRS : 1; /*!< [4..4] DMA Software Start Bit Auto Clear Select */
|
|
|
+ uint8_t : 3;
|
|
|
+ } DMREQ_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t DMSTS; /*!< (@ 0x0000001E) DMA Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t ESIF : 1; /*!< [0..0] Transfer Escape End Interrupt Flag */
|
|
|
+ uint8_t : 3;
|
|
|
+ __IOM uint8_t DTIF : 1; /*!< [4..4] Transfer End Interrupt Flag */
|
|
|
+ uint8_t : 2;
|
|
|
+ __IM uint8_t ACT : 1; /*!< [7..7] DMA Active Flag */
|
|
|
+ } DMSTS_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED2;
|
|
|
+ __IOM uint32_t DMSRR; /*!< (@ 0x00000020) DMA Source Reload Address Register */
|
|
|
+ __IOM uint32_t DMDRR; /*!< (@ 0x00000024) DMA Destination Reload Address Register */
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t DMSBS; /*!< (@ 0x00000028) DMA Source Buffer Size Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer
|
|
|
+ * mode */
|
|
|
+ __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer
|
|
|
+ * mode */
|
|
|
+ } DMSBS_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t DMDBS; /*!< (@ 0x0000002C) DMA Destination Buffer Size Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer
|
|
|
+ * mode */
|
|
|
+ __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer
|
|
|
+ * mode */
|
|
|
+ } DMDBS_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t DMBWR; /*!< (@ 0x00000030) DMA Bufferable Write Enable Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t BWE : 1; /*!< [0..0] Bufferable Write Enable */
|
|
|
+ uint8_t : 7;
|
|
|
+ } DMBWR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED3;
|
|
|
+ __IM uint16_t RESERVED4;
|
|
|
+} R_DMAC0_Type; /*!< Size = 52 (0x34) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_DOC ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Data Operation Circuit (R_DOC)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x40311000) R_DOC Structure */
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */
|
|
|
+ __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */
|
|
|
+ uint8_t : 2;
|
|
|
+ __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */
|
|
|
+ __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */
|
|
|
+ uint8_t : 1;
|
|
|
+ } DOCR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for
|
|
|
+ * use in the operations are stored. */
|
|
|
+ } DODIR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference
|
|
|
+ * in data comparison mode. This register also stores the
|
|
|
+ * results of operations in data addition and data subtraction
|
|
|
+ * modes. */
|
|
|
+ } DODSR_b;
|
|
|
+ };
|
|
|
+} R_DOC_Type; /*!< Size = 6 (0x6) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_DTC ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Data Transfer Controller (R_DTC)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x4000AC00) R_DTC Structure */
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint8_t : 4;
|
|
|
+ __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */
|
|
|
+ uint8_t : 3;
|
|
|
+ } DTCCR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED;
|
|
|
+ __IM uint16_t RESERVED1;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set
|
|
|
+ * in the lower-order 10 bits. These bits are fixed to 0. */
|
|
|
+ } DTCVBR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED2;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */
|
|
|
+ uint8_t : 7;
|
|
|
+ } DTCST_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED3;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate
|
|
|
+ * the vector number for the activating source when DTC transfer
|
|
|
+ * is in progress.The value is only valid if DTC transfer
|
|
|
+ * is in progress (the value of the ACT flag is 1) */
|
|
|
+ uint16_t : 7;
|
|
|
+ __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */
|
|
|
+ } DTCSTS_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint8_t : 4;
|
|
|
+ __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */
|
|
|
+ uint8_t : 3;
|
|
|
+ } DTCCR_SEC_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED4;
|
|
|
+ __IM uint16_t RESERVED5;
|
|
|
+ __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */
|
|
|
+ __IM uint32_t RESERVED6[2];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */
|
|
|
+ __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */
|
|
|
+ uint32_t : 7;
|
|
|
+ __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */
|
|
|
+ uint32_t : 15;
|
|
|
+ } DTEVR_b;
|
|
|
+ };
|
|
|
+} R_DTC_Type; /*!< Size = 36 (0x24) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_ELC ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Event Link Controller (R_ELC)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x40201000) R_ELC Structure */
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint8_t : 7;
|
|
|
+ __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */
|
|
|
+ } ELCR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED;
|
|
|
+ __IM uint16_t RESERVED1;
|
|
|
+ __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000004) Event Link Software Event Generation Register */
|
|
|
+ __IM uint32_t RESERVED2[6];
|
|
|
+ __IOM R_ELC_ELSR_Type ELSR[31]; /*!< (@ 0x00000020) Event Link Setting Register [0..30] */
|
|
|
+ __IM uint32_t RESERVED3[17];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t ELCSARA; /*!< (@ 0x000000E0) Event Link Controller Security Attribution Register
|
|
|
+ * A */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t ELCR : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution */
|
|
|
+ __IOM uint32_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security
|
|
|
+ * Attribution */
|
|
|
+ __IOM uint32_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security
|
|
|
+ * Attribution */
|
|
|
+ uint32_t : 29;
|
|
|
+ } ELCSARA_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t ELCSARB; /*!< (@ 0x000000E4) Event Link Controller Security Attribution Register
|
|
|
+ * B */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0 Security Attribution */
|
|
|
+ __IOM uint32_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1 Security Attribution */
|
|
|
+ __IOM uint32_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2 Security Attribution */
|
|
|
+ __IOM uint32_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3 Security Attribution */
|
|
|
+ __IOM uint32_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4 Security Attribution */
|
|
|
+ __IOM uint32_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5 Security Attribution */
|
|
|
+ __IOM uint32_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6 Security Attribution */
|
|
|
+ __IOM uint32_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7 Security Attribution */
|
|
|
+ __IOM uint32_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8 Security Attribution */
|
|
|
+ __IOM uint32_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9 Security Attribution */
|
|
|
+ __IOM uint32_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10 Security Attribution */
|
|
|
+ __IOM uint32_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11 Security Attribution */
|
|
|
+ __IOM uint32_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12 Security Attribution */
|
|
|
+ __IOM uint32_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13 Security Attribution */
|
|
|
+ __IOM uint32_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14 Security Attribution */
|
|
|
+ __IOM uint32_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15 Security Attribution */
|
|
|
+ __IOM uint32_t ELSR16 : 1; /*!< [16..16] Event Link Setting Register 16 Security Attribution */
|
|
|
+ __IOM uint32_t ELSR17 : 1; /*!< [17..17] Event Link Setting Register 17 Security Attribution */
|
|
|
+ uint32_t : 12;
|
|
|
+ __IOM uint32_t ELSR30 : 1; /*!< [30..30] Event Link Setting Register 30 Security Attribution */
|
|
|
+ uint32_t : 1;
|
|
|
+ } ELCSARB_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED4[2];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t ELCPARA; /*!< (@ 0x000000F0) Event Link Controller Priviledge Attribution
|
|
|
+ * Register A */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t ELCR : 1; /*!< [0..0] Event Link Controller Register Priviledge Attribution */
|
|
|
+ __IOM uint32_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Priviledge
|
|
|
+ * Attribution */
|
|
|
+ __IOM uint32_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1 Priviledge
|
|
|
+ * Attribution */
|
|
|
+ uint32_t : 29;
|
|
|
+ } ELCPARA_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t ELCPARB; /*!< (@ 0x000000F4) Event Link Controller Priviledge Attribution
|
|
|
+ * Register B */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0 Priviledge Attribution */
|
|
|
+ __IOM uint32_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1 Priviledge Attribution */
|
|
|
+ __IOM uint32_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2 Priviledge Attribution */
|
|
|
+ __IOM uint32_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3 Priviledge Attribution */
|
|
|
+ __IOM uint32_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4 Priviledge Attribution */
|
|
|
+ __IOM uint32_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5 Priviledge Attribution */
|
|
|
+ __IOM uint32_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6 Priviledge Attribution */
|
|
|
+ __IOM uint32_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7 Priviledge Attribution */
|
|
|
+ __IOM uint32_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8 Priviledge Attribution */
|
|
|
+ __IOM uint32_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9 Priviledge Attribution */
|
|
|
+ __IOM uint32_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10 Priviledge Attribution */
|
|
|
+ __IOM uint32_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11 Priviledge Attribution */
|
|
|
+ __IOM uint32_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12 Priviledge Attribution */
|
|
|
+ __IOM uint32_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13 Priviledge Attribution */
|
|
|
+ __IOM uint32_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14 Priviledge Attribution */
|
|
|
+ __IOM uint32_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15 Priviledge Attribution */
|
|
|
+ __IOM uint32_t ELSR16 : 1; /*!< [16..16] Event Link Setting Register 16 Priviledge Attribution */
|
|
|
+ __IOM uint32_t ELSR17 : 1; /*!< [17..17] Event Link Setting Register 17 Priviledge Attribution */
|
|
|
+ uint32_t : 12;
|
|
|
+ __IOM uint32_t ELSR30 : 1; /*!< [30..30] Event Link Setting Register 30 Priviledge Attribution */
|
|
|
+ uint32_t : 1;
|
|
|
+ } ELCPARB_b;
|
|
|
+ };
|
|
|
+} R_ELC_Type; /*!< Size = 248 (0xf8) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_ETHERC0 ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Ethernet MAC Controller (R_ETHERC0)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x40354100) R_ETHERC0 Structure */
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t ECMR; /*!< (@ 0x00000000) ETHERC Mode Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t PRM : 1; /*!< [0..0] Promiscuous Mode */
|
|
|
+ __IOM uint32_t DM : 1; /*!< [1..1] Duplex Mode */
|
|
|
+ __IOM uint32_t RTM : 1; /*!< [2..2] Bit Rate */
|
|
|
+ __IOM uint32_t ILB : 1; /*!< [3..3] Internal Loopback Mode */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t TE : 1; /*!< [5..5] Transmission Enable */
|
|
|
+ __IOM uint32_t RE : 1; /*!< [6..6] Reception Enable */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t MPDE : 1; /*!< [9..9] Magic Packet Detection Enable */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t PRCEF : 1; /*!< [12..12] CRC Error Frame Receive Mode */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t TXF : 1; /*!< [16..16] Transmit Flow Control Operating Mode */
|
|
|
+ __IOM uint32_t RXF : 1; /*!< [17..17] Receive Flow Control Operating Mode */
|
|
|
+ __IOM uint32_t PFR : 1; /*!< [18..18] PAUSE Frame Receive Mode */
|
|
|
+ __IOM uint32_t ZPF : 1; /*!< [19..19] 0 Time PAUSE Frame Enable */
|
|
|
+ __IOM uint32_t TPC : 1; /*!< [20..20] PAUSE Frame Transmit */
|
|
|
+ uint32_t : 11;
|
|
|
+ } ECMR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t RFLR; /*!< (@ 0x00000008) Receive Frame Maximum Length Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t RFL : 12; /*!< [11..0] Receive Frame Maximum LengthThe set value becomes the
|
|
|
+ * maximum frame length. The minimum value that can be set
|
|
|
+ * is 1,518 bytes, and the maximum value that can be set is
|
|
|
+ * 2,048 bytes. Values that are less than 1,518 bytes are
|
|
|
+ * regarded as 1,518 bytes, and values larger than 2,048 bytes
|
|
|
+ * are regarded as 2,048 bytes. */
|
|
|
+ uint32_t : 20;
|
|
|
+ } RFLR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED1;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t ECSR; /*!< (@ 0x00000010) ETHERC Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t ICD : 1; /*!< [0..0] False Carrier Detect Flag */
|
|
|
+ __IOM uint32_t MPD : 1; /*!< [1..1] Magic Packet Detect Flag */
|
|
|
+ __IOM uint32_t LCHNG : 1; /*!< [2..2] LCHNG Link Signal Change Flag */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t PSRTO : 1; /*!< [4..4] PAUSE Frame Retransmit Over Flag */
|
|
|
+ __IOM uint32_t BFR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Flag */
|
|
|
+ uint32_t : 26;
|
|
|
+ } ECSR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED2;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t ECSIPR; /*!< (@ 0x00000018) ETHERC Interrupt Enable Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t ICDIP : 1; /*!< [0..0] False Carrier Detect Interrupt Enable */
|
|
|
+ __IOM uint32_t MPDIP : 1; /*!< [1..1] Magic Packet Detect Interrupt Enable */
|
|
|
+ __IOM uint32_t LCHNGIP : 1; /*!< [2..2] LINK Signal Change Interrupt Enable */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t PSRTOIP : 1; /*!< [4..4] PAUSE Frame Retransmit Over Interrupt Enable */
|
|
|
+ __IOM uint32_t BFSIPR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Interrupt Enable */
|
|
|
+ uint32_t : 26;
|
|
|
+ } ECSIPR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED3;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t PIR; /*!< (@ 0x00000020) PHY Interface Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t MDC : 1; /*!< [0..0] MII/RMII Management Data ClockThe MDC bit value is output
|
|
|
+ * from the ETn_MDC pin to supply the management data clock
|
|
|
+ * to the MII or RMII. */
|
|
|
+ __IOM uint32_t MMD : 1; /*!< [1..1] MII/RMII Management Mode */
|
|
|
+ __IOM uint32_t MDO : 1; /*!< [2..2] MII/RMII Management Data-OutThe MDO bit value is output
|
|
|
+ * from the ETn_MDIO pin when the MMD bit is 1 (write). The
|
|
|
+ * value is not output when the MMD bit is 0 (read). */
|
|
|
+ __IM uint32_t MDI : 1; /*!< [3..3] MII/RMII Management Data-InThis bit indicates the level
|
|
|
+ * of the ETn_MDIO pin. The write value should be 0. */
|
|
|
+ uint32_t : 28;
|
|
|
+ } PIR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED4;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t PSR; /*!< (@ 0x00000028) PHY Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t LMON : 1; /*!< [0..0] ETn_LINKSTA Pin Status FlagThe link status can be read
|
|
|
+ * by connecting the link signal output from the PHY-LSI to
|
|
|
+ * the ETn_LINKSTA pin. For details on the polarity, refer
|
|
|
+ * to the specifications of the connected PHY-LSI. */
|
|
|
+ uint32_t : 31;
|
|
|
+ } PSR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED5[5];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t RDMLR; /*!< (@ 0x00000040) Random Number Generation Counter Upper Limit
|
|
|
+ * Setting Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t RMD : 20; /*!< [19..0] Random Number Generation Counter */
|
|
|
+ uint32_t : 12;
|
|
|
+ } RDMLR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED6[3];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t IPGR; /*!< (@ 0x00000050) IPG Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t IPG : 5; /*!< [4..0] Interpacket Gap Range:'16bit time(0x00)'-'140bit time(0x1F)' */
|
|
|
+ uint32_t : 27;
|
|
|
+ } IPGR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t APR; /*!< (@ 0x00000054) Automatic PAUSE Frame Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t AP : 16; /*!< [15..0] Automatic PAUSE Time SettingThese bits set the value
|
|
|
+ * of the pause_time parameter for a PAUSE frame that is automatically
|
|
|
+ * transmitted. Transmission is not performed until the set
|
|
|
+ * value multiplied by 512 bit time has elapsed. */
|
|
|
+ uint32_t : 16;
|
|
|
+ } APR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __OM uint32_t MPR; /*!< (@ 0x00000058) Manual PAUSE Frame Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __OM uint32_t MP : 16; /*!< [15..0] Manual PAUSE Time SettingThese bits set the value of
|
|
|
+ * the pause_time parameter for a PAUSE frame that is manually
|
|
|
+ * transmitted. Transmission is not performed until the set
|
|
|
+ * value multiplied by 512 bit time has elapsed. The read
|
|
|
+ * value is undefined. */
|
|
|
+ uint32_t : 16;
|
|
|
+ } MPR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED7;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t RFCF; /*!< (@ 0x00000060) Received PAUSE Frame Counter */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t RPAUSE : 8; /*!< [7..0] Received PAUSE Frame CountNumber of received PAUSE frames */
|
|
|
+ uint32_t : 24;
|
|
|
+ } RFCF_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t TPAUSER; /*!< (@ 0x00000064) PAUSE Frame Retransmit Count Setting Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t TPAUSE : 16; /*!< [15..0] Automatic PAUSE Frame Retransmit Setting */
|
|
|
+ uint32_t : 16;
|
|
|
+ } TPAUSER_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t TPAUSECR; /*!< (@ 0x00000068) PAUSE Frame Retransmit Counter */
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t BCFRR; /*!< (@ 0x0000006C) Broadcast Frame Receive Count Setting Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t BCF : 16; /*!< [15..0] Broadcast Frame Continuous Receive Count Setting */
|
|
|
+ uint32_t : 16;
|
|
|
+ } BCFRR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED8[20];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t MAHR; /*!< (@ 0x000000C0) MAC Address Upper Bit Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t MAHR : 32; /*!< [31..0] MAC Address Upper Bit RegisterThe MAHR register sets
|
|
|
+ * the upper 32 bits (b47 to b16) of the 48-bit MAC address. */
|
|
|
+ } MAHR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED9;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t MALR; /*!< (@ 0x000000C8) MAC Address Lower Bit Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t MALR : 16; /*!< [15..0] MAC Address Lower Bit RegisterThe MALR register sets
|
|
|
+ * the lower 16 bits of the 48-bit MAC address. */
|
|
|
+ uint32_t : 16;
|
|
|
+ } MALR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED10;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t TROCR; /*!< (@ 0x000000D0) Transmit Retry Over Counter Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t TROCR : 32; /*!< [31..0] Transmit Retry Over Counter RegisterThe TROCR register
|
|
|
+ * is a counter indicating the number of frames that fail
|
|
|
+ * to be retransmitted. */
|
|
|
+ } TROCR_b;
|
|
|
+ };
|
|
|
+ __IOM uint32_t CDCR; /*!< (@ 0x000000D4) Late Collision Detect Counter Register */
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t LCCR; /*!< (@ 0x000000D8) Lost Carrier Counter Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t LCCR : 32; /*!< [31..0] Lost Carrier Counter RegisterThe LCCR register is a
|
|
|
+ * counter indicating the number of times a loss of carrier
|
|
|
+ * is detected during frame transmission. */
|
|
|
+ } LCCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CNDCR; /*!< (@ 0x000000DC) Carrier Not Detect Counter Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CNDCR : 32; /*!< [31..0] Carrier Not Detect Counter RegisterThe CNDCR register
|
|
|
+ * is a counter indicating the number of times a carrier is
|
|
|
+ * not detected during preamble transmission. */
|
|
|
+ } CNDCR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED11;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CEFCR; /*!< (@ 0x000000E4) CRC Error Frame Receive Counter Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CEFCR : 32; /*!< [31..0] CRC Error Frame Receive Counter RegisterThe CEFCR register
|
|
|
+ * is a counter indicating the number of received frames where
|
|
|
+ * a CRC error has been detected. */
|
|
|
+ } CEFCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t FRECR; /*!< (@ 0x000000E8) Frame Receive Error Counter Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t FRECR : 32; /*!< [31..0] Frame Receive Error Counter RegisterThe FRECR register
|
|
|
+ * is a counter indicating the number of times a frame receive
|
|
|
+ * error has occurred. */
|
|
|
+ } FRECR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t TSFRCR; /*!< (@ 0x000000EC) Too-Short Frame Receive Counter Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t TSFRCR : 32; /*!< [31..0] Too-Short Frame Receive Counter RegisterThe TSFRCR register
|
|
|
+ * is a counter indicating the number of times a short frame
|
|
|
+ * that is shorter than 64 bytes has been received. */
|
|
|
+ } TSFRCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t TLFRCR; /*!< (@ 0x000000F0) Too-Long Frame Receive Counter Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t TLFRCR : 32; /*!< [31..0] Too-Long Frame Receive Counter RegisterThe TLFRCR register
|
|
|
+ * is a counter indicating the number of times a long frame
|
|
|
+ * that is longer than the RFLR register value has been received. */
|
|
|
+ } TLFRCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t RFCR; /*!< (@ 0x000000F4) Received Alignment Error Frame Counter Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t RFCR : 32; /*!< [31..0] Received Alignment Error Frame Counter RegisterThe RFCR
|
|
|
+ * register is a counter indicating the number of times a
|
|
|
+ * frame has been received with the alignment error (frame
|
|
|
+ * is not an integral number of octets). */
|
|
|
+ } RFCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t MAFCR; /*!< (@ 0x000000F8) Multicast Address Frame Receive Counter Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t MAFCR : 32; /*!< [31..0] Multicast Address Frame Receive Counter RegisterThe
|
|
|
+ * MAFCR register is a counter indicating the number of times
|
|
|
+ * a frame where the multicast address is set has been received. */
|
|
|
+ } MAFCR_b;
|
|
|
+ };
|
|
|
+} R_ETHERC0_Type; /*!< Size = 252 (0xfc) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_ETHERC_EDMAC ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Ethernet DMA Controller (R_ETHERC_EDMAC)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x40354000) R_ETHERC_EDMAC Structure */
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t EDMR; /*!< (@ 0x00000000) EDMAC Mode Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __OM uint32_t SWR : 1; /*!< [0..0] Software Reset */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t DL : 2; /*!< [5..4] Transmit/Receive DescriptorLength */
|
|
|
+ __IOM uint32_t DE : 1; /*!< [6..6] Big Endian Mode/Little Endian ModeNOTE: This setting
|
|
|
+ * applies to data for the transmit/receive buffer. It does
|
|
|
+ * not apply to transmit/receive descriptors and registers. */
|
|
|
+ uint32_t : 25;
|
|
|
+ } EDMR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t EDTRR; /*!< (@ 0x00000008) EDMAC Transmit Request Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __OM uint32_t TR : 1; /*!< [0..0] Transmit Request */
|
|
|
+ uint32_t : 31;
|
|
|
+ } EDTRR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED1;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t EDRRR; /*!< (@ 0x00000010) EDMAC Receive Request Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t RR : 1; /*!< [0..0] Receive Request */
|
|
|
+ uint32_t : 31;
|
|
|
+ } EDRRR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED2;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t TDLAR; /*!< (@ 0x00000018) Transmit Descriptor List Start Address Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t TDLAR : 32; /*!< [31..0] The start address of the transmit descriptor list is
|
|
|
+ * set. Set the start address according to the descriptor
|
|
|
+ * length selected by the EDMR.DL[1:0] bits.16-byte boundary:
|
|
|
+ * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte
|
|
|
+ * boundary: Lower 6 bits = 000000b */
|
|
|
+ } TDLAR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED3;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t RDLAR; /*!< (@ 0x00000020) Receive Descriptor List Start Address Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t RDLAR : 32; /*!< [31..0] The start address of the receive descriptor list is
|
|
|
+ * set. Set the start address according to the descriptor
|
|
|
+ * length selected by the EDMR.DL[1:0] bits.16-byte boundary:
|
|
|
+ * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte
|
|
|
+ * boundary: Lower 6 bits = 000000b */
|
|
|
+ } RDLAR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED4;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t EESR; /*!< (@ 0x00000028) ETHERC/EDMAC Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CERF : 1; /*!< [0..0] CRC Error Flag */
|
|
|
+ __IOM uint32_t PRE : 1; /*!< [1..1] PHY-LSI Receive Error Flag */
|
|
|
+ __IOM uint32_t RTSF : 1; /*!< [2..2] Frame-Too-Short Error Flag */
|
|
|
+ __IOM uint32_t RTLF : 1; /*!< [3..3] Frame-Too-Long Error Flag */
|
|
|
+ __IOM uint32_t RRF : 1; /*!< [4..4] Alignment Error Flag */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t RMAF : 1; /*!< [7..7] Multicast Address Frame Receive Flag */
|
|
|
+ __IOM uint32_t TRO : 1; /*!< [8..8] Transmit Retry Over Flag */
|
|
|
+ __IOM uint32_t CD : 1; /*!< [9..9] Late Collision Detect Flag */
|
|
|
+ __IOM uint32_t DLC : 1; /*!< [10..10] Loss of Carrier Detect Flag */
|
|
|
+ __IOM uint32_t CND : 1; /*!< [11..11] Carrier Not Detect Flag */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t RFOF : 1; /*!< [16..16] Receive FIFO Overflow Flag */
|
|
|
+ __IOM uint32_t RDE : 1; /*!< [17..17] Receive Descriptor Empty Flag */
|
|
|
+ __IOM uint32_t FR : 1; /*!< [18..18] Frame Receive Flag */
|
|
|
+ __IOM uint32_t TFUF : 1; /*!< [19..19] Transmit FIFO Underflow Flag */
|
|
|
+ __IOM uint32_t TDE : 1; /*!< [20..20] Transmit Descriptor Empty Flag */
|
|
|
+ __IOM uint32_t TC : 1; /*!< [21..21] Frame Transfer Complete Flag */
|
|
|
+ __IM uint32_t ECI : 1; /*!< [22..22] ETHERC Status Register Source FlagNOTE: When the source
|
|
|
+ * in the ETHERCn.ECSR register is cleared, the ECI flag is
|
|
|
+ * also cleared. */
|
|
|
+ __IOM uint32_t ADE : 1; /*!< [23..23] Address Error Flag */
|
|
|
+ __IOM uint32_t RFCOF : 1; /*!< [24..24] Receive Frame Counter Overflow Flag */
|
|
|
+ __IOM uint32_t RABT : 1; /*!< [25..25] Receive Abort Detect Flag */
|
|
|
+ __IOM uint32_t TABT : 1; /*!< [26..26] Transmit Abort Detect Flag */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t TWB : 1; /*!< [30..30] Write-Back Complete Flag */
|
|
|
+ uint32_t : 1;
|
|
|
+ } EESR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED5;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t EESIPR; /*!< (@ 0x00000030) ETHERC/EDMAC Status Interrupt Enable Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CERFIP : 1; /*!< [0..0] CRC Error Interrupt Request Enable */
|
|
|
+ __IOM uint32_t PREIP : 1; /*!< [1..1] PHY-LSI Receive Error Interrupt Request Enable */
|
|
|
+ __IOM uint32_t RTSFIP : 1; /*!< [2..2] Frame-Too-Short Error Interrupt Request Enable */
|
|
|
+ __IOM uint32_t RTLFIP : 1; /*!< [3..3] Frame-Too-Long Error Interrupt Request Enable */
|
|
|
+ __IOM uint32_t RRFIP : 1; /*!< [4..4] Alignment Error Interrupt Request Enable */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t RMAFIP : 1; /*!< [7..7] Multicast Address Frame Receive Interrupt Request Enable */
|
|
|
+ __IOM uint32_t TROIP : 1; /*!< [8..8] Transmit Retry Over Interrupt Request Enable */
|
|
|
+ __IOM uint32_t CDIP : 1; /*!< [9..9] Late Collision Detect Interrupt Request Enable */
|
|
|
+ __IOM uint32_t DLCIP : 1; /*!< [10..10] Loss of Carrier Detect Interrupt Request Enable */
|
|
|
+ __IOM uint32_t CNDIP : 1; /*!< [11..11] Carrier Not Detect Interrupt Request Enable */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t RFOFIP : 1; /*!< [16..16] Receive FIFO Overflow Interrupt Request Enable */
|
|
|
+ __IOM uint32_t RDEIP : 1; /*!< [17..17] Receive Descriptor Empty Interrupt Request Enable */
|
|
|
+ __IOM uint32_t FRIP : 1; /*!< [18..18] Frame Receive Interrupt Request Enable */
|
|
|
+ __IOM uint32_t TFUFIP : 1; /*!< [19..19] Transmit FIFO Underflow Interrupt Request Enable */
|
|
|
+ __IOM uint32_t TDEIP : 1; /*!< [20..20] Transmit Descriptor Empty Interrupt Request Enable */
|
|
|
+ __IOM uint32_t TCIP : 1; /*!< [21..21] Frame Transfer Complete Interrupt Request Enable */
|
|
|
+ __IOM uint32_t ECIIP : 1; /*!< [22..22] ETHERC Status Register Source Interrupt Request Enable */
|
|
|
+ __IOM uint32_t ADEIP : 1; /*!< [23..23] Address Error Interrupt Request Enable */
|
|
|
+ __IOM uint32_t RFCOFIP : 1; /*!< [24..24] Receive Frame Counter Overflow Interrupt Request Enable */
|
|
|
+ __IOM uint32_t RABTIP : 1; /*!< [25..25] Receive Abort Detect Interrupt Request Enable */
|
|
|
+ __IOM uint32_t TABTIP : 1; /*!< [26..26] Transmit Abort Detect Interrupt Request Enable */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t TWBIP : 1; /*!< [30..30] Write-Back Complete Interrupt Request Enable */
|
|
|
+ uint32_t : 1;
|
|
|
+ } EESIPR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED6;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t TRSCER; /*!< (@ 0x00000038) ETHERC/EDMAC Transmit/Receive Status Copy Enable
|
|
|
+ * Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t RRFCE : 1; /*!< [4..4] RRF Flag Copy Enable */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t RMAFCE : 1; /*!< [7..7] RMAF Flag Copy Enable */
|
|
|
+ uint32_t : 24;
|
|
|
+ } TRSCER_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED7;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t RMFCR; /*!< (@ 0x00000040) Missed-Frame Counter Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t MFC : 16; /*!< [15..0] Missed-Frame CounterThese bits indicate the number of
|
|
|
+ * frames that are discarded and not transferred to the receive
|
|
|
+ * buffer during reception. */
|
|
|
+ uint32_t : 16;
|
|
|
+ } RMFCR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED8;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t TFTR; /*!< (@ 0x00000048) Transmit FIFO Threshold Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t TFT : 11; /*!< [10..0] Transmit FIFO Threshold00Dh to 200h: The threshold is
|
|
|
+ * the set value multiplied by 4. Example: 00Dh: 52 bytes
|
|
|
+ * 040h: 256 bytes 100h: 1024 bytes 200h: 2048 bytes */
|
|
|
+ uint32_t : 21;
|
|
|
+ } TFTR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED9;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t FDR; /*!< (@ 0x00000050) Transmit FIFO Threshold Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t RFD : 5; /*!< [4..0] Transmit FIFO Depth */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t TFD : 5; /*!< [12..8] Receive FIFO Depth */
|
|
|
+ uint32_t : 19;
|
|
|
+ } FDR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED10;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t RMCR; /*!< (@ 0x00000058) Receive Method Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t RNR : 1; /*!< [0..0] Receive Request Reset */
|
|
|
+ uint32_t : 31;
|
|
|
+ } RMCR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED11[2];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t TFUCR; /*!< (@ 0x00000064) Transmit FIFO Underflow Counter */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t UNDER : 16; /*!< [15..0] Transmit FIFO Underflow CountThese bits indicate how
|
|
|
+ * many times the transmit FIFO has underflowed. The counter
|
|
|
+ * stops when the counter value reaches FFFFh. */
|
|
|
+ uint32_t : 16;
|
|
|
+ } TFUCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t RFOCR; /*!< (@ 0x00000068) Receive FIFO Overflow Counter */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t OVER : 16; /*!< [15..0] Receive FIFO Overflow CountThese bits indicate how many
|
|
|
+ * times the receive FIFO has overflowed. The counter stops
|
|
|
+ * when the counter value reaches FFFFh. */
|
|
|
+ uint32_t : 16;
|
|
|
+ } RFOCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t IOSR; /*!< (@ 0x0000006C) Independent Output Signal Setting Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t ELB : 1; /*!< [0..0] External Loopback Mode */
|
|
|
+ uint32_t : 31;
|
|
|
+ } IOSR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t FCFTR; /*!< (@ 0x00000070) Flow Control Start FIFO Threshold Setting Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t RFDO : 3; /*!< [2..0] Receive FIFO Data PAUSE Output Threshold(When (RFDO+1)x256-32
|
|
|
+ * bytes of data is stored in the receive FIFO.) */
|
|
|
+ uint32_t : 13;
|
|
|
+ __IOM uint32_t RFFO : 3; /*!< [18..16] Receive FIFO Frame PAUSE Output Threshold(When ((RFFO+1)x2)
|
|
|
+ * receive frames have been stored in the receive FIFO.) */
|
|
|
+ uint32_t : 13;
|
|
|
+ } FCFTR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED12;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t RPADIR; /*!< (@ 0x00000078) Receive Data Padding Insert Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t PADR : 6; /*!< [5..0] Padding Slot */
|
|
|
+ uint32_t : 10;
|
|
|
+ __IOM uint32_t PADS : 2; /*!< [17..16] Padding Size */
|
|
|
+ uint32_t : 14;
|
|
|
+ } RPADIR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t TRIMD; /*!< (@ 0x0000007C) Transmit Interrupt Setting Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t TIS : 1; /*!< [0..0] Transmit Interrupt EnableSet the EESR.TWB flag to 1 in
|
|
|
+ * the mode selected by the TIM bit to notify an interrupt. */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t TIM : 1; /*!< [4..4] Transmit Interrupt Mode */
|
|
|
+ uint32_t : 27;
|
|
|
+ } TRIMD_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED13[18];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t RBWAR; /*!< (@ 0x000000C8) Receive Buffer Write Address Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t RBWAR : 32; /*!< [31..0] Receive Buffer Write Address RegisterThe RBWAR register
|
|
|
+ * indicates the last address that the EDMAC has written data
|
|
|
+ * to when writing to the receive buffer.Refer to the address
|
|
|
+ * indicated by the RBWAR register to recognize which address
|
|
|
+ * in the receive buffer the EDMAC is writing data to. Note
|
|
|
+ * that the address that the EDMAC is outputting to the receive
|
|
|
+ * buffer may not match the read value of the RBWAR register
|
|
|
+ * during data reception. */
|
|
|
+ } RBWAR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t RDFAR; /*!< (@ 0x000000CC) Receive Descriptor Fetch Address Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t RDFAR : 32; /*!< [31..0] Receive Descriptor Fetch Address RegisterThe RDFAR register
|
|
|
+ * indicates the start address of the last fetched receive
|
|
|
+ * descriptor when the EDMAC fetches descriptor information
|
|
|
+ * from the receive descriptor.Refer to the address indicated
|
|
|
+ * by the RDFAR register to recognize which receive descriptor
|
|
|
+ * information the EDMAC is using for the current processing.
|
|
|
+ * Note that the address of the receive descriptor that the
|
|
|
+ * EDMAC fetches may not match the read value of the RDFAR
|
|
|
+ * register during data reception. */
|
|
|
+ } RDFAR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED14;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t TBRAR; /*!< (@ 0x000000D4) Transmit Buffer Read Address Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t TBRAR : 32; /*!< [31..0] Transmit Buffer Read Address RegisterThe TBRAR register
|
|
|
+ * indicates the last address that the EDMAC has read data
|
|
|
+ * from when reading data from the transmit buffer.Refer to
|
|
|
+ * the address indicated by the TBRAR register to recognize
|
|
|
+ * which address in the transmit buffer the EDMAC is reading
|
|
|
+ * from. Note that the address that the EDMAC is outputting
|
|
|
+ * to the transmit buffer may not match the read value of
|
|
|
+ * the TBRAR register. */
|
|
|
+ } TBRAR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t TDFAR; /*!< (@ 0x000000D8) Transmit Descriptor Fetch Address Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t TDFAR : 32; /*!< [31..0] Transmit Descriptor Fetch Address RegisterThe TDFAR
|
|
|
+ * register indicates the start address of the last fetched
|
|
|
+ * transmit descriptor when the EDMAC fetches descriptor information
|
|
|
+ * from the transmit descriptor.Refer to the address indicated
|
|
|
+ * by the TDFAR register to recognize which transmit descriptor
|
|
|
+ * information the EDMAC is using for the current processing.
|
|
|
+ * Note that the address of the transmit descriptor that the
|
|
|
+ * EDMAC fetches may not match the read value of the TDFAR
|
|
|
+ * register. */
|
|
|
+ } TDFAR_b;
|
|
|
+ };
|
|
|
+} R_ETHERC_EDMAC_Type; /*!< Size = 220 (0xdc) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_FACI_HP_CMD ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x40100000) R_FACI_HP_CMD Structure */
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t FACI_CMD16; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */
|
|
|
+ __IOM uint8_t FACI_CMD8; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */
|
|
|
+ };
|
|
|
+} R_FACI_HP_CMD_Type; /*!< Size = 2 (0x2) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_FACI_HP ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Flash Application Command Interface (R_FACI_HP)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x4011E000) R_FACI_HP Structure */
|
|
|
+{
|
|
|
+ __IM uint32_t RESERVED[4];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t FASTAT; /*!< (@ 0x00000010) Flash Access Status */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint8_t : 3;
|
|
|
+ __IOM uint8_t DFAE : 1; /*!< [3..3] Data Flash Access Error */
|
|
|
+ __IM uint8_t CMDLK : 1; /*!< [4..4] Command Lock */
|
|
|
+ uint8_t : 2;
|
|
|
+ __IOM uint8_t CFAE : 1; /*!< [7..7] Code Flash Access Error */
|
|
|
+ } FASTAT_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED1;
|
|
|
+ __IM uint16_t RESERVED2;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t FAEINT; /*!< (@ 0x00000014) Flash Access Error Interrupt Enable */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint8_t : 3;
|
|
|
+ __IOM uint8_t DFAEIE : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable */
|
|
|
+ __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable */
|
|
|
+ uint8_t : 2;
|
|
|
+ __IOM uint8_t CFAEIE : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable */
|
|
|
+ } FAEINT_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED3;
|
|
|
+ __IM uint16_t RESERVED4;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t FRDYIE; /*!< (@ 0x00000018) Flash Ready Interrupt Enable */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t FRDYIE : 1; /*!< [0..0] FRDY Interrupt Enable */
|
|
|
+ uint8_t : 7;
|
|
|
+ } FRDYIE_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED5;
|
|
|
+ __IM uint16_t RESERVED6;
|
|
|
+ __IM uint32_t RESERVED7[5];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t FSADDR; /*!< (@ 0x00000030) Flash Start Address */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t FSA : 32; /*!< [31..0] Start Address of Flash Sequencer Command Target Area
|
|
|
+ * These bits can be written when FRDY bit of FSTATR register
|
|
|
+ * is '1'. Writing to these bits in FRDY = '0' is ignored. */
|
|
|
+ } FSADDR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t FEADDR; /*!< (@ 0x00000034) Flash End Address */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t FEA : 32; /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies
|
|
|
+ * end address of target area in 'Blank Check' command. These
|
|
|
+ * bits can be written when FRDY bit of FSTATR register is
|
|
|
+ * '1'. Writing to these bits in FRDY = '0' is ignored. */
|
|
|
+ } FEADDR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED8[3];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t FMEPROT; /*!< (@ 0x00000044) Flash P/E Mode Entry Protection Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t CEPROT : 1; /*!< [0..0] Code Flash P/E Mode Entry ProtectionWriting to this bit
|
|
|
+ * is only possible when the FRDY bit in the FSTATR register
|
|
|
+ * is 1. Writing to this bit while the FRDY bit = 0 isignored.Writing
|
|
|
+ * to this bit is only possible when 16 bits are written and
|
|
|
+ * the value written to the KEY bits is D9h.Written values
|
|
|
+ * are not retained by these bits (always read as 0x00).Only
|
|
|
+ * secure access can write to this register. Both secure access
|
|
|
+ * and non-secure read access are allowed. Non-secure writeaccess
|
|
|
+ * is denied, but TrustZo */
|
|
|
+ uint16_t : 7;
|
|
|
+ __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */
|
|
|
+ } FMEPROT_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED9;
|
|
|
+ __IM uint32_t RESERVED10[12];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t FBPROT0; /*!< (@ 0x00000078) Flash Block Protection Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t BPCN0 : 1; /*!< [0..0] Block Protection for Non-secure CancelThis bit can be
|
|
|
+ * written when the FRDY bit in the FSTATR register is 1.
|
|
|
+ * Writing to this bit is ignored when the FRDY bit is 0.Writing
|
|
|
+ * to this bit is only possible when 16 bits are written and
|
|
|
+ * the value written to the KEY[7:0] bits is 0x78.Written
|
|
|
+ * values are not retained by these bits (always read as 0x00). */
|
|
|
+ uint16_t : 7;
|
|
|
+ __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */
|
|
|
+ } FBPROT0_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED11;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t FBPROT1; /*!< (@ 0x0000007C) Flash Block Protection for Secure Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t BPCN1 : 1; /*!< [0..0] Block Protection for Secure CancelWriting to this bit
|
|
|
+ * is only possible when the FRDY bit in the FSTATR register
|
|
|
+ * is 1. Writing to this bit while FRDY bit = 0 is ignored.Writing
|
|
|
+ * to this bit is only possible when 16 bits are written and
|
|
|
+ * the value written to the KEY[7:0] bits is 0xB1.Written
|
|
|
+ * values are not retained by these bits (always read as 0x00). */
|
|
|
+ uint16_t : 7;
|
|
|
+ __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */
|
|
|
+ } FBPROT1_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED12;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t FSTATR; /*!< (@ 0x00000080) Flash Status */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 6;
|
|
|
+ __IM uint32_t FLWEERR : 1; /*!< [6..6] Flash Write/Erase Protect Error Flag */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IM uint32_t PRGSPD : 1; /*!< [8..8] Programming-Suspended Status */
|
|
|
+ __IM uint32_t ERSSPD : 1; /*!< [9..9] Erasure-Suspended Status */
|
|
|
+ __IM uint32_t DBFULL : 1; /*!< [10..10] Data Buffer Full */
|
|
|
+ __IM uint32_t SUSRDY : 1; /*!< [11..11] Suspend Ready */
|
|
|
+ __IM uint32_t PRGERR : 1; /*!< [12..12] Programming Error */
|
|
|
+ __IM uint32_t ERSERR : 1; /*!< [13..13] Erasure Error */
|
|
|
+ __IM uint32_t ILGLERR : 1; /*!< [14..14] Illegal Command Error */
|
|
|
+ __IM uint32_t FRDY : 1; /*!< [15..15] Flash Ready */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IM uint32_t OTERR : 1; /*!< [20..20] Other Error */
|
|
|
+ __IOM uint32_t SECERR : 1; /*!< [21..21] Security Error */
|
|
|
+ __IM uint32_t FESETERR : 1; /*!< [22..22] FENTRY Setting Error */
|
|
|
+ __IM uint32_t ILGCOMERR : 1; /*!< [23..23] Illegal Command Error */
|
|
|
+ uint32_t : 8;
|
|
|
+ } FSTATR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t FENTRYR; /*!< (@ 0x00000084) Program/Erase Mode Entry */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when
|
|
|
+ * FRDY bit in FSTATR register is '1'. Writing to this bit
|
|
|
+ * in FRDY = '0' is ignored. Writing to these bits is enabled
|
|
|
+ * only when this register is accessed in 16-bit size and
|
|
|
+ * H'AA is written to KEY bits */
|
|
|
+ uint16_t : 6;
|
|
|
+ __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when
|
|
|
+ * FRDY bit in FSTATR register is '1'. Writing to this bit
|
|
|
+ * in FRDY = '0' is ignored. Writing to these bits is enabled
|
|
|
+ * only when this register is accessed in 16-bit size and
|
|
|
+ * H'AA is written to KEY bits. */
|
|
|
+ __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */
|
|
|
+ } FENTRYR_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED13;
|
|
|
+ __IM uint32_t RESERVED14;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t FSUINITR; /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY
|
|
|
+ * bit of FSTATR register is '1'. Writing to this bit in FRDY
|
|
|
+ * = '0' is ignored. Writing to these bits is enabled only
|
|
|
+ * when this register is accessed in 16-bit size and H'2D
|
|
|
+ * is written to KEY bits. */
|
|
|
+ uint16_t : 7;
|
|
|
+ __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */
|
|
|
+ } FSUINITR_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED15;
|
|
|
+ __IM uint32_t RESERVED16[4];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint16_t FCMDR; /*!< (@ 0x000000A0) Flash Sequencer Command */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t PCMDR : 8; /*!< [7..0] Previous Command Register */
|
|
|
+ __IM uint16_t CMDR : 8; /*!< [15..8] Command Register */
|
|
|
+ } FCMDR_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED17;
|
|
|
+ __IM uint32_t RESERVED18[11];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t FBCCNT; /*!< (@ 0x000000D0) Blank Check Control */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t BCDIR : 1; /*!< [0..0] Blank Check Direction */
|
|
|
+ uint8_t : 7;
|
|
|
+ } FBCCNT_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED19;
|
|
|
+ __IM uint16_t RESERVED20;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint8_t FBCSTAT; /*!< (@ 0x000000D4) Blank Check Status */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint8_t BCST : 1; /*!< [0..0] Blank Check Status Bit */
|
|
|
+ uint8_t : 7;
|
|
|
+ } FBCSTAT_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED21;
|
|
|
+ __IM uint16_t RESERVED22;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t FPSADDR; /*!< (@ 0x000000D8) Programmed Area Start Address */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t PSADR : 19; /*!< [18..0] Programmed Area Start Address NOTE: Indicates address
|
|
|
+ * of the first programmed data which is found in 'Blank Check'
|
|
|
+ * command execution. */
|
|
|
+ uint32_t : 13;
|
|
|
+ } FPSADDR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t FAWMON; /*!< (@ 0x000000DC) Flash Access Window Monitor */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t FAWS : 11; /*!< [10..0] Start Sector Address for Access Window NOTE: These bits
|
|
|
+ * indicate the start sector address for setting the access
|
|
|
+ * window that is located in the configuration area. */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IM uint32_t FSPR : 1; /*!< [15..15] Protection Flag of programming the Access Window, Boot
|
|
|
+ * Flag and Temporary Boot Swap Control and 'Config Clear'
|
|
|
+ * command execution */
|
|
|
+ __IM uint32_t FAWE : 11; /*!< [26..16] End Sector Address for Access Window NOTE: These bits
|
|
|
+ * indicate the end sector address for setting the access
|
|
|
+ * window that is located in the configuration area. */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IM uint32_t BTFLG : 1; /*!< [31..31] Flag of Start-Up area select for Boot Swap */
|
|
|
+ } FAWMON_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t FCPSR; /*!< (@ 0x000000E0) FCU Process Switch */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode */
|
|
|
+ uint16_t : 15;
|
|
|
+ } FCPSR_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED23;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t FPCKAR; /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t PCKA : 8; /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits
|
|
|
+ * can be written when FRDY bit in FSTATR register is '1'.
|
|
|
+ * Writing to this bit in FRDY = '0' is ignored. Writing to
|
|
|
+ * these bits is enabled only when this register is accessed
|
|
|
+ * in 16-bit size and H'1E is written to KEY bits. */
|
|
|
+ __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */
|
|
|
+ } FPCKAR_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED24;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t FSUACR; /*!< (@ 0x000000E8) Flash Start-Up Area Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t SAS : 2; /*!< [1..0] Start Up Area Select These bits can be written when FRDY
|
|
|
+ * bit in FSTATR register is '1'. Writing to this bit in FRDY
|
|
|
+ * = '0' is ignored. Writing to these bits is enabled only
|
|
|
+ * when this register is accessed in 16-bit size and H'66
|
|
|
+ * is written to KEY bits. */
|
|
|
+ uint16_t : 6;
|
|
|
+ __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */
|
|
|
+ } FSUACR_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED25;
|
|
|
+} R_FACI_HP_Type; /*!< Size = 236 (0xec) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_FCACHE ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Flash Cache (R_FCACHE)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x4001C100) R_FCACHE Structure */
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t FCACHEE; /*!< (@ 0x00000000) Flash Cache Enable Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t FCACHEEN : 1; /*!< [0..0] Flash Cache Enable */
|
|
|
+ uint16_t : 15;
|
|
|
+ } FCACHEE_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t FCACHEIV; /*!< (@ 0x00000004) Flash Cache Invalidate Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate */
|
|
|
+ uint16_t : 15;
|
|
|
+ } FCACHEIV_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED1[11];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t FLWT; /*!< (@ 0x0000001C) Flash Wait Cycle Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t FLWT : 3; /*!< [2..0] Flash Wait Cycle */
|
|
|
+ uint8_t : 5;
|
|
|
+ } FLWT_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED2;
|
|
|
+ __IM uint16_t RESERVED3[17];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t FSAR; /*!< (@ 0x00000040) Flash Security Attribution Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */
|
|
|
+ __IOM uint16_t FCACHEENSA : 1; /*!< [1..1] FCHACHEEN Security Attribution */
|
|
|
+ uint16_t : 6;
|
|
|
+ __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */
|
|
|
+ __IOM uint16_t FACICOMISA : 1; /*!< [9..9] FACI command Issuing Security Attribution */
|
|
|
+ __IOM uint16_t FACICOMRSA : 1; /*!< [10..10] FACI command Registers Security Attribution */
|
|
|
+ __IOM uint16_t FACITRSA : 1; /*!< [11..11] FACI transfer Security Attribution */
|
|
|
+ uint16_t : 4;
|
|
|
+ } FSAR_b;
|
|
|
+ };
|
|
|
+} R_FCACHE_Type; /*!< Size = 66 (0x42) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_GPT0 ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief General PWM Timer (R_GPT0)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x40322000) R_GPT0 Structure */
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */
|
|
|
+ __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */
|
|
|
+ __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */
|
|
|
+ __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */
|
|
|
+ __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */
|
|
|
+ uint32_t : 3;
|
|
|
+ __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */
|
|
|
+ uint32_t : 16;
|
|
|
+ } GTWP_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
|
|
|
+ * means counter running. */
|
|
|
+ __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
|
|
|
+ * means counter running. */
|
|
|
+ __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
|
|
|
+ * means counter running. */
|
|
|
+ __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
|
|
|
+ * means counter running. */
|
|
|
+ __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
|
|
|
+ * means counter running. */
|
|
|
+ __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
|
|
|
+ * means counter running. */
|
|
|
+ __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
|
|
|
+ * means counter running. */
|
|
|
+ __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
|
|
|
+ * means counter running. */
|
|
|
+ __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
|
|
|
+ * means counter running. */
|
|
|
+ __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
|
|
|
+ * means counter running. */
|
|
|
+ __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
|
|
|
+ * means counter running. */
|
|
|
+ __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
|
|
|
+ * means counter running. */
|
|
|
+ __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
|
|
|
+ * means counter running. */
|
|
|
+ __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
|
|
|
+ * means counter running. */
|
|
|
+ __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
|
|
|
+ * means counter running. */
|
|
|
+ __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
|
|
|
+ * means counter running. */
|
|
|
+ __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
|
|
|
+ * means counter running. */
|
|
|
+ __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
|
|
|
+ * means counter running. */
|
|
|
+ __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
|
|
|
+ * means counter running. */
|
|
|
+ __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
|
|
|
+ * means counter running. */
|
|
|
+ __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
|
|
|
+ * means counter running. */
|
|
|
+ __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
|
|
|
+ * means counter running. */
|
|
|
+ __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
|
|
|
+ * means counter running. */
|
|
|
+ __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
|
|
|
+ * means counter running. */
|
|
|
+ __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
|
|
|
+ * means counter running. */
|
|
|
+ __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
|
|
|
+ * means counter running. */
|
|
|
+ __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
|
|
|
+ * means counter running. */
|
|
|
+ __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
|
|
|
+ * means counter running. */
|
|
|
+ __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
|
|
|
+ * means counter running. */
|
|
|
+ __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
|
|
|
+ * means counter running. */
|
|
|
+ __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
|
|
|
+ * means counter running. */
|
|
|
+ __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter stop. 1
|
|
|
+ * means counter running. */
|
|
|
+ } GTSTR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter runnning.
|
|
|
+ * 1 means counter stop. */
|
|
|
+ __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter runnning.
|
|
|
+ * 1 means counter stop. */
|
|
|
+ __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter runnning.
|
|
|
+ * 1 means counter stop. */
|
|
|
+ __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter runnning.
|
|
|
+ * 1 means counter stop. */
|
|
|
+ __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter runnning.
|
|
|
+ * 1 means counter stop. */
|
|
|
+ __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter runnning.
|
|
|
+ * 1 means counter stop. */
|
|
|
+ __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter runnning.
|
|
|
+ * 1 means counter stop. */
|
|
|
+ __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter runnning.
|
|
|
+ * 1 means counter stop. */
|
|
|
+ __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter runnning.
|
|
|
+ * 1 means counter stop. */
|
|
|
+ __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter runnning.
|
|
|
+ * 1 means counter stop. */
|
|
|
+ __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter runnning.
|
|
|
+ * 1 means counter stop. */
|
|
|
+ __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter runnning.
|
|
|
+ * 1 means counter stop. */
|
|
|
+ __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter runnning.
|
|
|
+ * 1 means counter stop. */
|
|
|
+ __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter runnning.
|
|
|
+ * 1 means counter stop. */
|
|
|
+ __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter runnning.
|
|
|
+ * 1 means counter stop. */
|
|
|
+ __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter runnning.
|
|
|
+ * 1 means counter stop. */
|
|
|
+ __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter runnning.
|
|
|
+ * 1 means counter stop. */
|
|
|
+ __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter runnning.
|
|
|
+ * 1 means counter stop. */
|
|
|
+ __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter runnning.
|
|
|
+ * 1 means counter stop. */
|
|
|
+ __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter runnning.
|
|
|
+ * 1 means counter stop. */
|
|
|
+ __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter runnning.
|
|
|
+ * 1 means counter stop. */
|
|
|
+ __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter runnning.
|
|
|
+ * 1 means counter stop. */
|
|
|
+ __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter runnning.
|
|
|
+ * 1 means counter stop. */
|
|
|
+ __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter runnning.
|
|
|
+ * 1 means counter stop. */
|
|
|
+ __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter runnning.
|
|
|
+ * 1 means counter stop. */
|
|
|
+ __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter runnning.
|
|
|
+ * 1 means counter stop. */
|
|
|
+ __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter runnning.
|
|
|
+ * 1 means counter stop. */
|
|
|
+ __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter runnning.
|
|
|
+ * 1 means counter stop. */
|
|
|
+ __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter runnning.
|
|
|
+ * 1 means counter stop. */
|
|
|
+ __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter runnning.
|
|
|
+ * 1 means counter stop. */
|
|
|
+ __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter runnning.
|
|
|
+ * 1 means counter stop. */
|
|
|
+ __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's
|
|
|
+ * counter status (GTCR.CST bit). 0 means counter runnning.
|
|
|
+ * 1 means counter stop. */
|
|
|
+ } GTSTP_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */
|
|
|
+ __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */
|
|
|
+ __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */
|
|
|
+ __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */
|
|
|
+ __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */
|
|
|
+ __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */
|
|
|
+ __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */
|
|
|
+ __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */
|
|
|
+ __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */
|
|
|
+ __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */
|
|
|
+ __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */
|
|
|
+ __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */
|
|
|
+ __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */
|
|
|
+ __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */
|
|
|
+ __OM uint32_t CCLR14 : 1; /*!< [14..14] Channel GTCNT Count Clear */
|
|
|
+ __OM uint32_t CCLR15 : 1; /*!< [15..15] Channel GTCNT Count Clear */
|
|
|
+ __OM uint32_t CCLR16 : 1; /*!< [16..16] Channel GTCNT Count Clear */
|
|
|
+ __OM uint32_t CCLR17 : 1; /*!< [17..17] Channel GTCNT Count Clear */
|
|
|
+ __OM uint32_t CCLR18 : 1; /*!< [18..18] Channel GTCNT Count Clear */
|
|
|
+ __OM uint32_t CCLR19 : 1; /*!< [19..19] Channel GTCNT Count Clear */
|
|
|
+ __OM uint32_t CCLR20 : 1; /*!< [20..20] Channel GTCNT Count Clear */
|
|
|
+ __OM uint32_t CCLR21 : 1; /*!< [21..21] Channel GTCNT Count Clear */
|
|
|
+ __OM uint32_t CCLR22 : 1; /*!< [22..22] Channel GTCNT Count Clear */
|
|
|
+ __OM uint32_t CCLR23 : 1; /*!< [23..23] Channel GTCNT Count Clear */
|
|
|
+ __OM uint32_t CCLR24 : 1; /*!< [24..24] Channel GTCNT Count Clear */
|
|
|
+ __OM uint32_t CCLR25 : 1; /*!< [25..25] Channel GTCNT Count Clear */
|
|
|
+ __OM uint32_t CCLR26 : 1; /*!< [26..26] Channel GTCNT Count Clear */
|
|
|
+ __OM uint32_t CCLR27 : 1; /*!< [27..27] Channel GTCNT Count Clear */
|
|
|
+ __OM uint32_t CCLR28 : 1; /*!< [28..28] Channel GTCNT Count Clear */
|
|
|
+ __OM uint32_t CCLR29 : 1; /*!< [29..29] Channel GTCNT Count Clear */
|
|
|
+ __OM uint32_t CCLR30 : 1; /*!< [30..30] Channel GTCNT Count Clear */
|
|
|
+ __OM uint32_t CCLR31 : 1; /*!< [31..31] Channel GTCNT Count Clear */
|
|
|
+ } GTCLR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */
|
|
|
+ __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */
|
|
|
+ __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */
|
|
|
+ __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */
|
|
|
+ __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */
|
|
|
+ __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */
|
|
|
+ __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */
|
|
|
+ __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */
|
|
|
+ __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
|
|
|
+ * Counter Start Enable */
|
|
|
+ __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
|
|
|
+ * Counter Start Enable */
|
|
|
+ __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
|
|
|
+ * Counter Start Enable */
|
|
|
+ __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
|
|
|
+ * Counter Start Enable */
|
|
|
+ __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
|
|
|
+ * Counter Start Enable */
|
|
|
+ __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
|
|
|
+ * Counter Start Enable */
|
|
|
+ __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
|
|
|
+ * Counter Start Enable */
|
|
|
+ __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
|
|
|
+ * Counter Start Enable */
|
|
|
+ __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */
|
|
|
+ __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */
|
|
|
+ __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */
|
|
|
+ __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */
|
|
|
+ __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */
|
|
|
+ __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */
|
|
|
+ __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */
|
|
|
+ __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */
|
|
|
+ uint32_t : 7;
|
|
|
+ __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */
|
|
|
+ } GTSSR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */
|
|
|
+ __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */
|
|
|
+ __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */
|
|
|
+ __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */
|
|
|
+ __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */
|
|
|
+ __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */
|
|
|
+ __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */
|
|
|
+ __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */
|
|
|
+ __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
|
|
|
+ * Counter Stop Enable */
|
|
|
+ __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
|
|
|
+ * Counter Stop Enable */
|
|
|
+ __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
|
|
|
+ * Counter Stop Enable */
|
|
|
+ __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
|
|
|
+ * Counter Stop Enable */
|
|
|
+ __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
|
|
|
+ * Counter Stop Enable */
|
|
|
+ __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
|
|
|
+ * Counter Stop Enable */
|
|
|
+ __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
|
|
|
+ * Counter Stop Enable */
|
|
|
+ __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
|
|
|
+ * Counter Stop Enable */
|
|
|
+ __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */
|
|
|
+ __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */
|
|
|
+ __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */
|
|
|
+ __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */
|
|
|
+ __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */
|
|
|
+ __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */
|
|
|
+ __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */
|
|
|
+ __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */
|
|
|
+ uint32_t : 7;
|
|
|
+ __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */
|
|
|
+ } GTPSR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */
|
|
|
+ __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */
|
|
|
+ __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */
|
|
|
+ __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */
|
|
|
+ __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */
|
|
|
+ __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */
|
|
|
+ __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */
|
|
|
+ __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */
|
|
|
+ __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
|
|
|
+ * Counter Clear Enable */
|
|
|
+ __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
|
|
|
+ * Counter Clear Enable */
|
|
|
+ __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
|
|
|
+ * Counter Clear Enable */
|
|
|
+ __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
|
|
|
+ * Counter Clear Enable */
|
|
|
+ __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
|
|
|
+ * Counter Clear Enable */
|
|
|
+ __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
|
|
|
+ * Counter Clear Enable */
|
|
|
+ __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
|
|
|
+ * Counter Clear Enable */
|
|
|
+ __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
|
|
|
+ * Counter Clear Enable */
|
|
|
+ __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */
|
|
|
+ __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */
|
|
|
+ __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */
|
|
|
+ __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */
|
|
|
+ __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */
|
|
|
+ __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */
|
|
|
+ __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */
|
|
|
+ __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */
|
|
|
+ __IOM uint32_t CSCMSC : 3; /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing
|
|
|
+ * Source Counter Clear Enable. */
|
|
|
+ __IOM uint32_t CP1CCE : 1; /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear
|
|
|
+ * Enable (This bit is only available in GPT324 to GPT329.
|
|
|
+ * In GPT320 to GPT323, this bit is read as 0. The write value
|
|
|
+ * should be 0.) */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */
|
|
|
+ } GTCSR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */
|
|
|
+ __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */
|
|
|
+ __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */
|
|
|
+ __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */
|
|
|
+ __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */
|
|
|
+ __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */
|
|
|
+ __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */
|
|
|
+ __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */
|
|
|
+ __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
|
|
|
+ * Counter Count Up Enable */
|
|
|
+ __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
|
|
|
+ * Counter Count Up Enable */
|
|
|
+ __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
|
|
|
+ * Counter Count Up Enable */
|
|
|
+ __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
|
|
|
+ * Counter Count Up Enable */
|
|
|
+ __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
|
|
|
+ * Counter Count Up Enable */
|
|
|
+ __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
|
|
|
+ * Counter Count Up Enable */
|
|
|
+ __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
|
|
|
+ * Counter Count Up Enable */
|
|
|
+ __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
|
|
|
+ * Counter Count Up Enable */
|
|
|
+ __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */
|
|
|
+ __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */
|
|
|
+ __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */
|
|
|
+ __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */
|
|
|
+ __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */
|
|
|
+ __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */
|
|
|
+ __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */
|
|
|
+ __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */
|
|
|
+ __IOM uint32_t USILVL : 4; /*!< [27..24] External Input Level Source Count-Up Enable */
|
|
|
+ uint32_t : 4;
|
|
|
+ } GTUPSR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */
|
|
|
+ __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */
|
|
|
+ __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */
|
|
|
+ __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */
|
|
|
+ __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */
|
|
|
+ __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */
|
|
|
+ __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */
|
|
|
+ __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */
|
|
|
+ __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
|
|
|
+ * Counter Count Down Enable */
|
|
|
+ __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
|
|
|
+ * Counter Count Down Enable */
|
|
|
+ __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
|
|
|
+ * Counter Count Down Enable */
|
|
|
+ __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
|
|
|
+ * Counter Count Down Enable */
|
|
|
+ __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
|
|
|
+ * Counter Count Down Enable */
|
|
|
+ __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
|
|
|
+ * Counter Count Down Enable */
|
|
|
+ __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
|
|
|
+ * Counter Count Down Enable */
|
|
|
+ __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
|
|
|
+ * Counter Count Down Enable */
|
|
|
+ __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */
|
|
|
+ __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */
|
|
|
+ __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */
|
|
|
+ __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */
|
|
|
+ __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */
|
|
|
+ __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */
|
|
|
+ __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */
|
|
|
+ __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */
|
|
|
+ __IOM uint32_t DSILVL : 4; /*!< [27..24] External Input Level Source Count-Down Enable */
|
|
|
+ uint32_t : 4;
|
|
|
+ } GTDNSR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select
|
|
|
+ * Register A */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */
|
|
|
+ __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture
|
|
|
+ * Enable */
|
|
|
+ __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */
|
|
|
+ __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture
|
|
|
+ * Enable */
|
|
|
+ __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */
|
|
|
+ __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture
|
|
|
+ * Enable */
|
|
|
+ __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */
|
|
|
+ __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture
|
|
|
+ * Enable */
|
|
|
+ __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
|
|
|
+ * GTCCRA Input Capture Enable */
|
|
|
+ __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
|
|
|
+ * GTCCRA Input Capture Enable */
|
|
|
+ __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
|
|
|
+ * GTCCRA Input Capture Enable */
|
|
|
+ __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
|
|
|
+ * GTCCRA Input Capture Enable */
|
|
|
+ __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
|
|
|
+ * GTCCRA Input Capture Enable */
|
|
|
+ __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
|
|
|
+ * GTCCRA Input Capture Enable */
|
|
|
+ __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
|
|
|
+ * GTCCRA Input Capture Enable */
|
|
|
+ __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
|
|
|
+ * GTCCRA Input Capture Enable */
|
|
|
+ __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */
|
|
|
+ __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */
|
|
|
+ __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */
|
|
|
+ __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */
|
|
|
+ __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */
|
|
|
+ __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */
|
|
|
+ __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */
|
|
|
+ __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */
|
|
|
+ uint32_t : 8;
|
|
|
+ } GTICASR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select
|
|
|
+ * Register B */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */
|
|
|
+ __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture
|
|
|
+ * Enable */
|
|
|
+ __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */
|
|
|
+ __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture
|
|
|
+ * Enable */
|
|
|
+ __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */
|
|
|
+ __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture
|
|
|
+ * Enable */
|
|
|
+ __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */
|
|
|
+ __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture
|
|
|
+ * Enable */
|
|
|
+ __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
|
|
|
+ * GTCCRB Input Capture Enable */
|
|
|
+ __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
|
|
|
+ * GTCCRB Input Capture Enable */
|
|
|
+ __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
|
|
|
+ * GTCCRB Input Capture Enable */
|
|
|
+ __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
|
|
|
+ * GTCCRB Input Capture Enable */
|
|
|
+ __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
|
|
|
+ * GTCCRB Input Capture Enable */
|
|
|
+ __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
|
|
|
+ * GTCCRB Input Capture Enable */
|
|
|
+ __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
|
|
|
+ * GTCCRB Input Capture Enable */
|
|
|
+ __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
|
|
|
+ * GTCCRB Input Capture Enable */
|
|
|
+ __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */
|
|
|
+ __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */
|
|
|
+ __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */
|
|
|
+ __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */
|
|
|
+ __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */
|
|
|
+ __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */
|
|
|
+ __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */
|
|
|
+ __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */
|
|
|
+ uint32_t : 8;
|
|
|
+ } GTICBSR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CST : 1; /*!< [0..0] Count Start */
|
|
|
+ uint32_t : 7;
|
|
|
+ __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select During Count Stop */
|
|
|
+ __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable */
|
|
|
+ __IOM uint32_t SSCGRP : 2; /*!< [11..10] Synchronous Set/Clear Group Select */
|
|
|
+ __IOM uint32_t CPSCD : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t SSCEN : 1; /*!< [15..15] Synchronous Set/Clear Enable */
|
|
|
+ __IOM uint32_t MD : 4; /*!< [19..16] Mode Select */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */
|
|
|
+ __IOM uint32_t CKEG : 2; /*!< [28..27] Clock Edge Select */
|
|
|
+ uint32_t : 3;
|
|
|
+ } GTCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting
|
|
|
+ * Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */
|
|
|
+ __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */
|
|
|
+ uint32_t : 14;
|
|
|
+ __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */
|
|
|
+ __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */
|
|
|
+ __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100
|
|
|
+ * percent Duty Setting */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */
|
|
|
+ __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */
|
|
|
+ __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100
|
|
|
+ * percent Duty Setting */
|
|
|
+ uint32_t : 4;
|
|
|
+ } GTUDDTYC_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */
|
|
|
+ __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous
|
|
|
+ * Clear Disable.(This bit is only available in GPT324 to
|
|
|
+ * GPT329. In GPT320 to GPT323, this bit is read as 0. The
|
|
|
+ * write value should be 0.) */
|
|
|
+ __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */
|
|
|
+ __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */
|
|
|
+ __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */
|
|
|
+ __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */
|
|
|
+ __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This
|
|
|
+ * bit is only available in GPT324 to GPT329. In GPT320 to
|
|
|
+ * GPT323, this bit is read as 0. The write value should be
|
|
|
+ * 0.) */
|
|
|
+ __IOM uint32_t PSYE : 1; /*!< [12..12] PWM Synchronous output Enable */
|
|
|
+ __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */
|
|
|
+ __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */
|
|
|
+ __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */
|
|
|
+ __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */
|
|
|
+ __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */
|
|
|
+ __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */
|
|
|
+ __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This
|
|
|
+ * bit is only available in GPT324 to GPT329. In GPT320 to
|
|
|
+ * GPT323, this bit is read as 0. The write value should be
|
|
|
+ * 0.) */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */
|
|
|
+ __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */
|
|
|
+ } GTIOR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 8;
|
|
|
+ __IOM uint32_t SCFA : 1; /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous
|
|
|
+ * Clear Enable */
|
|
|
+ __IOM uint32_t SCFB : 1; /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous
|
|
|
+ * Clear Enable */
|
|
|
+ __IOM uint32_t SCFC : 1; /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source
|
|
|
+ * Synchronous Clear Enable */
|
|
|
+ __IOM uint32_t SCFD : 1; /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source
|
|
|
+ * Synchronous Clear Enable */
|
|
|
+ __IOM uint32_t SCFE : 1; /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source
|
|
|
+ * Synchronous Clear Enable */
|
|
|
+ __IOM uint32_t SCFF : 1; /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source
|
|
|
+ * Synchronous Clear Enable */
|
|
|
+ __IOM uint32_t SCFPO : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable */
|
|
|
+ __IOM uint32_t SCFPU : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable */
|
|
|
+ __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
|
|
|
+ * Start Request Enable */
|
|
|
+ __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D
|
|
|
+ * Conversion Start Request Enable */
|
|
|
+ __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
|
|
|
+ * Start Request Enable */
|
|
|
+ __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D
|
|
|
+ * Conversion Start Request Enable */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */
|
|
|
+ __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */
|
|
|
+ __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */
|
|
|
+ __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */
|
|
|
+ } GTINTAD_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */
|
|
|
+ __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */
|
|
|
+ __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */
|
|
|
+ __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */
|
|
|
+ __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */
|
|
|
+ __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */
|
|
|
+ __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */
|
|
|
+ __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */
|
|
|
+ __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter
|
|
|
+ * for counting the number of times a timer interrupt has
|
|
|
+ * been skipped.) */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */
|
|
|
+ __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start
|
|
|
+ * Request Interrupt Enable */
|
|
|
+ __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor
|
|
|
+ * Start Request Flag */
|
|
|
+ __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start
|
|
|
+ * Request Flag */
|
|
|
+ __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor
|
|
|
+ * Start Request Flag */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */
|
|
|
+ __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */
|
|
|
+ __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */
|
|
|
+ __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */
|
|
|
+ } GTST_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */
|
|
|
+ __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */
|
|
|
+ __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */
|
|
|
+ __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable */
|
|
|
+ uint32_t : 5;
|
|
|
+ __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */
|
|
|
+ __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */
|
|
|
+ __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */
|
|
|
+ __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
|
|
|
+ * is read as 0. */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
|
|
|
+ * wavesNOTE: In the Saw waves, values other than 0 0: Transfer
|
|
|
+ * at an underflow (in down-counting) or overflow (in up-counting)
|
|
|
+ * is performed. */
|
|
|
+ __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
|
|
|
+ * wavesNOTE: In the Saw waves, values other than 0 0: Transfer
|
|
|
+ * at an underflow (in down-counting) or overflow (in up-counting)
|
|
|
+ * is performed. */
|
|
|
+ __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */
|
|
|
+ uint32_t : 1;
|
|
|
+ } GTBER_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter
|
|
|
+ * Start Request Skipping Setting Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */
|
|
|
+ __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */
|
|
|
+ __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */
|
|
|
+ __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */
|
|
|
+ __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */
|
|
|
+ __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */
|
|
|
+ __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */
|
|
|
+ __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */
|
|
|
+ uint32_t : 17;
|
|
|
+ } GTITC_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */
|
|
|
+ } GTCNT_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */
|
|
|
+ } GTCCR_b[6];
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */
|
|
|
+ } GTPR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */
|
|
|
+ } GTPBR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer
|
|
|
+ * Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */
|
|
|
+ } GTPDBR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */
|
|
|
+ } GTADTRA_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register
|
|
|
+ * A */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */
|
|
|
+ } GTADTBRA_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer
|
|
|
+ * Register A */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register
|
|
|
+ * A */
|
|
|
+ } GTADTDBRA_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */
|
|
|
+ } GTADTRB_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register
|
|
|
+ * B */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */
|
|
|
+ } GTADTBRB_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer
|
|
|
+ * Register B */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register
|
|
|
+ * B */
|
|
|
+ } GTADTDBRB_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */
|
|
|
+ __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */
|
|
|
+ uint32_t : 23;
|
|
|
+ } GTDTCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */
|
|
|
+ } GTDVU_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */
|
|
|
+ } GTDVD_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */
|
|
|
+ } GTDBU_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */
|
|
|
+ } GTDBD_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function
|
|
|
+ * Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */
|
|
|
+ uint32_t : 30;
|
|
|
+ } GTSOS_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function
|
|
|
+ * Temporary Release Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */
|
|
|
+ uint32_t : 31;
|
|
|
+ } GTSOTR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTADSMR; /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request
|
|
|
+ * Signal Monitoring Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t ADSMS0 : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection */
|
|
|
+ uint32_t : 6;
|
|
|
+ __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output
|
|
|
+ * Enabling */
|
|
|
+ uint32_t : 7;
|
|
|
+ __IOM uint32_t ADSMS1 : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection */
|
|
|
+ uint32_t : 6;
|
|
|
+ __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output
|
|
|
+ * Enabling */
|
|
|
+ uint32_t : 7;
|
|
|
+ } GTADSMR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTEITC; /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping
|
|
|
+ * Counter Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t EIVTC1 : 2; /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t EIVTT1 : 4; /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IM uint32_t EITCNT1 : 4; /*!< [15..12] Extended Interrupt Skipping Counter 1 */
|
|
|
+ __IOM uint32_t EIVTC2 : 2; /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source
|
|
|
+ * select */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t EIVTT2 : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting */
|
|
|
+ __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value */
|
|
|
+ __IM uint32_t EITCNT2 : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2 */
|
|
|
+ } GTEITC_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTEITLI1; /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping
|
|
|
+ * Setting Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t EITLA : 3; /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt
|
|
|
+ * Extended Skipping Function Select */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t EITLB : 3; /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt
|
|
|
+ * Extended Skipping Function Select */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t EITLC : 3; /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping
|
|
|
+ * Function Select */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t EITLD : 3; /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping
|
|
|
+ * Function Select */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t EITLE : 3; /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping
|
|
|
+ * Function Select */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t EITLF : 3; /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping
|
|
|
+ * Function Select */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t EITLV : 3; /*!< [26..24] Overflow Interrupt Extended Skipping Function Select */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t EITLU : 3; /*!< [30..28] Underflow Interrupt Extended Skipping Function Select */
|
|
|
+ uint32_t : 1;
|
|
|
+ } GTEITLI1_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTEITLI2; /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping
|
|
|
+ * Setting Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended
|
|
|
+ * Skipping Function Select */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended
|
|
|
+ * Skipping Function Select */
|
|
|
+ uint32_t : 25;
|
|
|
+ } GTEITLI2_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTEITLB; /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping
|
|
|
+ * Setting Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t EBTLCA : 3; /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function
|
|
|
+ * Select */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t EBTLCB : 3; /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function
|
|
|
+ * Select */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t EBTLPR : 3; /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function
|
|
|
+ * Select */
|
|
|
+ uint32_t : 5;
|
|
|
+ __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping
|
|
|
+ * Function Select */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping
|
|
|
+ * Function Select */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function
|
|
|
+ * Select */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function
|
|
|
+ * Select */
|
|
|
+ uint32_t : 1;
|
|
|
+ } GTEITLB_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation
|
|
|
+ * Function Setting Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */
|
|
|
+ uint32_t : 6;
|
|
|
+ __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */
|
|
|
+ uint32_t : 6;
|
|
|
+ } GTICLF_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */
|
|
|
+ uint32_t : 7;
|
|
|
+ __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */
|
|
|
+ uint32_t : 7;
|
|
|
+ __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */
|
|
|
+ uint32_t : 4;
|
|
|
+ } GTPC_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED[4];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous
|
|
|
+ * Control Channel Select Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel
|
|
|
+ * Select */
|
|
|
+ __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel
|
|
|
+ * Select */
|
|
|
+ __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel
|
|
|
+ * Select */
|
|
|
+ __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel
|
|
|
+ * Select */
|
|
|
+ __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel
|
|
|
+ * Select */
|
|
|
+ __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel
|
|
|
+ * Select */
|
|
|
+ __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel
|
|
|
+ * Select */
|
|
|
+ __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel
|
|
|
+ * Select */
|
|
|
+ __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel
|
|
|
+ * Select */
|
|
|
+ __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel
|
|
|
+ * Select */
|
|
|
+ uint32_t : 22;
|
|
|
+ } GTSECSR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous
|
|
|
+ * Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */
|
|
|
+ __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */
|
|
|
+ __IOM uint32_t SBDAE : 1; /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable */
|
|
|
+ __IOM uint32_t SBDDE : 1; /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */
|
|
|
+ __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */
|
|
|
+ __IOM uint32_t SBDAD : 1; /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable */
|
|
|
+ __IOM uint32_t SBDDD : 1; /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */
|
|
|
+ __IOM uint32_t SSCE : 1; /*!< [17..17] Synchronous Set/Clear Simultaneous Enable */
|
|
|
+ uint32_t : 6;
|
|
|
+ __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */
|
|
|
+ __IOM uint32_t SSCD : 1; /*!< [25..25] Synchronous Set/Clear Simultaneous Disable */
|
|
|
+ uint32_t : 6;
|
|
|
+ } GTSECR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED1[2];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTBER2; /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CCTCA : 1; /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer
|
|
|
+ * Disable */
|
|
|
+ __IOM uint32_t CCTCB : 1; /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer
|
|
|
+ * Disable */
|
|
|
+ __IOM uint32_t CCTPR : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable */
|
|
|
+ __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer
|
|
|
+ * Disable */
|
|
|
+ __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer
|
|
|
+ * Disable */
|
|
|
+ __IOM uint32_t CCTDV : 1; /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer
|
|
|
+ * Disable */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t CMTCA : 2; /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer
|
|
|
+ * Enable */
|
|
|
+ __IOM uint32_t CMTCB : 2; /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer
|
|
|
+ * Enable */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer
|
|
|
+ * Enable */
|
|
|
+ __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer
|
|
|
+ * Enable */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t CPTCA : 1; /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer
|
|
|
+ * Disable */
|
|
|
+ __IOM uint32_t CPTCB : 1; /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer
|
|
|
+ * Disable */
|
|
|
+ __IOM uint32_t CPTPR : 1; /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer
|
|
|
+ * Disable */
|
|
|
+ __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer
|
|
|
+ * Disable */
|
|
|
+ __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer
|
|
|
+ * Disable */
|
|
|
+ __IOM uint32_t CPTDV : 1; /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer
|
|
|
+ * Transfer Disable */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t CP3DB : 1; /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select */
|
|
|
+ __IOM uint32_t CPBTD : 1; /*!< [25..25] Complementary PWM mode Buffer Transfer Disable */
|
|
|
+ __IOM uint32_t OLTTA : 2; /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select */
|
|
|
+ __IOM uint32_t OLTTB : 2; /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select */
|
|
|
+ uint32_t : 2;
|
|
|
+ } GTBER2_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTOLBR; /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits */
|
|
|
+ uint32_t : 11;
|
|
|
+ __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits */
|
|
|
+ uint32_t : 11;
|
|
|
+ } GTOLBR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED2;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t GTICCR; /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input
|
|
|
+ * Capture Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t ICAFA : 1; /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture
|
|
|
+ * to Other Channel GTCCRA Input Capture Source Enable */
|
|
|
+ __IOM uint32_t ICAFB : 1; /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture
|
|
|
+ * to Other Channel GTCCRA Input Capture Source Enable */
|
|
|
+ __IOM uint32_t ICAFC : 1; /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other
|
|
|
+ * Channel GTCCRA Input Capture Source Enable */
|
|
|
+ __IOM uint32_t ICAFD : 1; /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other
|
|
|
+ * Channel GTCCRA Input Capture Source Enable */
|
|
|
+ __IOM uint32_t ICAFE : 1; /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other
|
|
|
+ * Channel GTCCRA Input Capture Source Enable */
|
|
|
+ __IOM uint32_t ICAFF : 1; /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other
|
|
|
+ * Channel GTCCRA Input Capture Source Enable */
|
|
|
+ __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture
|
|
|
+ * Source Enable */
|
|
|
+ __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture
|
|
|
+ * Source Enable */
|
|
|
+ __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input
|
|
|
+ * Capture Source Enable */
|
|
|
+ uint32_t : 5;
|
|
|
+ __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select */
|
|
|
+ __IOM uint32_t ICBFA : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture
|
|
|
+ * to Other Channel GTCCRB Input Capture Source Enable */
|
|
|
+ __IOM uint32_t ICBFB : 1; /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture
|
|
|
+ * to Other Channel GTCCRB Input Capture Source Enable */
|
|
|
+ __IOM uint32_t ICBFC : 1; /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to
|
|
|
+ * Other Channel GTCCRB Input Capture Source Enable */
|
|
|
+ __IOM uint32_t ICBFD : 1; /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to
|
|
|
+ * Other Channel GTCCRB Input Capture Source Enable */
|
|
|
+ __IOM uint32_t ICBFE : 1; /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to
|
|
|
+ * Other Channel GTCCRb Input Capture Source Enable */
|
|
|
+ __IOM uint32_t ICBFF : 1; /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to
|
|
|
+ * Other Channel GTCCRB Input Capture Source Enable */
|
|
|
+ __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture
|
|
|
+ * Source Enable */
|
|
|
+ __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input
|
|
|
+ * Capture Source Enable */
|
|
|
+ __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input
|
|
|
+ * Capture Source Enable */
|
|
|
+ uint32_t : 5;
|
|
|
+ __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select */
|
|
|
+ } GTICCR_b;
|
|
|
+ };
|
|
|
+} R_GPT0_Type; /*!< Size = 240 (0xf0) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_GPT_OPS ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Output Phase Switching for GPT (R_GPT_OPS)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x40323F00) R_GPT_OPS Structure */
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t OPSCR; /*!< (@ 0x00000000) Output Phase Switching Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t UF : 1; /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase
|
|
|
+ * by the software settings.This bit setting is valid when
|
|
|
+ * the OPSCR.FB bit = 1. */
|
|
|
+ __IOM uint32_t VF : 1; /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase
|
|
|
+ * by the software settings.This bit setting is valid when
|
|
|
+ * the OPSCR.FB bit = 1. */
|
|
|
+ __IOM uint32_t WF : 1; /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase
|
|
|
+ * by the software settings.This bit setting is valid when
|
|
|
+ * the OPSCR.FB bit = 1. */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IM uint32_t U : 1; /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the
|
|
|
+ * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa
|
|
|
+ * e settings (UF/VF/WF) */
|
|
|
+ __IM uint32_t V : 1; /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the
|
|
|
+ * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa
|
|
|
+ * e settings (UF/VF/WF) */
|
|
|
+ __IM uint32_t W : 1; /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the
|
|
|
+ * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa
|
|
|
+ * e settings (UF/VF/WF) */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t EN : 1; /*!< [8..8] Enable-Phase Output Control */
|
|
|
+ uint32_t : 7;
|
|
|
+ __IOM uint32_t FB : 1; /*!< [16..16] External Feedback Signal EnableThis bit selects the
|
|
|
+ * input phase from the software settings and external input. */
|
|
|
+ __IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control */
|
|
|
+ __IOM uint32_t N : 1; /*!< [18..18] Negative-Phase Output (N) Control */
|
|
|
+ __IOM uint32_t INV : 1; /*!< [19..19] Invert-Phase Output Control */
|
|
|
+ __IOM uint32_t RV : 1; /*!< [20..20] Output phase rotation direction reversal */
|
|
|
+ __IOM uint32_t ALIGN : 1; /*!< [21..21] Input phase alignment */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t GRP : 2; /*!< [25..24] Output disabled source selection */
|
|
|
+ __IOM uint32_t GODF : 1; /*!< [26..26] Group output disable function */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t NFEN : 1; /*!< [29..29] External Input Noise Filter Enable */
|
|
|
+ __IOM uint32_t NFCS : 2; /*!< [31..30] External Input Noise Filter Clock selectionNoise filter
|
|
|
+ * sampling clock setting of the external input. */
|
|
|
+ } OPSCR_b;
|
|
|
+ };
|
|
|
+} R_GPT_OPS_Type; /*!< Size = 4 (0x4) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_GPT_POEG0 ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Port Output Enable for GPT (R_GPT_POEG0)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x40212000) R_GPT_POEG0 Structure */
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */
|
|
|
+ __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */
|
|
|
+ __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */
|
|
|
+ __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */
|
|
|
+ __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable. Note: Can be modified only
|
|
|
+ * once after a reset. */
|
|
|
+ __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified
|
|
|
+ * only once after a reset. */
|
|
|
+ __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified
|
|
|
+ * only once after a reset. */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified
|
|
|
+ * only once after a reset. */
|
|
|
+ __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified
|
|
|
+ * only once after a reset. */
|
|
|
+ __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified
|
|
|
+ * only once after a reset. */
|
|
|
+ __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified
|
|
|
+ * only once after a reset. */
|
|
|
+ __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified
|
|
|
+ * only once after a reset. */
|
|
|
+ __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified
|
|
|
+ * only once after a reset. */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */
|
|
|
+ uint32_t : 7;
|
|
|
+ __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag */
|
|
|
+ __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag */
|
|
|
+ __IOM uint32_t DERR0E : 1; /*!< [26..26] DSMIF0 Error Detection Enable */
|
|
|
+ __IOM uint32_t DERR1E : 1; /*!< [27..27] DSMIF1 Error Detection Enable */
|
|
|
+ __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */
|
|
|
+ __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */
|
|
|
+ __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */
|
|
|
+ } POEGG_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED[15];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t GTONCWP; /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection
|
|
|
+ * Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t WP : 1; /*!< [0..0] Register Writing Disable */
|
|
|
+ uint16_t : 7;
|
|
|
+ __IOM uint16_t PRKEY : 8; /*!< [15..8] Key Code */
|
|
|
+ } GTONCWP_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED1;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t GTONCCR; /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling
|
|
|
+ * Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t NE : 1; /*!< [0..0] Direct Stopping Request Setting */
|
|
|
+ uint16_t : 3;
|
|
|
+ __IOM uint16_t NFS : 4; /*!< [7..4] Direct Stopping Request Selection */
|
|
|
+ __IOM uint16_t NFV : 1; /*!< [8..8] Direct Stopping Request Active Sense */
|
|
|
+ uint16_t : 7;
|
|
|
+ } GTONCCR_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED2;
|
|
|
+} R_GPT_POEG0_Type; /*!< Size = 72 (0x48) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_ICU ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Interrupt Controller Unit (R_ICU)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x40006000) R_ICU Structure */
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t IRQCR[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */
|
|
|
+ uint8_t : 2;
|
|
|
+ __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */
|
|
|
+ } IRQCR_b[16];
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint8_t NMICR; /*!< (@ 0x00000010) NMI Pin Interrupt Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */
|
|
|
+ uint8_t : 3;
|
|
|
+ __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */
|
|
|
+ } NMICR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED;
|
|
|
+ __IM uint16_t RESERVED1;
|
|
|
+ __IM uint32_t RESERVED2[6143];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SWIRQ_S; /*!< (@ 0x00006010) Software Interrupt Request Register for Secure
|
|
|
+ * Interrupt */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t SWIRQS : 1; /*!< [0..0] Generates an interrupt for the other CPU subsystem. */
|
|
|
+ uint8_t : 7;
|
|
|
+ } SWIRQ_S_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED3;
|
|
|
+ __IM uint16_t RESERVED4;
|
|
|
+ __IM uint32_t RESERVED5[3];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SWIRQ_NS; /*!< (@ 0x00006020) Software Interrupt Request Register for Non-secure
|
|
|
+ * Interrupt */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t SWIRQNS : 1; /*!< [0..0] Generates an interrupt for the other CPU subsystem. */
|
|
|
+ uint8_t : 7;
|
|
|
+ } SWIRQ_NS_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED6;
|
|
|
+ __IM uint16_t RESERVED7;
|
|
|
+ __IM uint32_t RESERVED8[15];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t IENMIER; /*!< (@ 0x00006060) Integrated Error NMI Interrupt Enable Registe
|
|
|
+ * for CPU */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t CMEN : 1; /*!< [0..0] Integrated Common Memory error nmi Enable */
|
|
|
+ __IOM uint16_t LMEN : 1; /*!< [1..1] Integrated Local Memory error nmi Enable */
|
|
|
+ __IOM uint16_t BUSEN : 1; /*!< [2..2] Integrated BUS error nmi Enable */
|
|
|
+ uint16_t : 13;
|
|
|
+ } IENMIER_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED9;
|
|
|
+ __IM uint32_t RESERVED10[39];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t NMIER; /*!< (@ 0x00006100) Non-Maskable Interrupt Enable Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */
|
|
|
+ __IOM uint16_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */
|
|
|
+ __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */
|
|
|
+ __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IOM uint16_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */
|
|
|
+ __IOM uint16_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */
|
|
|
+ uint16_t : 4;
|
|
|
+ __IOM uint16_t BUSEN : 1; /*!< [12..12] BUS error Interrupt Enable */
|
|
|
+ __IOM uint16_t CMEN : 1; /*!< [13..13] Common Memory error Interrupt Enable */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t LUEN : 1; /*!< [15..15] LockUp Interrupt Enable */
|
|
|
+ } NMIER_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED11;
|
|
|
+ __IM uint32_t RESERVED12[3];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t NMICLR; /*!< (@ 0x00006110) Non-Maskable Interrupt Status Clear Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */
|
|
|
+ __IOM uint16_t WDTCLR : 1; /*!< [1..1] WDT Clear */
|
|
|
+ __IOM uint16_t LVD1CLR : 1; /*!< [2..2] PVD1 Clear */
|
|
|
+ __IOM uint16_t LVD2CLR : 1; /*!< [3..3] PVD2 Clear */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IOM uint16_t OSTCLR : 1; /*!< [6..6] OST Clear */
|
|
|
+ __IOM uint16_t NMICLR : 1; /*!< [7..7] NMI Clear */
|
|
|
+ uint16_t : 4;
|
|
|
+ __IOM uint16_t BUSCLR : 1; /*!< [12..12] Bus Clear */
|
|
|
+ __IOM uint16_t CMCLR : 1; /*!< [13..13] CM Clear */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t LUCLR : 1; /*!< [15..15] LU Clear */
|
|
|
+ } NMICLR_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED13;
|
|
|
+ __IM uint32_t RESERVED14[3];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint16_t NMISR; /*!< (@ 0x00006120) Non-Maskable Interrupt Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */
|
|
|
+ __IM uint16_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */
|
|
|
+ __IM uint16_t LVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */
|
|
|
+ __IM uint16_t LVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IM uint16_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */
|
|
|
+ __IM uint16_t NMIST : 1; /*!< [7..7] NMI Status Flag */
|
|
|
+ uint16_t : 4;
|
|
|
+ __IM uint16_t BUSST : 1; /*!< [12..12] BUS error Interrupt Status Flag */
|
|
|
+ __IM uint16_t CMST : 1; /*!< [13..13] Common Memory error Interrupt Status Flag */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IM uint16_t LUST : 1; /*!< [15..15] LockUp Interrupt Status Flag */
|
|
|
+ } NMISR_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED15;
|
|
|
+ __IM uint32_t RESERVED16[31];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t WUPEN; /*!< (@ 0x000061A0) Wake Up Interrupt Enable Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ0 Interrupt Deep Sleep/Software Standby Returns Enable
|
|
|
+ * bit */
|
|
|
+ __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ1 Interrupt Deep Sleep/Software Standby Returns Enable
|
|
|
+ * bit */
|
|
|
+ __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ2 Interrupt Deep Sleep/Software Standby Returns Enable
|
|
|
+ * bit */
|
|
|
+ __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ3 Interrupt Deep Sleep/Software Standby Returns Enable
|
|
|
+ * bit */
|
|
|
+ __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ4 Interrupt Deep Sleep/Software Standby Returns Enable
|
|
|
+ * bit */
|
|
|
+ __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ5 Interrupt Deep Sleep/Software Standby Returns Enable
|
|
|
+ * bit */
|
|
|
+ __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ6 Interrupt Deep Sleep/Software Standby Returns Enable
|
|
|
+ * bit */
|
|
|
+ __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ7 Interrupt Deep Sleep/Software Standby Returns Enable
|
|
|
+ * bit */
|
|
|
+ __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ8 Interrupt Deep Sleep/Software Standby Returns Enable
|
|
|
+ * bit */
|
|
|
+ __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ9 Interrupt Deep Sleep/Software Standby Returns Enable
|
|
|
+ * bit */
|
|
|
+ __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ10 Interrupt Deep Sleep/Software Standby Returns
|
|
|
+ * Enable bit */
|
|
|
+ __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ11 Interrupt Deep Sleep/Software Standby Returns
|
|
|
+ * Enable bit */
|
|
|
+ __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ12 Interrupt Deep Sleep/Software Standby Returns
|
|
|
+ * Enable bit */
|
|
|
+ __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ13 Interrupt Deep Sleep/Software Standby Returns
|
|
|
+ * Enable bit */
|
|
|
+ __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ14 Interrupt Deep Sleep/Software Standby Returns
|
|
|
+ * Enable bit */
|
|
|
+ __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ15 Interrupt Deep Sleep/Software Standby Returns
|
|
|
+ * Enable bit */
|
|
|
+ __IOM uint32_t IWDTWUPEN : 1; /*!< [16..16] IWDT Interrupt Deep Sleep/Software Standby Returns
|
|
|
+ * Enable bit */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t LVD1WUPEN : 1; /*!< [18..18] PVD1 Interrupt Deep Sleep/Software Standby Returns
|
|
|
+ * Enable bit */
|
|
|
+ __IOM uint32_t LVD2WUPEN : 1; /*!< [19..19] PVD2 Interrupt Deep Sleep/Software Standby Returns
|
|
|
+ * Enable bit */
|
|
|
+ __IOM uint32_t VBATTWUPEN : 1; /*!< [20..20] VBATT Monitor Interrupt Deep Sleep/Software Standby
|
|
|
+ * Returns Enable bit */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC Alarm Interrupt Deep Sleep/Software Standby Returns
|
|
|
+ * Enable bit */
|
|
|
+ __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT Period Interrupt Deep Sleep/Software Standby Returns
|
|
|
+ * Enable bit */
|
|
|
+ __IOM uint32_t USBHSWUPEN : 1; /*!< [26..26] USBHS Interrupt Deep Sleep/Software Standby Returns
|
|
|
+ * Enable bit */
|
|
|
+ __IOM uint32_t USBFSWUPEN : 1; /*!< [27..27] USBFS0 Interrupt Deep Sleep/Software Standby Returns
|
|
|
+ * Enable bit */
|
|
|
+ __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 Underflow Interrupt Deep Sleep/Software Standby
|
|
|
+ * Returns Enable bit */
|
|
|
+ __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 Compare Match A Interrupt Deep Sleep/Software
|
|
|
+ * Standby Returns Enable bit */
|
|
|
+ __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 Compare Match B Interrupt Deep Sleep/Software
|
|
|
+ * Standby Returns Enable bit */
|
|
|
+ __IOM uint32_t RIIC0WUPEN : 1; /*!< [31..31] RIIC0 Address Match Interrupt Deep Sleep/Software Standby
|
|
|
+ * Returns Enable bit */
|
|
|
+ } WUPEN_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t WUPEN1; /*!< (@ 0x000061A4) Wake Up Interrupt Enable Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t COMPHS0WUPEN : 1; /*!< [3..3] Comparator-HS0 Interrupt Deep Sleep/Software Standby
|
|
|
+ * Returns Enable bit */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t ULP0UWUPEN : 1; /*!< [8..8] ULPT0 Underflow Interrupt Deep Sleep/Software Standby
|
|
|
+ * Returns Enable bit */
|
|
|
+ __IOM uint32_t ULP0AWUPEN : 1; /*!< [9..9] ULPT0 Compare Match A Interrupt Deep Sleep/Software Standby
|
|
|
+ * Returns Enable bit */
|
|
|
+ __IOM uint32_t ULP0BWUPEN : 1; /*!< [10..10] ULPT0 Compare Match B Interrupt Deep Sleep/Software
|
|
|
+ * Standby Returns Enable bit */
|
|
|
+ __IOM uint32_t I3CWUPEN : 1; /*!< [11..11] I3C Wakeup Condition Detection Interrupt Deep Sleep/Software
|
|
|
+ * Standby Returns Enable bit */
|
|
|
+ __IOM uint32_t ULP1UWUPEN : 1; /*!< [12..12] ULPT1 Underflow Interrupt Deep Sleep/Software Standby
|
|
|
+ * Returns Enable bit */
|
|
|
+ __IOM uint32_t ULP1AWUPEN : 1; /*!< [13..13] ULPT1 Compare Match A Interrupt Deep Sleep/Software
|
|
|
+ * Standby Returns Enable bit */
|
|
|
+ __IOM uint32_t ULP1BWUPEN : 1; /*!< [14..14] ULPT1 Compare Match B Interrupt Deep Sleep/Software
|
|
|
+ * Standby Returns Enable bit */
|
|
|
+ uint32_t : 17;
|
|
|
+ } WUPEN1_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED17[86];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t IELSR[96]; /*!< (@ 0x00006300) ICU Event Link Setting Register [0..95] */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t IELS : 9; /*!< [8..0] ICU Event selection to NVICSet the number for the event
|
|
|
+ * signal to be linked . */
|
|
|
+ uint32_t : 7;
|
|
|
+ __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */
|
|
|
+ uint32_t : 7;
|
|
|
+ __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */
|
|
|
+ uint32_t : 7;
|
|
|
+ } IELSR_b[96];
|
|
|
+ };
|
|
|
+} R_ICU_Type; /*!< Size = 25728 (0x6480) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_IIC0 ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief I2C Bus Interface (R_IIC0)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x4025E000) R_IIC0 Structure */
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */
|
|
|
+ __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */
|
|
|
+ __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */
|
|
|
+ __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */
|
|
|
+ __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */
|
|
|
+ __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */
|
|
|
+ __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset
|
|
|
+ * is initiated using the IICRST bit for a bus hang-up occurred
|
|
|
+ * during communication with the master device in slave mode,
|
|
|
+ * the states may become different between the slave device
|
|
|
+ * and the master device (due to the difference in the bit
|
|
|
+ * counter information). */
|
|
|
+ __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */
|
|
|
+ } ICCR1_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start
|
|
|
+ * condition issuance request) when the BBSY flag is set to
|
|
|
+ * 0 (bus free state). */
|
|
|
+ __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the
|
|
|
+ * RS bit to 1 while issuing a stop condition. */
|
|
|
+ __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP
|
|
|
+ * bit is not possible while the setting of the BBSY flag
|
|
|
+ * is 0 (bus free state).Note: Do not set the SP bit to 1
|
|
|
+ * while a restart condition is being issued. */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */
|
|
|
+ __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */
|
|
|
+ __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */
|
|
|
+ } ICCR2_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */
|
|
|
+ __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */
|
|
|
+ __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB
|
|
|
+ * / 2^CKS ) */
|
|
|
+ __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */
|
|
|
+ } ICMR1_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */
|
|
|
+ __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */
|
|
|
+ __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */
|
|
|
+ __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */
|
|
|
+ } ICMR2_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */
|
|
|
+ __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */
|
|
|
+ __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */
|
|
|
+ __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */
|
|
|
+ __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */
|
|
|
+ __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read,
|
|
|
+ * be sure to read the ICDRR beforehand. */
|
|
|
+ __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */
|
|
|
+ } ICMR3_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */
|
|
|
+ __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */
|
|
|
+ __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */
|
|
|
+ __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */
|
|
|
+ __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */
|
|
|
+ __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */
|
|
|
+ __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */
|
|
|
+ __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */
|
|
|
+ } ICFER_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */
|
|
|
+ __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */
|
|
|
+ __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */
|
|
|
+ __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */
|
|
|
+ } ICSER_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */
|
|
|
+ __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */
|
|
|
+ __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */
|
|
|
+ __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */
|
|
|
+ __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */
|
|
|
+ __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */
|
|
|
+ __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */
|
|
|
+ __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */
|
|
|
+ } ICIER_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */
|
|
|
+ __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */
|
|
|
+ __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */
|
|
|
+ __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */
|
|
|
+ } ICSR1_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */
|
|
|
+ __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */
|
|
|
+ __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */
|
|
|
+ __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */
|
|
|
+ __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */
|
|
|
+ __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */
|
|
|
+ __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */
|
|
|
+ __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */
|
|
|
+ } ICSR2_b;
|
|
|
+ };
|
|
|
+ __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */
|
|
|
+ uint8_t : 3;
|
|
|
+ } ICBRL_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */
|
|
|
+ uint8_t : 3;
|
|
|
+ } ICBRH_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */
|
|
|
+ } ICDRT_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */
|
|
|
+ } ICDRR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED[2];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */
|
|
|
+ uint8_t : 3;
|
|
|
+ __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */
|
|
|
+ __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */
|
|
|
+ __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */
|
|
|
+ __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */
|
|
|
+ } ICWUR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */
|
|
|
+ __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */
|
|
|
+ __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */
|
|
|
+ uint8_t : 5;
|
|
|
+ } ICWUR2_b;
|
|
|
+ };
|
|
|
+} R_IIC0_Type; /*!< Size = 24 (0x18) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_IWDT ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Independent Watchdog Timer (R_IWDT)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x40202200) R_IWDT Structure */
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing
|
|
|
+ * 0xFF to this register. */
|
|
|
+ } IWDTRR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t IWDTCR; /*!< (@ 0x00000002) IWDT Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */
|
|
|
+ __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */
|
|
|
+ uint16_t : 2;
|
|
|
+ } IWDTCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */
|
|
|
+ __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */
|
|
|
+ __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */
|
|
|
+ } IWDTSR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t IWDTRCR; /*!< (@ 0x00000006) IWDT Reset Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint8_t : 7;
|
|
|
+ __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */
|
|
|
+ } IWDTRCR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED1;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t IWDTCSTPR; /*!< (@ 0x00000008) IWDT Count Stop Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint8_t : 7;
|
|
|
+ __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */
|
|
|
+ } IWDTCSTPR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED2;
|
|
|
+ __IM uint16_t RESERVED3;
|
|
|
+} R_IWDT_Type; /*!< Size = 12 (0xc) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_I3C0 ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief I3C Bus Interface (R_I3C0)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x4035F000) R_I3C0 Structure */
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t PRTS; /*!< (@ 0x00000000) Protocol Selection Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t PRTMD : 1; /*!< [0..0] Protocol Mode */
|
|
|
+ uint32_t : 31;
|
|
|
+ } PRTS_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED[3];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CECTL; /*!< (@ 0x00000010) Clock Enable Control Resisters */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CLKE : 1; /*!< [0..0] Clock Enable */
|
|
|
+ uint32_t : 31;
|
|
|
+ } CECTL_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t BCTL; /*!< (@ 0x00000014) Bus Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t INCBA : 1; /*!< [0..0] Include I3C Broadcast Address */
|
|
|
+ uint32_t : 6;
|
|
|
+ __IOM uint32_t BMDS : 1; /*!< [7..7] Bus Mode Selection */
|
|
|
+ __IOM uint32_t HJACKCTL : 1; /*!< [8..8] Hot-Join Acknowledge Control */
|
|
|
+ uint32_t : 20;
|
|
|
+ __IOM uint32_t ABT : 1; /*!< [29..29] Abort */
|
|
|
+ __IOM uint32_t RSM : 1; /*!< [30..30] Resume */
|
|
|
+ __IOM uint32_t BUSE : 1; /*!< [31..31] Bus Enable */
|
|
|
+ } BCTL_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t MSDVAD; /*!< (@ 0x00000018) Master Device Address Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 16;
|
|
|
+ __IOM uint32_t MDYAD : 7; /*!< [22..16] Master Dynamic Address */
|
|
|
+ uint32_t : 8;
|
|
|
+ __IOM uint32_t MDYADV : 1; /*!< [31..31] Master Dynamic Address Valid */
|
|
|
+ } MSDVAD_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED1;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */
|
|
|
+ __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */
|
|
|
+ __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */
|
|
|
+ __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */
|
|
|
+ __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */
|
|
|
+ __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */
|
|
|
+ __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */
|
|
|
+ uint32_t : 9;
|
|
|
+ __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */
|
|
|
+ uint32_t : 15;
|
|
|
+ } RSTCTL_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t PRSST; /*!< (@ 0x00000024) Present State Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t CRMS : 1; /*!< [2..2] Current Master */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IM uint32_t TRMD : 1; /*!< [4..4] Transmit/Receive Mode */
|
|
|
+ uint32_t : 2;
|
|
|
+ __OM uint32_t PRSSTWP : 1; /*!< [7..7] Present State Write Protect */
|
|
|
+ uint32_t : 24;
|
|
|
+ } PRSST_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED2[2];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t INST; /*!< (@ 0x00000030) Internal Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 10;
|
|
|
+ __IOM uint32_t INEF : 1; /*!< [10..10] Internal Error Flag */
|
|
|
+ uint32_t : 21;
|
|
|
+ } INST_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t INSTE; /*!< (@ 0x00000034) Internal Status Enable Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 10;
|
|
|
+ __IOM uint32_t INEE : 1; /*!< [10..10] Internal Error Enable */
|
|
|
+ uint32_t : 21;
|
|
|
+ } INSTE_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t INIE; /*!< (@ 0x00000038) Internal Interrupt Enable Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 10;
|
|
|
+ __IOM uint32_t INEIE : 1; /*!< [10..10] Internal Error Interrupt Enable */
|
|
|
+ uint32_t : 21;
|
|
|
+ } INIE_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t INSTFC; /*!< (@ 0x0000003C) Internal Status Force Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 10;
|
|
|
+ __OM uint32_t INEFC : 1; /*!< [10..10] Internal Error Force */
|
|
|
+ uint32_t : 21;
|
|
|
+ } INSTFC_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED3;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t DVCT; /*!< (@ 0x00000044) Device Characteristic Table Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 19;
|
|
|
+ __IM uint32_t IDX : 5; /*!< [23..19] DCT Table Index */
|
|
|
+ uint32_t : 8;
|
|
|
+ } DVCT_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED4[4];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t IBINCTL; /*!< (@ 0x00000058) IBI Notify Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t NRHJCTL : 1; /*!< [0..0] Notify Rejected Hot-Join Control */
|
|
|
+ __IOM uint32_t NRMRCTL : 1; /*!< [1..1] Notify Rejected Master Request Control */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t NRSIRCTL : 1; /*!< [3..3] Notify Rejected Slave Interrupt Request Control */
|
|
|
+ uint32_t : 28;
|
|
|
+ } IBINCTL_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED5;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t BFCTL; /*!< (@ 0x00000060) Bus Function Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t MALE : 1; /*!< [0..0] Master Arbitration-Lost Detection Enable */
|
|
|
+ __IOM uint32_t NALE : 1; /*!< [1..1] NACK Transmission Arbitration-Lost Detection Enable */
|
|
|
+ __IOM uint32_t SALE : 1; /*!< [2..2] Slave Arbitration-Lost Detection Enable */
|
|
|
+ uint32_t : 5;
|
|
|
+ __IOM uint32_t SCSYNE : 1; /*!< [8..8] SCL Synchronous Circuit Enable */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t SMBS : 1; /*!< [12..12] SMBus/I2C Bus Selection */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t FMPE : 1; /*!< [14..14] Fast-mode Plus Enable */
|
|
|
+ __IOM uint32_t HSME : 1; /*!< [15..15] High Speed Mode Enable */
|
|
|
+ uint32_t : 16;
|
|
|
+ } BFCTL_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SVCTL; /*!< (@ 0x00000064) Slave Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t GCAE : 1; /*!< [0..0] General Call Address Enable */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t HSMCE : 1; /*!< [5..5] Hs-mode Master Code Enable */
|
|
|
+ __IOM uint32_t DVIDE : 1; /*!< [6..6] Device-ID Address Enable */
|
|
|
+ uint32_t : 8;
|
|
|
+ __IOM uint32_t HOAE : 1; /*!< [15..15] Host Address Enable */
|
|
|
+ __IOM uint32_t SVAEn : 1; /*!< [16..16] Slave Address Enable n (n = 0) */
|
|
|
+ uint32_t : 15;
|
|
|
+ } SVCTL_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED6[2];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t REFCKCTL; /*!< (@ 0x00000070) Reference Clock Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t IREFCKS : 3; /*!< [2..0] Internal Reference Clock Selection */
|
|
|
+ uint32_t : 29;
|
|
|
+ } REFCKCTL_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t STDBR; /*!< (@ 0x00000074) Standard Bit Rate Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t SBRLO : 8; /*!< [7..0] Count value of the Low-level period of SCL clock */
|
|
|
+ __IOM uint32_t SBRHO : 8; /*!< [15..8] Count value of the High-level period of SCL clock */
|
|
|
+ __IOM uint32_t SBRLP : 6; /*!< [21..16] Standard Bit Rate Low-level Period Push-Pull */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t SBRHP : 6; /*!< [29..24] Standard Bit Rate High-Level Period Push-Pull */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t DSBRPO : 1; /*!< [31..31] Double the Standard Bit Rate Period for Open-Drain */
|
|
|
+ } STDBR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t EXTBR; /*!< (@ 0x00000078) Extended Bit Rate Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t EBRLO : 8; /*!< [7..0] Extended Bit Rate Low-Level Period Open-Drain */
|
|
|
+ __IOM uint32_t EBRHO : 8; /*!< [15..8] Extended Bit Rate High-Level Period Open-Drain */
|
|
|
+ __IOM uint32_t EBRLP : 6; /*!< [21..16] Extended Bit Rate Low-Level Period Push-Pull */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate Low-Level Period Push-Pull */
|
|
|
+ uint32_t : 2;
|
|
|
+ } EXTBR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t BFRECDT; /*!< (@ 0x0000007C) Bus Free Condition Detection Time Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t FRECYC : 9; /*!< [8..0] Bus Free Condition Detection Cycle */
|
|
|
+ uint32_t : 23;
|
|
|
+ } BFRECDT_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t BAVLCDT; /*!< (@ 0x00000080) Bus Available Condition Detection Time Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t AVLCYC : 9; /*!< [8..0] Bus Available Condition Detection Cycle */
|
|
|
+ uint32_t : 23;
|
|
|
+ } BAVLCDT_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t BIDLCDT; /*!< (@ 0x00000084) Bus Idle Condition Detection Time Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t IDLCYC : 18; /*!< [17..0] Bus Idle Condition Detection Cycle */
|
|
|
+ uint32_t : 14;
|
|
|
+ } BIDLCDT_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t OUTCTL; /*!< (@ 0x00000088) Output Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t SDOC : 1; /*!< [0..0] SDA Output Control */
|
|
|
+ __IOM uint32_t SCOC : 1; /*!< [1..1] SCL Output Control */
|
|
|
+ __OM uint32_t SOCWP : 1; /*!< [2..2] SCL/SDA Output Control Write Protect */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t EXCYC : 1; /*!< [4..4] Extra SCL Clock Cycle Output */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t SDOD : 3; /*!< [10..8] SDA Output Delay */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t SDODCS : 1; /*!< [15..15] SDA Output Delay Clock Source Selection */
|
|
|
+ uint32_t : 16;
|
|
|
+ } OUTCTL_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t INCTL; /*!< (@ 0x0000008C) Input Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t DNFS : 4; /*!< [3..0] Digital Noise Filter Stage Selection */
|
|
|
+ __IOM uint32_t DNFE : 1; /*!< [4..4] Digital Noise Filter Circuit Enable */
|
|
|
+ uint32_t : 27;
|
|
|
+ } INCTL_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t TMOCTL; /*!< (@ 0x00000090) Timeout Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t TODTS : 2; /*!< [1..0] Timeout Detection Time Selection */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t TOLCTL : 1; /*!< [4..4] Timeout L Count Control */
|
|
|
+ __IOM uint32_t TOHCTL : 1; /*!< [5..5] Timeout H Count Control */
|
|
|
+ __IOM uint32_t TOMDS : 2; /*!< [7..6] Timeout Operation Mode Selection */
|
|
|
+ uint32_t : 24;
|
|
|
+ } TMOCTL_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED7;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t WUCTL; /*!< (@ 0x00000098) Wake Up Unit Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t WUACKS : 1; /*!< [0..0] Wake-Up Acknowledge Selection */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t WUANFS : 1; /*!< [4..4] Wake-Up Analog Noise Filter Selection */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t WUFSYNE : 1; /*!< [6..6] Wake-Up function PCLKA Synchronous Enable */
|
|
|
+ __IOM uint32_t WUFE : 1; /*!< [7..7] Wake-Up function Enable. */
|
|
|
+ uint32_t : 24;
|
|
|
+ } WUCTL_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED8;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t ACKCTL; /*!< (@ 0x000000A0) Acknowledge Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t ACKR : 1; /*!< [0..0] Acknowledge Reception */
|
|
|
+ __IOM uint32_t ACKT : 1; /*!< [1..1] Acknowledge Transmission */
|
|
|
+ __OM uint32_t ACKTWP : 1; /*!< [2..2] ACKT Write Protect */
|
|
|
+ uint32_t : 29;
|
|
|
+ } ACKCTL_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SCSTRCTL; /*!< (@ 0x000000A4) SCL Stretch Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t ACKTWE : 1; /*!< [0..0] Acknowledge Transmission Wait Enable */
|
|
|
+ __IOM uint32_t RWE : 1; /*!< [1..1] Receive Wait Enable */
|
|
|
+ uint32_t : 30;
|
|
|
+ } SCSTRCTL_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED9[2];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SCSTLCTL; /*!< (@ 0x000000B0) SCL Stalling Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t STLCYC : 16; /*!< [15..0] Stalling Cycle */
|
|
|
+ uint32_t : 12;
|
|
|
+ __IOM uint32_t AAPE : 1; /*!< [28..28] Assigend Address Phase Enable */
|
|
|
+ __IOM uint32_t TRAPE : 1; /*!< [29..29] Transition Phase Enable */
|
|
|
+ __IOM uint32_t PARPE : 1; /*!< [30..30] Parity Phase Enable */
|
|
|
+ __IOM uint32_t ACKPE : 1; /*!< [31..31] ACK phase Enable */
|
|
|
+ } SCSTLCTL_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED10[3];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SVTDLG0; /*!< (@ 0x000000C0) Slave Transfer Data Length Register 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 16;
|
|
|
+ __IOM uint32_t STDLG : 16; /*!< [31..16] Slave Transfer Data Length */
|
|
|
+ } SVTDLG0_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED11[31];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CNDCTL; /*!< (@ 0x00000140) Condition Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t STCND : 1; /*!< [0..0] START (S) Condition Issuance */
|
|
|
+ __IOM uint32_t SRCND : 1; /*!< [1..1] Repeated START (Sr) Condition Issuance */
|
|
|
+ __IOM uint32_t SPCND : 1; /*!< [2..2] STOP (P) Condition Issuance */
|
|
|
+ uint32_t : 29;
|
|
|
+ } CNDCTL_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED12[3];
|
|
|
+ __OM uint32_t NCMDQP; /*!< (@ 0x00000150) Normal Command Queue Port Register */
|
|
|
+ __IM uint32_t NRSPQP; /*!< (@ 0x00000154) Normal Response Queue Port Register */
|
|
|
+ __IOM uint32_t NTDTBP0; /*!< (@ 0x00000158) Normal Transfer Data Buffer Port Register 0 */
|
|
|
+ __IM uint32_t RESERVED13[8];
|
|
|
+ __IOM uint32_t NIBIQP; /*!< (@ 0x0000017C) Normal IBI Queue Port Register */
|
|
|
+ __IM uint32_t NRSQP; /*!< (@ 0x00000180) Normal Receive Status Queue Port Register */
|
|
|
+ __IM uint32_t RESERVED14[3];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t NQTHCTL; /*!< (@ 0x00000190) Normal Queue Threshold Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CMDQTH : 8; /*!< [7..0] Normal Command Ready Queue Threshold */
|
|
|
+ __IOM uint32_t RSPQTH : 8; /*!< [15..8] Normal Response Queue Threshold */
|
|
|
+ __IOM uint32_t IBIDSSZ : 8; /*!< [23..16] Normal IBI Data Segment Size */
|
|
|
+ __IOM uint32_t IBIQTH : 8; /*!< [31..24] Normal IBI Queue Threshold */
|
|
|
+ } NQTHCTL_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t NTBTHCTL0; /*!< (@ 0x00000194) Normal Transfer Data Buffer Threshold Control
|
|
|
+ * Register 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t TXDBTH : 3; /*!< [2..0] Normal Transmit Data Buffer Threshold */
|
|
|
+ uint32_t : 5;
|
|
|
+ __IOM uint32_t RXDBTH : 3; /*!< [10..8] Normal Receive Data Buffer Threshold */
|
|
|
+ uint32_t : 5;
|
|
|
+ __IOM uint32_t TXSTTH : 3; /*!< [18..16] Normal Tx Start Threshold */
|
|
|
+ uint32_t : 5;
|
|
|
+ __IOM uint32_t RXSTTH : 3; /*!< [26..24] Normal Rx Start Threshold */
|
|
|
+ uint32_t : 5;
|
|
|
+ } NTBTHCTL0_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED15[10];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t NRQTHCTL; /*!< (@ 0x000001C0) Normal Receive Status Queue Threshold Control
|
|
|
+ * Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t RSQTH : 8; /*!< [7..0] Normal Receive Status Queue Threshold */
|
|
|
+ uint32_t : 24;
|
|
|
+ } NRQTHCTL_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED16[3];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t BST; /*!< (@ 0x000001D0) Bus Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t STCNDDF : 1; /*!< [0..0] START condition Detection Flag */
|
|
|
+ __IOM uint32_t SPCNDDF : 1; /*!< [1..1] STOP condition Detection Flag */
|
|
|
+ __IOM uint32_t HDREXDF : 1; /*!< [2..2] HDR Exit Pattern Detection Flag */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t NACKDF : 1; /*!< [4..4] NACK Detection Flag */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t TENDF : 1; /*!< [8..8] Transmit End Flag */
|
|
|
+ uint32_t : 7;
|
|
|
+ __IOM uint32_t ALF : 1; /*!< [16..16] Arbitration Lost Flag */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t TODF : 1; /*!< [20..20] Timeout Detection Flag */
|
|
|
+ uint32_t : 11;
|
|
|
+ } BST_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t BSTE; /*!< (@ 0x000001D4) Bus Status Enable Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t STCNDDE : 1; /*!< [0..0] START condition Detection Enable */
|
|
|
+ __IOM uint32_t SPCNDDE : 1; /*!< [1..1] STOP condition Detection Enable */
|
|
|
+ __IOM uint32_t HDREXDE : 1; /*!< [2..2] HDR Exit Pattern Detection Enable */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t NACKDE : 1; /*!< [4..4] NACK Detection Enable */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t TENDE : 1; /*!< [8..8] Transmit End Enable */
|
|
|
+ uint32_t : 7;
|
|
|
+ __IOM uint32_t ALE : 1; /*!< [16..16] Arbitration Lost Enable */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t TODE : 1; /*!< [20..20] Timeout Detection Enable */
|
|
|
+ uint32_t : 11;
|
|
|
+ } BSTE_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t BIE; /*!< (@ 0x000001D8) Bus Interrupt Enable Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t STCNDDIE : 1; /*!< [0..0] START condition Detection Interrupt Enable */
|
|
|
+ __IOM uint32_t SPCNDDIE : 1; /*!< [1..1] STOP condition Detection Interrupt Enable */
|
|
|
+ __IOM uint32_t HDREXDIE : 1; /*!< [2..2] HDR Exit Pattern Detection Interrupt Enable */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t NACKDIE : 1; /*!< [4..4] NACK Detection Interrupt Enable */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t TENDIE : 1; /*!< [8..8] Transmit End Interrupt Enable */
|
|
|
+ uint32_t : 7;
|
|
|
+ __IOM uint32_t ALIE : 1; /*!< [16..16] Arbitration Lost Interrupt Enable */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t TODIE : 1; /*!< [20..20] Timeout Detection Interrupt Enable */
|
|
|
+ uint32_t : 11;
|
|
|
+ } BIE_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */
|
|
|
+ __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */
|
|
|
+ __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */
|
|
|
+ uint32_t : 1;
|
|
|
+ __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */
|
|
|
+ uint32_t : 3;
|
|
|
+ __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */
|
|
|
+ uint32_t : 7;
|
|
|
+ __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */
|
|
|
+ uint32_t : 3;
|
|
|
+ __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */
|
|
|
+ uint32_t : 11;
|
|
|
+ } BSTFC_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t NTST; /*!< (@ 0x000001E0) Normal Transfer Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t TDBEF0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Flag 0 */
|
|
|
+ __IOM uint32_t RDBFF0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Flag 0 */
|
|
|
+ __IOM uint32_t IBIQEFF : 1; /*!< [2..2] Normal IBI Queue Empty/Full Flag */
|
|
|
+ __IOM uint32_t CMDQEF : 1; /*!< [3..3] Normal Command Queue Empty Flag */
|
|
|
+ __IOM uint32_t RSPQFF : 1; /*!< [4..4] Normal Response Queue Full Flag */
|
|
|
+ __IOM uint32_t TABTF : 1; /*!< [5..5] Normal Transfer Abort Flag */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t TEF : 1; /*!< [9..9] Normal Transfer Error Flag */
|
|
|
+ uint32_t : 10;
|
|
|
+ __IOM uint32_t RSQFF : 1; /*!< [20..20] Normal Receive Status Queue Full Flag */
|
|
|
+ uint32_t : 11;
|
|
|
+ } NTST_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t NTSTE; /*!< (@ 0x000001E4) Normal Transfer Status Enable Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t TDBEE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Enable 0 */
|
|
|
+ __IOM uint32_t RDBFE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Enable 0 */
|
|
|
+ __IOM uint32_t IBIQEFE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Enable */
|
|
|
+ __IOM uint32_t CMDQEE : 1; /*!< [3..3] Normal Command Queue Empty Enable */
|
|
|
+ __IOM uint32_t RSPQFE : 1; /*!< [4..4] Normal Response Queue Full Enable */
|
|
|
+ __IOM uint32_t TABTE : 1; /*!< [5..5] Normal Transfer Abort Enable */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t TEE : 1; /*!< [9..9] Normal Transfer Error Enable */
|
|
|
+ uint32_t : 10;
|
|
|
+ __IOM uint32_t RSQFE : 1; /*!< [20..20] Normal Receive Status Queue Full Enable */
|
|
|
+ uint32_t : 11;
|
|
|
+ } NTSTE_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t NTIE; /*!< (@ 0x000001E8) Normal Transfer Interrupt Enable Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t TDBEIE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Interrupt Enable 0 */
|
|
|
+ __IOM uint32_t RDBFIE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Interrupt Enable 0 */
|
|
|
+ __IOM uint32_t IBIQEFIE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Interrupt Enable */
|
|
|
+ __IOM uint32_t CMDQEIE : 1; /*!< [3..3] Normal Command Queue Empty Interrupt Enable */
|
|
|
+ __IOM uint32_t RSPQFIE : 1; /*!< [4..4] Normal Response Queue Full Interrupt Enable */
|
|
|
+ __IOM uint32_t TABTIE : 1; /*!< [5..5] Normal Transfer Abort Interrupt Enable */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t TEIE : 1; /*!< [9..9] Normal Transfer Error Interrupt Enable */
|
|
|
+ uint32_t : 10;
|
|
|
+ __IOM uint32_t RSQFIE : 1; /*!< [20..20] Normal Receive Status Queue Full Interrupt Enable */
|
|
|
+ uint32_t : 11;
|
|
|
+ } NTIE_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t NTSTFC; /*!< (@ 0x000001EC) Normal Transfer Status Force Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __OM uint32_t TDBEFC0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Force 0 */
|
|
|
+ __OM uint32_t RDBFFC0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Force 0 */
|
|
|
+ __OM uint32_t IBIQEFFC : 1; /*!< [2..2] Normal IBI Queue Empty/Full Force */
|
|
|
+ __OM uint32_t CMDQEFC : 1; /*!< [3..3] Normal Command Queue Empty Force */
|
|
|
+ __OM uint32_t RSPQFFC : 1; /*!< [4..4] Normal Response Queue Full Force */
|
|
|
+ __OM uint32_t TABTFC : 1; /*!< [5..5] Normal Transfer Abort Force */
|
|
|
+ uint32_t : 3;
|
|
|
+ __OM uint32_t TEFC : 1; /*!< [9..9] Normal Transfer Error Force */
|
|
|
+ uint32_t : 10;
|
|
|
+ __OM uint32_t RSQFFC : 1; /*!< [20..20] Normal Receive Status Queue Full Force */
|
|
|
+ uint32_t : 11;
|
|
|
+ } NTSTFC_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED17[8];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t BCST; /*!< (@ 0x00000210) Bus Condition Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t BFREF : 1; /*!< [0..0] Bus Free Detection Flag */
|
|
|
+ __IM uint32_t BAVLF : 1; /*!< [1..1] Bus Available Detection Flag */
|
|
|
+ __IM uint32_t BIDLF : 1; /*!< [2..2] Bus Idle Detection Flag */
|
|
|
+ uint32_t : 29;
|
|
|
+ } BCST_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SVST; /*!< (@ 0x00000214) Slave Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t GCAF : 1; /*!< [0..0] General Call Address Detection Flag */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t HSMCF : 1; /*!< [5..5] Hs-mode Master Code Detection Flag */
|
|
|
+ __IOM uint32_t DVIDF : 1; /*!< [6..6] Device-ID Address Detection Flag */
|
|
|
+ uint32_t : 8;
|
|
|
+ __IOM uint32_t HOAF : 1; /*!< [15..15] Host Address Detection Flag */
|
|
|
+ __IOM uint32_t SVAFn : 1; /*!< [16..16] Slave Address Detection Flag n (n = 0) */
|
|
|
+ uint32_t : 15;
|
|
|
+ } SVST_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t WUST; /*!< (@ 0x00000218) Wake Up Unit Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag. */
|
|
|
+ uint32_t : 31;
|
|
|
+ } WUST_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED18[2];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t DATBAS0; /*!< (@ 0x00000224) Device Address Table Basic Register 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */
|
|
|
+ uint32_t : 5;
|
|
|
+ __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */
|
|
|
+ __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */
|
|
|
+ __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */
|
|
|
+ __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */
|
|
|
+ __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */
|
|
|
+ uint32_t : 5;
|
|
|
+ __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */
|
|
|
+ __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */
|
|
|
+ } DATBAS0_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED19;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t DATBAS1; /*!< (@ 0x0000022C) Device Address Table Basic Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */
|
|
|
+ uint32_t : 5;
|
|
|
+ __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */
|
|
|
+ __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */
|
|
|
+ __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */
|
|
|
+ __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */
|
|
|
+ __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */
|
|
|
+ uint32_t : 5;
|
|
|
+ __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */
|
|
|
+ __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */
|
|
|
+ } DATBAS1_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED20;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t DATBAS2; /*!< (@ 0x00000234) Device Address Table Basic Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */
|
|
|
+ uint32_t : 5;
|
|
|
+ __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */
|
|
|
+ __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */
|
|
|
+ __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */
|
|
|
+ __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */
|
|
|
+ __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */
|
|
|
+ uint32_t : 5;
|
|
|
+ __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */
|
|
|
+ __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */
|
|
|
+ } DATBAS2_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED21;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t DATBAS3; /*!< (@ 0x0000023C) Device Address Table Basic Register 3 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */
|
|
|
+ uint32_t : 5;
|
|
|
+ __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */
|
|
|
+ __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */
|
|
|
+ __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */
|
|
|
+ __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */
|
|
|
+ __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */
|
|
|
+ uint32_t : 5;
|
|
|
+ __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */
|
|
|
+ __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */
|
|
|
+ } DATBAS3_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED22[24];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t EXDATBAS; /*!< (@ 0x000002A0) Extended Device Address Table Basic Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t EDSTAD : 7; /*!< [6..0] Extended Device Static Address */
|
|
|
+ uint32_t : 9;
|
|
|
+ __IOM uint32_t EDDYAD : 8; /*!< [23..16] Extended Device I3C Dynamic Address */
|
|
|
+ uint32_t : 5;
|
|
|
+ __IOM uint32_t EDNACK : 2; /*!< [30..29] Extended Device NACK Retry Count */
|
|
|
+ __IOM uint32_t EDTYP : 1; /*!< [31..31] Extended Device Type */
|
|
|
+ } EXDATBAS_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED23[3];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SDATBAS0; /*!< (@ 0x000002B0) Slave Device Address Table Basic Register 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */
|
|
|
+ __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */
|
|
|
+ uint32_t : 9;
|
|
|
+ } SDATBAS0_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SDATBAS1; /*!< (@ 0x000002B4) Slave Device Address Table Basic Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */
|
|
|
+ __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */
|
|
|
+ uint32_t : 9;
|
|
|
+ } SDATBAS1_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SDATBAS2; /*!< (@ 0x000002B8) Slave Device Address Table Basic Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */
|
|
|
+ __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */
|
|
|
+ uint32_t : 9;
|
|
|
+ } SDATBAS2_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED24[5];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t MSDCT0; /*!< (@ 0x000002D0) Master Device Characteristic Table Register 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 8;
|
|
|
+ __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */
|
|
|
+ __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */
|
|
|
+ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */
|
|
|
+ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */
|
|
|
+ uint32_t : 16;
|
|
|
+ } MSDCT0_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t MSDCT1; /*!< (@ 0x000002D4) Master Device Characteristic Table Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 8;
|
|
|
+ __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */
|
|
|
+ __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */
|
|
|
+ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */
|
|
|
+ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */
|
|
|
+ uint32_t : 16;
|
|
|
+ } MSDCT1_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t MSDCT2; /*!< (@ 0x000002D8) Master Device Characteristic Table Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 8;
|
|
|
+ __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */
|
|
|
+ __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */
|
|
|
+ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */
|
|
|
+ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */
|
|
|
+ uint32_t : 16;
|
|
|
+ } MSDCT2_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t MSDCT3; /*!< (@ 0x000002DC) Master Device Characteristic Table Register 3 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 8;
|
|
|
+ __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */
|
|
|
+ __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */
|
|
|
+ __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */
|
|
|
+ __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */
|
|
|
+ uint32_t : 16;
|
|
|
+ } MSDCT3_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED25[16];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SVDCT; /*!< (@ 0x00000320) Slave Device Characteristic Table Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t TDCR : 8; /*!< [7..0] Transfar Device Characteristic Register */
|
|
|
+ __IOM uint32_t TBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */
|
|
|
+ __IOM uint32_t TBCR1 : 1; /*!< [9..9] IBI Request Capable */
|
|
|
+ __IOM uint32_t TBCR2 : 1; /*!< [10..10] IBI Payload */
|
|
|
+ __IOM uint32_t TBCR3 : 1; /*!< [11..11] Offline Capable */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t TBCR76 : 2; /*!< [15..14] Device Role */
|
|
|
+ uint32_t : 16;
|
|
|
+ } SVDCT_b;
|
|
|
+ };
|
|
|
+ __IOM uint32_t SDCTPIDL; /*!< (@ 0x00000324) Slave Device Characteristic Table Provisional
|
|
|
+ * ID Low Register */
|
|
|
+ __IOM uint32_t SDCTPIDH; /*!< (@ 0x00000328) Slave Device Characteristic Table Provisional
|
|
|
+ * ID High Register */
|
|
|
+ __IM uint32_t RESERVED26;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t SVDVAD0; /*!< (@ 0x00000330) Slave Device Address Register 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 16;
|
|
|
+ __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */
|
|
|
+ __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */
|
|
|
+ } SVDVAD0_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED27[7];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CSECMD; /*!< (@ 0x00000350) CCC Slave Events Command Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t SVIRQE : 1; /*!< [0..0] Slave Interrupt Requests Enable */
|
|
|
+ __IOM uint32_t MSRQE : 1; /*!< [1..1] Mastership Requests Enable */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t HJEVE : 1; /*!< [3..3] Hot-Join Event Enable */
|
|
|
+ uint32_t : 28;
|
|
|
+ } CSECMD_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CEACTST; /*!< (@ 0x00000354) CCC Enter Activity State Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t ACTST : 4; /*!< [3..0] Activity State */
|
|
|
+ uint32_t : 28;
|
|
|
+ } CEACTST_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CMWLG; /*!< (@ 0x00000358) CCC Max Write Length Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t MWLG : 16; /*!< [15..0] Max Write Length */
|
|
|
+ uint32_t : 16;
|
|
|
+ } CMWLG_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CMRLG; /*!< (@ 0x0000035C) CCC Max Read Length Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t MRLG : 16; /*!< [15..0] Max Read Length */
|
|
|
+ __IOM uint32_t IBIPSZ : 8; /*!< [23..16] IBI Payload Size */
|
|
|
+ uint32_t : 8;
|
|
|
+ } CMRLG_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t CETSTMD; /*!< (@ 0x00000360) CCC Enter Test Mode Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t TSTMD : 8; /*!< [7..0] Test Mode */
|
|
|
+ uint32_t : 24;
|
|
|
+ } CETSTMD_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CGDVST; /*!< (@ 0x00000364) CCC Get Device Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t PNDINT : 4; /*!< [3..0] Pending Interrupt */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t PRTE : 1; /*!< [5..5] Protocol Error */
|
|
|
+ __IOM uint32_t ACTMD : 2; /*!< [7..6] Slave Device's current Activity Mode */
|
|
|
+ __IOM uint32_t VDRSV : 8; /*!< [15..8] Vendor Reserved */
|
|
|
+ uint32_t : 16;
|
|
|
+ } CGDVST_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CMDSPW; /*!< (@ 0x00000368) CCC Max Data Speed W (Write) Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t MSWDR : 3; /*!< [2..0] Maximum Sustained Write Data Rate */
|
|
|
+ uint32_t : 29;
|
|
|
+ } CMDSPW_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CMDSPR; /*!< (@ 0x0000036C) CCC Max Data Speed R (Read) Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t MSRDR : 3; /*!< [2..0] Maximum Sustained Read Data Rate */
|
|
|
+ __IOM uint32_t CDTTIM : 3; /*!< [5..3] Clock to Data Turnaround Time (TSCO) */
|
|
|
+ uint32_t : 26;
|
|
|
+ } CMDSPR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CMDSPT; /*!< (@ 0x00000370) CCC Max Data Speed T (Turnaround) Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t MRTTIM : 24; /*!< [23..0] Maximum Read Turnaround Time */
|
|
|
+ uint32_t : 7;
|
|
|
+ __IOM uint32_t MRTE : 1; /*!< [31..31] Maximum Read Turnaround Time Enable */
|
|
|
+ } CMDSPT_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode)
|
|
|
+ * Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 8;
|
|
|
+ __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */
|
|
|
+ __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */
|
|
|
+ uint32_t : 8;
|
|
|
+ } CETSM_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED28[2];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t BITCNT; /*!< (@ 0x00000380) Bit Count Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t BCNT : 5; /*!< [4..0] Bit Counter */
|
|
|
+ uint32_t : 2;
|
|
|
+ __OM uint32_t BCNTWP : 1; /*!< [7..7] BCNT Write Protect */
|
|
|
+ uint32_t : 24;
|
|
|
+ } BITCNT_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED29[4];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t NQSTLV; /*!< (@ 0x00000394) Normal Queue Status Level Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t CMDQFLV : 8; /*!< [7..0] Normal Command Queue Free Level */
|
|
|
+ __IM uint32_t RSPQLV : 8; /*!< [15..8] Normal Response Queue Level */
|
|
|
+ __IM uint32_t IBIQLV : 8; /*!< [23..16] Normal IBI Queue Level */
|
|
|
+ __IM uint32_t IBISCNT : 5; /*!< [28..24] Normal IBI Status Count */
|
|
|
+ uint32_t : 3;
|
|
|
+ } NQSTLV_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t TDBFLV : 8; /*!< [7..0] Normal Transmit Data Buffer Free Level */
|
|
|
+ __IM uint32_t RDBLV : 8; /*!< [15..8] Normal Receive Data Buffer Level */
|
|
|
+ uint32_t : 16;
|
|
|
+ } NDBSTLV0_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED30[9];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t NRSQSTLV; /*!< (@ 0x000003C0) Normal Receive Status Queue Status Level Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t RSQLV : 8; /*!< [7..0] Normal Receive Status Queue Level */
|
|
|
+ uint32_t : 24;
|
|
|
+ } NRSQSTLV_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED31[2];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t PRSTDBG; /*!< (@ 0x000003CC) Present State Debug Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t SCILV : 1; /*!< [0..0] SCL Line Signal Level */
|
|
|
+ __IM uint32_t SDILV : 1; /*!< [1..1] SDA Line Signal Level */
|
|
|
+ __IM uint32_t SCOLV : 1; /*!< [2..2] SCL Output Level */
|
|
|
+ __IM uint32_t SDOLV : 1; /*!< [3..3] SDA Output Level */
|
|
|
+ uint32_t : 28;
|
|
|
+ } PRSTDBG_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t MSERRCNT; /*!< (@ 0x000003D0) Master Error Counters Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t M2ECNT : 8; /*!< [7..0] M2 Error Counter */
|
|
|
+ uint32_t : 24;
|
|
|
+ } MSERRCNT_b;
|
|
|
+ };
|
|
|
+} R_I3C0_Type; /*!< Size = 980 (0x3d4) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_MPU_MMPU ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Bus Master MPU (R_MPU_MMPU)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x40000000) R_MPU_MMPU Structure */
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t OAD; /*!< (@ 0x00000000) MMPU Operation After Detection Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */
|
|
|
+ uint16_t : 7;
|
|
|
+ __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not
|
|
|
+ * stored. */
|
|
|
+ } OAD_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t OADPT; /*!< (@ 0x00000004) MMPU Operation After Detection Protect Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */
|
|
|
+ uint16_t : 7;
|
|
|
+ __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not
|
|
|
+ * stored. */
|
|
|
+ } OADPT_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED1;
|
|
|
+ __IM uint32_t RESERVED2[62];
|
|
|
+ __IOM R_MPU_MMPU_GROUP_Type DMAC0; /*!< (@ 0x00000100) DMAC0 MMPU Registers */
|
|
|
+ __IOM R_MPU_MMPU_GROUP_Type DMAC1; /*!< (@ 0x00000300) DMAC1 MMPU Registers */
|
|
|
+ __IOM R_MPU_MMPU_GROUP_Type EDMAC; /*!< (@ 0x00000500) EDMAC MMPU Registers */
|
|
|
+ __IOM R_MPU_MMPU_GROUP_Type GLCDC; /*!< (@ 0x00000700) GLCDC MMPU Registers */
|
|
|
+ __IOM R_MPU_MMPU_GROUP_Type DRW; /*!< (@ 0x00000900) DRW MMPU Registers */
|
|
|
+ __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers */
|
|
|
+ __IOM R_MPU_MMPU_GROUP_Type CEU; /*!< (@ 0x00000D00) CEU MMPU Registers */
|
|
|
+ __IOM R_MPU_MMPU_GROUP_Type MIPI_CSI; /*!< (@ 0x00000F00) MIPI_CSI MMPU Registers */
|
|
|
+ __IOM R_MPU_MMPU_GROUP_Type NPU; /*!< (@ 0x00001100) NPU MMPU Registers */
|
|
|
+} R_MPU_MMPU_Type; /*!< Size = 4864 (0x1300) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_MPU_SPMON ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief CPU Stack Pointer Monitor (R_MPU_SPMON)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */
|
|
|
+{
|
|
|
+ __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */
|
|
|
+} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_MSTP ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief System-Module Stop (R_MSTP)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x40203000) R_MSTP Structure */
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t MSTPCRA; /*!< (@ 0x00000000) Module Stop Control Register A */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t MSTPA0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPA1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPA2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPA3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPA4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPA5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPA6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPA8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPA9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ } MSTPCRA_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t MSTPCRB; /*!< (@ 0x00000004) Module Stop Control Register B */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t MSTPB0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPB1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPB2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPB3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPB4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPB5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPB7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPB8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPB9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPB10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPB13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPB14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPB15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPB16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPB17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPB20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPB21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ } MSTPCRB_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t MSTPCRC; /*!< (@ 0x00000008) Module Stop Control Register C */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t MSTPC0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPC1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPC2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPC5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPC6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPC7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPC8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPC9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPC10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPC15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPC16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPC17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPC18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPC19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPC21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPC22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPC23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPC24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPC25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPC26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPC27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPC29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPC30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPC31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ } MSTPCRC_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t MSTPCRD; /*!< (@ 0x0000000C) Module Stop Control Register D */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t MSTPD0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPD1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPD2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPD3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPD4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPD5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPD6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPD7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPD8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPD9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPD10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPD14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPD15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPD16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPD17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPD18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPD19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPD20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPD21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPD23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPD24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPD25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPD26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPD27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPD28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPD30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ } MSTPCRD_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t MSTPCRE; /*!< (@ 0x00000010) Module Stop Control Register E */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t MSTPE0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPE1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPE2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPE3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPE4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPE5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPE6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPE7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPE8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPE9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPE10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPE11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPE12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPE13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPE16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPE17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPE18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPE19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPE20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPE21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPE22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPE23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPE24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPE25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPE26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPE27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPE28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPE29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPE30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPE31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ } MSTPCRE_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t LSMRWDIS; /*!< (@ 0x00000010) Low Speed Module R/W Disable Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t RTCRWDIS : 1; /*!< [0..0] RTC Register R/W Enable Control */
|
|
|
+ __IOM uint16_t WDTDIS : 1; /*!< [1..1] WDT Operate Clock Control */
|
|
|
+ __IOM uint16_t IWDTIDS : 1; /*!< [2..2] IWDT Register Clock Control */
|
|
|
+ uint16_t : 4;
|
|
|
+ __IOM uint16_t WREN : 1; /*!< [7..7] Write Enable for bits [2:0] */
|
|
|
+ __OM uint16_t PRKEY : 8; /*!< [15..8] LSMRWDIS Key Code */
|
|
|
+ } LSMRWDIS_b;
|
|
|
+ };
|
|
|
+ };
|
|
|
+} R_MSTP_Type; /*!< Size = 20 (0x14) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_PORT0 ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief I/O Ports (R_PORT0)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x40400000) R_PORT0 Structure */
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */
|
|
|
+ __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */
|
|
|
+ } PCNTR1_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t PDR; /*!< (@ 0x00000000) Data direction register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */
|
|
|
+ __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */
|
|
|
+ __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */
|
|
|
+ __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */
|
|
|
+ __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */
|
|
|
+ __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */
|
|
|
+ __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */
|
|
|
+ __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */
|
|
|
+ __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */
|
|
|
+ __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */
|
|
|
+ __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */
|
|
|
+ __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */
|
|
|
+ __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */
|
|
|
+ __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */
|
|
|
+ __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */
|
|
|
+ __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */
|
|
|
+ } PDR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t PODR; /*!< (@ 0x00000002) Output data register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */
|
|
|
+ __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */
|
|
|
+ __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */
|
|
|
+ __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */
|
|
|
+ __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */
|
|
|
+ __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */
|
|
|
+ __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */
|
|
|
+ __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */
|
|
|
+ __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */
|
|
|
+ __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */
|
|
|
+ __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */
|
|
|
+ __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */
|
|
|
+ __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */
|
|
|
+ __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */
|
|
|
+ __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */
|
|
|
+ __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */
|
|
|
+ } PODR_b;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */
|
|
|
+ __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */
|
|
|
+ } PCNTR2_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint16_t PIDR; /*!< (@ 0x00000004) Input data register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */
|
|
|
+ __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */
|
|
|
+ __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */
|
|
|
+ __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */
|
|
|
+ __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */
|
|
|
+ __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */
|
|
|
+ __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */
|
|
|
+ __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */
|
|
|
+ __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */
|
|
|
+ __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */
|
|
|
+ __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */
|
|
|
+ __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */
|
|
|
+ __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */
|
|
|
+ __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */
|
|
|
+ __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */
|
|
|
+ __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */
|
|
|
+ } PIDR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint16_t EIDR; /*!< (@ 0x00000006) Event input data register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */
|
|
|
+ __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */
|
|
|
+ __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */
|
|
|
+ __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */
|
|
|
+ __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */
|
|
|
+ __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */
|
|
|
+ __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */
|
|
|
+ __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */
|
|
|
+ __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */
|
|
|
+ __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */
|
|
|
+ __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */
|
|
|
+ __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */
|
|
|
+ __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */
|
|
|
+ __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */
|
|
|
+ __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */
|
|
|
+ __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */
|
|
|
+ } EIDR_b;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */
|
|
|
+ __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */
|
|
|
+ } PCNTR3_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __OM uint16_t POSR; /*!< (@ 0x00000008) Output reset register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */
|
|
|
+ __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */
|
|
|
+ __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */
|
|
|
+ __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */
|
|
|
+ __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */
|
|
|
+ __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */
|
|
|
+ __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */
|
|
|
+ __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */
|
|
|
+ __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */
|
|
|
+ __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */
|
|
|
+ __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */
|
|
|
+ __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */
|
|
|
+ __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */
|
|
|
+ __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */
|
|
|
+ __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */
|
|
|
+ __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */
|
|
|
+ } POSR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __OM uint16_t PORR; /*!< (@ 0x0000000A) Output set register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */
|
|
|
+ __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */
|
|
|
+ __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */
|
|
|
+ __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */
|
|
|
+ __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */
|
|
|
+ __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */
|
|
|
+ __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */
|
|
|
+ __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */
|
|
|
+ __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */
|
|
|
+ __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */
|
|
|
+ __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */
|
|
|
+ __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */
|
|
|
+ __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */
|
|
|
+ __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */
|
|
|
+ __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */
|
|
|
+ __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */
|
|
|
+ } PORR_b;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */
|
|
|
+ __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */
|
|
|
+ } PCNTR4_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t EOSR; /*!< (@ 0x0000000C) Event output reset register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */
|
|
|
+ __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */
|
|
|
+ __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */
|
|
|
+ __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */
|
|
|
+ __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */
|
|
|
+ __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */
|
|
|
+ __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */
|
|
|
+ __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */
|
|
|
+ __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */
|
|
|
+ __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */
|
|
|
+ __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */
|
|
|
+ __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */
|
|
|
+ __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */
|
|
|
+ __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */
|
|
|
+ __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */
|
|
|
+ __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */
|
|
|
+ } EOSR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t EORR; /*!< (@ 0x0000000E) Event output set register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */
|
|
|
+ __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */
|
|
|
+ __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */
|
|
|
+ __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */
|
|
|
+ __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */
|
|
|
+ __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */
|
|
|
+ __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */
|
|
|
+ __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */
|
|
|
+ __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */
|
|
|
+ __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */
|
|
|
+ __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */
|
|
|
+ __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */
|
|
|
+ __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */
|
|
|
+ __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */
|
|
|
+ __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */
|
|
|
+ __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */
|
|
|
+ } EORR_b;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+} R_PORT0_Type; /*!< Size = 16 (0x10) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_PFS ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief I/O Ports-PFS (R_PFS)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x40400800) R_PFS Structure */
|
|
|
+{
|
|
|
+ __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */
|
|
|
+} R_PFS_Type; /*!< Size = 960 (0x3c0) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_PMISC ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief I/O Ports-MISC (R_PMISC)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x40400D00) R_PMISC Structure */
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint8_t : 4;
|
|
|
+ __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */
|
|
|
+ uint8_t : 3;
|
|
|
+ } PFENET_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED;
|
|
|
+ __IM uint16_t RESERVED1[5];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t PWPR; /*!< (@ 0x0000000C) Write-Protect Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint8_t : 6;
|
|
|
+ __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */
|
|
|
+ __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */
|
|
|
+ } PWPR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED2;
|
|
|
+ __IM uint16_t RESERVED3[3];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t PWPRS; /*!< (@ 0x00000014) Write-Protect Register for Secure */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint8_t : 6;
|
|
|
+ __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */
|
|
|
+ __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */
|
|
|
+ } PWPRS_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED4;
|
|
|
+ __IM uint16_t RESERVED5[13];
|
|
|
+ __IOM R_PMISC_PMSAR_Type PMSAR[15]; /*!< (@ 0x00000030) Port Security Attribution Register */
|
|
|
+} R_PMISC_Type; /*!< Size = 108 (0x6c) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_RTC ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Realtime Clock (R_RTC)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x40202000) R_RTC Structure */
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */
|
|
|
+ __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */
|
|
|
+ __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */
|
|
|
+ __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */
|
|
|
+ __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */
|
|
|
+ __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */
|
|
|
+ __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */
|
|
|
+ uint8_t : 1;
|
|
|
+ } R64CNT_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary
|
|
|
+ * counter b7 to b0. */
|
|
|
+ } BCNT0_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When
|
|
|
+ * a carry is generated, 1 is added to the tens place. */
|
|
|
+ __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */
|
|
|
+ uint8_t : 1;
|
|
|
+ } RSECCNT_b;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED1;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary
|
|
|
+ * counter b15 to b8. */
|
|
|
+ } BCNT1_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When
|
|
|
+ * a carry is generated, 1 is added to the tens place. */
|
|
|
+ __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */
|
|
|
+ uint8_t : 1;
|
|
|
+ } RMINCNT_b;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED2;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary
|
|
|
+ * counter b23 to b16. */
|
|
|
+ } BCNT2_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a
|
|
|
+ * carry is generated, 1 is added to the tens place. */
|
|
|
+ __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from
|
|
|
+ * the ones place. */
|
|
|
+ __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */
|
|
|
+ uint8_t : 1;
|
|
|
+ } RHRCNT_b;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED3;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary
|
|
|
+ * counter b31 to b24. */
|
|
|
+ } BCNT3_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */
|
|
|
+ uint8_t : 5;
|
|
|
+ } RWKCNT_b;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED4;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry
|
|
|
+ * is generated, 1 is added to the tens place. */
|
|
|
+ __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the
|
|
|
+ * ones place. */
|
|
|
+ uint8_t : 2;
|
|
|
+ } RDAYCNT_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED5;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When
|
|
|
+ * a carry is generated, 1 is added to the tens place. */
|
|
|
+ __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from
|
|
|
+ * the ones place. */
|
|
|
+ uint8_t : 3;
|
|
|
+ } RMONCNT_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED6;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a
|
|
|
+ * carry is generated, 1 is added to the tens place. */
|
|
|
+ __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from
|
|
|
+ * ones place. When a carry is generated in the tens place,
|
|
|
+ * 1 is added to the hundreds place. */
|
|
|
+ uint16_t : 8;
|
|
|
+ } RYRCNT_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register
|
|
|
+ * corresponding to 32-bit binary counter b7 to b0. */
|
|
|
+ } BCNT0AR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */
|
|
|
+ __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */
|
|
|
+ __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */
|
|
|
+ } RSECAR_b;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED7;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register
|
|
|
+ * corresponding to 32-bit binary counter b15 to b8. */
|
|
|
+ } BCNT1AR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */
|
|
|
+ __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */
|
|
|
+ __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */
|
|
|
+ } RMINAR_b;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED8;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary
|
|
|
+ * counter b23 to b16. */
|
|
|
+ } BCNT2AR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */
|
|
|
+ __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */
|
|
|
+ __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */
|
|
|
+ __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */
|
|
|
+ } RHRAR_b;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED9;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary
|
|
|
+ * counter b31 to b24. */
|
|
|
+ } BCNT3AR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */
|
|
|
+ uint8_t : 4;
|
|
|
+ __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */
|
|
|
+ } RWKAR_b;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED10;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register
|
|
|
+ * for setting the alarm enable corresponding to 32-bit binary
|
|
|
+ * counter b7 to b0. */
|
|
|
+ } BCNT0AER_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */
|
|
|
+ __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */
|
|
|
+ } RDAYAR_b;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED11;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register
|
|
|
+ * for setting the alarm enable corresponding to 32-bit binary
|
|
|
+ * counter b15 to b8. */
|
|
|
+ } BCNT1AER_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */
|
|
|
+ __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */
|
|
|
+ uint8_t : 2;
|
|
|
+ __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */
|
|
|
+ } RMONAR_b;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED12;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register
|
|
|
+ * for setting the alarm enable corresponding to 32-bit binary
|
|
|
+ * counter b23 to b16. */
|
|
|
+ uint16_t : 8;
|
|
|
+ } BCNT2AER_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */
|
|
|
+ __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */
|
|
|
+ uint16_t : 8;
|
|
|
+ } RYRAR_b;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register
|
|
|
+ * for setting the alarm enable corresponding to 32-bit binary
|
|
|
+ * counter b31 to b24. */
|
|
|
+ } BCNT3AER_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint8_t : 7;
|
|
|
+ __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */
|
|
|
+ } RYRAREN_b;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED13;
|
|
|
+ __IM uint16_t RESERVED14;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */
|
|
|
+ __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */
|
|
|
+ __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */
|
|
|
+ __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */
|
|
|
+ __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */
|
|
|
+ } RCR1_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED15;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t START : 1; /*!< [0..0] Start */
|
|
|
+ __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */
|
|
|
+ __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */
|
|
|
+ __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */
|
|
|
+ __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected,
|
|
|
+ * the setting of this bit is disabled.) */
|
|
|
+ __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock
|
|
|
+ * is selected, the setting of this bit is disabled.) */
|
|
|
+ __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */
|
|
|
+ __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */
|
|
|
+ } RCR2_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED16;
|
|
|
+ __IM uint16_t RESERVED17;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */
|
|
|
+ uint8_t : 6;
|
|
|
+ __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */
|
|
|
+ } RCR4_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED18;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating
|
|
|
+ * clock from the LOCOclock, this bit sets the comparison
|
|
|
+ * value of the 128-Hz clock cycle. */
|
|
|
+ uint16_t : 15;
|
|
|
+ } RFRH_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating
|
|
|
+ * clock from the main clock, this bit sets the comparison
|
|
|
+ * value of the 128-Hz clock cycle. */
|
|
|
+ } RFRL_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value
|
|
|
+ * from the prescaler. */
|
|
|
+ __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */
|
|
|
+ } RADJ_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED19;
|
|
|
+ __IM uint16_t RESERVED20[8];
|
|
|
+ __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */
|
|
|
+ __IM uint16_t RESERVED21[5];
|
|
|
+ __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */
|
|
|
+} R_RTC_Type; /*!< Size = 128 (0x80) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_SCI0 ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Serial Communications Interface (R_SCI0)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x40358000) R_SCI0 Structure */
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */
|
|
|
+ __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */
|
|
|
+ __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */
|
|
|
+ __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */
|
|
|
+ __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */
|
|
|
+ __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */
|
|
|
+ __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */
|
|
|
+ } SMR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */
|
|
|
+ __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */
|
|
|
+ __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */
|
|
|
+ __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */
|
|
|
+ __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */
|
|
|
+ __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */
|
|
|
+ } SMR_SMCI_b;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */
|
|
|
+ } BRR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */
|
|
|
+ __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */
|
|
|
+ __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous
|
|
|
+ * mode when SMR.MP = 1) */
|
|
|
+ __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */
|
|
|
+ __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */
|
|
|
+ __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */
|
|
|
+ __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */
|
|
|
+ } SCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */
|
|
|
+ __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */
|
|
|
+ __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */
|
|
|
+ __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */
|
|
|
+ __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */
|
|
|
+ __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */
|
|
|
+ __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */
|
|
|
+ } SCR_SMCI_b;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */
|
|
|
+ } TDR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */
|
|
|
+ __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */
|
|
|
+ __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */
|
|
|
+ __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */
|
|
|
+ __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */
|
|
|
+ __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */
|
|
|
+ __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */
|
|
|
+ __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */
|
|
|
+ } SSR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including
|
|
|
+ * multi-processor) and FIFO selected) */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */
|
|
|
+ __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */
|
|
|
+ __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */
|
|
|
+ __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */
|
|
|
+ __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */
|
|
|
+ __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */
|
|
|
+ } SSR_FIFO_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart
|
|
|
+ * card interface mode. */
|
|
|
+ __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface
|
|
|
+ * mode. */
|
|
|
+ __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */
|
|
|
+ __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */
|
|
|
+ __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */
|
|
|
+ __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */
|
|
|
+ __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */
|
|
|
+ __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */
|
|
|
+ } SSR_SMCI_b;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */
|
|
|
+ } RDR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if
|
|
|
+ * operation is to be in simple I2C mode. */
|
|
|
+ __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The
|
|
|
+ * setting is invalid and a fixed data length of 8 bits is
|
|
|
+ * used in modes other than asynchronous mode.Set this bit
|
|
|
+ * to 1 if operation is to be in simple I2C mode. */
|
|
|
+ __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */
|
|
|
+ uint8_t : 2;
|
|
|
+ __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles
|
|
|
+ * in combination with the SMR.BCP[1:0] bits */
|
|
|
+ } SCMR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in
|
|
|
+ * asynchronous mode). */
|
|
|
+ __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous
|
|
|
+ * mode). */
|
|
|
+ __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */
|
|
|
+ __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid
|
|
|
+ * only in asynchronous mode and SCR.CKE[1]=0) */
|
|
|
+ __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous
|
|
|
+ * mode) */
|
|
|
+ __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should
|
|
|
+ * be 0 without simple I2C mode and asynchronous mode.)In
|
|
|
+ * asynchronous mode, for RXDn input only. In simple I2C mode,
|
|
|
+ * for RXDn/TxDn input. */
|
|
|
+ __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid
|
|
|
+ * the CKE[1] bit in SCR is 0 in asynchronous mode). */
|
|
|
+ __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only
|
|
|
+ * in asynchronous mode) */
|
|
|
+ } SEMR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */
|
|
|
+ uint8_t : 5;
|
|
|
+ } SNFR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */
|
|
|
+ uint8_t : 2;
|
|
|
+ __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock
|
|
|
+ * signal from the on-chip baud rate generator. */
|
|
|
+ } SIMR1_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */
|
|
|
+ __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */
|
|
|
+ uint8_t : 3;
|
|
|
+ __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */
|
|
|
+ uint8_t : 2;
|
|
|
+ } SIMR2_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */
|
|
|
+ __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */
|
|
|
+ __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */
|
|
|
+ __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed
|
|
|
+ * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */
|
|
|
+ __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */
|
|
|
+ __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */
|
|
|
+ } SIMR3_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */
|
|
|
+ uint8_t : 7;
|
|
|
+ } SISR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */
|
|
|
+ __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */
|
|
|
+ __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */
|
|
|
+ __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */
|
|
|
+ __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */
|
|
|
+ __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */
|
|
|
+ } SPMR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */
|
|
|
+ } TDRHL_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including
|
|
|
+ * multi-processor) or clock synchronous mode, and FIFO selected) */
|
|
|
+ __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous
|
|
|
+ * mode and SMR.MP=1 and FIFO selected) */
|
|
|
+ uint16_t : 6;
|
|
|
+ } FTDRHL_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous
|
|
|
+ * mode(including multi-processor) or clock synchronous mode,
|
|
|
+ * and FIFO selected) */
|
|
|
+ __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous
|
|
|
+ * mode and SMR.MP=1 and FIFO selected) */
|
|
|
+ uint8_t : 6;
|
|
|
+ } FTDRH_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous
|
|
|
+ * mode(including multi-processor) or clock synchronous mode,
|
|
|
+ * and FIFO selected) */
|
|
|
+ } FTDRL_b;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */
|
|
|
+ } RDRHL_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including
|
|
|
+ * multi-processor) or clock synchronous mode, and FIFO selected) */
|
|
|
+ __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode
|
|
|
+ * with SMR.MP=1 and FIFO selected) It can read multi-processor
|
|
|
+ * bit corresponded to serial receive data(RDATA[8:0]) */
|
|
|
+ __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */
|
|
|
+ __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */
|
|
|
+ __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */
|
|
|
+ __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */
|
|
|
+ __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */
|
|
|
+ uint16_t : 1;
|
|
|
+ } FRDRHL_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including
|
|
|
+ * multi-processor) or clock synchronous mode, and FIFO selected) */
|
|
|
+ __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode
|
|
|
+ * with SMR.MP=1 and FIFO selected) It can read multi-processor
|
|
|
+ * bit corresponded to serial receive data(RDATA[8:0]) */
|
|
|
+ __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */
|
|
|
+ __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */
|
|
|
+ __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */
|
|
|
+ __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */
|
|
|
+ __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */
|
|
|
+ uint8_t : 1;
|
|
|
+ } FRDRH_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including
|
|
|
+ * multi-processor) or clock synchronous mode, and FIFO selected)NOTE:
|
|
|
+ * When reading both of FRDRH register and FRDRL register,
|
|
|
+ * please read by an order of the FRDRH register and the FRDRL
|
|
|
+ * register. */
|
|
|
+ } FRDRL_b;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */
|
|
|
+ } MDDR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */
|
|
|
+ uint8_t : 2;
|
|
|
+ __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */
|
|
|
+ __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including
|
|
|
+ * multi-processor) */
|
|
|
+ __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous
|
|
|
+ * mode(including multi-processor) */
|
|
|
+ } DCCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including
|
|
|
+ * multi-processor) or clock synchronous mode) */
|
|
|
+ __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */
|
|
|
+ __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */
|
|
|
+ __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a
|
|
|
+ * reception data ready, the interrupt request is selected.) */
|
|
|
+ __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous
|
|
|
+ * mode(including multi-processor) or clock synchronous mode) */
|
|
|
+ __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous
|
|
|
+ * mode(including multi-processor) or clock synchronous mode) */
|
|
|
+ __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only
|
|
|
+ * in asynchronous mode(including multi-processor) or clock
|
|
|
+ * synchronous mode) */
|
|
|
+ } FCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive
|
|
|
+ * data stored in FRDRH and FRDRL(Valid only in asynchronous
|
|
|
+ * mode(including multi-processor) or clock synchronous mode,
|
|
|
+ * while FCR.FM=1) */
|
|
|
+ uint16_t : 3;
|
|
|
+ __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit
|
|
|
+ * data stored in FTDRH and FTDRL(Valid only in asynchronous
|
|
|
+ * mode(including multi-processor) or clock synchronous mode,
|
|
|
+ * while FCR.FM=1) */
|
|
|
+ uint16_t : 3;
|
|
|
+ } FDR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including
|
|
|
+ * multi-processor) or clock synchronous mode, and FIFO selected) */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with
|
|
|
+ * a framing error among the receive data stored in the receive
|
|
|
+ * FIFO data register (FRDRH and FRDRL). */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with
|
|
|
+ * a parity error among the receive data stored in the receive
|
|
|
+ * FIFO data register (FRDRH and FRDRL). */
|
|
|
+ uint16_t : 3;
|
|
|
+ } LSR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match
|
|
|
+ * wake-up function */
|
|
|
+ uint16_t : 7;
|
|
|
+ } CDR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal
|
|
|
+ * is shown.) */
|
|
|
+ __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of
|
|
|
+ * TxD terminal is selected when SCR.TE = 0.) */
|
|
|
+ __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value
|
|
|
+ * of SPB2DT is output to TxD terminal.) */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */
|
|
|
+ __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */
|
|
|
+ __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */
|
|
|
+ __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */
|
|
|
+ } SPTR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */
|
|
|
+ __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */
|
|
|
+ __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */
|
|
|
+ __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */
|
|
|
+ } ACTR_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */
|
|
|
+ uint8_t : 7;
|
|
|
+ } ESMER_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint8_t : 1;
|
|
|
+ __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */
|
|
|
+ __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */
|
|
|
+ __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */
|
|
|
+ uint8_t : 4;
|
|
|
+ } CR0_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */
|
|
|
+ __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */
|
|
|
+ __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */
|
|
|
+ __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */
|
|
|
+ __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */
|
|
|
+ } CR1_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */
|
|
|
+ __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */
|
|
|
+ } CR2_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */
|
|
|
+ uint8_t : 7;
|
|
|
+ } CR3_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */
|
|
|
+ __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */
|
|
|
+ uint8_t : 2;
|
|
|
+ __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */
|
|
|
+ uint8_t : 3;
|
|
|
+ } PCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */
|
|
|
+ __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */
|
|
|
+ __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */
|
|
|
+ __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */
|
|
|
+ __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */
|
|
|
+ __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */
|
|
|
+ uint8_t : 2;
|
|
|
+ } ICR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */
|
|
|
+ __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */
|
|
|
+ __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */
|
|
|
+ __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */
|
|
|
+ __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */
|
|
|
+ __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */
|
|
|
+ uint8_t : 2;
|
|
|
+ } STR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */
|
|
|
+ __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */
|
|
|
+ __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */
|
|
|
+ __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */
|
|
|
+ __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */
|
|
|
+ __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */
|
|
|
+ uint8_t : 2;
|
|
|
+ } STCR_b;
|
|
|
+ };
|
|
|
+ __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */
|
|
|
+ __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */
|
|
|
+ __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */
|
|
|
+ __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */
|
|
|
+ __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */
|
|
|
+ __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */
|
|
|
+ __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */
|
|
|
+ __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */
|
|
|
+ } CF0CR_b;
|
|
|
+ };
|
|
|
+ __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */
|
|
|
+ __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */
|
|
|
+ __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */
|
|
|
+ __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */
|
|
|
+ __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */
|
|
|
+ __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */
|
|
|
+ __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */
|
|
|
+ __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */
|
|
|
+ __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */
|
|
|
+ __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */
|
|
|
+ } CF1CR_b;
|
|
|
+ };
|
|
|
+ __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */
|
|
|
+ uint8_t : 7;
|
|
|
+ } TCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */
|
|
|
+ __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */
|
|
|
+ uint8_t : 1;
|
|
|
+ } TMR_b;
|
|
|
+ };
|
|
|
+ __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */
|
|
|
+ __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */
|
|
|
+} R_SCI0_Type; /*!< Size = 52 (0x34) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_SDHI0 ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief SD/MMC Host Interface (R_SDHI0)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x40252000) R_SDHI0 Structure */
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SD_CMD; /*!< (@ 0x00000000) Command Type Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CMDIDX : 6; /*!< [5..0] Command IndexThese bits specify Command Format[45:40]
|
|
|
+ * (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18:
|
|
|
+ * SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101 */
|
|
|
+ __IOM uint32_t ACMD : 2; /*!< [7..6] Command Type Select */
|
|
|
+ __IOM uint32_t RSPTP : 3; /*!< [10..8] Mode/Response TypeNOTE: As some commands cannot be used
|
|
|
+ * in normal mode, see section 1.4.10, Example of SD_CMD Register
|
|
|
+ * Setting to select mode/response type. */
|
|
|
+ __IOM uint32_t CMDTP : 1; /*!< [11..11] Data Mode (Command Type) */
|
|
|
+ __IOM uint32_t CMDRW : 1; /*!< [12..12] Write/Read Mode (enabled when the command with data
|
|
|
+ * is handled) */
|
|
|
+ __IOM uint32_t TRSTP : 1; /*!< [13..13] Single/Multiple Block Transfer (enabled when the command
|
|
|
+ * with data is handled) */
|
|
|
+ __IOM uint32_t CMD12AT : 2; /*!< [15..14] Multiple Block Transfer Mode (enabled at multiple block
|
|
|
+ * transfer) */
|
|
|
+ uint32_t : 16;
|
|
|
+ } SD_CMD_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SD_ARG; /*!< (@ 0x00000008) SD Command Argument Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t SD_ARG : 32; /*!< [31..0] Argument RegisterSet command format[39:8] (argument) */
|
|
|
+ } SD_ARG_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SD_ARG1; /*!< (@ 0x0000000C) SD Command Argument Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t SD_ARG1 : 16; /*!< [15..0] Argument Register 1Set command format[39:24] (argument) */
|
|
|
+ uint32_t : 16;
|
|
|
+ } SD_ARG1_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SD_STOP; /*!< (@ 0x00000010) Data Stop Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t STP : 1; /*!< [0..0] Stop- When STP is set to 1 during multiple block transfer,
|
|
|
+ * CMD12 is issued to halt the transfer through the SD host
|
|
|
+ * interface.However, if a command sequence is halted because
|
|
|
+ * of a communications error or timeout, CMD12 is not issued.
|
|
|
+ * Although continued buffer access is possible even after
|
|
|
+ * STP has been set to 1, the buffer access error bit (ERR5
|
|
|
+ * or ERR4) in SD_INFO2 will be set accordingly.- When STP
|
|
|
+ * has been set to 1 during transfer for single block write,
|
|
|
+ * the access end flag is set when SD_BUF becomes emp */
|
|
|
+ uint32_t : 7;
|
|
|
+ __IOM uint32_t SEC : 1; /*!< [8..8] Block Count EnableSet SEC to 1 at multiple block transfer.When
|
|
|
+ * SD_CMD is set as follows to start the command sequence
|
|
|
+ * while SEC is set to 1, CMD12 is automatically issued to
|
|
|
+ * stop multi-block transfer with the number of blocks which
|
|
|
+ * is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8]
|
|
|
+ * = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is
|
|
|
+ * automatically issued, multiple block transfer)When the
|
|
|
+ * command sequence is halted because of a communications
|
|
|
+ * error or timeout, CMD12 is not automatically i */
|
|
|
+ uint32_t : 23;
|
|
|
+ } SD_STOP_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SD_SECCNT; /*!< (@ 0x00000014) Block Count Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t SD_SECCNT : 32; /*!< [31..0] Number of Transfer BlocksNOTE: Do not change the value
|
|
|
+ * of this bit when the CBSY bit in SD_INFO2 is set to 1. */
|
|
|
+ } SD_SECCNT_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t SD_RSP10; /*!< (@ 0x00000018) SD Card Response Register 10 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t SD_RSP10 : 32; /*!< [31..0] Store the response from the SD card/MMC */
|
|
|
+ } SD_RSP10_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t SD_RSP1; /*!< (@ 0x0000001C) SD Card Response Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t SD_RSP1 : 16; /*!< [15..0] Store the response from the SD card/MMC */
|
|
|
+ uint32_t : 16;
|
|
|
+ } SD_RSP1_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t SD_RSP32; /*!< (@ 0x00000020) SD Card Response Register 32 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t SD_RSP32 : 32; /*!< [31..0] Store the response from the SD card/MMC */
|
|
|
+ } SD_RSP32_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t SD_RSP3; /*!< (@ 0x00000024) SD Card Response Register 3 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t SD_RSP3 : 16; /*!< [15..0] Store the response from the SD card/MMC */
|
|
|
+ uint32_t : 16;
|
|
|
+ } SD_RSP3_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t SD_RSP54; /*!< (@ 0x00000028) SD Card Response Register 54 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t SD_RSP54 : 32; /*!< [31..0] Store the response from the SD card/MMC */
|
|
|
+ } SD_RSP54_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t SD_RSP5; /*!< (@ 0x0000002C) SD Card Response Register 5 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t SD_RSP5 : 16; /*!< [15..0] Store the response from the SD card/MMC */
|
|
|
+ uint32_t : 16;
|
|
|
+ } SD_RSP5_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t SD_RSP76; /*!< (@ 0x00000030) SD Card Response Register 76 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t SD_RSP76 : 24; /*!< [23..0] Store the response from the SD card/MMC */
|
|
|
+ uint32_t : 8;
|
|
|
+ } SD_RSP76_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t SD_RSP7; /*!< (@ 0x00000034) SD Card Response Register 7 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t SD_RSP7 : 8; /*!< [7..0] Store the response from the SD card/MMC */
|
|
|
+ uint32_t : 24;
|
|
|
+ } SD_RSP7_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SD_INFO1; /*!< (@ 0x00000038) SD Card Interrupt Flag Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t RSPEND : 1; /*!< [0..0] Response End Detection */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t ACEND : 1; /*!< [2..2] Access End */
|
|
|
+ __IOM uint32_t SDCDRM : 1; /*!< [3..3] SDnCD Card Removal */
|
|
|
+ __IOM uint32_t SDCDIN : 1; /*!< [4..4] SDnCD Card Insertion */
|
|
|
+ __IM uint32_t SDCDMON : 1; /*!< [5..5] Indicates the SDnCD state */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IM uint32_t SDWPMON : 1; /*!< [7..7] Indicates the SDnWP state */
|
|
|
+ __IOM uint32_t SDD3RM : 1; /*!< [8..8] SDnDAT3 Card Removal */
|
|
|
+ __IOM uint32_t SDD3IN : 1; /*!< [9..9] SDnDAT3 Card Insertion */
|
|
|
+ __IM uint32_t SDD3MON : 1; /*!< [10..10] Inticates the SDnDAT3 State */
|
|
|
+ uint32_t : 21;
|
|
|
+ } SD_INFO1_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SD_INFO2; /*!< (@ 0x0000003C) SD Card Interrupt Flag Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CMDE : 1; /*!< [0..0] Command Error */
|
|
|
+ __IOM uint32_t CRCE : 1; /*!< [1..1] CRC Error */
|
|
|
+ __IOM uint32_t ENDE : 1; /*!< [2..2] END Error */
|
|
|
+ __IOM uint32_t DTO : 1; /*!< [3..3] Data Timeout */
|
|
|
+ __IOM uint32_t ILW : 1; /*!< [4..4] SD_BUF Illegal Write Access */
|
|
|
+ __IOM uint32_t ILR : 1; /*!< [5..5] SD_BUF Illegal Read Access */
|
|
|
+ __IOM uint32_t RSPTO : 1; /*!< [6..6] Response Timeout */
|
|
|
+ __IM uint32_t SDD0MON : 1; /*!< [7..7] SDDAT0Indicates the SDDAT0 state of the port specified
|
|
|
+ * by SD_PORTSEL. */
|
|
|
+ __IOM uint32_t BRE : 1; /*!< [8..8] SD_BUF Read Enable */
|
|
|
+ __IOM uint32_t BWE : 1; /*!< [9..9] SD_BUF Write Enable */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IM uint32_t SD_CLK_CTRLEN : 1; /*!< [13..13] When a command sequence is started by writing to SD_CMD,
|
|
|
+ * the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN
|
|
|
+ * bit is set to 0. The SCLKDIVEN bit is set to 1 after 8
|
|
|
+ * cycles of SDCLK have elapsed after setting of the CBSY
|
|
|
+ * bit to 0 due to completion of the command sequence. */
|
|
|
+ __IM uint32_t CBSY : 1; /*!< [14..14] Command Type Register Busy */
|
|
|
+ __IOM uint32_t ILA : 1; /*!< [15..15] Illegal Access Error */
|
|
|
+ uint32_t : 16;
|
|
|
+ } SD_INFO2_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SD_INFO1_MASK; /*!< (@ 0x00000040) SD_INFO1 Interrupt Mask Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t RSPENDM : 1; /*!< [0..0] Response End Interrupt Request Mask */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t ACENDM : 1; /*!< [2..2] Access End Interrupt Request Mask */
|
|
|
+ __IOM uint32_t SDCDRMM : 1; /*!< [3..3] SDnCD card Removal Interrupt Request Mask */
|
|
|
+ __IOM uint32_t SDCDINM : 1; /*!< [4..4] SDnCD card Insertion Interrupt Request Mask */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t SDD3RMM : 1; /*!< [8..8] SDnDAT3 Card Removal Interrupt Request Mask */
|
|
|
+ __IOM uint32_t SDD3INM : 1; /*!< [9..9] SDnDAT3 Card Insertion Interrupt Request Mask */
|
|
|
+ uint32_t : 22;
|
|
|
+ } SD_INFO1_MASK_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SD_INFO2_MASK; /*!< (@ 0x00000044) SD_INFO2 Interrupt Mask Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CMDEM : 1; /*!< [0..0] Command Error Interrupt Request Mask */
|
|
|
+ __IOM uint32_t CRCEM : 1; /*!< [1..1] CRC Error Interrupt Request Mask */
|
|
|
+ __IOM uint32_t ENDEM : 1; /*!< [2..2] End Bit Error Interrupt Request Mask */
|
|
|
+ __IOM uint32_t DTOM : 1; /*!< [3..3] Data Timeout Interrupt Request Mask */
|
|
|
+ __IOM uint32_t ILWM : 1; /*!< [4..4] SD_BUF Register Illegal Write Interrupt Request Mask */
|
|
|
+ __IOM uint32_t ILRM : 1; /*!< [5..5] SD_BUF Register Illegal Read Interrupt Request Mask */
|
|
|
+ __IOM uint32_t RSPTOM : 1; /*!< [6..6] Response Timeout Interrupt Request Mask */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t BREM : 1; /*!< [8..8] BRE Interrupt Request Mask */
|
|
|
+ __IOM uint32_t BWEM : 1; /*!< [9..9] BWE Interrupt Request Mask */
|
|
|
+ uint32_t : 5;
|
|
|
+ __IOM uint32_t ILAM : 1; /*!< [15..15] Illegal Access Error Interrupt Request Mask */
|
|
|
+ uint32_t : 16;
|
|
|
+ } SD_INFO2_MASK_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CLKSEL : 8; /*!< [7..0] SDHI Clock Frequency Select */
|
|
|
+ __IOM uint32_t CLKEN : 1; /*!< [8..8] SD/MMC Clock Output Control Enable */
|
|
|
+ __IOM uint32_t CLKCTRLEN : 1; /*!< [9..9] SD/MMC Clock Output Automatic Control Enable */
|
|
|
+ uint32_t : 22;
|
|
|
+ } SD_CLK_CTRL_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SD_SIZE; /*!< (@ 0x0000004C) Transfer Data Length Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t LEN : 10; /*!< [9..0] Transfer Data SizeThese bits specify a size between 1
|
|
|
+ * and 512 bytes for the transfer of single blocks.In cases
|
|
|
+ * of multiple block transfer with automatic issuing of CMD12
|
|
|
+ * (CMD18 and CMD25), the only specifiable transfer data size
|
|
|
+ * is 512 bytes. Furthermore, in cases of multiple block transfer
|
|
|
+ * without automatic issuing of CMD12, as well as 512 bytes,
|
|
|
+ * 32, 64, 128, and 256 bytes are specifiable. However, in
|
|
|
+ * the reading of 32, 64, 128, and 256 bytes for the transfer
|
|
|
+ * of multiple blocks, this is restricted to mult */
|
|
|
+ uint32_t : 22;
|
|
|
+ } SD_SIZE_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SD_OPTION; /*!< (@ 0x00000050) SD Card Access Control Option Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CTOP : 4; /*!< [3..0] Card Detect Time Counter */
|
|
|
+ __IOM uint32_t TOP : 4; /*!< [7..4] Timeout Counter */
|
|
|
+ __IOM uint32_t TOUTMASK : 1; /*!< [8..8] Timeout MASKWhen timeout occurs in case of inactivating
|
|
|
+ * timeout, software reset should be executed to terminate
|
|
|
+ * command sequence. */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t WIDTH8 : 1; /*!< [13..13] Bus Widthsee b15, WIDTH bit */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t WIDTH : 1; /*!< [15..15] Bus WidthNOTE: The initial value is applied at a reset
|
|
|
+ * and when the SOFT_RST.SDRST flag is 0. */
|
|
|
+ uint32_t : 16;
|
|
|
+ } SD_OPTION_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED1;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t SD_ERR_STS1; /*!< (@ 0x00000058) SD Error Status Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t CMDE0 : 1; /*!< [0..0] Command Error 0NOTE: other than a response to a command
|
|
|
+ * issued within a command sequence */
|
|
|
+ __IM uint32_t CMDE1 : 1; /*!< [1..1] Command Error 1NOTE: In cases where CMD12 is issued by
|
|
|
+ * setting a command index in SD_CMD, this is Indicated in
|
|
|
+ * CMDE0. */
|
|
|
+ __IM uint32_t RSPLENE0 : 1; /*!< [2..2] Response Length Error 0NOTE: other than a response to
|
|
|
+ * a command issued within a command sequence */
|
|
|
+ __IM uint32_t RSPLENE1 : 1; /*!< [3..3] Response Length Error 1NOTE: In cases where CMD12 is
|
|
|
+ * issued by setting a command index in SD_CMD, this is indicated
|
|
|
+ * in RSPLENE0. */
|
|
|
+ __IM uint32_t RDLENE : 1; /*!< [4..4] Read Data Length Error */
|
|
|
+ __IM uint32_t CRCLENE : 1; /*!< [5..5] CRC Status Token Length Error */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IM uint32_t RSPCRCE0 : 1; /*!< [8..8] Response CRC Error 0NOTE: other than a response to a
|
|
|
+ * command issued within a command sequence */
|
|
|
+ __IM uint32_t RSPCRCE1 : 1; /*!< [9..9] Response CRC Error 1NOTE: In cases where CMD12 is issued
|
|
|
+ * by setting a command index in SD_CMD, this is indicated
|
|
|
+ * in RSPCRCE0. */
|
|
|
+ __IM uint32_t RDCRCE : 1; /*!< [10..10] Read Data CRC Error */
|
|
|
+ __IM uint32_t CRCTKE : 1; /*!< [11..11] CRC Status Token Error */
|
|
|
+ __IM uint32_t CRCTK : 3; /*!< [14..12] CRC Status TokenStore the CRC status token value (normal
|
|
|
+ * value is 010b) */
|
|
|
+ uint32_t : 17;
|
|
|
+ } SD_ERR_STS1_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t SD_ERR_STS2; /*!< (@ 0x0000005C) SD Error Status Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t RSPTO0 : 1; /*!< [0..0] Response Timeout 0 */
|
|
|
+ __IM uint32_t RSPTO1 : 1; /*!< [1..1] Response Timeout 1 */
|
|
|
+ __IM uint32_t BSYTO0 : 1; /*!< [2..2] Busy Timeout 0 */
|
|
|
+ __IM uint32_t BSYTO1 : 1; /*!< [3..3] Busy Timeout 1 */
|
|
|
+ __IM uint32_t RDTO : 1; /*!< [4..4] Read Data Timeout */
|
|
|
+ __IM uint32_t CRCTO : 1; /*!< [5..5] CRC Status Token Timeout */
|
|
|
+ __IM uint32_t CRCBSYTO : 1; /*!< [6..6] CRC Status Token Busy Timeout */
|
|
|
+ uint32_t : 25;
|
|
|
+ } SD_ERR_STS2_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SD_BUF0; /*!< (@ 0x00000060) SD Buffer Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t SD_BUF : 32; /*!< [31..0] SD Buffer RegisterWhen writing to the SD card, the write
|
|
|
+ * data is written to this register. When reading from the
|
|
|
+ * SD card, the read data is read from this register. This
|
|
|
+ * register is internally connected to two 512-byte buffers.If
|
|
|
+ * both buffers are not empty when executing multiple block
|
|
|
+ * read, SD/MMC clock is stopped to suspend receiving data.
|
|
|
+ * When one of buffers is empty, SD/MMC clock is supplied
|
|
|
+ * to resume receiving data. */
|
|
|
+ } SD_BUF0_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED2;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SDIO_MODE; /*!< (@ 0x00000068) SDIO Mode Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t INTEN : 1; /*!< [0..0] SDIO Mode */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t RWREQ : 1; /*!< [2..2] Read Wait Request */
|
|
|
+ uint32_t : 5;
|
|
|
+ __IOM uint32_t IOABT : 1; /*!< [8..8] SDIO AbortNOTE: See manual */
|
|
|
+ __IOM uint32_t C52PUB : 1; /*!< [9..9] SDIO None AbortNOTE: See manual */
|
|
|
+ uint32_t : 22;
|
|
|
+ } SDIO_MODE_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SDIO_INFO1; /*!< (@ 0x0000006C) SDIO Interrupt Flag Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t IOIRQ : 1; /*!< [0..0] SDIO Interrupt Status */
|
|
|
+ uint32_t : 13;
|
|
|
+ __IOM uint32_t EXPUB52 : 1; /*!< [14..14] EXPUB52 Status FlagNOTE: See manual */
|
|
|
+ __IOM uint32_t EXWT : 1; /*!< [15..15] EXWT Status FlagNOTE: See manual */
|
|
|
+ uint32_t : 16;
|
|
|
+ } SDIO_INFO1_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SDIO_INFO1_MASK; /*!< (@ 0x00000070) SDIO_INFO1 Interrupt Mask Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t IOIRQM : 1; /*!< [0..0] IOIRQ Interrupt Mask Control */
|
|
|
+ uint32_t : 13;
|
|
|
+ __IOM uint32_t EXPUB52M : 1; /*!< [14..14] EXPUB52 Interrupt Request Mask Control */
|
|
|
+ __IOM uint32_t EXWTM : 1; /*!< [15..15] EXWT Interrupt Request Mask Control */
|
|
|
+ uint32_t : 16;
|
|
|
+ } SDIO_INFO1_MASK_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED3[79];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SD_DMAEN; /*!< (@ 0x000001B0) DMA Mode Enable Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t DMAEN : 1; /*!< [1..1] SD_BUF Read/Write DMA Transfer */
|
|
|
+ uint32_t : 30;
|
|
|
+ } SD_DMAEN_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED4[3];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SOFT_RST; /*!< (@ 0x000001C0) Software Reset Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t SDRST : 1; /*!< [0..0] Software Reset of SD I/F Unit */
|
|
|
+ uint32_t : 31;
|
|
|
+ } SOFT_RST_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED5[2];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SDIF_MODE; /*!< (@ 0x000001CC) SD Interface Mode Setting Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 8;
|
|
|
+ __IOM uint32_t NOCHKCR : 1; /*!< [8..8] CRC Check Mask (for MMC test commands) */
|
|
|
+ uint32_t : 23;
|
|
|
+ } SDIF_MODE_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED6[4];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t EXT_SWAP; /*!< (@ 0x000001E0) Swap Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 6;
|
|
|
+ __IOM uint32_t BWSWP : 1; /*!< [6..6] SD_BUF0 Swap Write */
|
|
|
+ __IOM uint32_t BRSWP : 1; /*!< [7..7] SD_BUF0 Swap Read */
|
|
|
+ uint32_t : 24;
|
|
|
+ } EXT_SWAP_b;
|
|
|
+ };
|
|
|
+} R_SDHI0_Type; /*!< Size = 484 (0x1e4) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_SPI0 ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Serial Peripheral Interface (R_SPI0)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x4035C000) R_SPI0 Structure */
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */
|
|
|
+ __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */
|
|
|
+ __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */
|
|
|
+ __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */
|
|
|
+ __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */
|
|
|
+ __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */
|
|
|
+ __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */
|
|
|
+ __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */
|
|
|
+ } SPCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */
|
|
|
+ __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */
|
|
|
+ __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */
|
|
|
+ __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */
|
|
|
+ __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */
|
|
|
+ __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */
|
|
|
+ __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */
|
|
|
+ __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */
|
|
|
+ } SSLP_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */
|
|
|
+ __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */
|
|
|
+ uint8_t : 2;
|
|
|
+ __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */
|
|
|
+ __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */
|
|
|
+ uint8_t : 2;
|
|
|
+ } SPPCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */
|
|
|
+ __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */
|
|
|
+ __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */
|
|
|
+ __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */
|
|
|
+ __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */
|
|
|
+ __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */
|
|
|
+ __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */
|
|
|
+ __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */
|
|
|
+ } SPSR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */
|
|
|
+ __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */
|
|
|
+ __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which
|
|
|
+ * the SPCMD0 to SPCMD07 registers are to be referenced is
|
|
|
+ * changed in accordance with the sequence length that is
|
|
|
+ * set in these bits. The relationship among the setting of
|
|
|
+ * these bits, sequence length, and SPCMD0 to SPCMD7 registers
|
|
|
+ * referenced by the RSPI is shown above. However, the RSPI
|
|
|
+ * in slave mode always references SPCMD0. */
|
|
|
+ uint8_t : 5;
|
|
|
+ } SPSCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */
|
|
|
+ uint8_t : 1;
|
|
|
+ } SPSSR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */
|
|
|
+ } SPBR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */
|
|
|
+ __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */
|
|
|
+ __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */
|
|
|
+ __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */
|
|
|
+ __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */
|
|
|
+ uint8_t : 1;
|
|
|
+ } SPDCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */
|
|
|
+ uint8_t : 5;
|
|
|
+ } SPCKD_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */
|
|
|
+ uint8_t : 5;
|
|
|
+ } SSLND_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */
|
|
|
+ uint8_t : 5;
|
|
|
+ } SPND_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */
|
|
|
+ __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */
|
|
|
+ __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */
|
|
|
+ __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */
|
|
|
+ __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */
|
|
|
+ __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */
|
|
|
+ } SPCR2_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */
|
|
|
+ __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */
|
|
|
+ __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */
|
|
|
+ __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */
|
|
|
+ __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */
|
|
|
+ __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */
|
|
|
+ __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */
|
|
|
+ __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */
|
|
|
+ __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */
|
|
|
+ __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */
|
|
|
+ } SPCMD_b[8];
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */
|
|
|
+ __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */
|
|
|
+ uint8_t : 6;
|
|
|
+ } SPDCR2_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */
|
|
|
+ __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */
|
|
|
+ uint8_t : 2;
|
|
|
+ __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */
|
|
|
+ uint8_t : 3;
|
|
|
+ } SPCR3_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED;
|
|
|
+ __IM uint32_t RESERVED1[6];
|
|
|
+ __IM uint16_t RESERVED2;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint16_t : 4;
|
|
|
+ __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */
|
|
|
+ uint16_t : 3;
|
|
|
+ __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */
|
|
|
+ } SPPR_b;
|
|
|
+ };
|
|
|
+} R_SPI0_Type; /*!< Size = 64 (0x40) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_SRAM ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief SRAM (R_SRAM)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x40002000) R_SRAM Structure */
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t SRAMPRCR; /*!< (@ 0x00000000) SRAM Protection Control Register for Secure */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t PR : 1; /*!< [0..0] Register Write Control */
|
|
|
+ uint16_t : 7;
|
|
|
+ __OM uint16_t KW : 8; /*!< [15..8] Write Key Code */
|
|
|
+ } SRAMPRCR_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t SRAMPRCR_NS; /*!< (@ 0x00000004) SRAM Protection Control Register for Non-Secure */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t PR : 1; /*!< [0..0] Register Write Control */
|
|
|
+ uint16_t : 7;
|
|
|
+ __OM uint16_t KW : 8; /*!< [15..8] Write Key Code */
|
|
|
+ } SRAMPRCR_NS_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED1;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) SRAM Wait State Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t WTEN : 1; /*!< [0..0] Wait enable */
|
|
|
+ uint8_t : 7;
|
|
|
+ } SRAMWTSC_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED2;
|
|
|
+ __IM uint16_t RESERVED3;
|
|
|
+ __IM uint32_t RESERVED4;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SRAMCR0; /*!< (@ 0x00000010) SRAM Control Register 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t OAD : 1; /*!< [0..0] Operation after detection for 1-bit ECC error detection */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t ECCMOD : 2; /*!< [3..2] ECC Operating Mode Select */
|
|
|
+ __IOM uint8_t E1STSEN : 1; /*!< [4..4] ECC 1-Bit Error Information Update Enable */
|
|
|
+ uint8_t : 2;
|
|
|
+ __IOM uint8_t TSTBYP : 1; /*!< [7..7] ECC Test Enable / ECC Bypass Select */
|
|
|
+ } SRAMCR0_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED5;
|
|
|
+ __IM uint16_t RESERVED6;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SRAMCR1; /*!< (@ 0x00000014) SRAM Control Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t OAD : 1; /*!< [0..0] Operation after detection for parity error detection */
|
|
|
+ uint8_t : 7;
|
|
|
+ } SRAMCR1_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED7;
|
|
|
+ __IM uint16_t RESERVED8;
|
|
|
+ __IM uint32_t RESERVED9[6];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SRAMECCRGN0; /*!< (@ 0x00000030) SRAM0 ECC Region Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t ECCRGN : 2; /*!< [1..0] ECC Region */
|
|
|
+ uint8_t : 6;
|
|
|
+ } SRAMECCRGN0_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED10;
|
|
|
+ __IM uint16_t RESERVED11;
|
|
|
+ __IM uint32_t RESERVED12[3];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint16_t SRAMESR; /*!< (@ 0x00000040) SRAM Error Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t ERR00 : 1; /*!< [0..0] SRAM0 1-bit ECC Error Status */
|
|
|
+ __IM uint16_t ERR01 : 1; /*!< [1..1] SRAM0 2-bit ECC Error Status */
|
|
|
+ __IM uint16_t ERR1 : 1; /*!< [2..2] SRAM1 Parity Error Status */
|
|
|
+ uint16_t : 11;
|
|
|
+ __IM uint16_t ERRS : 1; /*!< [14..14] Standby SRAM Parity Error status */
|
|
|
+ uint16_t : 1;
|
|
|
+ } SRAMESR_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED13;
|
|
|
+ __IM uint32_t RESERVED14;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t SRAMESCLR; /*!< (@ 0x00000048) SRAM Error Status Clear Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t CLR00 : 1; /*!< [0..0] SRAM0 1-bit ECC Error Status Clear */
|
|
|
+ __IOM uint16_t CLR01 : 1; /*!< [1..1] SRAM0 2-bit ECC Error Status Clear */
|
|
|
+ __IOM uint16_t CLR1 : 1; /*!< [2..2] SRAM1 Parity Error Status Clear */
|
|
|
+ uint16_t : 11;
|
|
|
+ __IOM uint16_t CLRS : 1; /*!< [14..14] Standby SRAM Parity Error Status Clear */
|
|
|
+ uint16_t : 1;
|
|
|
+ } SRAMESCLR_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED15;
|
|
|
+ __IM uint32_t RESERVED16;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t SRAMEAR0; /*!< (@ 0x00000050) SRAM Error Address Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 3;
|
|
|
+ __IM uint32_t EA : 17; /*!< [19..3] SRAM Error Address */
|
|
|
+ uint32_t : 12;
|
|
|
+ } SRAMEAR0_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t SRAMEAR1; /*!< (@ 0x00000054) SRAM Error Address Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 3;
|
|
|
+ __IM uint32_t EA : 17; /*!< [19..3] SRAM Error Address */
|
|
|
+ uint32_t : 12;
|
|
|
+ } SRAMEAR1_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t SRAMEAR2; /*!< (@ 0x00000058) SRAM Error Address Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 3;
|
|
|
+ __IM uint32_t EA : 17; /*!< [19..3] SRAM Error Address */
|
|
|
+ uint32_t : 12;
|
|
|
+ } SRAMEAR2_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED17[45];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t STBRAMCR; /*!< (@ 0x00000110) Standby SRAM Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t OAD : 1; /*!< [0..0] Operation after detection */
|
|
|
+ uint8_t : 7;
|
|
|
+ } STBRAMCR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED18;
|
|
|
+ __IM uint16_t RESERVED19;
|
|
|
+ __IM uint32_t RESERVED20[15];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t STBRAMEAR; /*!< (@ 0x00000150) Standby SRAM Error Address Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 2;
|
|
|
+ __IM uint32_t EA : 8; /*!< [9..2] SRAM Error Address */
|
|
|
+ uint32_t : 22;
|
|
|
+ } STBRAMEAR_b;
|
|
|
+ };
|
|
|
+} R_SRAM_Type; /*!< Size = 340 (0x154) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_SSI0 ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Serial Sound Interface Enhanced (SSIE) (R_SSI0)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x4025D000) R_SSI0 Structure */
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SSICR; /*!< (@ 0x00000000) Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t REN : 1; /*!< [0..0] Receive Enable */
|
|
|
+ __IOM uint32_t TEN : 1; /*!< [1..1] Transmit Enable */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t MUEN : 1; /*!< [3..3] Mute EnableNOTE: When this module is muted, the value
|
|
|
+ * of outputting serial data is rewritten to 0 but data transmission
|
|
|
+ * is not stopped. Write dummy data to the SSIFTDR not to
|
|
|
+ * generate a transmit underflow because the number of data
|
|
|
+ * in the transmit FIFO is decreasing. */
|
|
|
+ __IOM uint32_t CKDV : 4; /*!< [7..4] Serial Oversampling Clock Division Ratio */
|
|
|
+ __IOM uint32_t DEL : 1; /*!< [8..8] Serial Data Delay */
|
|
|
+ __IOM uint32_t PDTA : 1; /*!< [9..9] Parallel Data Alignment */
|
|
|
+ __IOM uint32_t SDTA : 1; /*!< [10..10] Serial Data Alignment */
|
|
|
+ __IOM uint32_t SPDP : 1; /*!< [11..11] Serial Padding Polarity */
|
|
|
+ __IOM uint32_t LRCKP : 1; /*!< [12..12] Serial WS Polarity */
|
|
|
+ __IOM uint32_t BCKP : 1; /*!< [13..13] Serial Bit Clock Polarity */
|
|
|
+ __IOM uint32_t MST : 1; /*!< [14..14] Serial WS Direction NOTE: Only the following settings
|
|
|
+ * are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings
|
|
|
+ * are prohibited. */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t SWL : 3; /*!< [18..16] System Word LengthSet the system word length to the
|
|
|
+ * bit clock frequency/2 fs. */
|
|
|
+ __IOM uint32_t DWL : 3; /*!< [21..19] Data Word Length */
|
|
|
+ __IOM uint32_t FRM : 2; /*!< [23..22] Channels */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t IIEN : 1; /*!< [25..25] Idle Mode Interrupt Enable */
|
|
|
+ __IOM uint32_t ROIEN : 1; /*!< [26..26] Receive Overflow Interrupt Enable */
|
|
|
+ __IOM uint32_t RUIEN : 1; /*!< [27..27] Receive Underflow Interrupt Enable */
|
|
|
+ __IOM uint32_t TOIEN : 1; /*!< [28..28] Transmit Overflow Interrupt Enable */
|
|
|
+ __IOM uint32_t TUIEN : 1; /*!< [29..29] Transmit Underflow Interrupt Enable */
|
|
|
+ __IOM uint32_t CKS : 1; /*!< [30..30] Oversampling Clock Select */
|
|
|
+ uint32_t : 1;
|
|
|
+ } SSICR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SSISR; /*!< (@ 0x00000004) Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t IDST : 1; /*!< [0..0] Idle Mode Status Flag */
|
|
|
+ __IM uint32_t RSWNO : 1; /*!< [1..1] Receive Serial Word Number */
|
|
|
+ __IM uint32_t RCHNO : 2; /*!< [3..2] Receive Channel Number.These bits are read as 00b. */
|
|
|
+ __IM uint32_t TSWNO : 1; /*!< [4..4] Transmit Serial Word Number */
|
|
|
+ __IM uint32_t TCHNO : 2; /*!< [6..5] Transmit Channel Number */
|
|
|
+ uint32_t : 18;
|
|
|
+ __IM uint32_t IIRQ : 1; /*!< [25..25] Idle Mode Interrupt Status Flag */
|
|
|
+ __IOM uint32_t ROIRQ : 1; /*!< [26..26] Receive Overflow Error Interrupt Status Flag NOTE:
|
|
|
+ * Writable only to clear the flag. Confirm the value is 1
|
|
|
+ * and then write 0. */
|
|
|
+ __IOM uint32_t RUIRQ : 1; /*!< [27..27] Receive Underflow Error Interrupt Status Flag NOTE:
|
|
|
+ * Writable only to clear the flag. Confirm the value is 1
|
|
|
+ * and then write 0. */
|
|
|
+ __IOM uint32_t TOIRQ : 1; /*!< [28..28] Transmit Overflow Error Interrupt Status Flag NOTE:
|
|
|
+ * Writable only to clear the flag. Confirm the value is 1
|
|
|
+ * and then write 0. */
|
|
|
+ __IOM uint32_t TUIRQ : 1; /*!< [29..29] Transmit Underflow Error Interrupt Status Flag NOTE:
|
|
|
+ * Writable only to clear the flag. Confirm the value is 1
|
|
|
+ * and then write 0. */
|
|
|
+ uint32_t : 2;
|
|
|
+ } SSISR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED[2];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SSIFCR; /*!< (@ 0x00000010) FIFO Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t RFRST : 1; /*!< [0..0] Receive FIFO Data Register Reset */
|
|
|
+ __IOM uint32_t TFRST : 1; /*!< [1..1] Transmit FIFO Data Register Reset */
|
|
|
+ __IOM uint32_t RIE : 1; /*!< [2..2] Receive Interrupt Enable NOTE: RXI can be cleared by
|
|
|
+ * clearing either the RDF flag (see the description of the
|
|
|
+ * RDF bit for details) or RIE bit. */
|
|
|
+ __IOM uint32_t TIE : 1; /*!< [3..3] Transmit Interrupt Enable NOTE: TXI can be cleared by
|
|
|
+ * clearing either the TDE flag (see the description of the
|
|
|
+ * TDE bit for details) or TIE bit. */
|
|
|
+ __IOM uint32_t RTRG : 2; /*!< [5..4] Receive Data Trigger Number */
|
|
|
+ __IOM uint32_t TTRG : 2; /*!< [7..6] Transmit Data Trigger Number NOTE: The values in parenthesis
|
|
|
+ * are the number of empty stages in SSIFTDR at which the
|
|
|
+ * TDE flag is set. */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t BSW : 1; /*!< [11..11] Byte Swap Enable */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t SSIRST : 1; /*!< [16..16] SSI soft ware reset */
|
|
|
+ uint32_t : 14;
|
|
|
+ __IOM uint32_t AUCKE : 1; /*!< [31..31] Oversampling Clock Enable */
|
|
|
+ } SSIFCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SSIFSR; /*!< (@ 0x00000014) FIFO Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t RDF : 1; /*!< [0..0] Receive Data Full Flag NOTE: Since the SSIFRDR register
|
|
|
+ * is a 32-byte FIFO register, the maximum number of data
|
|
|
+ * bytes that can be read from it while the RDF flag is 1
|
|
|
+ * is indicated in the RDC[3:0] flags. If reading data from
|
|
|
+ * the SSIFRDR register is continued after all the data is
|
|
|
+ * read, undefined values will be read. */
|
|
|
+ uint32_t : 7;
|
|
|
+ __IM uint32_t RDC : 6; /*!< [13..8] Receive Data Indicate Flag(Indicates the number of data
|
|
|
+ * units stored in SSIFRDR) */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t TDE : 1; /*!< [16..16] Transmit Data Empty Flag NOTE: Since the SSIFTDR register
|
|
|
+ * is a 32-byte FIFO register, the maximum number of bytes
|
|
|
+ * that can be written to it while the TDE flag is 1 is 8
|
|
|
+ * - TDC[3:0]. If writing data to the SSIFTDR register is
|
|
|
+ * continued after all the data is written, writing will be
|
|
|
+ * invalid and an overflow occurs. */
|
|
|
+ uint32_t : 7;
|
|
|
+ __IM uint32_t TDC : 6; /*!< [29..24] Transmit Data Indicate Flag(Indicates the number of
|
|
|
+ * data units stored in SSIFTDR) */
|
|
|
+ uint32_t : 2;
|
|
|
+ } SSIFSR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __OM uint32_t SSIFTDR; /*!< (@ 0x00000018) Transmit FIFO Data Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __OM uint32_t SSIFTDR : 32; /*!< [31..0] SSIFTDR is a write-only FIFO register consisting of
|
|
|
+ * eight stages of 32-bit registers for storing data to be
|
|
|
+ * serially transmitted. NOTE: that when the SSIFTDR register
|
|
|
+ * is full of data (32 bytes), the next data cannot be written
|
|
|
+ * to it. If writing is attempted, it will be ignored and
|
|
|
+ * an overflow occurs. */
|
|
|
+ } SSIFTDR_b;
|
|
|
+ };
|
|
|
+ __OM uint16_t SSIFTDR16; /*!< (@ 0x00000018) Transmit FIFO Data Register */
|
|
|
+ __OM uint8_t SSIFTDR8; /*!< (@ 0x00000018) Transmit FIFO Data Register */
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t SSIFRDR; /*!< (@ 0x0000001C) Receive FIFO Data Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t SSIFRDR : 32; /*!< [31..0] SSIFRDR is a read-only FIFO register consisting of eight
|
|
|
+ * stages of 32-bit registers for storing serially received
|
|
|
+ * data. */
|
|
|
+ } SSIFRDR_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t SSIFRDR16; /*!< (@ 0x0000001C) Receive FIFO Data Register */
|
|
|
+ __IM uint8_t SSIFRDR8; /*!< (@ 0x0000001C) Receive FIFO Data Register */
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SSIOFR; /*!< (@ 0x00000020) Audio Format Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t OMOD : 2; /*!< [1..0] Audio Format Select */
|
|
|
+ uint32_t : 6;
|
|
|
+ __IOM uint32_t LRCONT : 1; /*!< [8..8] Whether to Enable LRCK/FS Continuation */
|
|
|
+ __IOM uint32_t BCKASTP : 1; /*!< [9..9] Whether to Enable Stopping BCK Output When SSIE is in
|
|
|
+ * Idle Status */
|
|
|
+ uint32_t : 22;
|
|
|
+ } SSIOFR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SSISCR; /*!< (@ 0x00000024) Status Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t RDFS : 5; /*!< [4..0] RDF Setting Condition Select */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t TDES : 5; /*!< [12..8] TDE Setting Condition Select */
|
|
|
+ uint32_t : 19;
|
|
|
+ } SSISCR_b;
|
|
|
+ };
|
|
|
+} R_SSI0_Type; /*!< Size = 40 (0x28) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_SYSTEM ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief System Pins (R_SYSTEM)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure */
|
|
|
+{
|
|
|
+ __IM uint32_t RESERVED[3];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SBYCR; /*!< (@ 0x0000000C) Standby Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint8_t : 6;
|
|
|
+ __IOM uint8_t OPE : 1; /*!< [6..6] Output Port Enable */
|
|
|
+ uint8_t : 1;
|
|
|
+ } SBYCR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED1;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SSCR2; /*!< (@ 0x0000000E) Software Standby Control Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint8_t SS1RSF : 1; /*!< [0..0] Software Standby 1 regulator status flag */
|
|
|
+ uint8_t : 7;
|
|
|
+ } SSCR2_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED2;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t FLSCR; /*!< (@ 0x00000010) Flash Standby Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t FLSWCF : 1; /*!< [0..0] Flash Stabilization wait completion flag */
|
|
|
+ uint8_t : 7;
|
|
|
+ } FLSCR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED3;
|
|
|
+ __IM uint16_t RESERVED4;
|
|
|
+ __IM uint32_t RESERVED5[2];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t MSTPCRA; /*!< (@ 0x0000001C) Module Stop Control Register A */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t MSTPA0 : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPA1 : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPA2 : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPA3 : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPA4 : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPA5 : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPA6 : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPA8 : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPA9 : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage. */
|
|
|
+ __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
|
|
|
+ * usage. */
|
|
|
+ } MSTPCRA_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SCKDIVCR; /*!< (@ 0x00000020) System Clock Division Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t PCKD : 4; /*!< [3..0] Peripheral Module Clock D (PCLKD) Select */
|
|
|
+ __IOM uint32_t PCKC : 4; /*!< [7..4] Peripheral Module Clock C (PCLKC) Select */
|
|
|
+ __IOM uint32_t PCKB : 4; /*!< [11..8] Peripheral Module Clock B (PCLKB) Select */
|
|
|
+ __IOM uint32_t PCKA : 4; /*!< [15..12] Peripheral Module Clock A (PCLKA) Select */
|
|
|
+ __IOM uint32_t BCK : 4; /*!< [19..16] External Bus Clock (BCLK) Select */
|
|
|
+ __IOM uint32_t PCKE : 4; /*!< [23..20] Peripheral Module Clock E (PCLKE) Select */
|
|
|
+ __IOM uint32_t ICK : 4; /*!< [27..24] System Clock (ICLK) Select */
|
|
|
+ __IOM uint32_t FCK : 4; /*!< [31..28] Flash IF Clock (FCLK) Select */
|
|
|
+ } SCKDIVCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t CPUCK : 4; /*!< [3..0] CPU Clock (CPUCLK) Select */
|
|
|
+ uint8_t : 4;
|
|
|
+ } SCKDIVCR2_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED6;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SCKSCR; /*!< (@ 0x00000026) System Clock Source Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t CKSEL : 3; /*!< [2..0] Clock Source Select */
|
|
|
+ uint8_t : 5;
|
|
|
+ } SCKSCR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED7;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t PLIDIV : 2; /*!< [1..0] PLL1 Input Frequency Division Ratio Select */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL1 Clock Source Select */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t PLLMULNF : 2; /*!< [7..6] PLL1 Frequency Multiplication Fractional Factor Select */
|
|
|
+ __IOM uint16_t PLLMUL : 8; /*!< [15..8] PLL1 Frequency Multiplication Factor Select */
|
|
|
+ } PLLCCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t PLLCR; /*!< (@ 0x0000002A) PLL Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t PLLSTP : 1; /*!< [0..0] PLL Stop Control */
|
|
|
+ uint8_t : 7;
|
|
|
+ } PLLCR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED8;
|
|
|
+ __IM uint32_t RESERVED9;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t BCKCR; /*!< (@ 0x00000030) External Bus Clock Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select */
|
|
|
+ uint8_t : 7;
|
|
|
+ } BCKCR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED10;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t MOSCCR; /*!< (@ 0x00000032) Main Clock Oscillator Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t MOSTP : 1; /*!< [0..0] Main Clock Oscillator Stop */
|
|
|
+ uint8_t : 7;
|
|
|
+ } MOSCCR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED11;
|
|
|
+ __IM uint16_t RESERVED12;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t HOCOCR; /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t HCSTP : 1; /*!< [0..0] HOCO Stop */
|
|
|
+ uint8_t : 7;
|
|
|
+ } HOCOCR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED13;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t MOCOCR; /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t MCSTP : 1; /*!< [0..0] MOCO Stop */
|
|
|
+ uint8_t : 7;
|
|
|
+ } MOCOCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t FLLCR1; /*!< (@ 0x00000039) FLL Control Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t FLLEN : 1; /*!< [0..0] FLL Enable */
|
|
|
+ uint8_t : 7;
|
|
|
+ } FLLCR1_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t FLLCR2; /*!< (@ 0x0000003A) FLL Control Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication Control */
|
|
|
+ uint16_t : 5;
|
|
|
+ } FLLCR2_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint8_t OSCSF; /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint8_t HOCOSF : 1; /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF
|
|
|
+ * bit value after a reset is 1 when the OFS1.HOCOEN bit is
|
|
|
+ * 0. It is 0 when the OFS1.HOCOEN bit is 1. */
|
|
|
+ uint8_t : 2;
|
|
|
+ __IM uint8_t MOSCSF : 1; /*!< [3..3] Main Clock Oscillation Stabilization Flag */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IM uint8_t PLLSF : 1; /*!< [5..5] PLL1 Clock Oscillation Stabilization Flag */
|
|
|
+ __IM uint8_t PLL2SF : 1; /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag */
|
|
|
+ uint8_t : 1;
|
|
|
+ } OSCSF_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED14;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t CKOCR; /*!< (@ 0x0000003E) Clock Out Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint8_t : 4;
|
|
|
+ __IOM uint8_t CKODIV : 3; /*!< [6..4] Clock out input frequency Division Select */
|
|
|
+ __IOM uint8_t CKOEN : 1; /*!< [7..7] Clock out enable */
|
|
|
+ } CKOCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t TRCKCR; /*!< (@ 0x0000003F) Trace Clock Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t TRCK : 4; /*!< [3..0] Trace Clock operating frequency select */
|
|
|
+ __IOM uint8_t TRCKSEL : 1; /*!< [4..4] Trace Clock source select */
|
|
|
+ uint8_t : 2;
|
|
|
+ __IOM uint8_t TRCKEN : 1; /*!< [7..7] Trace Clock operating Enable */
|
|
|
+ } TRCKCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t OSTDCR; /*!< (@ 0x00000040) Oscillation Stop Detection Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t OSTDIE : 1; /*!< [0..0] Oscillation Stop Detection Interrupt Enable */
|
|
|
+ uint8_t : 6;
|
|
|
+ __IOM uint8_t OSTDE : 1; /*!< [7..7] Oscillation Stop Detection Function Enable */
|
|
|
+ } OSTDCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t OSTDSR; /*!< (@ 0x00000041) Oscillation Stop Detection Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t OSTDF : 1; /*!< [0..0] Oscillation Stop Detection Flag */
|
|
|
+ uint8_t : 7;
|
|
|
+ } OSTDSR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED15;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint8_t OSCMONR; /*!< (@ 0x00000043) Oscillator Monitor Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint8_t : 1;
|
|
|
+ __IM uint8_t MOCOMON : 1; /*!< [1..1] MOCO operation monitor */
|
|
|
+ __IM uint8_t LOCOMON : 1; /*!< [2..2] LOCO operation monitor */
|
|
|
+ uint8_t : 5;
|
|
|
+ } OSCMONR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED16;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t PLL2CCR; /*!< (@ 0x00000048) PLL2 Clock Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t PL2IDIV : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IOM uint16_t PL2SRCSEL : 1; /*!< [4..4] PLL Clock Source Select */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t PLL2MULNF : 2; /*!< [7..6] PLL2 Frequency Multiplication Fractional Factor Select */
|
|
|
+ __IOM uint16_t PLL2MUL : 8; /*!< [15..8] PLL2 Frequency Multiplication Factor Select */
|
|
|
+ } PLL2CCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t PLL2CR; /*!< (@ 0x0000004A) PLL2 Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control */
|
|
|
+ uint8_t : 7;
|
|
|
+ } PLL2CR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED17;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t PLLCCR2; /*!< (@ 0x0000004C) PLL Clock Control Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t PLODIVP : 4; /*!< [3..0] PLL1 Output Frequency Division Ratio Select for output
|
|
|
+ * clock P */
|
|
|
+ __IOM uint16_t PLODIVQ : 4; /*!< [7..4] PLL1 Output Frequency Division Ratio Select for output
|
|
|
+ * clock Q */
|
|
|
+ __IOM uint16_t PLODIVR : 4; /*!< [11..8] PLL1 Output Frequency Division Ratio Select for output
|
|
|
+ * clock R */
|
|
|
+ uint16_t : 4;
|
|
|
+ } PLLCCR2_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t PLL2CCR2; /*!< (@ 0x0000004E) PLL2 Clock Control Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t PL2ODIVP : 4; /*!< [3..0] PLL2 Output Frequency Division Ratio Select for output
|
|
|
+ * clock P */
|
|
|
+ __IOM uint16_t PL2ODIVQ : 4; /*!< [7..4] PLL2 Output Frequency Division Ratio Select for output
|
|
|
+ * clock Q */
|
|
|
+ __IOM uint16_t PL2ODIVR : 4; /*!< [11..8] PLL2 Output Frequency Division Ratio Select for output
|
|
|
+ * clock R */
|
|
|
+ uint16_t : 4;
|
|
|
+ } PLL2CCR2_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED18;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t EBCKOCR; /*!< (@ 0x00000052) External Bus Clock Output Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t EBCKOEN : 1; /*!< [0..0] BCLK Pin Output Control */
|
|
|
+ uint8_t : 7;
|
|
|
+ } EBCKOCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SDCKOCR; /*!< (@ 0x00000053) SDRAM Clock Output Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control */
|
|
|
+ uint8_t : 7;
|
|
|
+ } SDCKOCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SCICKDIVCR; /*!< (@ 0x00000054) SCI clock Division control register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t CKDIV : 3; /*!< [2..0] Clock Division Select */
|
|
|
+ uint8_t : 5;
|
|
|
+ } SCICKDIVCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SCICKCR; /*!< (@ 0x00000055) SCI clock control register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t SCICKSEL : 4; /*!< [3..0] Clock Source Select */
|
|
|
+ uint8_t : 2;
|
|
|
+ __IOM uint8_t CKSREQ : 1; /*!< [6..6] Clock Switching Request */
|
|
|
+ __IM uint8_t CKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */
|
|
|
+ } SCICKCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SPICKDIVCR; /*!< (@ 0x00000056) SPI clock Division control register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t CKDIV : 3; /*!< [2..0] Clock Division Select */
|
|
|
+ uint8_t : 5;
|
|
|
+ } SPICKDIVCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SPICKCR; /*!< (@ 0x00000057) SPI clock control register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t CKSEL : 4; /*!< [3..0] Clock Source Select */
|
|
|
+ uint8_t : 2;
|
|
|
+ __IOM uint8_t CKSREQ : 1; /*!< [6..6] Clock Switching Request */
|
|
|
+ __IM uint8_t CKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */
|
|
|
+ } SPICKCR_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED19;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ADCCKDIVCR; /*!< (@ 0x0000005A) ADC clock Division control register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t CKDIV : 3; /*!< [2..0] Clock Division Select */
|
|
|
+ uint8_t : 5;
|
|
|
+ } ADCCKDIVCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ADCCKCR; /*!< (@ 0x0000005B) ADC clock control register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t CKSEL : 4; /*!< [3..0] Clock Source Select */
|
|
|
+ uint8_t : 2;
|
|
|
+ __IOM uint8_t CKSREQ : 1; /*!< [6..6] Clock Switching Request */
|
|
|
+ __IM uint8_t CKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */
|
|
|
+ } ADCCKCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000005C) GPT clock Division control register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t CKDIV : 3; /*!< [2..0] Clock Division Select */
|
|
|
+ uint8_t : 5;
|
|
|
+ } GPTCKDIVCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t GPTCKCR; /*!< (@ 0x0000005D) GPT clock control register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t CKSEL : 4; /*!< [3..0] Clock Source Select */
|
|
|
+ uint8_t : 2;
|
|
|
+ __IOM uint8_t CKSREQ : 1; /*!< [6..6] Clock Switching Request */
|
|
|
+ __IM uint8_t CKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */
|
|
|
+ } GPTCKCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t LCDCKDIVCR; /*!< (@ 0x0000005E) LCD clock Division control register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t CKDIV : 3; /*!< [2..0] Clock Division Select */
|
|
|
+ uint8_t : 5;
|
|
|
+ } LCDCKDIVCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t LCDCKCR; /*!< (@ 0x0000005F) LCD clock control register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t CKSEL : 4; /*!< [3..0] Clock Source Select */
|
|
|
+ uint8_t : 2;
|
|
|
+ __IOM uint8_t CKSREQ : 1; /*!< [6..6] Clock Switching Request */
|
|
|
+ __IM uint8_t CKSRDY : 1; /*!< [7..7] Clock Switching Ready state flag */
|
|
|
+ } LCDCKCR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED20;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t MOCOUTCR; /*!< (@ 0x00000061) MOCO User Trimming Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127
|
|
|
+ * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center
|
|
|
+ * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 :
|
|
|
+ +126 0111_1111 : +127These bits are added to original MOCO
|
|
|
+ * trimming bits */
|
|
|
+ } MOCOUTCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t HOCOUTCR; /*!< (@ 0x00000062) HOCO User Trimming Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127
|
|
|
+ * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center
|
|
|
+ * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 :
|
|
|
+ +126 0111_1111 : +127These bits are added to original HOCO
|
|
|
+ * trimming bits */
|
|
|
+ } HOCOUTCR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED21;
|
|
|
+ __IM uint32_t RESERVED22[2];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t USBCKDIVCR; /*!< (@ 0x0000006C) USB clock Division control register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t USBCKDIV : 3; /*!< [2..0] USB clock (USBCLK) Division Select */
|
|
|
+ uint8_t : 5;
|
|
|
+ } USBCKDIVCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t OCTACKDIVCR; /*!< (@ 0x0000006D) Octal-SPI clock Division control register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t OCTACKDIV : 3; /*!< [2..0] Octal-SPI clock (OCTACLK) Division Select */
|
|
|
+ uint8_t : 5;
|
|
|
+ } OCTACKDIVCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t CANFDCKDIVCR; /*!< (@ 0x0000006E) CANFD Core clock Division control register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t CANFDCKDIV : 3; /*!< [2..0] CANFD Core clock (CANFDCLK) Division Select */
|
|
|
+ uint8_t : 5;
|
|
|
+ } CANFDCKDIVCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t USB60CKDIVCR; /*!< (@ 0x0000006F) USB60 clock Division control register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t USB60CKDIV : 3; /*!< [2..0] USB clock (USB60CLK) Division Select */
|
|
|
+ uint8_t : 5;
|
|
|
+ } USB60CKDIVCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t I3CCKDIVCR; /*!< (@ 0x00000070) I3C clock Division control register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t I3CCKDIV : 3; /*!< [2..0] I3C clock (I3CCLK) Division Select */
|
|
|
+ uint8_t : 5;
|
|
|
+ } I3CCKDIVCR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED23;
|
|
|
+ __IM uint16_t RESERVED24;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t USBCKCR; /*!< (@ 0x00000074) USB clock control register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t USBCKSEL : 4; /*!< [3..0] USB clock (USBCLK) Source Select */
|
|
|
+ uint8_t : 2;
|
|
|
+ __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB clock (USBCLK) Switching Request */
|
|
|
+ __IOM uint8_t USBCKSRDY : 1; /*!< [7..7] USB clock (USBCLK) Switching Ready state flag */
|
|
|
+ } USBCKCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t OCTACKCR; /*!< (@ 0x00000075) Octal-SPI clock control register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t OCTACKSEL : 4; /*!< [3..0] Octal-SPI clock (OCTACLK) Source Select */
|
|
|
+ uint8_t : 2;
|
|
|
+ __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI clock (OCTACLK) Switching Request */
|
|
|
+ __IOM uint8_t OCTACKSRDY : 1; /*!< [7..7] Octal-SPI clock (OCTACLK) Switching Ready state flag */
|
|
|
+ } OCTACKCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t CANFDCKCR; /*!< (@ 0x00000076) CANFD Core clock control register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t CANFDCKSEL : 4; /*!< [3..0] CANFD Core clock (CANFDCLK) Source Select */
|
|
|
+ uint8_t : 2;
|
|
|
+ __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Core clock (CANFDCLK) Switching Request */
|
|
|
+ __IOM uint8_t CANFDCKSRDY : 1; /*!< [7..7] CANFD Core clock (CANFDCLK) Switching Ready state flag */
|
|
|
+ } CANFDCKCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t USB60CKCR; /*!< (@ 0x00000077) USB60 clock control register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t USB60CKSEL : 4; /*!< [3..0] USB clock (USB60CLK) Source Select */
|
|
|
+ uint8_t : 2;
|
|
|
+ __IOM uint8_t USB60CKSREQ : 1; /*!< [6..6] USB clock (USB60CLK) Switching Request */
|
|
|
+ __IOM uint8_t USB60CKSRDY : 1; /*!< [7..7] USB clock (USB60CLK) Switching Ready state flag */
|
|
|
+ } USB60CKCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t I3CCKCR; /*!< (@ 0x00000078) I3C clock control register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t I3CCKSEL : 4; /*!< [3..0] I3C clock (I3CCLK) Source Select */
|
|
|
+ uint8_t : 2;
|
|
|
+ __IOM uint8_t I3CCKREQ : 1; /*!< [6..6] I3C clock (I3CCLK) Switching Request */
|
|
|
+ __IOM uint8_t I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) Switching Ready state flag */
|
|
|
+ } I3CCKCR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED25;
|
|
|
+ __IM uint16_t RESERVED26;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t MOSCSCR; /*!< (@ 0x0000007C) Main Clock Oscillator Standby Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t MOSCSOKP : 1; /*!< [0..0] Main Clock Oscillator Standby Oscillation Keep select */
|
|
|
+ uint8_t : 7;
|
|
|
+ } MOSCSCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t HOCOSCR; /*!< (@ 0x0000007D) High-Speed On-Chip Oscillator Standby Control
|
|
|
+ * Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t HOCOSOKP : 1; /*!< [0..0] HOCO Standby Oscillation Keep select */
|
|
|
+ uint8_t : 7;
|
|
|
+ } HOCOSCR_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED27;
|
|
|
+ __IM uint32_t RESERVED28[2];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SNZREQCR1; /*!< (@ 0x00000088) Snooze Request Control Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Enable AGT0 underflow snooze request */
|
|
|
+ __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Enable AGT1 underflow snooze request */
|
|
|
+ __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Enable AGT2 underflow snooze request */
|
|
|
+ uint32_t : 29;
|
|
|
+ } SNZREQCR1_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED29;
|
|
|
+ __IM uint16_t RESERVED30;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SNZCR; /*!< (@ 0x00000092) Snooze Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t RXDREQEN : 1; /*!< [0..0] RXD0 Snooze Request Enable NOTE: Do not set to 1 other
|
|
|
+ * than in asynchronous mode. */
|
|
|
+ __IOM uint8_t SNZDTCEN : 1; /*!< [1..1] DTC Enable in Snooze Mode */
|
|
|
+ uint8_t : 5;
|
|
|
+ __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */
|
|
|
+ } SNZCR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED31;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SNZEDCR; /*!< (@ 0x00000094) Snooze End Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t AGT1UNFED : 1; /*!< [0..0] AGT1 underflow Snooze End Enable */
|
|
|
+ __IOM uint8_t DTCZRED : 1; /*!< [1..1] Last DTC transmission completion Snooze End Enable */
|
|
|
+ __IOM uint8_t DTCNZRED : 1; /*!< [2..2] Not Last DTC transmission completion Snooze End Enable */
|
|
|
+ __IOM uint8_t AD0MATED : 1; /*!< [3..3] AD compare match 0 Snooze End Enable */
|
|
|
+ __IOM uint8_t AD0UMTED : 1; /*!< [4..4] AD compare mismatch 0 Snooze End Enable */
|
|
|
+ __IOM uint8_t AD1MATED : 1; /*!< [5..5] AD compare match 1 Snooze End Enable */
|
|
|
+ __IOM uint8_t AD1UMTED : 1; /*!< [6..6] AD compare mismatch 1 Snooze End Enable */
|
|
|
+ __IOM uint8_t SCI0UMTED : 1; /*!< [7..7] SCI0 address unmatch Snooze End EnableNote: Do not set
|
|
|
+ * to 1 other than in asynchronous mode. */
|
|
|
+ } SNZEDCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SNZEDCR1; /*!< (@ 0x00000095) Snooze End Control Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t AGT3UNFED : 1; /*!< [0..0] AGT3 underflow Snooze End Enable */
|
|
|
+ uint8_t : 7;
|
|
|
+ } SNZEDCR1_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED32;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SNZREQCR; /*!< (@ 0x00000098) Snooze Request Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Snooze Request Enable 0. Enable IRQ pin snooze request */
|
|
|
+ __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Snooze Request Enable 1. Enable IRQ pin snooze request */
|
|
|
+ __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Snooze Request Enable 2. Enable IRQ pin snooze request */
|
|
|
+ __IOM uint32_t SNZREQEN3 : 1; /*!< [3..3] Snooze Request Enable 3. Enable IRQ pin snooze request */
|
|
|
+ __IOM uint32_t SNZREQEN4 : 1; /*!< [4..4] Snooze Request Enable 4. Enable IRQ pin snooze request */
|
|
|
+ __IOM uint32_t SNZREQEN5 : 1; /*!< [5..5] Snooze Request Enable 5. Enable IRQ pin snooze request */
|
|
|
+ __IOM uint32_t SNZREQEN6 : 1; /*!< [6..6] Snooze Request Enable 6. Enable IRQ pin snooze request */
|
|
|
+ __IOM uint32_t SNZREQEN7 : 1; /*!< [7..7] Snooze Request Enable 7. Enable IRQ pin snooze request */
|
|
|
+ __IOM uint32_t SNZREQEN8 : 1; /*!< [8..8] Snooze Request Enable 8. Enable IRQ pin snooze request */
|
|
|
+ __IOM uint32_t SNZREQEN9 : 1; /*!< [9..9] Snooze Request Enable 9. Enable IRQ pin snooze request */
|
|
|
+ __IOM uint32_t SNZREQEN10 : 1; /*!< [10..10] Snooze Request Enable 10. Enable IRQ pin snooze request */
|
|
|
+ __IOM uint32_t SNZREQEN11 : 1; /*!< [11..11] Snooze Request Enable 11. Enable IRQ pin snooze request */
|
|
|
+ __IOM uint32_t SNZREQEN12 : 1; /*!< [12..12] Snooze Request Enable 12. Enable IRQ pin snooze request */
|
|
|
+ __IOM uint32_t SNZREQEN13 : 1; /*!< [13..13] Snooze Request Enable 13. Enable IRQ pin snooze request */
|
|
|
+ __IOM uint32_t SNZREQEN14 : 1; /*!< [14..14] Snooze Request Enable 14. Enable IRQ pin snooze request */
|
|
|
+ __IOM uint32_t SNZREQEN15 : 1; /*!< [15..15] Snooze Request Enable 15. Enable IRQ pin snooze request */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t SNZREQEN17 : 1; /*!< [17..17] Snooze Request Enable 17 Enable KR snooze request */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t SNZREQEN22 : 1; /*!< [22..22] Snooze Request Enable 22 Enable Comparator-HS0 snooze
|
|
|
+ * request */
|
|
|
+ __IOM uint32_t SNZREQEN23 : 1; /*!< [23..23] Snooze Request Enable 23 Enable Comparator-LP0 snooze
|
|
|
+ * request */
|
|
|
+ __IOM uint32_t SNZREQEN24 : 1; /*!< [24..24] Snooze Request Enable 24 Enable RTC alarm snooze request */
|
|
|
+ __IOM uint32_t SNZREQEN25 : 1; /*!< [25..25] Snooze Request Enable 25 Enable RTC period snooze request */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t SNZREQEN28 : 1; /*!< [28..28] Snooze Request Enable 28 Enable AGT1 underflow snooze
|
|
|
+ * request */
|
|
|
+ __IOM uint32_t SNZREQEN29 : 1; /*!< [29..29] Snooze Request Enable 29 Enable AGT1 compare match
|
|
|
+ * A snooze request */
|
|
|
+ __IOM uint32_t SNZREQEN30 : 1; /*!< [30..30] Snooze Request Enable 30 Enable AGT1 compare match
|
|
|
+ * B snooze request */
|
|
|
+ uint32_t : 1;
|
|
|
+ } SNZREQCR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED33;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t OPCCR; /*!< (@ 0x000000A0) Operating Power Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t OPCM : 2; /*!< [1..0] Operating Power Control Mode Select */
|
|
|
+ uint8_t : 2;
|
|
|
+ __IM uint8_t OPCMTSF : 1; /*!< [4..4] Operating Power Control Mode Transition Status Flag */
|
|
|
+ uint8_t : 3;
|
|
|
+ } OPCCR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED34;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t MOSCWTCR; /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t MSTS : 4; /*!< [3..0] Main clock oscillator wait time setting */
|
|
|
+ uint8_t : 4;
|
|
|
+ } MOSCWTCR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED35[2];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t HOCOWTCR; /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t HSTS : 3; /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of
|
|
|
+ * the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) */
|
|
|
+ uint8_t : 5;
|
|
|
+ } HOCOWTCR_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED36[2];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SOPCCR; /*!< (@ 0x000000AA) Sub Operating Power Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t SOPCM : 1; /*!< [0..0] Sub Operating Power Control Mode Select */
|
|
|
+ uint8_t : 3;
|
|
|
+ __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag */
|
|
|
+ uint8_t : 3;
|
|
|
+ } SOPCCR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED37;
|
|
|
+ __IM uint32_t RESERVED38[5];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t RSTSR1; /*!< (@ 0x000000C0) Reset Status Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect Flag. NOTE: Writable
|
|
|
+ * only to clear the flag. Confirm the value is 1 and then
|
|
|
+ * write 0. */
|
|
|
+ __IOM uint32_t WDTRF : 1; /*!< [1..1] Watchdog Timer0 Reset Detect Flag. NOTE: Writable only
|
|
|
+ * to clear the flag. Confirm the value is 1 and then write
|
|
|
+ * 0. */
|
|
|
+ __IOM uint32_t SWRF : 1; /*!< [2..2] Software Reset Detect Flag. NOTE: Writable only to clear
|
|
|
+ * the flag. Confirm the value is 1 and then write 0. */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t CLU0RF : 1; /*!< [4..4] CPU0 Lockup Reset Detect Flag. NOTE: Writable only to
|
|
|
+ * clear the flag. Confirm the value is 1 and then write 0. */
|
|
|
+ __IOM uint32_t LM0RF : 1; /*!< [5..5] Local memory 0 error Reset Detect Flag. NOTE: Writable
|
|
|
+ * only to clear the flag. Confirm the value is 1 and then
|
|
|
+ * write 0. */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t BUSRF : 1; /*!< [10..10] Bus error Reset Detect Flag. NOTE: Writable only to
|
|
|
+ * clear the flag. Confirm the value is 1 and then write 0. */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t CMRF : 1; /*!< [14..14] Common memory error Reset Detect Flag. NOTE: Writable
|
|
|
+ * only to clear the flag. Confirm the value is 1 and then
|
|
|
+ * write 0. */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t WDT1RF : 1; /*!< [17..17] Watchdog Timer1 Reset Detect Flag. NOTE: Writable only
|
|
|
+ * to clear the flag. Confirm the value is 1 and then write
|
|
|
+ * 0. */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t CLU1RF : 1; /*!< [20..20] CPU1 Lockup Reset Detect Flag. NOTE: Writable only
|
|
|
+ * to clear the flag. Confirm the value is 1 and then write
|
|
|
+ * 0. */
|
|
|
+ __IOM uint32_t LM1RF : 1; /*!< [21..21] Local memory 1 error Reset Detect Flag. NOTE: Writable
|
|
|
+ * only to clear the flag. Confirm the value is 1 and then
|
|
|
+ * write 0. */
|
|
|
+ __IOM uint32_t NWRF : 1; /*!< [22..22] Network Reset Detect Flag. NOTE: Writable only to clear
|
|
|
+ * the flag. Confirm the value is 1 and then write 0. */
|
|
|
+ uint32_t : 9;
|
|
|
+ } RSTSR1_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED39[2];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SYRACCR; /*!< (@ 0x000000CC) System Register Access Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t BUSY : 1; /*!< [0..0] Access Ready monitor */
|
|
|
+ uint8_t : 7;
|
|
|
+ } SYRACCR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED40;
|
|
|
+ __IM uint16_t RESERVED41;
|
|
|
+ __IM uint32_t RESERVED42[4];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t LVD1CR1; /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */
|
|
|
+ __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */
|
|
|
+ uint8_t : 5;
|
|
|
+ } LVD1CR1_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t LVD1SR; /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only
|
|
|
+ * 0 can be written to this bit. After writing 0 to this bit,
|
|
|
+ * it takes 2 system clock cycles for the bit to be read as
|
|
|
+ * 0. */
|
|
|
+ __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor Signal Monitor Flag */
|
|
|
+ uint8_t : 6;
|
|
|
+ } LVD1SR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t LVD2CR1; /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */
|
|
|
+ __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */
|
|
|
+ uint8_t : 5;
|
|
|
+ } LVD2CR1_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t LVD2SR; /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only
|
|
|
+ * 0 can be written to this bit. After writing 0 to this bit,
|
|
|
+ * it takes 2 system clock cycles for the bit to be read as
|
|
|
+ * 0. */
|
|
|
+ __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor Signal Monitor Flag */
|
|
|
+ uint8_t : 6;
|
|
|
+ } LVD2SR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED43[3];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t CRVSYSCR; /*!< (@ 0x000000F0) Clock Recovery System Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t CRVEN : 1; /*!< [0..0] Clock Recovery Enable */
|
|
|
+ uint8_t : 7;
|
|
|
+ } CRVSYSCR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED44;
|
|
|
+ __IM uint16_t RESERVED45;
|
|
|
+ __IM uint32_t RESERVED46[7];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t PDCTRGD; /*!< (@ 0x00000110) Graphics Power Domain Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t PDDE : 1; /*!< [0..0] Power control enable */
|
|
|
+ uint8_t : 5;
|
|
|
+ __IM uint8_t PDCSF : 1; /*!< [6..6] Power control status flag */
|
|
|
+ __IM uint8_t PDPGSF : 1; /*!< [7..7] Power gating status flag */
|
|
|
+ } PDCTRGD_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED47;
|
|
|
+ __IM uint16_t RESERVED48;
|
|
|
+ __IM uint32_t RESERVED49[11];
|
|
|
+ __IOM uint16_t PDRAMSCR0; /*!< (@ 0x00000140) SRAM power domain Standby Control Register 0 */
|
|
|
+ __IOM uint8_t PDRAMSCR1; /*!< (@ 0x00000142) SRAM power domain Standby Control Register 1 */
|
|
|
+ __IM uint8_t RESERVED50;
|
|
|
+ __IM uint32_t RESERVED51[155];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t VBRSABAR; /*!< (@ 0x000003B0) VBATT Backup Register Security Attribute Boundary
|
|
|
+ * Address Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t SABA : 16; /*!< [15..0] Security Attribute Boundary Address */
|
|
|
+ } VBRSABAR_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED52;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t VBRPABARS; /*!< (@ 0x000003B4) VBATT Backup Register Privilege Attribute Boundary
|
|
|
+ * Address Register for Secure Region */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t PABAS : 16; /*!< [15..0] Privilege Attribute Boundary Address for Secure Region */
|
|
|
+ } VBRPABARS_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED53;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t VBRPABARNS; /*!< (@ 0x000003B8) VBATT Backup Register Privilege Attribute Boundary
|
|
|
+ * Address Register for Non-secure Region */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t PABANS : 16; /*!< [15..0] Privilege Attribute Boundary Address for Non-secure
|
|
|
+ * Region */
|
|
|
+ } VBRPABARNS_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED54;
|
|
|
+ __IM uint32_t RESERVED55;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CGFSAR; /*!< (@ 0x000003C0) Clock Generation Function Security Attribute
|
|
|
+ * Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non-secure Attribute bit 0 */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non-secure Attribute bit 2 */
|
|
|
+ __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non-secure Attribute bit 3 */
|
|
|
+ __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non-secure Attribute bit 4 */
|
|
|
+ __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non-secure Attribute bit 5 */
|
|
|
+ __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non-secure Attribute bit 6 */
|
|
|
+ __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non-secure Attribute bit 7 */
|
|
|
+ __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non-secure Attribute bit 8 */
|
|
|
+ __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non-secure Attribute bit 9 */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non-secure Attribute bit 11 */
|
|
|
+ __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non-secure Attribute bit 12 */
|
|
|
+ __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non-secure Attribute bit 13 */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non-secure Attribute bit 16 */
|
|
|
+ __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non-secure Attribute bit 17 */
|
|
|
+ __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non-secure Attribute bit 18 */
|
|
|
+ __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non-secure Attribute bit 19 */
|
|
|
+ __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non-secure Attribute bit 20 */
|
|
|
+ __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non-secure Attribute bit 21 */
|
|
|
+ __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non-secure Attribute bit 22 */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non-secure Attribute bit 24 */
|
|
|
+ __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non-secure Attribute bit 25 */
|
|
|
+ __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non-secure Attribute bit 26 */
|
|
|
+ uint32_t : 5;
|
|
|
+ } CGFSAR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t RSTSAR; /*!< (@ 0x000003C4) Reset Security Attribution Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non-secure Attribute bit 0 */
|
|
|
+ __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non-secure Attribute bit 1 */
|
|
|
+ __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non-secure Attribute bit 2 */
|
|
|
+ __IOM uint32_t NONSEC3 : 1; /*!< [3..3] Non-secure Attribute bit 3 */
|
|
|
+ uint32_t : 28;
|
|
|
+ } RSTSAR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t LPMSAR; /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non-secure Attribute bit 00 */
|
|
|
+ __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non-secure Attribute bit 01 */
|
|
|
+ __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non-secure Attribute bit 02 */
|
|
|
+ __IOM uint32_t NONSEC3 : 1; /*!< [3..3] Non-secure Attribute bit 03 */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non-secure Attribute bit 08 */
|
|
|
+ uint32_t : 7;
|
|
|
+ __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non-secure Attribute bit 16 */
|
|
|
+ __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non-secure Attribute bit 17 */
|
|
|
+ __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non-secure Attribute bit 18 */
|
|
|
+ __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non-secure Attribute bit 19 */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non-secure Attribute bit 21 */
|
|
|
+ uint32_t : 10;
|
|
|
+ } LPMSAR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t LVDSAR; /*!< (@ 0x000003CC) Programable Voltage Detection Security Attribution
|
|
|
+ * Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non-secure Attribute bit 0 */
|
|
|
+ __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non-secure Attribute bit 1 */
|
|
|
+ uint32_t : 30;
|
|
|
+ } LVDSAR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t BBFSAR; /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non-secure Attribute bit 0 */
|
|
|
+ __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non-secure Attribute bit 1 */
|
|
|
+ __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non-secure Attribute bit 2 */
|
|
|
+ __IOM uint32_t NONSEC3 : 1; /*!< [3..3] Non-secure Attribute bit 3 */
|
|
|
+ __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non-secure Attribute bit 4 */
|
|
|
+ uint32_t : 27;
|
|
|
+ } BBFSAR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED56;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t PGCSAR; /*!< (@ 0x000003D8) Power Gating Control Security Attribution Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non-secure Attribute bit 01 */
|
|
|
+ __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non-secure Attribute bit 02 */
|
|
|
+ uint32_t : 29;
|
|
|
+ } PGCSAR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED57;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t DPFSAR; /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution
|
|
|
+ * Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 16;
|
|
|
+ __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit
|
|
|
+ * 16 */
|
|
|
+ __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit
|
|
|
+ * 17 */
|
|
|
+ __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit
|
|
|
+ * 18 */
|
|
|
+ __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit
|
|
|
+ * 19 */
|
|
|
+ __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit
|
|
|
+ * 20 */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit
|
|
|
+ * 24 */
|
|
|
+ __IOM uint32_t DPFSA25 : 1; /*!< [25..25] Deep Standby Interrupt Factor Security Attribute bit
|
|
|
+ * 25 */
|
|
|
+ __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit
|
|
|
+ * 26 */
|
|
|
+ __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit
|
|
|
+ * 27 */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t DPFSA29 : 1; /*!< [29..29] Deep Standby Interrupt Factor Security Attribute bit
|
|
|
+ * 29 */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t DPFSA31 : 1; /*!< [31..31] Deep Standby Interrupt Factor Security Attribute bit
|
|
|
+ * 31 */
|
|
|
+ } DPFSAR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t RSCSAR; /*!< (@ 0x000003E4) RAM Standby Control Security Attribution Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t RSCSA0 : 1; /*!< [0..0] RAM Standby Control Security Attribute bit 00 */
|
|
|
+ __IOM uint32_t RSCSA1 : 1; /*!< [1..1] RAM Standby Control Security Attribute bit 01 */
|
|
|
+ __IOM uint32_t RSCSA2 : 1; /*!< [2..2] RAM Standby Control Security Attribute bit 02 */
|
|
|
+ __IOM uint32_t RSCSA3 : 1; /*!< [3..3] RAM Standby Control Security Attribute bit 03 */
|
|
|
+ __IOM uint32_t RSCSA4 : 1; /*!< [4..4] RAM Standby Control Security Attribute bit 04 */
|
|
|
+ __IOM uint32_t RSCSA5 : 1; /*!< [5..5] RAM Standby Control Security Attribute bit 05 */
|
|
|
+ __IOM uint32_t RSCSA6 : 1; /*!< [6..6] RAM Standby Control Security Attribute bit 06 */
|
|
|
+ __IOM uint32_t RSCSA7 : 1; /*!< [7..7] RAM Standby Control Security Attribute bit 07 */
|
|
|
+ __IOM uint32_t RSCSA8 : 1; /*!< [8..8] RAM Standby Control Security Attribute bit 08 */
|
|
|
+ __IOM uint32_t RSCSA9 : 1; /*!< [9..9] RAM Standby Control Security Attribute bit 09 */
|
|
|
+ __IOM uint32_t RSCSA10 : 1; /*!< [10..10] RAM Standby Control Security Attribute bit 10 */
|
|
|
+ __IOM uint32_t RSCSA11 : 1; /*!< [11..11] RAM Standby Control Security Attribute bit 11 */
|
|
|
+ __IOM uint32_t RSCSA12 : 1; /*!< [12..12] RAM Standby Control Security Attribute bit 12 */
|
|
|
+ __IOM uint32_t RSCSA13 : 1; /*!< [13..13] RAM Standby Control Security Attribute bit 13 */
|
|
|
+ __IOM uint32_t RSCSA14 : 1; /*!< [14..14] RAM Standby Control Security Attribute bit 14 */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t RSCSA16 : 1; /*!< [16..16] RAM Standby Control Security Attribute bit 16 */
|
|
|
+ __IOM uint32_t RSCSA17 : 1; /*!< [17..17] RAM Standby Control Security Attribute bit 17 */
|
|
|
+ uint32_t : 14;
|
|
|
+ } RSCSAR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED58[4];
|
|
|
+ __IM uint16_t RESERVED59;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t PRCR; /*!< (@ 0x000003FA) Protect Register for Secure Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock
|
|
|
+ * generation circuit. */
|
|
|
+ __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating
|
|
|
+ * modes, the low power modes, and the battery backup function. */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the PVD. */
|
|
|
+ __IOM uint16_t PRC4 : 1; /*!< [4..4] Enables writing to the registers related to the security
|
|
|
+ * and privilege setting registers. */
|
|
|
+ __IOM uint16_t PRC5 : 1; /*!< [5..5] Enables writing to the registers related the reset control. */
|
|
|
+ uint16_t : 2;
|
|
|
+ __OM uint16_t PRKEY : 8; /*!< [15..8] PRC Key Code */
|
|
|
+ } PRCR_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED60;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t PRCR_NS; /*!< (@ 0x000003FE) Protect Register for Non-secure Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock
|
|
|
+ * generation circuit. */
|
|
|
+ __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating
|
|
|
+ * modes, the low power modes, and the battery backup function. */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the PVD. */
|
|
|
+ __IOM uint16_t PRC4 : 1; /*!< [4..4] Enables writing to the registers related to the privilege
|
|
|
+ * setting registers. */
|
|
|
+ uint16_t : 3;
|
|
|
+ __OM uint16_t PRKEY : 8; /*!< [15..8] PRC Key Code */
|
|
|
+ } PRCR_NS_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t LOCOCR; /*!< (@ 0x00000400) Low-Speed On-Chip Oscillator Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t LCSTP : 1; /*!< [0..0] LOCO Stop */
|
|
|
+ uint8_t : 7;
|
|
|
+ } LOCOCR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED61;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t LOCOUTCR; /*!< (@ 0x00000402) LOCO User Trimming Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming */
|
|
|
+ } LOCOUTCR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED62;
|
|
|
+ __IM uint32_t RESERVED63[2];
|
|
|
+ __IM uint16_t RESERVED64;
|
|
|
+ __IM uint8_t RESERVED65;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t STCONR; /*!< (@ 0x0000040F) Standby Condition Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t STCON : 2; /*!< [1..0] SSTBY condition bit */
|
|
|
+ uint8_t : 6;
|
|
|
+ } STCONR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED66[380];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t DPSBYCR; /*!< (@ 0x00000A00) Deep Standby Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint8_t : 2;
|
|
|
+ __IOM uint8_t DCSSMODE : 1; /*!< [2..2] DCDC SSMODE */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t SRKEEP : 1; /*!< [4..4] Standby RAM Retention */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t IOKEEP : 1; /*!< [6..6] I/O Port Retention */
|
|
|
+ __IOM uint8_t DPSBY : 1; /*!< [7..7] Deep Software Standby */
|
|
|
+ } DPSBYCR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED67;
|
|
|
+ __IM uint16_t RESERVED68;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t DPSWCR; /*!< (@ 0x00000A04) Deep Standby Wait Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t WTSTS : 8; /*!< [7..0] Deep Software Wait Standby Time Setting Bit */
|
|
|
+ } DPSWCR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED69;
|
|
|
+ __IM uint16_t RESERVED70;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t DPSIER0; /*!< (@ 0x00000A08) Deep Standby Interrupt Enable Register 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t DIRQ0E : 1; /*!< [0..0] IRQ0-DS Pin Enable */
|
|
|
+ __IOM uint8_t DIRQ1E : 1; /*!< [1..1] IRQ1-DS Pin Enable */
|
|
|
+ __IOM uint8_t DIRQ2E : 1; /*!< [2..2] IRQ2-DS Pin Enable */
|
|
|
+ __IOM uint8_t DIRQ3E : 1; /*!< [3..3] IRQ3-DS Pin Enable */
|
|
|
+ __IOM uint8_t DIRQ4E : 1; /*!< [4..4] IRQ4-DS Pin Enable */
|
|
|
+ __IOM uint8_t DIRQ5E : 1; /*!< [5..5] IRQ5-DS Pin Enable */
|
|
|
+ __IOM uint8_t DIRQ6E : 1; /*!< [6..6] IRQ6-DS Pin Enable */
|
|
|
+ __IOM uint8_t DIRQ7E : 1; /*!< [7..7] IRQ7-DS Pin Enable */
|
|
|
+ } DPSIER0_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED71;
|
|
|
+ __IM uint16_t RESERVED72;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t DPSIER1; /*!< (@ 0x00000A0C) Deep Standby Interrupt Enable Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t DIRQ8E : 1; /*!< [0..0] IRQ8-DS Pin Enable */
|
|
|
+ __IOM uint8_t DIRQ9E : 1; /*!< [1..1] IRQ9-DS Pin Enable */
|
|
|
+ __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ10-DS Pin Enable */
|
|
|
+ __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ11-DS Pin Enable */
|
|
|
+ __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ12-DS Pin Enable */
|
|
|
+ __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ13-DS Pin Enable */
|
|
|
+ __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ14-DS Pin Enable */
|
|
|
+ __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ15-DS Pin Enable */
|
|
|
+ } DPSIER1_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED73;
|
|
|
+ __IM uint16_t RESERVED74;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t DPSIER2; /*!< (@ 0x00000A10) Deep Standby Interrupt Enable Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t DPVD1IE : 1; /*!< [0..0] PVD1 Deep Standby Cancel Signal Enable */
|
|
|
+ __IOM uint8_t DPVD2IE : 1; /*!< [1..1] PVD2 Deep Standby Cancel Signal Enable */
|
|
|
+ __IOM uint8_t DTRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable */
|
|
|
+ __IOM uint8_t DRTCAIE : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable */
|
|
|
+ __IOM uint8_t DNMIE : 1; /*!< [4..4] NMI Pin Enable */
|
|
|
+ uint8_t : 3;
|
|
|
+ } DPSIER2_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED75;
|
|
|
+ __IM uint16_t RESERVED76;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t DPSIER3; /*!< (@ 0x00000A14) Deep Standby Interrupt Enable Register 3 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable */
|
|
|
+ __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable */
|
|
|
+ __IOM uint8_t DULPT0IE : 1; /*!< [2..2] ULPT0 Overflow Deep Standby Cancel Signal Enable */
|
|
|
+ __IOM uint8_t DULPT1IE : 1; /*!< [3..3] ULPT1 Overflow Deep Standby Cancel Signal Enable */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t DIWDTIE : 1; /*!< [5..5] IWDT Overflow Deep Standby Cancel Signal Enable */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t DVBATTADIE : 1; /*!< [7..7] VBATT Tamper Detection Deep Standby Cancel Signal Enable */
|
|
|
+ } DPSIER3_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED77;
|
|
|
+ __IM uint16_t RESERVED78;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t DPSIFR0; /*!< (@ 0x00000A18) Deep Standby Interrupt Flag Register 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t DIRQ0F : 1; /*!< [0..0] IRQ0-DS Pin Deep Standby Cancel Flag */
|
|
|
+ __IOM uint8_t DIRQ1F : 1; /*!< [1..1] IRQ1-DS Pin Deep Standby Cancel Flag */
|
|
|
+ __IOM uint8_t DIRQ2F : 1; /*!< [2..2] IRQ2-DS Pin Deep Standby Cancel Flag */
|
|
|
+ __IOM uint8_t DIRQ3F : 1; /*!< [3..3] IRQ3-DS Pin Deep Standby Cancel Flag */
|
|
|
+ __IOM uint8_t DIRQ4F : 1; /*!< [4..4] IRQ4-DS Pin Deep Standby Cancel Flag */
|
|
|
+ __IOM uint8_t DIRQ5F : 1; /*!< [5..5] IRQ5-DS Pin Deep Standby Cancel Flag */
|
|
|
+ __IOM uint8_t DIRQ6F : 1; /*!< [6..6] IRQ6-DS Pin Deep Standby Cancel Flag */
|
|
|
+ __IOM uint8_t DIRQ7F : 1; /*!< [7..7] IRQ7-DS Pin Deep Standby Cancel Flag */
|
|
|
+ } DPSIFR0_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED79;
|
|
|
+ __IM uint16_t RESERVED80;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t DPSIFR1; /*!< (@ 0x00000A1C) Deep Standby Interrupt Flag Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t DIRQ8F : 1; /*!< [0..0] IRQ8-DS Pin Deep Standby Cancel Flag */
|
|
|
+ __IOM uint8_t DIRQ9F : 1; /*!< [1..1] IRQ9-DS Pin Deep Standby Cancel Flag */
|
|
|
+ __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ10-DS Pin Deep Standby Cancel Flag */
|
|
|
+ __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ11-DS Pin Deep Standby Cancel Flag */
|
|
|
+ __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ12-DS Pin Deep Standby Cancel Flag */
|
|
|
+ __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ13-DS Pin Deep Standby Cancel Flag */
|
|
|
+ __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ14-DS Pin Deep Standby Cancel Flag */
|
|
|
+ __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ15-DS Pin Deep Standby Cancel Flag */
|
|
|
+ } DPSIFR1_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED81;
|
|
|
+ __IM uint16_t RESERVED82;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t DPSIFR2; /*!< (@ 0x00000A20) Deep Standby Interrupt Flag Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t DPVD1IF : 1; /*!< [0..0] PVD1 Deep Standby Cancel Flag */
|
|
|
+ __IOM uint8_t DPVD2IF : 1; /*!< [1..1] PVD2 Deep Standby Cancel Flag */
|
|
|
+ __IOM uint8_t DTRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag */
|
|
|
+ __IOM uint8_t DRTCAIF : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag */
|
|
|
+ __IOM uint8_t DNMIF : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag */
|
|
|
+ uint8_t : 3;
|
|
|
+ } DPSIFR2_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED83;
|
|
|
+ __IM uint16_t RESERVED84;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t DPSIFR3; /*!< (@ 0x00000A24) Deep Standby Interrupt Flag Register 3 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag */
|
|
|
+ __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag */
|
|
|
+ __IOM uint8_t DULPT0IF : 1; /*!< [2..2] ULPT0 Overflow Deep Standby Cancel Flag */
|
|
|
+ __IOM uint8_t DULPT1IF : 1; /*!< [3..3] ULPT1 Overflow Deep Standby Cancel Flag */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t DIWDTIF : 1; /*!< [5..5] IWDT Overflow Deep Standby Cancel Flag */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t DVBATTADIF : 1; /*!< [7..7] VBATT Tamper Detection Deep Standby Cancel Flag */
|
|
|
+ } DPSIFR3_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED85;
|
|
|
+ __IM uint16_t RESERVED86;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t DPSIEGR0; /*!< (@ 0x00000A28) Deep Standby Interrupt Edge Register 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ0-DS Pin Edge Select */
|
|
|
+ __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ1-DS Pin Edge Select */
|
|
|
+ __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ2-DS Pin Edge Select */
|
|
|
+ __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ3-DS Pin Edge Select */
|
|
|
+ __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ4-DS Pin Edge Select */
|
|
|
+ __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ5-DS Pin Edge Select */
|
|
|
+ __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ6-DS Pin Edge Select */
|
|
|
+ __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ7-DS Pin Edge Select */
|
|
|
+ } DPSIEGR0_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED87;
|
|
|
+ __IM uint16_t RESERVED88;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t DPSIEGR1; /*!< (@ 0x00000A2C) Deep Standby Interrupt Edge Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t DIRQ8EG : 1; /*!< [0..0] IRQ8-DS Pin Edge Select */
|
|
|
+ __IOM uint8_t DIRQ9EG : 1; /*!< [1..1] IRQ9-DS Pin Edge Select */
|
|
|
+ __IOM uint8_t DIRQ10EG : 1; /*!< [2..2] IRQ10-DS Pin Edge Select */
|
|
|
+ __IOM uint8_t DIRQ11EG : 1; /*!< [3..3] IRQ11-DS Pin Edge Select */
|
|
|
+ __IOM uint8_t DIRQ12EG : 1; /*!< [4..4] IRQ12-DS Pin Edge Select */
|
|
|
+ __IOM uint8_t DIRQ13EG : 1; /*!< [5..5] IRQ13-DS Pin Edge Select */
|
|
|
+ __IOM uint8_t DIRQ14EG : 1; /*!< [6..6] IRQ14-DS Pin Edge Select */
|
|
|
+ __IOM uint8_t DIRQ15EG : 1; /*!< [7..7] IRQ15-DS Pin Edge Select */
|
|
|
+ } DPSIEGR1_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED89;
|
|
|
+ __IM uint16_t RESERVED90;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t DPSIEGR2; /*!< (@ 0x00000A30) Deep Standby Interrupt Edge Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t DPVD1EG : 1; /*!< [0..0] PVD1 Edge Select */
|
|
|
+ __IOM uint8_t DPVD2EG : 1; /*!< [1..1] PVD2 Edge Select */
|
|
|
+ uint8_t : 2;
|
|
|
+ __IOM uint8_t DNMIEG : 1; /*!< [4..4] NMI Pin Edge Select */
|
|
|
+ uint8_t : 3;
|
|
|
+ } DPSIEGR2_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED91;
|
|
|
+ __IM uint16_t RESERVED92;
|
|
|
+ __IM uint32_t RESERVED93;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SYOCDCR; /*!< (@ 0x00000A38) System Control OCD Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t DOCDF : 1; /*!< [0..0] Deep Standby OCD flag */
|
|
|
+ uint8_t : 6;
|
|
|
+ __IOM uint8_t DBGEN : 1; /*!< [7..7] Debugger Enable bit */
|
|
|
+ } SYOCDCR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED94;
|
|
|
+ __IM uint16_t RESERVED95;
|
|
|
+ __IM uint32_t RESERVED96;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t RSTSR0; /*!< (@ 0x00000A40) Reset Status Register 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t PORF : 1; /*!< [0..0] Power-On Reset Detect Flag. NOTE: Writable only to clear
|
|
|
+ * the flag. Confirm the value is 1 and then write 0. */
|
|
|
+ __IOM uint8_t LVD0RF : 1; /*!< [1..1] Voltage Monitor 0 Reset Detect Flag. NOTE: Writable only
|
|
|
+ * to clear the flag. Confirm the value is 1 and then write
|
|
|
+ * 0. */
|
|
|
+ __IOM uint8_t LVD1RF : 1; /*!< [2..2] Voltage Monitor 1 Reset Detect Flag. NOTE: Writable only
|
|
|
+ * to clear the flag. Confirm the value is 1 and then write
|
|
|
+ * 0. */
|
|
|
+ __IOM uint8_t LVD2RF : 1; /*!< [3..3] Voltage Monitor 2 Reset Detect Flag. NOTE: Writable only
|
|
|
+ * to clear the flag. Confirm the value is 1 and then write
|
|
|
+ * 0. */
|
|
|
+ __IOM uint8_t LVD3RF : 1; /*!< [4..4] Voltage Monitor 3 Reset Detect Flag. NOTE: Writable only
|
|
|
+ * to clear the flag. Confirm the value is 1 and then write
|
|
|
+ * 0. */
|
|
|
+ __IOM uint8_t LVD4RF : 1; /*!< [5..5] Voltage Monitor 4 Reset Detect Flag. NOTE: Writable only
|
|
|
+ * to clear the flag. Confirm the value is 1 and then write
|
|
|
+ * 0. */
|
|
|
+ __IOM uint8_t LVD5RF : 1; /*!< [6..6] Voltage Monitor 5 Reset Detect Flag. NOTE: Writable only
|
|
|
+ * to clear the flag. Confirm the value is 1 and then write
|
|
|
+ * 0. */
|
|
|
+ __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset Flag. NOTE: Writable only
|
|
|
+ * to clear the flag. Confirm the value is 1 and then write
|
|
|
+ * 0. */
|
|
|
+ } RSTSR0_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED97;
|
|
|
+ __IM uint16_t RESERVED98;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t RSTSR2; /*!< (@ 0x00000A44) Reset Status Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t CWSF : 1; /*!< [0..0] Cold/Warm Start Determination Flag */
|
|
|
+ uint8_t : 7;
|
|
|
+ } RSTSR2_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED99;
|
|
|
+ __IM uint16_t RESERVED100;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t RSTSR3; /*!< (@ 0x00000A48) Reset Status Register 3 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint8_t : 4;
|
|
|
+ __IOM uint8_t OCPRF : 1; /*!< [4..4] Overcurrent protection reset Detect Flag */
|
|
|
+ uint8_t : 3;
|
|
|
+ } RSTSR3_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED101;
|
|
|
+ __IM uint16_t RESERVED102;
|
|
|
+ __IM uint32_t RESERVED103;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t MOMCR; /*!< (@ 0x00000A50) Main Clock Oscillator Mode Oscillation Control
|
|
|
+ * Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t MODRV0 : 3; /*!< [3..1] Main Clock Oscillator Drive Capability 0 Switching */
|
|
|
+ uint8_t : 2;
|
|
|
+ __IOM uint8_t MOSEL : 1; /*!< [6..6] Main Clock Oscillator Switching */
|
|
|
+ uint8_t : 1;
|
|
|
+ } MOMCR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED104;
|
|
|
+ __IM uint16_t RESERVED105;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t FWEPROR; /*!< (@ 0x00000A54) Flash Write Erase Protect Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t FLWE : 2; /*!< [1..0] Flash Programing and Erasure */
|
|
|
+ uint8_t : 6;
|
|
|
+ } FWEPROR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED106;
|
|
|
+ __IM uint16_t RESERVED107;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t LVCMPCR; /*!< (@ 0x00000A58) Voltage Monitor Circuit Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint8_t : 5;
|
|
|
+ __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable */
|
|
|
+ __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable */
|
|
|
+ uint8_t : 1;
|
|
|
+ } LVCMPCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t LVD1CMPCR; /*!< (@ 0x00000A58) Voltage Monitor 1 Comparator Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Detection Voltage 1 Level Select(Standard voltage during
|
|
|
+ * drop in voltage) */
|
|
|
+ uint8_t : 2;
|
|
|
+ __IOM uint8_t LVD1E : 1; /*!< [7..7] Voltage Detection 1 Enable */
|
|
|
+ } LVD1CMPCR_b;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED108;
|
|
|
+ __IM uint16_t RESERVED109;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t LVD2CMPCR; /*!< (@ 0x00000A5C) Voltage Monitor 2 Comparator Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t LVD2LVL : 5; /*!< [4..0] Detection Voltage 2 Level Select(Standard voltage during
|
|
|
+ * drop in voltage) */
|
|
|
+ uint8_t : 2;
|
|
|
+ __IOM uint8_t LVD2E : 1; /*!< [7..7] Voltage Detection 2 Enable */
|
|
|
+ } LVD2CMPCR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED110;
|
|
|
+ __IM uint16_t RESERVED111;
|
|
|
+ __IM uint32_t RESERVED112[4];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t LVD1CR0; /*!< (@ 0x00000A70) Voltage Monitor 1 Circuit Control Register 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */
|
|
|
+ __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */
|
|
|
+ __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */
|
|
|
+ __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */
|
|
|
+ __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */
|
|
|
+ } LVD1CR0_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED113;
|
|
|
+ __IM uint16_t RESERVED114;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t LVD2CR0; /*!< (@ 0x00000A74) Voltage Monitor 2 Circuit Control Register 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */
|
|
|
+ __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */
|
|
|
+ __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */
|
|
|
+ __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */
|
|
|
+ __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */
|
|
|
+ } LVD2CR0_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED115;
|
|
|
+ __IM uint16_t RESERVED116;
|
|
|
+ __IM uint32_t RESERVED117[3];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBATTMNSELR; /*!< (@ 0x00000A84) Battery Backup Voltage Monitor Function Select
|
|
|
+ * Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Voltage Monitor Function Select Bit */
|
|
|
+ uint8_t : 7;
|
|
|
+ } VBATTMNSELR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED118;
|
|
|
+ __IM uint16_t RESERVED119;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBPCR1; /*!< (@ 0x00000A88) VBATT Battery Power Supply Control Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power Supply Switch Stop */
|
|
|
+ uint8_t : 7;
|
|
|
+ } VBTBPCR1_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED120;
|
|
|
+ __IM uint16_t RESERVED121;
|
|
|
+ __IM uint32_t RESERVED122;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t LPSCR; /*!< (@ 0x00000A90) Low Power State Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t LPMD : 4; /*!< [3..0] Low power mode setting bit */
|
|
|
+ uint8_t : 4;
|
|
|
+ } LPSCR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED123;
|
|
|
+ __IM uint16_t RESERVED124;
|
|
|
+ __IM uint32_t RESERVED125;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SSCR1; /*!< (@ 0x00000A98) Software Standby Control Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t SS1FR : 1; /*!< [0..0] Software Standby 1 Fast Return */
|
|
|
+ uint8_t : 7;
|
|
|
+ } SSCR1_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED126;
|
|
|
+ __IM uint16_t RESERVED127;
|
|
|
+ __IM uint32_t RESERVED128[5];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t LVOCR; /*!< (@ 0x00000AB0) Low Power State Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t LVO0E : 1; /*!< [0..0] Low Voltage Operation 0 Enable */
|
|
|
+ __IOM uint8_t LVO1E : 1; /*!< [1..1] Low Voltage Operation 1 Enable */
|
|
|
+ uint8_t : 6;
|
|
|
+ } LVOCR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED129;
|
|
|
+ __IM uint16_t RESERVED130;
|
|
|
+ __IM uint32_t RESERVED131[7];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SYRSTMSK0; /*!< (@ 0x00000AD0) System Reset Mask Control Register0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t IWDTMASK : 1; /*!< [0..0] Independent watchdog timer Reset Mask */
|
|
|
+ __IOM uint8_t WDT0MASK : 1; /*!< [1..1] CPU0 Watchdog timer Reset Mask */
|
|
|
+ __IOM uint8_t SWMASK : 1; /*!< [2..2] Software Reset Mask */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t CLUP0MASK : 1; /*!< [4..4] CPU0 Lockup Reset Mask */
|
|
|
+ __IOM uint8_t LM0MASK : 1; /*!< [5..5] Local memory 0 error Reset Mask */
|
|
|
+ __IOM uint8_t CMMASK : 1; /*!< [6..6] Common memory error Reset Mask */
|
|
|
+ __IOM uint8_t BUSMASK : 1; /*!< [7..7] BUS error Reset Mask */
|
|
|
+ } SYRSTMSK0_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED132;
|
|
|
+ __IM uint16_t RESERVED133;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SYRSTMSK1; /*!< (@ 0x00000AD4) System Reset Mask Control Register1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t WDT1MASK : 1; /*!< [1..1] CPU1 Watchdog timer Reset Mask */
|
|
|
+ uint8_t : 2;
|
|
|
+ __IOM uint8_t CLUP1MASK : 1; /*!< [4..4] CPU1 Lockup Reset Mask */
|
|
|
+ __IOM uint8_t LM1MASK : 1; /*!< [5..5] Local memory 1 error Reset Mask */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t NWMASK : 1; /*!< [7..7] Network Reset Mask */
|
|
|
+ } SYRSTMSK1_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED134;
|
|
|
+ __IM uint16_t RESERVED135;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SYRSTMSK2; /*!< (@ 0x00000AD8) System Reset Mask Control Register2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t LVD1MASK : 1; /*!< [0..0] Voltage Monitor 1 Reset Mask */
|
|
|
+ __IOM uint8_t LVD2MASK : 1; /*!< [1..1] Voltage Monitor 2 Reset Mask */
|
|
|
+ __IOM uint8_t LVD3MASK : 1; /*!< [2..2] Voltage Monitor 3 Reset Mask */
|
|
|
+ __IOM uint8_t LVD4MASK : 1; /*!< [3..3] Voltage Monitor 4 Reset Mask */
|
|
|
+ __IOM uint8_t LVD5MASK : 1; /*!< [4..4] Voltage Monitor 5 Reset Mask */
|
|
|
+ uint8_t : 3;
|
|
|
+ } SYRSTMSK2_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED136;
|
|
|
+ __IM uint16_t RESERVED137;
|
|
|
+ __IM uint32_t RESERVED138[10];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t PLL1LDOCR; /*!< (@ 0x00000B04) PLL1-LDO Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t LDOSTP : 1; /*!< [0..0] LDO Stop */
|
|
|
+ __IOM uint8_t SKEEP : 1; /*!< [1..1] STBY Keep */
|
|
|
+ uint8_t : 6;
|
|
|
+ } PLL1LDOCR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED139;
|
|
|
+ __IM uint16_t RESERVED140;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t PLL2LDOCR; /*!< (@ 0x00000B08) PLL2-LDO Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t LDOSTP : 1; /*!< [0..0] LDO Stop */
|
|
|
+ __IOM uint8_t SKEEP : 1; /*!< [1..1] STBY Keep */
|
|
|
+ uint8_t : 6;
|
|
|
+ } PLL2LDOCR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED141;
|
|
|
+ __IM uint16_t RESERVED142;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t HOCOLDOCR; /*!< (@ 0x00000B0C) HOCO-LDO Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t LDOSTP : 1; /*!< [0..0] LDO Stop */
|
|
|
+ __IOM uint8_t SKEEP : 1; /*!< [1..1] STBY Keep */
|
|
|
+ uint8_t : 6;
|
|
|
+ } HOCOLDOCR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED143;
|
|
|
+ __IM uint16_t RESERVED144;
|
|
|
+ __IM uint32_t RESERVED145[4];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t LVD1FCR; /*!< (@ 0x00000B20) Voltage Monitor % Function Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t RHSEL : 1; /*!< [0..0] Rise Hysteresis Select */
|
|
|
+ uint8_t : 7;
|
|
|
+ } LVD1FCR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED146;
|
|
|
+ __IM uint16_t RESERVED147;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t LVD2FCR; /*!< (@ 0x00000B24) Voltage Monitor % Function Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t RHSEL : 1; /*!< [0..0] Rise Hysteresis Select */
|
|
|
+ uint8_t : 7;
|
|
|
+ } LVD2FCR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED148;
|
|
|
+ __IM uint16_t RESERVED149;
|
|
|
+ __IM uint32_t RESERVED150[54];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SOSCCR; /*!< (@ 0x00000C00) Sub-clock oscillator control register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t SOSTP : 1; /*!< [0..0] Sub-Clock Oscillator Stop */
|
|
|
+ uint8_t : 7;
|
|
|
+ } SOSCCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t SOMCR; /*!< (@ 0x00000C01) Sub Clock Oscillator Mode Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t SODRV : 2; /*!< [1..0] Sub Clock Oscillator Drive Capability Switching */
|
|
|
+ uint8_t : 4;
|
|
|
+ __IOM uint8_t SOSEL : 1; /*!< [6..6] Sub Clock Oscillator Switching */
|
|
|
+ uint8_t : 1;
|
|
|
+ } SOMCR_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED151;
|
|
|
+ __IM uint32_t RESERVED152[15];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBER; /*!< (@ 0x00000C40) VBATT Backup Enable Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint8_t : 3;
|
|
|
+ __IOM uint8_t VBAE : 1; /*!< [3..3] VBATT backup register access enable bit */
|
|
|
+ uint8_t : 4;
|
|
|
+ } VBTBER_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED153;
|
|
|
+ __IM uint16_t RESERVED154;
|
|
|
+ __IM uint8_t RESERVED155;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBPCR2; /*!< (@ 0x00000C45) VBATT Battery Power Supply Control Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VDETLVL : 3; /*!< [2..0] VDETBAT Level Select */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t VDETE : 1; /*!< [4..4] Voltage drop detection enable */
|
|
|
+ uint8_t : 3;
|
|
|
+ } VBTBPCR2_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBPSR; /*!< (@ 0x00000C46) VBATT Battery Power Supply Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBPORF : 1; /*!< [0..0] VBATT_POR Flag */
|
|
|
+ uint8_t : 3;
|
|
|
+ __IOM uint8_t VBPORM : 1; /*!< [4..4] VBATT_POR Monitor */
|
|
|
+ __IOM uint8_t BPWSWM : 1; /*!< [5..5] Battery Power Supply Switch Status Monitor */
|
|
|
+ uint8_t : 2;
|
|
|
+ } VBTBPSR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED156;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTADSR; /*!< (@ 0x00000C48) VBATT Tamper detection Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTADF0 : 1; /*!< [0..0] VBATT Tamper Detection flag 0 */
|
|
|
+ __IOM uint8_t VBTADF1 : 1; /*!< [1..1] VBATT Tamper Detection flag 1 */
|
|
|
+ __IOM uint8_t VBTADF2 : 1; /*!< [2..2] VBATT Tamper Detection flag 2 */
|
|
|
+ uint8_t : 5;
|
|
|
+ } VBTADSR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTADCR1; /*!< (@ 0x00000C49) VBATT Tamper detection Control Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTADIE0 : 1; /*!< [0..0] VBATT Tamper Detection Interrupt Enable 0 */
|
|
|
+ __IOM uint8_t VBTADIE1 : 1; /*!< [1..1] VBATT Tamper Detection Interrupt Enable 1 */
|
|
|
+ __IOM uint8_t VBTADIE2 : 1; /*!< [2..2] VBATT Tamper Detection Interrupt Enable 2 */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t VBTADCLE0 : 1; /*!< [4..4] VBATT Tamper Detection Backup Register Clear Enable 0 */
|
|
|
+ __IOM uint8_t VBTADCLE1 : 1; /*!< [5..5] VBATT Tamper Detection Backup Register Clear Enable 1 */
|
|
|
+ __IOM uint8_t VBTADCLE2 : 1; /*!< [6..6] VBATT Tamper Detection Backup Register Clear Enable 2 */
|
|
|
+ uint8_t : 1;
|
|
|
+ } VBTADCR1_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTADCR2; /*!< (@ 0x00000C4A) VBATT Tamper detection Control Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBRTCES0 : 1; /*!< [0..0] VBATT RTC Time Capture Event Source Select 0 */
|
|
|
+ __IOM uint8_t VBRTCES1 : 1; /*!< [1..1] VBATT RTC Time Capture Event Source Select 1 */
|
|
|
+ __IOM uint8_t VBRTCES2 : 1; /*!< [2..2] VBATT RTC Time Capture Event Source Select 2 */
|
|
|
+ uint8_t : 5;
|
|
|
+ } VBTADCR2_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED157;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTICTLR; /*!< (@ 0x00000C4C) VBATT Input Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable */
|
|
|
+ __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable */
|
|
|
+ __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable */
|
|
|
+ uint8_t : 5;
|
|
|
+ } VBTICTLR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTICTLR2; /*!< (@ 0x00000C4D) VBATT Input Control Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VCH0NCE : 1; /*!< [0..0] VBATT CH0 Input Noise Canceler Enable */
|
|
|
+ __IOM uint8_t VCH1NCE : 1; /*!< [1..1] VBATT CH1 Input Noise Canceler Enable */
|
|
|
+ __IOM uint8_t VCH2NCE : 1; /*!< [2..2] VBATT CH2 Input Noise Canceler Enable */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t VCH0EG : 1; /*!< [4..4] VBATT CH0 Input Edge Select */
|
|
|
+ __IOM uint8_t VCH1EG : 1; /*!< [5..5] VBATT CH1 Input Edge Select */
|
|
|
+ __IOM uint8_t VCH2EG : 1; /*!< [6..6] VBATT CH2 Input Edge Select */
|
|
|
+ uint8_t : 1;
|
|
|
+ } VBTICTLR2_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTIMONR; /*!< (@ 0x00000C4E) VBATT Input Monitor Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VCH0MON : 1; /*!< [0..0] VBATT CH0 Input monitor */
|
|
|
+ __IOM uint8_t VCH1MON : 1; /*!< [1..1] VBATT CH1 Input monitor */
|
|
|
+ __IOM uint8_t VCH2MON : 1; /*!< [2..2] VBATT CH2 Input monitor */
|
|
|
+ uint8_t : 5;
|
|
|
+ } VBTIMONR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED158;
|
|
|
+ __IM uint32_t RESERVED159[44];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR0; /*!< (@ 0x00000D00) VBATT Backup Register 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR0_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR1; /*!< (@ 0x00000D01) VBATT Backup Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR1_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR2; /*!< (@ 0x00000D02) VBATT Backup Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR2_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR3; /*!< (@ 0x00000D03) VBATT Backup Register 3 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR3_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR4; /*!< (@ 0x00000D04) VBATT Backup Register 4 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR4_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR5; /*!< (@ 0x00000D05) VBATT Backup Register 5 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR5_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR6; /*!< (@ 0x00000D06) VBATT Backup Register 6 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR6_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR7; /*!< (@ 0x00000D07) VBATT Backup Register 7 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR7_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR8; /*!< (@ 0x00000D08) VBATT Backup Register 8 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR8_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR9; /*!< (@ 0x00000D09) VBATT Backup Register 9 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR9_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR10; /*!< (@ 0x00000D0A) VBATT Backup Register 10 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR10_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR11; /*!< (@ 0x00000D0B) VBATT Backup Register 11 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR11_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR12; /*!< (@ 0x00000D0C) VBATT Backup Register 12 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR12_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR13; /*!< (@ 0x00000D0D) VBATT Backup Register 13 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR13_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR14; /*!< (@ 0x00000D0E) VBATT Backup Register 14 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR14_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR15; /*!< (@ 0x00000D0F) VBATT Backup Register 15 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR15_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR16; /*!< (@ 0x00000D10) VBATT Backup Register 16 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR16_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR17; /*!< (@ 0x00000D11) VBATT Backup Register 17 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR17_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR18; /*!< (@ 0x00000D12) VBATT Backup Register 18 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR18_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR19; /*!< (@ 0x00000D13) VBATT Backup Register 19 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR19_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR20; /*!< (@ 0x00000D14) VBATT Backup Register 20 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR20_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR21; /*!< (@ 0x00000D15) VBATT Backup Register 21 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR21_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR22; /*!< (@ 0x00000D16) VBATT Backup Register 22 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR22_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR23; /*!< (@ 0x00000D17) VBATT Backup Register 23 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR23_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR24; /*!< (@ 0x00000D18) VBATT Backup Register 24 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR24_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR25; /*!< (@ 0x00000D19) VBATT Backup Register 25 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR25_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR26; /*!< (@ 0x00000D1A) VBATT Backup Register 26 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR26_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR27; /*!< (@ 0x00000D1B) VBATT Backup Register 27 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR27_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR28; /*!< (@ 0x00000D1C) VBATT Backup Register 28 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR28_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR29; /*!< (@ 0x00000D1D) VBATT Backup Register 29 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR29_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR30; /*!< (@ 0x00000D1E) VBATT Backup Register 30 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR30_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR31; /*!< (@ 0x00000D1F) VBATT Backup Register 31 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR31_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR32; /*!< (@ 0x00000D20) VBATT Backup Register 32 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR32_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR33; /*!< (@ 0x00000D21) VBATT Backup Register 33 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR33_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR34; /*!< (@ 0x00000D22) VBATT Backup Register 34 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR34_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR35; /*!< (@ 0x00000D23) VBATT Backup Register 35 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR35_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR36; /*!< (@ 0x00000D24) VBATT Backup Register 36 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR36_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR37; /*!< (@ 0x00000D25) VBATT Backup Register 37 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR37_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR38; /*!< (@ 0x00000D26) VBATT Backup Register 38 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR38_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR39; /*!< (@ 0x00000D27) VBATT Backup Register 39 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR39_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR40; /*!< (@ 0x00000D28) VBATT Backup Register 40 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR40_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR41; /*!< (@ 0x00000D29) VBATT Backup Register 41 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR41_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR42; /*!< (@ 0x00000D2A) VBATT Backup Register 42 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR42_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR43; /*!< (@ 0x00000D2B) VBATT Backup Register 43 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR43_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR44; /*!< (@ 0x00000D2C) VBATT Backup Register 44 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR44_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR45; /*!< (@ 0x00000D2D) VBATT Backup Register 45 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR45_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR46; /*!< (@ 0x00000D2E) VBATT Backup Register 46 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR46_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR47; /*!< (@ 0x00000D2F) VBATT Backup Register 47 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR47_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR48; /*!< (@ 0x00000D30) VBATT Backup Register 48 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR48_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR49; /*!< (@ 0x00000D31) VBATT Backup Register 49 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR49_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR50; /*!< (@ 0x00000D32) VBATT Backup Register 50 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR50_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR51; /*!< (@ 0x00000D33) VBATT Backup Register 51 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR51_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR52; /*!< (@ 0x00000D34) VBATT Backup Register 52 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR52_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR53; /*!< (@ 0x00000D35) VBATT Backup Register 53 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR53_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR54; /*!< (@ 0x00000D36) VBATT Backup Register 54 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR54_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR55; /*!< (@ 0x00000D37) VBATT Backup Register 55 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR55_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR56; /*!< (@ 0x00000D38) VBATT Backup Register 56 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR56_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR57; /*!< (@ 0x00000D39) VBATT Backup Register 57 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR57_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR58; /*!< (@ 0x00000D3A) VBATT Backup Register 58 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR58_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR59; /*!< (@ 0x00000D3B) VBATT Backup Register 59 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR59_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR60; /*!< (@ 0x00000D3C) VBATT Backup Register 60 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR60_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR61; /*!< (@ 0x00000D3D) VBATT Backup Register 61 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR61_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR62; /*!< (@ 0x00000D3E) VBATT Backup Register 62 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR62_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR63; /*!< (@ 0x00000D3F) VBATT Backup Register 63 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR63_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR64; /*!< (@ 0x00000D40) VBATT Backup Register 64 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR64_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR65; /*!< (@ 0x00000D41) VBATT Backup Register 65 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR65_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR66; /*!< (@ 0x00000D42) VBATT Backup Register 66 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR66_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR67; /*!< (@ 0x00000D43) VBATT Backup Register 67 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR67_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR68; /*!< (@ 0x00000D44) VBATT Backup Register 68 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR68_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR69; /*!< (@ 0x00000D45) VBATT Backup Register 69 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR69_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR70; /*!< (@ 0x00000D46) VBATT Backup Register 70 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR70_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR71; /*!< (@ 0x00000D47) VBATT Backup Register 71 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR71_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR72; /*!< (@ 0x00000D48) VBATT Backup Register 72 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR72_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR73; /*!< (@ 0x00000D49) VBATT Backup Register 73 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR73_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR74; /*!< (@ 0x00000D4A) VBATT Backup Register 74 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR74_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR75; /*!< (@ 0x00000D4B) VBATT Backup Register 75 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR75_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR76; /*!< (@ 0x00000D4C) VBATT Backup Register 76 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR76_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR77; /*!< (@ 0x00000D4D) VBATT Backup Register 77 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR77_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR78; /*!< (@ 0x00000D4E) VBATT Backup Register 78 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR78_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR79; /*!< (@ 0x00000D4F) VBATT Backup Register 79 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR79_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR80; /*!< (@ 0x00000D50) VBATT Backup Register 80 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR80_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR81; /*!< (@ 0x00000D51) VBATT Backup Register 81 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR81_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR82; /*!< (@ 0x00000D52) VBATT Backup Register 82 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR82_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR83; /*!< (@ 0x00000D53) VBATT Backup Register 83 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR83_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR84; /*!< (@ 0x00000D54) VBATT Backup Register 84 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR84_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR85; /*!< (@ 0x00000D55) VBATT Backup Register 85 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR85_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR86; /*!< (@ 0x00000D56) VBATT Backup Register 86 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR86_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR87; /*!< (@ 0x00000D57) VBATT Backup Register 87 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR87_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR88; /*!< (@ 0x00000D58) VBATT Backup Register 88 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR88_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR89; /*!< (@ 0x00000D59) VBATT Backup Register 89 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR89_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR90; /*!< (@ 0x00000D5A) VBATT Backup Register 90 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR90_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR91; /*!< (@ 0x00000D5B) VBATT Backup Register 91 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR91_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR92; /*!< (@ 0x00000D5C) VBATT Backup Register 92 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR92_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR93; /*!< (@ 0x00000D5D) VBATT Backup Register 93 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR93_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR94; /*!< (@ 0x00000D5E) VBATT Backup Register 94 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR94_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR95; /*!< (@ 0x00000D5F) VBATT Backup Register 95 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR95_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR96; /*!< (@ 0x00000D60) VBATT Backup Register 96 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR96_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR97; /*!< (@ 0x00000D61) VBATT Backup Register 97 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR97_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR98; /*!< (@ 0x00000D62) VBATT Backup Register 98 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR98_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR99; /*!< (@ 0x00000D63) VBATT Backup Register 99 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR99_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR100; /*!< (@ 0x00000D64) VBATT Backup Register 100 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR100_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR101; /*!< (@ 0x00000D65) VBATT Backup Register 101 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR101_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR102; /*!< (@ 0x00000D66) VBATT Backup Register 102 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR102_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR103; /*!< (@ 0x00000D67) VBATT Backup Register 103 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR103_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR104; /*!< (@ 0x00000D68) VBATT Backup Register 104 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR104_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR105; /*!< (@ 0x00000D69) VBATT Backup Register 105 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR105_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR106; /*!< (@ 0x00000D6A) VBATT Backup Register 106 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR106_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR107; /*!< (@ 0x00000D6B) VBATT Backup Register 107 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR107_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR108; /*!< (@ 0x00000D6C) VBATT Backup Register 108 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR108_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR109; /*!< (@ 0x00000D6D) VBATT Backup Register 109 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR109_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR110; /*!< (@ 0x00000D6E) VBATT Backup Register 110 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR110_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR111; /*!< (@ 0x00000D6F) VBATT Backup Register 111 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR111_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR112; /*!< (@ 0x00000D70) VBATT Backup Register 112 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR112_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR113; /*!< (@ 0x00000D71) VBATT Backup Register 113 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR113_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR114; /*!< (@ 0x00000D72) VBATT Backup Register 114 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR114_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR115; /*!< (@ 0x00000D73) VBATT Backup Register 115 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR115_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR116; /*!< (@ 0x00000D74) VBATT Backup Register 116 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR116_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR117; /*!< (@ 0x00000D75) VBATT Backup Register 117 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR117_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR118; /*!< (@ 0x00000D76) VBATT Backup Register 118 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR118_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR119; /*!< (@ 0x00000D77) VBATT Backup Register 119 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR119_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR120; /*!< (@ 0x00000D78) VBATT Backup Register 120 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR120_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR121; /*!< (@ 0x00000D79) VBATT Backup Register 121 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR121_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR122; /*!< (@ 0x00000D7A) VBATT Backup Register 122 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR122_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR123; /*!< (@ 0x00000D7B) VBATT Backup Register 123 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR123_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR124; /*!< (@ 0x00000D7C) VBATT Backup Register 124 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR124_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR125; /*!< (@ 0x00000D7D) VBATT Backup Register 125 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR125_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR126; /*!< (@ 0x00000D7E) VBATT Backup Register 126 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR126_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR127; /*!< (@ 0x00000D7F) VBATT Backup Register 127 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKRn [7:0] (n=0 to 127) */
|
|
|
+ } VBTBKR127_b;
|
|
|
+ };
|
|
|
+} R_SYSTEM_Type; /*!< Size = 3456 (0xd80) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_TSN_CAL ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Temperature Sensor (R_TSN_CAL)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x4011B17C) R_TSN_CAL Structure */
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t TSCDR; /*!< (@ 0x00000000) Temperature Sensor 32 bit Calibration Data Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t TSCDR : 32; /*!< [31..0] The 32 bit TSCDR register stores temperature sensor
|
|
|
+ * calibration converted value. */
|
|
|
+ } TSCDR_b;
|
|
|
+ };
|
|
|
+} R_TSN_CAL_Type; /*!< Size = 4 (0x4) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_TSN_CTRL ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Temperature Sensor (R_TSN_CTRL)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x40235000) R_TSN_CTRL Structure */
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t TSCR; /*!< (@ 0x00000000) Temperature Sensor Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint8_t : 4;
|
|
|
+ __IOM uint8_t TSOE : 1; /*!< [4..4] Temperature Sensor Enable */
|
|
|
+ uint8_t : 2;
|
|
|
+ __IOM uint8_t TSEN : 1; /*!< [7..7] Temperature Sensor Output Enable */
|
|
|
+ } TSCR_b;
|
|
|
+ };
|
|
|
+} R_TSN_CTRL_Type; /*!< Size = 1 (0x1) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_USB_FS0 ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief USB 2.0 Module (R_USB_FS0)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x40250000) R_USB_FS0 Structure */
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IOM uint16_t DMRPU : 1; /*!< [3..3] D- Line Resistor Control */
|
|
|
+ __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */
|
|
|
+ __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */
|
|
|
+ __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t CNEN : 1; /*!< [8..8] CNEN Single End Receiver Enable */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t SCKE : 1; /*!< [10..10] USB Clock Enable */
|
|
|
+ uint16_t : 5;
|
|
|
+ } SYSCFG_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2
|
|
|
+ * access cycles) */
|
|
|
+ uint16_t : 12;
|
|
|
+ } BUSWAIT_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */
|
|
|
+ __IM uint16_t IDMON : 1; /*!< [2..2] External ID0 Input Pin Monitor */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is
|
|
|
+ * Selected. */
|
|
|
+ __IM uint16_t HTACT : 1; /*!< [6..6] USB Host Sequencer Status Monitor */
|
|
|
+ uint16_t : 7;
|
|
|
+ __IM uint16_t OVCMON : 2; /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe
|
|
|
+ * OCVMON[1] bit indicates the status of the USBHS_OVRCURA
|
|
|
+ * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB
|
|
|
+ * pin. */
|
|
|
+ } SYSSTS0_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */
|
|
|
+ uint16_t : 15;
|
|
|
+ } PLLSTA_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Enable */
|
|
|
+ __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Output */
|
|
|
+ __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output */
|
|
|
+ __IOM uint16_t RWUPE : 1; /*!< [7..7] Wakeup Detection Enable */
|
|
|
+ __IOM uint16_t WKUP : 1; /*!< [8..8] Wakeup Output */
|
|
|
+ __IOM uint16_t VBUSEN : 1; /*!< [9..9] USB_VBUSEN Output Pin Control */
|
|
|
+ __IOM uint16_t EXICEN : 1; /*!< [10..10] USB_EXICEN Output Pin Control */
|
|
|
+ __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is
|
|
|
+ * used when switching from device B to device A while in
|
|
|
+ * OTG mode. If the HNPBTOA bit is 1, the internal function
|
|
|
+ * control keeps the suspended state until the HNP processing
|
|
|
+ * ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is
|
|
|
+ * set. */
|
|
|
+ uint16_t : 4;
|
|
|
+ } DVSTCTR0_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */
|
|
|
+ uint16_t : 12;
|
|
|
+ } TESTMODE_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED1;
|
|
|
+ __IM uint32_t RESERVED2;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */
|
|
|
+ __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint8_t RESERVED3;
|
|
|
+ __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */
|
|
|
+ __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint8_t RESERVED4;
|
|
|
+ __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */
|
|
|
+ __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint8_t RESERVED5;
|
|
|
+ __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t ISEL : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IOM uint16_t BIGEND : 1; /*!< [8..8] CFIFO Port Endian Control */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */
|
|
|
+ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */
|
|
|
+ } CFIFOSEL_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive
|
|
|
+ * data. */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */
|
|
|
+ __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */
|
|
|
+ __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */
|
|
|
+ } CFIFOCTR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED6;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */
|
|
|
+ uint16_t : 4;
|
|
|
+ __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */
|
|
|
+ __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */
|
|
|
+ __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified
|
|
|
+ * Pipe Data is Read */
|
|
|
+ __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */
|
|
|
+ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */
|
|
|
+ } D0FIFOSEL_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive
|
|
|
+ * data. */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */
|
|
|
+ __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */
|
|
|
+ __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */
|
|
|
+ } D0FIFOCTR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */
|
|
|
+ uint16_t : 4;
|
|
|
+ __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */
|
|
|
+ __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */
|
|
|
+ __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified
|
|
|
+ * Pipe Data is Read */
|
|
|
+ __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */
|
|
|
+ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */
|
|
|
+ } D1FIFOSEL_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive
|
|
|
+ * data. */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */
|
|
|
+ __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */
|
|
|
+ __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */
|
|
|
+ } D1FIFOCTR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint16_t : 8;
|
|
|
+ __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */
|
|
|
+ __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */
|
|
|
+ __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */
|
|
|
+ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */
|
|
|
+ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */
|
|
|
+ __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */
|
|
|
+ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */
|
|
|
+ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */
|
|
|
+ } INTENB0_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */
|
|
|
+ uint16_t : 3;
|
|
|
+ __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */
|
|
|
+ __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */
|
|
|
+ __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */
|
|
|
+ uint16_t : 4;
|
|
|
+ __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */
|
|
|
+ __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */
|
|
|
+ __IOM uint16_t OVRCRE : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable */
|
|
|
+ } INTENB1_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED7;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE */
|
|
|
+ __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE */
|
|
|
+ __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE */
|
|
|
+ __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE */
|
|
|
+ __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE */
|
|
|
+ __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE */
|
|
|
+ __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE */
|
|
|
+ __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE */
|
|
|
+ __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE */
|
|
|
+ __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE */
|
|
|
+ uint16_t : 6;
|
|
|
+ } BRDYENB_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE */
|
|
|
+ __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE */
|
|
|
+ __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE */
|
|
|
+ __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE */
|
|
|
+ __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE */
|
|
|
+ __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE */
|
|
|
+ __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE */
|
|
|
+ __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE */
|
|
|
+ __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE */
|
|
|
+ __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE */
|
|
|
+ uint16_t : 6;
|
|
|
+ } NRDYENB_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE */
|
|
|
+ __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE */
|
|
|
+ __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE */
|
|
|
+ __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE */
|
|
|
+ __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE */
|
|
|
+ __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE */
|
|
|
+ __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE */
|
|
|
+ __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE */
|
|
|
+ __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE */
|
|
|
+ __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE */
|
|
|
+ uint16_t : 6;
|
|
|
+ } BEMPENB_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Output Configuration Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint16_t : 4;
|
|
|
+ __IM uint16_t EDGESTS : 1; /*!< [4..4] Edge Interrupt Output Status Monitor */
|
|
|
+ __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */
|
|
|
+ __IOM uint16_t BRDYM : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select */
|
|
|
+ uint16_t : 7;
|
|
|
+ } SOFCFG_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */
|
|
|
+ __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */
|
|
|
+ __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */
|
|
|
+ uint16_t : 3;
|
|
|
+ __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */
|
|
|
+ } PHYSET_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */
|
|
|
+ __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */
|
|
|
+ __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */
|
|
|
+ __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */
|
|
|
+ __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */
|
|
|
+ __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */
|
|
|
+ __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */
|
|
|
+ __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */
|
|
|
+ __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */
|
|
|
+ __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */
|
|
|
+ __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */
|
|
|
+ __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */
|
|
|
+ } INTSTS0_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status */
|
|
|
+ uint16_t : 3;
|
|
|
+ __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */
|
|
|
+ __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */
|
|
|
+ __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */
|
|
|
+ __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t ATTCH : 1; /*!< [11..11] ATTCH Interrupt Status */
|
|
|
+ __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */
|
|
|
+ __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status */
|
|
|
+ } INTSTS1_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED8;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE */
|
|
|
+ __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE */
|
|
|
+ __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE */
|
|
|
+ __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE */
|
|
|
+ __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE */
|
|
|
+ __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE */
|
|
|
+ __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE */
|
|
|
+ __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE */
|
|
|
+ __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE */
|
|
|
+ __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE */
|
|
|
+ uint16_t : 6;
|
|
|
+ } BRDYSTS_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE */
|
|
|
+ __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE */
|
|
|
+ __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE */
|
|
|
+ __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE */
|
|
|
+ __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE */
|
|
|
+ __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE */
|
|
|
+ __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE */
|
|
|
+ __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE */
|
|
|
+ __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE */
|
|
|
+ __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE */
|
|
|
+ uint16_t : 6;
|
|
|
+ } NRDYSTS_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE */
|
|
|
+ __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE */
|
|
|
+ __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE */
|
|
|
+ __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE */
|
|
|
+ __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE */
|
|
|
+ __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE */
|
|
|
+ __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE */
|
|
|
+ __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE */
|
|
|
+ __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE */
|
|
|
+ __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE */
|
|
|
+ uint16_t : 6;
|
|
|
+ } BEMPSTS_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t FRNM : 11; /*!< [10..0] Frame NumberLatest frame number */
|
|
|
+ uint16_t : 3;
|
|
|
+ __IOM uint16_t CRCE : 1; /*!< [14..14] Receive Data Error */
|
|
|
+ __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */
|
|
|
+ } FRMNUM_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */
|
|
|
+ uint16_t : 12;
|
|
|
+ __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */
|
|
|
+ } UFRMNUM_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t USBADDR : 7; /*!< [6..0] USB Address In device controller mode, these flags indicate
|
|
|
+ * the USB address assigned by the host when the USBHS processed
|
|
|
+ * the SET_ADDRESS request successfully. */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */
|
|
|
+ uint16_t : 5;
|
|
|
+ } USBADDR_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED9;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType
|
|
|
+ * value. */
|
|
|
+ __IOM uint16_t BREQUEST : 8; /*!< [15..8] RequestThese bits store the USB request bRequest value. */
|
|
|
+ } USBREQ_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value. */
|
|
|
+ } USBVAL_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value. */
|
|
|
+ } USBINDX_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value. */
|
|
|
+ } USBLENG_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint16_t : 4;
|
|
|
+ __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */
|
|
|
+ __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */
|
|
|
+ uint16_t : 7;
|
|
|
+ } DCPCFG_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount
|
|
|
+ * of data (maximum packet size) in payloads for the DCP. */
|
|
|
+ uint16_t : 5;
|
|
|
+ __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */
|
|
|
+ } DCPMAXP_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t PID : 2; /*!< [1..0] Response PID */
|
|
|
+ __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */
|
|
|
+ __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */
|
|
|
+ __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */
|
|
|
+ __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IOM uint16_t SUREQ : 1; /*!< [14..14] Setup Token Transmission */
|
|
|
+ __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */
|
|
|
+ } DCPCTR_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED10;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select */
|
|
|
+ uint16_t : 12;
|
|
|
+ } PIPESEL_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED11;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint NumberThese bits specify the endpoint number
|
|
|
+ * for the selected pipe.Setting 0000b means unused pipe. */
|
|
|
+ __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */
|
|
|
+ __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */
|
|
|
+ uint16_t : 3;
|
|
|
+ __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */
|
|
|
+ } PIPECFG_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED12;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t MXPS : 9; /*!< [8..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to
|
|
|
+ * 256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes
|
|
|
+ * (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and
|
|
|
+ * [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to
|
|
|
+ * 64 bytes (040h) (Bits [8:7] are not provided.) */
|
|
|
+ uint16_t : 3;
|
|
|
+ __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */
|
|
|
+ } PIPEMAXP_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalSpecifies the interval
|
|
|
+ * error detection timing for the selected pipe in terms of
|
|
|
+ * frames, which is expressed as nth power of 2. */
|
|
|
+ uint16_t : 9;
|
|
|
+ __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */
|
|
|
+ uint16_t : 3;
|
|
|
+ } PIPEPERI_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) Pipe [0..8] Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t PID : 2; /*!< [1..0] Response PID */
|
|
|
+ uint16_t : 3;
|
|
|
+ __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */
|
|
|
+ __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Confirmation */
|
|
|
+ __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */
|
|
|
+ __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */
|
|
|
+ __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear Mode */
|
|
|
+ __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of
|
|
|
+ * Split Transaction of the relevant pipe */
|
|
|
+ __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing
|
|
|
+ * the CSSTS bit of the relevant pipe */
|
|
|
+ __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer Monitor */
|
|
|
+ __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */
|
|
|
+ } PIPE_CTR_b[9];
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED13;
|
|
|
+ __IM uint32_t RESERVED14[3];
|
|
|
+ __IOM R_USB_FS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */
|
|
|
+ __IM uint32_t RESERVED15[3];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t USBBCCTRL0; /*!< (@ 0x000000B0) BC Control Register 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t RPDME0 : 1; /*!< [0..0] D- Pin Pull-Down Control */
|
|
|
+ __IOM uint16_t IDPSRCE0 : 1; /*!< [1..1] D+ Pin IDPSRC Output Control */
|
|
|
+ __IOM uint16_t IDMSINKE0 : 1; /*!< [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */
|
|
|
+ __IOM uint16_t VDPSRCE0 : 1; /*!< [3..3] D+ Pin VDPSRC (0.6 V) Output Control */
|
|
|
+ __IOM uint16_t IDPSINKE0 : 1; /*!< [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */
|
|
|
+ __IOM uint16_t VDMSRCE0 : 1; /*!< [5..5] D- Pin VDMSRC (0.6 V) Output Control */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t BATCHGE0 : 1; /*!< [7..7] BC (Battery Charger) Function Ch0 General Enable Control */
|
|
|
+ __IM uint16_t CHGDETSTS0 : 1; /*!< [8..8] D- Pin 0.6 V Input Detection Status */
|
|
|
+ __IM uint16_t PDDETSTS0 : 1; /*!< [9..9] D+ Pin 0.6 V Input Detection Status */
|
|
|
+ uint16_t : 6;
|
|
|
+ } USBBCCTRL0_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED16;
|
|
|
+ __IM uint32_t RESERVED17[4];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t UCKSEL; /*!< (@ 0x000000C4) USB Clock Selection Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t UCKSELC : 1; /*!< [0..0] USB Clock Selection */
|
|
|
+ uint16_t : 15;
|
|
|
+ } UCKSEL_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED18;
|
|
|
+ __IM uint32_t RESERVED19;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t USBMC; /*!< (@ 0x000000CC) USB Module Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t VDDUSBE : 1; /*!< [0..0] USB Reference Power Supply Circuit On/Off Control */
|
|
|
+ uint16_t : 6;
|
|
|
+ __IOM uint16_t VDCEN : 1; /*!< [7..7] USB Regulator On/Off Control */
|
|
|
+ uint16_t : 8;
|
|
|
+ } USBMC_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED20;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint16_t : 6;
|
|
|
+ __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */
|
|
|
+ __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */
|
|
|
+ __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */
|
|
|
+ uint16_t : 1;
|
|
|
+ } DEVADD_b[10];
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED21[3];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t PHYSLEW; /*!< (@ 0x000000F0) PHY Cross Point Adjustment Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t SLEWR00 : 1; /*!< [0..0] Receiver Cross Point Adjustment 00 */
|
|
|
+ __IOM uint32_t SLEWR01 : 1; /*!< [1..1] Receiver Cross Point Adjustment 01 */
|
|
|
+ __IOM uint32_t SLEWF00 : 1; /*!< [2..2] Receiver Cross Point Adjustment 00 */
|
|
|
+ __IOM uint32_t SLEWF01 : 1; /*!< [3..3] Receiver Cross Point Adjustment 01 */
|
|
|
+ uint32_t : 28;
|
|
|
+ } PHYSLEW_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED22[3];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint16_t : 7;
|
|
|
+ __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */
|
|
|
+ uint16_t : 8;
|
|
|
+ } LPCTRL_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint16_t : 14;
|
|
|
+ __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */
|
|
|
+ uint16_t : 1;
|
|
|
+ } LPSTS_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED23[15];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */
|
|
|
+ __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */
|
|
|
+ __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */
|
|
|
+ __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */
|
|
|
+ __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */
|
|
|
+ __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */
|
|
|
+ __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */
|
|
|
+ uint16_t : 6;
|
|
|
+ } BCCTRL_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED24;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */
|
|
|
+ __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */
|
|
|
+ __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid
|
|
|
+ * only when the L1RESPMD[1:0] value is 2'b11. */
|
|
|
+ __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates
|
|
|
+ * the L1 state together with the device state bits DVSQ[2:0]. */
|
|
|
+ __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold
|
|
|
+ * value used for L1NEGOMD.The format is the same as the HIRD
|
|
|
+ * field in HL1CTRL. */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */
|
|
|
+ uint16_t : 1;
|
|
|
+ } PL1CTRL1_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint16_t : 8;
|
|
|
+ __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */
|
|
|
+ __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */
|
|
|
+ uint16_t : 3;
|
|
|
+ } PL1CTRL2_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */
|
|
|
+ __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */
|
|
|
+ uint16_t : 13;
|
|
|
+ } HL1CTRL1_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to
|
|
|
+ * be set in the ADDR field of LPM token. */
|
|
|
+ uint16_t : 4;
|
|
|
+ __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */
|
|
|
+ __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the
|
|
|
+ * value to be set in the RWE field of LPM token. */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive
|
|
|
+ * period at the time of L1 Resume. */
|
|
|
+ } HL1CTRL2_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED25[5];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor
|
|
|
+ * Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 20;
|
|
|
+ __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the
|
|
|
+ * HS side of USB port. */
|
|
|
+ __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the
|
|
|
+ * HS side of USB port. */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side
|
|
|
+ * of USB port. */
|
|
|
+ uint32_t : 8;
|
|
|
+ } DPUSR0R_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */
|
|
|
+ __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */
|
|
|
+ uint32_t : 12;
|
|
|
+ __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */
|
|
|
+ __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */
|
|
|
+ uint32_t : 8;
|
|
|
+ } DPUSR1R_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */
|
|
|
+ __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB
|
|
|
+ * port. */
|
|
|
+ __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB
|
|
|
+ * port. */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */
|
|
|
+ __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */
|
|
|
+ uint16_t : 6;
|
|
|
+ } DPUSR2R_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */
|
|
|
+ __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */
|
|
|
+ uint16_t : 14;
|
|
|
+ } DPUSRCR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED26[165];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t DPUSR0R_FS; /*!< (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin
|
|
|
+ * Monitor Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t SRPC0 : 1; /*!< [0..0] USB Single End Receiver Control */
|
|
|
+ __IOM uint32_t RPUE0 : 1; /*!< [1..1] DP Pull-Up Resistor Control */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t DRPD0 : 1; /*!< [3..3] D+/D- Pull-Down Resistor Control */
|
|
|
+ __IOM uint32_t FIXPHY0 : 1; /*!< [4..4] USB Transceiver Output Fix */
|
|
|
+ uint32_t : 11;
|
|
|
+ __IM uint32_t DP0 : 1; /*!< [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */
|
|
|
+ __IM uint32_t DM0 : 1; /*!< [17..17] USB D-InputIndicates the D- input signal of the USB. */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IM uint32_t DOVCA0 : 1; /*!< [20..20] USB OVRCURA InputIndicates the OVRCURA input signal
|
|
|
+ * of the USB. */
|
|
|
+ __IM uint32_t DOVCB0 : 1; /*!< [21..21] USB OVRCURB InputIndicates the OVRCURB input signal
|
|
|
+ * of the USB. */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IM uint32_t DVBSTS0 : 1; /*!< [23..23] USB VBUS InputIndicates the VBUS input signal of the
|
|
|
+ * USB. */
|
|
|
+ uint32_t : 8;
|
|
|
+ } DPUSR0R_FS_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t DPUSR1R_FS; /*!< (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt
|
|
|
+ * Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t DPINTE0 : 1; /*!< [0..0] USB DP Interrupt Enable/Clear */
|
|
|
+ __IOM uint32_t DMINTE0 : 1; /*!< [1..1] USB DM Interrupt Enable/Clear */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t DOVRCRAE0 : 1; /*!< [4..4] USB OVRCURA Interrupt Enable/Clear */
|
|
|
+ __IOM uint32_t DOVRCRBE0 : 1; /*!< [5..5] USB OVRCURB Interrupt Enable/Clear */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t DVBSE0 : 1; /*!< [7..7] USB VBUS Interrupt Enable/Clear */
|
|
|
+ uint32_t : 8;
|
|
|
+ __IM uint32_t DPINT0 : 1; /*!< [16..16] USB DP Interrupt Source Recovery */
|
|
|
+ __IM uint32_t DMINT0 : 1; /*!< [17..17] USB DM Interrupt Source Recovery */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IM uint32_t DOVRCRA0 : 1; /*!< [20..20] USB OVRCURA Interrupt Source Recovery */
|
|
|
+ __IM uint32_t DOVRCRB0 : 1; /*!< [21..21] USB OVRCURB Interrupt Source Recovery */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IM uint32_t DVBINT0 : 1; /*!< [23..23] USB VBUS Interrupt Source Recovery */
|
|
|
+ uint32_t : 8;
|
|
|
+ } DPUSR1R_FS_b;
|
|
|
+ };
|
|
|
+} R_USB_FS0_Type; /*!< Size = 1032 (0x408) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_WDT ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Watchdog Timer (R_WDT)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x40202600) R_WDT Structure */
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t WDTRR; /*!< (@ 0x00000000) WDT Refresh Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t WDTRR : 8; /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter
|
|
|
+ * of the WDT. */
|
|
|
+ } WDTRR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t WDTCR; /*!< (@ 0x00000002) WDT Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */
|
|
|
+ __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */
|
|
|
+ uint16_t : 2;
|
|
|
+ } WDTCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t WDTSR; /*!< (@ 0x00000004) WDT Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */
|
|
|
+ __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */
|
|
|
+ __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */
|
|
|
+ } WDTSR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t WDTRCR; /*!< (@ 0x00000006) WDT Reset Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint8_t : 7;
|
|
|
+ __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */
|
|
|
+ } WDTRCR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED1;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t WDTCSTPR; /*!< (@ 0x00000008) WDT Count Stop Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint8_t : 7;
|
|
|
+ __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */
|
|
|
+ } WDTCSTPR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED2;
|
|
|
+ __IM uint16_t RESERVED3;
|
|
|
+} R_WDT_Type; /*!< Size = 12 (0xc) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_TZF ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief TrustZone Filter (R_TZF)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x40004000) R_TZF Structure */
|
|
|
+{
|
|
|
+ __IM uint16_t RESERVED[8];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t TZFOAD; /*!< (@ 0x00000010) TrustZone Filter Operation After Detection register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */
|
|
|
+ uint16_t : 7;
|
|
|
+ __OM uint16_t KEY : 8; /*!< [15..8] Key Code */
|
|
|
+ } TZFOAD_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED1;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t TZFPT; /*!< (@ 0x00000014) TrustZone Filter Protect register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */
|
|
|
+ uint16_t : 7;
|
|
|
+ __OM uint16_t KEY : 8; /*!< [15..8] Key Code */
|
|
|
+ } TZFPT_b;
|
|
|
+ };
|
|
|
+} R_TZF_Type; /*!< Size = 22 (0x16) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_CPSCU ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief CPU System Security Control Unit (R_CPSCU)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x40008000) R_CPSCU Structure */
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CSAR; /*!< (@ 0x00000000) Cache Security Attribution Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CACHESA : 1; /*!< [0..0] Security Attributes of Registers for Cache Control */
|
|
|
+ __IOM uint32_t CACHELSA : 1; /*!< [1..1] Security Attributes of Registers for Cache Line Configuration */
|
|
|
+ __IOM uint32_t CACHEESA : 1; /*!< [2..2] Security Attributes of Registers for Cache Error */
|
|
|
+ uint32_t : 29;
|
|
|
+ } CSAR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED[3];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SRAMSAR; /*!< (@ 0x00000010) SRAM Security Attribution Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t SRAMSA0 : 1; /*!< [0..0] Security attributes of registers for SRAM Protection */
|
|
|
+ __IOM uint32_t SRAMSA1 : 1; /*!< [1..1] Security attributes of registers for SRAM Protection
|
|
|
+ * 2 */
|
|
|
+ __IOM uint32_t SRAMSA2 : 1; /*!< [2..2] Security attributes of registers for ECC Relation */
|
|
|
+ uint32_t : 29;
|
|
|
+ } SRAMSAR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t STBRAMSAR; /*!< (@ 0x00000014) Standby RAM memory Security Attribution Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t NSBSTBR : 4; /*!< [3..0] Security attributes of each region for Standby RAM */
|
|
|
+ uint32_t : 28;
|
|
|
+ } STBRAMSAR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED1[6];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t DTCSAR; /*!< (@ 0x00000030) DTC Controller Security Attribution Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t DTCSTSA : 1; /*!< [0..0] DTC Security Attribution */
|
|
|
+ uint32_t : 31;
|
|
|
+ } DTCSAR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t DMACSAR; /*!< (@ 0x00000034) DMAC Controller Security Attribution Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t DMASTSA : 1; /*!< [0..0] DMAST Security Attribution */
|
|
|
+ uint32_t : 31;
|
|
|
+ } DMACSAR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED2[2];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t ICUSARA; /*!< (@ 0x00000040) ICU Security Attribution Register A */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t SAIRQCRn : 16; /*!< [15..0] Security Attributes of registers for the IRQCRn registers */
|
|
|
+ uint32_t : 16;
|
|
|
+ } ICUSARA_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t ICUSARB; /*!< (@ 0x00000044) ICU Security Attribution Register B */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t SANMI : 1; /*!< [0..0] Security Attributes of nonmaskable interrupt */
|
|
|
+ uint32_t : 31;
|
|
|
+ } ICUSARB_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t ICUSARC; /*!< (@ 0x00000048) ICU Security Attribution Register C */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t SADMACn : 8; /*!< [7..0] Security Attributes of registers for DMAC channel */
|
|
|
+ uint32_t : 24;
|
|
|
+ } ICUSARC_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t ICUSARD; /*!< (@ 0x0000004C) ICU Security Attribution Register D */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t SASELSR0 : 1; /*!< [0..0] Security Attributes of registers for SELSR0 */
|
|
|
+ uint32_t : 31;
|
|
|
+ } ICUSARD_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t ICUSARE; /*!< (@ 0x00000050) ICU Security Attribution Register E */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 16;
|
|
|
+ __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */
|
|
|
+ __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */
|
|
|
+ __IOM uint32_t SAVBATTWUP : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20 */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */
|
|
|
+ __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */
|
|
|
+ __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */
|
|
|
+ __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */
|
|
|
+ __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */
|
|
|
+ __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */
|
|
|
+ } ICUSARE_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t ICUSARF; /*!< (@ 0x00000054) ICU Security Attribution Register F */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t SAAGT3UDWUP : 1; /*!< [0..0] Security Attributes of registers for WUPEN1.b 0 */
|
|
|
+ __IOM uint32_t SAAGT3CAWUP : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1 */
|
|
|
+ __IOM uint32_t SAAGT3CBWUP : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2 */
|
|
|
+ __IOM uint32_t SACOMPHS0WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN1.b 3 */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t SAULP0UWUP : 1; /*!< [8..8] Security attributes of registers for WUPEN1.b 8 */
|
|
|
+ __IOM uint32_t SAULP0AWUP : 1; /*!< [9..9] Security attributes of registers for WUPEN1.b 9 */
|
|
|
+ __IOM uint32_t SAULP0BWUP : 1; /*!< [10..10] Security Attributes of registers for WUPEN1.b 10 */
|
|
|
+ __IOM uint32_t SAI3CWUP : 1; /*!< [11..11] Security Attributes of registers for WUPEN1.b 11 */
|
|
|
+ __IOM uint32_t SAULP1UWUP : 1; /*!< [12..12] Security Attributes of registers for WUPEN1.b 12 */
|
|
|
+ __IOM uint32_t SAULP1AWUP : 1; /*!< [13..13] Security Attributes of registers for WUPEN1.b 13 */
|
|
|
+ __IOM uint32_t SAULP1BWUP : 1; /*!< [14..14] Security Attributes of registers for WUPEN1.b 14 */
|
|
|
+ uint32_t : 17;
|
|
|
+ } ICUSARF_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED3[6];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t ICUSARG; /*!< (@ 0x00000070) ICU Security Attribution Register G */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR31 to IELSR0 */
|
|
|
+ } ICUSARG_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t ICUSARH; /*!< (@ 0x00000074) ICU Security Attribution Register H */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR63 to IELSR32 */
|
|
|
+ } ICUSARH_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t ICUSARI; /*!< (@ 0x00000078) ICU Security Attribution Register I */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR95 to IELSR64 */
|
|
|
+ } ICUSARI_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED4[33];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t BUSSARA; /*!< (@ 0x00000100) Bus Security Attribution Register A */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t BUSSA0 : 1; /*!< [0..0] BUS Security Attribution A0 */
|
|
|
+ uint32_t : 31;
|
|
|
+ } BUSSARA_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t BUSSARB; /*!< (@ 0x00000104) Bus Security Attribution Register B */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t BUSSB0 : 1; /*!< [0..0] BUS Security Attribution B0 */
|
|
|
+ uint32_t : 31;
|
|
|
+ } BUSSARB_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED5[10];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t MMPUSARA; /*!< (@ 0x00000130) Master Memory Protection Unit Security Attribution
|
|
|
+ * Register A */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t MMPUAnSA : 8; /*!< [7..0] MMPUAn Security Attribution (n = 0 to 7) */
|
|
|
+ uint32_t : 24;
|
|
|
+ } MMPUSARA_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t MMPUSARB; /*!< (@ 0x00000134) Master Memory Protection Unit Security Attribution
|
|
|
+ * Register B */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t MMPUB0SA : 1; /*!< [0..0] MMPUB0 Security Attribution */
|
|
|
+ uint32_t : 31;
|
|
|
+ } MMPUSARB_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED6[26];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t DMACCHSAR; /*!< (@ 0x000001A0) DMA channel Security Attribution Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t DMACCHSARn : 8; /*!< [7..0] Security attributes of output and registers for DMAC
|
|
|
+ * channel */
|
|
|
+ uint32_t : 24;
|
|
|
+ } DMACCHSAR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED7[3];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CPUDSAR; /*!< (@ 0x000001B0) CPU Debug Security Attribution Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CPUDSA0 : 1; /*!< [0..0] CPU Debug Security Attribution 0 */
|
|
|
+ uint32_t : 31;
|
|
|
+ } CPUDSAR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED8[147];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SRAMSABAR0; /*!< (@ 0x00000400) SRAM Security Attribute Boundary Address Register
|
|
|
+ * 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 13;
|
|
|
+ __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start
|
|
|
+ * address of non-secure region). */
|
|
|
+ uint32_t : 11;
|
|
|
+ } SRAMSABAR0_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SRAMSABAR1; /*!< (@ 0x00000404) SRAM Security Attribute Boundary Address Register
|
|
|
+ * 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 13;
|
|
|
+ __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start
|
|
|
+ * address of non-secure region). */
|
|
|
+ uint32_t : 11;
|
|
|
+ } SRAMSABAR1_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED9[126];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t TEVTRCR; /*!< (@ 0x00000600) Trusted Event Route Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t TEVTE : 1; /*!< [0..0] Trusted Event Route Control Register for IELSRn, DELSRn
|
|
|
+ * and ELCSRn */
|
|
|
+ uint32_t : 31;
|
|
|
+ } TEVTRCR_b;
|
|
|
+ };
|
|
|
+} R_CPSCU_Type; /*!< Size = 1540 (0x604) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_DOC_B ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Data Operation Circuit (R_DOC_B)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x40311000) R_DOC_B Structure */
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t DOBW : 1; /*!< [3..3] Data Operation Bit Width Select */
|
|
|
+ __IOM uint8_t DCSEL : 3; /*!< [6..4] Detection Condition Select */
|
|
|
+ uint8_t : 1;
|
|
|
+ } DOCR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED;
|
|
|
+ __IM uint16_t RESERVED1;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t DOSR; /*!< (@ 0x00000004) DOC Flag Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint8_t DOPCF : 1; /*!< [0..0] Data Operation Circuit Flag */
|
|
|
+ uint8_t : 7;
|
|
|
+ } DOSR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED2;
|
|
|
+ __IM uint16_t RESERVED3;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t DOSCR; /*!< (@ 0x00000008) DOC Flag Status Clear Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __OM uint8_t DOPCFCL : 1; /*!< [0..0] DOPCF Clear */
|
|
|
+ uint8_t : 7;
|
|
|
+ } DOSCR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED4;
|
|
|
+ __IM uint16_t RESERVED5;
|
|
|
+ __IOM uint32_t DODIR; /*!< (@ 0x0000000C) DOC Data Input Register */
|
|
|
+ __IOM uint32_t DODSR0; /*!< (@ 0x00000010) DOC Data Setting Register 0 */
|
|
|
+ __IOM uint32_t DODSR1; /*!< (@ 0x00000014) DOC Data Setting Register 1 */
|
|
|
+} R_DOC_B_Type; /*!< Size = 24 (0x18) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_SCI_B0 ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Serial Communication Interface 0 (R_SCI_B0)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x40358000) R_SCI_B0 Structure */
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t RDR; /*!< (@ 0x00000000) Receive Data Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t RDAT : 9; /*!< [8..0] Serial receive data */
|
|
|
+ __IM uint32_t MPB : 1; /*!< [9..9] Multi-processor flag */
|
|
|
+ __IM uint32_t DR : 1; /*!< [10..10] Receive data ready flag */
|
|
|
+ __IM uint32_t FPER : 1; /*!< [11..11] FIFO parity error flag */
|
|
|
+ __IM uint32_t FFER : 1; /*!< [12..12] FIFO framing error flag */
|
|
|
+ uint32_t : 11;
|
|
|
+ __IM uint32_t ORER : 1; /*!< [24..24] Overrun Error flag */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IM uint32_t PER : 1; /*!< [27..27] Parity error flag */
|
|
|
+ __IM uint32_t FER : 1; /*!< [28..28] Framing error flag */
|
|
|
+ uint32_t : 3;
|
|
|
+ } RDR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t RDR_BY; /*!< (@ 0x00000000) Receive Data Register (byte access) */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t RDAT : 8; /*!< [7..0] Serial receive data */
|
|
|
+ } RDR_BY_b;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t TDR; /*!< (@ 0x00000004) Transmit Data Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t TDAT : 9; /*!< [8..0] Serial transmit data */
|
|
|
+ __IOM uint32_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t TSYNC : 1; /*!< [12..12] Transmit SYNC data */
|
|
|
+ uint32_t : 19;
|
|
|
+ } TDR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t TDR_BY; /*!< (@ 0x00000004) Transmit Data Register (byte access) */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t TDAT : 8; /*!< [7..0] Serial transmit data */
|
|
|
+ } TDR_BY_b;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CCR0; /*!< (@ 0x00000008) Common Control Register 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t RE : 1; /*!< [0..0] Receive Enable */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t TE : 1; /*!< [4..4] Transmit Enable */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t MPIE : 1; /*!< [8..8] Multi-Processor Interrupt Enable */
|
|
|
+ __IOM uint32_t DCME : 1; /*!< [9..9] Data Compare Match Enable */
|
|
|
+ __IOM uint32_t IDSEL : 1; /*!< [10..10] ID frame select */
|
|
|
+ uint32_t : 5;
|
|
|
+ __IOM uint32_t RIE : 1; /*!< [16..16] Receive Interrupt Enable */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t TIE : 1; /*!< [20..20] Transmit Interrupt Enable */
|
|
|
+ __IOM uint32_t TEIE : 1; /*!< [21..21] Transmit End Interrupt Enable */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t SSE : 1; /*!< [24..24] SSn Pin Function Enable */
|
|
|
+ uint32_t : 7;
|
|
|
+ } CCR0_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CCR1; /*!< (@ 0x0000000C) Common Control Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CTSE : 1; /*!< [0..0] CTS Enable */
|
|
|
+ __IOM uint32_t CTSPEN : 1; /*!< [1..1] CTS external pin Enable */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t SPB2DT : 1; /*!< [4..4] Serial port break data select */
|
|
|
+ __IOM uint32_t SPB2IO : 1; /*!< [5..5] Serial port break I/O */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t PE : 1; /*!< [8..8] Parity Enable */
|
|
|
+ __IOM uint32_t PM : 1; /*!< [9..9] Parity Mode */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t TINV : 1; /*!< [12..12] TXD invert */
|
|
|
+ __IOM uint32_t RINV : 1; /*!< [13..13] RXD invert */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t SPLP : 1; /*!< [16..16] Loopback Control */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t SHARPS : 1; /*!< [20..20] Half-duplex communication select */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t NFCS : 3; /*!< [26..24] Noise Filter Clock Select */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t NFEN : 1; /*!< [28..28] Digital Noise Filter Function Enable */
|
|
|
+ uint32_t : 3;
|
|
|
+ } CCR1_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CCR2; /*!< (@ 0x00000010) Common Control Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t BCP : 3; /*!< [2..0] Base Clock Pulse */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t BGDM : 1; /*!< [4..4] Baud Rate Generator Double-Speed Mode Select */
|
|
|
+ __IOM uint32_t ABCS : 1; /*!< [5..5] Asynchronous Mode Base Clock Select */
|
|
|
+ __IOM uint32_t ABCSE : 1; /*!< [6..6] Asynchronous Mode Extended Base Clock Select */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t BRR : 8; /*!< [15..8] Bit rate setting */
|
|
|
+ __IOM uint32_t BRME : 1; /*!< [16..16] Bit Modulation Enable */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t CKS : 2; /*!< [21..20] Clock Select */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t MDDR : 8; /*!< [31..24] Modulation Duty Setting */
|
|
|
+ } CCR2_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CCR3; /*!< (@ 0x00000014) Common Control Register 3 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CPHA : 1; /*!< [0..0] Clock Phase Select */
|
|
|
+ __IOM uint32_t CPOL : 1; /*!< [1..1] Clock Polarity Select */
|
|
|
+ uint32_t : 5;
|
|
|
+ __IOM uint32_t BPEN : 1; /*!< [7..7] Synchronizer bypass enable */
|
|
|
+ __IOM uint32_t CHR : 2; /*!< [9..8] Character Length */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t LSBF : 1; /*!< [12..12] LSB First select */
|
|
|
+ __IOM uint32_t SINV : 1; /*!< [13..13] Transmitted/Received Data Invert */
|
|
|
+ __IOM uint32_t STP : 1; /*!< [14..14] Stop Bit Length */
|
|
|
+ __IOM uint32_t RXDESEL : 1; /*!< [15..15] Asynchronous Start Bit Edge Detection Select */
|
|
|
+ __IOM uint32_t MOD : 3; /*!< [18..16] Communication mode select */
|
|
|
+ __IOM uint32_t MP : 1; /*!< [19..19] Multi-Processor Mode */
|
|
|
+ __IOM uint32_t FM : 1; /*!< [20..20] FIFO Mode select */
|
|
|
+ __IOM uint32_t DEN : 1; /*!< [21..21] Driver enable */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t CKE : 2; /*!< [25..24] Clock enable */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t GM : 1; /*!< [28..28] GSM Mode */
|
|
|
+ __IOM uint32_t BLK : 1; /*!< [29..29] Block Transfer Mode */
|
|
|
+ uint32_t : 2;
|
|
|
+ } CCR3_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CCR4; /*!< (@ 0x00000018) Common Control Register 4 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CMPD : 9; /*!< [8..0] Compare Match Data */
|
|
|
+ uint32_t : 7;
|
|
|
+ __IOM uint32_t ASEN : 1; /*!< [16..16] Adjust receive sampling timing enable */
|
|
|
+ __IOM uint32_t ATEN : 1; /*!< [17..17] Adjust transmit timing enable */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t SCKSEL : 1; /*!< [19..19] Master receive clock selection bit. */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t AST : 3; /*!< [26..24] Adjustment value for receive Sampling Timing */
|
|
|
+ __IOM uint32_t AJD : 1; /*!< [27..27] Adjustment Direction for receive sampling timing */
|
|
|
+ __IOM uint32_t ATT : 3; /*!< [30..28] Adjustment value for Transmit timing */
|
|
|
+ __IOM uint32_t AET : 1; /*!< [31..31] Adjustment edge for transmit timing */
|
|
|
+ } CCR4_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint8_t CESR; /*!< (@ 0x0000001C) Communication Enable Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint8_t RIST : 1; /*!< [0..0] RE Internal status */
|
|
|
+ uint8_t : 3;
|
|
|
+ __IM uint8_t TIST : 1; /*!< [4..4] TE Internal status */
|
|
|
+ uint8_t : 3;
|
|
|
+ } CESR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED;
|
|
|
+ __IM uint16_t RESERVED1;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t ICR; /*!< (@ 0x00000020) Simple I2C Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t IICDL : 5; /*!< [4..0] SDA Delay Output Select */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t IICINTM : 1; /*!< [8..8] IIC Interrupt Mode Select */
|
|
|
+ __IOM uint32_t IICCSC : 1; /*!< [9..9] Clock Synchronization */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t IICACKT : 1; /*!< [13..13] ACK Transmission Data */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t IICSTAREQ : 1; /*!< [16..16] Start Condition Generation */
|
|
|
+ __IOM uint32_t IICRSTAREQ : 1; /*!< [17..17] Restart Condition Generation */
|
|
|
+ __IOM uint32_t IICSTPREQ : 1; /*!< [18..18] Stop Condition Generation */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t IICSDAS : 2; /*!< [21..20] SDA Output Select */
|
|
|
+ __IOM uint32_t IICSCLS : 2; /*!< [23..22] SCL Output Select */
|
|
|
+ uint32_t : 8;
|
|
|
+ } ICR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t FCR; /*!< (@ 0x00000024) FIFO Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t DRES : 1; /*!< [0..0] Receive data ready error select bit */
|
|
|
+ uint32_t : 7;
|
|
|
+ __IOM uint32_t TTRG : 5; /*!< [12..8] Transmit FIFO data trigger number */
|
|
|
+ uint32_t : 2;
|
|
|
+ __OM uint32_t TFRST : 1; /*!< [15..15] Transmit FIFO Data Register Reset */
|
|
|
+ __IOM uint32_t RTRG : 5; /*!< [20..16] Receive FIFO data trigger number */
|
|
|
+ uint32_t : 2;
|
|
|
+ __OM uint32_t RFRST : 1; /*!< [23..23] Receive FIFO Data Register Reset */
|
|
|
+ __IOM uint32_t RSTRG : 5; /*!< [28..24] RTS Output Active Trigger Number Select */
|
|
|
+ uint32_t : 3;
|
|
|
+ } FCR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED2;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t MCR; /*!< (@ 0x0000002C) Manchester Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t RMPOL : 1; /*!< [0..0] Polarity of Received Manchester Code */
|
|
|
+ __IOM uint32_t TMPOL : 1; /*!< [1..1] Polarity of Transmit Manchester Code */
|
|
|
+ __IOM uint32_t ERTEN : 1; /*!< [2..2] Manchester Edge Retiming Enable */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t SYNVAL : 1; /*!< [4..4] SYNC value Setting */
|
|
|
+ __IOM uint32_t SYNSEL : 1; /*!< [5..5] SYNC Select */
|
|
|
+ __IOM uint32_t SBSEL : 1; /*!< [6..6] Start Bit Select */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t TPLEN : 4; /*!< [11..8] Transmit preface length */
|
|
|
+ __IOM uint32_t TPPAT : 2; /*!< [13..12] Transmit preface pattern */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t RPLEN : 4; /*!< [19..16] Receive Preface Length */
|
|
|
+ __IOM uint32_t RPPAT : 2; /*!< [21..20] Receive Preface Pattern */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t PFEREN : 1; /*!< [24..24] Preface Error Enable */
|
|
|
+ __IOM uint32_t SYEREN : 1; /*!< [25..25] Receive SYNC Error Enable */
|
|
|
+ __IOM uint32_t SBEREN : 1; /*!< [26..26] Start Bit Error Enable */
|
|
|
+ uint32_t : 5;
|
|
|
+ } MCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t DCR; /*!< (@ 0x00000030) Driver Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t DEPOL : 1; /*!< [0..0] Driver effective polarity select */
|
|
|
+ uint32_t : 7;
|
|
|
+ __IOM uint32_t DEAST : 5; /*!< [12..8] Driver Assertion Time */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t DENGT : 5; /*!< [20..16] Driver negate time */
|
|
|
+ uint32_t : 11;
|
|
|
+ } DCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t XCR0; /*!< (@ 0x00000034) Simple LIN(SCIX) Control Register 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t TCSS : 2; /*!< [1..0] Timer count clock source selection */
|
|
|
+ uint32_t : 6;
|
|
|
+ __IOM uint32_t BFE : 1; /*!< [8..8] Break Field enable */
|
|
|
+ __IOM uint32_t CF0RE : 1; /*!< [9..9] Control Field 0 enable */
|
|
|
+ __IOM uint32_t CF1DS : 2; /*!< [11..10] Control Field1 compare data select */
|
|
|
+ __IOM uint32_t PIBE : 1; /*!< [12..12] Priority interrupt bit enable */
|
|
|
+ __IOM uint32_t PIBS : 3; /*!< [15..13] Priority interrupt bit select */
|
|
|
+ __IOM uint32_t BFOIE : 1; /*!< [16..16] Break Field output completion interrupt enable */
|
|
|
+ __IOM uint32_t BCDIE : 1; /*!< [17..17] Bus conflict detection interrupt enable */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t BFDIE : 1; /*!< [20..20] Break Field detection interrupt enable */
|
|
|
+ __IOM uint32_t COFIE : 1; /*!< [21..21] Counter overflow interrupt enable */
|
|
|
+ __IOM uint32_t AEDIE : 1; /*!< [22..22] Active edge detection interrupt enable */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t BCCS : 2; /*!< [25..24] Bus conflict detection clock selection */
|
|
|
+ uint32_t : 6;
|
|
|
+ } XCR0_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t XCR1; /*!< (@ 0x00000038) Simple LIN(SCIX) Control Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t TCST : 1; /*!< [0..0] Break Field output timer count start trigger */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t SDST : 1; /*!< [4..4] Start Frame detection enable */
|
|
|
+ __IOM uint32_t BMEN : 1; /*!< [5..5] Bit rate measurement enable */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t PCF1D : 8; /*!< [15..8] Priority compare data for Control Field 1 */
|
|
|
+ __IOM uint32_t SCF1D : 8; /*!< [23..16] Secondary compare data for Control Field 1 */
|
|
|
+ __IOM uint32_t CF1CE : 8; /*!< [31..24] Control Field 1 compare bit enable */
|
|
|
+ } XCR1_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t XCR2; /*!< (@ 0x0000003C) Simple LIN(SCIX) Control Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CF0D : 8; /*!< [7..0] Control Field 0compare data */
|
|
|
+ __IOM uint32_t CF0CE : 8; /*!< [15..8] Control Field 0 compare bit enable */
|
|
|
+ __IOM uint32_t BFLW : 16; /*!< [31..16] Break Field length setting */
|
|
|
+ } XCR2_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED3[2];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t CSR; /*!< (@ 0x00000048) Common Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 4;
|
|
|
+ __IM uint32_t ERS : 1; /*!< [4..4] Error Signal Status Flag */
|
|
|
+ uint32_t : 10;
|
|
|
+ __IM uint32_t RXDMON : 1; /*!< [15..15] Serial input data monitor bit */
|
|
|
+ __IM uint32_t DCMF : 1; /*!< [16..16] Data Compare Match Flag */
|
|
|
+ __IM uint32_t DPER : 1; /*!< [17..17] Data Compare Match Parity Error Flag */
|
|
|
+ __IM uint32_t DFER : 1; /*!< [18..18] Data Compare Match Framing Error Flag */
|
|
|
+ uint32_t : 5;
|
|
|
+ __IM uint32_t ORER : 1; /*!< [24..24] Overrun Error Flag */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IM uint32_t MFF : 1; /*!< [26..26] Mode Fault Flag */
|
|
|
+ __IM uint32_t PER : 1; /*!< [27..27] Parity Error Flag */
|
|
|
+ __IM uint32_t FER : 1; /*!< [28..28] Framing Error Flag */
|
|
|
+ __IM uint32_t TDRE : 1; /*!< [29..29] Transmit Data Empty Flag */
|
|
|
+ __IM uint32_t TEND : 1; /*!< [30..30] Transmit End Flag */
|
|
|
+ __IM uint32_t RDRF : 1; /*!< [31..31] Receive Data Full Flag */
|
|
|
+ } CSR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t ISR; /*!< (@ 0x0000004C) Simple I2C Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IM uint32_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed
|
|
|
+ * Flag */
|
|
|
+ uint32_t : 28;
|
|
|
+ } ISR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t FRSR; /*!< (@ 0x00000050) FIFO Receive Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t DR : 1; /*!< [0..0] Receive Data Ready flag */
|
|
|
+ uint32_t : 7;
|
|
|
+ __IM uint32_t R : 6; /*!< [13..8] Receive-FIFO Data Count */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IM uint32_t PNUM : 6; /*!< [21..16] Parity Error Count */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IM uint32_t FNUM : 6; /*!< [29..24] Framing Error Count */
|
|
|
+ uint32_t : 2;
|
|
|
+ } FRSR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t FTSR; /*!< (@ 0x00000054) FIFO Transmit Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t T : 6; /*!< [5..0] Transmit-FIFO Data Count */
|
|
|
+ uint32_t : 26;
|
|
|
+ } FTSR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t MSR; /*!< (@ 0x00000058) Manchester Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t PFER : 1; /*!< [0..0] Preface Error flag */
|
|
|
+ __IM uint32_t SYER : 1; /*!< [1..1] SYNC Error flag */
|
|
|
+ __IM uint32_t SBER : 1; /*!< [2..2] Start Bit Error flag */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IM uint32_t MER : 1; /*!< [4..4] Manchester Error Flag */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IM uint32_t RSYNC : 1; /*!< [6..6] Receive SYNC data bit */
|
|
|
+ uint32_t : 25;
|
|
|
+ } MSR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t XSR0; /*!< (@ 0x0000005C) Simple LIN (SCIX) Status Register 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t SFSF : 1; /*!< [0..0] Start Frame Status flag */
|
|
|
+ __IM uint32_t RXDSF : 1; /*!< [1..1] RXDn input status flag */
|
|
|
+ uint32_t : 6;
|
|
|
+ __IM uint32_t BFOF : 1; /*!< [8..8] Break Field Output completion flag */
|
|
|
+ __IM uint32_t BCDF : 1; /*!< [9..9] Bus Conflict detection flag */
|
|
|
+ __IM uint32_t BFDF : 1; /*!< [10..10] Break Field detection flag */
|
|
|
+ __IM uint32_t CF0MF : 1; /*!< [11..11] Control Field 0 compare match flag */
|
|
|
+ __IM uint32_t CF1MF : 1; /*!< [12..12] Control Field 1 compare match flag */
|
|
|
+ __IM uint32_t PIBDF : 1; /*!< [13..13] Priority interrupt bit detection flag */
|
|
|
+ __IM uint32_t COF : 1; /*!< [14..14] Counter Overflow flag */
|
|
|
+ __IM uint32_t AEDF : 1; /*!< [15..15] Active Edge detection flag */
|
|
|
+ __IM uint32_t CF0RD : 8; /*!< [23..16] Control Field 0 received data */
|
|
|
+ __IM uint32_t CF1RD : 8; /*!< [31..24] Control Field 1 received data */
|
|
|
+ } XSR0_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t XSR1; /*!< (@ 0x00000060) Simple LIN(SCIX) Status Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t TCNT : 16; /*!< [15..0] Timer Count Capture value */
|
|
|
+ uint32_t : 16;
|
|
|
+ } XSR1_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED4;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __OM uint32_t CFCLR; /*!< (@ 0x00000068) Common Flag Clear Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 4;
|
|
|
+ __OM uint32_t ERSC : 1; /*!< [4..4] ERS clear bit */
|
|
|
+ uint32_t : 11;
|
|
|
+ __OM uint32_t DCMFC : 1; /*!< [16..16] DCMF clear bit */
|
|
|
+ __OM uint32_t DPERC : 1; /*!< [17..17] DPER clear bit */
|
|
|
+ __OM uint32_t DFERC : 1; /*!< [18..18] DFER clear bit */
|
|
|
+ uint32_t : 5;
|
|
|
+ __OM uint32_t ORERC : 1; /*!< [24..24] ORER clear bit */
|
|
|
+ uint32_t : 1;
|
|
|
+ __OM uint32_t MFFC : 1; /*!< [26..26] MFF clear bit */
|
|
|
+ __OM uint32_t PERC : 1; /*!< [27..27] PER clear bit */
|
|
|
+ __OM uint32_t FERC : 1; /*!< [28..28] FER clear bit */
|
|
|
+ __OM uint32_t TDREC : 1; /*!< [29..29] TDRE clear bit */
|
|
|
+ uint32_t : 1;
|
|
|
+ __OM uint32_t RDRFC : 1; /*!< [31..31] RDRF clear bit */
|
|
|
+ } CFCLR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __OM uint32_t ICFCLR; /*!< (@ 0x0000006C) Simple I2C Flag Clear Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 3;
|
|
|
+ __OM uint32_t IICSTIFC : 1; /*!< [3..3] IICSTIF clear bit */
|
|
|
+ uint32_t : 28;
|
|
|
+ } ICFCLR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __OM uint32_t FFCLR; /*!< (@ 0x00000070) FIFO Flag Clear Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __OM uint32_t DRC : 1; /*!< [0..0] DR clear bit */
|
|
|
+ uint32_t : 31;
|
|
|
+ } FFCLR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __OM uint32_t MFCLR; /*!< (@ 0x00000074) Manchester Flag Clear Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __OM uint32_t PFERC : 1; /*!< [0..0] PFER clear bit */
|
|
|
+ __OM uint32_t SYERC : 1; /*!< [1..1] SYER clear bit */
|
|
|
+ __OM uint32_t SBERC : 1; /*!< [2..2] SBER clear bit */
|
|
|
+ uint32_t : 1;
|
|
|
+ __OM uint32_t MERC : 1; /*!< [4..4] MER clear bit */
|
|
|
+ uint32_t : 27;
|
|
|
+ } MFCLR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __OM uint32_t XFCLR; /*!< (@ 0x00000078) Simple LIN(SCIX) Flag Clear Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 8;
|
|
|
+ __OM uint32_t BFOC : 1; /*!< [8..8] BFOF clear bit */
|
|
|
+ __OM uint32_t BCDC : 1; /*!< [9..9] BCDF clear bit */
|
|
|
+ __OM uint32_t BFDC : 1; /*!< [10..10] BFDF clear bit */
|
|
|
+ __OM uint32_t CF0MC : 1; /*!< [11..11] CF0MF clear bit */
|
|
|
+ __OM uint32_t CF1MC : 1; /*!< [12..12] CF1MF clear bit */
|
|
|
+ __OM uint32_t PIBDC : 1; /*!< [13..13] PIBDF clear bit */
|
|
|
+ __OM uint32_t COFC : 1; /*!< [14..14] COFF clear bit */
|
|
|
+ __OM uint32_t AEDC : 1; /*!< [15..15] AEDF clear bit */
|
|
|
+ uint32_t : 16;
|
|
|
+ } XFCLR_b;
|
|
|
+ };
|
|
|
+} R_SCI_B0_Type; /*!< Size = 124 (0x7c) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_SPI_B0 ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Serial Peripheral Interface 0 (R_SPI_B0)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x4035C000) R_SPI_B0 Structure */
|
|
|
+{
|
|
|
+ __IOM uint32_t SPDR; /*!< (@ 0x00000000) RSPI Data Register */
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SPDECR; /*!< (@ 0x00000004) RSPI Delay Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t SCKDL : 3; /*!< [2..0] RSPCK Delay */
|
|
|
+ uint32_t : 5;
|
|
|
+ __IOM uint32_t SLNDL : 3; /*!< [10..8] SSL Negation Delay */
|
|
|
+ uint32_t : 5;
|
|
|
+ __IOM uint32_t SPNDL : 3; /*!< [18..16] RSPI Next-Access Delay */
|
|
|
+ uint32_t : 5;
|
|
|
+ __IOM uint32_t ARST : 3; /*!< [26..24] Receive Sampling Timing Adjustment bits */
|
|
|
+ uint32_t : 5;
|
|
|
+ } SPDECR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SPCR; /*!< (@ 0x00000008) RSPI Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t SPE : 1; /*!< [0..0] RSPI Function Enable */
|
|
|
+ uint32_t : 6;
|
|
|
+ __IOM uint32_t SPSCKSEL : 1; /*!< [7..7] RSPI Master Receive Clock Select */
|
|
|
+ __IOM uint32_t SPPE : 1; /*!< [8..8] Parity Enable */
|
|
|
+ __IOM uint32_t SPOE : 1; /*!< [9..9] Parity Mode */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t PTE : 1; /*!< [11..11] Parity Self-Diagnosis Enable */
|
|
|
+ __IOM uint32_t SCKASE : 1; /*!< [12..12] RSPCK Auto-Stop Function Enable */
|
|
|
+ __IOM uint32_t BFDS : 1; /*!< [13..13] Between Burst Transfer Frames Delay Select */
|
|
|
+ __IOM uint32_t MODFEN : 1; /*!< [14..14] Mode Fault Error Detection Enable */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t SPEIE : 1; /*!< [16..16] RSPI Error Interrupt Enable */
|
|
|
+ __IOM uint32_t SPRIE : 1; /*!< [17..17] RSPI Receive Buffer Full Interrupt Enable */
|
|
|
+ __IOM uint32_t SPIIE : 1; /*!< [18..18] RSPI Idle Interrupt Enable */
|
|
|
+ __IOM uint32_t SPDRES : 1; /*!< [19..19] RSPI receive data ready error select */
|
|
|
+ __IOM uint32_t SPTIE : 1; /*!< [20..20] RSPI Transmit Buffer Empty Interrupt Enable */
|
|
|
+ __IOM uint32_t CENDIE : 1; /*!< [21..21] RSPI Communication End Interrupt Enable */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t SPMS : 1; /*!< [24..24] RSPI Mode Select */
|
|
|
+ __IOM uint32_t SPFRF : 1; /*!< [25..25] RSPI Frame Format Select */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t TXMD : 2; /*!< [29..28] Communication Mode Select */
|
|
|
+ __IOM uint32_t MSTR : 1; /*!< [30..30] RSPI Master/Slave Mode Select */
|
|
|
+ __IOM uint32_t BPEN : 1; /*!< [31..31] Synchronization Circuit Bypass Enable */
|
|
|
+ } SPCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SPCR2; /*!< (@ 0x0000000C) RSPI Control Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t RMFM : 5; /*!< [4..0] Frame processing count setting in Master Receive only */
|
|
|
+ uint32_t : 1;
|
|
|
+ __OM uint32_t RMEDTG : 1; /*!< [6..6] End Trigger in Master Receive only */
|
|
|
+ __OM uint32_t RMSTTG : 1; /*!< [7..7] Start Trigger in Master Receive only */
|
|
|
+ __IOM uint32_t SPDRC : 8; /*!< [15..8] RSPI received data ready detect adjustment */
|
|
|
+ __IOM uint32_t SPLP : 1; /*!< [16..16] RSPI Loopback */
|
|
|
+ __IOM uint32_t SPLP2 : 1; /*!< [17..17] RSPI Loopback 2 */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t MOIFV : 1; /*!< [20..20] MOSI Idle Fixed Value */
|
|
|
+ __IOM uint32_t MOIFE : 1; /*!< [21..21] MOSI Idle Fixed Value Enable */
|
|
|
+ uint32_t : 10;
|
|
|
+ } SPCR2_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SPCR3; /*!< (@ 0x00000010) RSPI Control Register 3 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity */
|
|
|
+ __IOM uint32_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity */
|
|
|
+ __IOM uint32_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity */
|
|
|
+ __IOM uint32_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t SPBR : 8; /*!< [15..8] SPI Bit Rate */
|
|
|
+ uint32_t : 8;
|
|
|
+ __IOM uint32_t SPSLN : 3; /*!< [26..24] RSPI Sequence Length */
|
|
|
+ uint32_t : 5;
|
|
|
+ } SPCR3_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SPCMD0; /*!< (@ 0x00000014) RSPI Command Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */
|
|
|
+ __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */
|
|
|
+ __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */
|
|
|
+ __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */
|
|
|
+ __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */
|
|
|
+ __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */
|
|
|
+ __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */
|
|
|
+ uint32_t : 5;
|
|
|
+ } SPCMD0_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SPCMD1; /*!< (@ 0x00000018) RSPI Command Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */
|
|
|
+ __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */
|
|
|
+ __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */
|
|
|
+ __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */
|
|
|
+ __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */
|
|
|
+ __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */
|
|
|
+ __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */
|
|
|
+ uint32_t : 5;
|
|
|
+ } SPCMD1_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SPCMD2; /*!< (@ 0x0000001C) RSPI Command Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */
|
|
|
+ __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */
|
|
|
+ __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */
|
|
|
+ __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */
|
|
|
+ __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */
|
|
|
+ __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */
|
|
|
+ __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */
|
|
|
+ uint32_t : 5;
|
|
|
+ } SPCMD2_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SPCMD3; /*!< (@ 0x00000020) RSPI Command Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */
|
|
|
+ __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */
|
|
|
+ __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */
|
|
|
+ __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */
|
|
|
+ __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */
|
|
|
+ __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */
|
|
|
+ __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */
|
|
|
+ uint32_t : 5;
|
|
|
+ } SPCMD3_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SPCMD4; /*!< (@ 0x00000024) RSPI Command Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */
|
|
|
+ __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */
|
|
|
+ __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */
|
|
|
+ __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */
|
|
|
+ __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */
|
|
|
+ __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */
|
|
|
+ __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */
|
|
|
+ uint32_t : 5;
|
|
|
+ } SPCMD4_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SPCMD5; /*!< (@ 0x00000028) RSPI Command Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */
|
|
|
+ __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */
|
|
|
+ __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */
|
|
|
+ __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */
|
|
|
+ __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */
|
|
|
+ __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */
|
|
|
+ __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */
|
|
|
+ uint32_t : 5;
|
|
|
+ } SPCMD5_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SPCMD6; /*!< (@ 0x0000002C) RSPI Command Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */
|
|
|
+ __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */
|
|
|
+ __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */
|
|
|
+ __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */
|
|
|
+ __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */
|
|
|
+ __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */
|
|
|
+ __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */
|
|
|
+ uint32_t : 5;
|
|
|
+ } SPCMD6_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SPCMD7; /*!< (@ 0x00000030) RSPI Command Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */
|
|
|
+ __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */
|
|
|
+ __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */
|
|
|
+ __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */
|
|
|
+ __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */
|
|
|
+ __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */
|
|
|
+ __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */
|
|
|
+ uint32_t : 5;
|
|
|
+ } SPCMD7_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED[3];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SPDCR; /*!< (@ 0x00000040) RSPI Data Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t SPRDTD : 1; /*!< [3..3] RSPI Receive Data or Transmit Data Select */
|
|
|
+ __IOM uint32_t SINV : 1; /*!< [4..4] Serial data invert bit */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t SPFC : 2; /*!< [9..8] Frame Count */
|
|
|
+ uint32_t : 22;
|
|
|
+ } SPDCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SPDCR2; /*!< (@ 0x00000044) RSPI Data Control Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t RTRG : 2; /*!< [1..0] Receive FIFO threshold setting */
|
|
|
+ uint32_t : 6;
|
|
|
+ __IOM uint32_t TTRG : 2; /*!< [9..8] Transmission FIFO threshold setting */
|
|
|
+ uint32_t : 22;
|
|
|
+ } SPDCR2_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED1[2];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t SPSR; /*!< (@ 0x00000050) SPI Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 8;
|
|
|
+ __IM uint32_t SPCP : 3; /*!< [10..8] RSPI Command Pointer */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IM uint32_t SPECM : 3; /*!< [14..12] RSPI Error Command */
|
|
|
+ uint32_t : 8;
|
|
|
+ __IM uint32_t SPDRF : 1; /*!< [23..23] RSPI Receive Data Ready Flag */
|
|
|
+ __IM uint32_t OVRF : 1; /*!< [24..24] Overrun Error Flag */
|
|
|
+ __IM uint32_t IDLNF : 1; /*!< [25..25] RSPI Idle Flag */
|
|
|
+ __IM uint32_t MODF : 1; /*!< [26..26] Mode Fault Error Flag */
|
|
|
+ __IM uint32_t PERF : 1; /*!< [27..27] Parity Error Flag */
|
|
|
+ __IM uint32_t UDRF : 1; /*!< [28..28] Underrun Error Flag */
|
|
|
+ __IM uint32_t SPTEF : 1; /*!< [29..29] RSPI Transmit Buffer Empty Flag */
|
|
|
+ __IM uint32_t CENDF : 1; /*!< [30..30] Communication End Flag */
|
|
|
+ __IM uint32_t SPRF : 1; /*!< [31..31] RSPI Receive Buffer Full Flag */
|
|
|
+ } SPSR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED2;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t SPTFSR; /*!< (@ 0x00000058) RSPI Transfer FIFO Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t TFDN : 3; /*!< [2..0] Transmit FIFO data empty stage number */
|
|
|
+ uint32_t : 29;
|
|
|
+ } SPTFSR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t SPRFSR; /*!< (@ 0x0000005C) RSPI Receive FIFO Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t RFDN : 3; /*!< [2..0] Receive FIFO data store stage number */
|
|
|
+ uint32_t : 29;
|
|
|
+ } SPRFSR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t SPPSR; /*!< (@ 0x00000060) RSPI Poling Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t SPEPS : 1; /*!< [0..0] RSPI Poling Status */
|
|
|
+ uint32_t : 31;
|
|
|
+ } SPPSR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED3;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SPSRC; /*!< (@ 0x00000068) RSPI Status Clear Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 23;
|
|
|
+ __OM uint32_t SPDRFC : 1; /*!< [23..23] RSPI Receive Data Ready Flag Clear */
|
|
|
+ __OM uint32_t OVRFC : 1; /*!< [24..24] Overrun Error Flag Clear */
|
|
|
+ uint32_t : 1;
|
|
|
+ __OM uint32_t MODFC : 1; /*!< [26..26] Mode Fault Error Flag Clear */
|
|
|
+ __OM uint32_t PERFC : 1; /*!< [27..27] Parity Error Flag Clear */
|
|
|
+ __OM uint32_t UDRFC : 1; /*!< [28..28] Underrun Error Flag Clear */
|
|
|
+ __OM uint32_t SPTEFC : 1; /*!< [29..29] RSPI Transmit Buffer Empty Flag Clear */
|
|
|
+ __OM uint32_t CENDFC : 1; /*!< [30..30] Communication End Flag Clear */
|
|
|
+ __OM uint32_t SPRFC : 1; /*!< [31..31] RSPI Receive Buffer Full Flag Clear */
|
|
|
+ } SPSRC_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t SPFCR; /*!< (@ 0x0000006C) RSPI FIFO Clear Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __OM uint32_t SPFRST : 1; /*!< [0..0] RSPI FIFO clear */
|
|
|
+ uint32_t : 31;
|
|
|
+ } SPFCR_b;
|
|
|
+ };
|
|
|
+} R_SPI_B0_Type; /*!< Size = 112 (0x70) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_USB_HS0 ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief USB 2.0 High-Speed Module (R_USB_HS0)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x40351000) R_USB_HS0 Structure */
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */
|
|
|
+ uint16_t : 3;
|
|
|
+ __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */
|
|
|
+ __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */
|
|
|
+ __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */
|
|
|
+ __IOM uint16_t HSE : 1; /*!< [7..7] High-Speed Operation Enable */
|
|
|
+ __IOM uint16_t CNEN : 1; /*!< [8..8] Single End Receiver Enable */
|
|
|
+ uint16_t : 7;
|
|
|
+ } SYSCFG_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2
|
|
|
+ * access cycles) */
|
|
|
+ uint16_t : 12;
|
|
|
+ } BUSWAIT_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */
|
|
|
+ __IM uint16_t IDMON : 1; /*!< [2..2] ID0 Pin Monitor */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is
|
|
|
+ * Selected. */
|
|
|
+ __IM uint16_t HTACT : 1; /*!< [6..6] Host Sequencer Status Monitor */
|
|
|
+ uint16_t : 7;
|
|
|
+ __IM uint16_t OVCMON : 2; /*!< [15..14] External USB1_OVRCURA/USB1_OVRCURB Input Pin MonitorThe
|
|
|
+ * OCVMON[1] bit indicates the status of the USBHS_OVRCURA
|
|
|
+ * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB
|
|
|
+ * pin. */
|
|
|
+ } SYSSTS0_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */
|
|
|
+ uint16_t : 15;
|
|
|
+ } PLLSTA_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Operation Enable for the Host Controller Operation */
|
|
|
+ __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Signal Output for the Host Controller Operation */
|
|
|
+ __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output for the Host Controller Operation */
|
|
|
+ __IOM uint16_t RWUPE : 1; /*!< [7..7] Remote Wakeup Detection Enable for the Host Controller
|
|
|
+ * Operation */
|
|
|
+ __IOM uint16_t WKUP : 1; /*!< [8..8] Remote Wakeup Output for the Device Controller Operation */
|
|
|
+ __IOM uint16_t VBUSEN : 1; /*!< [9..9] USBHS_VBUSEN Output Pin Control */
|
|
|
+ __IOM uint16_t EXICEN : 1; /*!< [10..10] USBHS_EXICEN Output Pin Control */
|
|
|
+ __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control Use this bit
|
|
|
+ * when switching from device B to device A in OTGmode. If
|
|
|
+ * the HNPBTOA bit is 1, the internal function controlremains
|
|
|
+ * in the Suspend state until the HNP processing endseven
|
|
|
+ * if SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is set. */
|
|
|
+ uint16_t : 4;
|
|
|
+ } DVSTCTR0_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */
|
|
|
+ uint16_t : 12;
|
|
|
+ } TESTMODE_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED1;
|
|
|
+ __IM uint32_t RESERVED2;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port.Read receive data from the FIFO buffer or
|
|
|
+ * write transmit data to the FIFO buffer by accessing these
|
|
|
+ * bits. */
|
|
|
+ } CFIFO_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */
|
|
|
+ __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint8_t RESERVED3;
|
|
|
+ __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port Read receive data from the FIFO buffer or
|
|
|
+ * write transmit data to the FIFO buffer by accessing these
|
|
|
+ * bits. */
|
|
|
+ } D0FIFO_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */
|
|
|
+ __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint8_t RESERVED4;
|
|
|
+ __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO PortRead receive data from the FIFO buffer or write
|
|
|
+ * transmit data to the FIFO buffer by accessing these bits. */
|
|
|
+ } D1FIFO_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */
|
|
|
+ __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint8_t RESERVED5;
|
|
|
+ __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t ISEL : 1; /*!< [5..5] FIFO Port Access Direction when DCP is Selected */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */
|
|
|
+ uint16_t : 2;
|
|
|
+ __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */
|
|
|
+ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */
|
|
|
+ } CFIFOSEL_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive
|
|
|
+ * data. */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can
|
|
|
+ * be accessed. */
|
|
|
+ __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */
|
|
|
+ __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */
|
|
|
+ } CFIFOCTR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED6;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */
|
|
|
+ uint16_t : 4;
|
|
|
+ __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */
|
|
|
+ __IOM uint16_t DREQE : 1; /*!< [12..12] UCL_Dx_DREQ Signal Output Enable */
|
|
|
+ __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified
|
|
|
+ * Pipe Data is Read */
|
|
|
+ __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */
|
|
|
+ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */
|
|
|
+ } D0FIFOSEL_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive
|
|
|
+ * data. */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can
|
|
|
+ * be accessed. */
|
|
|
+ __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */
|
|
|
+ __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */
|
|
|
+ } D0FIFOCTR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */
|
|
|
+ uint16_t : 4;
|
|
|
+ __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */
|
|
|
+ __IOM uint16_t DREQE : 1; /*!< [12..12] UCL_Dx_DREQ Signal Output Enable */
|
|
|
+ __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified
|
|
|
+ * Pipe Data is Read */
|
|
|
+ __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */
|
|
|
+ __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */
|
|
|
+ } D1FIFOSEL_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive
|
|
|
+ * data. */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can
|
|
|
+ * be accessed. */
|
|
|
+ __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */
|
|
|
+ __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */
|
|
|
+ } D1FIFOCTR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint16_t : 8;
|
|
|
+ __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */
|
|
|
+ __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */
|
|
|
+ __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */
|
|
|
+ __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */
|
|
|
+ __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */
|
|
|
+ __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */
|
|
|
+ __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */
|
|
|
+ __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */
|
|
|
+ } INTENB0_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */
|
|
|
+ uint16_t : 3;
|
|
|
+ __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */
|
|
|
+ __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */
|
|
|
+ __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t LPMENDE : 1; /*!< [8..8] LPM Transaction End Interrupt Enable */
|
|
|
+ __IOM uint16_t L1RSMENDE : 1; /*!< [9..9] L1 Resume End Interrupt Enable */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */
|
|
|
+ __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */
|
|
|
+ __IOM uint16_t OVRCRE : 1; /*!< [15..15] OVRCRE Interrupt Enable */
|
|
|
+ } INTENB1_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED7;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t PIPEBRDYE : 10; /*!< [9..0] BRDY Interrupt Enable for Each Pipe */
|
|
|
+ uint16_t : 6;
|
|
|
+ } BRDYENB_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t PIPENRDYE : 10; /*!< [9..0] NRDY Interrupt Enable for Each Pipe */
|
|
|
+ uint16_t : 6;
|
|
|
+ } NRDYENB_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t PIPEBEMPE : 10; /*!< [9..0] BEMP Interrupt Enable for Each Pipe */
|
|
|
+ uint16_t : 6;
|
|
|
+ } BEMPENB_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Pin Configuration Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint16_t : 4;
|
|
|
+ __IM uint16_t EDGESTS : 1; /*!< [4..4] Interrupt Edge Processing Status Monitor */
|
|
|
+ __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */
|
|
|
+ __IOM uint16_t BRDYM : 1; /*!< [6..6] PIPEBRDY Interrupt Status Clear Timing.This bit can be
|
|
|
+ * set only in the initial setting (before communications).The
|
|
|
+ * setting cannot be changed once communication starts. */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select.The transfer efficiency
|
|
|
+ * can be improved by setting this bit to 1 if no low-speed
|
|
|
+ * device is connected directly or via FS-HUB to the USB port. */
|
|
|
+ uint16_t : 7;
|
|
|
+ } SOFCFG_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */
|
|
|
+ __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */
|
|
|
+ __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */
|
|
|
+ uint16_t : 3;
|
|
|
+ __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */
|
|
|
+ } PHYSET_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */
|
|
|
+ __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */
|
|
|
+ __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */
|
|
|
+ __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */
|
|
|
+ __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */
|
|
|
+ __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */
|
|
|
+ __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */
|
|
|
+ __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */
|
|
|
+ __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */
|
|
|
+ __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */
|
|
|
+ __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */
|
|
|
+ __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */
|
|
|
+ } INTSTS0_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET Detection Interrupt Status */
|
|
|
+ uint16_t : 3;
|
|
|
+ __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */
|
|
|
+ __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */
|
|
|
+ __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */
|
|
|
+ __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t ATTCH : 1; /*!< [11..11] USB Connection Detection Interrupt Status */
|
|
|
+ __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */
|
|
|
+ __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Interrupt Status */
|
|
|
+ } INTSTS1_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED8;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t PIPEBRDY : 10; /*!< [9..0] BRDY Interrupt Status for Each Pipe */
|
|
|
+ uint16_t : 6;
|
|
|
+ } BRDYSTS_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t PIPENRDY : 10; /*!< [9..0] NRDY Interrupt Status for Each Pipe */
|
|
|
+ uint16_t : 6;
|
|
|
+ } NRDYSTS_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t PIPEBEMP : 10; /*!< [9..0] BEMP Interrupt Status for Each Pipe */
|
|
|
+ uint16_t : 6;
|
|
|
+ } BEMPSTS_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t FRNM : 11; /*!< [10..0] Frame Number.Indicate the latest frame number. */
|
|
|
+ uint16_t : 3;
|
|
|
+ __IOM uint16_t CRCE : 1; /*!< [14..14] CRC Error Detection Status */
|
|
|
+ __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */
|
|
|
+ } FRMNUM_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */
|
|
|
+ uint16_t : 12;
|
|
|
+ __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */
|
|
|
+ } UFRMNUM_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint16_t : 8;
|
|
|
+ __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */
|
|
|
+ uint16_t : 5;
|
|
|
+ } USBADDR_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED9;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] USB request bmRequestType value Finction controller selected
|
|
|
+ * : read-only Host controller selected : read-write */
|
|
|
+ __IOM uint16_t BREQUEST : 8; /*!< [15..8] USB request bRequest value Finction controller selected
|
|
|
+ * : read-only Host controller selected : read-write */
|
|
|
+ } USBREQ_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t WVALUE : 16; /*!< [15..0] Value of USB request wValue Finction controller selected
|
|
|
+ * : read-only Host controller selected : read-write */
|
|
|
+ } USBVAL_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t WINDEX : 16; /*!< [15..0] Value of USB request wIndex Finction controller selected
|
|
|
+ * : read-only Host controller selected : read-write */
|
|
|
+ } USBINDX_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t WLENGTH : 16; /*!< [15..0] Value of USB request wLength Finction controller selected
|
|
|
+ * : read-only Host controller selected : read-write */
|
|
|
+ } USBLENG_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint16_t : 4;
|
|
|
+ __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Blocking on End of Transfer */
|
|
|
+ __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */
|
|
|
+ uint16_t : 7;
|
|
|
+ } DCPCFG_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits specify the maximum data
|
|
|
+ * payload (maximum packet size) for the DCP. */
|
|
|
+ uint16_t : 5;
|
|
|
+ __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device SelectThese bits specify the address of the
|
|
|
+ * destination function device for control transfer when the
|
|
|
+ * host controller function is selected. */
|
|
|
+ } DCPMAXP_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t PID : 2; /*!< [1..0] Response PID */
|
|
|
+ __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t PINGE : 1; /*!< [4..4] PING Token Issue Enable */
|
|
|
+ __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */
|
|
|
+ __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */
|
|
|
+ __IOM uint16_t SQSET : 1; /*!< [7..7] Toggle Bit Set */
|
|
|
+ __IOM uint16_t SQCLR : 1; /*!< [8..8] Toggle Bit Clear */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */
|
|
|
+ __IM uint16_t CSSTS : 1; /*!< [12..12] Split Transaction COMPLETE SPLIT(CSPLIT) Status */
|
|
|
+ __IOM uint16_t CSCLR : 1; /*!< [13..13] Split Transaction CSPLIT Status Clear */
|
|
|
+ __IOM uint16_t SUREQ : 1; /*!< [14..14] SETUP Token Transmission */
|
|
|
+ __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */
|
|
|
+ } DCPCTR_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED10;
|
|
|
+ __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */
|
|
|
+ __IM uint16_t RESERVED11;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint Number */
|
|
|
+ __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */
|
|
|
+ __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */
|
|
|
+ __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */
|
|
|
+ __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */
|
|
|
+ uint16_t : 3;
|
|
|
+ __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */
|
|
|
+ } PIPECFG_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t PIPEBUF; /*!< (@ 0x0000006A) Pipe Buffer Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t BUFNMB : 8; /*!< [7..0] Buffer NumberThese bits specify the FIFO buffer number
|
|
|
+ * of the selected pipe (04h to 87h). */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IOM uint16_t BUFSIZE : 5; /*!< [14..10] Buffer Size 00h: 64 bytes 01h: 128 bytes : 1Fh: 2 Kbytes */
|
|
|
+ uint16_t : 1;
|
|
|
+ } PIPEBUF_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t MXPS : 11; /*!< [10..0] Maximum Packet SizeThese bits specify the maximum data
|
|
|
+ * payload (maximum packet size) for the selected pipe.A size
|
|
|
+ * of 1h to 40h bytes can be set for PIPE6 to PIPE9. */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device SelectThese bits specify the address of the
|
|
|
+ * peripheral device when the host controller function is
|
|
|
+ * selected. */
|
|
|
+ } PIPEMAXP_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalThese bits specify the
|
|
|
+ * transfer interval timing for the selected pipe as n-th
|
|
|
+ * power of 2 of the frame timing. */
|
|
|
+ uint16_t : 9;
|
|
|
+ __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */
|
|
|
+ uint16_t : 3;
|
|
|
+ } PIPEPERI_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) PIPE Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t PID : 2; /*!< [1..0] Response PIDThese bits specify the response type for
|
|
|
+ * the next transaction of the relevant pipe. */
|
|
|
+ uint16_t : 3;
|
|
|
+ __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe BusyThis bit indicates whether the relevant pipe
|
|
|
+ * is being used for the USB bus */
|
|
|
+ __IM uint16_t SQMON : 1; /*!< [6..6] Toggle Bit ConfirmationThis bit indicates the expected
|
|
|
+ * value of the sequence toggle bit for the next transaction
|
|
|
+ * of the relevant pipe */
|
|
|
+ __IOM uint16_t SQSET : 1; /*!< [7..7] Toggle Bit SetThis bit is set to 1 when the expected
|
|
|
+ * value of the sequence toggle bit for the next transaction
|
|
|
+ * of the relevant pipe is set for DATA1 */
|
|
|
+ __IOM uint16_t SQCLR : 1; /*!< [8..8] Toggle Bit ClearThis bit is set to 1 when the expected
|
|
|
+ * value of the sequence toggle bit for the next transaction
|
|
|
+ * of the relevant pipe is cleared to DATA0 */
|
|
|
+ __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear ModeThis bit enables or disables auto
|
|
|
+ * buffer clear mode for the relevant pipe */
|
|
|
+ __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response ModeThis bit enables or disables auto
|
|
|
+ * response mode for the relevant pipe. */
|
|
|
+ uint16_t : 1;
|
|
|
+ __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of
|
|
|
+ * Split Transaction of the relevant pipe */
|
|
|
+ __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing
|
|
|
+ * the CSSTS bit of the relevant pipe */
|
|
|
+ __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer MonitorThis bit indicates the FIFO
|
|
|
+ * buffer status for the relevant pipe in the transmitting
|
|
|
+ * direction. */
|
|
|
+ __IM uint16_t BSTS : 1; /*!< [15..15] Buffer StatusThis bit indicates the FIFO buffer status
|
|
|
+ * for the relevant pipe. */
|
|
|
+ } PIPE_CTR_b[9];
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED12;
|
|
|
+ __IM uint32_t RESERVED13[3];
|
|
|
+ __IOM R_USB_HS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */
|
|
|
+ __IM uint32_t RESERVED14[11];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint16_t : 6;
|
|
|
+ __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */
|
|
|
+ __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */
|
|
|
+ __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */
|
|
|
+ uint16_t : 1;
|
|
|
+ } DEVADD_b[10];
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED15[7];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint16_t : 7;
|
|
|
+ __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */
|
|
|
+ uint16_t : 8;
|
|
|
+ } LPCTRL_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint16_t : 14;
|
|
|
+ __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */
|
|
|
+ uint16_t : 1;
|
|
|
+ } LPSTS_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED16[15];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */
|
|
|
+ __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */
|
|
|
+ __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */
|
|
|
+ __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */
|
|
|
+ __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */
|
|
|
+ __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */
|
|
|
+ __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */
|
|
|
+ uint16_t : 6;
|
|
|
+ } BCCTRL_b;
|
|
|
+ };
|
|
|
+ __IM uint16_t RESERVED17;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */
|
|
|
+ __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */
|
|
|
+ __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid
|
|
|
+ * only when the L1RESPMD[1:0] value is 2'b11. */
|
|
|
+ __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates
|
|
|
+ * the L1 state together with the device state bits DVSQ[2:0]. */
|
|
|
+ __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold
|
|
|
+ * value used for L1NEGOMD.The format is the same as the HIRD
|
|
|
+ * field in HL1CTRL. */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */
|
|
|
+ uint16_t : 1;
|
|
|
+ } PL1CTRL1_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint16_t : 8;
|
|
|
+ __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */
|
|
|
+ __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */
|
|
|
+ uint16_t : 3;
|
|
|
+ } PL1CTRL2_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */
|
|
|
+ __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */
|
|
|
+ uint16_t : 13;
|
|
|
+ } HL1CTRL1_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to
|
|
|
+ * be set in the ADDR field of LPM token. */
|
|
|
+ uint16_t : 4;
|
|
|
+ __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */
|
|
|
+ __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the
|
|
|
+ * value to be set in the RWE field of LPM token. */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive
|
|
|
+ * period at the time of L1 Resume. */
|
|
|
+ } HL1CTRL2_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED18;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t PHYTRIM1; /*!< (@ 0x00000150) PHY Timing Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t DRISE : 2; /*!< [1..0] FS/LS Rising-Edge Output Waveform Adjustment Function */
|
|
|
+ __IOM uint16_t DFALL : 2; /*!< [3..2] FS/LS Falling-Edge Output Waveform Adjustment Function */
|
|
|
+ uint16_t : 3;
|
|
|
+ __IOM uint16_t PCOMPENB : 1; /*!< [7..7] PVDD Start-up Detection */
|
|
|
+ __IOM uint16_t HSIUP : 4; /*!< [11..8] HS Output Level Setting */
|
|
|
+ __IOM uint16_t IMPOFFSET : 3; /*!< [14..12] terminating resistance offset value setting.Offset
|
|
|
+ * value for adjusting the terminating resistance. */
|
|
|
+ uint16_t : 1;
|
|
|
+ } PHYTRIM1_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t PHYTRIM2; /*!< (@ 0x00000152) PHY Timing Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t SQU : 4; /*!< [3..0] Squelch Detection Level */
|
|
|
+ uint16_t : 3;
|
|
|
+ __IOM uint16_t HSRXENMO : 1; /*!< [7..7] HS Receive Enable Control Mode */
|
|
|
+ __IOM uint16_t PDR : 2; /*!< [9..8] HS Output Adjustment Function */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IOM uint16_t DIS : 3; /*!< [14..12] Disconnect Detection Level */
|
|
|
+ uint16_t : 1;
|
|
|
+ } PHYTRIM2_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED19[3];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor
|
|
|
+ * Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 20;
|
|
|
+ __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the
|
|
|
+ * HS side of USB port. */
|
|
|
+ __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the
|
|
|
+ * HS side of USB port. */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side
|
|
|
+ * of USB port. */
|
|
|
+ uint32_t : 8;
|
|
|
+ } DPUSR0R_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */
|
|
|
+ __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */
|
|
|
+ uint32_t : 12;
|
|
|
+ __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */
|
|
|
+ __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */
|
|
|
+ uint32_t : 8;
|
|
|
+ } DPUSR1R_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */
|
|
|
+ __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB
|
|
|
+ * port. */
|
|
|
+ __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB
|
|
|
+ * port. */
|
|
|
+ uint16_t : 2;
|
|
|
+ __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */
|
|
|
+ __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */
|
|
|
+ uint16_t : 6;
|
|
|
+ } DPUSR2R_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */
|
|
|
+ __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */
|
|
|
+ uint16_t : 14;
|
|
|
+ } DPUSRCR_b;
|
|
|
+ };
|
|
|
+} R_USB_HS0_Type; /*!< Size = 364 (0x16c) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_XSPI ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief eXpanded SPI (R_XSPI)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x40268000) R_XSPI Structure */
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t WRAPCFG; /*!< (@ 0x00000000) xSPI Wrapper Configuration register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CKSFTCS0 : 5; /*!< [4..0] CK shift for slave0 */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t DSSFTCS0 : 5; /*!< [12..8] DS shift for slave0 */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t CKSFTCS1 : 5; /*!< [20..16] CK shift for slave1 */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t DSSFTCS1 : 5; /*!< [28..24] DS shift for slave1 */
|
|
|
+ uint32_t : 3;
|
|
|
+ } WRAPCFG_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t COMCFG; /*!< (@ 0x00000004) xSPI Common Configuration register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t ARBMD : 2; /*!< [1..0] Channel arbitration mode */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t ECSINTOUTEN : 2; /*!< [5..4] ECS/INT Output Enable */
|
|
|
+ uint32_t : 10;
|
|
|
+ __IOM uint32_t OEASTEX : 1; /*!< [16..16] Output Enable Asserting extension */
|
|
|
+ __IOM uint32_t OENEGEX : 1; /*!< [17..17] Output Enable Negating extension */
|
|
|
+ uint32_t : 14;
|
|
|
+ } COMCFG_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t BMCFGCH[2]; /*!< (@ 0x00000008) xSPI Bridge Map Configuration register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t WRMD : 1; /*!< [0..0] AHB Write Response mode */
|
|
|
+ uint32_t : 6;
|
|
|
+ __IOM uint32_t MWRCOMB : 1; /*!< [7..7] Memory Write Combination mode */
|
|
|
+ __IOM uint32_t MWRSIZE : 8; /*!< [15..8] Memory Write Size */
|
|
|
+ __IOM uint32_t PREEN : 1; /*!< [16..16] Prefetch enable */
|
|
|
+ uint32_t : 7;
|
|
|
+ __IOM uint32_t CMBTIM : 8; /*!< [31..24] Combination timer */
|
|
|
+ } BMCFGCH_b[2];
|
|
|
+ };
|
|
|
+ __IOM R_XSPI_CMCFGCS_Type CMCFGCS[2]; /*!< (@ 0x00000010) xSPI Command Map Configuration registers */
|
|
|
+ __IM uint32_t RESERVED[8];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t LIOCFGCS[2]; /*!< (@ 0x00000050) xSPI Link I/O Configuration register CS[0..1] */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t PRTMD : 10; /*!< [9..0] Protocol mode */
|
|
|
+ __IOM uint32_t LATEMD : 1; /*!< [10..10] Latency mode */
|
|
|
+ __IOM uint32_t WRMSKMD : 1; /*!< [11..11] Write mask mode */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t CSMIN : 4; /*!< [19..16] CS minimum idle term */
|
|
|
+ __IOM uint32_t CSASTEX : 1; /*!< [20..20] CS asserting extension */
|
|
|
+ __IOM uint32_t CSNEGEX : 1; /*!< [21..21] CS negating extension */
|
|
|
+ __IOM uint32_t SDRDRV : 1; /*!< [22..22] SDR driving timing */
|
|
|
+ __IOM uint32_t SDRSMPMD : 1; /*!< [23..23] SDR Sampling mode */
|
|
|
+ __IOM uint32_t SDRSMPSFT : 4; /*!< [27..24] SDR Sampling window shift */
|
|
|
+ __IOM uint32_t DDRSMPEX : 4; /*!< [31..28] DDR sampling window extend */
|
|
|
+ } LIOCFGCS_b[2];
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t ABMCFG; /*!< (@ 0x00000058) xSPI AXI Bridge Map Config */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t ODRMD : 2; /*!< [1..0] AXI Transfer Ordering Mode */
|
|
|
+ uint32_t : 14;
|
|
|
+ __IOM uint32_t CHSEL : 16; /*!< [31..16] AXI ID to Bridge Channel Select */
|
|
|
+ } ABMCFG_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED1;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t BMCTL0; /*!< (@ 0x00000060) xSPI Bridge Map Control register 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CH0CS0ACC : 2; /*!< [1..0] System bus ch0 to slave0 memory area access enable */
|
|
|
+ __IOM uint32_t CH0CS1ACC : 2; /*!< [3..2] System bus ch0 to slave1 memory area access enable */
|
|
|
+ __IOM uint32_t CH1CS0ACC : 2; /*!< [5..4] System bus ch1 to slave0 memory area access enable */
|
|
|
+ __IOM uint32_t CH1CS1ACC : 2; /*!< [7..6] System bus ch1 to slave1 memory area access enable */
|
|
|
+ uint32_t : 24;
|
|
|
+ } BMCTL0_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __OM uint32_t BMCTL1; /*!< (@ 0x00000064) xSPI Bridge Map Control register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 8;
|
|
|
+ __OM uint32_t MWRPUSHCH0 : 1; /*!< [8..8] Memory Write Data Push for ch0 */
|
|
|
+ __OM uint32_t MWRPUSHCH1 : 1; /*!< [9..9] Memory Write Data Push for ch1 */
|
|
|
+ __OM uint32_t PBUFCLRCH0 : 1; /*!< [10..10] Prefetch Buffer clear for ch0 */
|
|
|
+ __OM uint32_t PBUFCLRCH1 : 1; /*!< [11..11] Prefetch Buffer clear for ch1 */
|
|
|
+ uint32_t : 20;
|
|
|
+ } BMCTL1_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CMCTLCH[2]; /*!< (@ 0x00000068) xSPI Command Map Control register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t XIPENCODE : 8; /*!< [7..0] XiP mode enter code */
|
|
|
+ __IOM uint32_t XIPEXCODE : 8; /*!< [15..8] XiP mode exit code */
|
|
|
+ __IOM uint32_t XIPEN : 1; /*!< [16..16] XiP mode enable */
|
|
|
+ uint32_t : 15;
|
|
|
+ } CMCTLCH_b[2];
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CDCTL0; /*!< (@ 0x00000070) xSPI Command Manual Control register 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t TRREQ : 1; /*!< [0..0] Transaction request */
|
|
|
+ __IOM uint32_t PERMD : 1; /*!< [1..1] Periodic mode */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t CSSEL : 1; /*!< [3..3] Chip select */
|
|
|
+ __IOM uint32_t TRNUM : 2; /*!< [5..4] Transaction number */
|
|
|
+ uint32_t : 10;
|
|
|
+ __IOM uint32_t PERITV : 5; /*!< [20..16] Periodic transaction interval */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t PERREP : 4; /*!< [27..24] Periodic transaction repeat */
|
|
|
+ uint32_t : 4;
|
|
|
+ } CDCTL0_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CDCTL1; /*!< (@ 0x00000074) xSPI Command Manual Control register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t PEREXP : 32; /*!< [31..0] Periodic transaction expected value */
|
|
|
+ } CDCTL1_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CDCTL2; /*!< (@ 0x00000078) xSPI Command Manual Control register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t PERMSK : 32; /*!< [31..0] Periodic transaction masked value */
|
|
|
+ } CDCTL2_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED2;
|
|
|
+ __IOM R_XSPI_CDBUF_Type CDBUF[4]; /*!< (@ 0x00000080) xSPI BUF register */
|
|
|
+ __IM uint32_t RESERVED3[16];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t LPCTL0; /*!< (@ 0x00000100) xSPI Link Pattern Control register 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t PATREQ : 1; /*!< [0..0] Pattern request */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t CSSEL : 1; /*!< [3..3] Chip select */
|
|
|
+ __IOM uint32_t XDPIN : 2; /*!< [5..4] XiP Disable pattern pin */
|
|
|
+ uint32_t : 10;
|
|
|
+ __IOM uint32_t XD1LEN : 5; /*!< [20..16] XiP Disable pattern 1st phase length */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t XD1VAL : 1; /*!< [23..23] XiP Disable pattern 1st phase value */
|
|
|
+ __IOM uint32_t XD2LEN : 5; /*!< [28..24] XiP Disable pattern 2nd phase length */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t XD2VAL : 1; /*!< [31..31] XiP Disable pattern 2nd phase value */
|
|
|
+ } LPCTL0_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t LPCTL1; /*!< (@ 0x00000104) xSPI Link Pattern Control register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t PATREQ : 2; /*!< [1..0] Pattern request */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t CSSEL : 1; /*!< [3..3] Chip select */
|
|
|
+ __IOM uint32_t RSTREP : 2; /*!< [5..4] Reset pattern repeat */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t RSTWID : 3; /*!< [10..8] Reset pattern width */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t RSTSU : 3; /*!< [14..12] Reset pattern data output setup time */
|
|
|
+ uint32_t : 17;
|
|
|
+ } LPCTL1_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t LIOCTL; /*!< (@ 0x00000108) xSPI Link I/O Control register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t WPCS0 : 1; /*!< [0..0] WP drive for slave 0 */
|
|
|
+ __IOM uint32_t WPCS1 : 1; /*!< [1..1] WP drive for slave 1 */
|
|
|
+ uint32_t : 14;
|
|
|
+ __IOM uint32_t RSTCS0 : 1; /*!< [16..16] Reset drive for slave 0 */
|
|
|
+ __IOM uint32_t RSTCS1 : 1; /*!< [17..17] Reset drive for slave 1 */
|
|
|
+ uint32_t : 14;
|
|
|
+ } LIOCTL_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED4[9];
|
|
|
+ __IOM R_XSPI_CCCTLCS_Type CCCTLCS[2]; /*!< (@ 0x00000130) xSPI CS register */
|
|
|
+ __IM uint32_t RESERVED5[4];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t VERSTT; /*!< (@ 0x00000180) xSPI Version register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t VER : 32; /*!< [31..0] Version */
|
|
|
+ } VERSTT_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t COMSTT; /*!< (@ 0x00000184) xSPI Common Status register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t MEMACCCH0 : 1; /*!< [0..0] Memory access ongoing from ch0 */
|
|
|
+ __IM uint32_t MEMACCCH1 : 1; /*!< [1..1] Memory access ongoing from ch1 */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IM uint32_t PBUFNECH0 : 1; /*!< [4..4] Prefetch Buffer Not Empty for ch0 */
|
|
|
+ __IM uint32_t PBUFNECH1 : 1; /*!< [5..5] Prefetch Buffer Not Empty for ch1 */
|
|
|
+ __IM uint32_t WRBUFNECH0 : 1; /*!< [6..6] Write Buffer Not Empty for ch0 */
|
|
|
+ __IM uint32_t WRBUFNECH1 : 1; /*!< [7..7] Write Buffer Not Empty for ch1 */
|
|
|
+ uint32_t : 8;
|
|
|
+ __IM uint32_t ECSCS0 : 1; /*!< [16..16] ECS monitor for slave0 */
|
|
|
+ __IM uint32_t INTCS0 : 1; /*!< [17..17] INT monitor for slave0 */
|
|
|
+ __IM uint32_t RSTOCS0 : 1; /*!< [18..18] RSTO monitor for slave0 */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IM uint32_t ECSCS1 : 1; /*!< [20..20] ECS monitor for slave1 */
|
|
|
+ __IM uint32_t INTCS1 : 1; /*!< [21..21] INT monitor for slave1 */
|
|
|
+ __IM uint32_t RSTOCS1 : 1; /*!< [22..22] RSTO monitor for slave1 */
|
|
|
+ uint32_t : 9;
|
|
|
+ } COMSTT_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t CASTTCS[2]; /*!< (@ 0x00000188) xSPI Calibration Status register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t CASUC : 32; /*!< [31..0] Calibration Success */
|
|
|
+ } CASTTCS_b[2];
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t INTS; /*!< (@ 0x00000190) xSPI Interrupt Status register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t CMDCMP : 1; /*!< [0..0] Command Completed */
|
|
|
+ __IM uint32_t PATCMP : 1; /*!< [1..1] Pattern Completed */
|
|
|
+ __IM uint32_t INICMP : 1; /*!< [2..2] Initial Sequence Completed */
|
|
|
+ __IM uint32_t PERTO : 1; /*!< [3..3] Periodic transaction timeout */
|
|
|
+ __IM uint32_t DSTOCS0 : 1; /*!< [4..4] DS timeout for slave0 */
|
|
|
+ __IM uint32_t DSTOCS1 : 1; /*!< [5..5] DS timeout for slave1 */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IM uint32_t ECSCS0 : 1; /*!< [8..8] ECC error detection for slave0 */
|
|
|
+ __IM uint32_t ECSCS1 : 1; /*!< [9..9] ECC error detection for slave1 */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IM uint32_t INTCS0 : 1; /*!< [12..12] Interrupt detection for slave0 */
|
|
|
+ __IM uint32_t INTCS1 : 1; /*!< [13..13] Interrupt detection for slave1 */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IM uint32_t BRGOFCH0 : 1; /*!< [16..16] Bridge Buffer overflow for CH0 */
|
|
|
+ __IM uint32_t BRGOFCH1 : 1; /*!< [17..17] Bridge Buffer overflow for CH1 */
|
|
|
+ __IM uint32_t BRGUFCH0 : 1; /*!< [18..18] Bridge Buffer underflow for CH0 */
|
|
|
+ __IM uint32_t BRGUFCH1 : 1; /*!< [19..19] Bridge Buffer underflow for CH1 */
|
|
|
+ __IM uint32_t BUSERRCH0 : 1; /*!< [20..20] AHB bus error for CH0 */
|
|
|
+ __IM uint32_t BUSERRCH1 : 1; /*!< [21..21] AHB bus error for CH1 */
|
|
|
+ uint32_t : 6;
|
|
|
+ __IM uint32_t CAFAILCS0 : 1; /*!< [28..28] Calibration failed for slave0 */
|
|
|
+ __IM uint32_t CAFAILCS1 : 1; /*!< [29..29] Calibration failed for slave1 */
|
|
|
+ __IM uint32_t CASUCCS0 : 1; /*!< [30..30] Calibration success for slave0 */
|
|
|
+ __IM uint32_t CASUCCS1 : 1; /*!< [31..31] Calibration success for slave1 */
|
|
|
+ } INTS_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __OM uint32_t INTC; /*!< (@ 0x00000194) xSPI Interrupt Clear register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __OM uint32_t CMDCMPC : 1; /*!< [0..0] Command Completed interrupt clear */
|
|
|
+ __OM uint32_t PATCMPC : 1; /*!< [1..1] Pattern Completed interrupt clear */
|
|
|
+ __OM uint32_t INICMPC : 1; /*!< [2..2] Initial Sequence Completed interrupt clear */
|
|
|
+ __OM uint32_t PERTOC : 1; /*!< [3..3] Periodic transaction timeout interrupt clear */
|
|
|
+ __OM uint32_t DSTOCS0C : 1; /*!< [4..4] DS timeout for slave0 interrupt clear */
|
|
|
+ __OM uint32_t DSTOCS1C : 1; /*!< [5..5] DS timeout for slave1 interrupt clear */
|
|
|
+ uint32_t : 2;
|
|
|
+ __OM uint32_t ECSCS0C : 1; /*!< [8..8] ECC error detection for slave0 interrupt clear */
|
|
|
+ __OM uint32_t ECSCS1C : 1; /*!< [9..9] ECC error detection for slave1 interrupt clear */
|
|
|
+ uint32_t : 2;
|
|
|
+ __OM uint32_t INTCS0C : 1; /*!< [12..12] Interrupt detection for slave0 interrupt clear */
|
|
|
+ __OM uint32_t INTCS1C : 1; /*!< [13..13] Interrupt detection for slave1 interrupt clear */
|
|
|
+ uint32_t : 2;
|
|
|
+ __OM uint32_t BRGOFCH0C : 1; /*!< [16..16] Bridge Buffer overflow for CH0 interrupt clear */
|
|
|
+ __OM uint32_t BRGOFCH1C : 1; /*!< [17..17] Bridge Buffer overflow for CH1 interrupt clear */
|
|
|
+ __OM uint32_t BRGUFCH0C : 1; /*!< [18..18] Bridge Buffer underflow for CH0 interrupt clear */
|
|
|
+ __OM uint32_t BRGUFCH1C : 1; /*!< [19..19] Bridge Buffer underflow for CH1 interrupt clear */
|
|
|
+ __OM uint32_t BUSERRCH0C : 1; /*!< [20..20] AHB bus error for CH0 interrupt clear */
|
|
|
+ __OM uint32_t BUSERRCH1C : 1; /*!< [21..21] AHB bus error for CH1 interrupt clear */
|
|
|
+ uint32_t : 6;
|
|
|
+ __OM uint32_t CAFAILCS0C : 1; /*!< [28..28] Calibration failed for slave0 interrupt clear */
|
|
|
+ __OM uint32_t CAFAILCS1C : 1; /*!< [29..29] Calibration failed for slave1 interrupt clear */
|
|
|
+ __OM uint32_t CASUCCS0C : 1; /*!< [30..30] Calibration success for slave0 interrupt clear */
|
|
|
+ __OM uint32_t CASUCCS1C : 1; /*!< [31..31] Calibration success for slave1 interrupt clear */
|
|
|
+ } INTC_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t INTE; /*!< (@ 0x00000198) xSPI Interrupt Enable register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CMDCMPE : 1; /*!< [0..0] Command Completed interrupt enable */
|
|
|
+ __IOM uint32_t PATCMPE : 1; /*!< [1..1] Pattern Completed interrupt enable */
|
|
|
+ __IOM uint32_t INICMPE : 1; /*!< [2..2] Initial Sequence Completed interrupt enable */
|
|
|
+ __IOM uint32_t PERTOE : 1; /*!< [3..3] Periodic transaction timeout interrupt enable */
|
|
|
+ __IOM uint32_t DSTOCS0E : 1; /*!< [4..4] DS timeout for slave0 interrupt enable */
|
|
|
+ __IOM uint32_t DSTOCS1E : 1; /*!< [5..5] DS timeout for slave1 interrupt enable */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t ECSCS0E : 1; /*!< [8..8] ECC error detection for slave0 interrupt enable */
|
|
|
+ __IOM uint32_t ECSCS1E : 1; /*!< [9..9] ECC error detection for slave1 interrupt enable */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t INTCS0E : 1; /*!< [12..12] Interrupt detection for slave0 interrupt enable */
|
|
|
+ __IOM uint32_t INTCS1E : 1; /*!< [13..13] Interrupt detection for slave1 interrupt enable */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t BRGOFCH0E : 1; /*!< [16..16] Bridge Buffer overflow for CH0 interrupt enable */
|
|
|
+ __IOM uint32_t BRGOFCH1E : 1; /*!< [17..17] Bridge Buffer overflow for CH1 interrupt enable */
|
|
|
+ __IOM uint32_t BRGUFCH0E : 1; /*!< [18..18] Bridge Buffer underflow for CH0 interrupt enable */
|
|
|
+ __IOM uint32_t BRGUFCH1E : 1; /*!< [19..19] Bridge Buffer underflow for CH1 interrupt enable */
|
|
|
+ __IOM uint32_t BUSERRCH0E : 1; /*!< [20..20] AHB bus error for CH0 interrupt enable */
|
|
|
+ __IOM uint32_t BUSERRCH1E : 1; /*!< [21..21] AHB bus error for CH1 interrupt enable */
|
|
|
+ uint32_t : 6;
|
|
|
+ __IOM uint32_t CAFAILCS0E : 1; /*!< [28..28] Calibration failed for slave0 interrupt enable */
|
|
|
+ __IOM uint32_t CAFAILCS1E : 1; /*!< [29..29] Calibration failed for slave1 interrupt enable */
|
|
|
+ __IOM uint32_t CASUCCS0E : 1; /*!< [30..30] Calibration success for slave0 interrupt enable */
|
|
|
+ __IOM uint32_t CASUCCS1E : 1; /*!< [31..31] Calibration success for slave1 interrupt enable */
|
|
|
+ } INTE_b;
|
|
|
+ };
|
|
|
+} R_XSPI_Type; /*!< Size = 412 (0x19c) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_CEU ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Capture Engine Unit (R_CEU)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x40348000) R_CEU Structure */
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CAPSR; /*!< (@ 0x00000000) Capture Start Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CE : 1; /*!< [0..0] Capture enable */
|
|
|
+ uint32_t : 15;
|
|
|
+ __IOM uint32_t CPKIL : 1; /*!< [16..16] Write 1 to this bit to perform a software reset of
|
|
|
+ * capturing. */
|
|
|
+ uint32_t : 15;
|
|
|
+ } CAPSR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CAPCR; /*!< (@ 0x00000004) Capture Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 16;
|
|
|
+ __IOM uint32_t CTNCP : 1; /*!< [16..16] When capturing is started with this bit set to 1, capturing
|
|
|
+ * continues until the CE bit in CAPSR is cleared to 0 or
|
|
|
+ * a software reset is initiated by the CPKIL bit in CAPSR
|
|
|
+ * (see ). Continuous capture must be set before capturing
|
|
|
+ * is started. */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t MTCM : 2; /*!< [21..20] Specify the unit for transferring data to a bus bridge
|
|
|
+ * module. */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t FDRP : 8; /*!< [31..24] Set the frame drop interval in continuous-frame capture. */
|
|
|
+ } CAPCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CAMCR; /*!< (@ 0x00000008) Capture interface control register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t HDPOL : 1; /*!< [0..0] Sets the polarity for detection of the horizontal sync
|
|
|
+ * signal input from an external module. */
|
|
|
+ __IOM uint32_t VDPOL : 1; /*!< [1..1] Sets the polarity for detection of the vertical sync
|
|
|
+ * signal input from an external module. */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t JPG : 2; /*!< [5..4] These bits select the fetched data type. */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t DTARY : 2; /*!< [9..8] Set the input order of the luminance component and chrominance
|
|
|
+ * component. */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t DTIF : 1; /*!< [12..12] Sets the digital image input pins from which data is
|
|
|
+ * to be captured. */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t FLDPOL : 1; /*!< [16..16] Sets the polarity of the field identification signal
|
|
|
+ * (FLD) from an external module. */
|
|
|
+ uint32_t : 7;
|
|
|
+ __IOM uint32_t DSEL : 1; /*!< [24..24] Sets the edge for fetching the image data (D7 to D0)
|
|
|
+ * from an external module. */
|
|
|
+ __IOM uint32_t FLDSEL : 1; /*!< [25..25] Sets the edge for capturing the field identification
|
|
|
+ * signal (FLD) from an external module. */
|
|
|
+ __IOM uint32_t HDSEL : 1; /*!< [26..26] Sets the edge for capturing the horizontal sync signal
|
|
|
+ * (HD) from an external module. */
|
|
|
+ __IOM uint32_t VDSEL : 1; /*!< [27..27] Sets the edge for capturing the vertical sync signal
|
|
|
+ * (VD) from an external module. */
|
|
|
+ uint32_t : 4;
|
|
|
+ } CAMCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CMCYR; /*!< (@ 0x0000000C) Capture Interface Cycle Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t HCYL : 14; /*!< [13..0] Horizontal Cycle Count of External Module */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t VCYL : 14; /*!< [29..16] Vertical HD Count of External Module */
|
|
|
+ uint32_t : 2;
|
|
|
+ } CMCYR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CAMOR; /*!< (@ 0x00000010) Capture Interface Offset Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t HOFST : 13; /*!< [12..0] Specify the capture start location in terms of the number
|
|
|
+ * of clock cycles from a horizontal sync signal (1-cycle
|
|
|
+ * units). */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t VOFST : 12; /*!< [27..16] Specify the capture start location in terms of the
|
|
|
+ * HD count from a vertical sync signal (1-HD units). */
|
|
|
+ uint32_t : 4;
|
|
|
+ } CAMOR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CAPWR; /*!< (@ 0x00000014) Capture Interface Width Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t HWDTH : 13; /*!< [12..0] Specify the horizontal capture period. */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t VWDTH : 12; /*!< [27..16] Specify the vertical capture period (4-HD units). */
|
|
|
+ uint32_t : 4;
|
|
|
+ } CAPWR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CAIFR; /*!< (@ 0x00000018) Capture Interface Input Format Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t FCI : 2; /*!< [1..0] Set the timing to start capturing. */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t CIM : 1; /*!< [4..4] Sets the images to be captured. */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t IFS : 1; /*!< [8..8] Sets the input mode for capturing images. */
|
|
|
+ uint32_t : 23;
|
|
|
+ } CAIFR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED[3];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CRCNTR; /*!< (@ 0x00000028) CEU Register Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t RC : 1; /*!< [0..0] Specifies switching of the register plane used by the
|
|
|
+ * CEU in synchronization with VD. */
|
|
|
+ __IOM uint32_t RS : 1; /*!< [1..1] Specifies which register plane is used by the CEU in
|
|
|
+ * synchronization with VD. */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t RVS : 1; /*!< [4..4] Sets the timing to switch the register plane in both-field
|
|
|
+ * capture. */
|
|
|
+ uint32_t : 27;
|
|
|
+ } CRCNTR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CRCMPR; /*!< (@ 0x0000002C) CEU Register Forcible Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t RA : 1; /*!< [0..0] Indicates the register plane currently specified. */
|
|
|
+ uint32_t : 31;
|
|
|
+ } CRCMPR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFLCR; /*!< (@ 0x00000030) Capture Filter Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t HFRAC : 12; /*!< [11..0] Fraction Part of Horizontal Scale-Down Factor */
|
|
|
+ __IOM uint32_t HMANT : 4; /*!< [15..12] Mantissa Part of Horizontal Scale-Down Factor */
|
|
|
+ __IOM uint32_t VFRAC : 12; /*!< [27..16] Fraction Part of Vertical Scale-Down Factor */
|
|
|
+ __IOM uint32_t VMANT : 4; /*!< [31..28] Mantissa Part of Vertical Scale-Down Factor */
|
|
|
+ } CFLCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFSZR; /*!< (@ 0x00000034) Capture Filter Size Clip Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t HFCLP : 12; /*!< [11..0] Specify the horizontal clipping value of the filter
|
|
|
+ * output size (4-pixel units). */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t VFCLP : 12; /*!< [27..16] Set the vertical clipping value of the filter output
|
|
|
+ * size (4-pixel units). */
|
|
|
+ uint32_t : 4;
|
|
|
+ } CFSZR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CDWDR; /*!< (@ 0x00000038) Capture Destination Width Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CHDW : 13; /*!< [12..0] Specify the horizontal image size in the memory area
|
|
|
+ * where the captured image is to be stored (4-byte units). */
|
|
|
+ uint32_t : 19;
|
|
|
+ } CDWDR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CDAYR; /*!< (@ 0x0000003C) Capture Data Address Y Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CAYR : 32; /*!< [31..0] Capture Data Address Y */
|
|
|
+ } CDAYR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CDACR; /*!< (@ 0x00000040) Capture Data Address C Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CACR : 32; /*!< [31..0] Capture Data Address C */
|
|
|
+ } CDACR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CDBYR; /*!< (@ 0x00000044) Capture Data Bottom-Field Address Y Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CBYR : 32; /*!< [31..0] Set the address for storing the Y (luminance) component
|
|
|
+ * data of the captured bottom-field data (4-pixel units). */
|
|
|
+ } CDBYR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CDBCR; /*!< (@ 0x00000048) Capture Data Bottom-Field Address C Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CBCR : 32; /*!< [31..0] Set the address for storing the C (chrominance) component
|
|
|
+ * data of the captured bottom-field data (4-pixel units). */
|
|
|
+ } CDBCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CBDSR; /*!< (@ 0x0000004C) Capture Bundle Destination Size Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CBVS : 23; /*!< [22..0] Select the number of lines or number of bytes for output
|
|
|
+ * to the memory in a bundle write. */
|
|
|
+ uint32_t : 9;
|
|
|
+ } CBDSR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED1[3];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFWCR; /*!< (@ 0x0000005C) Firewall Operation Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t FWE : 1; /*!< [0..0] With the setting of FWE = 1, when an address exceeds
|
|
|
+ * the value set with FWV, the address is retained and an
|
|
|
+ * interrupt source FWF is set. After this, the address is
|
|
|
+ * not incremented and data is overwritten on the upper limit
|
|
|
+ * address. */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t FWV : 27; /*!< [31..5] Specify the upper limit of a write address. */
|
|
|
+ } CFWCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CLFCR; /*!< (@ 0x00000060) Capture Low-Pass Filter Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t LPF : 1; /*!< [0..0] Enables or disables operation of the low-pass filter. */
|
|
|
+ uint32_t : 31;
|
|
|
+ } CLFCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CDOCR; /*!< (@ 0x00000064) Capture Data Output Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t COBS : 1; /*!< [0..0] Controls swapping in 8-bit units for data output from
|
|
|
+ * the CEU. */
|
|
|
+ __IOM uint32_t COWS : 1; /*!< [1..1] Controls swapping in 16-bit units for data output from
|
|
|
+ * the CEU. */
|
|
|
+ __IOM uint32_t COLS : 1; /*!< [2..2] Controls swapping in 32-bit units for data output from
|
|
|
+ * the CEU. */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t CDS : 1; /*!< [4..4] Sets the image format when outputting the image data
|
|
|
+ * captured in the YCbCr422 format to the memory. */
|
|
|
+ uint32_t : 11;
|
|
|
+ __IOM uint32_t CBE : 1; /*!< [16..16] Controls the number of lines of captured data to be
|
|
|
+ * written to the memory. */
|
|
|
+ uint32_t : 15;
|
|
|
+ } CDOCR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED2[2];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CEIER; /*!< (@ 0x00000070) Capture Event Interrupt Enable Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CPEIE : 1; /*!< [0..0] One-Frame Capture End Interrupt Enable */
|
|
|
+ __IOM uint32_t CFEIE : 1; /*!< [1..1] CFE Interrupt Enable */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t IGRWIE : 1; /*!< [4..4] Register-Access-During-Capture Interrupt Enable */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t HDIE : 1; /*!< [8..8] HD Interrupt Enable */
|
|
|
+ __IOM uint32_t VDIE : 1; /*!< [9..9] VD Interrupt Enable */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t CPBE1IE : 1; /*!< [12..12] CPBE1 Interrupt Enable */
|
|
|
+ __IOM uint32_t CPBE2IE : 1; /*!< [13..13] CPBE2 Interrupt Enable */
|
|
|
+ __IOM uint32_t CPBE3IE : 1; /*!< [14..14] CPBE3 Interrupt Enable */
|
|
|
+ __IOM uint32_t CPBE4IE : 1; /*!< [15..15] CPBE4 Interrupt Enable */
|
|
|
+ __IOM uint32_t CDTOFIE : 1; /*!< [16..16] CDTOF Interrupt Enable */
|
|
|
+ __IOM uint32_t IGHSIE : 1; /*!< [17..17] IGHS Interrupt Enable */
|
|
|
+ __IOM uint32_t IGVSIE : 1; /*!< [18..18] IGVS Interrupt Enable */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t VBPIE : 1; /*!< [20..20] VBP Interrupt Enable */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t FWFIE : 1; /*!< [23..23] FWF Interrupt Enable */
|
|
|
+ __IOM uint32_t NHDIE : 1; /*!< [24..24] Non-HD Interrupt Enable */
|
|
|
+ __IOM uint32_t NVDIE : 1; /*!< [25..25] Non-VD Interrupt Enable */
|
|
|
+ uint32_t : 6;
|
|
|
+ } CEIER_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CETCR; /*!< (@ 0x00000074) Capture Event Flag Clear Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CPE : 1; /*!< [0..0] An interrupt indicating that capturing of one frame from
|
|
|
+ * an external module has finished. */
|
|
|
+ __IOM uint32_t CFE : 1; /*!< [1..1] An interrupt indicating that capturing of one field from
|
|
|
+ * an external module has finished. */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t IGRW : 1; /*!< [4..4] An interrupt indicating that during capturing, access
|
|
|
+ * was attempted to a register to which writing during operation
|
|
|
+ * is prohibited. */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t HD : 1; /*!< [8..8] An interrupt indicating that HD (horizontal sync signal)
|
|
|
+ * was input from an external module. */
|
|
|
+ __IOM uint32_t VD : 1; /*!< [9..9] An interrupt indicating that VD (vertical sync signal)
|
|
|
+ * was input from an external module. */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t CPBE1 : 1; /*!< [12..12] An interrupt indicating that writing to CDAYR and CDACR
|
|
|
+ * in a bundle write has finished. */
|
|
|
+ __IOM uint32_t CPBE2 : 1; /*!< [13..13] An interrupt indicating that writing to CDAYR2 and
|
|
|
+ * CDACR2 in a bundle write has finished. */
|
|
|
+ __IOM uint32_t CPBE3 : 1; /*!< [14..14] An interrupt indicating that writing to CDBYR and CDBCR
|
|
|
+ * in a bundle write has finished. */
|
|
|
+ __IOM uint32_t CPBE4 : 1; /*!< [15..15] An interrupt indicating that writing to CDBYR2 and
|
|
|
+ * CDBCR2 in a bundle write has finished. */
|
|
|
+ __IOM uint32_t CDTOF : 1; /*!< [16..16] An interrupt indicating that data overflowed in the
|
|
|
+ * CRAM of the write buffer */
|
|
|
+ __IOM uint32_t IGHS : 1; /*!< [17..17] An interrupt generated when the number of HD cycles
|
|
|
+ * set in CMCYR differ from the number of HD cycles input
|
|
|
+ * from an external module. */
|
|
|
+ __IOM uint32_t IGVS : 1; /*!< [18..18] An interrupt generated when the number of VD cycles
|
|
|
+ * set in CMCYR differ from the number of VD cycles input
|
|
|
+ * from an external module. */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t VBP : 1; /*!< [20..20] An interrupt indicating that VD has been input while
|
|
|
+ * the CEU holds data (insufficient vertical-sync front porch). */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t FWF : 1; /*!< [23..23] The interrupt is generated when data is written to
|
|
|
+ * the address that exceeds the value specified with CFWCR.FMV. */
|
|
|
+ __IOM uint32_t NHD : 1; /*!< [24..24] An interrupt indicating that no HD was input. */
|
|
|
+ __IOM uint32_t NVD : 1; /*!< [25..25] An interrupt indicating that no VD was input. */
|
|
|
+ uint32_t : 6;
|
|
|
+ } CETCR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED3;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t CSTSR; /*!< (@ 0x0000007C) Capture Status Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t CPTON : 1; /*!< [0..0] Indicates that the CEU is operating. */
|
|
|
+ uint32_t : 15;
|
|
|
+ __IM uint32_t CPFLD : 1; /*!< [16..16] Indicates which field is being captured. */
|
|
|
+ uint32_t : 7;
|
|
|
+ __IM uint32_t CRST : 1; /*!< [24..24] Indicates which register plane is currently used. */
|
|
|
+ uint32_t : 7;
|
|
|
+ } CSTSR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED4;
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t CDSSR; /*!< (@ 0x00000084) Capture Data Size Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t CDSS : 32; /*!< [31..0] Indicate the size of data written to the memory in data
|
|
|
+ * enable fetch. */
|
|
|
+ } CDSSR_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED5[2];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CDAYR2; /*!< (@ 0x00000090) Capture Data Address Y Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CAYR2 : 32; /*!< [31..0] Capture Data Address Y */
|
|
|
+ } CDAYR2_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CDACR2; /*!< (@ 0x00000094) Capture Data Address C Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CACR2 : 32; /*!< [31..0] Capture Data Address C2 */
|
|
|
+ } CDACR2_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CDBYR2; /*!< (@ 0x00000098) Capture Data Bottom-Field Address Y Register
|
|
|
+ * 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CBYR2 : 32; /*!< [31..0] Set the address for storing the Y component data of
|
|
|
+ * the captured bottom-field data (4-pixel units). */
|
|
|
+ } CDBYR2_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CDBCR2; /*!< (@ 0x0000009C) Capture Data Bottom-Field Address C Register
|
|
|
+ * 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CBCR2 : 32; /*!< [31..0] Set the address for storing the C component data of
|
|
|
+ * the captured bottom-field data (4-pixel units). */
|
|
|
+ } CDBCR2_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t AXIBUSCTL2; /*!< (@ 0x000000A0) AXI Bus Control Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t AWCACHE : 4; /*!< [3..0] AWCACHE[3:0] Signals for Capture Engine Unit */
|
|
|
+ uint32_t : 28;
|
|
|
+ } AXIBUSCTL2_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED6[987];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CAMOR_B; /*!< (@ 0x00001010) Capture Interface Offset Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t HOFST : 13; /*!< [12..0] Specify the capture start location in terms of the number
|
|
|
+ * of clock cycles from a horizontal sync signal (1-cycle
|
|
|
+ * units). */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t VOFST : 12; /*!< [27..16] Specify the capture start location in terms of the
|
|
|
+ * HD count from a vertical sync signal (1-HD units). */
|
|
|
+ uint32_t : 4;
|
|
|
+ } CAMOR_B_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CAPWR_B; /*!< (@ 0x00001014) Capture Interface Width Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t HWDTH : 13; /*!< [12..0] Specify the horizontal capture period. */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t VWDTH : 12; /*!< [27..16] Specify the vertical capture period (4-HD units). */
|
|
|
+ uint32_t : 4;
|
|
|
+ } CAPWR_B_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED7[6];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFLCR_B; /*!< (@ 0x00001030) Capture Filter Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t HFRAC : 12; /*!< [11..0] Fraction Part of Horizontal Scale-Down Factor */
|
|
|
+ __IOM uint32_t HMANT : 4; /*!< [15..12] Mantissa Part of Horizontal Scale-Down Factor */
|
|
|
+ __IOM uint32_t VFRAC : 12; /*!< [27..16] Fraction Part of Vertical Scale-Down Factor */
|
|
|
+ __IOM uint32_t VMANT : 4; /*!< [31..28] Mantissa Part of Vertical Scale-Down Factor */
|
|
|
+ } CFLCR_B_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFSZR_B; /*!< (@ 0x00001034) Capture Filter Size Clip Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t HFCLP : 12; /*!< [11..0] Specify the horizontal clipping value of the filter
|
|
|
+ * output size (4-pixel units). */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t VFCLP : 12; /*!< [27..16] Set the vertical clipping value of the filter output
|
|
|
+ * size (4-pixel units). */
|
|
|
+ uint32_t : 4;
|
|
|
+ } CFSZR_B_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CDWDR_B; /*!< (@ 0x00001038) Capture Destination Width Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CHDW : 13; /*!< [12..0] Specify the horizontal image size in the memory area
|
|
|
+ * where the captured image is to be stored (4-byte units). */
|
|
|
+ uint32_t : 19;
|
|
|
+ } CDWDR_B_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CDAYR_B; /*!< (@ 0x0000103C) Capture Data Address Y Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CAYR : 32; /*!< [31..0] Capture Data Address Y */
|
|
|
+ } CDAYR_B_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CDACR_B; /*!< (@ 0x00001040) Capture Data Address C Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CACR : 32; /*!< [31..0] Capture Data Address C */
|
|
|
+ } CDACR_B_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CDBYR_B; /*!< (@ 0x00001044) Capture Data Bottom-Field Address Y Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CBYR : 32; /*!< [31..0] Set the address for storing the Y (luminance) component
|
|
|
+ * data of the captured bottom-field data (4-pixel units). */
|
|
|
+ } CDBYR_B_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CDBCR_B; /*!< (@ 0x00001048) Capture Data Bottom-Field Address C Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CBCR : 32; /*!< [31..0] Set the address for storing the C (chrominance) component
|
|
|
+ * data of the captured bottom-field data (4-pixel units). */
|
|
|
+ } CDBCR_B_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CBDSR_B; /*!< (@ 0x0000104C) Capture Bundle Destination Size Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CBVS : 23; /*!< [22..0] Select the number of lines or number of bytes for output
|
|
|
+ * to the memory in a bundle write. */
|
|
|
+ uint32_t : 9;
|
|
|
+ } CBDSR_B_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED8[4];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CLFCR_B; /*!< (@ 0x00001060) Capture Low-Pass Filter Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t LPF : 1; /*!< [0..0] Enables or disables operation of the low-pass filter. */
|
|
|
+ uint32_t : 31;
|
|
|
+ } CLFCR_B_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CDOCR_B; /*!< (@ 0x00001064) Capture Data Output Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t COBS : 1; /*!< [0..0] Controls swapping in 8-bit units for data output from
|
|
|
+ * the CEU. */
|
|
|
+ __IOM uint32_t COWS : 1; /*!< [1..1] Controls swapping in 16-bit units for data output from
|
|
|
+ * the CEU. */
|
|
|
+ __IOM uint32_t COLS : 1; /*!< [2..2] Controls swapping in 32-bit units for data output from
|
|
|
+ * the CEU. */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t CDS : 1; /*!< [4..4] Sets the image format when outputting the image data
|
|
|
+ * captured in the YCbCr422 format to the memory. */
|
|
|
+ uint32_t : 11;
|
|
|
+ __IOM uint32_t CBE : 1; /*!< [16..16] Controls the number of lines of captured data to be
|
|
|
+ * written to the memory. */
|
|
|
+ uint32_t : 15;
|
|
|
+ } CDOCR_B_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED9[10];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CDAYR2_B; /*!< (@ 0x00001090) Capture Data Address Y Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CAYR2 : 32; /*!< [31..0] Capture Data Address Y */
|
|
|
+ } CDAYR2_B_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CDACR2_B; /*!< (@ 0x00001094) Capture Data Address C Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CACR2 : 32; /*!< [31..0] Capture Data Address C2 */
|
|
|
+ } CDACR2_B_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CDBYR2_B; /*!< (@ 0x00001098) Capture Data Bottom-Field Address Y Register
|
|
|
+ * 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CBYR2 : 32; /*!< [31..0] Set the address for storing the Y component data of
|
|
|
+ * the captured bottom-field data (4-pixel units). */
|
|
|
+ } CDBYR2_B_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CDBCR2_B; /*!< (@ 0x0000109C) Capture Data Bottom-Field Address C Register
|
|
|
+ * 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CBCR2 : 32; /*!< [31..0] Set the address for storing the C component data of
|
|
|
+ * the captured bottom-field data (4-pixel units). */
|
|
|
+ } CDBCR2_B_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED10[988];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CAMOR_M; /*!< (@ 0x00002010) Capture Interface Offset Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t HOFST : 13; /*!< [12..0] Specify the capture start location in terms of the number
|
|
|
+ * of clock cycles from a horizontal sync signal (1-cycle
|
|
|
+ * units). */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t VOFST : 12; /*!< [27..16] Specify the capture start location in terms of the
|
|
|
+ * HD count from a vertical sync signal (1-HD units). */
|
|
|
+ uint32_t : 4;
|
|
|
+ } CAMOR_M_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CAPWR_M; /*!< (@ 0x00002014) Capture Interface Width Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t HWDTH : 13; /*!< [12..0] Specify the horizontal capture period. */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t VWDTH : 12; /*!< [27..16] Specify the vertical capture period (4-HD units). */
|
|
|
+ uint32_t : 4;
|
|
|
+ } CAPWR_M_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED11[6];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFLCR_M; /*!< (@ 0x00002030) Capture Filter Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t HFRAC : 12; /*!< [11..0] Fraction Part of Horizontal Scale-Down Factor */
|
|
|
+ __IOM uint32_t HMANT : 4; /*!< [15..12] Mantissa Part of Horizontal Scale-Down Factor */
|
|
|
+ __IOM uint32_t VFRAC : 12; /*!< [27..16] Fraction Part of Vertical Scale-Down Factor */
|
|
|
+ __IOM uint32_t VMANT : 4; /*!< [31..28] Mantissa Part of Vertical Scale-Down Factor */
|
|
|
+ } CFLCR_M_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CFSZR_M; /*!< (@ 0x00002034) Capture Filter Size Clip Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t HFCLP : 12; /*!< [11..0] Specify the horizontal clipping value of the filter
|
|
|
+ * output size (4-pixel units). */
|
|
|
+ uint32_t : 4;
|
|
|
+ __IOM uint32_t VFCLP : 12; /*!< [27..16] Set the vertical clipping value of the filter output
|
|
|
+ * size (4-pixel units). */
|
|
|
+ uint32_t : 4;
|
|
|
+ } CFSZR_M_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CDWDR_M; /*!< (@ 0x00002038) Capture Destination Width Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CHDW : 13; /*!< [12..0] Specify the horizontal image size in the memory area
|
|
|
+ * where the captured image is to be stored (4-byte units). */
|
|
|
+ uint32_t : 19;
|
|
|
+ } CDWDR_M_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CDAYR_M; /*!< (@ 0x0000203C) Capture Data Address Y Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CAYR : 32; /*!< [31..0] Capture Data Address Y */
|
|
|
+ } CDAYR_M_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CDACR_M; /*!< (@ 0x00002040) Capture Data Address C Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CACR : 32; /*!< [31..0] Capture Data Address C */
|
|
|
+ } CDACR_M_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CDBYR_M; /*!< (@ 0x00002044) Capture Data Bottom-Field Address Y Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CBYR : 32; /*!< [31..0] Set the address for storing the Y (luminance) component
|
|
|
+ * data of the captured bottom-field data (4-pixel units). */
|
|
|
+ } CDBYR_M_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CDBCR_M; /*!< (@ 0x00002048) Capture Data Bottom-Field Address C Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CBCR : 32; /*!< [31..0] Set the address for storing the C (chrominance) component
|
|
|
+ * data of the captured bottom-field data (4-pixel units). */
|
|
|
+ } CDBCR_M_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CBDSR_M; /*!< (@ 0x0000204C) Capture Bundle Destination Size Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CBVS : 23; /*!< [22..0] Select the number of lines or number of bytes for output
|
|
|
+ * to the memory in a bundle write. */
|
|
|
+ uint32_t : 9;
|
|
|
+ } CBDSR_M_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED12[4];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CLFCR_M; /*!< (@ 0x00002060) Capture Low-Pass Filter Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t LPF : 1; /*!< [0..0] Enables or disables operation of the low-pass filter. */
|
|
|
+ uint32_t : 31;
|
|
|
+ } CLFCR_M_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CDOCR_M; /*!< (@ 0x00002064) Capture Data Output Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t COBS : 1; /*!< [0..0] Controls swapping in 8-bit units for data output from
|
|
|
+ * the CEU. */
|
|
|
+ __IOM uint32_t COWS : 1; /*!< [1..1] Controls swapping in 16-bit units for data output from
|
|
|
+ * the CEU. */
|
|
|
+ __IOM uint32_t COLS : 1; /*!< [2..2] Controls swapping in 32-bit units for data output from
|
|
|
+ * the CEU. */
|
|
|
+ uint32_t : 1;
|
|
|
+ __IOM uint32_t CDS : 1; /*!< [4..4] Sets the image format when outputting the image data
|
|
|
+ * captured in the YCbCr422 format to the memory. */
|
|
|
+ uint32_t : 11;
|
|
|
+ __IOM uint32_t CBE : 1; /*!< [16..16] Controls the number of lines of captured data to be
|
|
|
+ * written to the memory. */
|
|
|
+ uint32_t : 15;
|
|
|
+ } CDOCR_M_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED13[10];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CDAYR2_M; /*!< (@ 0x00002090) Capture Data Address Y Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CAYR2 : 32; /*!< [31..0] Capture Data Address Y */
|
|
|
+ } CDAYR2_M_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CDACR2_M; /*!< (@ 0x00002094) Capture Data Address C Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CACR2 : 32; /*!< [31..0] Capture Data Address C2 */
|
|
|
+ } CDACR2_M_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CDBYR2_M; /*!< (@ 0x00002098) Capture Data Bottom-Field Address Y Register
|
|
|
+ * 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CBYR2 : 32; /*!< [31..0] Set the address for storing the Y component data of
|
|
|
+ * the captured bottom-field data (4-pixel units). */
|
|
|
+ } CDBYR2_M_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CDBCR2_M; /*!< (@ 0x0000209C) Capture Data Bottom-Field Address C Register
|
|
|
+ * 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t CBCR2 : 32; /*!< [31..0] Set the address for storing the C component data of
|
|
|
+ * the captured bottom-field data (4-pixel units). */
|
|
|
+ } CDBCR2_M_b;
|
|
|
+ };
|
|
|
+} R_CEU_Type; /*!< Size = 8352 (0x20a0) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_ULPT0 ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Ultra-Low Power Timer 0 (R_ULPT0)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x40220000) R_ULPT0 Structure */
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t ULPTCNT; /*!< (@ 0x00000000) ULPT Counter Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t ULPTCNT : 32; /*!< [31..0] 32bit counter and reload registerNOTE : When 1 is written
|
|
|
+ * to the TSTOP bit in the ULPTCR register, the 32-bit counter
|
|
|
+ * is forcibly stopped and set to FFFFFFFFH. */
|
|
|
+ } ULPTCNT_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t ULPTCMA; /*!< (@ 0x00000004) ULPT Compare Match A Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t ULPTCMA : 32; /*!< [31..0] ULPT Compare Match A RegisterNOTE : When 1 is written
|
|
|
+ * to the TSTOP bit in the ULPTCR register, set to FFFFFFFFH */
|
|
|
+ } ULPTCMA_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t ULPTCMB; /*!< (@ 0x00000008) ULPT Compare Match B Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t ULPTCMB : 32; /*!< [31..0] AGT Compare Match B RegisterNOTE : When 1 is written
|
|
|
+ * to the TSTOP bit in the ULPTCR register, set to FFFFFFFFH */
|
|
|
+ } ULPTCMB_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ULPTCR; /*!< (@ 0x0000000C) ULPT Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t TSTART : 1; /*!< [0..0] ULPT count start */
|
|
|
+ __IM uint8_t TCSTF : 1; /*!< [1..1] ULPT count status flag */
|
|
|
+ __OM uint8_t TSTOP : 1; /*!< [2..2] ULPT count forced stop */
|
|
|
+ uint8_t : 2;
|
|
|
+ __IOM uint8_t TUNDF : 1; /*!< [5..5] ULPT underflow flag */
|
|
|
+ __IOM uint8_t TCMAF : 1; /*!< [6..6] ULPT compare match A flag */
|
|
|
+ __IOM uint8_t TCMBF : 1; /*!< [7..7] ULPT compare match B flag */
|
|
|
+ } ULPTCR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ULPTMR1; /*!< (@ 0x0000000D) ULPT Mode Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t TMOD1 : 1; /*!< [1..1] ULPT operating mode select */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t TEDGPL : 1; /*!< [3..3] ULPTEVI edge polarity select */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t TCK1 : 1; /*!< [5..5] ULPT count source select */
|
|
|
+ uint8_t : 2;
|
|
|
+ } ULPTMR1_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ULPTMR2; /*!< (@ 0x0000000E) ULPT Mode Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t CKS : 3; /*!< [2..0] fsub/LOCO count source clock frequency division ratio
|
|
|
+ * select */
|
|
|
+ uint8_t : 4;
|
|
|
+ __IOM uint8_t LPM : 1; /*!< [7..7] ULPT Low Power Mode */
|
|
|
+ } ULPTMR2_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ULPTMR3; /*!< (@ 0x0000000F) ULPT Mode Register 3 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t TCNTCTL : 1; /*!< [0..0] ULPT count function select */
|
|
|
+ __IOM uint8_t TEVPOL : 1; /*!< [1..1] ULPTEVI polarity switch */
|
|
|
+ __IOM uint8_t TOPOL : 1; /*!< [2..2] ULPTO polarity select */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t TEECTL : 2; /*!< [5..4] ULPTEE function select */
|
|
|
+ __IOM uint8_t TEEPOL : 2; /*!< [7..6] ULPTEE edge polarity select */
|
|
|
+ } ULPTMR3_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ULPTIOC; /*!< (@ 0x00000010) ULPT I/O Control Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint8_t : 2;
|
|
|
+ __IOM uint8_t TOE : 1; /*!< [2..2] ULPTO output enable */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t TIPF : 2; /*!< [5..4] ULPTEVI input filter select */
|
|
|
+ __IOM uint8_t TIOGT0 : 1; /*!< [6..6] ULPTEVI count control */
|
|
|
+ uint8_t : 1;
|
|
|
+ } ULPTIOC_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ULPTISR; /*!< (@ 0x00000011) ULPT Event Pin Select Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint8_t : 2;
|
|
|
+ __IOM uint8_t RCCPSEL2 : 1; /*!< [2..2] ULPTEE polarty selection */
|
|
|
+ uint8_t : 5;
|
|
|
+ } ULPTISR_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t ULPTCMSR; /*!< (@ 0x00000012) ULPT Compare Match Function Select Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */
|
|
|
+ __IOM uint8_t TOEA : 1; /*!< [1..1] ULPTOA output enable */
|
|
|
+ __IOM uint8_t TOPOLA : 1; /*!< [2..2] ULPTOA polarity select */
|
|
|
+ uint8_t : 1;
|
|
|
+ __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */
|
|
|
+ __IOM uint8_t TOEB : 1; /*!< [5..5] ULPTOB output enable */
|
|
|
+ __IOM uint8_t TOPOLB : 1; /*!< [6..6] ULPTOB polarity select */
|
|
|
+ uint8_t : 1;
|
|
|
+ } ULPTCMSR_b;
|
|
|
+ };
|
|
|
+ __IM uint8_t RESERVED;
|
|
|
+} R_ULPT0_Type; /*!< Size = 20 (0x14) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_DEBUG_OCD ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief On-Chip Debug Function (R_DEBUG_OCD)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x40011000) R_DEBUG_OCD Structure */
|
|
|
+{
|
|
|
+ __IM uint32_t RESERVED[192];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t FSBLSTATM; /*!< (@ 0x00000300) First Stage Boot Loader Status Monitor Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t CS : 1; /*!< [0..0] FSBL completion status. */
|
|
|
+ __IM uint32_t RS : 1; /*!< [1..1] FSBL result status. */
|
|
|
+ uint32_t : 30;
|
|
|
+ } FSBLSTATM_b;
|
|
|
+ };
|
|
|
+} R_DEBUG_OCD_Type; /*!< Size = 772 (0x304) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_DOTF ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Decryption On The Fly (R_DOTF)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x40268800) R_DOTF Structure */
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CONVAREAST; /*!< (@ 0x00000000) DOTF Conversion Area Start Address Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 12;
|
|
|
+ __IOM uint32_t CONVAREAST : 20; /*!< [31..12] First address of decryption processing area */
|
|
|
+ } CONVAREAST_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t CONVAREAD; /*!< (@ 0x00000004) DOTF Conversion Area End Address Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 12;
|
|
|
+ __IOM uint32_t CONVAREAD : 20; /*!< [31..12] End address of decryption processing area */
|
|
|
+ } CONVAREAD_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED[30];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t REG00; /*!< (@ 0x00000080) Register 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ uint32_t : 9;
|
|
|
+ __IOM uint32_t B09 : 1; /*!< [9..9] Bit 09 */
|
|
|
+ uint32_t : 6;
|
|
|
+ __IOM uint32_t B16 : 1; /*!< [16..16] Bit 09 */
|
|
|
+ __IOM uint32_t B17 : 1; /*!< [17..17] Bit 17 */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t B20 : 1; /*!< [20..20] Bit 20 */
|
|
|
+ uint32_t : 3;
|
|
|
+ __IOM uint32_t B24 : 2; /*!< [25..24] Bit24-25 */
|
|
|
+ uint32_t : 2;
|
|
|
+ __IOM uint32_t B28 : 2; /*!< [29..28] Bit28-29 */
|
|
|
+ uint32_t : 2;
|
|
|
+ } REG00_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED1[2];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t REG03; /*!< (@ 0x0000008C) Register 03 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t B00 : 32; /*!< [31..0] Bit 0 */
|
|
|
+ } REG03_b;
|
|
|
+ };
|
|
|
+} R_DOTF_Type; /*!< Size = 144 (0x90) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_AGTX0 ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Asynchronous General Purpose Timer (R_AGTX0)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x40221000) R_AGTX0 Structure */
|
|
|
+{
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM R_AGTX0_AGT32_Type AGT32; /*!< (@ 0x00000000) AGTW (32-bit) peripheral registers */
|
|
|
+ __IOM R_AGTX0_AGT16_Type AGT16; /*!< (@ 0x00000000) AGT (16-bit) peripheral registers */
|
|
|
+ };
|
|
|
+} R_AGTX0_Type; /*!< Size = 20 (0x14) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_FLAD ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Data Flash (R_FLAD)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x4011C000) R_FLAD Structure */
|
|
|
+{
|
|
|
+ __IM uint8_t RESERVED[64];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint8_t FCKMHZ; /*!< (@ 0x00000040) Data Flash Access Frequency Register */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint8_t FCKMHZ : 8; /*!< [7..0] Data Flash Access Frequency Register */
|
|
|
+ } FCKMHZ_b;
|
|
|
+ };
|
|
|
+} R_FLAD_Type; /*!< Size = 65 (0x41) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_OFS_DATAFLASH ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Data Flash Option-Setting Memory (R_OFS_DATAFLASH)
|
|
|
+ */
|
|
|
+
|
|
|
+typedef struct /*!< (@ 0x27030000) R_OFS_DATAFLASH Structure */
|
|
|
+{
|
|
|
+ __IM uint32_t RESERVED[32];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t FSBLCTRL0; /*!< (@ 0x00000080) FSBL Control Register 0 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t FSBLEN : 3; /*!< [2..0] FSBL Enable */
|
|
|
+ __IM uint32_t FSBLSKIPSW : 3; /*!< [5..3] FSBL Skip Enable for Software Reset */
|
|
|
+ __IM uint32_t FSBLSKIPDS : 3; /*!< [8..6] FSBL Skip Enable for Deep Software Standby Reset */
|
|
|
+ __IM uint32_t FSBLCLK : 3; /*!< [11..9] Clock Frequency Selection during FSBL Execution */
|
|
|
+ uint32_t : 20;
|
|
|
+ } FSBLCTRL0_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t FSBLCTRL1; /*!< (@ 0x00000084) FSBL Control Register 1 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t FSBLEXMD : 2; /*!< [1..0] FSBL Execution Mode */
|
|
|
+ uint32_t : 30;
|
|
|
+ } FSBLCTRL1_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IM uint32_t FSBLCTRL2; /*!< (@ 0x00000088) FSBL Control Register 2 */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IM uint32_t PORTPN : 4; /*!< [3..0] FSBL Error Notification Port Pin Number */
|
|
|
+ __IM uint32_t PORTGN : 5; /*!< [8..4] FSBL Error Notification Port Group Name */
|
|
|
+ uint32_t : 23;
|
|
|
+ } FSBLCTRL2_b;
|
|
|
+ };
|
|
|
+ __IOM uint32_t SACC0; /*!< (@ 0x0000008C) Start Address of Code Certification 0 */
|
|
|
+ __IOM uint32_t SACC1; /*!< (@ 0x00000090) Start Address of Code Certification 1 */
|
|
|
+ __IOM uint32_t SAMR; /*!< (@ 0x00000094) Start Address of Measurement Report */
|
|
|
+ __IM uint32_t RESERVED1[178];
|
|
|
+ __IM uint32_t HOEMRTPK; /*!< (@ 0x00000360) Hask of OEM_ROOT_PK */
|
|
|
+ __IM uint32_t RESERVED2[7];
|
|
|
+ __IOM R_OFS_DATAFLASH_CFGDLOCK_Type CFGDLOCK; /*!< (@ 0x00000380) Configuration Data Lock Bits */
|
|
|
+ __IM uint32_t RESERVED3[11];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t ARCLS; /*!< (@ 0x000003C0) Anti-Rollback Counter Lock Setting */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t ARCS_LK : 1; /*!< [0..0] ARC_SEC Lock */
|
|
|
+ __IOM uint16_t ARCNS_LK : 4; /*!< [4..1] ARC_NSEC Lock */
|
|
|
+ __IOM uint16_t ARCBL_LK : 1; /*!< [5..5] ARC_OEMBL Lock */
|
|
|
+ uint16_t : 10;
|
|
|
+ } ARCLS_b;
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint16_t ARCCS; /*!< (@ 0x000003C2) ARCCS */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint16_t CNF_ARCNS : 2; /*!< [1..0] Configuation setting for ARC_NSEC */
|
|
|
+ uint16_t : 14;
|
|
|
+ } ARCCS_b;
|
|
|
+ };
|
|
|
+ __IM uint32_t RESERVED4[291];
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t ARC_SEC[2]; /*!< (@ 0x00000850) Anti-Rollback Counter for Secure Application
|
|
|
+ * n */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t ARC_SEC : 32; /*!< [31..0] ARC_SEC */
|
|
|
+ } ARC_SEC_b[2];
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t ARC_NSEC[8]; /*!< (@ 0x00000858) Anti-Rollback Counter for Non-Secure Application */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t ARC_NSEC : 32; /*!< [31..0] Anti-Rollback Counter for Non-secure Application */
|
|
|
+ } ARC_NSEC_b[8];
|
|
|
+ };
|
|
|
+
|
|
|
+ union
|
|
|
+ {
|
|
|
+ __IOM uint32_t ARC_OEMBL[2]; /*!< (@ 0x00000878) Anti-Rollback Counter for OEMBL */
|
|
|
+
|
|
|
+ struct
|
|
|
+ {
|
|
|
+ __IOM uint32_t ARC_OEMBL : 32; /*!< [31..0] Anti-Rollback Counter for OEM_BL Application */
|
|
|
+ } ARC_OEMBL_b[2];
|
|
|
+ };
|
|
|
+} R_OFS_DATAFLASH_Type; /*!< Size = 2176 (0x880) */
|
|
|
+
|
|
|
+/** @} */ /* End of group Device_Peripheral_peripherals */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ Device Specific Peripheral Address Map ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/** @addtogroup Device_Peripheral_peripheralAddr
|
|
|
+ * @{
|
|
|
+ */
|
|
|
+
|
|
|
+ #if defined(_RA_TZ_NONSECURE)
|
|
|
+ #define BASE_NS_OFFSET (BSP_FEATURE_TZ_NS_OFFSET)
|
|
|
+ #else
|
|
|
+ #define BASE_NS_OFFSET 0U
|
|
|
+ #endif
|
|
|
+
|
|
|
+ #define R_ACMPHS0_BASE (0x40236000UL + BASE_NS_OFFSET)
|
|
|
+ #define R_ACMPHS1_BASE (0x40236100UL + BASE_NS_OFFSET)
|
|
|
+ #define R_ACMPHS2_BASE (0x40236200UL + BASE_NS_OFFSET)
|
|
|
+ #define R_ACMPHS3_BASE (0x40236300UL + BASE_NS_OFFSET)
|
|
|
+ #define R_ACMPHS4_BASE (0x40236400UL + BASE_NS_OFFSET)
|
|
|
+ #define R_ACMPHS5_BASE (0x40236500UL + BASE_NS_OFFSET)
|
|
|
+ #define R_ADC0_BASE (0x40332000UL + BASE_NS_OFFSET)
|
|
|
+ #define R_ADC1_BASE (0x40332200UL + BASE_NS_OFFSET)
|
|
|
+ #define R_PSCU_BASE (0x40204000UL + BASE_NS_OFFSET)
|
|
|
+ #define R_BUS_BASE (0x40003000UL + BASE_NS_OFFSET)
|
|
|
+ #define R_CAC_BASE (0x40202400UL + BASE_NS_OFFSET)
|
|
|
+ #define R_CANFD_BASE (0x40380000UL + BASE_NS_OFFSET)
|
|
|
+ #define R_CANFD1_BASE (0x40382000UL + BASE_NS_OFFSET)
|
|
|
+ #define R_CRC_BASE (0x40310000UL + BASE_NS_OFFSET)
|
|
|
+ #define R_DAC_BASE (0x40333000UL + BASE_NS_OFFSET)
|
|
|
+ #define R_DAC1_BASE (0x40333100UL + BASE_NS_OFFSET)
|
|
|
+ #define R_DEBUG_BASE (0x4001B000UL + BASE_NS_OFFSET)
|
|
|
+ #define R_DMA_BASE (0x4000A800UL + BASE_NS_OFFSET)
|
|
|
+ #define R_DMAC0_BASE (0x4000A000UL + BASE_NS_OFFSET)
|
|
|
+ #define R_DMAC1_BASE (0x4000A040UL + BASE_NS_OFFSET)
|
|
|
+ #define R_DMAC2_BASE (0x4000A080UL + BASE_NS_OFFSET)
|
|
|
+ #define R_DMAC3_BASE (0x4000A0C0UL + BASE_NS_OFFSET)
|
|
|
+ #define R_DMAC4_BASE (0x4000A100UL + BASE_NS_OFFSET)
|
|
|
+ #define R_DMAC5_BASE (0x4000A140UL + BASE_NS_OFFSET)
|
|
|
+ #define R_DMAC6_BASE (0x4000A180UL + BASE_NS_OFFSET)
|
|
|
+ #define R_DMAC7_BASE (0x4000A1C0UL + BASE_NS_OFFSET)
|
|
|
+ #define R_DOC_BASE (0x40311000UL + BASE_NS_OFFSET)
|
|
|
+ #define R_DTC_BASE (0x4000AC00UL + BASE_NS_OFFSET)
|
|
|
+ #define R_ELC_BASE (0x40201000UL + BASE_NS_OFFSET)
|
|
|
+ #define R_ETHERC0_BASE (0x40354100UL + BASE_NS_OFFSET)
|
|
|
+ #define R_ETHERC_EDMAC_BASE (0x40354000UL + BASE_NS_OFFSET)
|
|
|
+ #define R_FACI_HP_CMD_BASE (0x40100000UL + BASE_NS_OFFSET)
|
|
|
+ #define R_FACI_HP_BASE (0x4011E000UL + BASE_NS_OFFSET)
|
|
|
+ #define R_FCACHE_BASE (0x4001C100UL + BASE_NS_OFFSET)
|
|
|
+ #define R_GPT0_BASE (0x40322000UL + BASE_NS_OFFSET)
|
|
|
+ #define R_GPT1_BASE (0x40322100UL + BASE_NS_OFFSET)
|
|
|
+ #define R_GPT2_BASE (0x40322200UL + BASE_NS_OFFSET)
|
|
|
+ #define R_GPT3_BASE (0x40322300UL + BASE_NS_OFFSET)
|
|
|
+ #define R_GPT4_BASE (0x40322400UL + BASE_NS_OFFSET)
|
|
|
+ #define R_GPT5_BASE (0x40322500UL + BASE_NS_OFFSET)
|
|
|
+ #define R_GPT6_BASE (0x40322600UL + BASE_NS_OFFSET)
|
|
|
+ #define R_GPT7_BASE (0x40322700UL + BASE_NS_OFFSET)
|
|
|
+ #define R_GPT8_BASE (0x40322800UL + BASE_NS_OFFSET)
|
|
|
+ #define R_GPT9_BASE (0x40322900UL + BASE_NS_OFFSET)
|
|
|
+ #define R_GPT10_BASE (0x40322A00UL + BASE_NS_OFFSET)
|
|
|
+ #define R_GPT11_BASE (0x40322B00UL + BASE_NS_OFFSET)
|
|
|
+ #define R_GPT12_BASE (0x40322C00UL + BASE_NS_OFFSET)
|
|
|
+ #define R_GPT13_BASE (0x40322D00UL + BASE_NS_OFFSET)
|
|
|
+ #define R_GPT_OPS_BASE (0x40323F00UL + BASE_NS_OFFSET)
|
|
|
+ #define R_GPT_POEG0_BASE (0x40212000UL + BASE_NS_OFFSET)
|
|
|
+ #define R_GPT_POEG1_BASE (0x40212100UL + BASE_NS_OFFSET)
|
|
|
+ #define R_GPT_POEG2_BASE (0x40212200UL + BASE_NS_OFFSET)
|
|
|
+ #define R_GPT_POEG3_BASE (0x40212300UL + BASE_NS_OFFSET)
|
|
|
+ #define R_ICU_BASE (0x40006000UL + BASE_NS_OFFSET)
|
|
|
+ #define R_IIC0_BASE (0x4025E000UL + BASE_NS_OFFSET)
|
|
|
+ #define R_IIC1_BASE (0x4025E100UL + BASE_NS_OFFSET)
|
|
|
+ #define R_IIC2_BASE (0x4025E200UL + BASE_NS_OFFSET)
|
|
|
+ #define R_IWDT_BASE (0x40202200UL + BASE_NS_OFFSET)
|
|
|
+ #define R_I3C0_BASE (0x4035F000UL + BASE_NS_OFFSET)
|
|
|
+ #define R_I3C1_BASE (0x4035F100UL + BASE_NS_OFFSET)
|
|
|
+ #define R_MPU_MMPU_BASE (0x40000000UL + BASE_NS_OFFSET)
|
|
|
+ #define R_MPU_SPMON_BASE (0x40000D00UL + BASE_NS_OFFSET)
|
|
|
+ #define R_MSTP_BASE (0x40203000UL + BASE_NS_OFFSET)
|
|
|
+ #define R_PORT0_BASE (0x40400000UL + BASE_NS_OFFSET)
|
|
|
+ #define R_PORT1_BASE (0x40400020UL + BASE_NS_OFFSET)
|
|
|
+ #define R_PORT2_BASE (0x40400040UL + BASE_NS_OFFSET)
|
|
|
+ #define R_PORT3_BASE (0x40400060UL + BASE_NS_OFFSET)
|
|
|
+ #define R_PORT4_BASE (0x40400080UL + BASE_NS_OFFSET)
|
|
|
+ #define R_PORT5_BASE (0x404000A0UL + BASE_NS_OFFSET)
|
|
|
+ #define R_PORT6_BASE (0x404000C0UL + BASE_NS_OFFSET)
|
|
|
+ #define R_PORT7_BASE (0x404000E0UL + BASE_NS_OFFSET)
|
|
|
+ #define R_PORT8_BASE (0x40400100UL + BASE_NS_OFFSET)
|
|
|
+ #define R_PORT9_BASE (0x40400120UL + BASE_NS_OFFSET)
|
|
|
+ #define R_PORT10_BASE (0x40400140UL + BASE_NS_OFFSET)
|
|
|
+ #define R_PORT11_BASE (0x40400160UL + BASE_NS_OFFSET)
|
|
|
+ #define R_PORT12_BASE (0x40400180UL + BASE_NS_OFFSET)
|
|
|
+ #define R_PORT13_BASE (0x404001A0UL + BASE_NS_OFFSET)
|
|
|
+ #define R_PORT14_BASE (0x404001C0UL + BASE_NS_OFFSET)
|
|
|
+ #define R_PFS_BASE (0x40400800UL + BASE_NS_OFFSET)
|
|
|
+ #define R_PMISC_BASE (0x40400D00UL + BASE_NS_OFFSET)
|
|
|
+ #define R_RTC_BASE (0x40202000UL + BASE_NS_OFFSET)
|
|
|
+ #define R_SCI0_BASE (0x40358000UL + BASE_NS_OFFSET)
|
|
|
+ #define R_SCI1_BASE (0x40358100UL + BASE_NS_OFFSET)
|
|
|
+ #define R_SCI2_BASE (0x40358200UL + BASE_NS_OFFSET)
|
|
|
+ #define R_SCI3_BASE (0x40358300UL + BASE_NS_OFFSET)
|
|
|
+ #define R_SCI4_BASE (0x40358400UL + BASE_NS_OFFSET)
|
|
|
+ #define R_SCI5_BASE (0x40358500UL + BASE_NS_OFFSET)
|
|
|
+ #define R_SCI6_BASE (0x40358600UL + BASE_NS_OFFSET)
|
|
|
+ #define R_SCI7_BASE (0x40358700UL + BASE_NS_OFFSET)
|
|
|
+ #define R_SCI8_BASE (0x40358800UL + BASE_NS_OFFSET)
|
|
|
+ #define R_SCI9_BASE (0x40358900UL + BASE_NS_OFFSET)
|
|
|
+ #define R_SDHI0_BASE (0x40252000UL + BASE_NS_OFFSET)
|
|
|
+ #define R_SDHI1_BASE (0x40252400UL + BASE_NS_OFFSET)
|
|
|
+ #define R_SPI0_BASE (0x4035C000UL + BASE_NS_OFFSET)
|
|
|
+ #define R_SPI1_BASE (0x4035C100UL + BASE_NS_OFFSET)
|
|
|
+ #define R_SRAM_BASE (0x40002000UL + BASE_NS_OFFSET)
|
|
|
+ #define R_SSI0_BASE (0x4025D000UL + BASE_NS_OFFSET)
|
|
|
+ #define R_SSI1_BASE (0x4025D100UL + BASE_NS_OFFSET)
|
|
|
+ #define R_SYSTEM_BASE (0x4001E000UL + BASE_NS_OFFSET)
|
|
|
+ #define R_TSN_CAL_BASE (0x4011B17CUL + BASE_NS_OFFSET)
|
|
|
+ #define R_TSN_CTRL_BASE (0x40235000UL + BASE_NS_OFFSET)
|
|
|
+ #define R_USB_FS0_BASE (0x40250000UL + BASE_NS_OFFSET)
|
|
|
+ #define R_WDT_BASE (0x40202600UL + BASE_NS_OFFSET)
|
|
|
+ #define R_TZF_BASE (0x40004000UL + BASE_NS_OFFSET)
|
|
|
+ #define R_CPSCU_BASE (0x40008000UL + BASE_NS_OFFSET)
|
|
|
+ #define R_DOC_B_BASE (0x40311000UL + BASE_NS_OFFSET)
|
|
|
+ #define R_SCI_B0_BASE (0x40358000UL + BASE_NS_OFFSET)
|
|
|
+ #define R_SCI_B1_BASE (0x40358100UL + BASE_NS_OFFSET)
|
|
|
+ #define R_SCI_B2_BASE (0x40358200UL + BASE_NS_OFFSET)
|
|
|
+ #define R_SCI_B3_BASE (0x40358300UL + BASE_NS_OFFSET)
|
|
|
+ #define R_SCI_B4_BASE (0x40358400UL + BASE_NS_OFFSET)
|
|
|
+ #define R_SCI_B9_BASE (0x40358900UL + BASE_NS_OFFSET)
|
|
|
+ #define R_SPI_B0_BASE (0x4035C000UL + BASE_NS_OFFSET)
|
|
|
+ #define R_SPI_B1_BASE (0x4035C100UL + BASE_NS_OFFSET)
|
|
|
+ #define R_USB_HS0_BASE (0x40351000UL + BASE_NS_OFFSET)
|
|
|
+ #define R_XSPI_BASE (0x40268000UL + BASE_NS_OFFSET)
|
|
|
+ #define R_CEU_BASE (0x40348000UL + BASE_NS_OFFSET)
|
|
|
+ #define R_ULPT0_BASE (0x40220000UL + BASE_NS_OFFSET)
|
|
|
+ #define R_ULPT1_BASE (0x40220100UL + BASE_NS_OFFSET)
|
|
|
+ #define R_DEBUG_OCD_BASE (0x40011000UL + BASE_NS_OFFSET)
|
|
|
+ #define R_DOTF_BASE (0x40268800UL + BASE_NS_OFFSET)
|
|
|
+ #define R_AGTX0_BASE (0x40221000UL + BASE_NS_OFFSET)
|
|
|
+ #define R_AGTX1_BASE (0x40221100UL + BASE_NS_OFFSET)
|
|
|
+ #define R_AGTX2_BASE (0x40221200UL + BASE_NS_OFFSET)
|
|
|
+ #define R_AGTX3_BASE (0x40221300UL + BASE_NS_OFFSET)
|
|
|
+ #define R_AGTX4_BASE (0x40221400UL + BASE_NS_OFFSET)
|
|
|
+ #define R_AGTX5_BASE (0x40221500UL + BASE_NS_OFFSET)
|
|
|
+ #define R_AGTX6_BASE (0x40221600UL + BASE_NS_OFFSET)
|
|
|
+ #define R_AGTX7_BASE (0x40221700UL + BASE_NS_OFFSET)
|
|
|
+ #define R_AGTX8_BASE (0x40221800UL + BASE_NS_OFFSET)
|
|
|
+ #define R_AGTX9_BASE (0x40221900UL + BASE_NS_OFFSET)
|
|
|
+ #define R_FLAD_BASE (0x4011C000UL + BASE_NS_OFFSET)
|
|
|
+ #define R_OFS_DATAFLASH_BASE (0x27030000UL + BASE_NS_OFFSET)
|
|
|
+
|
|
|
+/** @} */ /* End of group Device_Peripheral_peripheralAddr */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ Peripheral declaration ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/** @addtogroup Device_Peripheral_declaration
|
|
|
+ * @{
|
|
|
+ */
|
|
|
+
|
|
|
+ #define R_ACMPHS0 ((R_ACMPHS0_Type *) R_ACMPHS0_BASE)
|
|
|
+ #define R_ACMPHS1 ((R_ACMPHS0_Type *) R_ACMPHS1_BASE)
|
|
|
+ #define R_ACMPHS2 ((R_ACMPHS0_Type *) R_ACMPHS2_BASE)
|
|
|
+ #define R_ACMPHS3 ((R_ACMPHS0_Type *) R_ACMPHS3_BASE)
|
|
|
+ #define R_ACMPHS4 ((R_ACMPHS0_Type *) R_ACMPHS4_BASE)
|
|
|
+ #define R_ACMPHS5 ((R_ACMPHS0_Type *) R_ACMPHS5_BASE)
|
|
|
+ #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE)
|
|
|
+ #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE)
|
|
|
+ #define R_PSCU ((R_PSCU_Type *) R_PSCU_BASE)
|
|
|
+ #define R_BUS ((R_BUS_Type *) R_BUS_BASE)
|
|
|
+ #define R_CAC ((R_CAC_Type *) R_CAC_BASE)
|
|
|
+ #define R_CANFD ((R_CANFD_Type *) R_CANFD_BASE)
|
|
|
+ #define R_CANFD0 ((R_CANFD_Type *) R_CANFD_BASE)
|
|
|
+ #define R_CANFD1 ((R_CANFD_Type *) R_CANFD1_BASE)
|
|
|
+ #define R_CRC ((R_CRC_Type *) R_CRC_BASE)
|
|
|
+ #define R_DAC ((R_DAC_Type *) R_DAC_BASE)
|
|
|
+ #define R_DAC1 ((R_DAC_Type *) R_DAC1_BASE)
|
|
|
+ #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE)
|
|
|
+ #define R_DMA ((R_DMA_Type *) R_DMA_BASE)
|
|
|
+ #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE)
|
|
|
+ #define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE)
|
|
|
+ #define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE)
|
|
|
+ #define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE)
|
|
|
+ #define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE)
|
|
|
+ #define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE)
|
|
|
+ #define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE)
|
|
|
+ #define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE)
|
|
|
+ #define R_DOC ((R_DOC_Type *) R_DOC_BASE)
|
|
|
+ #define R_DTC ((R_DTC_Type *) R_DTC_BASE)
|
|
|
+ #define R_ELC ((R_ELC_Type *) R_ELC_BASE)
|
|
|
+ #define R_ETHERC0 ((R_ETHERC0_Type *) R_ETHERC0_BASE)
|
|
|
+ #define R_ETHERC_EDMAC ((R_ETHERC_EDMAC_Type *) R_ETHERC_EDMAC_BASE)
|
|
|
+ #define R_FACI_HP_CMD ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE)
|
|
|
+ #define R_FACI_HP ((R_FACI_HP_Type *) R_FACI_HP_BASE)
|
|
|
+ #define R_FCACHE ((R_FCACHE_Type *) R_FCACHE_BASE)
|
|
|
+ #define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE)
|
|
|
+ #define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE)
|
|
|
+ #define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE)
|
|
|
+ #define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE)
|
|
|
+ #define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE)
|
|
|
+ #define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE)
|
|
|
+ #define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE)
|
|
|
+ #define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE)
|
|
|
+ #define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE)
|
|
|
+ #define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE)
|
|
|
+ #define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE)
|
|
|
+ #define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE)
|
|
|
+ #define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE)
|
|
|
+ #define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE)
|
|
|
+ #define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE)
|
|
|
+ #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE)
|
|
|
+ #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE)
|
|
|
+ #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE)
|
|
|
+ #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE)
|
|
|
+ #define R_ICU ((R_ICU_Type *) R_ICU_BASE)
|
|
|
+ #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE)
|
|
|
+ #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE)
|
|
|
+ #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE)
|
|
|
+ #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE)
|
|
|
+ #define R_I3C0 ((R_I3C0_Type *) R_I3C0_BASE)
|
|
|
+ #define R_I3C1 ((R_I3C0_Type *) R_I3C1_BASE)
|
|
|
+ #define R_MPU_MMPU ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE)
|
|
|
+ #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE)
|
|
|
+ #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE)
|
|
|
+ #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE)
|
|
|
+ #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE)
|
|
|
+ #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE)
|
|
|
+ #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE)
|
|
|
+ #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE)
|
|
|
+ #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE)
|
|
|
+ #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE)
|
|
|
+ #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE)
|
|
|
+ #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE)
|
|
|
+ #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE)
|
|
|
+ #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE)
|
|
|
+ #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE)
|
|
|
+ #define R_PORT12 ((R_PORT0_Type *) R_PORT12_BASE)
|
|
|
+ #define R_PORT13 ((R_PORT0_Type *) R_PORT13_BASE)
|
|
|
+ #define R_PORT14 ((R_PORT0_Type *) R_PORT14_BASE)
|
|
|
+ #define R_PFS ((R_PFS_Type *) R_PFS_BASE)
|
|
|
+ #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE)
|
|
|
+ #define R_RTC ((R_RTC_Type *) R_RTC_BASE)
|
|
|
+ #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE)
|
|
|
+ #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE)
|
|
|
+ #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE)
|
|
|
+ #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE)
|
|
|
+ #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE)
|
|
|
+ #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE)
|
|
|
+ #define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE)
|
|
|
+ #define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE)
|
|
|
+ #define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE)
|
|
|
+ #define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE)
|
|
|
+ #define R_SDHI0 ((R_SDHI0_Type *) R_SDHI0_BASE)
|
|
|
+ #define R_SDHI1 ((R_SDHI0_Type *) R_SDHI1_BASE)
|
|
|
+ #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE)
|
|
|
+ #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE)
|
|
|
+ #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE)
|
|
|
+ #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE)
|
|
|
+ #define R_SSI1 ((R_SSI0_Type *) R_SSI1_BASE)
|
|
|
+ #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE)
|
|
|
+ #define R_TSN_CAL ((R_TSN_CAL_Type *) R_TSN_CAL_BASE)
|
|
|
+ #define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE)
|
|
|
+ #define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE)
|
|
|
+ #define R_WDT ((R_WDT_Type *) R_WDT_BASE)
|
|
|
+ #define R_TZF ((R_TZF_Type *) R_TZF_BASE)
|
|
|
+ #define R_CPSCU ((R_CPSCU_Type *) R_CPSCU_BASE)
|
|
|
+ #define R_DOC_B ((R_DOC_B_Type *) R_DOC_B_BASE)
|
|
|
+ #define R_SCI_B0 ((R_SCI_B0_Type *) R_SCI_B0_BASE)
|
|
|
+ #define R_SCI_B1 ((R_SCI_B0_Type *) R_SCI_B1_BASE)
|
|
|
+ #define R_SCI_B2 ((R_SCI_B0_Type *) R_SCI_B2_BASE)
|
|
|
+ #define R_SCI_B3 ((R_SCI_B0_Type *) R_SCI_B3_BASE)
|
|
|
+ #define R_SCI_B4 ((R_SCI_B0_Type *) R_SCI_B4_BASE)
|
|
|
+ #define R_SCI_B9 ((R_SCI_B0_Type *) R_SCI_B9_BASE)
|
|
|
+ #define R_SPI_B0 ((R_SPI_B0_Type *) R_SPI_B0_BASE)
|
|
|
+ #define R_SPI_B1 ((R_SPI_B0_Type *) R_SPI_B1_BASE)
|
|
|
+ #define R_USB_HS0 ((R_USB_HS0_Type *) R_USB_HS0_BASE)
|
|
|
+ #define R_XSPI ((R_XSPI_Type *) R_XSPI_BASE)
|
|
|
+ #define R_CEU ((R_CEU_Type *) R_CEU_BASE)
|
|
|
+ #define R_ULPT0 ((R_ULPT0_Type *) R_ULPT0_BASE)
|
|
|
+ #define R_ULPT1 ((R_ULPT0_Type *) R_ULPT1_BASE)
|
|
|
+ #define R_DEBUG_OCD ((R_DEBUG_OCD_Type *) R_DEBUG_OCD_BASE)
|
|
|
+ #define R_DOTF ((R_DOTF_Type *) R_DOTF_BASE)
|
|
|
+ #define R_AGT0 ((R_AGTX0_Type *) R_AGTX0_BASE)
|
|
|
+ #define R_AGT1 ((R_AGTX0_Type *) R_AGTX1_BASE)
|
|
|
+ #define R_AGT2 ((R_AGTX0_Type *) R_AGTX2_BASE)
|
|
|
+ #define R_AGT3 ((R_AGTX0_Type *) R_AGTX3_BASE)
|
|
|
+ #define R_AGT4 ((R_AGTX0_Type *) R_AGTX4_BASE)
|
|
|
+ #define R_AGT5 ((R_AGTX0_Type *) R_AGTX5_BASE)
|
|
|
+ #define R_AGT6 ((R_AGTX0_Type *) R_AGTX6_BASE)
|
|
|
+ #define R_AGT7 ((R_AGTX0_Type *) R_AGTX7_BASE)
|
|
|
+ #define R_AGT8 ((R_AGTX0_Type *) R_AGTX8_BASE)
|
|
|
+ #define R_AGT9 ((R_AGTX0_Type *) R_AGTX9_BASE)
|
|
|
+ #define R_FLAD ((R_FLAD_Type *) R_FLAD_BASE)
|
|
|
+ #define R_OFS_DATAFLASH ((R_OFS_DATAFLASH_Type *) R_OFS_DATAFLASH_BASE)
|
|
|
+
|
|
|
+/** @} */ /* End of group Device_Peripheral_declaration */
|
|
|
+
|
|
|
+/* ========================================= End of section using anonymous unions ========================================= */
|
|
|
+ #if defined(__CC_ARM)
|
|
|
+ #pragma pop
|
|
|
+ #elif defined(__ICCARM__)
|
|
|
+
|
|
|
+/* leave anonymous unions enabled */
|
|
|
+ #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
|
|
+ #pragma clang diagnostic pop
|
|
|
+ #elif defined(__GNUC__)
|
|
|
+
|
|
|
+/* anonymous unions are enabled by default */
|
|
|
+ #elif defined(__TMS470__)
|
|
|
+
|
|
|
+/* anonymous unions are enabled by default */
|
|
|
+ #elif defined(__TASKING__)
|
|
|
+ #pragma warning restore
|
|
|
+ #elif defined(__CSMC__)
|
|
|
+
|
|
|
+/* anonymous unions are enabled by default */
|
|
|
+ #endif
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ Pos/Mask Cluster Section ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/** @addtogroup PosMask_clusters
|
|
|
+ * @{
|
|
|
+ */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ CSa ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================== MOD ========================================================== */
|
|
|
+ #define R_BUS_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */
|
|
|
+ #define R_BUS_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_BUS_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */
|
|
|
+ #define R_BUS_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_BUS_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */
|
|
|
+ #define R_BUS_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_BUS_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */
|
|
|
+ #define R_BUS_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_BUS_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */
|
|
|
+ #define R_BUS_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= WCR1 ========================================================== */
|
|
|
+ #define R_BUS_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */
|
|
|
+ #define R_BUS_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */
|
|
|
+ #define R_BUS_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */
|
|
|
+ #define R_BUS_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */
|
|
|
+ #define R_BUS_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */
|
|
|
+ #define R_BUS_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_BUS_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */
|
|
|
+ #define R_BUS_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */
|
|
|
+/* ========================================================= WCR2 ========================================================== */
|
|
|
+ #define R_BUS_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */
|
|
|
+ #define R_BUS_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_BUS_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */
|
|
|
+ #define R_BUS_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_BUS_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */
|
|
|
+ #define R_BUS_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_BUS_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */
|
|
|
+ #define R_BUS_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_BUS_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */
|
|
|
+ #define R_BUS_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_BUS_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */
|
|
|
+ #define R_BUS_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_BUS_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */
|
|
|
+ #define R_BUS_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_BUS_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */
|
|
|
+ #define R_BUS_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ CSb ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================== CR =========================================================== */
|
|
|
+ #define R_BUS_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */
|
|
|
+ #define R_BUS_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_BUS_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */
|
|
|
+ #define R_BUS_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_BUS_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */
|
|
|
+ #define R_BUS_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_BUS_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */
|
|
|
+ #define R_BUS_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================== REC ========================================================== */
|
|
|
+ #define R_BUS_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */
|
|
|
+ #define R_BUS_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_BUS_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */
|
|
|
+ #define R_BUS_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ SDRAM ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================= SDCCR ========================================================= */
|
|
|
+ #define R_BUS_SDRAM_SDCCR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */
|
|
|
+ #define R_BUS_SDRAM_SDCCR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_BUS_SDRAM_SDCCR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */
|
|
|
+ #define R_BUS_SDRAM_SDCCR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== SDCMOD ========================================================= */
|
|
|
+ #define R_BUS_SDRAM_SDCMOD_EMODE_Pos (0UL) /*!< EMODE (Bit 0) */
|
|
|
+ #define R_BUS_SDRAM_SDCMOD_EMODE_Msk (0x1UL) /*!< EMODE (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== SDAMOD ========================================================= */
|
|
|
+ #define R_BUS_SDRAM_SDAMOD_BE_Pos (0UL) /*!< BE (Bit 0) */
|
|
|
+ #define R_BUS_SDRAM_SDAMOD_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== SDSELF ========================================================= */
|
|
|
+ #define R_BUS_SDRAM_SDSELF_SFEN_Pos (0UL) /*!< SFEN (Bit 0) */
|
|
|
+ #define R_BUS_SDRAM_SDSELF_SFEN_Msk (0x1UL) /*!< SFEN (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== SDRFCR ========================================================= */
|
|
|
+ #define R_BUS_SDRAM_SDRFCR_REFW_Pos (12UL) /*!< REFW (Bit 12) */
|
|
|
+ #define R_BUS_SDRAM_SDRFCR_REFW_Msk (0xf000UL) /*!< REFW (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_BUS_SDRAM_SDRFCR_RFC_Pos (0UL) /*!< RFC (Bit 0) */
|
|
|
+ #define R_BUS_SDRAM_SDRFCR_RFC_Msk (0xfffUL) /*!< RFC (Bitfield-Mask: 0xfff) */
|
|
|
+/* ======================================================== SDRFEN ========================================================= */
|
|
|
+ #define R_BUS_SDRAM_SDRFEN_RFEN_Pos (0UL) /*!< RFEN (Bit 0) */
|
|
|
+ #define R_BUS_SDRAM_SDRFEN_RFEN_Msk (0x1UL) /*!< RFEN (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= SDICR ========================================================= */
|
|
|
+ #define R_BUS_SDRAM_SDICR_INIRQ_Pos (0UL) /*!< INIRQ (Bit 0) */
|
|
|
+ #define R_BUS_SDRAM_SDICR_INIRQ_Msk (0x1UL) /*!< INIRQ (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= SDIR ========================================================== */
|
|
|
+ #define R_BUS_SDRAM_SDIR_PRC_Pos (8UL) /*!< PRC (Bit 8) */
|
|
|
+ #define R_BUS_SDRAM_SDIR_PRC_Msk (0x700UL) /*!< PRC (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_BUS_SDRAM_SDIR_ARFC_Pos (4UL) /*!< ARFC (Bit 4) */
|
|
|
+ #define R_BUS_SDRAM_SDIR_ARFC_Msk (0xf0UL) /*!< ARFC (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_BUS_SDRAM_SDIR_ARFI_Pos (0UL) /*!< ARFI (Bit 0) */
|
|
|
+ #define R_BUS_SDRAM_SDIR_ARFI_Msk (0xfUL) /*!< ARFI (Bitfield-Mask: 0x0f) */
|
|
|
+/* ========================================================= SDADR ========================================================= */
|
|
|
+ #define R_BUS_SDRAM_SDADR_MXC_Pos (0UL) /*!< MXC (Bit 0) */
|
|
|
+ #define R_BUS_SDRAM_SDADR_MXC_Msk (0x3UL) /*!< MXC (Bitfield-Mask: 0x03) */
|
|
|
+/* ========================================================= SDTR ========================================================== */
|
|
|
+ #define R_BUS_SDRAM_SDTR_RAS_Pos (16UL) /*!< RAS (Bit 16) */
|
|
|
+ #define R_BUS_SDRAM_SDTR_RAS_Msk (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_BUS_SDRAM_SDTR_RCD_Pos (12UL) /*!< RCD (Bit 12) */
|
|
|
+ #define R_BUS_SDRAM_SDTR_RCD_Msk (0x3000UL) /*!< RCD (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_BUS_SDRAM_SDTR_RP_Pos (9UL) /*!< RP (Bit 9) */
|
|
|
+ #define R_BUS_SDRAM_SDTR_RP_Msk (0xe00UL) /*!< RP (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_BUS_SDRAM_SDTR_WR_Pos (8UL) /*!< WR (Bit 8) */
|
|
|
+ #define R_BUS_SDRAM_SDTR_WR_Msk (0x100UL) /*!< WR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_BUS_SDRAM_SDTR_CL_Pos (0UL) /*!< CL (Bit 0) */
|
|
|
+ #define R_BUS_SDRAM_SDTR_CL_Msk (0x7UL) /*!< CL (Bitfield-Mask: 0x07) */
|
|
|
+/* ========================================================= SDMOD ========================================================= */
|
|
|
+ #define R_BUS_SDRAM_SDMOD_MR_Pos (0UL) /*!< MR (Bit 0) */
|
|
|
+ #define R_BUS_SDRAM_SDMOD_MR_Msk (0x7fffUL) /*!< MR (Bitfield-Mask: 0x7fff) */
|
|
|
+/* ========================================================= SDSR ========================================================== */
|
|
|
+ #define R_BUS_SDRAM_SDSR_SRFST_Pos (4UL) /*!< SRFST (Bit 4) */
|
|
|
+ #define R_BUS_SDRAM_SDSR_SRFST_Msk (0x10UL) /*!< SRFST (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_BUS_SDRAM_SDSR_INIST_Pos (3UL) /*!< INIST (Bit 3) */
|
|
|
+ #define R_BUS_SDRAM_SDSR_INIST_Msk (0x8UL) /*!< INIST (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_BUS_SDRAM_SDSR_MRSST_Pos (0UL) /*!< MRSST (Bit 0) */
|
|
|
+ #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ BUSERRa ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================== ADD ========================================================== */
|
|
|
+ #define R_BUS_BUSERRa_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */
|
|
|
+ #define R_BUS_BUSERRa_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ========================================================= STAT ========================================================== */
|
|
|
+ #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */
|
|
|
+ #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */
|
|
|
+ #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================== RW =========================================================== */
|
|
|
+ #define R_BUS_BUSERRa_RW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */
|
|
|
+ #define R_BUS_BUSERRa_RW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ BTZFERR ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================== ADD ========================================================== */
|
|
|
+ #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */
|
|
|
+ #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ========================================================== RW =========================================================== */
|
|
|
+ #define R_BUS_BTZFERR_RW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */
|
|
|
+ #define R_BUS_BTZFERR_RW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ BUSERRb ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================= STAT ========================================================== */
|
|
|
+ #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos (5UL) /*!< MSERRSTAT (Bit 5) */
|
|
|
+ #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */
|
|
|
+ #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */
|
|
|
+ #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */
|
|
|
+ #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */
|
|
|
+ #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================== CLR ========================================================== */
|
|
|
+ #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos (5UL) /*!< MSERRCLR (Bit 5) */
|
|
|
+ #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */
|
|
|
+ #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */
|
|
|
+ #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_BUS_BUSERRb_CLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */
|
|
|
+ #define R_BUS_BUSERRb_CLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */
|
|
|
+ #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ DMACDTCERR ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================= STAT ========================================================== */
|
|
|
+ #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */
|
|
|
+ #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================== CLR ========================================================== */
|
|
|
+ #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */
|
|
|
+ #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ BUSSABT0 ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================= FLBI ========================================================== */
|
|
|
+ #define R_BUS_BUSSABT0_FLBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
|
|
|
+ #define R_BUS_BUSSABT0_FLBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== MRE0BI ========================================================= */
|
|
|
+ #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
|
|
|
+ #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= S0BI ========================================================== */
|
|
|
+ #define R_BUS_BUSSABT0_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
|
|
|
+ #define R_BUS_BUSSABT0_S0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= S1BI ========================================================== */
|
|
|
+ #define R_BUS_BUSSABT0_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
|
|
|
+ #define R_BUS_BUSSABT0_S1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= S2BI ========================================================== */
|
|
|
+ #define R_BUS_BUSSABT0_S2BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
|
|
|
+ #define R_BUS_BUSSABT0_S2BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= S3BI ========================================================== */
|
|
|
+ #define R_BUS_BUSSABT0_S3BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
|
|
|
+ #define R_BUS_BUSSABT0_S3BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== STBYSBI ======================================================== */
|
|
|
+ #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
|
|
|
+ #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= ECBI ========================================================== */
|
|
|
+ #define R_BUS_BUSSABT0_ECBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
|
|
|
+ #define R_BUS_BUSSABT0_ECBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= EOBI ========================================================== */
|
|
|
+ #define R_BUS_BUSSABT0_EOBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
|
|
|
+ #define R_BUS_BUSSABT0_EOBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== SPI0BI ========================================================= */
|
|
|
+ #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
|
|
|
+ #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== SPI1BI ========================================================= */
|
|
|
+ #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
|
|
|
+ #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= PBBI ========================================================== */
|
|
|
+ #define R_BUS_BUSSABT0_PBBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
|
|
|
+ #define R_BUS_BUSSABT0_PBBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= PABI ========================================================== */
|
|
|
+ #define R_BUS_BUSSABT0_PABI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
|
|
|
+ #define R_BUS_BUSSABT0_PABI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= PIBI ========================================================== */
|
|
|
+ #define R_BUS_BUSSABT0_PIBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
|
|
|
+ #define R_BUS_BUSSABT0_PIBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= PSBI ========================================================== */
|
|
|
+ #define R_BUS_BUSSABT0_PSBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
|
|
|
+ #define R_BUS_BUSSABT0_PSBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= CPU0SAHBI ======================================================= */
|
|
|
+ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
|
|
|
+ #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= CPU1TCMBI ======================================================= */
|
|
|
+ #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
|
|
|
+ #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ BUSSABT1 ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================= FHBI ========================================================== */
|
|
|
+ #define R_BUS_BUSSABT1_FHBI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
|
|
|
+ #define R_BUS_BUSSABT1_FHBI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */
|
|
|
+/* ======================================================== MRC0BI ========================================================= */
|
|
|
+ #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
|
|
|
+ #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */
|
|
|
+/* ========================================================= S0BI ========================================================== */
|
|
|
+ #define R_BUS_BUSSABT1_S0BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
|
|
|
+ #define R_BUS_BUSSABT1_S0BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */
|
|
|
+/* ========================================================= S1BI ========================================================== */
|
|
|
+ #define R_BUS_BUSSABT1_S1BI_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
|
|
|
+ #define R_BUS_BUSSABT1_S1BI_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ BMSAERR ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================== ADD ========================================================== */
|
|
|
+ #define R_BUS_BMSAERR_ADD_MSERAD_Pos (0UL) /*!< MSERAD (Bit 0) */
|
|
|
+ #define R_BUS_BMSAERR_ADD_MSERAD_Msk (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ========================================================== RW =========================================================== */
|
|
|
+ #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos (0UL) /*!< MSARWSTAT (Bit 0) */
|
|
|
+ #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk (0x1UL) /*!< MSARWSTAT (Bitfield-Mask: 0x01) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ OAD ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ======================================================== BUSOAD ========================================================= */
|
|
|
+ #define R_BUS_OAD_BUSOAD_BWERROAD_Pos (2UL) /*!< BWERROAD (Bit 2) */
|
|
|
+ #define R_BUS_OAD_BUSOAD_BWERROAD_Msk (0x4UL) /*!< BWERROAD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_BUS_OAD_BUSOAD_SLERROAD_Pos (1UL) /*!< SLERROAD (Bit 1) */
|
|
|
+ #define R_BUS_OAD_BUSOAD_SLERROAD_Msk (0x2UL) /*!< SLERROAD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_BUS_OAD_BUSOAD_ILERROAD_Pos (0UL) /*!< ILERROAD (Bit 0) */
|
|
|
+ #define R_BUS_OAD_BUSOAD_ILERROAD_Msk (0x1UL) /*!< ILERROAD (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= BUSOADPT ======================================================== */
|
|
|
+ #define R_BUS_OAD_BUSOADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */
|
|
|
+ #define R_BUS_OAD_BUSOADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_BUS_OAD_BUSOADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */
|
|
|
+ #define R_BUS_OAD_BUSOADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== MSAOAD ========================================================= */
|
|
|
+ #define R_BUS_OAD_MSAOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */
|
|
|
+ #define R_BUS_OAD_MSAOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_BUS_OAD_MSAOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */
|
|
|
+ #define R_BUS_OAD_MSAOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= MSAPT ========================================================= */
|
|
|
+ #define R_BUS_OAD_MSAPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */
|
|
|
+ #define R_BUS_OAD_MSAPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_BUS_OAD_MSAPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */
|
|
|
+ #define R_BUS_OAD_MSAPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ MBWERR ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================= STAT ========================================================== */
|
|
|
+ #define R_BUS_MBWERR_STAT_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */
|
|
|
+ #define R_BUS_MBWERR_STAT_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================== CLR ========================================================== */
|
|
|
+ #define R_BUS_MBWERR_CLR_BWERR_Pos (0UL) /*!< BWERR (Bit 0) */
|
|
|
+ #define R_BUS_MBWERR_CLR_BWERR_Msk (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ BUSM ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================== CNT ========================================================== */
|
|
|
+ #define R_BUS_BUSM_CNT_IERES_Pos (15UL) /*!< IERES (Bit 15) */
|
|
|
+ #define R_BUS_BUSM_CNT_IERES_Msk (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ BUSS ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================== CNT ========================================================== */
|
|
|
+ #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */
|
|
|
+ #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_BUS_BUSS_CNT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
|
|
|
+ #define R_BUS_BUSS_CNT_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ CFDC ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================= NCFG ========================================================== */
|
|
|
+ #define R_CANFD_CFDC_NCFG_NBRP_Pos (0UL) /*!< NBRP (Bit 0) */
|
|
|
+ #define R_CANFD_CFDC_NCFG_NBRP_Msk (0x3ffUL) /*!< NBRP (Bitfield-Mask: 0x3ff) */
|
|
|
+ #define R_CANFD_CFDC_NCFG_NSJW_Pos (10UL) /*!< NSJW (Bit 10) */
|
|
|
+ #define R_CANFD_CFDC_NCFG_NSJW_Msk (0x1fc00UL) /*!< NSJW (Bitfield-Mask: 0x7f) */
|
|
|
+ #define R_CANFD_CFDC_NCFG_NTSEG1_Pos (17UL) /*!< NTSEG1 (Bit 17) */
|
|
|
+ #define R_CANFD_CFDC_NCFG_NTSEG1_Msk (0x1fe0000UL) /*!< NTSEG1 (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_CANFD_CFDC_NCFG_NTSEG2_Pos (25UL) /*!< NTSEG2 (Bit 25) */
|
|
|
+ #define R_CANFD_CFDC_NCFG_NTSEG2_Msk (0xfe000000UL) /*!< NTSEG2 (Bitfield-Mask: 0x7f) */
|
|
|
+/* ========================================================== CTR ========================================================== */
|
|
|
+ #define R_CANFD_CFDC_CTR_CHMDC_Pos (0UL) /*!< CHMDC (Bit 0) */
|
|
|
+ #define R_CANFD_CFDC_CTR_CHMDC_Msk (0x3UL) /*!< CHMDC (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_CANFD_CFDC_CTR_CSLPR_Pos (2UL) /*!< CSLPR (Bit 2) */
|
|
|
+ #define R_CANFD_CFDC_CTR_CSLPR_Msk (0x4UL) /*!< CSLPR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC_CTR_RTBO_Pos (3UL) /*!< RTBO (Bit 3) */
|
|
|
+ #define R_CANFD_CFDC_CTR_RTBO_Msk (0x8UL) /*!< RTBO (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC_CTR_BEIE_Pos (8UL) /*!< BEIE (Bit 8) */
|
|
|
+ #define R_CANFD_CFDC_CTR_BEIE_Msk (0x100UL) /*!< BEIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC_CTR_EWIE_Pos (9UL) /*!< EWIE (Bit 9) */
|
|
|
+ #define R_CANFD_CFDC_CTR_EWIE_Msk (0x200UL) /*!< EWIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC_CTR_EPIE_Pos (10UL) /*!< EPIE (Bit 10) */
|
|
|
+ #define R_CANFD_CFDC_CTR_EPIE_Msk (0x400UL) /*!< EPIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC_CTR_BOEIE_Pos (11UL) /*!< BOEIE (Bit 11) */
|
|
|
+ #define R_CANFD_CFDC_CTR_BOEIE_Msk (0x800UL) /*!< BOEIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC_CTR_BORIE_Pos (12UL) /*!< BORIE (Bit 12) */
|
|
|
+ #define R_CANFD_CFDC_CTR_BORIE_Msk (0x1000UL) /*!< BORIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC_CTR_OLIE_Pos (13UL) /*!< OLIE (Bit 13) */
|
|
|
+ #define R_CANFD_CFDC_CTR_OLIE_Msk (0x2000UL) /*!< OLIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC_CTR_BLIE_Pos (14UL) /*!< BLIE (Bit 14) */
|
|
|
+ #define R_CANFD_CFDC_CTR_BLIE_Msk (0x4000UL) /*!< BLIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC_CTR_ALIE_Pos (15UL) /*!< ALIE (Bit 15) */
|
|
|
+ #define R_CANFD_CFDC_CTR_ALIE_Msk (0x8000UL) /*!< ALIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC_CTR_TAIE_Pos (16UL) /*!< TAIE (Bit 16) */
|
|
|
+ #define R_CANFD_CFDC_CTR_TAIE_Msk (0x10000UL) /*!< TAIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC_CTR_EOCOIE_Pos (17UL) /*!< EOCOIE (Bit 17) */
|
|
|
+ #define R_CANFD_CFDC_CTR_EOCOIE_Msk (0x20000UL) /*!< EOCOIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC_CTR_SOCOIE_Pos (18UL) /*!< SOCOIE (Bit 18) */
|
|
|
+ #define R_CANFD_CFDC_CTR_SOCOIE_Msk (0x40000UL) /*!< SOCOIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC_CTR_TDCVFIE_Pos (19UL) /*!< TDCVFIE (Bit 19) */
|
|
|
+ #define R_CANFD_CFDC_CTR_TDCVFIE_Msk (0x80000UL) /*!< TDCVFIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC_CTR_BOM_Pos (21UL) /*!< BOM (Bit 21) */
|
|
|
+ #define R_CANFD_CFDC_CTR_BOM_Msk (0x600000UL) /*!< BOM (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_CANFD_CFDC_CTR_ERRD_Pos (23UL) /*!< ERRD (Bit 23) */
|
|
|
+ #define R_CANFD_CFDC_CTR_ERRD_Msk (0x800000UL) /*!< ERRD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC_CTR_CTME_Pos (24UL) /*!< CTME (Bit 24) */
|
|
|
+ #define R_CANFD_CFDC_CTR_CTME_Msk (0x1000000UL) /*!< CTME (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC_CTR_CTMS_Pos (25UL) /*!< CTMS (Bit 25) */
|
|
|
+ #define R_CANFD_CFDC_CTR_CTMS_Msk (0x6000000UL) /*!< CTMS (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_CANFD_CFDC_CTR_CRCT_Pos (30UL) /*!< CRCT (Bit 30) */
|
|
|
+ #define R_CANFD_CFDC_CTR_CRCT_Msk (0x40000000UL) /*!< CRCT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC_CTR_ROM_Pos (31UL) /*!< ROM (Bit 31) */
|
|
|
+ #define R_CANFD_CFDC_CTR_ROM_Msk (0x80000000UL) /*!< ROM (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================== STS ========================================================== */
|
|
|
+ #define R_CANFD_CFDC_STS_CRSTSTS_Pos (0UL) /*!< CRSTSTS (Bit 0) */
|
|
|
+ #define R_CANFD_CFDC_STS_CRSTSTS_Msk (0x1UL) /*!< CRSTSTS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC_STS_CHLTSTS_Pos (1UL) /*!< CHLTSTS (Bit 1) */
|
|
|
+ #define R_CANFD_CFDC_STS_CHLTSTS_Msk (0x2UL) /*!< CHLTSTS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC_STS_CSLPSTS_Pos (2UL) /*!< CSLPSTS (Bit 2) */
|
|
|
+ #define R_CANFD_CFDC_STS_CSLPSTS_Msk (0x4UL) /*!< CSLPSTS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC_STS_EPSTS_Pos (3UL) /*!< EPSTS (Bit 3) */
|
|
|
+ #define R_CANFD_CFDC_STS_EPSTS_Msk (0x8UL) /*!< EPSTS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC_STS_BOSTS_Pos (4UL) /*!< BOSTS (Bit 4) */
|
|
|
+ #define R_CANFD_CFDC_STS_BOSTS_Msk (0x10UL) /*!< BOSTS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC_STS_TRMSTS_Pos (5UL) /*!< TRMSTS (Bit 5) */
|
|
|
+ #define R_CANFD_CFDC_STS_TRMSTS_Msk (0x20UL) /*!< TRMSTS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC_STS_RECSTS_Pos (6UL) /*!< RECSTS (Bit 6) */
|
|
|
+ #define R_CANFD_CFDC_STS_RECSTS_Msk (0x40UL) /*!< RECSTS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC_STS_COMSTS_Pos (7UL) /*!< COMSTS (Bit 7) */
|
|
|
+ #define R_CANFD_CFDC_STS_COMSTS_Msk (0x80UL) /*!< COMSTS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC_STS_ESIF_Pos (8UL) /*!< ESIF (Bit 8) */
|
|
|
+ #define R_CANFD_CFDC_STS_ESIF_Msk (0x100UL) /*!< ESIF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC_STS_REC_Pos (16UL) /*!< REC (Bit 16) */
|
|
|
+ #define R_CANFD_CFDC_STS_REC_Msk (0xff0000UL) /*!< REC (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_CANFD_CFDC_STS_TEC_Pos (24UL) /*!< TEC (Bit 24) */
|
|
|
+ #define R_CANFD_CFDC_STS_TEC_Msk (0xff000000UL) /*!< TEC (Bitfield-Mask: 0xff) */
|
|
|
+/* ========================================================= ERFL ========================================================== */
|
|
|
+ #define R_CANFD_CFDC_ERFL_BEF_Pos (0UL) /*!< BEF (Bit 0) */
|
|
|
+ #define R_CANFD_CFDC_ERFL_BEF_Msk (0x1UL) /*!< BEF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC_ERFL_EWF_Pos (1UL) /*!< EWF (Bit 1) */
|
|
|
+ #define R_CANFD_CFDC_ERFL_EWF_Msk (0x2UL) /*!< EWF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC_ERFL_EPF_Pos (2UL) /*!< EPF (Bit 2) */
|
|
|
+ #define R_CANFD_CFDC_ERFL_EPF_Msk (0x4UL) /*!< EPF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC_ERFL_BOEF_Pos (3UL) /*!< BOEF (Bit 3) */
|
|
|
+ #define R_CANFD_CFDC_ERFL_BOEF_Msk (0x8UL) /*!< BOEF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC_ERFL_BORF_Pos (4UL) /*!< BORF (Bit 4) */
|
|
|
+ #define R_CANFD_CFDC_ERFL_BORF_Msk (0x10UL) /*!< BORF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC_ERFL_OVLF_Pos (5UL) /*!< OVLF (Bit 5) */
|
|
|
+ #define R_CANFD_CFDC_ERFL_OVLF_Msk (0x20UL) /*!< OVLF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC_ERFL_BLF_Pos (6UL) /*!< BLF (Bit 6) */
|
|
|
+ #define R_CANFD_CFDC_ERFL_BLF_Msk (0x40UL) /*!< BLF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC_ERFL_ALF_Pos (7UL) /*!< ALF (Bit 7) */
|
|
|
+ #define R_CANFD_CFDC_ERFL_ALF_Msk (0x80UL) /*!< ALF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC_ERFL_SERR_Pos (8UL) /*!< SERR (Bit 8) */
|
|
|
+ #define R_CANFD_CFDC_ERFL_SERR_Msk (0x100UL) /*!< SERR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC_ERFL_FERR_Pos (9UL) /*!< FERR (Bit 9) */
|
|
|
+ #define R_CANFD_CFDC_ERFL_FERR_Msk (0x200UL) /*!< FERR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC_ERFL_AERR_Pos (10UL) /*!< AERR (Bit 10) */
|
|
|
+ #define R_CANFD_CFDC_ERFL_AERR_Msk (0x400UL) /*!< AERR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC_ERFL_CERR_Pos (11UL) /*!< CERR (Bit 11) */
|
|
|
+ #define R_CANFD_CFDC_ERFL_CERR_Msk (0x800UL) /*!< CERR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC_ERFL_B1ERR_Pos (12UL) /*!< B1ERR (Bit 12) */
|
|
|
+ #define R_CANFD_CFDC_ERFL_B1ERR_Msk (0x1000UL) /*!< B1ERR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC_ERFL_B0ERR_Pos (13UL) /*!< B0ERR (Bit 13) */
|
|
|
+ #define R_CANFD_CFDC_ERFL_B0ERR_Msk (0x2000UL) /*!< B0ERR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC_ERFL_ADERR_Pos (14UL) /*!< ADERR (Bit 14) */
|
|
|
+ #define R_CANFD_CFDC_ERFL_ADERR_Msk (0x4000UL) /*!< ADERR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC_ERFL_CRCREG_Pos (16UL) /*!< CRCREG (Bit 16) */
|
|
|
+ #define R_CANFD_CFDC_ERFL_CRCREG_Msk (0x7fff0000UL) /*!< CRCREG (Bitfield-Mask: 0x7fff) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ CFDC2 ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================= DCFG ========================================================== */
|
|
|
+ #define R_CANFD_CFDC2_DCFG_DBRP_Pos (0UL) /*!< DBRP (Bit 0) */
|
|
|
+ #define R_CANFD_CFDC2_DCFG_DBRP_Msk (0xffUL) /*!< DBRP (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_CANFD_CFDC2_DCFG_DTSEG1_Pos (8UL) /*!< DTSEG1 (Bit 8) */
|
|
|
+ #define R_CANFD_CFDC2_DCFG_DTSEG1_Msk (0x1f00UL) /*!< DTSEG1 (Bitfield-Mask: 0x1f) */
|
|
|
+ #define R_CANFD_CFDC2_DCFG_DTSEG2_Pos (16UL) /*!< DTSEG2 (Bit 16) */
|
|
|
+ #define R_CANFD_CFDC2_DCFG_DTSEG2_Msk (0xf0000UL) /*!< DTSEG2 (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_CANFD_CFDC2_DCFG_DSJW_Pos (24UL) /*!< DSJW (Bit 24) */
|
|
|
+ #define R_CANFD_CFDC2_DCFG_DSJW_Msk (0xf000000UL) /*!< DSJW (Bitfield-Mask: 0x0f) */
|
|
|
+/* ========================================================= FDCFG ========================================================= */
|
|
|
+ #define R_CANFD_CFDC2_FDCFG_EOCCFG_Pos (0UL) /*!< EOCCFG (Bit 0) */
|
|
|
+ #define R_CANFD_CFDC2_FDCFG_EOCCFG_Msk (0x7UL) /*!< EOCCFG (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_CANFD_CFDC2_FDCFG_TDCOC_Pos (8UL) /*!< TDCOC (Bit 8) */
|
|
|
+ #define R_CANFD_CFDC2_FDCFG_TDCOC_Msk (0x100UL) /*!< TDCOC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC2_FDCFG_TDCE_Pos (9UL) /*!< TDCE (Bit 9) */
|
|
|
+ #define R_CANFD_CFDC2_FDCFG_TDCE_Msk (0x200UL) /*!< TDCE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC2_FDCFG_ESIC_Pos (10UL) /*!< ESIC (Bit 10) */
|
|
|
+ #define R_CANFD_CFDC2_FDCFG_ESIC_Msk (0x400UL) /*!< ESIC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC2_FDCFG_TDCO_Pos (16UL) /*!< TDCO (Bit 16) */
|
|
|
+ #define R_CANFD_CFDC2_FDCFG_TDCO_Msk (0xff0000UL) /*!< TDCO (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_CANFD_CFDC2_FDCFG_FDOE_Pos (28UL) /*!< FDOE (Bit 28) */
|
|
|
+ #define R_CANFD_CFDC2_FDCFG_FDOE_Msk (0x10000000UL) /*!< FDOE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC2_FDCFG_REFE_Pos (29UL) /*!< REFE (Bit 29) */
|
|
|
+ #define R_CANFD_CFDC2_FDCFG_REFE_Msk (0x20000000UL) /*!< REFE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC2_FDCFG_CLOE_Pos (30UL) /*!< CLOE (Bit 30) */
|
|
|
+ #define R_CANFD_CFDC2_FDCFG_CLOE_Msk (0x40000000UL) /*!< CLOE (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= FDCTR ========================================================= */
|
|
|
+ #define R_CANFD_CFDC2_FDCTR_EOCCLR_Pos (0UL) /*!< EOCCLR (Bit 0) */
|
|
|
+ #define R_CANFD_CFDC2_FDCTR_EOCCLR_Msk (0x1UL) /*!< EOCCLR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC2_FDCTR_SOCCLR_Pos (1UL) /*!< SOCCLR (Bit 1) */
|
|
|
+ #define R_CANFD_CFDC2_FDCTR_SOCCLR_Msk (0x2UL) /*!< SOCCLR (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= FDSTS ========================================================= */
|
|
|
+ #define R_CANFD_CFDC2_FDSTS_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */
|
|
|
+ #define R_CANFD_CFDC2_FDSTS_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_CANFD_CFDC2_FDSTS_EOCO_Pos (8UL) /*!< EOCO (Bit 8) */
|
|
|
+ #define R_CANFD_CFDC2_FDSTS_EOCO_Msk (0x100UL) /*!< EOCO (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC2_FDSTS_SOCO_Pos (9UL) /*!< SOCO (Bit 9) */
|
|
|
+ #define R_CANFD_CFDC2_FDSTS_SOCO_Msk (0x200UL) /*!< SOCO (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC2_FDSTS_TDCVF_Pos (15UL) /*!< TDCVF (Bit 15) */
|
|
|
+ #define R_CANFD_CFDC2_FDSTS_TDCVF_Msk (0x8000UL) /*!< TDCVF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDC2_FDSTS_EOC_Pos (16UL) /*!< EOC (Bit 16) */
|
|
|
+ #define R_CANFD_CFDC2_FDSTS_EOC_Msk (0xff0000UL) /*!< EOC (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_CANFD_CFDC2_FDSTS_SOC_Pos (24UL) /*!< SOC (Bit 24) */
|
|
|
+ #define R_CANFD_CFDC2_FDSTS_SOC_Msk (0xff000000UL) /*!< SOC (Bitfield-Mask: 0xff) */
|
|
|
+/* ========================================================= FDCRC ========================================================= */
|
|
|
+ #define R_CANFD_CFDC2_FDCRC_CRCREG_Pos (0UL) /*!< CRCREG (Bit 0) */
|
|
|
+ #define R_CANFD_CFDC2_FDCRC_CRCREG_Msk (0x1fffffUL) /*!< CRCREG (Bitfield-Mask: 0x1fffff) */
|
|
|
+ #define R_CANFD_CFDC2_FDCRC_SCNT_Pos (24UL) /*!< SCNT (Bit 24) */
|
|
|
+ #define R_CANFD_CFDC2_FDCRC_SCNT_Msk (0xf000000UL) /*!< SCNT (Bitfield-Mask: 0x0f) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ CFDGAFL ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================== ID =========================================================== */
|
|
|
+ #define R_CANFD_CFDGAFL_ID_GAFLID_Pos (0UL) /*!< GAFLID (Bit 0) */
|
|
|
+ #define R_CANFD_CFDGAFL_ID_GAFLID_Msk (0x1fffffffUL) /*!< GAFLID (Bitfield-Mask: 0x1fffffff) */
|
|
|
+ #define R_CANFD_CFDGAFL_ID_GAFLLB_Pos (29UL) /*!< GAFLLB (Bit 29) */
|
|
|
+ #define R_CANFD_CFDGAFL_ID_GAFLLB_Msk (0x20000000UL) /*!< GAFLLB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDGAFL_ID_GAFLRTR_Pos (30UL) /*!< GAFLRTR (Bit 30) */
|
|
|
+ #define R_CANFD_CFDGAFL_ID_GAFLRTR_Msk (0x40000000UL) /*!< GAFLRTR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDGAFL_ID_GAFLIDE_Pos (31UL) /*!< GAFLIDE (Bit 31) */
|
|
|
+ #define R_CANFD_CFDGAFL_ID_GAFLIDE_Msk (0x80000000UL) /*!< GAFLIDE (Bitfield-Mask: 0x01) */
|
|
|
+/* =========================================================== M =========================================================== */
|
|
|
+ #define R_CANFD_CFDGAFL_M_GAFLIDM_Pos (0UL) /*!< GAFLIDM (Bit 0) */
|
|
|
+ #define R_CANFD_CFDGAFL_M_GAFLIDM_Msk (0x1fffffffUL) /*!< GAFLIDM (Bitfield-Mask: 0x1fffffff) */
|
|
|
+ #define R_CANFD_CFDGAFL_M_GAFLIFL1_Pos (29UL) /*!< GAFLIFL1 (Bit 29) */
|
|
|
+ #define R_CANFD_CFDGAFL_M_GAFLIFL1_Msk (0x20000000UL) /*!< GAFLIFL1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDGAFL_M_GAFLRTRM_Pos (30UL) /*!< GAFLRTRM (Bit 30) */
|
|
|
+ #define R_CANFD_CFDGAFL_M_GAFLRTRM_Msk (0x40000000UL) /*!< GAFLRTRM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDGAFL_M_GAFLIDEM_Pos (31UL) /*!< GAFLIDEM (Bit 31) */
|
|
|
+ #define R_CANFD_CFDGAFL_M_GAFLIDEM_Msk (0x80000000UL) /*!< GAFLIDEM (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================== P0 =========================================================== */
|
|
|
+ #define R_CANFD_CFDGAFL_P0_GAFLDLC_Pos (0UL) /*!< GAFLDLC (Bit 0) */
|
|
|
+ #define R_CANFD_CFDGAFL_P0_GAFLDLC_Msk (0xfUL) /*!< GAFLDLC (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Pos (7UL) /*!< GAFLIFL0 (Bit 7) */
|
|
|
+ #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Msk (0x80UL) /*!< GAFLIFL0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Pos (8UL) /*!< GAFLRMDP (Bit 8) */
|
|
|
+ #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Msk (0x1f00UL) /*!< GAFLRMDP (Bitfield-Mask: 0x1f) */
|
|
|
+ #define R_CANFD_CFDGAFL_P0_GAFLRMV_Pos (15UL) /*!< GAFLRMV (Bit 15) */
|
|
|
+ #define R_CANFD_CFDGAFL_P0_GAFLRMV_Msk (0x8000UL) /*!< GAFLRMV (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDGAFL_P0_GAFLPTR_Pos (16UL) /*!< GAFLPTR (Bit 16) */
|
|
|
+ #define R_CANFD_CFDGAFL_P0_GAFLPTR_Msk (0xffff0000UL) /*!< GAFLPTR (Bitfield-Mask: 0xffff) */
|
|
|
+/* ========================================================== P1 =========================================================== */
|
|
|
+ #define R_CANFD_CFDGAFL_P1_GAFLFDP_Pos (0UL) /*!< GAFLFDP (Bit 0) */
|
|
|
+ #define R_CANFD_CFDGAFL_P1_GAFLFDP_Msk (0x1ffUL) /*!< GAFLFDP (Bitfield-Mask: 0x1ff) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ CFDTHL ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================= ACC0 ========================================================== */
|
|
|
+ #define R_CANFD_CFDTHL_ACC0_BT_Pos (0UL) /*!< BT (Bit 0) */
|
|
|
+ #define R_CANFD_CFDTHL_ACC0_BT_Msk (0x7UL) /*!< BT (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_CANFD_CFDTHL_ACC0_BN_Pos (3UL) /*!< BN (Bit 3) */
|
|
|
+ #define R_CANFD_CFDTHL_ACC0_BN_Msk (0x3f8UL) /*!< BN (Bitfield-Mask: 0x7f) */
|
|
|
+ #define R_CANFD_CFDTHL_ACC0_TMTS_Pos (16UL) /*!< TMTS (Bit 16) */
|
|
|
+ #define R_CANFD_CFDTHL_ACC0_TMTS_Msk (0xffff0000UL) /*!< TMTS (Bitfield-Mask: 0xffff) */
|
|
|
+/* ========================================================= ACC1 ========================================================== */
|
|
|
+ #define R_CANFD_CFDTHL_ACC1_TID_Pos (0UL) /*!< TID (Bit 0) */
|
|
|
+ #define R_CANFD_CFDTHL_ACC1_TID_Msk (0xffffUL) /*!< TID (Bitfield-Mask: 0xffff) */
|
|
|
+ #define R_CANFD_CFDTHL_ACC1_TIFL_Pos (16UL) /*!< TIFL (Bit 16) */
|
|
|
+ #define R_CANFD_CFDTHL_ACC1_TIFL_Msk (0x30000UL) /*!< TIFL (Bitfield-Mask: 0x03) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ CFDRF ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================== ID =========================================================== */
|
|
|
+ #define R_CANFD_CFDRF_ID_RFID_Pos (0UL) /*!< RFID (Bit 0) */
|
|
|
+ #define R_CANFD_CFDRF_ID_RFID_Msk (0x1fffffffUL) /*!< RFID (Bitfield-Mask: 0x1fffffff) */
|
|
|
+ #define R_CANFD_CFDRF_ID_RFRTR_Pos (30UL) /*!< RFRTR (Bit 30) */
|
|
|
+ #define R_CANFD_CFDRF_ID_RFRTR_Msk (0x40000000UL) /*!< RFRTR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDRF_ID_RFIDE_Pos (31UL) /*!< RFIDE (Bit 31) */
|
|
|
+ #define R_CANFD_CFDRF_ID_RFIDE_Msk (0x80000000UL) /*!< RFIDE (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================== PTR ========================================================== */
|
|
|
+ #define R_CANFD_CFDRF_PTR_RFTS_Pos (0UL) /*!< RFTS (Bit 0) */
|
|
|
+ #define R_CANFD_CFDRF_PTR_RFTS_Msk (0xffffUL) /*!< RFTS (Bitfield-Mask: 0xffff) */
|
|
|
+ #define R_CANFD_CFDRF_PTR_RFDLC_Pos (28UL) /*!< RFDLC (Bit 28) */
|
|
|
+ #define R_CANFD_CFDRF_PTR_RFDLC_Msk (0xf0000000UL) /*!< RFDLC (Bitfield-Mask: 0x0f) */
|
|
|
+/* ========================================================= FDSTS ========================================================= */
|
|
|
+ #define R_CANFD_CFDRF_FDSTS_RFESI_Pos (0UL) /*!< RFESI (Bit 0) */
|
|
|
+ #define R_CANFD_CFDRF_FDSTS_RFESI_Msk (0x1UL) /*!< RFESI (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDRF_FDSTS_RFBRS_Pos (1UL) /*!< RFBRS (Bit 1) */
|
|
|
+ #define R_CANFD_CFDRF_FDSTS_RFBRS_Msk (0x2UL) /*!< RFBRS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDRF_FDSTS_RFFDF_Pos (2UL) /*!< RFFDF (Bit 2) */
|
|
|
+ #define R_CANFD_CFDRF_FDSTS_RFFDF_Msk (0x4UL) /*!< RFFDF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDRF_FDSTS_RFIFL_Pos (8UL) /*!< RFIFL (Bit 8) */
|
|
|
+ #define R_CANFD_CFDRF_FDSTS_RFIFL_Msk (0x300UL) /*!< RFIFL (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_CANFD_CFDRF_FDSTS_RFPTR_Pos (16UL) /*!< RFPTR (Bit 16) */
|
|
|
+ #define R_CANFD_CFDRF_FDSTS_RFPTR_Msk (0xffff0000UL) /*!< RFPTR (Bitfield-Mask: 0xffff) */
|
|
|
+/* ========================================================== DF =========================================================== */
|
|
|
+ #define R_CANFD_CFDRF_DF_RFDB_Pos (0UL) /*!< RFDB (Bit 0) */
|
|
|
+ #define R_CANFD_CFDRF_DF_RFDB_Msk (0xffUL) /*!< RFDB (Bitfield-Mask: 0xff) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ CFDCF ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================== ID =========================================================== */
|
|
|
+ #define R_CANFD_CFDCF_ID_CFID_Pos (0UL) /*!< CFID (Bit 0) */
|
|
|
+ #define R_CANFD_CFDCF_ID_CFID_Msk (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff) */
|
|
|
+ #define R_CANFD_CFDCF_ID_CFRTR_Pos (30UL) /*!< CFRTR (Bit 30) */
|
|
|
+ #define R_CANFD_CFDCF_ID_CFRTR_Msk (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDCF_ID_CFIDE_Pos (31UL) /*!< CFIDE (Bit 31) */
|
|
|
+ #define R_CANFD_CFDCF_ID_CFIDE_Msk (0x80000000UL) /*!< CFIDE (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================== PTR ========================================================== */
|
|
|
+ #define R_CANFD_CFDCF_PTR_CFTS_Pos (0UL) /*!< CFTS (Bit 0) */
|
|
|
+ #define R_CANFD_CFDCF_PTR_CFTS_Msk (0xffffUL) /*!< CFTS (Bitfield-Mask: 0xffff) */
|
|
|
+ #define R_CANFD_CFDCF_PTR_CFDLC_Pos (28UL) /*!< CFDLC (Bit 28) */
|
|
|
+ #define R_CANFD_CFDCF_PTR_CFDLC_Msk (0xf0000000UL) /*!< CFDLC (Bitfield-Mask: 0x0f) */
|
|
|
+/* ========================================================= FDSTS ========================================================= */
|
|
|
+ #define R_CANFD_CFDCF_FDSTS_CFESI_Pos (0UL) /*!< CFESI (Bit 0) */
|
|
|
+ #define R_CANFD_CFDCF_FDSTS_CFESI_Msk (0x1UL) /*!< CFESI (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDCF_FDSTS_CFBRS_Pos (1UL) /*!< CFBRS (Bit 1) */
|
|
|
+ #define R_CANFD_CFDCF_FDSTS_CFBRS_Msk (0x2UL) /*!< CFBRS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDCF_FDSTS_CFFDF_Pos (2UL) /*!< CFFDF (Bit 2) */
|
|
|
+ #define R_CANFD_CFDCF_FDSTS_CFFDF_Msk (0x4UL) /*!< CFFDF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDCF_FDSTS_CFIFL_Pos (8UL) /*!< CFIFL (Bit 8) */
|
|
|
+ #define R_CANFD_CFDCF_FDSTS_CFIFL_Msk (0x300UL) /*!< CFIFL (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_CANFD_CFDCF_FDSTS_CFPTR_Pos (16UL) /*!< CFPTR (Bit 16) */
|
|
|
+ #define R_CANFD_CFDCF_FDSTS_CFPTR_Msk (0xffff0000UL) /*!< CFPTR (Bitfield-Mask: 0xffff) */
|
|
|
+/* ========================================================== DF =========================================================== */
|
|
|
+ #define R_CANFD_CFDCF_DF_CFDB_Pos (0UL) /*!< CFDB (Bit 0) */
|
|
|
+ #define R_CANFD_CFDCF_DF_CFDB_Msk (0xffUL) /*!< CFDB (Bitfield-Mask: 0xff) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ CFDTM ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================== ID =========================================================== */
|
|
|
+ #define R_CANFD_CFDTM_ID_TMID_Pos (0UL) /*!< TMID (Bit 0) */
|
|
|
+ #define R_CANFD_CFDTM_ID_TMID_Msk (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff) */
|
|
|
+ #define R_CANFD_CFDTM_ID_TMRTR_Pos (30UL) /*!< TMRTR (Bit 30) */
|
|
|
+ #define R_CANFD_CFDTM_ID_TMRTR_Msk (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDTM_ID_TMIDE_Pos (31UL) /*!< TMIDE (Bit 31) */
|
|
|
+ #define R_CANFD_CFDTM_ID_TMIDE_Msk (0x80000000UL) /*!< TMIDE (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================== PTR ========================================================== */
|
|
|
+ #define R_CANFD_CFDTM_PTR_TMTS_Pos (0UL) /*!< TMTS (Bit 0) */
|
|
|
+ #define R_CANFD_CFDTM_PTR_TMTS_Msk (0xffffUL) /*!< TMTS (Bitfield-Mask: 0xffff) */
|
|
|
+ #define R_CANFD_CFDTM_PTR_TMDLC_Pos (28UL) /*!< TMDLC (Bit 28) */
|
|
|
+ #define R_CANFD_CFDTM_PTR_TMDLC_Msk (0xf0000000UL) /*!< TMDLC (Bitfield-Mask: 0x0f) */
|
|
|
+/* ========================================================= FDCTR ========================================================= */
|
|
|
+ #define R_CANFD_CFDTM_FDCTR_TMESI_Pos (0UL) /*!< TMESI (Bit 0) */
|
|
|
+ #define R_CANFD_CFDTM_FDCTR_TMESI_Msk (0x1UL) /*!< TMESI (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDTM_FDCTR_TMBRS_Pos (1UL) /*!< TMBRS (Bit 1) */
|
|
|
+ #define R_CANFD_CFDTM_FDCTR_TMBRS_Msk (0x2UL) /*!< TMBRS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDTM_FDCTR_TMFDF_Pos (2UL) /*!< TMFDF (Bit 2) */
|
|
|
+ #define R_CANFD_CFDTM_FDCTR_TMFDF_Msk (0x4UL) /*!< TMFDF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDTM_FDCTR_TMIFL_Pos (8UL) /*!< TMIFL (Bit 8) */
|
|
|
+ #define R_CANFD_CFDTM_FDCTR_TMIFL_Msk (0x300UL) /*!< TMIFL (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_CANFD_CFDTM_FDCTR_TMPTR_Pos (16UL) /*!< TMPTR (Bit 16) */
|
|
|
+ #define R_CANFD_CFDTM_FDCTR_TMPTR_Msk (0xffff0000UL) /*!< TMPTR (Bitfield-Mask: 0xffff) */
|
|
|
+/* ========================================================== DF =========================================================== */
|
|
|
+ #define R_CANFD_CFDTM_DF_TMDB_Pos (0UL) /*!< TMDB (Bit 0) */
|
|
|
+ #define R_CANFD_CFDTM_DF_TMDB_Msk (0xffUL) /*!< TMDB (Bitfield-Mask: 0xff) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ RM ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================== ID =========================================================== */
|
|
|
+ #define R_CANFD_CFDRM_RM_ID_RMID_Pos (0UL) /*!< RMID (Bit 0) */
|
|
|
+ #define R_CANFD_CFDRM_RM_ID_RMID_Msk (0x1fffffffUL) /*!< RMID (Bitfield-Mask: 0x1fffffff) */
|
|
|
+ #define R_CANFD_CFDRM_RM_ID_RMRTR_Pos (30UL) /*!< RMRTR (Bit 30) */
|
|
|
+ #define R_CANFD_CFDRM_RM_ID_RMRTR_Msk (0x40000000UL) /*!< RMRTR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDRM_RM_ID_RMIDE_Pos (31UL) /*!< RMIDE (Bit 31) */
|
|
|
+ #define R_CANFD_CFDRM_RM_ID_RMIDE_Msk (0x80000000UL) /*!< RMIDE (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================== PTR ========================================================== */
|
|
|
+ #define R_CANFD_CFDRM_RM_PTR_RMTS_Pos (0UL) /*!< RMTS (Bit 0) */
|
|
|
+ #define R_CANFD_CFDRM_RM_PTR_RMTS_Msk (0xffffUL) /*!< RMTS (Bitfield-Mask: 0xffff) */
|
|
|
+ #define R_CANFD_CFDRM_RM_PTR_RMDLC_Pos (28UL) /*!< RMDLC (Bit 28) */
|
|
|
+ #define R_CANFD_CFDRM_RM_PTR_RMDLC_Msk (0xf0000000UL) /*!< RMDLC (Bitfield-Mask: 0x0f) */
|
|
|
+/* ========================================================= FDSTS ========================================================= */
|
|
|
+ #define R_CANFD_CFDRM_RM_FDSTS_RMESI_Pos (0UL) /*!< RMESI (Bit 0) */
|
|
|
+ #define R_CANFD_CFDRM_RM_FDSTS_RMESI_Msk (0x1UL) /*!< RMESI (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDRM_RM_FDSTS_RMBRS_Pos (1UL) /*!< RMBRS (Bit 1) */
|
|
|
+ #define R_CANFD_CFDRM_RM_FDSTS_RMBRS_Msk (0x2UL) /*!< RMBRS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDRM_RM_FDSTS_RMFDF_Pos (2UL) /*!< RMFDF (Bit 2) */
|
|
|
+ #define R_CANFD_CFDRM_RM_FDSTS_RMFDF_Msk (0x4UL) /*!< RMFDF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDRM_RM_FDSTS_RMIFL_Pos (8UL) /*!< RMIFL (Bit 8) */
|
|
|
+ #define R_CANFD_CFDRM_RM_FDSTS_RMIFL_Msk (0x300UL) /*!< RMIFL (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_CANFD_CFDRM_RM_FDSTS_RMPTR_Pos (16UL) /*!< RMPTR (Bit 16) */
|
|
|
+ #define R_CANFD_CFDRM_RM_FDSTS_RMPTR_Msk (0xffff0000UL) /*!< RMPTR (Bitfield-Mask: 0xffff) */
|
|
|
+/* ========================================================== DF =========================================================== */
|
|
|
+ #define R_CANFD_CFDRM_RM_DF_RMDB_Pos (0UL) /*!< RMDB (Bit 0) */
|
|
|
+ #define R_CANFD_CFDRM_RM_DF_RMDB_Msk (0xffUL) /*!< RMDB (Bitfield-Mask: 0xff) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ CFDRM ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ ELSEGR ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================== BY =========================================================== */
|
|
|
+ #define R_ELC_ELSEGR_BY_WI_Pos (7UL) /*!< WI (Bit 7) */
|
|
|
+ #define R_ELC_ELSEGR_BY_WI_Msk (0x80UL) /*!< WI (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ELC_ELSEGR_BY_WE_Pos (6UL) /*!< WE (Bit 6) */
|
|
|
+ #define R_ELC_ELSEGR_BY_WE_Msk (0x40UL) /*!< WE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ELC_ELSEGR_BY_SEG_Pos (0UL) /*!< SEG (Bit 0) */
|
|
|
+ #define R_ELC_ELSEGR_BY_SEG_Msk (0x1UL) /*!< SEG (Bitfield-Mask: 0x01) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ ELSR ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================== HA =========================================================== */
|
|
|
+ #define R_ELC_ELSR_HA_ELS_Pos (0UL) /*!< ELS (Bit 0) */
|
|
|
+ #define R_ELC_ELSR_HA_ELS_Msk (0x1ffUL) /*!< ELS (Bitfield-Mask: 0x1ff) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ SAR ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* =========================================================== L =========================================================== */
|
|
|
+ #define R_IIC0_SAR_L_SVA_Pos (0UL) /*!< SVA (Bit 0) */
|
|
|
+ #define R_IIC0_SAR_L_SVA_Msk (0xffUL) /*!< SVA (Bitfield-Mask: 0xff) */
|
|
|
+/* =========================================================== U =========================================================== */
|
|
|
+ #define R_IIC0_SAR_U_SVA9_Pos (2UL) /*!< SVA9 (Bit 2) */
|
|
|
+ #define R_IIC0_SAR_U_SVA9_Msk (0x4UL) /*!< SVA9 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_SAR_U_SVA8_Pos (1UL) /*!< SVA8 (Bit 1) */
|
|
|
+ #define R_IIC0_SAR_U_SVA8_Msk (0x2UL) /*!< SVA8 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_SAR_U_FS_Pos (0UL) /*!< FS (Bit 0) */
|
|
|
+ #define R_IIC0_SAR_U_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ REGION ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================== AC =========================================================== */
|
|
|
+ #define R_MPU_MMPU_GROUP_REGION_AC_PP_Pos (3UL) /*!< PP (Bit 3) */
|
|
|
+ #define R_MPU_MMPU_GROUP_REGION_AC_PP_Msk (0x8UL) /*!< PP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_MPU_MMPU_GROUP_REGION_AC_WP_Pos (2UL) /*!< WP (Bit 2) */
|
|
|
+ #define R_MPU_MMPU_GROUP_REGION_AC_WP_Msk (0x4UL) /*!< WP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_MPU_MMPU_GROUP_REGION_AC_RP_Pos (1UL) /*!< RP (Bit 1) */
|
|
|
+ #define R_MPU_MMPU_GROUP_REGION_AC_RP_Msk (0x2UL) /*!< RP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */
|
|
|
+ #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
|
|
|
+/* =========================================================== S =========================================================== */
|
|
|
+ #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Pos (0UL) /*!< MMPUS (Bit 0) */
|
|
|
+ #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Msk (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* =========================================================== E =========================================================== */
|
|
|
+ #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Pos (0UL) /*!< MMPUE (Bit 0) */
|
|
|
+ #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Msk (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ GROUP ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================== EN =========================================================== */
|
|
|
+ #define R_MPU_MMPU_GROUP_EN_KEY_Pos (8UL) /*!< KEY (Bit 8) */
|
|
|
+ #define R_MPU_MMPU_GROUP_EN_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_MPU_MMPU_GROUP_EN_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */
|
|
|
+ #define R_MPU_MMPU_GROUP_EN_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= ENPT ========================================================== */
|
|
|
+ #define R_MPU_MMPU_GROUP_ENPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */
|
|
|
+ #define R_MPU_MMPU_GROUP_ENPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */
|
|
|
+ #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================== RPT ========================================================== */
|
|
|
+ #define R_MPU_MMPU_GROUP_RPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */
|
|
|
+ #define R_MPU_MMPU_GROUP_RPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_MPU_MMPU_GROUP_RPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */
|
|
|
+ #define R_MPU_MMPU_GROUP_RPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== RPT_SEC ======================================================== */
|
|
|
+ #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Pos (8UL) /*!< KEY (Bit 8) */
|
|
|
+ #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */
|
|
|
+ #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ SP ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================== OAD ========================================================== */
|
|
|
+ #define R_MPU_SPMON_SP_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */
|
|
|
+ #define R_MPU_SPMON_SP_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_MPU_SPMON_SP_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */
|
|
|
+ #define R_MPU_SPMON_SP_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================== CTL ========================================================== */
|
|
|
+ #define R_MPU_SPMON_SP_CTL_ERROR_Pos (8UL) /*!< ERROR (Bit 8) */
|
|
|
+ #define R_MPU_SPMON_SP_CTL_ERROR_Msk (0x100UL) /*!< ERROR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_MPU_SPMON_SP_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */
|
|
|
+ #define R_MPU_SPMON_SP_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================== PT =========================================================== */
|
|
|
+ #define R_MPU_SPMON_SP_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */
|
|
|
+ #define R_MPU_SPMON_SP_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_MPU_SPMON_SP_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */
|
|
|
+ #define R_MPU_SPMON_SP_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================== SA =========================================================== */
|
|
|
+ #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos (0UL) /*!< MSPMPUSA (Bit 0) */
|
|
|
+ #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ========================================================== EA =========================================================== */
|
|
|
+ #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos (0UL) /*!< MSPMPUEA (Bit 0) */
|
|
|
+ #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ PIN ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ======================================================= PmnPFS_BY ======================================================= */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos (0UL) /*!< PODR (Bit 0) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos (2UL) /*!< PDR (Bit 2) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos (4UL) /*!< PCR (Bit 4) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= PmnPFS_HA ======================================================= */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos (0UL) /*!< PODR (Bit 0) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos (2UL) /*!< PDR (Bit 2) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos (4UL) /*!< PCR (Bit 4) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== PmnPFS ========================================================= */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos (0UL) /*!< PODR (Bit 0) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos (2UL) /*!< PDR (Bit 2) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos (4UL) /*!< PCR (Bit 4) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos (16UL) /*!< PMR (Bit 16) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk (0x10000UL) /*!< PMR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos (24UL) /*!< PSEL (Bit 24) */
|
|
|
+ #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ PORT ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ PMSAR ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================= PMSAR ========================================================= */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ RTCCR ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================= RTCCR ========================================================= */
|
|
|
+ #define R_RTC_RTCCR_RTCCR_TCEN_Pos (7UL) /*!< TCEN (Bit 7) */
|
|
|
+ #define R_RTC_RTCCR_RTCCR_TCEN_Msk (0x80UL) /*!< TCEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_RTC_RTCCR_RTCCR_TCNF_Pos (4UL) /*!< TCNF (Bit 4) */
|
|
|
+ #define R_RTC_RTCCR_RTCCR_TCNF_Msk (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_RTC_RTCCR_RTCCR_TCST_Pos (2UL) /*!< TCST (Bit 2) */
|
|
|
+ #define R_RTC_RTCCR_RTCCR_TCST_Msk (0x4UL) /*!< TCST (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_RTC_RTCCR_RTCCR_TCCT_Pos (0UL) /*!< TCCT (Bit 0) */
|
|
|
+ #define R_RTC_RTCCR_RTCCR_TCCT_Msk (0x3UL) /*!< TCCT (Bitfield-Mask: 0x03) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ CP ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================= RSEC ========================================================== */
|
|
|
+ #define R_RTC_CP_RSEC_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */
|
|
|
+ #define R_RTC_CP_RSEC_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_RTC_CP_RSEC_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */
|
|
|
+ #define R_RTC_CP_RSEC_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */
|
|
|
+/* ========================================================= BCNT0 ========================================================= */
|
|
|
+ #define R_RTC_CP_BCNT0_BCNT0CP_Pos (0UL) /*!< BCNT0CP (Bit 0) */
|
|
|
+ #define R_RTC_CP_BCNT0_BCNT0CP_Msk (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff) */
|
|
|
+/* ========================================================= RMIN ========================================================== */
|
|
|
+ #define R_RTC_CP_RMIN_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */
|
|
|
+ #define R_RTC_CP_RMIN_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_RTC_CP_RMIN_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */
|
|
|
+ #define R_RTC_CP_RMIN_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */
|
|
|
+/* ========================================================= BCNT1 ========================================================= */
|
|
|
+ #define R_RTC_CP_BCNT1_BCNT1CP_Pos (0UL) /*!< BCNT1CP (Bit 0) */
|
|
|
+ #define R_RTC_CP_BCNT1_BCNT1CP_Msk (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff) */
|
|
|
+/* ========================================================== RHR ========================================================== */
|
|
|
+ #define R_RTC_CP_RHR_PM_Pos (6UL) /*!< PM (Bit 6) */
|
|
|
+ #define R_RTC_CP_RHR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_RTC_CP_RHR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */
|
|
|
+ #define R_RTC_CP_RHR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_RTC_CP_RHR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */
|
|
|
+ #define R_RTC_CP_RHR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */
|
|
|
+/* ========================================================= BCNT2 ========================================================= */
|
|
|
+ #define R_RTC_CP_BCNT2_BCNT2CP_Pos (0UL) /*!< BCNT2CP (Bit 0) */
|
|
|
+ #define R_RTC_CP_BCNT2_BCNT2CP_Msk (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff) */
|
|
|
+/* ========================================================= RDAY ========================================================== */
|
|
|
+ #define R_RTC_CP_RDAY_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */
|
|
|
+ #define R_RTC_CP_RDAY_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_RTC_CP_RDAY_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */
|
|
|
+ #define R_RTC_CP_RDAY_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */
|
|
|
+/* ========================================================= BCNT3 ========================================================= */
|
|
|
+ #define R_RTC_CP_BCNT3_BCNT3CP_Pos (0UL) /*!< BCNT3CP (Bit 0) */
|
|
|
+ #define R_RTC_CP_BCNT3_BCNT3CP_Msk (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff) */
|
|
|
+/* ========================================================= RMON ========================================================== */
|
|
|
+ #define R_RTC_CP_RMON_MON10_Pos (4UL) /*!< MON10 (Bit 4) */
|
|
|
+ #define R_RTC_CP_RMON_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */
|
|
|
+ #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ PIPE_TR ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* =========================================================== E =========================================================== */
|
|
|
+ #define R_USB_FS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */
|
|
|
+ #define R_USB_FS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */
|
|
|
+ #define R_USB_FS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */
|
|
|
+/* =========================================================== N =========================================================== */
|
|
|
+ #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */
|
|
|
+ #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ PIPE_TR ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* =========================================================== E =========================================================== */
|
|
|
+ #define R_USB_HS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */
|
|
|
+ #define R_USB_HS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */
|
|
|
+ #define R_USB_HS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */
|
|
|
+/* =========================================================== N =========================================================== */
|
|
|
+ #define R_USB_HS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */
|
|
|
+ #define R_USB_HS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ CMCFGCS ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ======================================================== CMCFG0 ========================================================= */
|
|
|
+ #define R_XSPI_CMCFGCS_CMCFG0_FFMT_Pos (0UL) /*!< FFMT (Bit 0) */
|
|
|
+ #define R_XSPI_CMCFGCS_CMCFG0_FFMT_Msk (0x3UL) /*!< FFMT (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_XSPI_CMCFGCS_CMCFG0_ADDSIZE_Pos (2UL) /*!< ADDSIZE (Bit 2) */
|
|
|
+ #define R_XSPI_CMCFGCS_CMCFG0_ADDSIZE_Msk (0xcUL) /*!< ADDSIZE (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_XSPI_CMCFGCS_CMCFG0_WPBSTMD_Pos (4UL) /*!< WPBSTMD (Bit 4) */
|
|
|
+ #define R_XSPI_CMCFGCS_CMCFG0_WPBSTMD_Msk (0x10UL) /*!< WPBSTMD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_CMCFGCS_CMCFG0_ARYAMD_Pos (5UL) /*!< ARYAMD (Bit 5) */
|
|
|
+ #define R_XSPI_CMCFGCS_CMCFG0_ARYAMD_Msk (0x20UL) /*!< ARYAMD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_CMCFGCS_CMCFG0_ADDRPEN_Pos (16UL) /*!< ADDRPEN (Bit 16) */
|
|
|
+ #define R_XSPI_CMCFGCS_CMCFG0_ADDRPEN_Msk (0xff0000UL) /*!< ADDRPEN (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_XSPI_CMCFGCS_CMCFG0_ADDRPCD_Pos (24UL) /*!< ADDRPCD (Bit 24) */
|
|
|
+ #define R_XSPI_CMCFGCS_CMCFG0_ADDRPCD_Msk (0xff000000UL) /*!< ADDRPCD (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== CMCFG1 ========================================================= */
|
|
|
+ #define R_XSPI_CMCFGCS_CMCFG1_RDCMD_Pos (0UL) /*!< RDCMD (Bit 0) */
|
|
|
+ #define R_XSPI_CMCFGCS_CMCFG1_RDCMD_Msk (0xffffUL) /*!< RDCMD (Bitfield-Mask: 0xffff) */
|
|
|
+ #define R_XSPI_CMCFGCS_CMCFG1_RDLATE_Pos (16UL) /*!< RDLATE (Bit 16) */
|
|
|
+ #define R_XSPI_CMCFGCS_CMCFG1_RDLATE_Msk (0x1f0000UL) /*!< RDLATE (Bitfield-Mask: 0x1f) */
|
|
|
+/* ======================================================== CMCFG2 ========================================================= */
|
|
|
+ #define R_XSPI_CMCFGCS_CMCFG2_WRCMD_Pos (0UL) /*!< WRCMD (Bit 0) */
|
|
|
+ #define R_XSPI_CMCFGCS_CMCFG2_WRCMD_Msk (0xffffUL) /*!< WRCMD (Bitfield-Mask: 0xffff) */
|
|
|
+ #define R_XSPI_CMCFGCS_CMCFG2_WRLATE_Pos (16UL) /*!< WRLATE (Bit 16) */
|
|
|
+ #define R_XSPI_CMCFGCS_CMCFG2_WRLATE_Msk (0x1f0000UL) /*!< WRLATE (Bitfield-Mask: 0x1f) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ CDBUF ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================== CDT ========================================================== */
|
|
|
+ #define R_XSPI_CDBUF_CDT_CMDSIZE_Pos (0UL) /*!< CMDSIZE (Bit 0) */
|
|
|
+ #define R_XSPI_CDBUF_CDT_CMDSIZE_Msk (0x3UL) /*!< CMDSIZE (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_XSPI_CDBUF_CDT_ADDSIZE_Pos (2UL) /*!< ADDSIZE (Bit 2) */
|
|
|
+ #define R_XSPI_CDBUF_CDT_ADDSIZE_Msk (0x1cUL) /*!< ADDSIZE (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_XSPI_CDBUF_CDT_DATASIZE_Pos (5UL) /*!< DATASIZE (Bit 5) */
|
|
|
+ #define R_XSPI_CDBUF_CDT_DATASIZE_Msk (0x1e0UL) /*!< DATASIZE (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_XSPI_CDBUF_CDT_LATE_Pos (9UL) /*!< LATE (Bit 9) */
|
|
|
+ #define R_XSPI_CDBUF_CDT_LATE_Msk (0x3e00UL) /*!< LATE (Bitfield-Mask: 0x1f) */
|
|
|
+ #define R_XSPI_CDBUF_CDT_TRTYPE_Pos (15UL) /*!< TRTYPE (Bit 15) */
|
|
|
+ #define R_XSPI_CDBUF_CDT_TRTYPE_Msk (0x8000UL) /*!< TRTYPE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_CDBUF_CDT_CMD_Pos (16UL) /*!< CMD (Bit 16) */
|
|
|
+ #define R_XSPI_CDBUF_CDT_CMD_Msk (0xffff0000UL) /*!< CMD (Bitfield-Mask: 0xffff) */
|
|
|
+/* ========================================================== CDA ========================================================== */
|
|
|
+ #define R_XSPI_CDBUF_CDA_ADD_Pos (0UL) /*!< ADD (Bit 0) */
|
|
|
+ #define R_XSPI_CDBUF_CDA_ADD_Msk (0xffffffffUL) /*!< ADD (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ========================================================= CDD0 ========================================================== */
|
|
|
+ #define R_XSPI_CDBUF_CDD0_DATA_Pos (0UL) /*!< DATA (Bit 0) */
|
|
|
+ #define R_XSPI_CDBUF_CDD0_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ========================================================= CDD1 ========================================================== */
|
|
|
+ #define R_XSPI_CDBUF_CDD1_DATA_Pos (0UL) /*!< DATA (Bit 0) */
|
|
|
+ #define R_XSPI_CDBUF_CDD1_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ CCCTLCS ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ======================================================== CCCTL0 ========================================================= */
|
|
|
+ #define R_XSPI_CCCTLCS_CCCTL0_CAEN_Pos (0UL) /*!< CAEN (Bit 0) */
|
|
|
+ #define R_XSPI_CCCTLCS_CCCTL0_CAEN_Msk (0x1UL) /*!< CAEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_CCCTLCS_CCCTL0_CANOWR_Pos (1UL) /*!< CANOWR (Bit 1) */
|
|
|
+ #define R_XSPI_CCCTLCS_CCCTL0_CANOWR_Msk (0x2UL) /*!< CANOWR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_CCCTLCS_CCCTL0_CAITV_Pos (8UL) /*!< CAITV (Bit 8) */
|
|
|
+ #define R_XSPI_CCCTLCS_CCCTL0_CAITV_Msk (0x1f00UL) /*!< CAITV (Bitfield-Mask: 0x1f) */
|
|
|
+ #define R_XSPI_CCCTLCS_CCCTL0_CASFTSTA_Pos (16UL) /*!< CASFTSTA (Bit 16) */
|
|
|
+ #define R_XSPI_CCCTLCS_CCCTL0_CASFTSTA_Msk (0x1f0000UL) /*!< CASFTSTA (Bitfield-Mask: 0x1f) */
|
|
|
+ #define R_XSPI_CCCTLCS_CCCTL0_CASFTEND_Pos (24UL) /*!< CASFTEND (Bit 24) */
|
|
|
+ #define R_XSPI_CCCTLCS_CCCTL0_CASFTEND_Msk (0x1f000000UL) /*!< CASFTEND (Bitfield-Mask: 0x1f) */
|
|
|
+/* ======================================================== CCCTL1 ========================================================= */
|
|
|
+ #define R_XSPI_CCCTLCS_CCCTL1_CACMDSIZE_Pos (0UL) /*!< CACMDSIZE (Bit 0) */
|
|
|
+ #define R_XSPI_CCCTLCS_CCCTL1_CACMDSIZE_Msk (0x3UL) /*!< CACMDSIZE (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_XSPI_CCCTLCS_CCCTL1_CAADDSIZE_Pos (2UL) /*!< CAADDSIZE (Bit 2) */
|
|
|
+ #define R_XSPI_CCCTLCS_CCCTL1_CAADDSIZE_Msk (0x1cUL) /*!< CAADDSIZE (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_XSPI_CCCTLCS_CCCTL1_CADATASIZE_Pos (5UL) /*!< CADATASIZE (Bit 5) */
|
|
|
+ #define R_XSPI_CCCTLCS_CCCTL1_CADATASIZE_Msk (0x1e0UL) /*!< CADATASIZE (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_XSPI_CCCTLCS_CCCTL1_CAWRLATE_Pos (16UL) /*!< CAWRLATE (Bit 16) */
|
|
|
+ #define R_XSPI_CCCTLCS_CCCTL1_CAWRLATE_Msk (0x1f0000UL) /*!< CAWRLATE (Bitfield-Mask: 0x1f) */
|
|
|
+ #define R_XSPI_CCCTLCS_CCCTL1_CARDLATE_Pos (24UL) /*!< CARDLATE (Bit 24) */
|
|
|
+ #define R_XSPI_CCCTLCS_CCCTL1_CARDLATE_Msk (0x1f000000UL) /*!< CARDLATE (Bitfield-Mask: 0x1f) */
|
|
|
+/* ======================================================== CCCTL2 ========================================================= */
|
|
|
+ #define R_XSPI_CCCTLCS_CCCTL2_CAWRCMD_Pos (0UL) /*!< CAWRCMD (Bit 0) */
|
|
|
+ #define R_XSPI_CCCTLCS_CCCTL2_CAWRCMD_Msk (0xffffUL) /*!< CAWRCMD (Bitfield-Mask: 0xffff) */
|
|
|
+ #define R_XSPI_CCCTLCS_CCCTL2_CARDCMD_Pos (16UL) /*!< CARDCMD (Bit 16) */
|
|
|
+ #define R_XSPI_CCCTLCS_CCCTL2_CARDCMD_Msk (0xffff0000UL) /*!< CARDCMD (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================== CCCTL3 ========================================================= */
|
|
|
+ #define R_XSPI_CCCTLCS_CCCTL3_CAADD_Pos (0UL) /*!< CAADD (Bit 0) */
|
|
|
+ #define R_XSPI_CCCTLCS_CCCTL3_CAADD_Msk (0xffffffffUL) /*!< CAADD (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================== CCCTL4 ========================================================= */
|
|
|
+ #define R_XSPI_CCCTLCS_CCCTL4_CADATA_Pos (0UL) /*!< CADATA (Bit 0) */
|
|
|
+ #define R_XSPI_CCCTLCS_CCCTL4_CADATA_Msk (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================== CCCTL5 ========================================================= */
|
|
|
+ #define R_XSPI_CCCTLCS_CCCTL5_CADATA_Pos (0UL) /*!< CADATA (Bit 0) */
|
|
|
+ #define R_XSPI_CCCTLCS_CCCTL5_CADATA_Msk (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================== CCCTL6 ========================================================= */
|
|
|
+ #define R_XSPI_CCCTLCS_CCCTL6_CADATA_Pos (0UL) /*!< CADATA (Bit 0) */
|
|
|
+ #define R_XSPI_CCCTLCS_CCCTL6_CADATA_Msk (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================== CCCTL7 ========================================================= */
|
|
|
+ #define R_XSPI_CCCTLCS_CCCTL7_CADATA_Pos (0UL) /*!< CADATA (Bit 0) */
|
|
|
+ #define R_XSPI_CCCTLCS_CCCTL7_CADATA_Msk (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ CTRL ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================= AGTCR ========================================================= */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos (4UL) /*!< TEDGF (Bit 4) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Msk (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== AGTMR1 ========================================================= */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos (4UL) /*!< TCK (Bit 4) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Msk (0x70UL) /*!< TCK (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Pos (0UL) /*!< TMOD (Bit 0) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk (0x7UL) /*!< TMOD (Bitfield-Mask: 0x07) */
|
|
|
+/* ======================================================== AGTMR2 ========================================================= */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */
|
|
|
+/* ===================================================== AGTIOSEL_ALT ====================================================== */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Pos (4UL) /*!< TIES (Bit 4) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Pos (0UL) /*!< SEL (Bit 0) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */
|
|
|
+/* ======================================================== AGTIOC ========================================================= */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Pos (6UL) /*!< TIOGT (Bit 6) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos (0UL) /*!< TEDGSEL (Bit 0) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk (0x1UL) /*!< TEDGSEL (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== AGTISR ========================================================= */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Pos (2UL) /*!< EEPS (Bit 2) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk (0x4UL) /*!< EEPS (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== AGTCMSR ======================================================== */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= AGTIOSEL ======================================================== */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Pos (4UL) /*!< TIES (Bit 4) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Pos (0UL) /*!< SEL (Bit 0) */
|
|
|
+ #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ AGT16 ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================== AGT ========================================================== */
|
|
|
+ #define R_AGTX0_AGT16_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */
|
|
|
+ #define R_AGTX0_AGT16_AGT_AGT_Msk (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================== AGTCMA ========================================================= */
|
|
|
+ #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */
|
|
|
+ #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Msk (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================== AGTCMB ========================================================= */
|
|
|
+ #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */
|
|
|
+ #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Msk (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ AGT32 ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================== AGT ========================================================== */
|
|
|
+ #define R_AGTX0_AGT32_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */
|
|
|
+ #define R_AGTX0_AGT32_AGT_AGT_Msk (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================== AGTCMA ========================================================= */
|
|
|
+ #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */
|
|
|
+ #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Msk (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================== AGTCMB ========================================================= */
|
|
|
+ #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */
|
|
|
+ #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Msk (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ CFGD ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ======================================================== CFGD_L ========================================================= */
|
|
|
+ #define R_OFS_DATAFLASH_CFGDLOCK_CFGD_CFGD_L_CDLK_Pos (0UL) /*!< CDLK (Bit 0) */
|
|
|
+ #define R_OFS_DATAFLASH_CFGDLOCK_CFGD_CFGD_L_CDLK_Msk (0x1UL) /*!< CDLK (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== CFGD_H ========================================================= */
|
|
|
+ #define R_OFS_DATAFLASH_CFGDLOCK_CFGD_CFGD_H_CDLK_Pos (0UL) /*!< CDLK (Bit 0) */
|
|
|
+ #define R_OFS_DATAFLASH_CFGDLOCK_CFGD_CFGD_H_CDLK_Msk (0x1UL) /*!< CDLK (Bitfield-Mask: 0x01) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ CFGDLOCK ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================= CFGD2 ========================================================= */
|
|
|
+ #define R_OFS_DATAFLASH_CFGDLOCK_CFGD2_CDLK_Pos (0UL) /*!< CDLK (Bit 0) */
|
|
|
+ #define R_OFS_DATAFLASH_CFGDLOCK_CFGD2_CDLK_Msk (0x1UL) /*!< CDLK (Bitfield-Mask: 0x01) */
|
|
|
+
|
|
|
+/** @} */ /* End of group PosMask_clusters */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ Pos/Mask Peripheral Section ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/** @addtogroup PosMask_peripherals
|
|
|
+ * @{
|
|
|
+ */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_ACMPHS0 ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ======================================================== CMPCTL ========================================================= */
|
|
|
+ #define R_ACMPHS0_CMPCTL_HCMPON_Pos (7UL) /*!< HCMPON (Bit 7) */
|
|
|
+ #define R_ACMPHS0_CMPCTL_HCMPON_Msk (0x80UL) /*!< HCMPON (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ACMPHS0_CMPCTL_CDFS_Pos (5UL) /*!< CDFS (Bit 5) */
|
|
|
+ #define R_ACMPHS0_CMPCTL_CDFS_Msk (0x60UL) /*!< CDFS (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_ACMPHS0_CMPCTL_CEG_Pos (3UL) /*!< CEG (Bit 3) */
|
|
|
+ #define R_ACMPHS0_CMPCTL_CEG_Msk (0x18UL) /*!< CEG (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_ACMPHS0_CMPCTL_CSTEN_Pos (2UL) /*!< CSTEN (Bit 2) */
|
|
|
+ #define R_ACMPHS0_CMPCTL_CSTEN_Msk (0x4UL) /*!< CSTEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ACMPHS0_CMPCTL_COE_Pos (1UL) /*!< COE (Bit 1) */
|
|
|
+ #define R_ACMPHS0_CMPCTL_COE_Msk (0x2UL) /*!< COE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ACMPHS0_CMPCTL_CINV_Pos (0UL) /*!< CINV (Bit 0) */
|
|
|
+ #define R_ACMPHS0_CMPCTL_CINV_Msk (0x1UL) /*!< CINV (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== CMPSEL0 ======================================================== */
|
|
|
+ #define R_ACMPHS0_CMPSEL0_CMPSEL_Pos (0UL) /*!< CMPSEL (Bit 0) */
|
|
|
+ #define R_ACMPHS0_CMPSEL0_CMPSEL_Msk (0xfUL) /*!< CMPSEL (Bitfield-Mask: 0x0f) */
|
|
|
+/* ======================================================== CMPSEL1 ======================================================== */
|
|
|
+ #define R_ACMPHS0_CMPSEL1_CRVS_Pos (0UL) /*!< CRVS (Bit 0) */
|
|
|
+ #define R_ACMPHS0_CMPSEL1_CRVS_Msk (0x3fUL) /*!< CRVS (Bitfield-Mask: 0x3f) */
|
|
|
+/* ======================================================== CMPMON ========================================================= */
|
|
|
+ #define R_ACMPHS0_CMPMON_CMPMON_Pos (0UL) /*!< CMPMON (Bit 0) */
|
|
|
+ #define R_ACMPHS0_CMPMON_CMPMON_Msk (0x1UL) /*!< CMPMON (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= CPIOC ========================================================= */
|
|
|
+ #define R_ACMPHS0_CPIOC_VREFEN_Pos (7UL) /*!< VREFEN (Bit 7) */
|
|
|
+ #define R_ACMPHS0_CPIOC_VREFEN_Msk (0x80UL) /*!< VREFEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ACMPHS0_CPIOC_CPOE_Pos (0UL) /*!< CPOE (Bit 0) */
|
|
|
+ #define R_ACMPHS0_CPIOC_CPOE_Msk (0x1UL) /*!< CPOE (Bitfield-Mask: 0x01) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_ADC0 ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================= ADCSR ========================================================= */
|
|
|
+ #define R_ADC0_ADCSR_ADST_Pos (15UL) /*!< ADST (Bit 15) */
|
|
|
+ #define R_ADC0_ADCSR_ADST_Msk (0x8000UL) /*!< ADST (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADCSR_ADCS_Pos (13UL) /*!< ADCS (Bit 13) */
|
|
|
+ #define R_ADC0_ADCSR_ADCS_Msk (0x6000UL) /*!< ADCS (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_ADC0_ADCSR_ADHSC_Pos (10UL) /*!< ADHSC (Bit 10) */
|
|
|
+ #define R_ADC0_ADCSR_ADHSC_Msk (0x400UL) /*!< ADHSC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADCSR_TRGE_Pos (9UL) /*!< TRGE (Bit 9) */
|
|
|
+ #define R_ADC0_ADCSR_TRGE_Msk (0x200UL) /*!< TRGE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADCSR_EXTRG_Pos (8UL) /*!< EXTRG (Bit 8) */
|
|
|
+ #define R_ADC0_ADCSR_EXTRG_Msk (0x100UL) /*!< EXTRG (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADCSR_DBLE_Pos (7UL) /*!< DBLE (Bit 7) */
|
|
|
+ #define R_ADC0_ADCSR_DBLE_Msk (0x80UL) /*!< DBLE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADCSR_GBADIE_Pos (6UL) /*!< GBADIE (Bit 6) */
|
|
|
+ #define R_ADC0_ADCSR_GBADIE_Msk (0x40UL) /*!< GBADIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADCSR_DBLANS_Pos (0UL) /*!< DBLANS (Bit 0) */
|
|
|
+ #define R_ADC0_ADCSR_DBLANS_Msk (0x1fUL) /*!< DBLANS (Bitfield-Mask: 0x1f) */
|
|
|
+ #define R_ADC0_ADCSR_ADIE_Pos (12UL) /*!< ADIE (Bit 12) */
|
|
|
+ #define R_ADC0_ADCSR_ADIE_Msk (0x1000UL) /*!< ADIE (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== ADANSA ========================================================= */
|
|
|
+ #define R_ADC0_ADANSA_ANSA_Pos (0UL) /*!< ANSA (Bit 0) */
|
|
|
+ #define R_ADC0_ADANSA_ANSA_Msk (0x1UL) /*!< ANSA (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= ADADS ========================================================= */
|
|
|
+ #define R_ADC0_ADADS_ADS_Pos (0UL) /*!< ADS (Bit 0) */
|
|
|
+ #define R_ADC0_ADADS_ADS_Msk (0x1UL) /*!< ADS (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= ADADC ========================================================= */
|
|
|
+ #define R_ADC0_ADADC_ADC_Pos (0UL) /*!< ADC (Bit 0) */
|
|
|
+ #define R_ADC0_ADADC_ADC_Msk (0x7UL) /*!< ADC (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_ADC0_ADADC_AVEE_Pos (7UL) /*!< AVEE (Bit 7) */
|
|
|
+ #define R_ADC0_ADADC_AVEE_Msk (0x80UL) /*!< AVEE (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= ADCER ========================================================= */
|
|
|
+ #define R_ADC0_ADCER_ADRFMT_Pos (15UL) /*!< ADRFMT (Bit 15) */
|
|
|
+ #define R_ADC0_ADCER_ADRFMT_Msk (0x8000UL) /*!< ADRFMT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADCER_ADINV_Pos (14UL) /*!< ADINV (Bit 14) */
|
|
|
+ #define R_ADC0_ADCER_ADINV_Msk (0x4000UL) /*!< ADINV (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADCER_DIAGM_Pos (11UL) /*!< DIAGM (Bit 11) */
|
|
|
+ #define R_ADC0_ADCER_DIAGM_Msk (0x800UL) /*!< DIAGM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADCER_DIAGLD_Pos (10UL) /*!< DIAGLD (Bit 10) */
|
|
|
+ #define R_ADC0_ADCER_DIAGLD_Msk (0x400UL) /*!< DIAGLD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADCER_DIAGVAL_Pos (8UL) /*!< DIAGVAL (Bit 8) */
|
|
|
+ #define R_ADC0_ADCER_DIAGVAL_Msk (0x300UL) /*!< DIAGVAL (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_ADC0_ADCER_ACE_Pos (5UL) /*!< ACE (Bit 5) */
|
|
|
+ #define R_ADC0_ADCER_ACE_Msk (0x20UL) /*!< ACE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADCER_ADPRC_Pos (1UL) /*!< ADPRC (Bit 1) */
|
|
|
+ #define R_ADC0_ADCER_ADPRC_Msk (0x6UL) /*!< ADPRC (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_ADC0_ADCER_DCE_Pos (4UL) /*!< DCE (Bit 4) */
|
|
|
+ #define R_ADC0_ADCER_DCE_Msk (0x10UL) /*!< DCE (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== ADSTRGR ======================================================== */
|
|
|
+ #define R_ADC0_ADSTRGR_TRSA_Pos (8UL) /*!< TRSA (Bit 8) */
|
|
|
+ #define R_ADC0_ADSTRGR_TRSA_Msk (0x3f00UL) /*!< TRSA (Bitfield-Mask: 0x3f) */
|
|
|
+ #define R_ADC0_ADSTRGR_TRSB_Pos (0UL) /*!< TRSB (Bit 0) */
|
|
|
+ #define R_ADC0_ADSTRGR_TRSB_Msk (0x3fUL) /*!< TRSB (Bitfield-Mask: 0x3f) */
|
|
|
+/* ======================================================== ADEXICR ======================================================== */
|
|
|
+ #define R_ADC0_ADEXICR_OCSB_Pos (11UL) /*!< OCSB (Bit 11) */
|
|
|
+ #define R_ADC0_ADEXICR_OCSB_Msk (0x800UL) /*!< OCSB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADEXICR_TSSB_Pos (10UL) /*!< TSSB (Bit 10) */
|
|
|
+ #define R_ADC0_ADEXICR_TSSB_Msk (0x400UL) /*!< TSSB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADEXICR_OCSA_Pos (9UL) /*!< OCSA (Bit 9) */
|
|
|
+ #define R_ADC0_ADEXICR_OCSA_Msk (0x200UL) /*!< OCSA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADEXICR_TSSA_Pos (8UL) /*!< TSSA (Bit 8) */
|
|
|
+ #define R_ADC0_ADEXICR_TSSA_Msk (0x100UL) /*!< TSSA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADEXICR_OCSAD_Pos (1UL) /*!< OCSAD (Bit 1) */
|
|
|
+ #define R_ADC0_ADEXICR_OCSAD_Msk (0x2UL) /*!< OCSAD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADEXICR_TSSAD_Pos (0UL) /*!< TSSAD (Bit 0) */
|
|
|
+ #define R_ADC0_ADEXICR_TSSAD_Msk (0x1UL) /*!< TSSAD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADEXICR_EXSEL_Pos (14UL) /*!< EXSEL (Bit 14) */
|
|
|
+ #define R_ADC0_ADEXICR_EXSEL_Msk (0x4000UL) /*!< EXSEL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADEXICR_EXOEN_Pos (15UL) /*!< EXOEN (Bit 15) */
|
|
|
+ #define R_ADC0_ADEXICR_EXOEN_Msk (0x8000UL) /*!< EXOEN (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== ADANSB ========================================================= */
|
|
|
+ #define R_ADC0_ADANSB_ANSB_Pos (0UL) /*!< ANSB (Bit 0) */
|
|
|
+ #define R_ADC0_ADANSB_ANSB_Msk (0x1UL) /*!< ANSB (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== ADDBLDR ======================================================== */
|
|
|
+ #define R_ADC0_ADDBLDR_ADDBLDR_Pos (0UL) /*!< ADDBLDR (Bit 0) */
|
|
|
+ #define R_ADC0_ADDBLDR_ADDBLDR_Msk (0xffffUL) /*!< ADDBLDR (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================== ADTSDR ========================================================= */
|
|
|
+ #define R_ADC0_ADTSDR_ADTSDR_Pos (0UL) /*!< ADTSDR (Bit 0) */
|
|
|
+ #define R_ADC0_ADTSDR_ADTSDR_Msk (0xffffUL) /*!< ADTSDR (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================== ADOCDR ========================================================= */
|
|
|
+ #define R_ADC0_ADOCDR_ADOCDR_Pos (0UL) /*!< ADOCDR (Bit 0) */
|
|
|
+ #define R_ADC0_ADOCDR_ADOCDR_Msk (0xffffUL) /*!< ADOCDR (Bitfield-Mask: 0xffff) */
|
|
|
+/* ====================================================== ADRD_RIGHT ======================================================= */
|
|
|
+ #define R_ADC0_ADRD_RIGHT_DIAGST_Pos (14UL) /*!< DIAGST (Bit 14) */
|
|
|
+ #define R_ADC0_ADRD_RIGHT_DIAGST_Msk (0xc000UL) /*!< DIAGST (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_ADC0_ADRD_RIGHT_AD_Pos (0UL) /*!< AD (Bit 0) */
|
|
|
+ #define R_ADC0_ADRD_RIGHT_AD_Msk (0x3fffUL) /*!< AD (Bitfield-Mask: 0x3fff) */
|
|
|
+/* ======================================================= ADRD_LEFT ======================================================= */
|
|
|
+ #define R_ADC0_ADRD_LEFT_AD_Pos (2UL) /*!< AD (Bit 2) */
|
|
|
+ #define R_ADC0_ADRD_LEFT_AD_Msk (0xfffcUL) /*!< AD (Bitfield-Mask: 0x3fff) */
|
|
|
+ #define R_ADC0_ADRD_LEFT_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */
|
|
|
+ #define R_ADC0_ADRD_LEFT_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */
|
|
|
+/* ========================================================= ADDR ========================================================== */
|
|
|
+ #define R_ADC0_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */
|
|
|
+ #define R_ADC0_ADDR_ADDR_Msk (0xffffUL) /*!< ADDR (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================== ADSHCR ========================================================= */
|
|
|
+ #define R_ADC0_ADSHCR_SHANS2_Pos (10UL) /*!< SHANS2 (Bit 10) */
|
|
|
+ #define R_ADC0_ADSHCR_SHANS2_Msk (0x400UL) /*!< SHANS2 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADSHCR_SHANS1_Pos (9UL) /*!< SHANS1 (Bit 9) */
|
|
|
+ #define R_ADC0_ADSHCR_SHANS1_Msk (0x200UL) /*!< SHANS1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADSHCR_SHANS0_Pos (8UL) /*!< SHANS0 (Bit 8) */
|
|
|
+ #define R_ADC0_ADSHCR_SHANS0_Msk (0x100UL) /*!< SHANS0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADSHCR_SSTSH_Pos (0UL) /*!< SSTSH (Bit 0) */
|
|
|
+ #define R_ADC0_ADSHCR_SSTSH_Msk (0xffUL) /*!< SSTSH (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== ADDISCR ======================================================== */
|
|
|
+ #define R_ADC0_ADDISCR_CHARGE_Pos (4UL) /*!< CHARGE (Bit 4) */
|
|
|
+ #define R_ADC0_ADDISCR_CHARGE_Msk (0x10UL) /*!< CHARGE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADDISCR_ADNDIS_Pos (0UL) /*!< ADNDIS (Bit 0) */
|
|
|
+ #define R_ADC0_ADDISCR_ADNDIS_Msk (0xfUL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */
|
|
|
+/* ======================================================== ADSHMSR ======================================================== */
|
|
|
+ #define R_ADC0_ADSHMSR_SHMD_Pos (0UL) /*!< SHMD (Bit 0) */
|
|
|
+ #define R_ADC0_ADSHMSR_SHMD_Msk (0x1UL) /*!< SHMD (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== ADACSR ========================================================= */
|
|
|
+ #define R_ADC0_ADACSR_ADSAC_Pos (1UL) /*!< ADSAC (Bit 1) */
|
|
|
+ #define R_ADC0_ADACSR_ADSAC_Msk (0x2UL) /*!< ADSAC (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== ADGSPCR ======================================================== */
|
|
|
+ #define R_ADC0_ADGSPCR_GBRP_Pos (15UL) /*!< GBRP (Bit 15) */
|
|
|
+ #define R_ADC0_ADGSPCR_GBRP_Msk (0x8000UL) /*!< GBRP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADGSPCR_GBRSCN_Pos (1UL) /*!< GBRSCN (Bit 1) */
|
|
|
+ #define R_ADC0_ADGSPCR_GBRSCN_Msk (0x2UL) /*!< GBRSCN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADGSPCR_PGS_Pos (0UL) /*!< PGS (Bit 0) */
|
|
|
+ #define R_ADC0_ADGSPCR_PGS_Msk (0x1UL) /*!< PGS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADGSPCR_GBEXTRG_Pos (8UL) /*!< GBEXTRG (Bit 8) */
|
|
|
+ #define R_ADC0_ADGSPCR_GBEXTRG_Msk (0x100UL) /*!< GBEXTRG (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= ADICR ========================================================= */
|
|
|
+ #define R_ADC0_ADICR_ADIC_Pos (0UL) /*!< ADIC (Bit 0) */
|
|
|
+ #define R_ADC0_ADICR_ADIC_Msk (0x3UL) /*!< ADIC (Bitfield-Mask: 0x03) */
|
|
|
+/* ======================================================= ADDBLDRA ======================================================== */
|
|
|
+ #define R_ADC0_ADDBLDRA_ADDBLDRA_Pos (0UL) /*!< ADDBLDRA (Bit 0) */
|
|
|
+ #define R_ADC0_ADDBLDRA_ADDBLDRA_Msk (0xffffUL) /*!< ADDBLDRA (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================= ADDBLDRB ======================================================== */
|
|
|
+ #define R_ADC0_ADDBLDRB_ADDBLDRB_Pos (0UL) /*!< ADDBLDRB (Bit 0) */
|
|
|
+ #define R_ADC0_ADDBLDRB_ADDBLDRB_Msk (0xffffUL) /*!< ADDBLDRB (Bitfield-Mask: 0xffff) */
|
|
|
+/* ====================================================== ADHVREFCNT ======================================================= */
|
|
|
+ #define R_ADC0_ADHVREFCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */
|
|
|
+ #define R_ADC0_ADHVREFCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADHVREFCNT_LVSEL_Pos (4UL) /*!< LVSEL (Bit 4) */
|
|
|
+ #define R_ADC0_ADHVREFCNT_LVSEL_Msk (0x10UL) /*!< LVSEL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADHVREFCNT_HVSEL_Pos (0UL) /*!< HVSEL (Bit 0) */
|
|
|
+ #define R_ADC0_ADHVREFCNT_HVSEL_Msk (0x3UL) /*!< HVSEL (Bitfield-Mask: 0x03) */
|
|
|
+/* ======================================================= ADWINMON ======================================================== */
|
|
|
+ #define R_ADC0_ADWINMON_MONCMPB_Pos (5UL) /*!< MONCMPB (Bit 5) */
|
|
|
+ #define R_ADC0_ADWINMON_MONCMPB_Msk (0x20UL) /*!< MONCMPB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADWINMON_MONCMPA_Pos (4UL) /*!< MONCMPA (Bit 4) */
|
|
|
+ #define R_ADC0_ADWINMON_MONCMPA_Msk (0x10UL) /*!< MONCMPA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADWINMON_MONCOMB_Pos (0UL) /*!< MONCOMB (Bit 0) */
|
|
|
+ #define R_ADC0_ADWINMON_MONCOMB_Msk (0x1UL) /*!< MONCOMB (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== ADCMPCR ======================================================== */
|
|
|
+ #define R_ADC0_ADCMPCR_CMPAIE_Pos (15UL) /*!< CMPAIE (Bit 15) */
|
|
|
+ #define R_ADC0_ADCMPCR_CMPAIE_Msk (0x8000UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADCMPCR_WCMPE_Pos (14UL) /*!< WCMPE (Bit 14) */
|
|
|
+ #define R_ADC0_ADCMPCR_WCMPE_Msk (0x4000UL) /*!< WCMPE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADCMPCR_CMPBIE_Pos (13UL) /*!< CMPBIE (Bit 13) */
|
|
|
+ #define R_ADC0_ADCMPCR_CMPBIE_Msk (0x2000UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADCMPCR_CMPAE_Pos (11UL) /*!< CMPAE (Bit 11) */
|
|
|
+ #define R_ADC0_ADCMPCR_CMPAE_Msk (0x800UL) /*!< CMPAE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADCMPCR_CMPBE_Pos (9UL) /*!< CMPBE (Bit 9) */
|
|
|
+ #define R_ADC0_ADCMPCR_CMPBE_Msk (0x200UL) /*!< CMPBE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADCMPCR_CMPAB_Pos (0UL) /*!< CMPAB (Bit 0) */
|
|
|
+ #define R_ADC0_ADCMPCR_CMPAB_Msk (0x3UL) /*!< CMPAB (Bitfield-Mask: 0x03) */
|
|
|
+/* ====================================================== ADCMPANSER ======================================================= */
|
|
|
+ #define R_ADC0_ADCMPANSER_CMPOCA_Pos (1UL) /*!< CMPOCA (Bit 1) */
|
|
|
+ #define R_ADC0_ADCMPANSER_CMPOCA_Msk (0x2UL) /*!< CMPOCA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADCMPANSER_CMPTSA_Pos (0UL) /*!< CMPTSA (Bit 0) */
|
|
|
+ #define R_ADC0_ADCMPANSER_CMPTSA_Msk (0x1UL) /*!< CMPTSA (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= ADCMPLER ======================================================== */
|
|
|
+ #define R_ADC0_ADCMPLER_CMPLOCA_Pos (1UL) /*!< CMPLOCA (Bit 1) */
|
|
|
+ #define R_ADC0_ADCMPLER_CMPLOCA_Msk (0x2UL) /*!< CMPLOCA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADCMPLER_CMPLTSA_Pos (0UL) /*!< CMPLTSA (Bit 0) */
|
|
|
+ #define R_ADC0_ADCMPLER_CMPLTSA_Msk (0x1UL) /*!< CMPLTSA (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= ADCMPANSR ======================================================= */
|
|
|
+ #define R_ADC0_ADCMPANSR_CMPCHA_Pos (0UL) /*!< CMPCHA (Bit 0) */
|
|
|
+ #define R_ADC0_ADCMPANSR_CMPCHA_Msk (0x1UL) /*!< CMPCHA (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== ADCMPLR ======================================================== */
|
|
|
+ #define R_ADC0_ADCMPLR_CMPLCHA_Pos (0UL) /*!< CMPLCHA (Bit 0) */
|
|
|
+ #define R_ADC0_ADCMPLR_CMPLCHA_Msk (0x1UL) /*!< CMPLCHA (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= ADCMPDR0 ======================================================== */
|
|
|
+ #define R_ADC0_ADCMPDR0_ADCMPDR0_Pos (0UL) /*!< ADCMPDR0 (Bit 0) */
|
|
|
+ #define R_ADC0_ADCMPDR0_ADCMPDR0_Msk (0xffffUL) /*!< ADCMPDR0 (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================= ADCMPDR1 ======================================================== */
|
|
|
+ #define R_ADC0_ADCMPDR1_ADCMPDR1_Pos (0UL) /*!< ADCMPDR1 (Bit 0) */
|
|
|
+ #define R_ADC0_ADCMPDR1_ADCMPDR1_Msk (0xffffUL) /*!< ADCMPDR1 (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================== ADCMPSR ======================================================== */
|
|
|
+ #define R_ADC0_ADCMPSR_CMPSTCHA_Pos (0UL) /*!< CMPSTCHA (Bit 0) */
|
|
|
+ #define R_ADC0_ADCMPSR_CMPSTCHA_Msk (0x1UL) /*!< CMPSTCHA (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= ADCMPSER ======================================================== */
|
|
|
+ #define R_ADC0_ADCMPSER_CMPSTOCA_Pos (1UL) /*!< CMPSTOCA (Bit 1) */
|
|
|
+ #define R_ADC0_ADCMPSER_CMPSTOCA_Msk (0x2UL) /*!< CMPSTOCA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADCMPSER_CMPSTTSA_Pos (0UL) /*!< CMPSTTSA (Bit 0) */
|
|
|
+ #define R_ADC0_ADCMPSER_CMPSTTSA_Msk (0x1UL) /*!< CMPSTTSA (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= ADCMPBNSR ======================================================= */
|
|
|
+ #define R_ADC0_ADCMPBNSR_CMPLB_Pos (7UL) /*!< CMPLB (Bit 7) */
|
|
|
+ #define R_ADC0_ADCMPBNSR_CMPLB_Msk (0x80UL) /*!< CMPLB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADCMPBNSR_CMPCHB_Pos (0UL) /*!< CMPCHB (Bit 0) */
|
|
|
+ #define R_ADC0_ADCMPBNSR_CMPCHB_Msk (0x3fUL) /*!< CMPCHB (Bitfield-Mask: 0x3f) */
|
|
|
+/* ======================================================= ADWINLLB ======================================================== */
|
|
|
+ #define R_ADC0_ADWINLLB_ADWINLLB_Pos (0UL) /*!< ADWINLLB (Bit 0) */
|
|
|
+ #define R_ADC0_ADWINLLB_ADWINLLB_Msk (0xffffUL) /*!< ADWINLLB (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================= ADWINULB ======================================================== */
|
|
|
+ #define R_ADC0_ADWINULB_ADWINULB_Pos (0UL) /*!< ADWINULB (Bit 0) */
|
|
|
+ #define R_ADC0_ADWINULB_ADWINULB_Msk (0xffffUL) /*!< ADWINULB (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================= ADCMPBSR ======================================================== */
|
|
|
+ #define R_ADC0_ADCMPBSR_CMPSTB_Pos (0UL) /*!< CMPSTB (Bit 0) */
|
|
|
+ #define R_ADC0_ADCMPBSR_CMPSTB_Msk (0x1UL) /*!< CMPSTB (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== ADSSTRL ======================================================== */
|
|
|
+ #define R_ADC0_ADSSTRL_SST_Pos (0UL) /*!< SST (Bit 0) */
|
|
|
+ #define R_ADC0_ADSSTRL_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== ADSSTRT ======================================================== */
|
|
|
+ #define R_ADC0_ADSSTRT_SST_Pos (0UL) /*!< SST (Bit 0) */
|
|
|
+ #define R_ADC0_ADSSTRT_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== ADSSTRO ======================================================== */
|
|
|
+ #define R_ADC0_ADSSTRO_SST_Pos (0UL) /*!< SST (Bit 0) */
|
|
|
+ #define R_ADC0_ADSSTRO_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== ADSSTR ========================================================= */
|
|
|
+ #define R_ADC0_ADSSTR_SST_Pos (0UL) /*!< SST (Bit 0) */
|
|
|
+ #define R_ADC0_ADSSTR_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== ADPGACR ======================================================== */
|
|
|
+ #define R_ADC0_ADPGACR_P002GEN_Pos (11UL) /*!< P002GEN (Bit 11) */
|
|
|
+ #define R_ADC0_ADPGACR_P002GEN_Msk (0x800UL) /*!< P002GEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADPGACR_P002ENAMP_Pos (10UL) /*!< P002ENAMP (Bit 10) */
|
|
|
+ #define R_ADC0_ADPGACR_P002ENAMP_Msk (0x400UL) /*!< P002ENAMP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADPGACR_P002SEL1_Pos (9UL) /*!< P002SEL1 (Bit 9) */
|
|
|
+ #define R_ADC0_ADPGACR_P002SEL1_Msk (0x200UL) /*!< P002SEL1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADPGACR_P002SEL0_Pos (8UL) /*!< P002SEL0 (Bit 8) */
|
|
|
+ #define R_ADC0_ADPGACR_P002SEL0_Msk (0x100UL) /*!< P002SEL0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADPGACR_P001GEN_Pos (7UL) /*!< P001GEN (Bit 7) */
|
|
|
+ #define R_ADC0_ADPGACR_P001GEN_Msk (0x80UL) /*!< P001GEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADPGACR_P001ENAMP_Pos (6UL) /*!< P001ENAMP (Bit 6) */
|
|
|
+ #define R_ADC0_ADPGACR_P001ENAMP_Msk (0x40UL) /*!< P001ENAMP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADPGACR_P001SEL1_Pos (5UL) /*!< P001SEL1 (Bit 5) */
|
|
|
+ #define R_ADC0_ADPGACR_P001SEL1_Msk (0x20UL) /*!< P001SEL1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADPGACR_P001SEL0_Pos (4UL) /*!< P001SEL0 (Bit 4) */
|
|
|
+ #define R_ADC0_ADPGACR_P001SEL0_Msk (0x10UL) /*!< P001SEL0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADPGACR_P000GEN_Pos (3UL) /*!< P000GEN (Bit 3) */
|
|
|
+ #define R_ADC0_ADPGACR_P000GEN_Msk (0x8UL) /*!< P000GEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADPGACR_P000ENAMP_Pos (2UL) /*!< P000ENAMP (Bit 2) */
|
|
|
+ #define R_ADC0_ADPGACR_P000ENAMP_Msk (0x4UL) /*!< P000ENAMP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADPGACR_P000SEL1_Pos (1UL) /*!< P000SEL1 (Bit 1) */
|
|
|
+ #define R_ADC0_ADPGACR_P000SEL1_Msk (0x2UL) /*!< P000SEL1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADPGACR_P000SEL0_Pos (0UL) /*!< P000SEL0 (Bit 0) */
|
|
|
+ #define R_ADC0_ADPGACR_P000SEL0_Msk (0x1UL) /*!< P000SEL0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADPGACR_P003SEL0_Pos (12UL) /*!< P003SEL0 (Bit 12) */
|
|
|
+ #define R_ADC0_ADPGACR_P003SEL0_Msk (0x1000UL) /*!< P003SEL0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADPGACR_P003SEL1_Pos (13UL) /*!< P003SEL1 (Bit 13) */
|
|
|
+ #define R_ADC0_ADPGACR_P003SEL1_Msk (0x2000UL) /*!< P003SEL1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADPGACR_P003ENAMP_Pos (14UL) /*!< P003ENAMP (Bit 14) */
|
|
|
+ #define R_ADC0_ADPGACR_P003ENAMP_Msk (0x4000UL) /*!< P003ENAMP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADPGACR_P003GEN_Pos (15UL) /*!< P003GEN (Bit 15) */
|
|
|
+ #define R_ADC0_ADPGACR_P003GEN_Msk (0x8000UL) /*!< P003GEN (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= ADRD ========================================================== */
|
|
|
+ #define R_ADC0_ADRD_AD_Pos (0UL) /*!< AD (Bit 0) */
|
|
|
+ #define R_ADC0_ADRD_AD_Msk (0xffffUL) /*!< AD (Bitfield-Mask: 0xffff) */
|
|
|
+/* ========================================================= ADRST ========================================================= */
|
|
|
+ #define R_ADC0_ADRST_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */
|
|
|
+ #define R_ADC0_ADRST_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */
|
|
|
+/* ====================================================== VREFAMPCNT ======================================================= */
|
|
|
+ #define R_ADC0_VREFAMPCNT_VREFADCG_Pos (1UL) /*!< VREFADCG (Bit 1) */
|
|
|
+ #define R_ADC0_VREFAMPCNT_VREFADCG_Msk (0x6UL) /*!< VREFADCG (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_ADC0_VREFAMPCNT_VREFADCEN_Pos (3UL) /*!< VREFADCEN (Bit 3) */
|
|
|
+ #define R_ADC0_VREFAMPCNT_VREFADCEN_Msk (0x8UL) /*!< VREFADCEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_VREFAMPCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */
|
|
|
+ #define R_ADC0_VREFAMPCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_VREFAMPCNT_OLDETEN_Pos (0UL) /*!< OLDETEN (Bit 0) */
|
|
|
+ #define R_ADC0_VREFAMPCNT_OLDETEN_Msk (0x1UL) /*!< OLDETEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_VREFAMPCNT_BGREN_Pos (4UL) /*!< BGREN (Bit 4) */
|
|
|
+ #define R_ADC0_VREFAMPCNT_BGREN_Msk (0x10UL) /*!< BGREN (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= ADCALEXE ======================================================== */
|
|
|
+ #define R_ADC0_ADCALEXE_CALEXE_Pos (7UL) /*!< CALEXE (Bit 7) */
|
|
|
+ #define R_ADC0_ADCALEXE_CALEXE_Msk (0x80UL) /*!< CALEXE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADCALEXE_CALMON_Pos (6UL) /*!< CALMON (Bit 6) */
|
|
|
+ #define R_ADC0_ADCALEXE_CALMON_Msk (0x40UL) /*!< CALMON (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== ADANIM ========================================================= */
|
|
|
+ #define R_ADC0_ADANIM_ANIM_Pos (0UL) /*!< ANIM (Bit 0) */
|
|
|
+ #define R_ADC0_ADANIM_ANIM_Msk (0x1UL) /*!< ANIM (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= ADPGAGS0 ======================================================== */
|
|
|
+ #define R_ADC0_ADPGAGS0_P002GAIN_Pos (8UL) /*!< P002GAIN (Bit 8) */
|
|
|
+ #define R_ADC0_ADPGAGS0_P002GAIN_Msk (0xf00UL) /*!< P002GAIN (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_ADC0_ADPGAGS0_P001GAIN_Pos (4UL) /*!< P001GAIN (Bit 4) */
|
|
|
+ #define R_ADC0_ADPGAGS0_P001GAIN_Msk (0xf0UL) /*!< P001GAIN (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_ADC0_ADPGAGS0_P000GAIN_Pos (0UL) /*!< P000GAIN (Bit 0) */
|
|
|
+ #define R_ADC0_ADPGAGS0_P000GAIN_Msk (0xfUL) /*!< P000GAIN (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_ADC0_ADPGAGS0_P003GAIN_Pos (12UL) /*!< P003GAIN (Bit 12) */
|
|
|
+ #define R_ADC0_ADPGAGS0_P003GAIN_Msk (0xf000UL) /*!< P003GAIN (Bitfield-Mask: 0x0f) */
|
|
|
+/* ======================================================= ADPGADCR0 ======================================================= */
|
|
|
+ #define R_ADC0_ADPGADCR0_P003DG_Pos (12UL) /*!< P003DG (Bit 12) */
|
|
|
+ #define R_ADC0_ADPGADCR0_P003DG_Msk (0x3000UL) /*!< P003DG (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_ADC0_ADPGADCR0_P002DEN_Pos (11UL) /*!< P002DEN (Bit 11) */
|
|
|
+ #define R_ADC0_ADPGADCR0_P002DEN_Msk (0x800UL) /*!< P002DEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADPGADCR0_P002DG_Pos (8UL) /*!< P002DG (Bit 8) */
|
|
|
+ #define R_ADC0_ADPGADCR0_P002DG_Msk (0x300UL) /*!< P002DG (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_ADC0_ADPGADCR0_P001DEN_Pos (7UL) /*!< P001DEN (Bit 7) */
|
|
|
+ #define R_ADC0_ADPGADCR0_P001DEN_Msk (0x80UL) /*!< P001DEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADPGADCR0_P001DG_Pos (4UL) /*!< P001DG (Bit 4) */
|
|
|
+ #define R_ADC0_ADPGADCR0_P001DG_Msk (0x30UL) /*!< P001DG (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_ADC0_ADPGADCR0_P000DEN_Pos (3UL) /*!< P000DEN (Bit 3) */
|
|
|
+ #define R_ADC0_ADPGADCR0_P000DEN_Msk (0x8UL) /*!< P000DEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADPGADCR0_P000DG_Pos (0UL) /*!< P000DG (Bit 0) */
|
|
|
+ #define R_ADC0_ADPGADCR0_P000DG_Msk (0x3UL) /*!< P000DG (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_ADC0_ADPGADCR0_P003DEN_Pos (15UL) /*!< P003DEN (Bit 15) */
|
|
|
+ #define R_ADC0_ADPGADCR0_P003DEN_Msk (0x8000UL) /*!< P003DEN (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= ADREF ========================================================= */
|
|
|
+ #define R_ADC0_ADREF_ADF_Pos (0UL) /*!< ADF (Bit 0) */
|
|
|
+ #define R_ADC0_ADREF_ADF_Msk (0x1UL) /*!< ADF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADREF_ADSCACT_Pos (7UL) /*!< ADSCACT (Bit 7) */
|
|
|
+ #define R_ADC0_ADREF_ADSCACT_Msk (0x80UL) /*!< ADSCACT (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== ADEXREF ======================================================== */
|
|
|
+ #define R_ADC0_ADEXREF_GBADF_Pos (0UL) /*!< GBADF (Bit 0) */
|
|
|
+ #define R_ADC0_ADEXREF_GBADF_Msk (0x1UL) /*!< GBADF (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= ADAMPOFF ======================================================== */
|
|
|
+ #define R_ADC0_ADAMPOFF_OPOFF_Pos (0UL) /*!< OPOFF (Bit 0) */
|
|
|
+ #define R_ADC0_ADAMPOFF_OPOFF_Msk (0xffUL) /*!< OPOFF (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== ADTSTPR ======================================================== */
|
|
|
+ #define R_ADC0_ADTSTPR_PRO_Pos (0UL) /*!< PRO (Bit 0) */
|
|
|
+ #define R_ADC0_ADTSTPR_PRO_Msk (0x1UL) /*!< PRO (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADTSTPR_B0WI_Pos (1UL) /*!< B0WI (Bit 1) */
|
|
|
+ #define R_ADC0_ADTSTPR_B0WI_Msk (0x2UL) /*!< B0WI (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= ADDDACER ======================================================== */
|
|
|
+ #define R_ADC0_ADDDACER_WRION_Pos (0UL) /*!< WRION (Bit 0) */
|
|
|
+ #define R_ADC0_ADDDACER_WRION_Msk (0x1fUL) /*!< WRION (Bitfield-Mask: 0x1f) */
|
|
|
+ #define R_ADC0_ADDDACER_WRIOFF_Pos (8UL) /*!< WRIOFF (Bit 8) */
|
|
|
+ #define R_ADC0_ADDDACER_WRIOFF_Msk (0x1f00UL) /*!< WRIOFF (Bitfield-Mask: 0x1f) */
|
|
|
+ #define R_ADC0_ADDDACER_ADHS_Pos (15UL) /*!< ADHS (Bit 15) */
|
|
|
+ #define R_ADC0_ADDDACER_ADHS_Msk (0x8000UL) /*!< ADHS (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= ADEXTSTR ======================================================== */
|
|
|
+ #define R_ADC0_ADEXTSTR_SHTEST_Pos (0UL) /*!< SHTEST (Bit 0) */
|
|
|
+ #define R_ADC0_ADEXTSTR_SHTEST_Msk (0x7UL) /*!< SHTEST (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_ADC0_ADEXTSTR_SWTST_Pos (4UL) /*!< SWTST (Bit 4) */
|
|
|
+ #define R_ADC0_ADEXTSTR_SWTST_Msk (0x30UL) /*!< SWTST (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_ADC0_ADEXTSTR_SHTRM_Pos (8UL) /*!< SHTRM (Bit 8) */
|
|
|
+ #define R_ADC0_ADEXTSTR_SHTRM_Msk (0x300UL) /*!< SHTRM (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_ADC0_ADEXTSTR_ADTRM3_Pos (11UL) /*!< ADTRM3 (Bit 11) */
|
|
|
+ #define R_ADC0_ADEXTSTR_ADTRM3_Msk (0x800UL) /*!< ADTRM3 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADEXTSTR_ADTRM2_Pos (12UL) /*!< ADTRM2 (Bit 12) */
|
|
|
+ #define R_ADC0_ADEXTSTR_ADTRM2_Msk (0x3000UL) /*!< ADTRM2 (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_ADC0_ADEXTSTR_ADTRM1_Pos (14UL) /*!< ADTRM1 (Bit 14) */
|
|
|
+ #define R_ADC0_ADEXTSTR_ADTRM1_Msk (0xc000UL) /*!< ADTRM1 (Bitfield-Mask: 0x03) */
|
|
|
+/* ======================================================== ADTSTRA ======================================================== */
|
|
|
+ #define R_ADC0_ADTSTRA_ATBUSSEL_Pos (0UL) /*!< ATBUSSEL (Bit 0) */
|
|
|
+ #define R_ADC0_ADTSTRA_ATBUSSEL_Msk (0x1UL) /*!< ATBUSSEL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADTSTRA_TSTSWREF_Pos (1UL) /*!< TSTSWREF (Bit 1) */
|
|
|
+ #define R_ADC0_ADTSTRA_TSTSWREF_Msk (0xeUL) /*!< TSTSWREF (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_ADC0_ADTSTRA_OCSW_Pos (5UL) /*!< OCSW (Bit 5) */
|
|
|
+ #define R_ADC0_ADTSTRA_OCSW_Msk (0x20UL) /*!< OCSW (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADTSTRA_TSSW_Pos (6UL) /*!< TSSW (Bit 6) */
|
|
|
+ #define R_ADC0_ADTSTRA_TSSW_Msk (0x40UL) /*!< TSSW (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADTSTRA_ADTEST_AD_Pos (8UL) /*!< ADTEST_AD (Bit 8) */
|
|
|
+ #define R_ADC0_ADTSTRA_ADTEST_AD_Msk (0xf00UL) /*!< ADTEST_AD (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_ADC0_ADTSTRA_ADTEST_IO_Pos (12UL) /*!< ADTEST_IO (Bit 12) */
|
|
|
+ #define R_ADC0_ADTSTRA_ADTEST_IO_Msk (0xf000UL) /*!< ADTEST_IO (Bitfield-Mask: 0x0f) */
|
|
|
+/* ======================================================== ADTSTRB ======================================================== */
|
|
|
+ #define R_ADC0_ADTSTRB_ADVAL_Pos (0UL) /*!< ADVAL (Bit 0) */
|
|
|
+ #define R_ADC0_ADTSTRB_ADVAL_Msk (0x7fffUL) /*!< ADVAL (Bitfield-Mask: 0x7fff) */
|
|
|
+/* ======================================================== ADTSTRC ======================================================== */
|
|
|
+ #define R_ADC0_ADTSTRC_ADMD_Pos (0UL) /*!< ADMD (Bit 0) */
|
|
|
+ #define R_ADC0_ADTSTRC_ADMD_Msk (0xffUL) /*!< ADMD (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_ADC0_ADTSTRC_SYNCERR_Pos (12UL) /*!< SYNCERR (Bit 12) */
|
|
|
+ #define R_ADC0_ADTSTRC_SYNCERR_Msk (0x1000UL) /*!< SYNCERR (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== ADTSTRD ======================================================== */
|
|
|
+ #define R_ADC0_ADTSTRD_ADVAL16_Pos (0UL) /*!< ADVAL16 (Bit 0) */
|
|
|
+ #define R_ADC0_ADTSTRD_ADVAL16_Msk (0x1UL) /*!< ADVAL16 (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= ADSWTSTR0 ======================================================= */
|
|
|
+ #define R_ADC0_ADSWTSTR0_CHSW00_Pos (0UL) /*!< CHSW00 (Bit 0) */
|
|
|
+ #define R_ADC0_ADSWTSTR0_CHSW00_Msk (0x1UL) /*!< CHSW00 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADSWTSTR0_CHSW01_Pos (1UL) /*!< CHSW01 (Bit 1) */
|
|
|
+ #define R_ADC0_ADSWTSTR0_CHSW01_Msk (0x2UL) /*!< CHSW01 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADSWTSTR0_CHSW02_Pos (2UL) /*!< CHSW02 (Bit 2) */
|
|
|
+ #define R_ADC0_ADSWTSTR0_CHSW02_Msk (0x4UL) /*!< CHSW02 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADSWTSTR0_CHSW03_Pos (3UL) /*!< CHSW03 (Bit 3) */
|
|
|
+ #define R_ADC0_ADSWTSTR0_CHSW03_Msk (0x8UL) /*!< CHSW03 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADSWTSTR0_CHSW04_Pos (4UL) /*!< CHSW04 (Bit 4) */
|
|
|
+ #define R_ADC0_ADSWTSTR0_CHSW04_Msk (0x10UL) /*!< CHSW04 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADSWTSTR0_CHSW05_Pos (5UL) /*!< CHSW05 (Bit 5) */
|
|
|
+ #define R_ADC0_ADSWTSTR0_CHSW05_Msk (0x20UL) /*!< CHSW05 (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= ADSWTSTR1 ======================================================= */
|
|
|
+ #define R_ADC0_ADSWTSTR1_CHSW16_Pos (0UL) /*!< CHSW16 (Bit 0) */
|
|
|
+ #define R_ADC0_ADSWTSTR1_CHSW16_Msk (0x1UL) /*!< CHSW16 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADSWTSTR1_CHSW17_Pos (1UL) /*!< CHSW17 (Bit 1) */
|
|
|
+ #define R_ADC0_ADSWTSTR1_CHSW17_Msk (0x2UL) /*!< CHSW17 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADSWTSTR1_CHSW18_Pos (2UL) /*!< CHSW18 (Bit 2) */
|
|
|
+ #define R_ADC0_ADSWTSTR1_CHSW18_Msk (0x4UL) /*!< CHSW18 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADSWTSTR1_CHSW19_Pos (3UL) /*!< CHSW19 (Bit 3) */
|
|
|
+ #define R_ADC0_ADSWTSTR1_CHSW19_Msk (0x8UL) /*!< CHSW19 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADSWTSTR1_CHSW20_Pos (4UL) /*!< CHSW20 (Bit 4) */
|
|
|
+ #define R_ADC0_ADSWTSTR1_CHSW20_Msk (0x10UL) /*!< CHSW20 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADSWTSTR1_CHSW21_Pos (5UL) /*!< CHSW21 (Bit 5) */
|
|
|
+ #define R_ADC0_ADSWTSTR1_CHSW21_Msk (0x20UL) /*!< CHSW21 (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= ADSWTSTR2 ======================================================= */
|
|
|
+ #define R_ADC0_ADSWTSTR2_EX0SW_Pos (0UL) /*!< EX0SW (Bit 0) */
|
|
|
+ #define R_ADC0_ADSWTSTR2_EX0SW_Msk (0x1UL) /*!< EX0SW (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADSWTSTR2_EX1SW_Pos (1UL) /*!< EX1SW (Bit 1) */
|
|
|
+ #define R_ADC0_ADSWTSTR2_EX1SW_Msk (0x2UL) /*!< EX1SW (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADSWTSTR2_SHBYPS0_Pos (4UL) /*!< SHBYPS0 (Bit 4) */
|
|
|
+ #define R_ADC0_ADSWTSTR2_SHBYPS0_Msk (0x10UL) /*!< SHBYPS0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADSWTSTR2_SHBYPS1_Pos (5UL) /*!< SHBYPS1 (Bit 5) */
|
|
|
+ #define R_ADC0_ADSWTSTR2_SHBYPS1_Msk (0x20UL) /*!< SHBYPS1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADSWTSTR2_SHBYPS2_Pos (6UL) /*!< SHBYPS2 (Bit 6) */
|
|
|
+ #define R_ADC0_ADSWTSTR2_SHBYPS2_Msk (0x40UL) /*!< SHBYPS2 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADSWTSTR2_GRP0SW_Pos (8UL) /*!< GRP0SW (Bit 8) */
|
|
|
+ #define R_ADC0_ADSWTSTR2_GRP0SW_Msk (0x100UL) /*!< GRP0SW (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADSWTSTR2_GRP1SW_Pos (9UL) /*!< GRP1SW (Bit 9) */
|
|
|
+ #define R_ADC0_ADSWTSTR2_GRP1SW_Msk (0x200UL) /*!< GRP1SW (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADSWTSTR2_GRP2SW_Pos (10UL) /*!< GRP2SW (Bit 10) */
|
|
|
+ #define R_ADC0_ADSWTSTR2_GRP2SW_Msk (0x400UL) /*!< GRP2SW (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADSWTSTR2_GRP3SW_Pos (11UL) /*!< GRP3SW (Bit 11) */
|
|
|
+ #define R_ADC0_ADSWTSTR2_GRP3SW_Msk (0x800UL) /*!< GRP3SW (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ADC0_ADSWTSTR2_GRPEX1SW_Pos (12UL) /*!< GRPEX1SW (Bit 12) */
|
|
|
+ #define R_ADC0_ADSWTSTR2_GRPEX1SW_Msk (0x1000UL) /*!< GRPEX1SW (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== ADSWCR ========================================================= */
|
|
|
+ #define R_ADC0_ADSWCR_ADSWREF_Pos (0UL) /*!< ADSWREF (Bit 0) */
|
|
|
+ #define R_ADC0_ADSWCR_ADSWREF_Msk (0x7UL) /*!< ADSWREF (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_ADC0_ADSWCR_SHSWREF_Pos (4UL) /*!< SHSWREF (Bit 4) */
|
|
|
+ #define R_ADC0_ADSWCR_SHSWREF_Msk (0x70UL) /*!< SHSWREF (Bitfield-Mask: 0x07) */
|
|
|
+/* ======================================================== ADGSCS ========================================================= */
|
|
|
+ #define R_ADC0_ADGSCS_CHSELGB_Pos (0UL) /*!< CHSELGB (Bit 0) */
|
|
|
+ #define R_ADC0_ADGSCS_CHSELGB_Msk (0xffUL) /*!< CHSELGB (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_ADC0_ADGSCS_CHSELGA_Pos (8UL) /*!< CHSELGA (Bit 8) */
|
|
|
+ #define R_ADC0_ADGSCS_CHSELGA_Msk (0xff00UL) /*!< CHSELGA (Bitfield-Mask: 0xff) */
|
|
|
+/* ========================================================= ADSER ========================================================= */
|
|
|
+ #define R_ADC0_ADSER_SMPEX_Pos (7UL) /*!< SMPEX (Bit 7) */
|
|
|
+ #define R_ADC0_ADSER_SMPEX_Msk (0x80UL) /*!< SMPEX (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== ADBUF0 ========================================================= */
|
|
|
+ #define R_ADC0_ADBUF0_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
|
|
|
+ #define R_ADC0_ADBUF0_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================== ADBUF1 ========================================================= */
|
|
|
+ #define R_ADC0_ADBUF1_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
|
|
|
+ #define R_ADC0_ADBUF1_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================== ADBUF2 ========================================================= */
|
|
|
+ #define R_ADC0_ADBUF2_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
|
|
|
+ #define R_ADC0_ADBUF2_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================== ADBUF3 ========================================================= */
|
|
|
+ #define R_ADC0_ADBUF3_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
|
|
|
+ #define R_ADC0_ADBUF3_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================== ADBUF4 ========================================================= */
|
|
|
+ #define R_ADC0_ADBUF4_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
|
|
|
+ #define R_ADC0_ADBUF4_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================== ADBUF5 ========================================================= */
|
|
|
+ #define R_ADC0_ADBUF5_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
|
|
|
+ #define R_ADC0_ADBUF5_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================== ADBUF6 ========================================================= */
|
|
|
+ #define R_ADC0_ADBUF6_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
|
|
|
+ #define R_ADC0_ADBUF6_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================== ADBUF7 ========================================================= */
|
|
|
+ #define R_ADC0_ADBUF7_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
|
|
|
+ #define R_ADC0_ADBUF7_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================== ADBUF8 ========================================================= */
|
|
|
+ #define R_ADC0_ADBUF8_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
|
|
|
+ #define R_ADC0_ADBUF8_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================== ADBUF9 ========================================================= */
|
|
|
+ #define R_ADC0_ADBUF9_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
|
|
|
+ #define R_ADC0_ADBUF9_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================== ADBUF10 ======================================================== */
|
|
|
+ #define R_ADC0_ADBUF10_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
|
|
|
+ #define R_ADC0_ADBUF10_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================== ADBUF11 ======================================================== */
|
|
|
+ #define R_ADC0_ADBUF11_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
|
|
|
+ #define R_ADC0_ADBUF11_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================== ADBUF12 ======================================================== */
|
|
|
+ #define R_ADC0_ADBUF12_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
|
|
|
+ #define R_ADC0_ADBUF12_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================== ADBUF13 ======================================================== */
|
|
|
+ #define R_ADC0_ADBUF13_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
|
|
|
+ #define R_ADC0_ADBUF13_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================== ADBUF14 ======================================================== */
|
|
|
+ #define R_ADC0_ADBUF14_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
|
|
|
+ #define R_ADC0_ADBUF14_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================== ADBUF15 ======================================================== */
|
|
|
+ #define R_ADC0_ADBUF15_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */
|
|
|
+ #define R_ADC0_ADBUF15_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================== ADBUFEN ======================================================== */
|
|
|
+ #define R_ADC0_ADBUFEN_BUFEN_Pos (0UL) /*!< BUFEN (Bit 0) */
|
|
|
+ #define R_ADC0_ADBUFEN_BUFEN_Msk (0x1UL) /*!< BUFEN (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= ADBUFPTR ======================================================== */
|
|
|
+ #define R_ADC0_ADBUFPTR_BUFPTR_Pos (0UL) /*!< BUFPTR (Bit 0) */
|
|
|
+ #define R_ADC0_ADBUFPTR_BUFPTR_Msk (0xfUL) /*!< BUFPTR (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_ADC0_ADBUFPTR_PTROVF_Pos (4UL) /*!< PTROVF (Bit 4) */
|
|
|
+ #define R_ADC0_ADBUFPTR_PTROVF_Msk (0x10UL) /*!< PTROVF (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= ADPGADBS0 ======================================================= */
|
|
|
+ #define R_ADC0_ADPGADBS0_P0BIAS_Pos (0UL) /*!< P0BIAS (Bit 0) */
|
|
|
+ #define R_ADC0_ADPGADBS0_P0BIAS_Msk (0x1UL) /*!< P0BIAS (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= ADPGADBS1 ======================================================= */
|
|
|
+ #define R_ADC0_ADPGADBS1_P3BIAS_Pos (0UL) /*!< P3BIAS (Bit 0) */
|
|
|
+ #define R_ADC0_ADPGADBS1_P3BIAS_Msk (0x1UL) /*!< P3BIAS (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= ADREFMON ======================================================== */
|
|
|
+ #define R_ADC0_ADREFMON_PGAMON_Pos (0UL) /*!< PGAMON (Bit 0) */
|
|
|
+ #define R_ADC0_ADREFMON_PGAMON_Msk (0x7UL) /*!< PGAMON (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_ADC0_ADREFMON_MONSEL_Pos (16UL) /*!< MONSEL (Bit 16) */
|
|
|
+ #define R_ADC0_ADREFMON_MONSEL_Msk (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_PSCU ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================= PSARB ========================================================= */
|
|
|
+ #define R_PSCU_PSARB_PSARB4_Pos (4UL) /*!< PSARB4 (Bit 4) */
|
|
|
+ #define R_PSCU_PSARB_PSARB4_Msk (0x10UL) /*!< PSARB4 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARB_PSARB8_Pos (8UL) /*!< PSARB8 (Bit 8) */
|
|
|
+ #define R_PSCU_PSARB_PSARB8_Msk (0x100UL) /*!< PSARB8 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARB_PSARB9_Pos (9UL) /*!< PSARB9 (Bit 9) */
|
|
|
+ #define R_PSCU_PSARB_PSARB9_Msk (0x200UL) /*!< PSARB9 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARB_PSARB11_Pos (11UL) /*!< PSARB11 (Bit 11) */
|
|
|
+ #define R_PSCU_PSARB_PSARB11_Msk (0x800UL) /*!< PSARB11 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARB_PSARB12_Pos (12UL) /*!< PSARB12 (Bit 12) */
|
|
|
+ #define R_PSCU_PSARB_PSARB12_Msk (0x1000UL) /*!< PSARB12 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARB_PSARB15_Pos (15UL) /*!< PSARB15 (Bit 15) */
|
|
|
+ #define R_PSCU_PSARB_PSARB15_Msk (0x8000UL) /*!< PSARB15 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARB_PSARB16_Pos (16UL) /*!< PSARB16 (Bit 16) */
|
|
|
+ #define R_PSCU_PSARB_PSARB16_Msk (0x10000UL) /*!< PSARB16 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARB_PSARB18_Pos (18UL) /*!< PSARB18 (Bit 18) */
|
|
|
+ #define R_PSCU_PSARB_PSARB18_Msk (0x40000UL) /*!< PSARB18 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARB_PSARB19_Pos (19UL) /*!< PSARB19 (Bit 19) */
|
|
|
+ #define R_PSCU_PSARB_PSARB19_Msk (0x80000UL) /*!< PSARB19 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARB_PSARB22_Pos (22UL) /*!< PSARB22 (Bit 22) */
|
|
|
+ #define R_PSCU_PSARB_PSARB22_Msk (0x400000UL) /*!< PSARB22 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARB_PSARB27_Pos (27UL) /*!< PSARB27 (Bit 27) */
|
|
|
+ #define R_PSCU_PSARB_PSARB27_Msk (0x8000000UL) /*!< PSARB27 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARB_PSARB28_Pos (28UL) /*!< PSARB28 (Bit 28) */
|
|
|
+ #define R_PSCU_PSARB_PSARB28_Msk (0x10000000UL) /*!< PSARB28 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARB_PSARB29_Pos (29UL) /*!< PSARB29 (Bit 29) */
|
|
|
+ #define R_PSCU_PSARB_PSARB29_Msk (0x20000000UL) /*!< PSARB29 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARB_PSARB30_Pos (30UL) /*!< PSARB30 (Bit 30) */
|
|
|
+ #define R_PSCU_PSARB_PSARB30_Msk (0x40000000UL) /*!< PSARB30 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARB_PSARB31_Pos (31UL) /*!< PSARB31 (Bit 31) */
|
|
|
+ #define R_PSCU_PSARB_PSARB31_Msk (0x80000000UL) /*!< PSARB31 (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= PSARC ========================================================= */
|
|
|
+ #define R_PSCU_PSARC_PSARC0_Pos (0UL) /*!< PSARC0 (Bit 0) */
|
|
|
+ #define R_PSCU_PSARC_PSARC0_Msk (0x1UL) /*!< PSARC0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARC_PSARC1_Pos (1UL) /*!< PSARC1 (Bit 1) */
|
|
|
+ #define R_PSCU_PSARC_PSARC1_Msk (0x2UL) /*!< PSARC1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARC_PSARC7_Pos (7UL) /*!< PSARC7 (Bit 7) */
|
|
|
+ #define R_PSCU_PSARC_PSARC7_Msk (0x80UL) /*!< PSARC7 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARC_PSARC8_Pos (8UL) /*!< PSARC8 (Bit 8) */
|
|
|
+ #define R_PSCU_PSARC_PSARC8_Msk (0x100UL) /*!< PSARC8 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARC_PSARC11_Pos (11UL) /*!< PSARC11 (Bit 11) */
|
|
|
+ #define R_PSCU_PSARC_PSARC11_Msk (0x800UL) /*!< PSARC11 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARC_PSARC12_Pos (12UL) /*!< PSARC12 (Bit 12) */
|
|
|
+ #define R_PSCU_PSARC_PSARC12_Msk (0x1000UL) /*!< PSARC12 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARC_PSARC13_Pos (13UL) /*!< PSARC13 (Bit 13) */
|
|
|
+ #define R_PSCU_PSARC_PSARC13_Msk (0x2000UL) /*!< PSARC13 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARC_PSARC15_Pos (15UL) /*!< PSARC15 (Bit 15) */
|
|
|
+ #define R_PSCU_PSARC_PSARC15_Msk (0x8000UL) /*!< PSARC15 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARC_PSARC16_Pos (16UL) /*!< PSARC16 (Bit 16) */
|
|
|
+ #define R_PSCU_PSARC_PSARC16_Msk (0x10000UL) /*!< PSARC16 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARC_PSARC26_Pos (26UL) /*!< PSARC26 (Bit 26) */
|
|
|
+ #define R_PSCU_PSARC_PSARC26_Msk (0x4000000UL) /*!< PSARC26 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARC_PSARC27_Pos (27UL) /*!< PSARC27 (Bit 27) */
|
|
|
+ #define R_PSCU_PSARC_PSARC27_Msk (0x8000000UL) /*!< PSARC27 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARC_PSARC31_Pos (31UL) /*!< PSARC31 (Bit 31) */
|
|
|
+ #define R_PSCU_PSARC_PSARC31_Msk (0x80000000UL) /*!< PSARC31 (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= PSARD ========================================================= */
|
|
|
+ #define R_PSCU_PSARD_PSARD4_Pos (4UL) /*!< PSARD4 (Bit 4) */
|
|
|
+ #define R_PSCU_PSARD_PSARD4_Msk (0x10UL) /*!< PSARD4 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARD_PSARD5_Pos (5UL) /*!< PSARD5 (Bit 5) */
|
|
|
+ #define R_PSCU_PSARD_PSARD5_Msk (0x20UL) /*!< PSARD5 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARD_PSARD11_Pos (11UL) /*!< PSARD11 (Bit 11) */
|
|
|
+ #define R_PSCU_PSARD_PSARD11_Msk (0x800UL) /*!< PSARD11 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARD_PSARD12_Pos (12UL) /*!< PSARD12 (Bit 12) */
|
|
|
+ #define R_PSCU_PSARD_PSARD12_Msk (0x1000UL) /*!< PSARD12 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARD_PSARD13_Pos (13UL) /*!< PSARD13 (Bit 13) */
|
|
|
+ #define R_PSCU_PSARD_PSARD13_Msk (0x2000UL) /*!< PSARD13 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARD_PSARD14_Pos (14UL) /*!< PSARD14 (Bit 14) */
|
|
|
+ #define R_PSCU_PSARD_PSARD14_Msk (0x4000UL) /*!< PSARD14 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARD_PSARD15_Pos (15UL) /*!< PSARD15 (Bit 15) */
|
|
|
+ #define R_PSCU_PSARD_PSARD15_Msk (0x8000UL) /*!< PSARD15 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARD_PSARD16_Pos (16UL) /*!< PSARD16 (Bit 16) */
|
|
|
+ #define R_PSCU_PSARD_PSARD16_Msk (0x10000UL) /*!< PSARD16 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARD_PSARD20_Pos (20UL) /*!< PSARD20 (Bit 20) */
|
|
|
+ #define R_PSCU_PSARD_PSARD20_Msk (0x100000UL) /*!< PSARD20 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARD_PSARD22_Pos (22UL) /*!< PSARD22 (Bit 22) */
|
|
|
+ #define R_PSCU_PSARD_PSARD22_Msk (0x400000UL) /*!< PSARD22 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARD_PSARD27_Pos (27UL) /*!< PSARD27 (Bit 27) */
|
|
|
+ #define R_PSCU_PSARD_PSARD27_Msk (0x8000000UL) /*!< PSARD27 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARD_PSARD28_Pos (28UL) /*!< PSARD28 (Bit 28) */
|
|
|
+ #define R_PSCU_PSARD_PSARD28_Msk (0x10000000UL) /*!< PSARD28 (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= PSARE ========================================================= */
|
|
|
+ #define R_PSCU_PSARE_PSARE1_Pos (1UL) /*!< PSARE1 (Bit 1) */
|
|
|
+ #define R_PSCU_PSARE_PSARE1_Msk (0x2UL) /*!< PSARE1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARE_PSARE2_Pos (2UL) /*!< PSARE2 (Bit 2) */
|
|
|
+ #define R_PSCU_PSARE_PSARE2_Msk (0x4UL) /*!< PSARE2 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARE_PSARE3_Pos (3UL) /*!< PSARE3 (Bit 3) */
|
|
|
+ #define R_PSCU_PSARE_PSARE3_Msk (0x8UL) /*!< PSARE3 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARE_PSARE8_Pos (8UL) /*!< PSARE8 (Bit 8) */
|
|
|
+ #define R_PSCU_PSARE_PSARE8_Msk (0x100UL) /*!< PSARE8 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARE_PSARE9_Pos (9UL) /*!< PSARE9 (Bit 9) */
|
|
|
+ #define R_PSCU_PSARE_PSARE9_Msk (0x200UL) /*!< PSARE9 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARE_PSARE18_Pos (18UL) /*!< PSARE18 (Bit 18) */
|
|
|
+ #define R_PSCU_PSARE_PSARE18_Msk (0x40000UL) /*!< PSARE18 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARE_PSARE19_Pos (19UL) /*!< PSARE19 (Bit 19) */
|
|
|
+ #define R_PSCU_PSARE_PSARE19_Msk (0x80000UL) /*!< PSARE19 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARE_PSARE20_Pos (20UL) /*!< PSARE20 (Bit 20) */
|
|
|
+ #define R_PSCU_PSARE_PSARE20_Msk (0x100000UL) /*!< PSARE20 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARE_PSARE21_Pos (21UL) /*!< PSARE21 (Bit 21) */
|
|
|
+ #define R_PSCU_PSARE_PSARE21_Msk (0x200000UL) /*!< PSARE21 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARE_PSARE22_Pos (22UL) /*!< PSARE22 (Bit 22) */
|
|
|
+ #define R_PSCU_PSARE_PSARE22_Msk (0x400000UL) /*!< PSARE22 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARE_PSARE23_Pos (23UL) /*!< PSARE23 (Bit 23) */
|
|
|
+ #define R_PSCU_PSARE_PSARE23_Msk (0x800000UL) /*!< PSARE23 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARE_PSARE24_Pos (24UL) /*!< PSARE24 (Bit 24) */
|
|
|
+ #define R_PSCU_PSARE_PSARE24_Msk (0x1000000UL) /*!< PSARE24 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARE_PSARE25_Pos (25UL) /*!< PSARE25 (Bit 25) */
|
|
|
+ #define R_PSCU_PSARE_PSARE25_Msk (0x2000000UL) /*!< PSARE25 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARE_PSARE26_Pos (26UL) /*!< PSARE26 (Bit 26) */
|
|
|
+ #define R_PSCU_PSARE_PSARE26_Msk (0x4000000UL) /*!< PSARE26 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARE_PSARE27_Pos (27UL) /*!< PSARE27 (Bit 27) */
|
|
|
+ #define R_PSCU_PSARE_PSARE27_Msk (0x8000000UL) /*!< PSARE27 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARE_PSARE28_Pos (28UL) /*!< PSARE28 (Bit 28) */
|
|
|
+ #define R_PSCU_PSARE_PSARE28_Msk (0x10000000UL) /*!< PSARE28 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARE_PSARE29_Pos (29UL) /*!< PSARE29 (Bit 29) */
|
|
|
+ #define R_PSCU_PSARE_PSARE29_Msk (0x20000000UL) /*!< PSARE29 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARE_PSARE30_Pos (30UL) /*!< PSARE30 (Bit 30) */
|
|
|
+ #define R_PSCU_PSARE_PSARE30_Msk (0x40000000UL) /*!< PSARE30 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PSARE_PSARE31_Pos (31UL) /*!< PSARE31 (Bit 31) */
|
|
|
+ #define R_PSCU_PSARE_PSARE31_Msk (0x80000000UL) /*!< PSARE31 (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= MSSAR ========================================================= */
|
|
|
+ #define R_PSCU_MSSAR_MSSAR0_Pos (0UL) /*!< MSSAR0 (Bit 0) */
|
|
|
+ #define R_PSCU_MSSAR_MSSAR0_Msk (0x1UL) /*!< MSSAR0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_MSSAR_MSSAR1_Pos (1UL) /*!< MSSAR1 (Bit 1) */
|
|
|
+ #define R_PSCU_MSSAR_MSSAR1_Msk (0x2UL) /*!< MSSAR1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_MSSAR_MSSAR11_Pos (11UL) /*!< MSSAR11 (Bit 11) */
|
|
|
+ #define R_PSCU_MSSAR_MSSAR11_Msk (0x800UL) /*!< MSSAR11 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_MSSAR_MSSAR13_Pos (13UL) /*!< MSSAR13 (Bit 13) */
|
|
|
+ #define R_PSCU_MSSAR_MSSAR13_Msk (0x2000UL) /*!< MSSAR13 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_MSSAR_MSSAR15_Pos (15UL) /*!< MSSAR15 (Bit 15) */
|
|
|
+ #define R_PSCU_MSSAR_MSSAR15_Msk (0x8000UL) /*!< MSSAR15 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_MSSAR_MSSAR22_Pos (22UL) /*!< MSSAR22 (Bit 22) */
|
|
|
+ #define R_PSCU_MSSAR_MSSAR22_Msk (0x400000UL) /*!< MSSAR22 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_MSSAR_MSSAR31_Pos (31UL) /*!< MSSAR31 (Bit 31) */
|
|
|
+ #define R_PSCU_MSSAR_MSSAR31_Msk (0x80000000UL) /*!< MSSAR31 (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= PPARB ========================================================= */
|
|
|
+ #define R_PSCU_PPARB_PPARB4_Pos (4UL) /*!< PPARB4 (Bit 4) */
|
|
|
+ #define R_PSCU_PPARB_PPARB4_Msk (0x10UL) /*!< PPARB4 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARB_PPARB8_Pos (8UL) /*!< PPARB8 (Bit 8) */
|
|
|
+ #define R_PSCU_PPARB_PPARB8_Msk (0x100UL) /*!< PPARB8 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARB_PPARB9_Pos (9UL) /*!< PPARB9 (Bit 9) */
|
|
|
+ #define R_PSCU_PPARB_PPARB9_Msk (0x200UL) /*!< PPARB9 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARB_PPARB11_Pos (11UL) /*!< PPARB11 (Bit 11) */
|
|
|
+ #define R_PSCU_PPARB_PPARB11_Msk (0x800UL) /*!< PPARB11 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARB_PPARB12_Pos (12UL) /*!< PPARB12 (Bit 12) */
|
|
|
+ #define R_PSCU_PPARB_PPARB12_Msk (0x1000UL) /*!< PPARB12 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARB_PPARB15_Pos (15UL) /*!< PPARB15 (Bit 15) */
|
|
|
+ #define R_PSCU_PPARB_PPARB15_Msk (0x8000UL) /*!< PPARB15 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARB_PPARB16_Pos (16UL) /*!< PPARB16 (Bit 16) */
|
|
|
+ #define R_PSCU_PPARB_PPARB16_Msk (0x10000UL) /*!< PPARB16 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARB_PPARB18_Pos (18UL) /*!< PPARB18 (Bit 18) */
|
|
|
+ #define R_PSCU_PPARB_PPARB18_Msk (0x40000UL) /*!< PPARB18 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARB_PPARB19_Pos (19UL) /*!< PPARB19 (Bit 19) */
|
|
|
+ #define R_PSCU_PPARB_PPARB19_Msk (0x80000UL) /*!< PPARB19 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARB_PPARB22_Pos (22UL) /*!< PPARB22 (Bit 22) */
|
|
|
+ #define R_PSCU_PPARB_PPARB22_Msk (0x400000UL) /*!< PPARB22 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARB_PPARB27_Pos (27UL) /*!< PPARB27 (Bit 27) */
|
|
|
+ #define R_PSCU_PPARB_PPARB27_Msk (0x8000000UL) /*!< PPARB27 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARB_PPARB28_Pos (28UL) /*!< PPARB28 (Bit 28) */
|
|
|
+ #define R_PSCU_PPARB_PPARB28_Msk (0x10000000UL) /*!< PPARB28 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARB_PPARB29_Pos (29UL) /*!< PPARB29 (Bit 29) */
|
|
|
+ #define R_PSCU_PPARB_PPARB29_Msk (0x20000000UL) /*!< PPARB29 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARB_PPARB30_Pos (30UL) /*!< PPARB30 (Bit 30) */
|
|
|
+ #define R_PSCU_PPARB_PPARB30_Msk (0x40000000UL) /*!< PPARB30 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARB_PPARB31_Pos (31UL) /*!< PPARB31 (Bit 31) */
|
|
|
+ #define R_PSCU_PPARB_PPARB31_Msk (0x80000000UL) /*!< PPARB31 (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= PPARC ========================================================= */
|
|
|
+ #define R_PSCU_PPARC_PPARC0_Pos (0UL) /*!< PPARC0 (Bit 0) */
|
|
|
+ #define R_PSCU_PPARC_PPARC0_Msk (0x1UL) /*!< PPARC0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARC_PPARC1_Pos (1UL) /*!< PPARC1 (Bit 1) */
|
|
|
+ #define R_PSCU_PPARC_PPARC1_Msk (0x2UL) /*!< PPARC1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARC_PPARC7_Pos (7UL) /*!< PPARC7 (Bit 7) */
|
|
|
+ #define R_PSCU_PPARC_PPARC7_Msk (0x80UL) /*!< PPARC7 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARC_PPARC8_Pos (8UL) /*!< PPARC8 (Bit 8) */
|
|
|
+ #define R_PSCU_PPARC_PPARC8_Msk (0x100UL) /*!< PPARC8 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARC_PPARC11_Pos (11UL) /*!< PPARC11 (Bit 11) */
|
|
|
+ #define R_PSCU_PPARC_PPARC11_Msk (0x800UL) /*!< PPARC11 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARC_PPARC12_Pos (12UL) /*!< PPARC12 (Bit 12) */
|
|
|
+ #define R_PSCU_PPARC_PPARC12_Msk (0x1000UL) /*!< PPARC12 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARC_PPARC13_Pos (13UL) /*!< PPARC13 (Bit 13) */
|
|
|
+ #define R_PSCU_PPARC_PPARC13_Msk (0x2000UL) /*!< PPARC13 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARC_PPARC15_Pos (15UL) /*!< PPARC15 (Bit 15) */
|
|
|
+ #define R_PSCU_PPARC_PPARC15_Msk (0x8000UL) /*!< PPARC15 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARC_PPARC16_Pos (16UL) /*!< PPARC16 (Bit 16) */
|
|
|
+ #define R_PSCU_PPARC_PPARC16_Msk (0x10000UL) /*!< PPARC16 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARC_PPARC26_Pos (26UL) /*!< PPARC26 (Bit 26) */
|
|
|
+ #define R_PSCU_PPARC_PPARC26_Msk (0x4000000UL) /*!< PPARC26 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARC_PPARC27_Pos (27UL) /*!< PPARC27 (Bit 27) */
|
|
|
+ #define R_PSCU_PPARC_PPARC27_Msk (0x8000000UL) /*!< PPARC27 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARC_PPARC31_Pos (31UL) /*!< PPARC31 (Bit 31) */
|
|
|
+ #define R_PSCU_PPARC_PPARC31_Msk (0x80000000UL) /*!< PPARC31 (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= PPARD ========================================================= */
|
|
|
+ #define R_PSCU_PPARD_PPARD4_Pos (4UL) /*!< PPARD4 (Bit 4) */
|
|
|
+ #define R_PSCU_PPARD_PPARD4_Msk (0x10UL) /*!< PPARD4 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARD_PPARD5_Pos (5UL) /*!< PPARD5 (Bit 5) */
|
|
|
+ #define R_PSCU_PPARD_PPARD5_Msk (0x20UL) /*!< PPARD5 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARD_PPARD11_Pos (11UL) /*!< PPARD11 (Bit 11) */
|
|
|
+ #define R_PSCU_PPARD_PPARD11_Msk (0x800UL) /*!< PPARD11 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARD_PPARD12_Pos (12UL) /*!< PPARD12 (Bit 12) */
|
|
|
+ #define R_PSCU_PPARD_PPARD12_Msk (0x1000UL) /*!< PPARD12 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARD_PPARD13_Pos (13UL) /*!< PPARD13 (Bit 13) */
|
|
|
+ #define R_PSCU_PPARD_PPARD13_Msk (0x2000UL) /*!< PPARD13 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARD_PPARD14_Pos (14UL) /*!< PPARD14 (Bit 14) */
|
|
|
+ #define R_PSCU_PPARD_PPARD14_Msk (0x4000UL) /*!< PPARD14 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARD_PPARD15_Pos (15UL) /*!< PPARD15 (Bit 15) */
|
|
|
+ #define R_PSCU_PPARD_PPARD15_Msk (0x8000UL) /*!< PPARD15 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARD_PPARD16_Pos (16UL) /*!< PPARD16 (Bit 16) */
|
|
|
+ #define R_PSCU_PPARD_PPARD16_Msk (0x10000UL) /*!< PPARD16 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARD_PPARD20_Pos (20UL) /*!< PPARD20 (Bit 20) */
|
|
|
+ #define R_PSCU_PPARD_PPARD20_Msk (0x100000UL) /*!< PPARD20 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARD_PPARD22_Pos (22UL) /*!< PPARD22 (Bit 22) */
|
|
|
+ #define R_PSCU_PPARD_PPARD22_Msk (0x400000UL) /*!< PPARD22 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARD_PPARD27_Pos (27UL) /*!< PPARD27 (Bit 27) */
|
|
|
+ #define R_PSCU_PPARD_PPARD27_Msk (0x8000000UL) /*!< PPARD27 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARD_PPARD28_Pos (28UL) /*!< PPARD28 (Bit 28) */
|
|
|
+ #define R_PSCU_PPARD_PPARD28_Msk (0x10000000UL) /*!< PPARD28 (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= PPARE ========================================================= */
|
|
|
+ #define R_PSCU_PPARE_PPARE1_Pos (1UL) /*!< PPARE1 (Bit 1) */
|
|
|
+ #define R_PSCU_PPARE_PPARE1_Msk (0x2UL) /*!< PPARE1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARE_PPARE2_Pos (2UL) /*!< PPARE2 (Bit 2) */
|
|
|
+ #define R_PSCU_PPARE_PPARE2_Msk (0x4UL) /*!< PPARE2 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARE_PPARE3_Pos (3UL) /*!< PPARE3 (Bit 3) */
|
|
|
+ #define R_PSCU_PPARE_PPARE3_Msk (0x8UL) /*!< PPARE3 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARE_PPARE8_Pos (8UL) /*!< PPARE8 (Bit 8) */
|
|
|
+ #define R_PSCU_PPARE_PPARE8_Msk (0x100UL) /*!< PPARE8 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARE_PPARE9_Pos (9UL) /*!< PPARE9 (Bit 9) */
|
|
|
+ #define R_PSCU_PPARE_PPARE9_Msk (0x200UL) /*!< PPARE9 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARE_PPARE18_Pos (18UL) /*!< PPARE18 (Bit 18) */
|
|
|
+ #define R_PSCU_PPARE_PPARE18_Msk (0x40000UL) /*!< PPARE18 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARE_PPARE19_Pos (19UL) /*!< PPARE19 (Bit 19) */
|
|
|
+ #define R_PSCU_PPARE_PPARE19_Msk (0x80000UL) /*!< PPARE19 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARE_PPARE20_Pos (20UL) /*!< PPARE20 (Bit 20) */
|
|
|
+ #define R_PSCU_PPARE_PPARE20_Msk (0x100000UL) /*!< PPARE20 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARE_PPARE21_Pos (21UL) /*!< PPARE21 (Bit 21) */
|
|
|
+ #define R_PSCU_PPARE_PPARE21_Msk (0x200000UL) /*!< PPARE21 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARE_PPARE22_Pos (22UL) /*!< PPARE22 (Bit 22) */
|
|
|
+ #define R_PSCU_PPARE_PPARE22_Msk (0x400000UL) /*!< PPARE22 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARE_PPARE23_Pos (23UL) /*!< PPARE23 (Bit 23) */
|
|
|
+ #define R_PSCU_PPARE_PPARE23_Msk (0x800000UL) /*!< PPARE23 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARE_PPARE24_Pos (24UL) /*!< PPARE24 (Bit 24) */
|
|
|
+ #define R_PSCU_PPARE_PPARE24_Msk (0x1000000UL) /*!< PPARE24 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARE_PPARE25_Pos (25UL) /*!< PPARE25 (Bit 25) */
|
|
|
+ #define R_PSCU_PPARE_PPARE25_Msk (0x2000000UL) /*!< PPARE25 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARE_PPARE26_Pos (26UL) /*!< PPARE26 (Bit 26) */
|
|
|
+ #define R_PSCU_PPARE_PPARE26_Msk (0x4000000UL) /*!< PPARE26 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARE_PPARE27_Pos (27UL) /*!< PPARE27 (Bit 27) */
|
|
|
+ #define R_PSCU_PPARE_PPARE27_Msk (0x8000000UL) /*!< PPARE27 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARE_PPARE28_Pos (28UL) /*!< PPARE28 (Bit 28) */
|
|
|
+ #define R_PSCU_PPARE_PPARE28_Msk (0x10000000UL) /*!< PPARE28 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARE_PPARE29_Pos (29UL) /*!< PPARE29 (Bit 29) */
|
|
|
+ #define R_PSCU_PPARE_PPARE29_Msk (0x20000000UL) /*!< PPARE29 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARE_PPARE30_Pos (30UL) /*!< PPARE30 (Bit 30) */
|
|
|
+ #define R_PSCU_PPARE_PPARE30_Msk (0x40000000UL) /*!< PPARE30 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PSCU_PPARE_PPARE31_Pos (31UL) /*!< PPARE31 (Bit 31) */
|
|
|
+ #define R_PSCU_PPARE_PPARE31_Msk (0x80000000UL) /*!< PPARE31 (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= MSPAR ========================================================= */
|
|
|
+ #define R_PSCU_MSPAR_MSPAR31_Pos (31UL) /*!< MSPAR31 (Bit 31) */
|
|
|
+ #define R_PSCU_MSPAR_MSPAR31_Msk (0x80000000UL) /*!< MSPAR31 (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= CFSAMONA ======================================================== */
|
|
|
+ #define R_PSCU_CFSAMONA_CFS2_Pos (15UL) /*!< CFS2 (Bit 15) */
|
|
|
+ #define R_PSCU_CFSAMONA_CFS2_Msk (0xff8000UL) /*!< CFS2 (Bitfield-Mask: 0x1ff) */
|
|
|
+/* ======================================================== DFSAMON ======================================================== */
|
|
|
+ #define R_PSCU_DFSAMON_DFS_Pos (10UL) /*!< DFS (Bit 10) */
|
|
|
+ #define R_PSCU_DFSAMON_DFS_Msk (0xfc00UL) /*!< DFS (Bitfield-Mask: 0x3f) */
|
|
|
+/* ======================================================== DLMMON ========================================================= */
|
|
|
+ #define R_PSCU_DLMMON_DLMMON_Pos (0UL) /*!< DLMMON (Bit 0) */
|
|
|
+ #define R_PSCU_DLMMON_DLMMON_Msk (0xfUL) /*!< DLMMON (Bitfield-Mask: 0x0f) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_BUS ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ======================================================== CSRECEN ======================================================== */
|
|
|
+ #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */
|
|
|
+ #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */
|
|
|
+ #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== BUSMABT ======================================================== */
|
|
|
+ #define R_BUS_BUSMABT_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */
|
|
|
+ #define R_BUS_BUSMABT_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= BUSDIVBYP ======================================================= */
|
|
|
+ #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos (16UL) /*!< CPU0SBPE (Bit 16) */
|
|
|
+ #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_BUS_BUSDIVBYP_GDSSBPE_Pos (3UL) /*!< GDSSBPE (Bit 3) */
|
|
|
+ #define R_BUS_BUSDIVBYP_GDSSBPE_Msk (0x8UL) /*!< GDSSBPE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_BUS_BUSDIVBYP_EDMABPE_Pos (0UL) /*!< EDMABPE (Bit 0) */
|
|
|
+ #define R_BUS_BUSDIVBYP_EDMABPE_Msk (0x1UL) /*!< EDMABPE (Bitfield-Mask: 0x01) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_CAC ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================= CACR0 ========================================================= */
|
|
|
+ #define R_CAC_CACR0_CFME_Pos (0UL) /*!< CFME (Bit 0) */
|
|
|
+ #define R_CAC_CACR0_CFME_Msk (0x1UL) /*!< CFME (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= CACR1 ========================================================= */
|
|
|
+ #define R_CAC_CACR1_EDGES_Pos (6UL) /*!< EDGES (Bit 6) */
|
|
|
+ #define R_CAC_CACR1_EDGES_Msk (0xc0UL) /*!< EDGES (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_CAC_CACR1_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */
|
|
|
+ #define R_CAC_CACR1_TCSS_Msk (0x30UL) /*!< TCSS (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_CAC_CACR1_FMCS_Pos (1UL) /*!< FMCS (Bit 1) */
|
|
|
+ #define R_CAC_CACR1_FMCS_Msk (0xeUL) /*!< FMCS (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_CAC_CACR1_CACREFE_Pos (0UL) /*!< CACREFE (Bit 0) */
|
|
|
+ #define R_CAC_CACR1_CACREFE_Msk (0x1UL) /*!< CACREFE (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= CACR2 ========================================================= */
|
|
|
+ #define R_CAC_CACR2_DFS_Pos (6UL) /*!< DFS (Bit 6) */
|
|
|
+ #define R_CAC_CACR2_DFS_Msk (0xc0UL) /*!< DFS (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_CAC_CACR2_RCDS_Pos (4UL) /*!< RCDS (Bit 4) */
|
|
|
+ #define R_CAC_CACR2_RCDS_Msk (0x30UL) /*!< RCDS (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_CAC_CACR2_RSCS_Pos (1UL) /*!< RSCS (Bit 1) */
|
|
|
+ #define R_CAC_CACR2_RSCS_Msk (0xeUL) /*!< RSCS (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_CAC_CACR2_RPS_Pos (0UL) /*!< RPS (Bit 0) */
|
|
|
+ #define R_CAC_CACR2_RPS_Msk (0x1UL) /*!< RPS (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= CAICR ========================================================= */
|
|
|
+ #define R_CAC_CAICR_OVFFCL_Pos (6UL) /*!< OVFFCL (Bit 6) */
|
|
|
+ #define R_CAC_CAICR_OVFFCL_Msk (0x40UL) /*!< OVFFCL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CAC_CAICR_MENDFCL_Pos (5UL) /*!< MENDFCL (Bit 5) */
|
|
|
+ #define R_CAC_CAICR_MENDFCL_Msk (0x20UL) /*!< MENDFCL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CAC_CAICR_FERRFCL_Pos (4UL) /*!< FERRFCL (Bit 4) */
|
|
|
+ #define R_CAC_CAICR_FERRFCL_Msk (0x10UL) /*!< FERRFCL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CAC_CAICR_OVFIE_Pos (2UL) /*!< OVFIE (Bit 2) */
|
|
|
+ #define R_CAC_CAICR_OVFIE_Msk (0x4UL) /*!< OVFIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CAC_CAICR_MENDIE_Pos (1UL) /*!< MENDIE (Bit 1) */
|
|
|
+ #define R_CAC_CAICR_MENDIE_Msk (0x2UL) /*!< MENDIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CAC_CAICR_FERRIE_Pos (0UL) /*!< FERRIE (Bit 0) */
|
|
|
+ #define R_CAC_CAICR_FERRIE_Msk (0x1UL) /*!< FERRIE (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= CASTR ========================================================= */
|
|
|
+ #define R_CAC_CASTR_OVFF_Pos (2UL) /*!< OVFF (Bit 2) */
|
|
|
+ #define R_CAC_CASTR_OVFF_Msk (0x4UL) /*!< OVFF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CAC_CASTR_MENDF_Pos (1UL) /*!< MENDF (Bit 1) */
|
|
|
+ #define R_CAC_CASTR_MENDF_Msk (0x2UL) /*!< MENDF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CAC_CASTR_FERRF_Pos (0UL) /*!< FERRF (Bit 0) */
|
|
|
+ #define R_CAC_CASTR_FERRF_Msk (0x1UL) /*!< FERRF (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== CAULVR ========================================================= */
|
|
|
+ #define R_CAC_CAULVR_CAULVR_Pos (0UL) /*!< CAULVR (Bit 0) */
|
|
|
+ #define R_CAC_CAULVR_CAULVR_Msk (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================== CALLVR ========================================================= */
|
|
|
+ #define R_CAC_CALLVR_CALLVR_Pos (0UL) /*!< CALLVR (Bit 0) */
|
|
|
+ #define R_CAC_CALLVR_CALLVR_Msk (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================== CACNTBR ======================================================== */
|
|
|
+ #define R_CAC_CACNTBR_CACNTBR_Pos (0UL) /*!< CACNTBR (Bit 0) */
|
|
|
+ #define R_CAC_CACNTBR_CACNTBR_Msk (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_CANFD0 ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ======================================================== CFDGCFG ======================================================== */
|
|
|
+ #define R_CANFD_CFDGCFG_TPRI_Pos (0UL) /*!< TPRI (Bit 0) */
|
|
|
+ #define R_CANFD_CFDGCFG_TPRI_Msk (0x1UL) /*!< TPRI (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDGCFG_DCE_Pos (1UL) /*!< DCE (Bit 1) */
|
|
|
+ #define R_CANFD_CFDGCFG_DCE_Msk (0x2UL) /*!< DCE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDGCFG_DRE_Pos (2UL) /*!< DRE (Bit 2) */
|
|
|
+ #define R_CANFD_CFDGCFG_DRE_Msk (0x4UL) /*!< DRE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDGCFG_MME_Pos (3UL) /*!< MME (Bit 3) */
|
|
|
+ #define R_CANFD_CFDGCFG_MME_Msk (0x8UL) /*!< MME (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDGCFG_DCS_Pos (4UL) /*!< DCS (Bit 4) */
|
|
|
+ #define R_CANFD_CFDGCFG_DCS_Msk (0x10UL) /*!< DCS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDGCFG_CMPOC_Pos (5UL) /*!< CMPOC (Bit 5) */
|
|
|
+ #define R_CANFD_CFDGCFG_CMPOC_Msk (0x20UL) /*!< CMPOC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDGCFG_TSP_Pos (8UL) /*!< TSP (Bit 8) */
|
|
|
+ #define R_CANFD_CFDGCFG_TSP_Msk (0xf00UL) /*!< TSP (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_CANFD_CFDGCFG_TSSS_Pos (12UL) /*!< TSSS (Bit 12) */
|
|
|
+ #define R_CANFD_CFDGCFG_TSSS_Msk (0x1000UL) /*!< TSSS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDGCFG_ITRCP_Pos (16UL) /*!< ITRCP (Bit 16) */
|
|
|
+ #define R_CANFD_CFDGCFG_ITRCP_Msk (0xffff0000UL) /*!< ITRCP (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================== CFDGCTR ======================================================== */
|
|
|
+ #define R_CANFD_CFDGCTR_GMDC_Pos (0UL) /*!< GMDC (Bit 0) */
|
|
|
+ #define R_CANFD_CFDGCTR_GMDC_Msk (0x3UL) /*!< GMDC (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_CANFD_CFDGCTR_GSLPR_Pos (2UL) /*!< GSLPR (Bit 2) */
|
|
|
+ #define R_CANFD_CFDGCTR_GSLPR_Msk (0x4UL) /*!< GSLPR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDGCTR_DEIE_Pos (8UL) /*!< DEIE (Bit 8) */
|
|
|
+ #define R_CANFD_CFDGCTR_DEIE_Msk (0x100UL) /*!< DEIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDGCTR_MEIE_Pos (9UL) /*!< MEIE (Bit 9) */
|
|
|
+ #define R_CANFD_CFDGCTR_MEIE_Msk (0x200UL) /*!< MEIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDGCTR_THLEIE_Pos (10UL) /*!< THLEIE (Bit 10) */
|
|
|
+ #define R_CANFD_CFDGCTR_THLEIE_Msk (0x400UL) /*!< THLEIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDGCTR_CMPOFIE_Pos (11UL) /*!< CMPOFIE (Bit 11) */
|
|
|
+ #define R_CANFD_CFDGCTR_CMPOFIE_Msk (0x800UL) /*!< CMPOFIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDGCTR_TSRST_Pos (16UL) /*!< TSRST (Bit 16) */
|
|
|
+ #define R_CANFD_CFDGCTR_TSRST_Msk (0x10000UL) /*!< TSRST (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== CFDGSTS ======================================================== */
|
|
|
+ #define R_CANFD_CFDGSTS_GRSTSTS_Pos (0UL) /*!< GRSTSTS (Bit 0) */
|
|
|
+ #define R_CANFD_CFDGSTS_GRSTSTS_Msk (0x1UL) /*!< GRSTSTS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDGSTS_GHLTSTS_Pos (1UL) /*!< GHLTSTS (Bit 1) */
|
|
|
+ #define R_CANFD_CFDGSTS_GHLTSTS_Msk (0x2UL) /*!< GHLTSTS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDGSTS_GSLPSTS_Pos (2UL) /*!< GSLPSTS (Bit 2) */
|
|
|
+ #define R_CANFD_CFDGSTS_GSLPSTS_Msk (0x4UL) /*!< GSLPSTS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDGSTS_GRAMINIT_Pos (3UL) /*!< GRAMINIT (Bit 3) */
|
|
|
+ #define R_CANFD_CFDGSTS_GRAMINIT_Msk (0x8UL) /*!< GRAMINIT (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= CFDGERFL ======================================================== */
|
|
|
+ #define R_CANFD_CFDGERFL_DEF_Pos (0UL) /*!< DEF (Bit 0) */
|
|
|
+ #define R_CANFD_CFDGERFL_DEF_Msk (0x1UL) /*!< DEF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDGERFL_MES_Pos (1UL) /*!< MES (Bit 1) */
|
|
|
+ #define R_CANFD_CFDGERFL_MES_Msk (0x2UL) /*!< MES (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDGERFL_THLES_Pos (2UL) /*!< THLES (Bit 2) */
|
|
|
+ #define R_CANFD_CFDGERFL_THLES_Msk (0x4UL) /*!< THLES (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDGERFL_CMPOF_Pos (3UL) /*!< CMPOF (Bit 3) */
|
|
|
+ #define R_CANFD_CFDGERFL_CMPOF_Msk (0x8UL) /*!< CMPOF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDGERFL_EEF0_Pos (16UL) /*!< EEF0 (Bit 16) */
|
|
|
+ #define R_CANFD_CFDGERFL_EEF0_Msk (0x10000UL) /*!< EEF0 (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== CFDGTSC ======================================================== */
|
|
|
+ #define R_CANFD_CFDGTSC_TS_Pos (0UL) /*!< TS (Bit 0) */
|
|
|
+ #define R_CANFD_CFDGTSC_TS_Msk (0xffffUL) /*!< TS (Bitfield-Mask: 0xffff) */
|
|
|
+/* ====================================================== CFDGAFLECTR ====================================================== */
|
|
|
+ #define R_CANFD_CFDGAFLECTR_AFLPN_Pos (0UL) /*!< AFLPN (Bit 0) */
|
|
|
+ #define R_CANFD_CFDGAFLECTR_AFLPN_Msk (0xfUL) /*!< AFLPN (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_CANFD_CFDGAFLECTR_AFLDAE_Pos (8UL) /*!< AFLDAE (Bit 8) */
|
|
|
+ #define R_CANFD_CFDGAFLECTR_AFLDAE_Msk (0x100UL) /*!< AFLDAE (Bitfield-Mask: 0x01) */
|
|
|
+/* ====================================================== CFDGAFLCFG0 ====================================================== */
|
|
|
+ #define R_CANFD_CFDGAFLCFG0_RNC1_Pos (0UL) /*!< RNC1 (Bit 0) */
|
|
|
+ #define R_CANFD_CFDGAFLCFG0_RNC1_Msk (0x1ffUL) /*!< RNC1 (Bitfield-Mask: 0x1ff) */
|
|
|
+ #define R_CANFD_CFDGAFLCFG0_RNC0_Pos (16UL) /*!< RNC0 (Bit 16) */
|
|
|
+ #define R_CANFD_CFDGAFLCFG0_RNC0_Msk (0x1ff0000UL) /*!< RNC0 (Bitfield-Mask: 0x1ff) */
|
|
|
+/* ======================================================== CFDRMNB ======================================================== */
|
|
|
+ #define R_CANFD_CFDRMNB_NRXMB_Pos (0UL) /*!< NRXMB (Bit 0) */
|
|
|
+ #define R_CANFD_CFDRMNB_NRXMB_Msk (0xffUL) /*!< NRXMB (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_CANFD_CFDRMNB_RMPLS_Pos (8UL) /*!< RMPLS (Bit 8) */
|
|
|
+ #define R_CANFD_CFDRMNB_RMPLS_Msk (0x700UL) /*!< RMPLS (Bitfield-Mask: 0x07) */
|
|
|
+/* ======================================================= CFDRMND0 ======================================================== */
|
|
|
+ #define R_CANFD_CFDRMND0_RMNSu_Pos (0UL) /*!< RMNSu (Bit 0) */
|
|
|
+ #define R_CANFD_CFDRMND0_RMNSu_Msk (0xffffffffUL) /*!< RMNSu (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================= CFDRMIEC ======================================================== */
|
|
|
+ #define R_CANFD_CFDRMIEC_RMIE_Pos (0UL) /*!< RMIE (Bit 0) */
|
|
|
+ #define R_CANFD_CFDRMIEC_RMIE_Msk (0xffffffffUL) /*!< RMIE (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================== CFDRFCC ======================================================== */
|
|
|
+ #define R_CANFD_CFDRFCC_RFE_Pos (0UL) /*!< RFE (Bit 0) */
|
|
|
+ #define R_CANFD_CFDRFCC_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDRFCC_RFIE_Pos (1UL) /*!< RFIE (Bit 1) */
|
|
|
+ #define R_CANFD_CFDRFCC_RFIE_Msk (0x2UL) /*!< RFIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDRFCC_RFPLS_Pos (4UL) /*!< RFPLS (Bit 4) */
|
|
|
+ #define R_CANFD_CFDRFCC_RFPLS_Msk (0x70UL) /*!< RFPLS (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_CANFD_CFDRFCC_RFDC_Pos (8UL) /*!< RFDC (Bit 8) */
|
|
|
+ #define R_CANFD_CFDRFCC_RFDC_Msk (0x700UL) /*!< RFDC (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_CANFD_CFDRFCC_RFIM_Pos (12UL) /*!< RFIM (Bit 12) */
|
|
|
+ #define R_CANFD_CFDRFCC_RFIM_Msk (0x1000UL) /*!< RFIM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDRFCC_RFIGCV_Pos (13UL) /*!< RFIGCV (Bit 13) */
|
|
|
+ #define R_CANFD_CFDRFCC_RFIGCV_Msk (0xe000UL) /*!< RFIGCV (Bitfield-Mask: 0x07) */
|
|
|
+/* ======================================================= CFDRFSTS ======================================================== */
|
|
|
+ #define R_CANFD_CFDRFSTS_RFEMP_Pos (0UL) /*!< RFEMP (Bit 0) */
|
|
|
+ #define R_CANFD_CFDRFSTS_RFEMP_Msk (0x1UL) /*!< RFEMP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDRFSTS_RFFLL_Pos (1UL) /*!< RFFLL (Bit 1) */
|
|
|
+ #define R_CANFD_CFDRFSTS_RFFLL_Msk (0x2UL) /*!< RFFLL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDRFSTS_RFMLT_Pos (2UL) /*!< RFMLT (Bit 2) */
|
|
|
+ #define R_CANFD_CFDRFSTS_RFMLT_Msk (0x4UL) /*!< RFMLT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDRFSTS_RFIF_Pos (3UL) /*!< RFIF (Bit 3) */
|
|
|
+ #define R_CANFD_CFDRFSTS_RFIF_Msk (0x8UL) /*!< RFIF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDRFSTS_RFMC_Pos (8UL) /*!< RFMC (Bit 8) */
|
|
|
+ #define R_CANFD_CFDRFSTS_RFMC_Msk (0xff00UL) /*!< RFMC (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= CFDRFPCTR ======================================================= */
|
|
|
+ #define R_CANFD_CFDRFPCTR_RFPC_Pos (0UL) /*!< RFPC (Bit 0) */
|
|
|
+ #define R_CANFD_CFDRFPCTR_RFPC_Msk (0xffUL) /*!< RFPC (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== CFDCFCC ======================================================== */
|
|
|
+ #define R_CANFD_CFDCFCC_CFE_Pos (0UL) /*!< CFE (Bit 0) */
|
|
|
+ #define R_CANFD_CFDCFCC_CFE_Msk (0x1UL) /*!< CFE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDCFCC_CFRXIE_Pos (1UL) /*!< CFRXIE (Bit 1) */
|
|
|
+ #define R_CANFD_CFDCFCC_CFRXIE_Msk (0x2UL) /*!< CFRXIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDCFCC_CFTXIE_Pos (2UL) /*!< CFTXIE (Bit 2) */
|
|
|
+ #define R_CANFD_CFDCFCC_CFTXIE_Msk (0x4UL) /*!< CFTXIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDCFCC_CFPLS_Pos (4UL) /*!< CFPLS (Bit 4) */
|
|
|
+ #define R_CANFD_CFDCFCC_CFPLS_Msk (0x70UL) /*!< CFPLS (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_CANFD_CFDCFCC_CFM_Pos (8UL) /*!< CFM (Bit 8) */
|
|
|
+ #define R_CANFD_CFDCFCC_CFM_Msk (0x300UL) /*!< CFM (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_CANFD_CFDCFCC_CFITSS_Pos (10UL) /*!< CFITSS (Bit 10) */
|
|
|
+ #define R_CANFD_CFDCFCC_CFITSS_Msk (0x400UL) /*!< CFITSS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDCFCC_CFITR_Pos (11UL) /*!< CFITR (Bit 11) */
|
|
|
+ #define R_CANFD_CFDCFCC_CFITR_Msk (0x800UL) /*!< CFITR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDCFCC_CFIM_Pos (12UL) /*!< CFIM (Bit 12) */
|
|
|
+ #define R_CANFD_CFDCFCC_CFIM_Msk (0x1000UL) /*!< CFIM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDCFCC_CFIGCV_Pos (13UL) /*!< CFIGCV (Bit 13) */
|
|
|
+ #define R_CANFD_CFDCFCC_CFIGCV_Msk (0xe000UL) /*!< CFIGCV (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_CANFD_CFDCFCC_CFTML_Pos (16UL) /*!< CFTML (Bit 16) */
|
|
|
+ #define R_CANFD_CFDCFCC_CFTML_Msk (0x1f0000UL) /*!< CFTML (Bitfield-Mask: 0x1f) */
|
|
|
+ #define R_CANFD_CFDCFCC_CFDC_Pos (21UL) /*!< CFDC (Bit 21) */
|
|
|
+ #define R_CANFD_CFDCFCC_CFDC_Msk (0xe00000UL) /*!< CFDC (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_CANFD_CFDCFCC_CFITT_Pos (24UL) /*!< CFITT (Bit 24) */
|
|
|
+ #define R_CANFD_CFDCFCC_CFITT_Msk (0xff000000UL) /*!< CFITT (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= CFDCFSTS ======================================================== */
|
|
|
+ #define R_CANFD_CFDCFSTS_CFEMP_Pos (0UL) /*!< CFEMP (Bit 0) */
|
|
|
+ #define R_CANFD_CFDCFSTS_CFEMP_Msk (0x1UL) /*!< CFEMP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDCFSTS_CFFLL_Pos (1UL) /*!< CFFLL (Bit 1) */
|
|
|
+ #define R_CANFD_CFDCFSTS_CFFLL_Msk (0x2UL) /*!< CFFLL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDCFSTS_CFMLT_Pos (2UL) /*!< CFMLT (Bit 2) */
|
|
|
+ #define R_CANFD_CFDCFSTS_CFMLT_Msk (0x4UL) /*!< CFMLT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDCFSTS_CFRXIF_Pos (3UL) /*!< CFRXIF (Bit 3) */
|
|
|
+ #define R_CANFD_CFDCFSTS_CFRXIF_Msk (0x8UL) /*!< CFRXIF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDCFSTS_CFTXIF_Pos (4UL) /*!< CFTXIF (Bit 4) */
|
|
|
+ #define R_CANFD_CFDCFSTS_CFTXIF_Msk (0x10UL) /*!< CFTXIF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDCFSTS_CFMC_Pos (8UL) /*!< CFMC (Bit 8) */
|
|
|
+ #define R_CANFD_CFDCFSTS_CFMC_Msk (0xff00UL) /*!< CFMC (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= CFDCFPCTR ======================================================= */
|
|
|
+ #define R_CANFD_CFDCFPCTR_CFPC_Pos (0UL) /*!< CFPC (Bit 0) */
|
|
|
+ #define R_CANFD_CFDCFPCTR_CFPC_Msk (0xffUL) /*!< CFPC (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= CFDFESTS ======================================================== */
|
|
|
+ #define R_CANFD_CFDFESTS_RFXEMP_Pos (0UL) /*!< RFXEMP (Bit 0) */
|
|
|
+ #define R_CANFD_CFDFESTS_RFXEMP_Msk (0x3UL) /*!< RFXEMP (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_CANFD_CFDFESTS_CFXEMP_Pos (8UL) /*!< CFXEMP (Bit 8) */
|
|
|
+ #define R_CANFD_CFDFESTS_CFXEMP_Msk (0x100UL) /*!< CFXEMP (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= CFDFFSTS ======================================================== */
|
|
|
+ #define R_CANFD_CFDFFSTS_RFXFLL_Pos (0UL) /*!< RFXFLL (Bit 0) */
|
|
|
+ #define R_CANFD_CFDFFSTS_RFXFLL_Msk (0x3UL) /*!< RFXFLL (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_CANFD_CFDFFSTS_CFXFLL_Pos (8UL) /*!< CFXFLL (Bit 8) */
|
|
|
+ #define R_CANFD_CFDFFSTS_CFXFLL_Msk (0x100UL) /*!< CFXFLL (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= CFDFMSTS ======================================================== */
|
|
|
+ #define R_CANFD_CFDFMSTS_RFXMLT_Pos (0UL) /*!< RFXMLT (Bit 0) */
|
|
|
+ #define R_CANFD_CFDFMSTS_RFXMLT_Msk (0x3UL) /*!< RFXMLT (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_CANFD_CFDFMSTS_CFXMLT_Pos (8UL) /*!< CFXMLT (Bit 8) */
|
|
|
+ #define R_CANFD_CFDFMSTS_CFXMLT_Msk (0x100UL) /*!< CFXMLT (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= CFDRFISTS ======================================================= */
|
|
|
+ #define R_CANFD_CFDRFISTS_RFXIF_Pos (0UL) /*!< RFXIF (Bit 0) */
|
|
|
+ #define R_CANFD_CFDRFISTS_RFXIF_Msk (0x1UL) /*!< RFXIF (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== CFDTMC ========================================================= */
|
|
|
+ #define R_CANFD_CFDTMC_TMTR_Pos (0UL) /*!< TMTR (Bit 0) */
|
|
|
+ #define R_CANFD_CFDTMC_TMTR_Msk (0x1UL) /*!< TMTR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDTMC_TMTAR_Pos (1UL) /*!< TMTAR (Bit 1) */
|
|
|
+ #define R_CANFD_CFDTMC_TMTAR_Msk (0x2UL) /*!< TMTAR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDTMC_TMOM_Pos (2UL) /*!< TMOM (Bit 2) */
|
|
|
+ #define R_CANFD_CFDTMC_TMOM_Msk (0x4UL) /*!< TMOM (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= CFDTMSTS ======================================================== */
|
|
|
+ #define R_CANFD_CFDTMSTS_TMTSTS_Pos (0UL) /*!< TMTSTS (Bit 0) */
|
|
|
+ #define R_CANFD_CFDTMSTS_TMTSTS_Msk (0x1UL) /*!< TMTSTS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDTMSTS_TMTRF_Pos (1UL) /*!< TMTRF (Bit 1) */
|
|
|
+ #define R_CANFD_CFDTMSTS_TMTRF_Msk (0x6UL) /*!< TMTRF (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_CANFD_CFDTMSTS_TMTRM_Pos (3UL) /*!< TMTRM (Bit 3) */
|
|
|
+ #define R_CANFD_CFDTMSTS_TMTRM_Msk (0x8UL) /*!< TMTRM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDTMSTS_TMTARM_Pos (4UL) /*!< TMTARM (Bit 4) */
|
|
|
+ #define R_CANFD_CFDTMSTS_TMTARM_Msk (0x10UL) /*!< TMTARM (Bitfield-Mask: 0x01) */
|
|
|
+/* ====================================================== CFDTMTRSTS ======================================================= */
|
|
|
+ #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Pos (0UL) /*!< CFDTMTRSTSg (Bit 0) */
|
|
|
+ #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Msk (0xfUL) /*!< CFDTMTRSTSg (Bitfield-Mask: 0x0f) */
|
|
|
+/* ====================================================== CFDTMTARSTS ====================================================== */
|
|
|
+ #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Pos (0UL) /*!< CFDTMTARSTSg (Bit 0) */
|
|
|
+ #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Msk (0xfUL) /*!< CFDTMTARSTSg (Bitfield-Mask: 0x0f) */
|
|
|
+/* ====================================================== CFDTMTCSTS ======================================================= */
|
|
|
+ #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Pos (0UL) /*!< CFDTMTCSTSg (Bit 0) */
|
|
|
+ #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Msk (0xfUL) /*!< CFDTMTCSTSg (Bitfield-Mask: 0x0f) */
|
|
|
+/* ====================================================== CFDTMTASTS ======================================================= */
|
|
|
+ #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Pos (0UL) /*!< CFDTMTASTSg (Bit 0) */
|
|
|
+ #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Msk (0xfUL) /*!< CFDTMTASTSg (Bitfield-Mask: 0x0f) */
|
|
|
+/* ======================================================= CFDTMIEC ======================================================== */
|
|
|
+ #define R_CANFD_CFDTMIEC_TMIEg_Pos (0UL) /*!< TMIEg (Bit 0) */
|
|
|
+ #define R_CANFD_CFDTMIEC_TMIEg_Msk (0xfUL) /*!< TMIEg (Bitfield-Mask: 0x0f) */
|
|
|
+/* ======================================================= CFDTXQCC0 ======================================================= */
|
|
|
+ #define R_CANFD_CFDTXQCC0_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */
|
|
|
+ #define R_CANFD_CFDTXQCC0_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDTXQCC0_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */
|
|
|
+ #define R_CANFD_CFDTXQCC0_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDTXQCC0_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */
|
|
|
+ #define R_CANFD_CFDTXQCC0_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDTXQCC0_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */
|
|
|
+ #define R_CANFD_CFDTXQCC0_TXQDC_Msk (0x300UL) /*!< TXQDC (Bitfield-Mask: 0x03) */
|
|
|
+/* ====================================================== CFDTXQSTS0 ======================================================= */
|
|
|
+ #define R_CANFD_CFDTXQSTS0_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */
|
|
|
+ #define R_CANFD_CFDTXQSTS0_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDTXQSTS0_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */
|
|
|
+ #define R_CANFD_CFDTXQSTS0_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDTXQSTS0_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */
|
|
|
+ #define R_CANFD_CFDTXQSTS0_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDTXQSTS0_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */
|
|
|
+ #define R_CANFD_CFDTXQSTS0_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */
|
|
|
+/* ====================================================== CFDTXQPCTR0 ====================================================== */
|
|
|
+ #define R_CANFD_CFDTXQPCTR0_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */
|
|
|
+ #define R_CANFD_CFDTXQPCTR0_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= CFDTHLCC ======================================================== */
|
|
|
+ #define R_CANFD_CFDTHLCC_THLE_Pos (0UL) /*!< THLE (Bit 0) */
|
|
|
+ #define R_CANFD_CFDTHLCC_THLE_Msk (0x1UL) /*!< THLE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDTHLCC_THLIE_Pos (8UL) /*!< THLIE (Bit 8) */
|
|
|
+ #define R_CANFD_CFDTHLCC_THLIE_Msk (0x100UL) /*!< THLIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDTHLCC_THLIM_Pos (9UL) /*!< THLIM (Bit 9) */
|
|
|
+ #define R_CANFD_CFDTHLCC_THLIM_Msk (0x200UL) /*!< THLIM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDTHLCC_THLDTE_Pos (10UL) /*!< THLDTE (Bit 10) */
|
|
|
+ #define R_CANFD_CFDTHLCC_THLDTE_Msk (0x400UL) /*!< THLDTE (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= CFDTHLSTS ======================================================= */
|
|
|
+ #define R_CANFD_CFDTHLSTS_THLEMP_Pos (0UL) /*!< THLEMP (Bit 0) */
|
|
|
+ #define R_CANFD_CFDTHLSTS_THLEMP_Msk (0x1UL) /*!< THLEMP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDTHLSTS_THLFLL_Pos (1UL) /*!< THLFLL (Bit 1) */
|
|
|
+ #define R_CANFD_CFDTHLSTS_THLFLL_Msk (0x2UL) /*!< THLFLL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDTHLSTS_THLELT_Pos (2UL) /*!< THLELT (Bit 2) */
|
|
|
+ #define R_CANFD_CFDTHLSTS_THLELT_Msk (0x4UL) /*!< THLELT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDTHLSTS_THLIF_Pos (3UL) /*!< THLIF (Bit 3) */
|
|
|
+ #define R_CANFD_CFDTHLSTS_THLIF_Msk (0x8UL) /*!< THLIF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDTHLSTS_THLMC_Pos (8UL) /*!< THLMC (Bit 8) */
|
|
|
+ #define R_CANFD_CFDTHLSTS_THLMC_Msk (0x3f00UL) /*!< THLMC (Bitfield-Mask: 0x3f) */
|
|
|
+/* ====================================================== CFDTHLPCTR ======================================================= */
|
|
|
+ #define R_CANFD_CFDTHLPCTR_THLPC_Pos (0UL) /*!< THLPC (Bit 0) */
|
|
|
+ #define R_CANFD_CFDTHLPCTR_THLPC_Msk (0xffUL) /*!< THLPC (Bitfield-Mask: 0xff) */
|
|
|
+/* ===================================================== CFDGTINTSTS0 ====================================================== */
|
|
|
+ #define R_CANFD_CFDGTINTSTS0_TSIF0_Pos (0UL) /*!< TSIF0 (Bit 0) */
|
|
|
+ #define R_CANFD_CFDGTINTSTS0_TSIF0_Msk (0x1UL) /*!< TSIF0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDGTINTSTS0_TAIF0_Pos (1UL) /*!< TAIF0 (Bit 1) */
|
|
|
+ #define R_CANFD_CFDGTINTSTS0_TAIF0_Msk (0x2UL) /*!< TAIF0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDGTINTSTS0_TQIF0_Pos (2UL) /*!< TQIF0 (Bit 2) */
|
|
|
+ #define R_CANFD_CFDGTINTSTS0_TQIF0_Msk (0x4UL) /*!< TQIF0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDGTINTSTS0_CFTIF0_Pos (3UL) /*!< CFTIF0 (Bit 3) */
|
|
|
+ #define R_CANFD_CFDGTINTSTS0_CFTIF0_Msk (0x8UL) /*!< CFTIF0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDGTINTSTS0_THIF0_Pos (4UL) /*!< THIF0 (Bit 4) */
|
|
|
+ #define R_CANFD_CFDGTINTSTS0_THIF0_Msk (0x10UL) /*!< THIF0 (Bitfield-Mask: 0x01) */
|
|
|
+/* ====================================================== CFDGTSTCFG ======================================================= */
|
|
|
+ #define R_CANFD_CFDGTSTCFG_RTMPS_Pos (16UL) /*!< RTMPS (Bit 16) */
|
|
|
+ #define R_CANFD_CFDGTSTCFG_RTMPS_Msk (0x3ff0000UL) /*!< RTMPS (Bitfield-Mask: 0x3ff) */
|
|
|
+/* ====================================================== CFDGTSTCTR ======================================================= */
|
|
|
+ #define R_CANFD_CFDGTSTCTR_RTME_Pos (2UL) /*!< RTME (Bit 2) */
|
|
|
+ #define R_CANFD_CFDGTSTCTR_RTME_Msk (0x4UL) /*!< RTME (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= CFDGFDCFG ======================================================= */
|
|
|
+ #define R_CANFD_CFDGFDCFG_RPED_Pos (0UL) /*!< RPED (Bit 0) */
|
|
|
+ #define R_CANFD_CFDGFDCFG_RPED_Msk (0x1UL) /*!< RPED (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDGFDCFG_TSCCFG_Pos (8UL) /*!< TSCCFG (Bit 8) */
|
|
|
+ #define R_CANFD_CFDGFDCFG_TSCCFG_Msk (0x300UL) /*!< TSCCFG (Bitfield-Mask: 0x03) */
|
|
|
+/* ======================================================= CFDGLOCKK ======================================================= */
|
|
|
+ #define R_CANFD_CFDGLOCKK_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */
|
|
|
+ #define R_CANFD_CFDGLOCKK_LOCK_Msk (0xffffUL) /*!< LOCK (Bitfield-Mask: 0xffff) */
|
|
|
+/* ===================================================== CFDGAFLIGNENT ===================================================== */
|
|
|
+ #define R_CANFD_CFDGAFLIGNENT_IRN_Pos (0UL) /*!< IRN (Bit 0) */
|
|
|
+ #define R_CANFD_CFDGAFLIGNENT_IRN_Msk (0x1fUL) /*!< IRN (Bitfield-Mask: 0x1f) */
|
|
|
+/* ===================================================== CFDGAFLIGNCTR ===================================================== */
|
|
|
+ #define R_CANFD_CFDGAFLIGNCTR_IREN_Pos (0UL) /*!< IREN (Bit 0) */
|
|
|
+ #define R_CANFD_CFDGAFLIGNCTR_IREN_Msk (0x1UL) /*!< IREN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDGAFLIGNCTR_KEY_Pos (8UL) /*!< KEY (Bit 8) */
|
|
|
+ #define R_CANFD_CFDGAFLIGNCTR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= CFDCDTCT ======================================================== */
|
|
|
+ #define R_CANFD_CFDCDTCT_RFDMAE0_Pos (0UL) /*!< RFDMAE0 (Bit 0) */
|
|
|
+ #define R_CANFD_CFDCDTCT_RFDMAE0_Msk (0x1UL) /*!< RFDMAE0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDCDTCT_RFDMAE1_Pos (1UL) /*!< RFDMAE1 (Bit 1) */
|
|
|
+ #define R_CANFD_CFDCDTCT_RFDMAE1_Msk (0x2UL) /*!< RFDMAE1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDCDTCT_CFDMAE0_Pos (8UL) /*!< CFDMAE0 (Bit 8) */
|
|
|
+ #define R_CANFD_CFDCDTCT_CFDMAE0_Msk (0x100UL) /*!< CFDMAE0 (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= CFDCDTSTS ======================================================= */
|
|
|
+ #define R_CANFD_CFDCDTSTS_RFDMASTS0_Pos (0UL) /*!< RFDMASTS0 (Bit 0) */
|
|
|
+ #define R_CANFD_CFDCDTSTS_RFDMASTS0_Msk (0x1UL) /*!< RFDMASTS0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDCDTSTS_RFDMASTS1_Pos (1UL) /*!< RFDMASTS1 (Bit 1) */
|
|
|
+ #define R_CANFD_CFDCDTSTS_RFDMASTS1_Msk (0x2UL) /*!< RFDMASTS1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDCDTSTS_CFDMASTS0_Pos (8UL) /*!< CFDMASTS0 (Bit 8) */
|
|
|
+ #define R_CANFD_CFDCDTSTS_CFDMASTS0_Msk (0x100UL) /*!< CFDMASTS0 (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= CFDGRSTC ======================================================== */
|
|
|
+ #define R_CANFD_CFDGRSTC_SRST_Pos (0UL) /*!< SRST (Bit 0) */
|
|
|
+ #define R_CANFD_CFDGRSTC_SRST_Msk (0x1UL) /*!< SRST (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CANFD_CFDGRSTC_KEY_Pos (8UL) /*!< KEY (Bit 8) */
|
|
|
+ #define R_CANFD_CFDGRSTC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= CFDRPGACC ======================================================= */
|
|
|
+ #define R_CANFD_CFDRPGACC_RDTA_Pos (0UL) /*!< RDTA (Bit 0) */
|
|
|
+ #define R_CANFD_CFDRPGACC_RDTA_Msk (0xffffffffUL) /*!< RDTA (Bitfield-Mask: 0xffffffff) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_CRC ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ======================================================== CRCCR0 ========================================================= */
|
|
|
+ #define R_CRC_CRCCR0_DORCLR_Pos (7UL) /*!< DORCLR (Bit 7) */
|
|
|
+ #define R_CRC_CRCCR0_DORCLR_Msk (0x80UL) /*!< DORCLR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CRC_CRCCR0_LMS_Pos (6UL) /*!< LMS (Bit 6) */
|
|
|
+ #define R_CRC_CRCCR0_LMS_Msk (0x40UL) /*!< LMS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CRC_CRCCR0_GPS_Pos (0UL) /*!< GPS (Bit 0) */
|
|
|
+ #define R_CRC_CRCCR0_GPS_Msk (0x7UL) /*!< GPS (Bitfield-Mask: 0x07) */
|
|
|
+/* ======================================================== CRCCR1 ========================================================= */
|
|
|
+ #define R_CRC_CRCCR1_CRCSEN_Pos (7UL) /*!< CRCSEN (Bit 7) */
|
|
|
+ #define R_CRC_CRCCR1_CRCSEN_Msk (0x80UL) /*!< CRCSEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CRC_CRCCR1_CRCSWR_Pos (6UL) /*!< CRCSWR (Bit 6) */
|
|
|
+ #define R_CRC_CRCCR1_CRCSWR_Msk (0x40UL) /*!< CRCSWR (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== CRCDIR ========================================================= */
|
|
|
+ #define R_CRC_CRCDIR_CRCDIR_Pos (0UL) /*!< CRCDIR (Bit 0) */
|
|
|
+ #define R_CRC_CRCDIR_CRCDIR_Msk (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================= CRCDIR_BY ======================================================= */
|
|
|
+ #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos (0UL) /*!< CRCDIR_BY (Bit 0) */
|
|
|
+ #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk (0xffUL) /*!< CRCDIR_BY (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== CRCDOR ========================================================= */
|
|
|
+ #define R_CRC_CRCDOR_CRCDOR_Pos (0UL) /*!< CRCDOR (Bit 0) */
|
|
|
+ #define R_CRC_CRCDOR_CRCDOR_Msk (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================= CRCDOR_HA ======================================================= */
|
|
|
+ #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos (0UL) /*!< CRCDOR_HA (Bit 0) */
|
|
|
+ #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk (0xffffUL) /*!< CRCDOR_HA (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================= CRCDOR_BY ======================================================= */
|
|
|
+ #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos (0UL) /*!< CRCDOR_BY (Bit 0) */
|
|
|
+ #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk (0xffUL) /*!< CRCDOR_BY (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== CRCSAR ========================================================= */
|
|
|
+ #define R_CRC_CRCSAR_CRCSA_Pos (0UL) /*!< CRCSA (Bit 0) */
|
|
|
+ #define R_CRC_CRCSAR_CRCSA_Msk (0x3fffUL) /*!< CRCSA (Bitfield-Mask: 0x3fff) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_DAC ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================= DACR ========================================================== */
|
|
|
+ #define R_DAC_DACR_DAE_Pos (5UL) /*!< DAE (Bit 5) */
|
|
|
+ #define R_DAC_DACR_DAE_Msk (0x20UL) /*!< DAE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_DAC_DACR_DAOE_Pos (6UL) /*!< DAOE (Bit 6) */
|
|
|
+ #define R_DAC_DACR_DAOE_Msk (0x40UL) /*!< DAOE (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= DADR ========================================================== */
|
|
|
+ #define R_DAC_DADR_DADR_Pos (0UL) /*!< DADR (Bit 0) */
|
|
|
+ #define R_DAC_DADR_DADR_Msk (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff) */
|
|
|
+/* ========================================================= DADPR ========================================================= */
|
|
|
+ #define R_DAC_DADPR_DPSEL_Pos (7UL) /*!< DPSEL (Bit 7) */
|
|
|
+ #define R_DAC_DADPR_DPSEL_Msk (0x80UL) /*!< DPSEL (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== DAADSCR ======================================================== */
|
|
|
+ #define R_DAC_DAADSCR_DAADST_Pos (7UL) /*!< DAADST (Bit 7) */
|
|
|
+ #define R_DAC_DAADSCR_DAADST_Msk (0x80UL) /*!< DAADST (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= DAVREFCR ======================================================== */
|
|
|
+ #define R_DAC_DAVREFCR_REF_Pos (0UL) /*!< REF (Bit 0) */
|
|
|
+ #define R_DAC_DAVREFCR_REF_Msk (0x7UL) /*!< REF (Bitfield-Mask: 0x07) */
|
|
|
+/* ========================================================= DAPC ========================================================== */
|
|
|
+ #define R_DAC_DAPC_PUMPEN_Pos (0UL) /*!< PUMPEN (Bit 0) */
|
|
|
+ #define R_DAC_DAPC_PUMPEN_Msk (0x1UL) /*!< PUMPEN (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== DAAMPCR ======================================================== */
|
|
|
+ #define R_DAC_DAAMPCR_DAAMP_Pos (6UL) /*!< DAAMP (Bit 6) */
|
|
|
+ #define R_DAC_DAAMPCR_DAAMP_Msk (0x40UL) /*!< DAAMP (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== DAASWCR ======================================================== */
|
|
|
+ #define R_DAC_DAASWCR_DAASW1_Pos (7UL) /*!< DAASW1 (Bit 7) */
|
|
|
+ #define R_DAC_DAASWCR_DAASW1_Msk (0x80UL) /*!< DAASW1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */
|
|
|
+ #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== DAADUSR ======================================================== */
|
|
|
+ #define R_DAC_DAADUSR_AMADSEL0_Pos (0UL) /*!< AMADSEL0 (Bit 0) */
|
|
|
+ #define R_DAC_DAADUSR_AMADSEL0_Msk (0x1UL) /*!< AMADSEL0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_DAC_DAADUSR_AMADSEL1_Pos (1UL) /*!< AMADSEL1 (Bit 1) */
|
|
|
+ #define R_DAC_DAADUSR_AMADSEL1_Msk (0x2UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_DEBUG ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ======================================================== DBGSTR ========================================================= */
|
|
|
+ #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos (28UL) /*!< CDBGPWRUPREQ (Bit 28) */
|
|
|
+ #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos (29UL) /*!< CDBGPWRUPACK (Bit 29) */
|
|
|
+ #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= DBGSTOPCR ======================================================= */
|
|
|
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos (24UL) /*!< DBGSTOP_RPER (Bit 24) */
|
|
|
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk (0x1000000UL) /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos (16UL) /*!< DBGSTOP_LVD (Bit 16) */
|
|
|
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk (0x10000UL) /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos (25UL) /*!< DBGSTOP_RECCR (Bit 25) */
|
|
|
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk (0x2000000UL) /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos (0UL) /*!< DBGSTOP_IWDT (Bit 0) */
|
|
|
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk (0x1UL) /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos (1UL) /*!< DBGSTOP_WDT (Bit 1) */
|
|
|
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */
|
|
|
+ #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= FSBLSTAT ======================================================== */
|
|
|
+ #define R_DEBUG_FSBLSTAT_CS_Pos (0UL) /*!< CS (Bit 0) */
|
|
|
+ #define R_DEBUG_FSBLSTAT_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_DEBUG_FSBLSTAT_RS_Pos (1UL) /*!< RS (Bit 1) */
|
|
|
+ #define R_DEBUG_FSBLSTAT_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos (8UL) /*!< FSBLCLK (Bit 8) */
|
|
|
+ #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk (0x700UL) /*!< FSBLCLK (Bitfield-Mask: 0x07) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_DMA ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================= DMAST ========================================================= */
|
|
|
+ #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */
|
|
|
+ #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== DMECHR ========================================================= */
|
|
|
+ #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */
|
|
|
+ #define R_DMA_DMECHR_DMECH_Msk (0x7UL) /*!< DMECH (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */
|
|
|
+ #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */
|
|
|
+ #define R_DMA_DMECHR_DMESTA_Msk (0x10000UL) /*!< DMESTA (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= DELSR ========================================================= */
|
|
|
+ #define R_DMA_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */
|
|
|
+ #define R_DMA_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_DMA_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */
|
|
|
+ #define R_DMA_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_DMAC0 ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================= DMSAR ========================================================= */
|
|
|
+ #define R_DMAC0_DMSAR_DMSAR_Pos (0UL) /*!< DMSAR (Bit 0) */
|
|
|
+ #define R_DMAC0_DMSAR_DMSAR_Msk (0xffffffffUL) /*!< DMSAR (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ========================================================= DMDAR ========================================================= */
|
|
|
+ #define R_DMAC0_DMDAR_DMDAR_Pos (0UL) /*!< DMDAR (Bit 0) */
|
|
|
+ #define R_DMAC0_DMDAR_DMDAR_Msk (0xffffffffUL) /*!< DMDAR (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ========================================================= DMCRA ========================================================= */
|
|
|
+ #define R_DMAC0_DMCRA_DMCRAH_Pos (16UL) /*!< DMCRAH (Bit 16) */
|
|
|
+ #define R_DMAC0_DMCRA_DMCRAH_Msk (0x3ff0000UL) /*!< DMCRAH (Bitfield-Mask: 0x3ff) */
|
|
|
+ #define R_DMAC0_DMCRA_DMCRAL_Pos (0UL) /*!< DMCRAL (Bit 0) */
|
|
|
+ #define R_DMAC0_DMCRA_DMCRAL_Msk (0xffffUL) /*!< DMCRAL (Bitfield-Mask: 0xffff) */
|
|
|
+/* ========================================================= DMCRB ========================================================= */
|
|
|
+ #define R_DMAC0_DMCRB_DMCRBL_Pos (0UL) /*!< DMCRBL (Bit 0) */
|
|
|
+ #define R_DMAC0_DMCRB_DMCRBL_Msk (0xffffUL) /*!< DMCRBL (Bitfield-Mask: 0xffff) */
|
|
|
+ #define R_DMAC0_DMCRB_DMCRBH_Pos (16UL) /*!< DMCRBH (Bit 16) */
|
|
|
+ #define R_DMAC0_DMCRB_DMCRBH_Msk (0xffff0000UL) /*!< DMCRBH (Bitfield-Mask: 0xffff) */
|
|
|
+/* ========================================================= DMTMD ========================================================= */
|
|
|
+ #define R_DMAC0_DMTMD_MD_Pos (14UL) /*!< MD (Bit 14) */
|
|
|
+ #define R_DMAC0_DMTMD_MD_Msk (0xc000UL) /*!< MD (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_DMAC0_DMTMD_DTS_Pos (12UL) /*!< DTS (Bit 12) */
|
|
|
+ #define R_DMAC0_DMTMD_DTS_Msk (0x3000UL) /*!< DTS (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_DMAC0_DMTMD_SZ_Pos (8UL) /*!< SZ (Bit 8) */
|
|
|
+ #define R_DMAC0_DMTMD_SZ_Msk (0x300UL) /*!< SZ (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_DMAC0_DMTMD_DCTG_Pos (0UL) /*!< DCTG (Bit 0) */
|
|
|
+ #define R_DMAC0_DMTMD_DCTG_Msk (0x3UL) /*!< DCTG (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_DMAC0_DMTMD_TKP_Pos (10UL) /*!< TKP (Bit 10) */
|
|
|
+ #define R_DMAC0_DMTMD_TKP_Msk (0x400UL) /*!< TKP (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= DMINT ========================================================= */
|
|
|
+ #define R_DMAC0_DMINT_DTIE_Pos (4UL) /*!< DTIE (Bit 4) */
|
|
|
+ #define R_DMAC0_DMINT_DTIE_Msk (0x10UL) /*!< DTIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_DMAC0_DMINT_ESIE_Pos (3UL) /*!< ESIE (Bit 3) */
|
|
|
+ #define R_DMAC0_DMINT_ESIE_Msk (0x8UL) /*!< ESIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_DMAC0_DMINT_RPTIE_Pos (2UL) /*!< RPTIE (Bit 2) */
|
|
|
+ #define R_DMAC0_DMINT_RPTIE_Msk (0x4UL) /*!< RPTIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_DMAC0_DMINT_SARIE_Pos (1UL) /*!< SARIE (Bit 1) */
|
|
|
+ #define R_DMAC0_DMINT_SARIE_Msk (0x2UL) /*!< SARIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_DMAC0_DMINT_DARIE_Pos (0UL) /*!< DARIE (Bit 0) */
|
|
|
+ #define R_DMAC0_DMINT_DARIE_Msk (0x1UL) /*!< DARIE (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= DMAMD ========================================================= */
|
|
|
+ #define R_DMAC0_DMAMD_SM_Pos (14UL) /*!< SM (Bit 14) */
|
|
|
+ #define R_DMAC0_DMAMD_SM_Msk (0xc000UL) /*!< SM (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_DMAC0_DMAMD_SARA_Pos (8UL) /*!< SARA (Bit 8) */
|
|
|
+ #define R_DMAC0_DMAMD_SARA_Msk (0x1f00UL) /*!< SARA (Bitfield-Mask: 0x1f) */
|
|
|
+ #define R_DMAC0_DMAMD_DM_Pos (6UL) /*!< DM (Bit 6) */
|
|
|
+ #define R_DMAC0_DMAMD_DM_Msk (0xc0UL) /*!< DM (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_DMAC0_DMAMD_DARA_Pos (0UL) /*!< DARA (Bit 0) */
|
|
|
+ #define R_DMAC0_DMAMD_DARA_Msk (0x1fUL) /*!< DARA (Bitfield-Mask: 0x1f) */
|
|
|
+ #define R_DMAC0_DMAMD_DADR_Pos (5UL) /*!< DADR (Bit 5) */
|
|
|
+ #define R_DMAC0_DMAMD_DADR_Msk (0x20UL) /*!< DADR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_DMAC0_DMAMD_SADR_Pos (13UL) /*!< SADR (Bit 13) */
|
|
|
+ #define R_DMAC0_DMAMD_SADR_Msk (0x2000UL) /*!< SADR (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= DMOFR ========================================================= */
|
|
|
+ #define R_DMAC0_DMOFR_DMOFR_Pos (0UL) /*!< DMOFR (Bit 0) */
|
|
|
+ #define R_DMAC0_DMOFR_DMOFR_Msk (0xffffffffUL) /*!< DMOFR (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ========================================================= DMCNT ========================================================= */
|
|
|
+ #define R_DMAC0_DMCNT_DTE_Pos (0UL) /*!< DTE (Bit 0) */
|
|
|
+ #define R_DMAC0_DMCNT_DTE_Msk (0x1UL) /*!< DTE (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= DMREQ ========================================================= */
|
|
|
+ #define R_DMAC0_DMREQ_CLRS_Pos (4UL) /*!< CLRS (Bit 4) */
|
|
|
+ #define R_DMAC0_DMREQ_CLRS_Msk (0x10UL) /*!< CLRS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_DMAC0_DMREQ_SWREQ_Pos (0UL) /*!< SWREQ (Bit 0) */
|
|
|
+ #define R_DMAC0_DMREQ_SWREQ_Msk (0x1UL) /*!< SWREQ (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= DMSTS ========================================================= */
|
|
|
+ #define R_DMAC0_DMSTS_ACT_Pos (7UL) /*!< ACT (Bit 7) */
|
|
|
+ #define R_DMAC0_DMSTS_ACT_Msk (0x80UL) /*!< ACT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_DMAC0_DMSTS_DTIF_Pos (4UL) /*!< DTIF (Bit 4) */
|
|
|
+ #define R_DMAC0_DMSTS_DTIF_Msk (0x10UL) /*!< DTIF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_DMAC0_DMSTS_ESIF_Pos (0UL) /*!< ESIF (Bit 0) */
|
|
|
+ #define R_DMAC0_DMSTS_ESIF_Msk (0x1UL) /*!< ESIF (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= DMSRR ========================================================= */
|
|
|
+/* ========================================================= DMDRR ========================================================= */
|
|
|
+/* ========================================================= DMSBS ========================================================= */
|
|
|
+ #define R_DMAC0_DMSBS_DMSBSL_Pos (0UL) /*!< DMSBSL (Bit 0) */
|
|
|
+ #define R_DMAC0_DMSBS_DMSBSL_Msk (0xffffUL) /*!< DMSBSL (Bitfield-Mask: 0xffff) */
|
|
|
+ #define R_DMAC0_DMSBS_DMSBSH_Pos (16UL) /*!< DMSBSH (Bit 16) */
|
|
|
+ #define R_DMAC0_DMSBS_DMSBSH_Msk (0xffff0000UL) /*!< DMSBSH (Bitfield-Mask: 0xffff) */
|
|
|
+/* ========================================================= DMDBS ========================================================= */
|
|
|
+ #define R_DMAC0_DMDBS_DMDBSL_Pos (0UL) /*!< DMDBSL (Bit 0) */
|
|
|
+ #define R_DMAC0_DMDBS_DMDBSL_Msk (0xffffUL) /*!< DMDBSL (Bitfield-Mask: 0xffff) */
|
|
|
+ #define R_DMAC0_DMDBS_DMDBSH_Pos (16UL) /*!< DMDBSH (Bit 16) */
|
|
|
+ #define R_DMAC0_DMDBS_DMDBSH_Msk (0xffff0000UL) /*!< DMDBSH (Bitfield-Mask: 0xffff) */
|
|
|
+/* ========================================================= DMBWR ========================================================= */
|
|
|
+ #define R_DMAC0_DMBWR_BWE_Pos (0UL) /*!< BWE (Bit 0) */
|
|
|
+ #define R_DMAC0_DMBWR_BWE_Msk (0x1UL) /*!< BWE (Bitfield-Mask: 0x01) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_DOC ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================= DOCR ========================================================== */
|
|
|
+ #define R_DOC_DOCR_DOPCFCL_Pos (6UL) /*!< DOPCFCL (Bit 6) */
|
|
|
+ #define R_DOC_DOCR_DOPCFCL_Msk (0x40UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_DOC_DOCR_DOPCF_Pos (5UL) /*!< DOPCF (Bit 5) */
|
|
|
+ #define R_DOC_DOCR_DOPCF_Msk (0x20UL) /*!< DOPCF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_DOC_DOCR_DCSEL_Pos (2UL) /*!< DCSEL (Bit 2) */
|
|
|
+ #define R_DOC_DOCR_DCSEL_Msk (0x4UL) /*!< DCSEL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_DOC_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */
|
|
|
+ #define R_DOC_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */
|
|
|
+/* ========================================================= DODIR ========================================================= */
|
|
|
+ #define R_DOC_DODIR_DODIR_Pos (0UL) /*!< DODIR (Bit 0) */
|
|
|
+ #define R_DOC_DODIR_DODIR_Msk (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff) */
|
|
|
+/* ========================================================= DODSR ========================================================= */
|
|
|
+ #define R_DOC_DODSR_DODSR_Pos (0UL) /*!< DODSR (Bit 0) */
|
|
|
+ #define R_DOC_DODSR_DODSR_Msk (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_DTC ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================= DTCCR ========================================================= */
|
|
|
+ #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */
|
|
|
+ #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== DTCVBR ========================================================= */
|
|
|
+ #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */
|
|
|
+ #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ========================================================= DTCST ========================================================= */
|
|
|
+ #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */
|
|
|
+ #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== DTCSTS ========================================================= */
|
|
|
+ #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */
|
|
|
+ #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */
|
|
|
+ #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= DTCCR_SEC ======================================================= */
|
|
|
+ #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */
|
|
|
+ #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */
|
|
|
+/* ====================================================== DTCVBR_SEC ======================================================= */
|
|
|
+/* ========================================================= DTEVR ========================================================= */
|
|
|
+ #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */
|
|
|
+ #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */
|
|
|
+ #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */
|
|
|
+ #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_ELC ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================= ELCR ========================================================== */
|
|
|
+ #define R_ELC_ELCR_ELCON_Pos (7UL) /*!< ELCON (Bit 7) */
|
|
|
+ #define R_ELC_ELCR_ELCON_Msk (0x80UL) /*!< ELCON (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== ELCSARA ======================================================== */
|
|
|
+ #define R_ELC_ELCSARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */
|
|
|
+ #define R_ELC_ELCSARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ELC_ELCSARA_ELSEGR0_Pos (1UL) /*!< ELSEGR0 (Bit 1) */
|
|
|
+ #define R_ELC_ELCSARA_ELSEGR0_Msk (0x2UL) /*!< ELSEGR0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ELC_ELCSARA_ELSEGR1_Pos (2UL) /*!< ELSEGR1 (Bit 2) */
|
|
|
+ #define R_ELC_ELCSARA_ELSEGR1_Msk (0x4UL) /*!< ELSEGR1 (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== ELCSARB ======================================================== */
|
|
|
+ #define R_ELC_ELCSARB_ELSR_Pos (0UL) /*!< ELSR (Bit 0) */
|
|
|
+ #define R_ELC_ELCSARB_ELSR_Msk (0x1UL) /*!< ELSR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ELC_ELCSARB_ELSR30_Pos (30UL) /*!< ELSR30 (Bit 30) */
|
|
|
+ #define R_ELC_ELCSARB_ELSR30_Msk (0x40000000UL) /*!< ELSR30 (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== ELCPARA ======================================================== */
|
|
|
+ #define R_ELC_ELCPARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */
|
|
|
+ #define R_ELC_ELCPARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ELC_ELCPARA_ELSEGR0_Pos (1UL) /*!< ELSEGR0 (Bit 1) */
|
|
|
+ #define R_ELC_ELCPARA_ELSEGR0_Msk (0x2UL) /*!< ELSEGR0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ELC_ELCPARA_ELSEGR1_Pos (2UL) /*!< ELSEGR1 (Bit 2) */
|
|
|
+ #define R_ELC_ELCPARA_ELSEGR1_Msk (0x4UL) /*!< ELSEGR1 (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== ELCPARB ======================================================== */
|
|
|
+ #define R_ELC_ELCPARB_ELSR_Pos (0UL) /*!< ELSR (Bit 0) */
|
|
|
+ #define R_ELC_ELCPARB_ELSR_Msk (0x1UL) /*!< ELSR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ELC_ELCPARB_ELSR30_Pos (30UL) /*!< ELSR30 (Bit 30) */
|
|
|
+ #define R_ELC_ELCPARB_ELSR30_Msk (0x40000000UL) /*!< ELSR30 (Bitfield-Mask: 0x01) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_ETHERC0 ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================= ECMR ========================================================== */
|
|
|
+ #define R_ETHERC0_ECMR_TPC_Pos (20UL) /*!< TPC (Bit 20) */
|
|
|
+ #define R_ETHERC0_ECMR_TPC_Msk (0x100000UL) /*!< TPC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC0_ECMR_ZPF_Pos (19UL) /*!< ZPF (Bit 19) */
|
|
|
+ #define R_ETHERC0_ECMR_ZPF_Msk (0x80000UL) /*!< ZPF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC0_ECMR_PFR_Pos (18UL) /*!< PFR (Bit 18) */
|
|
|
+ #define R_ETHERC0_ECMR_PFR_Msk (0x40000UL) /*!< PFR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC0_ECMR_RXF_Pos (17UL) /*!< RXF (Bit 17) */
|
|
|
+ #define R_ETHERC0_ECMR_RXF_Msk (0x20000UL) /*!< RXF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC0_ECMR_TXF_Pos (16UL) /*!< TXF (Bit 16) */
|
|
|
+ #define R_ETHERC0_ECMR_TXF_Msk (0x10000UL) /*!< TXF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC0_ECMR_PRCEF_Pos (12UL) /*!< PRCEF (Bit 12) */
|
|
|
+ #define R_ETHERC0_ECMR_PRCEF_Msk (0x1000UL) /*!< PRCEF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC0_ECMR_MPDE_Pos (9UL) /*!< MPDE (Bit 9) */
|
|
|
+ #define R_ETHERC0_ECMR_MPDE_Msk (0x200UL) /*!< MPDE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC0_ECMR_RE_Pos (6UL) /*!< RE (Bit 6) */
|
|
|
+ #define R_ETHERC0_ECMR_RE_Msk (0x40UL) /*!< RE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC0_ECMR_TE_Pos (5UL) /*!< TE (Bit 5) */
|
|
|
+ #define R_ETHERC0_ECMR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC0_ECMR_ILB_Pos (3UL) /*!< ILB (Bit 3) */
|
|
|
+ #define R_ETHERC0_ECMR_ILB_Msk (0x8UL) /*!< ILB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC0_ECMR_RTM_Pos (2UL) /*!< RTM (Bit 2) */
|
|
|
+ #define R_ETHERC0_ECMR_RTM_Msk (0x4UL) /*!< RTM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC0_ECMR_DM_Pos (1UL) /*!< DM (Bit 1) */
|
|
|
+ #define R_ETHERC0_ECMR_DM_Msk (0x2UL) /*!< DM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC0_ECMR_PRM_Pos (0UL) /*!< PRM (Bit 0) */
|
|
|
+ #define R_ETHERC0_ECMR_PRM_Msk (0x1UL) /*!< PRM (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= RFLR ========================================================== */
|
|
|
+ #define R_ETHERC0_RFLR_RFL_Pos (0UL) /*!< RFL (Bit 0) */
|
|
|
+ #define R_ETHERC0_RFLR_RFL_Msk (0xfffUL) /*!< RFL (Bitfield-Mask: 0xfff) */
|
|
|
+/* ========================================================= ECSR ========================================================== */
|
|
|
+ #define R_ETHERC0_ECSR_BFR_Pos (5UL) /*!< BFR (Bit 5) */
|
|
|
+ #define R_ETHERC0_ECSR_BFR_Msk (0x20UL) /*!< BFR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC0_ECSR_PSRTO_Pos (4UL) /*!< PSRTO (Bit 4) */
|
|
|
+ #define R_ETHERC0_ECSR_PSRTO_Msk (0x10UL) /*!< PSRTO (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC0_ECSR_LCHNG_Pos (2UL) /*!< LCHNG (Bit 2) */
|
|
|
+ #define R_ETHERC0_ECSR_LCHNG_Msk (0x4UL) /*!< LCHNG (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC0_ECSR_MPD_Pos (1UL) /*!< MPD (Bit 1) */
|
|
|
+ #define R_ETHERC0_ECSR_MPD_Msk (0x2UL) /*!< MPD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC0_ECSR_ICD_Pos (0UL) /*!< ICD (Bit 0) */
|
|
|
+ #define R_ETHERC0_ECSR_ICD_Msk (0x1UL) /*!< ICD (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== ECSIPR ========================================================= */
|
|
|
+ #define R_ETHERC0_ECSIPR_BFSIPR_Pos (5UL) /*!< BFSIPR (Bit 5) */
|
|
|
+ #define R_ETHERC0_ECSIPR_BFSIPR_Msk (0x20UL) /*!< BFSIPR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC0_ECSIPR_PSRTOIP_Pos (4UL) /*!< PSRTOIP (Bit 4) */
|
|
|
+ #define R_ETHERC0_ECSIPR_PSRTOIP_Msk (0x10UL) /*!< PSRTOIP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC0_ECSIPR_LCHNGIP_Pos (2UL) /*!< LCHNGIP (Bit 2) */
|
|
|
+ #define R_ETHERC0_ECSIPR_LCHNGIP_Msk (0x4UL) /*!< LCHNGIP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC0_ECSIPR_MPDIP_Pos (1UL) /*!< MPDIP (Bit 1) */
|
|
|
+ #define R_ETHERC0_ECSIPR_MPDIP_Msk (0x2UL) /*!< MPDIP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC0_ECSIPR_ICDIP_Pos (0UL) /*!< ICDIP (Bit 0) */
|
|
|
+ #define R_ETHERC0_ECSIPR_ICDIP_Msk (0x1UL) /*!< ICDIP (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================== PIR ========================================================== */
|
|
|
+ #define R_ETHERC0_PIR_MDI_Pos (3UL) /*!< MDI (Bit 3) */
|
|
|
+ #define R_ETHERC0_PIR_MDI_Msk (0x8UL) /*!< MDI (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC0_PIR_MDO_Pos (2UL) /*!< MDO (Bit 2) */
|
|
|
+ #define R_ETHERC0_PIR_MDO_Msk (0x4UL) /*!< MDO (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC0_PIR_MMD_Pos (1UL) /*!< MMD (Bit 1) */
|
|
|
+ #define R_ETHERC0_PIR_MMD_Msk (0x2UL) /*!< MMD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC0_PIR_MDC_Pos (0UL) /*!< MDC (Bit 0) */
|
|
|
+ #define R_ETHERC0_PIR_MDC_Msk (0x1UL) /*!< MDC (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================== PSR ========================================================== */
|
|
|
+ #define R_ETHERC0_PSR_LMON_Pos (0UL) /*!< LMON (Bit 0) */
|
|
|
+ #define R_ETHERC0_PSR_LMON_Msk (0x1UL) /*!< LMON (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= RDMLR ========================================================= */
|
|
|
+ #define R_ETHERC0_RDMLR_RMD_Pos (0UL) /*!< RMD (Bit 0) */
|
|
|
+ #define R_ETHERC0_RDMLR_RMD_Msk (0xfffffUL) /*!< RMD (Bitfield-Mask: 0xfffff) */
|
|
|
+/* ========================================================= IPGR ========================================================== */
|
|
|
+ #define R_ETHERC0_IPGR_IPG_Pos (0UL) /*!< IPG (Bit 0) */
|
|
|
+ #define R_ETHERC0_IPGR_IPG_Msk (0x1fUL) /*!< IPG (Bitfield-Mask: 0x1f) */
|
|
|
+/* ========================================================== APR ========================================================== */
|
|
|
+ #define R_ETHERC0_APR_AP_Pos (0UL) /*!< AP (Bit 0) */
|
|
|
+ #define R_ETHERC0_APR_AP_Msk (0xffffUL) /*!< AP (Bitfield-Mask: 0xffff) */
|
|
|
+/* ========================================================== MPR ========================================================== */
|
|
|
+ #define R_ETHERC0_MPR_MP_Pos (0UL) /*!< MP (Bit 0) */
|
|
|
+ #define R_ETHERC0_MPR_MP_Msk (0xffffUL) /*!< MP (Bitfield-Mask: 0xffff) */
|
|
|
+/* ========================================================= RFCF ========================================================== */
|
|
|
+ #define R_ETHERC0_RFCF_RPAUSE_Pos (0UL) /*!< RPAUSE (Bit 0) */
|
|
|
+ #define R_ETHERC0_RFCF_RPAUSE_Msk (0xffUL) /*!< RPAUSE (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== TPAUSER ======================================================== */
|
|
|
+ #define R_ETHERC0_TPAUSER_TPAUSE_Pos (0UL) /*!< TPAUSE (Bit 0) */
|
|
|
+ #define R_ETHERC0_TPAUSER_TPAUSE_Msk (0xffffUL) /*!< TPAUSE (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================= TPAUSECR ======================================================== */
|
|
|
+/* ========================================================= BCFRR ========================================================= */
|
|
|
+ #define R_ETHERC0_BCFRR_BCF_Pos (0UL) /*!< BCF (Bit 0) */
|
|
|
+ #define R_ETHERC0_BCFRR_BCF_Msk (0xffffUL) /*!< BCF (Bitfield-Mask: 0xffff) */
|
|
|
+/* ========================================================= MAHR ========================================================== */
|
|
|
+ #define R_ETHERC0_MAHR_MAHR_Pos (0UL) /*!< MAHR (Bit 0) */
|
|
|
+ #define R_ETHERC0_MAHR_MAHR_Msk (0xffffffffUL) /*!< MAHR (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ========================================================= MALR ========================================================== */
|
|
|
+ #define R_ETHERC0_MALR_MALR_Pos (0UL) /*!< MALR (Bit 0) */
|
|
|
+ #define R_ETHERC0_MALR_MALR_Msk (0xffffUL) /*!< MALR (Bitfield-Mask: 0xffff) */
|
|
|
+/* ========================================================= TROCR ========================================================= */
|
|
|
+ #define R_ETHERC0_TROCR_TROCR_Pos (0UL) /*!< TROCR (Bit 0) */
|
|
|
+ #define R_ETHERC0_TROCR_TROCR_Msk (0xffffffffUL) /*!< TROCR (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ========================================================= CDCR ========================================================== */
|
|
|
+/* ========================================================= LCCR ========================================================== */
|
|
|
+ #define R_ETHERC0_LCCR_LCCR_Pos (0UL) /*!< LCCR (Bit 0) */
|
|
|
+ #define R_ETHERC0_LCCR_LCCR_Msk (0xffffffffUL) /*!< LCCR (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ========================================================= CNDCR ========================================================= */
|
|
|
+ #define R_ETHERC0_CNDCR_CNDCR_Pos (0UL) /*!< CNDCR (Bit 0) */
|
|
|
+ #define R_ETHERC0_CNDCR_CNDCR_Msk (0xffffffffUL) /*!< CNDCR (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ========================================================= CEFCR ========================================================= */
|
|
|
+ #define R_ETHERC0_CEFCR_CEFCR_Pos (0UL) /*!< CEFCR (Bit 0) */
|
|
|
+ #define R_ETHERC0_CEFCR_CEFCR_Msk (0xffffffffUL) /*!< CEFCR (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ========================================================= FRECR ========================================================= */
|
|
|
+ #define R_ETHERC0_FRECR_FRECR_Pos (0UL) /*!< FRECR (Bit 0) */
|
|
|
+ #define R_ETHERC0_FRECR_FRECR_Msk (0xffffffffUL) /*!< FRECR (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================== TSFRCR ========================================================= */
|
|
|
+ #define R_ETHERC0_TSFRCR_TSFRCR_Pos (0UL) /*!< TSFRCR (Bit 0) */
|
|
|
+ #define R_ETHERC0_TSFRCR_TSFRCR_Msk (0xffffffffUL) /*!< TSFRCR (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================== TLFRCR ========================================================= */
|
|
|
+ #define R_ETHERC0_TLFRCR_TLFRCR_Pos (0UL) /*!< TLFRCR (Bit 0) */
|
|
|
+ #define R_ETHERC0_TLFRCR_TLFRCR_Msk (0xffffffffUL) /*!< TLFRCR (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ========================================================= RFCR ========================================================== */
|
|
|
+ #define R_ETHERC0_RFCR_RFCR_Pos (0UL) /*!< RFCR (Bit 0) */
|
|
|
+ #define R_ETHERC0_RFCR_RFCR_Msk (0xffffffffUL) /*!< RFCR (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ========================================================= MAFCR ========================================================= */
|
|
|
+ #define R_ETHERC0_MAFCR_MAFCR_Pos (0UL) /*!< MAFCR (Bit 0) */
|
|
|
+ #define R_ETHERC0_MAFCR_MAFCR_Msk (0xffffffffUL) /*!< MAFCR (Bitfield-Mask: 0xffffffff) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_ETHERC_EDMAC ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================= EDMR ========================================================== */
|
|
|
+ #define R_ETHERC_EDMAC_EDMR_DE_Pos (6UL) /*!< DE (Bit 6) */
|
|
|
+ #define R_ETHERC_EDMAC_EDMR_DE_Msk (0x40UL) /*!< DE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC_EDMAC_EDMR_DL_Pos (4UL) /*!< DL (Bit 4) */
|
|
|
+ #define R_ETHERC_EDMAC_EDMR_DL_Msk (0x30UL) /*!< DL (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_ETHERC_EDMAC_EDMR_SWR_Pos (0UL) /*!< SWR (Bit 0) */
|
|
|
+ #define R_ETHERC_EDMAC_EDMR_SWR_Msk (0x1UL) /*!< SWR (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= EDTRR ========================================================= */
|
|
|
+ #define R_ETHERC_EDMAC_EDTRR_TR_Pos (0UL) /*!< TR (Bit 0) */
|
|
|
+ #define R_ETHERC_EDMAC_EDTRR_TR_Msk (0x1UL) /*!< TR (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= EDRRR ========================================================= */
|
|
|
+ #define R_ETHERC_EDMAC_EDRRR_RR_Pos (0UL) /*!< RR (Bit 0) */
|
|
|
+ #define R_ETHERC_EDMAC_EDRRR_RR_Msk (0x1UL) /*!< RR (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= TDLAR ========================================================= */
|
|
|
+ #define R_ETHERC_EDMAC_TDLAR_TDLAR_Pos (0UL) /*!< TDLAR (Bit 0) */
|
|
|
+ #define R_ETHERC_EDMAC_TDLAR_TDLAR_Msk (0xffffffffUL) /*!< TDLAR (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ========================================================= RDLAR ========================================================= */
|
|
|
+ #define R_ETHERC_EDMAC_RDLAR_RDLAR_Pos (0UL) /*!< RDLAR (Bit 0) */
|
|
|
+ #define R_ETHERC_EDMAC_RDLAR_RDLAR_Msk (0xffffffffUL) /*!< RDLAR (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ========================================================= EESR ========================================================== */
|
|
|
+ #define R_ETHERC_EDMAC_EESR_TWB_Pos (30UL) /*!< TWB (Bit 30) */
|
|
|
+ #define R_ETHERC_EDMAC_EESR_TWB_Msk (0x40000000UL) /*!< TWB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC_EDMAC_EESR_TABT_Pos (26UL) /*!< TABT (Bit 26) */
|
|
|
+ #define R_ETHERC_EDMAC_EESR_TABT_Msk (0x4000000UL) /*!< TABT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC_EDMAC_EESR_RABT_Pos (25UL) /*!< RABT (Bit 25) */
|
|
|
+ #define R_ETHERC_EDMAC_EESR_RABT_Msk (0x2000000UL) /*!< RABT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC_EDMAC_EESR_RFCOF_Pos (24UL) /*!< RFCOF (Bit 24) */
|
|
|
+ #define R_ETHERC_EDMAC_EESR_RFCOF_Msk (0x1000000UL) /*!< RFCOF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC_EDMAC_EESR_ADE_Pos (23UL) /*!< ADE (Bit 23) */
|
|
|
+ #define R_ETHERC_EDMAC_EESR_ADE_Msk (0x800000UL) /*!< ADE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC_EDMAC_EESR_ECI_Pos (22UL) /*!< ECI (Bit 22) */
|
|
|
+ #define R_ETHERC_EDMAC_EESR_ECI_Msk (0x400000UL) /*!< ECI (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC_EDMAC_EESR_TC_Pos (21UL) /*!< TC (Bit 21) */
|
|
|
+ #define R_ETHERC_EDMAC_EESR_TC_Msk (0x200000UL) /*!< TC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC_EDMAC_EESR_TDE_Pos (20UL) /*!< TDE (Bit 20) */
|
|
|
+ #define R_ETHERC_EDMAC_EESR_TDE_Msk (0x100000UL) /*!< TDE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC_EDMAC_EESR_TFUF_Pos (19UL) /*!< TFUF (Bit 19) */
|
|
|
+ #define R_ETHERC_EDMAC_EESR_TFUF_Msk (0x80000UL) /*!< TFUF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC_EDMAC_EESR_FR_Pos (18UL) /*!< FR (Bit 18) */
|
|
|
+ #define R_ETHERC_EDMAC_EESR_FR_Msk (0x40000UL) /*!< FR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC_EDMAC_EESR_RDE_Pos (17UL) /*!< RDE (Bit 17) */
|
|
|
+ #define R_ETHERC_EDMAC_EESR_RDE_Msk (0x20000UL) /*!< RDE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC_EDMAC_EESR_RFOF_Pos (16UL) /*!< RFOF (Bit 16) */
|
|
|
+ #define R_ETHERC_EDMAC_EESR_RFOF_Msk (0x10000UL) /*!< RFOF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC_EDMAC_EESR_CND_Pos (11UL) /*!< CND (Bit 11) */
|
|
|
+ #define R_ETHERC_EDMAC_EESR_CND_Msk (0x800UL) /*!< CND (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC_EDMAC_EESR_DLC_Pos (10UL) /*!< DLC (Bit 10) */
|
|
|
+ #define R_ETHERC_EDMAC_EESR_DLC_Msk (0x400UL) /*!< DLC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC_EDMAC_EESR_CD_Pos (9UL) /*!< CD (Bit 9) */
|
|
|
+ #define R_ETHERC_EDMAC_EESR_CD_Msk (0x200UL) /*!< CD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC_EDMAC_EESR_TRO_Pos (8UL) /*!< TRO (Bit 8) */
|
|
|
+ #define R_ETHERC_EDMAC_EESR_TRO_Msk (0x100UL) /*!< TRO (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC_EDMAC_EESR_RMAF_Pos (7UL) /*!< RMAF (Bit 7) */
|
|
|
+ #define R_ETHERC_EDMAC_EESR_RMAF_Msk (0x80UL) /*!< RMAF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC_EDMAC_EESR_RRF_Pos (4UL) /*!< RRF (Bit 4) */
|
|
|
+ #define R_ETHERC_EDMAC_EESR_RRF_Msk (0x10UL) /*!< RRF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC_EDMAC_EESR_RTLF_Pos (3UL) /*!< RTLF (Bit 3) */
|
|
|
+ #define R_ETHERC_EDMAC_EESR_RTLF_Msk (0x8UL) /*!< RTLF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC_EDMAC_EESR_RTSF_Pos (2UL) /*!< RTSF (Bit 2) */
|
|
|
+ #define R_ETHERC_EDMAC_EESR_RTSF_Msk (0x4UL) /*!< RTSF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC_EDMAC_EESR_PRE_Pos (1UL) /*!< PRE (Bit 1) */
|
|
|
+ #define R_ETHERC_EDMAC_EESR_PRE_Msk (0x2UL) /*!< PRE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC_EDMAC_EESR_CERF_Pos (0UL) /*!< CERF (Bit 0) */
|
|
|
+ #define R_ETHERC_EDMAC_EESR_CERF_Msk (0x1UL) /*!< CERF (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== EESIPR ========================================================= */
|
|
|
+ #define R_ETHERC_EDMAC_EESIPR_TWBIP_Pos (30UL) /*!< TWBIP (Bit 30) */
|
|
|
+ #define R_ETHERC_EDMAC_EESIPR_TWBIP_Msk (0x40000000UL) /*!< TWBIP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC_EDMAC_EESIPR_TABTIP_Pos (26UL) /*!< TABTIP (Bit 26) */
|
|
|
+ #define R_ETHERC_EDMAC_EESIPR_TABTIP_Msk (0x4000000UL) /*!< TABTIP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC_EDMAC_EESIPR_RABTIP_Pos (25UL) /*!< RABTIP (Bit 25) */
|
|
|
+ #define R_ETHERC_EDMAC_EESIPR_RABTIP_Msk (0x2000000UL) /*!< RABTIP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Pos (24UL) /*!< RFCOFIP (Bit 24) */
|
|
|
+ #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Msk (0x1000000UL) /*!< RFCOFIP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC_EDMAC_EESIPR_ADEIP_Pos (23UL) /*!< ADEIP (Bit 23) */
|
|
|
+ #define R_ETHERC_EDMAC_EESIPR_ADEIP_Msk (0x800000UL) /*!< ADEIP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC_EDMAC_EESIPR_ECIIP_Pos (22UL) /*!< ECIIP (Bit 22) */
|
|
|
+ #define R_ETHERC_EDMAC_EESIPR_ECIIP_Msk (0x400000UL) /*!< ECIIP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC_EDMAC_EESIPR_TCIP_Pos (21UL) /*!< TCIP (Bit 21) */
|
|
|
+ #define R_ETHERC_EDMAC_EESIPR_TCIP_Msk (0x200000UL) /*!< TCIP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC_EDMAC_EESIPR_TDEIP_Pos (20UL) /*!< TDEIP (Bit 20) */
|
|
|
+ #define R_ETHERC_EDMAC_EESIPR_TDEIP_Msk (0x100000UL) /*!< TDEIP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Pos (19UL) /*!< TFUFIP (Bit 19) */
|
|
|
+ #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Msk (0x80000UL) /*!< TFUFIP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC_EDMAC_EESIPR_FRIP_Pos (18UL) /*!< FRIP (Bit 18) */
|
|
|
+ #define R_ETHERC_EDMAC_EESIPR_FRIP_Msk (0x40000UL) /*!< FRIP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC_EDMAC_EESIPR_RDEIP_Pos (17UL) /*!< RDEIP (Bit 17) */
|
|
|
+ #define R_ETHERC_EDMAC_EESIPR_RDEIP_Msk (0x20000UL) /*!< RDEIP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Pos (16UL) /*!< RFOFIP (Bit 16) */
|
|
|
+ #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Msk (0x10000UL) /*!< RFOFIP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC_EDMAC_EESIPR_CNDIP_Pos (11UL) /*!< CNDIP (Bit 11) */
|
|
|
+ #define R_ETHERC_EDMAC_EESIPR_CNDIP_Msk (0x800UL) /*!< CNDIP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC_EDMAC_EESIPR_DLCIP_Pos (10UL) /*!< DLCIP (Bit 10) */
|
|
|
+ #define R_ETHERC_EDMAC_EESIPR_DLCIP_Msk (0x400UL) /*!< DLCIP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC_EDMAC_EESIPR_CDIP_Pos (9UL) /*!< CDIP (Bit 9) */
|
|
|
+ #define R_ETHERC_EDMAC_EESIPR_CDIP_Msk (0x200UL) /*!< CDIP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC_EDMAC_EESIPR_TROIP_Pos (8UL) /*!< TROIP (Bit 8) */
|
|
|
+ #define R_ETHERC_EDMAC_EESIPR_TROIP_Msk (0x100UL) /*!< TROIP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Pos (7UL) /*!< RMAFIP (Bit 7) */
|
|
|
+ #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Msk (0x80UL) /*!< RMAFIP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC_EDMAC_EESIPR_RRFIP_Pos (4UL) /*!< RRFIP (Bit 4) */
|
|
|
+ #define R_ETHERC_EDMAC_EESIPR_RRFIP_Msk (0x10UL) /*!< RRFIP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Pos (3UL) /*!< RTLFIP (Bit 3) */
|
|
|
+ #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Msk (0x8UL) /*!< RTLFIP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Pos (2UL) /*!< RTSFIP (Bit 2) */
|
|
|
+ #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Msk (0x4UL) /*!< RTSFIP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC_EDMAC_EESIPR_PREIP_Pos (1UL) /*!< PREIP (Bit 1) */
|
|
|
+ #define R_ETHERC_EDMAC_EESIPR_PREIP_Msk (0x2UL) /*!< PREIP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC_EDMAC_EESIPR_CERFIP_Pos (0UL) /*!< CERFIP (Bit 0) */
|
|
|
+ #define R_ETHERC_EDMAC_EESIPR_CERFIP_Msk (0x1UL) /*!< CERFIP (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== TRSCER ========================================================= */
|
|
|
+ #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Pos (7UL) /*!< RMAFCE (Bit 7) */
|
|
|
+ #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Msk (0x80UL) /*!< RMAFCE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC_EDMAC_TRSCER_RRFCE_Pos (4UL) /*!< RRFCE (Bit 4) */
|
|
|
+ #define R_ETHERC_EDMAC_TRSCER_RRFCE_Msk (0x10UL) /*!< RRFCE (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= RMFCR ========================================================= */
|
|
|
+ #define R_ETHERC_EDMAC_RMFCR_MFC_Pos (0UL) /*!< MFC (Bit 0) */
|
|
|
+ #define R_ETHERC_EDMAC_RMFCR_MFC_Msk (0xffffUL) /*!< MFC (Bitfield-Mask: 0xffff) */
|
|
|
+/* ========================================================= TFTR ========================================================== */
|
|
|
+ #define R_ETHERC_EDMAC_TFTR_TFT_Pos (0UL) /*!< TFT (Bit 0) */
|
|
|
+ #define R_ETHERC_EDMAC_TFTR_TFT_Msk (0x7ffUL) /*!< TFT (Bitfield-Mask: 0x7ff) */
|
|
|
+/* ========================================================== FDR ========================================================== */
|
|
|
+ #define R_ETHERC_EDMAC_FDR_TFD_Pos (8UL) /*!< TFD (Bit 8) */
|
|
|
+ #define R_ETHERC_EDMAC_FDR_TFD_Msk (0x1f00UL) /*!< TFD (Bitfield-Mask: 0x1f) */
|
|
|
+ #define R_ETHERC_EDMAC_FDR_RFD_Pos (0UL) /*!< RFD (Bit 0) */
|
|
|
+ #define R_ETHERC_EDMAC_FDR_RFD_Msk (0x1fUL) /*!< RFD (Bitfield-Mask: 0x1f) */
|
|
|
+/* ========================================================= RMCR ========================================================== */
|
|
|
+ #define R_ETHERC_EDMAC_RMCR_RNR_Pos (0UL) /*!< RNR (Bit 0) */
|
|
|
+ #define R_ETHERC_EDMAC_RMCR_RNR_Msk (0x1UL) /*!< RNR (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= TFUCR ========================================================= */
|
|
|
+ #define R_ETHERC_EDMAC_TFUCR_UNDER_Pos (0UL) /*!< UNDER (Bit 0) */
|
|
|
+ #define R_ETHERC_EDMAC_TFUCR_UNDER_Msk (0xffffUL) /*!< UNDER (Bitfield-Mask: 0xffff) */
|
|
|
+/* ========================================================= RFOCR ========================================================= */
|
|
|
+ #define R_ETHERC_EDMAC_RFOCR_OVER_Pos (0UL) /*!< OVER (Bit 0) */
|
|
|
+ #define R_ETHERC_EDMAC_RFOCR_OVER_Msk (0xffffUL) /*!< OVER (Bitfield-Mask: 0xffff) */
|
|
|
+/* ========================================================= IOSR ========================================================== */
|
|
|
+ #define R_ETHERC_EDMAC_IOSR_ELB_Pos (0UL) /*!< ELB (Bit 0) */
|
|
|
+ #define R_ETHERC_EDMAC_IOSR_ELB_Msk (0x1UL) /*!< ELB (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= FCFTR ========================================================= */
|
|
|
+ #define R_ETHERC_EDMAC_FCFTR_RFFO_Pos (16UL) /*!< RFFO (Bit 16) */
|
|
|
+ #define R_ETHERC_EDMAC_FCFTR_RFFO_Msk (0x70000UL) /*!< RFFO (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_ETHERC_EDMAC_FCFTR_RFDO_Pos (0UL) /*!< RFDO (Bit 0) */
|
|
|
+ #define R_ETHERC_EDMAC_FCFTR_RFDO_Msk (0x7UL) /*!< RFDO (Bitfield-Mask: 0x07) */
|
|
|
+/* ======================================================== RPADIR ========================================================= */
|
|
|
+ #define R_ETHERC_EDMAC_RPADIR_PADS_Pos (16UL) /*!< PADS (Bit 16) */
|
|
|
+ #define R_ETHERC_EDMAC_RPADIR_PADS_Msk (0x30000UL) /*!< PADS (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_ETHERC_EDMAC_RPADIR_PADR_Pos (0UL) /*!< PADR (Bit 0) */
|
|
|
+ #define R_ETHERC_EDMAC_RPADIR_PADR_Msk (0x3fUL) /*!< PADR (Bitfield-Mask: 0x3f) */
|
|
|
+/* ========================================================= TRIMD ========================================================= */
|
|
|
+ #define R_ETHERC_EDMAC_TRIMD_TIM_Pos (4UL) /*!< TIM (Bit 4) */
|
|
|
+ #define R_ETHERC_EDMAC_TRIMD_TIM_Msk (0x10UL) /*!< TIM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ETHERC_EDMAC_TRIMD_TIS_Pos (0UL) /*!< TIS (Bit 0) */
|
|
|
+ #define R_ETHERC_EDMAC_TRIMD_TIS_Msk (0x1UL) /*!< TIS (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= RBWAR ========================================================= */
|
|
|
+ #define R_ETHERC_EDMAC_RBWAR_RBWAR_Pos (0UL) /*!< RBWAR (Bit 0) */
|
|
|
+ #define R_ETHERC_EDMAC_RBWAR_RBWAR_Msk (0xffffffffUL) /*!< RBWAR (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ========================================================= RDFAR ========================================================= */
|
|
|
+ #define R_ETHERC_EDMAC_RDFAR_RDFAR_Pos (0UL) /*!< RDFAR (Bit 0) */
|
|
|
+ #define R_ETHERC_EDMAC_RDFAR_RDFAR_Msk (0xffffffffUL) /*!< RDFAR (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ========================================================= TBRAR ========================================================= */
|
|
|
+ #define R_ETHERC_EDMAC_TBRAR_TBRAR_Pos (0UL) /*!< TBRAR (Bit 0) */
|
|
|
+ #define R_ETHERC_EDMAC_TBRAR_TBRAR_Msk (0xffffffffUL) /*!< TBRAR (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ========================================================= TDFAR ========================================================= */
|
|
|
+ #define R_ETHERC_EDMAC_TDFAR_TDFAR_Pos (0UL) /*!< TDFAR (Bit 0) */
|
|
|
+ #define R_ETHERC_EDMAC_TDFAR_TDFAR_Msk (0xffffffffUL) /*!< TDFAR (Bitfield-Mask: 0xffffffff) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_FACI_HP_CMD ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ====================================================== FACI_CMD16 ======================================================= */
|
|
|
+/* ======================================================= FACI_CMD8 ======================================================= */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_FACI_HP ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ======================================================== FASTAT ========================================================= */
|
|
|
+ #define R_FACI_HP_FASTAT_CFAE_Pos (7UL) /*!< CFAE (Bit 7) */
|
|
|
+ #define R_FACI_HP_FASTAT_CFAE_Msk (0x80UL) /*!< CFAE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_FACI_HP_FASTAT_CMDLK_Pos (4UL) /*!< CMDLK (Bit 4) */
|
|
|
+ #define R_FACI_HP_FASTAT_CMDLK_Msk (0x10UL) /*!< CMDLK (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_FACI_HP_FASTAT_DFAE_Pos (3UL) /*!< DFAE (Bit 3) */
|
|
|
+ #define R_FACI_HP_FASTAT_DFAE_Msk (0x8UL) /*!< DFAE (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== FAEINT ========================================================= */
|
|
|
+ #define R_FACI_HP_FAEINT_CFAEIE_Pos (7UL) /*!< CFAEIE (Bit 7) */
|
|
|
+ #define R_FACI_HP_FAEINT_CFAEIE_Msk (0x80UL) /*!< CFAEIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_FACI_HP_FAEINT_CMDLKIE_Pos (4UL) /*!< CMDLKIE (Bit 4) */
|
|
|
+ #define R_FACI_HP_FAEINT_CMDLKIE_Msk (0x10UL) /*!< CMDLKIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_FACI_HP_FAEINT_DFAEIE_Pos (3UL) /*!< DFAEIE (Bit 3) */
|
|
|
+ #define R_FACI_HP_FAEINT_DFAEIE_Msk (0x8UL) /*!< DFAEIE (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== FRDYIE ========================================================= */
|
|
|
+ #define R_FACI_HP_FRDYIE_FRDYIE_Pos (0UL) /*!< FRDYIE (Bit 0) */
|
|
|
+ #define R_FACI_HP_FRDYIE_FRDYIE_Msk (0x1UL) /*!< FRDYIE (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== FSADDR ========================================================= */
|
|
|
+ #define R_FACI_HP_FSADDR_FSA_Pos (0UL) /*!< FSA (Bit 0) */
|
|
|
+ #define R_FACI_HP_FSADDR_FSA_Msk (0xffffffffUL) /*!< FSA (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================== FEADDR ========================================================= */
|
|
|
+ #define R_FACI_HP_FEADDR_FEA_Pos (0UL) /*!< FEA (Bit 0) */
|
|
|
+ #define R_FACI_HP_FEADDR_FEA_Msk (0xffffffffUL) /*!< FEA (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================== FMEPROT ======================================================== */
|
|
|
+ #define R_FACI_HP_FMEPROT_KEY_Pos (8UL) /*!< KEY (Bit 8) */
|
|
|
+ #define R_FACI_HP_FMEPROT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_FACI_HP_FMEPROT_CEPROT_Pos (0UL) /*!< CEPROT (Bit 0) */
|
|
|
+ #define R_FACI_HP_FMEPROT_CEPROT_Msk (0x1UL) /*!< CEPROT (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== FBPROT0 ======================================================== */
|
|
|
+ #define R_FACI_HP_FBPROT0_KEY_Pos (8UL) /*!< KEY (Bit 8) */
|
|
|
+ #define R_FACI_HP_FBPROT0_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_FACI_HP_FBPROT0_BPCN0_Pos (0UL) /*!< BPCN0 (Bit 0) */
|
|
|
+ #define R_FACI_HP_FBPROT0_BPCN0_Msk (0x1UL) /*!< BPCN0 (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== FBPROT1 ======================================================== */
|
|
|
+ #define R_FACI_HP_FBPROT1_KEY_Pos (8UL) /*!< KEY (Bit 8) */
|
|
|
+ #define R_FACI_HP_FBPROT1_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_FACI_HP_FBPROT1_BPCN1_Pos (0UL) /*!< BPCN1 (Bit 0) */
|
|
|
+ #define R_FACI_HP_FBPROT1_BPCN1_Msk (0x1UL) /*!< BPCN1 (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== FSTATR ========================================================= */
|
|
|
+ #define R_FACI_HP_FSTATR_ILGCOMERR_Pos (23UL) /*!< ILGCOMERR (Bit 23) */
|
|
|
+ #define R_FACI_HP_FSTATR_ILGCOMERR_Msk (0x800000UL) /*!< ILGCOMERR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_FACI_HP_FSTATR_FESETERR_Pos (22UL) /*!< FESETERR (Bit 22) */
|
|
|
+ #define R_FACI_HP_FSTATR_FESETERR_Msk (0x400000UL) /*!< FESETERR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_FACI_HP_FSTATR_SECERR_Pos (21UL) /*!< SECERR (Bit 21) */
|
|
|
+ #define R_FACI_HP_FSTATR_SECERR_Msk (0x200000UL) /*!< SECERR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_FACI_HP_FSTATR_OTERR_Pos (20UL) /*!< OTERR (Bit 20) */
|
|
|
+ #define R_FACI_HP_FSTATR_OTERR_Msk (0x100000UL) /*!< OTERR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_FACI_HP_FSTATR_FRDY_Pos (15UL) /*!< FRDY (Bit 15) */
|
|
|
+ #define R_FACI_HP_FSTATR_FRDY_Msk (0x8000UL) /*!< FRDY (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_FACI_HP_FSTATR_ILGLERR_Pos (14UL) /*!< ILGLERR (Bit 14) */
|
|
|
+ #define R_FACI_HP_FSTATR_ILGLERR_Msk (0x4000UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_FACI_HP_FSTATR_ERSERR_Pos (13UL) /*!< ERSERR (Bit 13) */
|
|
|
+ #define R_FACI_HP_FSTATR_ERSERR_Msk (0x2000UL) /*!< ERSERR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_FACI_HP_FSTATR_PRGERR_Pos (12UL) /*!< PRGERR (Bit 12) */
|
|
|
+ #define R_FACI_HP_FSTATR_PRGERR_Msk (0x1000UL) /*!< PRGERR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_FACI_HP_FSTATR_SUSRDY_Pos (11UL) /*!< SUSRDY (Bit 11) */
|
|
|
+ #define R_FACI_HP_FSTATR_SUSRDY_Msk (0x800UL) /*!< SUSRDY (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_FACI_HP_FSTATR_DBFULL_Pos (10UL) /*!< DBFULL (Bit 10) */
|
|
|
+ #define R_FACI_HP_FSTATR_DBFULL_Msk (0x400UL) /*!< DBFULL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_FACI_HP_FSTATR_ERSSPD_Pos (9UL) /*!< ERSSPD (Bit 9) */
|
|
|
+ #define R_FACI_HP_FSTATR_ERSSPD_Msk (0x200UL) /*!< ERSSPD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_FACI_HP_FSTATR_PRGSPD_Pos (8UL) /*!< PRGSPD (Bit 8) */
|
|
|
+ #define R_FACI_HP_FSTATR_PRGSPD_Msk (0x100UL) /*!< PRGSPD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_FACI_HP_FSTATR_FLWEERR_Pos (6UL) /*!< FLWEERR (Bit 6) */
|
|
|
+ #define R_FACI_HP_FSTATR_FLWEERR_Msk (0x40UL) /*!< FLWEERR (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== FENTRYR ======================================================== */
|
|
|
+ #define R_FACI_HP_FENTRYR_KEY_Pos (8UL) /*!< KEY (Bit 8) */
|
|
|
+ #define R_FACI_HP_FENTRYR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_FACI_HP_FENTRYR_FENTRYD_Pos (7UL) /*!< FENTRYD (Bit 7) */
|
|
|
+ #define R_FACI_HP_FENTRYR_FENTRYD_Msk (0x80UL) /*!< FENTRYD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_FACI_HP_FENTRYR_FENTRYC_Pos (0UL) /*!< FENTRYC (Bit 0) */
|
|
|
+ #define R_FACI_HP_FENTRYR_FENTRYC_Msk (0x1UL) /*!< FENTRYC (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= FSUINITR ======================================================== */
|
|
|
+ #define R_FACI_HP_FSUINITR_KEY_Pos (8UL) /*!< KEY (Bit 8) */
|
|
|
+ #define R_FACI_HP_FSUINITR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_FACI_HP_FSUINITR_SUINIT_Pos (0UL) /*!< SUINIT (Bit 0) */
|
|
|
+ #define R_FACI_HP_FSUINITR_SUINIT_Msk (0x1UL) /*!< SUINIT (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= FCMDR ========================================================= */
|
|
|
+ #define R_FACI_HP_FCMDR_CMDR_Pos (8UL) /*!< CMDR (Bit 8) */
|
|
|
+ #define R_FACI_HP_FCMDR_CMDR_Msk (0xff00UL) /*!< CMDR (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_FACI_HP_FCMDR_PCMDR_Pos (0UL) /*!< PCMDR (Bit 0) */
|
|
|
+ #define R_FACI_HP_FCMDR_PCMDR_Msk (0xffUL) /*!< PCMDR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== FBCCNT ========================================================= */
|
|
|
+ #define R_FACI_HP_FBCCNT_BCDIR_Pos (0UL) /*!< BCDIR (Bit 0) */
|
|
|
+ #define R_FACI_HP_FBCCNT_BCDIR_Msk (0x1UL) /*!< BCDIR (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== FBCSTAT ======================================================== */
|
|
|
+ #define R_FACI_HP_FBCSTAT_BCST_Pos (0UL) /*!< BCST (Bit 0) */
|
|
|
+ #define R_FACI_HP_FBCSTAT_BCST_Msk (0x1UL) /*!< BCST (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== FPSADDR ======================================================== */
|
|
|
+ #define R_FACI_HP_FPSADDR_PSADR_Pos (0UL) /*!< PSADR (Bit 0) */
|
|
|
+ #define R_FACI_HP_FPSADDR_PSADR_Msk (0x7ffffUL) /*!< PSADR (Bitfield-Mask: 0x7ffff) */
|
|
|
+/* ======================================================== FAWMON ========================================================= */
|
|
|
+ #define R_FACI_HP_FAWMON_BTFLG_Pos (31UL) /*!< BTFLG (Bit 31) */
|
|
|
+ #define R_FACI_HP_FAWMON_BTFLG_Msk (0x80000000UL) /*!< BTFLG (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_FACI_HP_FAWMON_FAWE_Pos (16UL) /*!< FAWE (Bit 16) */
|
|
|
+ #define R_FACI_HP_FAWMON_FAWE_Msk (0x7ff0000UL) /*!< FAWE (Bitfield-Mask: 0x7ff) */
|
|
|
+ #define R_FACI_HP_FAWMON_FSPR_Pos (15UL) /*!< FSPR (Bit 15) */
|
|
|
+ #define R_FACI_HP_FAWMON_FSPR_Msk (0x8000UL) /*!< FSPR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_FACI_HP_FAWMON_FAWS_Pos (0UL) /*!< FAWS (Bit 0) */
|
|
|
+ #define R_FACI_HP_FAWMON_FAWS_Msk (0x7ffUL) /*!< FAWS (Bitfield-Mask: 0x7ff) */
|
|
|
+/* ========================================================= FCPSR ========================================================= */
|
|
|
+ #define R_FACI_HP_FCPSR_ESUSPMD_Pos (0UL) /*!< ESUSPMD (Bit 0) */
|
|
|
+ #define R_FACI_HP_FCPSR_ESUSPMD_Msk (0x1UL) /*!< ESUSPMD (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== FPCKAR ========================================================= */
|
|
|
+ #define R_FACI_HP_FPCKAR_KEY_Pos (8UL) /*!< KEY (Bit 8) */
|
|
|
+ #define R_FACI_HP_FPCKAR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_FACI_HP_FPCKAR_PCKA_Pos (0UL) /*!< PCKA (Bit 0) */
|
|
|
+ #define R_FACI_HP_FPCKAR_PCKA_Msk (0xffUL) /*!< PCKA (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== FSUACR ========================================================= */
|
|
|
+ #define R_FACI_HP_FSUACR_KEY_Pos (8UL) /*!< KEY (Bit 8) */
|
|
|
+ #define R_FACI_HP_FSUACR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_FACI_HP_FSUACR_SAS_Pos (0UL) /*!< SAS (Bit 0) */
|
|
|
+ #define R_FACI_HP_FSUACR_SAS_Msk (0x3UL) /*!< SAS (Bitfield-Mask: 0x03) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_FCACHE ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ======================================================== FCACHEE ======================================================== */
|
|
|
+ #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */
|
|
|
+ #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= FCACHEIV ======================================================== */
|
|
|
+ #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */
|
|
|
+ #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= FLWT ========================================================== */
|
|
|
+ #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */
|
|
|
+ #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */
|
|
|
+/* ========================================================= FSAR ========================================================== */
|
|
|
+ #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */
|
|
|
+ #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_FCACHE_FSAR_FCACHEENSA_Pos (1UL) /*!< FCACHEENSA (Bit 1) */
|
|
|
+ #define R_FCACHE_FSAR_FCACHEENSA_Msk (0x2UL) /*!< FCACHEENSA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */
|
|
|
+ #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_FCACHE_FSAR_FACICOMISA_Pos (9UL) /*!< FACICOMISA (Bit 9) */
|
|
|
+ #define R_FCACHE_FSAR_FACICOMISA_Msk (0x200UL) /*!< FACICOMISA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_FCACHE_FSAR_FACICOMRSA_Pos (10UL) /*!< FACICOMRSA (Bit 10) */
|
|
|
+ #define R_FCACHE_FSAR_FACICOMRSA_Msk (0x400UL) /*!< FACICOMRSA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_FCACHE_FSAR_FACITRSA_Pos (11UL) /*!< FACITRSA (Bit 11) */
|
|
|
+ #define R_FCACHE_FSAR_FACITRSA_Msk (0x800UL) /*!< FACITRSA (Bitfield-Mask: 0x01) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_GPT0 ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================= GTWP ========================================================== */
|
|
|
+ #define R_GPT0_GTWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */
|
|
|
+ #define R_GPT0_GTWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_GPT0_GTWP_WP_Pos (0UL) /*!< WP (Bit 0) */
|
|
|
+ #define R_GPT0_GTWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTWP_STRWP_Pos (1UL) /*!< STRWP (Bit 1) */
|
|
|
+ #define R_GPT0_GTWP_STRWP_Msk (0x2UL) /*!< STRWP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTWP_STPWP_Pos (2UL) /*!< STPWP (Bit 2) */
|
|
|
+ #define R_GPT0_GTWP_STPWP_Msk (0x4UL) /*!< STPWP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTWP_CLRWP_Pos (3UL) /*!< CLRWP (Bit 3) */
|
|
|
+ #define R_GPT0_GTWP_CLRWP_Msk (0x8UL) /*!< CLRWP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTWP_CMNWP_Pos (4UL) /*!< CMNWP (Bit 4) */
|
|
|
+ #define R_GPT0_GTWP_CMNWP_Msk (0x10UL) /*!< CMNWP (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= GTSTR ========================================================= */
|
|
|
+ #define R_GPT0_GTSTR_CSTRT_Pos (0UL) /*!< CSTRT (Bit 0) */
|
|
|
+ #define R_GPT0_GTSTR_CSTRT_Msk (0x1UL) /*!< CSTRT (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= GTSTP ========================================================= */
|
|
|
+ #define R_GPT0_GTSTP_CSTOP_Pos (0UL) /*!< CSTOP (Bit 0) */
|
|
|
+ #define R_GPT0_GTSTP_CSTOP_Msk (0x1UL) /*!< CSTOP (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= GTCLR ========================================================= */
|
|
|
+ #define R_GPT0_GTCLR_CCLR_Pos (0UL) /*!< CCLR (Bit 0) */
|
|
|
+ #define R_GPT0_GTCLR_CCLR_Msk (0x1UL) /*!< CCLR (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= GTSSR ========================================================= */
|
|
|
+ #define R_GPT0_GTSSR_CSTRT_Pos (31UL) /*!< CSTRT (Bit 31) */
|
|
|
+ #define R_GPT0_GTSSR_CSTRT_Msk (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTSSR_SSELC_Pos (16UL) /*!< SSELC (Bit 16) */
|
|
|
+ #define R_GPT0_GTSSR_SSELC_Msk (0x10000UL) /*!< SSELC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTSSR_SSCBFAH_Pos (15UL) /*!< SSCBFAH (Bit 15) */
|
|
|
+ #define R_GPT0_GTSSR_SSCBFAH_Msk (0x8000UL) /*!< SSCBFAH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTSSR_SSCBFAL_Pos (14UL) /*!< SSCBFAL (Bit 14) */
|
|
|
+ #define R_GPT0_GTSSR_SSCBFAL_Msk (0x4000UL) /*!< SSCBFAL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTSSR_SSCBRAH_Pos (13UL) /*!< SSCBRAH (Bit 13) */
|
|
|
+ #define R_GPT0_GTSSR_SSCBRAH_Msk (0x2000UL) /*!< SSCBRAH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTSSR_SSCBRAL_Pos (12UL) /*!< SSCBRAL (Bit 12) */
|
|
|
+ #define R_GPT0_GTSSR_SSCBRAL_Msk (0x1000UL) /*!< SSCBRAL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTSSR_SSCAFBH_Pos (11UL) /*!< SSCAFBH (Bit 11) */
|
|
|
+ #define R_GPT0_GTSSR_SSCAFBH_Msk (0x800UL) /*!< SSCAFBH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTSSR_SSCAFBL_Pos (10UL) /*!< SSCAFBL (Bit 10) */
|
|
|
+ #define R_GPT0_GTSSR_SSCAFBL_Msk (0x400UL) /*!< SSCAFBL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTSSR_SSCARBH_Pos (9UL) /*!< SSCARBH (Bit 9) */
|
|
|
+ #define R_GPT0_GTSSR_SSCARBH_Msk (0x200UL) /*!< SSCARBH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTSSR_SSCARBL_Pos (8UL) /*!< SSCARBL (Bit 8) */
|
|
|
+ #define R_GPT0_GTSSR_SSCARBL_Msk (0x100UL) /*!< SSCARBL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTSSR_SSGTRGF_Pos (1UL) /*!< SSGTRGF (Bit 1) */
|
|
|
+ #define R_GPT0_GTSSR_SSGTRGF_Msk (0x2UL) /*!< SSGTRGF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTSSR_SSGTRGR_Pos (0UL) /*!< SSGTRGR (Bit 0) */
|
|
|
+ #define R_GPT0_GTSSR_SSGTRGR_Msk (0x1UL) /*!< SSGTRGR (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= GTPSR ========================================================= */
|
|
|
+ #define R_GPT0_GTPSR_CSTOP_Pos (31UL) /*!< CSTOP (Bit 31) */
|
|
|
+ #define R_GPT0_GTPSR_CSTOP_Msk (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTPSR_PSELC_Pos (16UL) /*!< PSELC (Bit 16) */
|
|
|
+ #define R_GPT0_GTPSR_PSELC_Msk (0x10000UL) /*!< PSELC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTPSR_PSCBFAH_Pos (15UL) /*!< PSCBFAH (Bit 15) */
|
|
|
+ #define R_GPT0_GTPSR_PSCBFAH_Msk (0x8000UL) /*!< PSCBFAH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTPSR_PSCBFAL_Pos (14UL) /*!< PSCBFAL (Bit 14) */
|
|
|
+ #define R_GPT0_GTPSR_PSCBFAL_Msk (0x4000UL) /*!< PSCBFAL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTPSR_PSCBRAH_Pos (13UL) /*!< PSCBRAH (Bit 13) */
|
|
|
+ #define R_GPT0_GTPSR_PSCBRAH_Msk (0x2000UL) /*!< PSCBRAH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTPSR_PSCBRAL_Pos (12UL) /*!< PSCBRAL (Bit 12) */
|
|
|
+ #define R_GPT0_GTPSR_PSCBRAL_Msk (0x1000UL) /*!< PSCBRAL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTPSR_PSCAFBH_Pos (11UL) /*!< PSCAFBH (Bit 11) */
|
|
|
+ #define R_GPT0_GTPSR_PSCAFBH_Msk (0x800UL) /*!< PSCAFBH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTPSR_PSCAFBL_Pos (10UL) /*!< PSCAFBL (Bit 10) */
|
|
|
+ #define R_GPT0_GTPSR_PSCAFBL_Msk (0x400UL) /*!< PSCAFBL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTPSR_PSCARBH_Pos (9UL) /*!< PSCARBH (Bit 9) */
|
|
|
+ #define R_GPT0_GTPSR_PSCARBH_Msk (0x200UL) /*!< PSCARBH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTPSR_PSCARBL_Pos (8UL) /*!< PSCARBL (Bit 8) */
|
|
|
+ #define R_GPT0_GTPSR_PSCARBL_Msk (0x100UL) /*!< PSCARBL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTPSR_PSGTRGF_Pos (1UL) /*!< PSGTRGF (Bit 1) */
|
|
|
+ #define R_GPT0_GTPSR_PSGTRGF_Msk (0x2UL) /*!< PSGTRGF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTPSR_PSGTRGR_Pos (0UL) /*!< PSGTRGR (Bit 0) */
|
|
|
+ #define R_GPT0_GTPSR_PSGTRGR_Msk (0x1UL) /*!< PSGTRGR (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= GTCSR ========================================================= */
|
|
|
+ #define R_GPT0_GTCSR_CCLR_Pos (31UL) /*!< CCLR (Bit 31) */
|
|
|
+ #define R_GPT0_GTCSR_CCLR_Msk (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTCSR_CP1CCE_Pos (27UL) /*!< CP1CCE (Bit 27) */
|
|
|
+ #define R_GPT0_GTCSR_CP1CCE_Msk (0x8000000UL) /*!< CP1CCE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTCSR_CSCMSC_Pos (24UL) /*!< CSCMSC (Bit 24) */
|
|
|
+ #define R_GPT0_GTCSR_CSCMSC_Msk (0x7000000UL) /*!< CSCMSC (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_GPT0_GTCSR_CSELC_Pos (16UL) /*!< CSELC (Bit 16) */
|
|
|
+ #define R_GPT0_GTCSR_CSELC_Msk (0x10000UL) /*!< CSELC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTCSR_CSCBFAH_Pos (15UL) /*!< CSCBFAH (Bit 15) */
|
|
|
+ #define R_GPT0_GTCSR_CSCBFAH_Msk (0x8000UL) /*!< CSCBFAH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTCSR_CSCBFAL_Pos (14UL) /*!< CSCBFAL (Bit 14) */
|
|
|
+ #define R_GPT0_GTCSR_CSCBFAL_Msk (0x4000UL) /*!< CSCBFAL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTCSR_CSCBRAH_Pos (13UL) /*!< CSCBRAH (Bit 13) */
|
|
|
+ #define R_GPT0_GTCSR_CSCBRAH_Msk (0x2000UL) /*!< CSCBRAH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTCSR_CSCBRAL_Pos (12UL) /*!< CSCBRAL (Bit 12) */
|
|
|
+ #define R_GPT0_GTCSR_CSCBRAL_Msk (0x1000UL) /*!< CSCBRAL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTCSR_CSCAFBH_Pos (11UL) /*!< CSCAFBH (Bit 11) */
|
|
|
+ #define R_GPT0_GTCSR_CSCAFBH_Msk (0x800UL) /*!< CSCAFBH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTCSR_CSCAFBL_Pos (10UL) /*!< CSCAFBL (Bit 10) */
|
|
|
+ #define R_GPT0_GTCSR_CSCAFBL_Msk (0x400UL) /*!< CSCAFBL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTCSR_CSCARBH_Pos (9UL) /*!< CSCARBH (Bit 9) */
|
|
|
+ #define R_GPT0_GTCSR_CSCARBH_Msk (0x200UL) /*!< CSCARBH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTCSR_CSCARBL_Pos (8UL) /*!< CSCARBL (Bit 8) */
|
|
|
+ #define R_GPT0_GTCSR_CSCARBL_Msk (0x100UL) /*!< CSCARBL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTCSR_CSGTRGF_Pos (1UL) /*!< CSGTRGF (Bit 1) */
|
|
|
+ #define R_GPT0_GTCSR_CSGTRGF_Msk (0x2UL) /*!< CSGTRGF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTCSR_CSGTRGR_Pos (0UL) /*!< CSGTRGR (Bit 0) */
|
|
|
+ #define R_GPT0_GTCSR_CSGTRGR_Msk (0x1UL) /*!< CSGTRGR (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== GTUPSR ========================================================= */
|
|
|
+ #define R_GPT0_GTUPSR_USILVL_Pos (24UL) /*!< USILVL (Bit 24) */
|
|
|
+ #define R_GPT0_GTUPSR_USILVL_Msk (0xf000000UL) /*!< USILVL (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_GPT0_GTUPSR_USELC_Pos (16UL) /*!< USELC (Bit 16) */
|
|
|
+ #define R_GPT0_GTUPSR_USELC_Msk (0x10000UL) /*!< USELC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTUPSR_USCBFAH_Pos (15UL) /*!< USCBFAH (Bit 15) */
|
|
|
+ #define R_GPT0_GTUPSR_USCBFAH_Msk (0x8000UL) /*!< USCBFAH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTUPSR_USCBFAL_Pos (14UL) /*!< USCBFAL (Bit 14) */
|
|
|
+ #define R_GPT0_GTUPSR_USCBFAL_Msk (0x4000UL) /*!< USCBFAL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTUPSR_USCBRAH_Pos (13UL) /*!< USCBRAH (Bit 13) */
|
|
|
+ #define R_GPT0_GTUPSR_USCBRAH_Msk (0x2000UL) /*!< USCBRAH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTUPSR_USCBRAL_Pos (12UL) /*!< USCBRAL (Bit 12) */
|
|
|
+ #define R_GPT0_GTUPSR_USCBRAL_Msk (0x1000UL) /*!< USCBRAL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTUPSR_USCAFBH_Pos (11UL) /*!< USCAFBH (Bit 11) */
|
|
|
+ #define R_GPT0_GTUPSR_USCAFBH_Msk (0x800UL) /*!< USCAFBH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTUPSR_USCAFBL_Pos (10UL) /*!< USCAFBL (Bit 10) */
|
|
|
+ #define R_GPT0_GTUPSR_USCAFBL_Msk (0x400UL) /*!< USCAFBL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTUPSR_USCARBH_Pos (9UL) /*!< USCARBH (Bit 9) */
|
|
|
+ #define R_GPT0_GTUPSR_USCARBH_Msk (0x200UL) /*!< USCARBH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTUPSR_USCARBL_Pos (8UL) /*!< USCARBL (Bit 8) */
|
|
|
+ #define R_GPT0_GTUPSR_USCARBL_Msk (0x100UL) /*!< USCARBL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTUPSR_USGTRGF_Pos (1UL) /*!< USGTRGF (Bit 1) */
|
|
|
+ #define R_GPT0_GTUPSR_USGTRGF_Msk (0x2UL) /*!< USGTRGF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTUPSR_USGTRGR_Pos (0UL) /*!< USGTRGR (Bit 0) */
|
|
|
+ #define R_GPT0_GTUPSR_USGTRGR_Msk (0x1UL) /*!< USGTRGR (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== GTDNSR ========================================================= */
|
|
|
+ #define R_GPT0_GTDNSR_DSILVL_Pos (24UL) /*!< DSILVL (Bit 24) */
|
|
|
+ #define R_GPT0_GTDNSR_DSILVL_Msk (0xf000000UL) /*!< DSILVL (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_GPT0_GTDNSR_DSELC_Pos (16UL) /*!< DSELC (Bit 16) */
|
|
|
+ #define R_GPT0_GTDNSR_DSELC_Msk (0x10000UL) /*!< DSELC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTDNSR_DSCBFAH_Pos (15UL) /*!< DSCBFAH (Bit 15) */
|
|
|
+ #define R_GPT0_GTDNSR_DSCBFAH_Msk (0x8000UL) /*!< DSCBFAH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTDNSR_DSCBFAL_Pos (14UL) /*!< DSCBFAL (Bit 14) */
|
|
|
+ #define R_GPT0_GTDNSR_DSCBFAL_Msk (0x4000UL) /*!< DSCBFAL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTDNSR_DSCBRAH_Pos (13UL) /*!< DSCBRAH (Bit 13) */
|
|
|
+ #define R_GPT0_GTDNSR_DSCBRAH_Msk (0x2000UL) /*!< DSCBRAH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTDNSR_DSCBRAL_Pos (12UL) /*!< DSCBRAL (Bit 12) */
|
|
|
+ #define R_GPT0_GTDNSR_DSCBRAL_Msk (0x1000UL) /*!< DSCBRAL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTDNSR_DSCAFBH_Pos (11UL) /*!< DSCAFBH (Bit 11) */
|
|
|
+ #define R_GPT0_GTDNSR_DSCAFBH_Msk (0x800UL) /*!< DSCAFBH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTDNSR_DSCAFBL_Pos (10UL) /*!< DSCAFBL (Bit 10) */
|
|
|
+ #define R_GPT0_GTDNSR_DSCAFBL_Msk (0x400UL) /*!< DSCAFBL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTDNSR_DSCARBH_Pos (9UL) /*!< DSCARBH (Bit 9) */
|
|
|
+ #define R_GPT0_GTDNSR_DSCARBH_Msk (0x200UL) /*!< DSCARBH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTDNSR_DSCARBL_Pos (8UL) /*!< DSCARBL (Bit 8) */
|
|
|
+ #define R_GPT0_GTDNSR_DSCARBL_Msk (0x100UL) /*!< DSCARBL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTDNSR_DSGTRGF_Pos (1UL) /*!< DSGTRGF (Bit 1) */
|
|
|
+ #define R_GPT0_GTDNSR_DSGTRGF_Msk (0x2UL) /*!< DSGTRGF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */
|
|
|
+ #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== GTICASR ======================================================== */
|
|
|
+ #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */
|
|
|
+ #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */
|
|
|
+ #define R_GPT0_GTICASR_ASCBFAH_Msk (0x8000UL) /*!< ASCBFAH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTICASR_ASCBFAL_Pos (14UL) /*!< ASCBFAL (Bit 14) */
|
|
|
+ #define R_GPT0_GTICASR_ASCBFAL_Msk (0x4000UL) /*!< ASCBFAL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTICASR_ASCBRAH_Pos (13UL) /*!< ASCBRAH (Bit 13) */
|
|
|
+ #define R_GPT0_GTICASR_ASCBRAH_Msk (0x2000UL) /*!< ASCBRAH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTICASR_ASCBRAL_Pos (12UL) /*!< ASCBRAL (Bit 12) */
|
|
|
+ #define R_GPT0_GTICASR_ASCBRAL_Msk (0x1000UL) /*!< ASCBRAL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTICASR_ASCAFBH_Pos (11UL) /*!< ASCAFBH (Bit 11) */
|
|
|
+ #define R_GPT0_GTICASR_ASCAFBH_Msk (0x800UL) /*!< ASCAFBH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTICASR_ASCAFBL_Pos (10UL) /*!< ASCAFBL (Bit 10) */
|
|
|
+ #define R_GPT0_GTICASR_ASCAFBL_Msk (0x400UL) /*!< ASCAFBL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTICASR_ASCARBH_Pos (9UL) /*!< ASCARBH (Bit 9) */
|
|
|
+ #define R_GPT0_GTICASR_ASCARBH_Msk (0x200UL) /*!< ASCARBH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTICASR_ASCARBL_Pos (8UL) /*!< ASCARBL (Bit 8) */
|
|
|
+ #define R_GPT0_GTICASR_ASCARBL_Msk (0x100UL) /*!< ASCARBL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTICASR_ASGTRGF_Pos (1UL) /*!< ASGTRGF (Bit 1) */
|
|
|
+ #define R_GPT0_GTICASR_ASGTRGF_Msk (0x2UL) /*!< ASGTRGF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */
|
|
|
+ #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== GTICBSR ======================================================== */
|
|
|
+ #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */
|
|
|
+ #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */
|
|
|
+ #define R_GPT0_GTICBSR_BSCBFAH_Msk (0x8000UL) /*!< BSCBFAH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTICBSR_BSCBFAL_Pos (14UL) /*!< BSCBFAL (Bit 14) */
|
|
|
+ #define R_GPT0_GTICBSR_BSCBFAL_Msk (0x4000UL) /*!< BSCBFAL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTICBSR_BSCBRAH_Pos (13UL) /*!< BSCBRAH (Bit 13) */
|
|
|
+ #define R_GPT0_GTICBSR_BSCBRAH_Msk (0x2000UL) /*!< BSCBRAH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTICBSR_BSCBRAL_Pos (12UL) /*!< BSCBRAL (Bit 12) */
|
|
|
+ #define R_GPT0_GTICBSR_BSCBRAL_Msk (0x1000UL) /*!< BSCBRAL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTICBSR_BSCAFBH_Pos (11UL) /*!< BSCAFBH (Bit 11) */
|
|
|
+ #define R_GPT0_GTICBSR_BSCAFBH_Msk (0x800UL) /*!< BSCAFBH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTICBSR_BSCAFBL_Pos (10UL) /*!< BSCAFBL (Bit 10) */
|
|
|
+ #define R_GPT0_GTICBSR_BSCAFBL_Msk (0x400UL) /*!< BSCAFBL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTICBSR_BSCARBH_Pos (9UL) /*!< BSCARBH (Bit 9) */
|
|
|
+ #define R_GPT0_GTICBSR_BSCARBH_Msk (0x200UL) /*!< BSCARBH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTICBSR_BSCARBL_Pos (8UL) /*!< BSCARBL (Bit 8) */
|
|
|
+ #define R_GPT0_GTICBSR_BSCARBL_Msk (0x100UL) /*!< BSCARBL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTICBSR_BSGTRGF_Pos (1UL) /*!< BSGTRGF (Bit 1) */
|
|
|
+ #define R_GPT0_GTICBSR_BSGTRGF_Msk (0x2UL) /*!< BSGTRGF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTICBSR_BSGTRGR_Pos (0UL) /*!< BSGTRGR (Bit 0) */
|
|
|
+ #define R_GPT0_GTICBSR_BSGTRGR_Msk (0x1UL) /*!< BSGTRGR (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= GTCR ========================================================== */
|
|
|
+ #define R_GPT0_GTCR_CKEG_Pos (27UL) /*!< CKEG (Bit 27) */
|
|
|
+ #define R_GPT0_GTCR_CKEG_Msk (0x18000000UL) /*!< CKEG (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_GPT0_GTCR_TPCS_Pos (23UL) /*!< TPCS (Bit 23) */
|
|
|
+ #define R_GPT0_GTCR_TPCS_Msk (0x7800000UL) /*!< TPCS (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_GPT0_GTCR_MD_Pos (16UL) /*!< MD (Bit 16) */
|
|
|
+ #define R_GPT0_GTCR_MD_Msk (0xf0000UL) /*!< MD (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_GPT0_GTCR_SSCEN_Pos (15UL) /*!< SSCEN (Bit 15) */
|
|
|
+ #define R_GPT0_GTCR_SSCEN_Msk (0x8000UL) /*!< SSCEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTCR_CPSCD_Pos (12UL) /*!< CPSCD (Bit 12) */
|
|
|
+ #define R_GPT0_GTCR_CPSCD_Msk (0x1000UL) /*!< CPSCD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTCR_SSCGRP_Pos (10UL) /*!< SSCGRP (Bit 10) */
|
|
|
+ #define R_GPT0_GTCR_SSCGRP_Msk (0xc00UL) /*!< SSCGRP (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_GPT0_GTCR_SCGTIOC_Pos (9UL) /*!< SCGTIOC (Bit 9) */
|
|
|
+ #define R_GPT0_GTCR_SCGTIOC_Msk (0x200UL) /*!< SCGTIOC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */
|
|
|
+ #define R_GPT0_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */
|
|
|
+ #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= GTUDDTYC ======================================================== */
|
|
|
+ #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */
|
|
|
+ #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */
|
|
|
+ #define R_GPT0_GTUDDTYC_OBDTYF_Msk (0x4000000UL) /*!< OBDTYF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTUDDTYC_OBDTY_Pos (24UL) /*!< OBDTY (Bit 24) */
|
|
|
+ #define R_GPT0_GTUDDTYC_OBDTY_Msk (0x3000000UL) /*!< OBDTY (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_GPT0_GTUDDTYC_OADTYR_Pos (19UL) /*!< OADTYR (Bit 19) */
|
|
|
+ #define R_GPT0_GTUDDTYC_OADTYR_Msk (0x80000UL) /*!< OADTYR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTUDDTYC_OADTYF_Pos (18UL) /*!< OADTYF (Bit 18) */
|
|
|
+ #define R_GPT0_GTUDDTYC_OADTYF_Msk (0x40000UL) /*!< OADTYF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTUDDTYC_OADTY_Pos (16UL) /*!< OADTY (Bit 16) */
|
|
|
+ #define R_GPT0_GTUDDTYC_OADTY_Msk (0x30000UL) /*!< OADTY (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_GPT0_GTUDDTYC_UDF_Pos (1UL) /*!< UDF (Bit 1) */
|
|
|
+ #define R_GPT0_GTUDDTYC_UDF_Msk (0x2UL) /*!< UDF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTUDDTYC_UD_Pos (0UL) /*!< UD (Bit 0) */
|
|
|
+ #define R_GPT0_GTUDDTYC_UD_Msk (0x1UL) /*!< UD (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= GTIOR ========================================================= */
|
|
|
+ #define R_GPT0_GTIOR_NFCSB_Pos (30UL) /*!< NFCSB (Bit 30) */
|
|
|
+ #define R_GPT0_GTIOR_NFCSB_Msk (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_GPT0_GTIOR_NFBEN_Pos (29UL) /*!< NFBEN (Bit 29) */
|
|
|
+ #define R_GPT0_GTIOR_NFBEN_Msk (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTIOR_OBEOCD_Pos (27UL) /*!< OBEOCD (Bit 27) */
|
|
|
+ #define R_GPT0_GTIOR_OBEOCD_Msk (0x8000000UL) /*!< OBEOCD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTIOR_OBDF_Pos (25UL) /*!< OBDF (Bit 25) */
|
|
|
+ #define R_GPT0_GTIOR_OBDF_Msk (0x6000000UL) /*!< OBDF (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_GPT0_GTIOR_OBE_Pos (24UL) /*!< OBE (Bit 24) */
|
|
|
+ #define R_GPT0_GTIOR_OBE_Msk (0x1000000UL) /*!< OBE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTIOR_OBHLD_Pos (23UL) /*!< OBHLD (Bit 23) */
|
|
|
+ #define R_GPT0_GTIOR_OBHLD_Msk (0x800000UL) /*!< OBHLD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTIOR_OBDFLT_Pos (22UL) /*!< OBDFLT (Bit 22) */
|
|
|
+ #define R_GPT0_GTIOR_OBDFLT_Msk (0x400000UL) /*!< OBDFLT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTIOR_GTIOB_Pos (16UL) /*!< GTIOB (Bit 16) */
|
|
|
+ #define R_GPT0_GTIOR_GTIOB_Msk (0x1f0000UL) /*!< GTIOB (Bitfield-Mask: 0x1f) */
|
|
|
+ #define R_GPT0_GTIOR_NFCSA_Pos (14UL) /*!< NFCSA (Bit 14) */
|
|
|
+ #define R_GPT0_GTIOR_NFCSA_Msk (0xc000UL) /*!< NFCSA (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_GPT0_GTIOR_NFAEN_Pos (13UL) /*!< NFAEN (Bit 13) */
|
|
|
+ #define R_GPT0_GTIOR_NFAEN_Msk (0x2000UL) /*!< NFAEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTIOR_PSYE_Pos (12UL) /*!< PSYE (Bit 12) */
|
|
|
+ #define R_GPT0_GTIOR_PSYE_Msk (0x1000UL) /*!< PSYE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTIOR_OAEOCD_Pos (11UL) /*!< OAEOCD (Bit 11) */
|
|
|
+ #define R_GPT0_GTIOR_OAEOCD_Msk (0x800UL) /*!< OAEOCD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTIOR_OADF_Pos (9UL) /*!< OADF (Bit 9) */
|
|
|
+ #define R_GPT0_GTIOR_OADF_Msk (0x600UL) /*!< OADF (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_GPT0_GTIOR_OAE_Pos (8UL) /*!< OAE (Bit 8) */
|
|
|
+ #define R_GPT0_GTIOR_OAE_Msk (0x100UL) /*!< OAE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTIOR_OAHLD_Pos (7UL) /*!< OAHLD (Bit 7) */
|
|
|
+ #define R_GPT0_GTIOR_OAHLD_Msk (0x80UL) /*!< OAHLD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTIOR_OADFLT_Pos (6UL) /*!< OADFLT (Bit 6) */
|
|
|
+ #define R_GPT0_GTIOR_OADFLT_Msk (0x40UL) /*!< OADFLT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTIOR_CPSCIR_Pos (5UL) /*!< CPSCIR (Bit 5) */
|
|
|
+ #define R_GPT0_GTIOR_CPSCIR_Msk (0x20UL) /*!< CPSCIR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTIOR_GTIOA_Pos (0UL) /*!< GTIOA (Bit 0) */
|
|
|
+ #define R_GPT0_GTIOR_GTIOA_Msk (0x1fUL) /*!< GTIOA (Bitfield-Mask: 0x1f) */
|
|
|
+/* ======================================================== GTINTAD ======================================================== */
|
|
|
+ #define R_GPT0_GTINTAD_GTINTPC_Pos (31UL) /*!< GTINTPC (Bit 31) */
|
|
|
+ #define R_GPT0_GTINTAD_GTINTPC_Msk (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTINTAD_GRPABL_Pos (30UL) /*!< GRPABL (Bit 30) */
|
|
|
+ #define R_GPT0_GTINTAD_GRPABL_Msk (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTINTAD_GRPABH_Pos (29UL) /*!< GRPABH (Bit 29) */
|
|
|
+ #define R_GPT0_GTINTAD_GRPABH_Msk (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTINTAD_GRPDTE_Pos (28UL) /*!< GRPDTE (Bit 28) */
|
|
|
+ #define R_GPT0_GTINTAD_GRPDTE_Msk (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTINTAD_GRP_Pos (24UL) /*!< GRP (Bit 24) */
|
|
|
+ #define R_GPT0_GTINTAD_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_GPT0_GTINTAD_ADTRDEN_Pos (17UL) /*!< ADTRDEN (Bit 17) */
|
|
|
+ #define R_GPT0_GTINTAD_ADTRDEN_Msk (0x20000UL) /*!< ADTRDEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTINTAD_ADTRUEN_Pos (16UL) /*!< ADTRUEN (Bit 16) */
|
|
|
+ #define R_GPT0_GTINTAD_ADTRUEN_Msk (0x10000UL) /*!< ADTRUEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTINTAD_SCFPU_Pos (15UL) /*!< SCFPU (Bit 15) */
|
|
|
+ #define R_GPT0_GTINTAD_SCFPU_Msk (0x8000UL) /*!< SCFPU (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTINTAD_SCFPO_Pos (14UL) /*!< SCFPO (Bit 14) */
|
|
|
+ #define R_GPT0_GTINTAD_SCFPO_Msk (0x4000UL) /*!< SCFPO (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTINTAD_SCF_Pos (8UL) /*!< SCF (Bit 8) */
|
|
|
+ #define R_GPT0_GTINTAD_SCF_Msk (0x100UL) /*!< SCF (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= GTST ========================================================== */
|
|
|
+ #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */
|
|
|
+ #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */
|
|
|
+ #define R_GPT0_GTST_OABHF_Msk (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTST_DTEF_Pos (28UL) /*!< DTEF (Bit 28) */
|
|
|
+ #define R_GPT0_GTST_DTEF_Msk (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTST_ODF_Pos (24UL) /*!< ODF (Bit 24) */
|
|
|
+ #define R_GPT0_GTST_ODF_Msk (0x1000000UL) /*!< ODF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTST_ADTRBDF_Pos (19UL) /*!< ADTRBDF (Bit 19) */
|
|
|
+ #define R_GPT0_GTST_ADTRBDF_Msk (0x80000UL) /*!< ADTRBDF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTST_ADTRBUF_Pos (18UL) /*!< ADTRBUF (Bit 18) */
|
|
|
+ #define R_GPT0_GTST_ADTRBUF_Msk (0x40000UL) /*!< ADTRBUF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTST_ADTRADF_Pos (17UL) /*!< ADTRADF (Bit 17) */
|
|
|
+ #define R_GPT0_GTST_ADTRADF_Msk (0x20000UL) /*!< ADTRADF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTST_ADTRAUF_Pos (16UL) /*!< ADTRAUF (Bit 16) */
|
|
|
+ #define R_GPT0_GTST_ADTRAUF_Msk (0x10000UL) /*!< ADTRAUF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTST_TUCF_Pos (15UL) /*!< TUCF (Bit 15) */
|
|
|
+ #define R_GPT0_GTST_TUCF_Msk (0x8000UL) /*!< TUCF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTST_ITCNT_Pos (8UL) /*!< ITCNT (Bit 8) */
|
|
|
+ #define R_GPT0_GTST_ITCNT_Msk (0x700UL) /*!< ITCNT (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_GPT0_GTST_TCFPU_Pos (7UL) /*!< TCFPU (Bit 7) */
|
|
|
+ #define R_GPT0_GTST_TCFPU_Msk (0x80UL) /*!< TCFPU (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTST_TCFPO_Pos (6UL) /*!< TCFPO (Bit 6) */
|
|
|
+ #define R_GPT0_GTST_TCFPO_Msk (0x40UL) /*!< TCFPO (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTST_TCFF_Pos (5UL) /*!< TCFF (Bit 5) */
|
|
|
+ #define R_GPT0_GTST_TCFF_Msk (0x20UL) /*!< TCFF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTST_TCFE_Pos (4UL) /*!< TCFE (Bit 4) */
|
|
|
+ #define R_GPT0_GTST_TCFE_Msk (0x10UL) /*!< TCFE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTST_TCFD_Pos (3UL) /*!< TCFD (Bit 3) */
|
|
|
+ #define R_GPT0_GTST_TCFD_Msk (0x8UL) /*!< TCFD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTST_TCFC_Pos (2UL) /*!< TCFC (Bit 2) */
|
|
|
+ #define R_GPT0_GTST_TCFC_Msk (0x4UL) /*!< TCFC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTST_TCFB_Pos (1UL) /*!< TCFB (Bit 1) */
|
|
|
+ #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */
|
|
|
+ #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */
|
|
|
+ #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= GTBER ========================================================= */
|
|
|
+ #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */
|
|
|
+ #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTBER_ADTTB_Pos (28UL) /*!< ADTTB (Bit 28) */
|
|
|
+ #define R_GPT0_GTBER_ADTTB_Msk (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_GPT0_GTBER_ADTDA_Pos (26UL) /*!< ADTDA (Bit 26) */
|
|
|
+ #define R_GPT0_GTBER_ADTDA_Msk (0x4000000UL) /*!< ADTDA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTBER_ADTTA_Pos (24UL) /*!< ADTTA (Bit 24) */
|
|
|
+ #define R_GPT0_GTBER_ADTTA_Msk (0x3000000UL) /*!< ADTTA (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_GPT0_GTBER_CCRSWT_Pos (22UL) /*!< CCRSWT (Bit 22) */
|
|
|
+ #define R_GPT0_GTBER_CCRSWT_Msk (0x400000UL) /*!< CCRSWT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTBER_PR_Pos (20UL) /*!< PR (Bit 20) */
|
|
|
+ #define R_GPT0_GTBER_PR_Msk (0x300000UL) /*!< PR (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_GPT0_GTBER_CCRB_Pos (18UL) /*!< CCRB (Bit 18) */
|
|
|
+ #define R_GPT0_GTBER_CCRB_Msk (0xc0000UL) /*!< CCRB (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_GPT0_GTBER_CCRA_Pos (16UL) /*!< CCRA (Bit 16) */
|
|
|
+ #define R_GPT0_GTBER_CCRA_Msk (0x30000UL) /*!< CCRA (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_GPT0_GTBER_DBRTEC_Pos (8UL) /*!< DBRTEC (Bit 8) */
|
|
|
+ #define R_GPT0_GTBER_DBRTEC_Msk (0x100UL) /*!< DBRTEC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTBER_BD3_Pos (3UL) /*!< BD3 (Bit 3) */
|
|
|
+ #define R_GPT0_GTBER_BD3_Msk (0x8UL) /*!< BD3 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTBER_BD2_Pos (2UL) /*!< BD2 (Bit 2) */
|
|
|
+ #define R_GPT0_GTBER_BD2_Msk (0x4UL) /*!< BD2 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTBER_BD1_Pos (1UL) /*!< BD1 (Bit 1) */
|
|
|
+ #define R_GPT0_GTBER_BD1_Msk (0x2UL) /*!< BD1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTBER_BD0_Pos (0UL) /*!< BD0 (Bit 0) */
|
|
|
+ #define R_GPT0_GTBER_BD0_Msk (0x1UL) /*!< BD0 (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= GTITC ========================================================= */
|
|
|
+ #define R_GPT0_GTITC_ADTBL_Pos (14UL) /*!< ADTBL (Bit 14) */
|
|
|
+ #define R_GPT0_GTITC_ADTBL_Msk (0x4000UL) /*!< ADTBL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTITC_ADTAL_Pos (12UL) /*!< ADTAL (Bit 12) */
|
|
|
+ #define R_GPT0_GTITC_ADTAL_Msk (0x1000UL) /*!< ADTAL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTITC_IVTT_Pos (8UL) /*!< IVTT (Bit 8) */
|
|
|
+ #define R_GPT0_GTITC_IVTT_Msk (0x700UL) /*!< IVTT (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_GPT0_GTITC_IVTC_Pos (6UL) /*!< IVTC (Bit 6) */
|
|
|
+ #define R_GPT0_GTITC_IVTC_Msk (0xc0UL) /*!< IVTC (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_GPT0_GTITC_ITLF_Pos (5UL) /*!< ITLF (Bit 5) */
|
|
|
+ #define R_GPT0_GTITC_ITLF_Msk (0x20UL) /*!< ITLF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTITC_ITLE_Pos (4UL) /*!< ITLE (Bit 4) */
|
|
|
+ #define R_GPT0_GTITC_ITLE_Msk (0x10UL) /*!< ITLE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTITC_ITLD_Pos (3UL) /*!< ITLD (Bit 3) */
|
|
|
+ #define R_GPT0_GTITC_ITLD_Msk (0x8UL) /*!< ITLD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTITC_ITLC_Pos (2UL) /*!< ITLC (Bit 2) */
|
|
|
+ #define R_GPT0_GTITC_ITLC_Msk (0x4UL) /*!< ITLC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTITC_ITLB_Pos (1UL) /*!< ITLB (Bit 1) */
|
|
|
+ #define R_GPT0_GTITC_ITLB_Msk (0x2UL) /*!< ITLB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTITC_ITLA_Pos (0UL) /*!< ITLA (Bit 0) */
|
|
|
+ #define R_GPT0_GTITC_ITLA_Msk (0x1UL) /*!< ITLA (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= GTCNT ========================================================= */
|
|
|
+ #define R_GPT0_GTCNT_GTCNT_Pos (0UL) /*!< GTCNT (Bit 0) */
|
|
|
+ #define R_GPT0_GTCNT_GTCNT_Msk (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ========================================================= GTCCR ========================================================= */
|
|
|
+ #define R_GPT0_GTCCR_GTCCR_Pos (0UL) /*!< GTCCR (Bit 0) */
|
|
|
+ #define R_GPT0_GTCCR_GTCCR_Msk (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ========================================================= GTPR ========================================================== */
|
|
|
+ #define R_GPT0_GTPR_GTPR_Pos (0UL) /*!< GTPR (Bit 0) */
|
|
|
+ #define R_GPT0_GTPR_GTPR_Msk (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ========================================================= GTPBR ========================================================= */
|
|
|
+ #define R_GPT0_GTPBR_GTPBR_Pos (0UL) /*!< GTPBR (Bit 0) */
|
|
|
+ #define R_GPT0_GTPBR_GTPBR_Msk (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================== GTPDBR ========================================================= */
|
|
|
+ #define R_GPT0_GTPDBR_GTPDBR_Pos (0UL) /*!< GTPDBR (Bit 0) */
|
|
|
+ #define R_GPT0_GTPDBR_GTPDBR_Msk (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================== GTADTRA ======================================================== */
|
|
|
+ #define R_GPT0_GTADTRA_GTADTRA_Pos (0UL) /*!< GTADTRA (Bit 0) */
|
|
|
+ #define R_GPT0_GTADTRA_GTADTRA_Msk (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================== GTADTRB ======================================================== */
|
|
|
+ #define R_GPT0_GTADTRB_GTADTRB_Pos (0UL) /*!< GTADTRB (Bit 0) */
|
|
|
+ #define R_GPT0_GTADTRB_GTADTRB_Msk (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================= GTADTBRA ======================================================== */
|
|
|
+ #define R_GPT0_GTADTBRA_GTADTBRA_Pos (0UL) /*!< GTADTBRA (Bit 0) */
|
|
|
+ #define R_GPT0_GTADTBRA_GTADTBRA_Msk (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================= GTADTBRB ======================================================== */
|
|
|
+ #define R_GPT0_GTADTBRB_GTADTBRB_Pos (0UL) /*!< GTADTBRB (Bit 0) */
|
|
|
+ #define R_GPT0_GTADTBRB_GTADTBRB_Msk (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================= GTADTDBRA ======================================================= */
|
|
|
+ #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos (0UL) /*!< GTADTDBRA (Bit 0) */
|
|
|
+ #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================= GTADTDBRB ======================================================= */
|
|
|
+ #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos (0UL) /*!< GTADTDBRB (Bit 0) */
|
|
|
+ #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================== GTDTCR ========================================================= */
|
|
|
+ #define R_GPT0_GTDTCR_TDFER_Pos (8UL) /*!< TDFER (Bit 8) */
|
|
|
+ #define R_GPT0_GTDTCR_TDFER_Msk (0x100UL) /*!< TDFER (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTDTCR_TDBDE_Pos (5UL) /*!< TDBDE (Bit 5) */
|
|
|
+ #define R_GPT0_GTDTCR_TDBDE_Msk (0x20UL) /*!< TDBDE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTDTCR_TDBUE_Pos (4UL) /*!< TDBUE (Bit 4) */
|
|
|
+ #define R_GPT0_GTDTCR_TDBUE_Msk (0x10UL) /*!< TDBUE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTDTCR_TDE_Pos (0UL) /*!< TDE (Bit 0) */
|
|
|
+ #define R_GPT0_GTDTCR_TDE_Msk (0x1UL) /*!< TDE (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= GTDVU ========================================================= */
|
|
|
+ #define R_GPT0_GTDVU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */
|
|
|
+ #define R_GPT0_GTDVU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ========================================================= GTDVD ========================================================= */
|
|
|
+ #define R_GPT0_GTDVD_GTDVD_Pos (0UL) /*!< GTDVD (Bit 0) */
|
|
|
+ #define R_GPT0_GTDVD_GTDVD_Msk (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ========================================================= GTDBU ========================================================= */
|
|
|
+ #define R_GPT0_GTDBU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */
|
|
|
+ #define R_GPT0_GTDBU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ========================================================= GTDBD ========================================================= */
|
|
|
+ #define R_GPT0_GTDBD_GTDBD_Pos (0UL) /*!< GTDBD (Bit 0) */
|
|
|
+ #define R_GPT0_GTDBD_GTDBD_Msk (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ========================================================= GTSOS ========================================================= */
|
|
|
+ #define R_GPT0_GTSOS_SOS_Pos (0UL) /*!< SOS (Bit 0) */
|
|
|
+ #define R_GPT0_GTSOS_SOS_Msk (0x3UL) /*!< SOS (Bitfield-Mask: 0x03) */
|
|
|
+/* ======================================================== GTSOTR ========================================================= */
|
|
|
+ #define R_GPT0_GTSOTR_SOTR_Pos (0UL) /*!< SOTR (Bit 0) */
|
|
|
+ #define R_GPT0_GTSOTR_SOTR_Msk (0x1UL) /*!< SOTR (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== GTADSMR ======================================================== */
|
|
|
+ #define R_GPT0_GTADSMR_ADSMS0_Pos (0UL) /*!< ADSMS0 (Bit 0) */
|
|
|
+ #define R_GPT0_GTADSMR_ADSMS0_Msk (0x3UL) /*!< ADSMS0 (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_GPT0_GTADSMR_ADSMEN0_Pos (8UL) /*!< ADSMEN0 (Bit 8) */
|
|
|
+ #define R_GPT0_GTADSMR_ADSMEN0_Msk (0x100UL) /*!< ADSMEN0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTADSMR_ADSMS1_Pos (16UL) /*!< ADSMS1 (Bit 16) */
|
|
|
+ #define R_GPT0_GTADSMR_ADSMS1_Msk (0x30000UL) /*!< ADSMS1 (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_GPT0_GTADSMR_ADSMEN1_Pos (24UL) /*!< ADSMEN1 (Bit 24) */
|
|
|
+ #define R_GPT0_GTADSMR_ADSMEN1_Msk (0x1000000UL) /*!< ADSMEN1 (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== GTEITC ========================================================= */
|
|
|
+ #define R_GPT0_GTEITC_EIVTC1_Pos (0UL) /*!< EIVTC1 (Bit 0) */
|
|
|
+ #define R_GPT0_GTEITC_EIVTC1_Msk (0x3UL) /*!< EIVTC1 (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_GPT0_GTEITC_EIVTT1_Pos (4UL) /*!< EIVTT1 (Bit 4) */
|
|
|
+ #define R_GPT0_GTEITC_EIVTT1_Msk (0xf0UL) /*!< EIVTT1 (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_GPT0_GTEITC_EITCNT1_Pos (12UL) /*!< EITCNT1 (Bit 12) */
|
|
|
+ #define R_GPT0_GTEITC_EITCNT1_Msk (0xf000UL) /*!< EITCNT1 (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_GPT0_GTEITC_EIVTC2_Pos (16UL) /*!< EIVTC2 (Bit 16) */
|
|
|
+ #define R_GPT0_GTEITC_EIVTC2_Msk (0x30000UL) /*!< EIVTC2 (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_GPT0_GTEITC_EIVTT2_Pos (20UL) /*!< EIVTT2 (Bit 20) */
|
|
|
+ #define R_GPT0_GTEITC_EIVTT2_Msk (0xf00000UL) /*!< EIVTT2 (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_GPT0_GTEITC_EITCNT2IV_Pos (24UL) /*!< EITCNT2IV (Bit 24) */
|
|
|
+ #define R_GPT0_GTEITC_EITCNT2IV_Msk (0xf000000UL) /*!< EITCNT2IV (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_GPT0_GTEITC_EITCNT2_Pos (28UL) /*!< EITCNT2 (Bit 28) */
|
|
|
+ #define R_GPT0_GTEITC_EITCNT2_Msk (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f) */
|
|
|
+/* ======================================================= GTEITLI1 ======================================================== */
|
|
|
+ #define R_GPT0_GTEITLI1_EITLA_Pos (0UL) /*!< EITLA (Bit 0) */
|
|
|
+ #define R_GPT0_GTEITLI1_EITLA_Msk (0x7UL) /*!< EITLA (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_GPT0_GTEITLI1_EITLB_Pos (4UL) /*!< EITLB (Bit 4) */
|
|
|
+ #define R_GPT0_GTEITLI1_EITLB_Msk (0x70UL) /*!< EITLB (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_GPT0_GTEITLI1_EITLC_Pos (8UL) /*!< EITLC (Bit 8) */
|
|
|
+ #define R_GPT0_GTEITLI1_EITLC_Msk (0x700UL) /*!< EITLC (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_GPT0_GTEITLI1_EITLD_Pos (12UL) /*!< EITLD (Bit 12) */
|
|
|
+ #define R_GPT0_GTEITLI1_EITLD_Msk (0x7000UL) /*!< EITLD (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_GPT0_GTEITLI1_EITLE_Pos (16UL) /*!< EITLE (Bit 16) */
|
|
|
+ #define R_GPT0_GTEITLI1_EITLE_Msk (0x70000UL) /*!< EITLE (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_GPT0_GTEITLI1_EITLF_Pos (20UL) /*!< EITLF (Bit 20) */
|
|
|
+ #define R_GPT0_GTEITLI1_EITLF_Msk (0x700000UL) /*!< EITLF (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_GPT0_GTEITLI1_EITLV_Pos (24UL) /*!< EITLV (Bit 24) */
|
|
|
+ #define R_GPT0_GTEITLI1_EITLV_Msk (0x7000000UL) /*!< EITLV (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_GPT0_GTEITLI1_EITLU_Pos (28UL) /*!< EITLU (Bit 28) */
|
|
|
+ #define R_GPT0_GTEITLI1_EITLU_Msk (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07) */
|
|
|
+/* ======================================================= GTEITLI2 ======================================================== */
|
|
|
+ #define R_GPT0_GTEITLI2_EADTAL_Pos (0UL) /*!< EADTAL (Bit 0) */
|
|
|
+ #define R_GPT0_GTEITLI2_EADTAL_Msk (0x7UL) /*!< EADTAL (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_GPT0_GTEITLI2_EADTBL_Pos (4UL) /*!< EADTBL (Bit 4) */
|
|
|
+ #define R_GPT0_GTEITLI2_EADTBL_Msk (0x70UL) /*!< EADTBL (Bitfield-Mask: 0x07) */
|
|
|
+/* ======================================================== GTEITLB ======================================================== */
|
|
|
+ #define R_GPT0_GTEITLB_EBTLCA_Pos (0UL) /*!< EBTLCA (Bit 0) */
|
|
|
+ #define R_GPT0_GTEITLB_EBTLCA_Msk (0x7UL) /*!< EBTLCA (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_GPT0_GTEITLB_EBTLCB_Pos (4UL) /*!< EBTLCB (Bit 4) */
|
|
|
+ #define R_GPT0_GTEITLB_EBTLCB_Msk (0x70UL) /*!< EBTLCB (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_GPT0_GTEITLB_EBTLPR_Pos (8UL) /*!< EBTLPR (Bit 8) */
|
|
|
+ #define R_GPT0_GTEITLB_EBTLPR_Msk (0x700UL) /*!< EBTLPR (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_GPT0_GTEITLB_EBTLADA_Pos (16UL) /*!< EBTLADA (Bit 16) */
|
|
|
+ #define R_GPT0_GTEITLB_EBTLADA_Msk (0x70000UL) /*!< EBTLADA (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_GPT0_GTEITLB_EBTLADB_Pos (20UL) /*!< EBTLADB (Bit 20) */
|
|
|
+ #define R_GPT0_GTEITLB_EBTLADB_Msk (0x700000UL) /*!< EBTLADB (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_GPT0_GTEITLB_EBTLDVU_Pos (24UL) /*!< EBTLDVU (Bit 24) */
|
|
|
+ #define R_GPT0_GTEITLB_EBTLDVU_Msk (0x7000000UL) /*!< EBTLDVU (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_GPT0_GTEITLB_EBTLDVD_Pos (28UL) /*!< EBTLDVD (Bit 28) */
|
|
|
+ #define R_GPT0_GTEITLB_EBTLDVD_Msk (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07) */
|
|
|
+/* ======================================================== GTICLF ========================================================= */
|
|
|
+ #define R_GPT0_GTICLF_ICLFA_Pos (0UL) /*!< ICLFA (Bit 0) */
|
|
|
+ #define R_GPT0_GTICLF_ICLFA_Msk (0x7UL) /*!< ICLFA (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_GPT0_GTICLF_ICLFSELC_Pos (4UL) /*!< ICLFSELC (Bit 4) */
|
|
|
+ #define R_GPT0_GTICLF_ICLFSELC_Msk (0x3f0UL) /*!< ICLFSELC (Bitfield-Mask: 0x3f) */
|
|
|
+ #define R_GPT0_GTICLF_ICLFB_Pos (16UL) /*!< ICLFB (Bit 16) */
|
|
|
+ #define R_GPT0_GTICLF_ICLFB_Msk (0x70000UL) /*!< ICLFB (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_GPT0_GTICLF_ICLFSELD_Pos (20UL) /*!< ICLFSELD (Bit 20) */
|
|
|
+ #define R_GPT0_GTICLF_ICLFSELD_Msk (0x3f00000UL) /*!< ICLFSELD (Bitfield-Mask: 0x3f) */
|
|
|
+/* ========================================================= GTPC ========================================================== */
|
|
|
+ #define R_GPT0_GTPC_PCEN_Pos (0UL) /*!< PCEN (Bit 0) */
|
|
|
+ #define R_GPT0_GTPC_PCEN_Msk (0x1UL) /*!< PCEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTPC_ASTP_Pos (8UL) /*!< ASTP (Bit 8) */
|
|
|
+ #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */
|
|
|
+ #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */
|
|
|
+/* ======================================================== GTSECSR ======================================================== */
|
|
|
+ #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */
|
|
|
+ #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTSECSR_SECSEL1_Pos (1UL) /*!< SECSEL1 (Bit 1) */
|
|
|
+ #define R_GPT0_GTSECSR_SECSEL1_Msk (0x2UL) /*!< SECSEL1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTSECSR_SECSEL2_Pos (2UL) /*!< SECSEL2 (Bit 2) */
|
|
|
+ #define R_GPT0_GTSECSR_SECSEL2_Msk (0x4UL) /*!< SECSEL2 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTSECSR_SECSEL3_Pos (3UL) /*!< SECSEL3 (Bit 3) */
|
|
|
+ #define R_GPT0_GTSECSR_SECSEL3_Msk (0x8UL) /*!< SECSEL3 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTSECSR_SECSEL4_Pos (4UL) /*!< SECSEL4 (Bit 4) */
|
|
|
+ #define R_GPT0_GTSECSR_SECSEL4_Msk (0x10UL) /*!< SECSEL4 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTSECSR_SECSEL5_Pos (5UL) /*!< SECSEL5 (Bit 5) */
|
|
|
+ #define R_GPT0_GTSECSR_SECSEL5_Msk (0x20UL) /*!< SECSEL5 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTSECSR_SECSEL6_Pos (6UL) /*!< SECSEL6 (Bit 6) */
|
|
|
+ #define R_GPT0_GTSECSR_SECSEL6_Msk (0x40UL) /*!< SECSEL6 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTSECSR_SECSEL7_Pos (7UL) /*!< SECSEL7 (Bit 7) */
|
|
|
+ #define R_GPT0_GTSECSR_SECSEL7_Msk (0x80UL) /*!< SECSEL7 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTSECSR_SECSEL8_Pos (8UL) /*!< SECSEL8 (Bit 8) */
|
|
|
+ #define R_GPT0_GTSECSR_SECSEL8_Msk (0x100UL) /*!< SECSEL8 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTSECSR_SECSEL9_Pos (9UL) /*!< SECSEL9 (Bit 9) */
|
|
|
+ #define R_GPT0_GTSECSR_SECSEL9_Msk (0x200UL) /*!< SECSEL9 (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== GTSECR ========================================================= */
|
|
|
+ #define R_GPT0_GTSECR_SBDCE_Pos (0UL) /*!< SBDCE (Bit 0) */
|
|
|
+ #define R_GPT0_GTSECR_SBDCE_Msk (0x1UL) /*!< SBDCE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTSECR_SBDPE_Pos (1UL) /*!< SBDPE (Bit 1) */
|
|
|
+ #define R_GPT0_GTSECR_SBDPE_Msk (0x2UL) /*!< SBDPE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTSECR_SBDAE_Pos (2UL) /*!< SBDAE (Bit 2) */
|
|
|
+ #define R_GPT0_GTSECR_SBDAE_Msk (0x4UL) /*!< SBDAE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTSECR_SBDDE_Pos (3UL) /*!< SBDDE (Bit 3) */
|
|
|
+ #define R_GPT0_GTSECR_SBDDE_Msk (0x8UL) /*!< SBDDE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTSECR_SBDCD_Pos (8UL) /*!< SBDCD (Bit 8) */
|
|
|
+ #define R_GPT0_GTSECR_SBDCD_Msk (0x100UL) /*!< SBDCD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTSECR_SBDPD_Pos (9UL) /*!< SBDPD (Bit 9) */
|
|
|
+ #define R_GPT0_GTSECR_SBDPD_Msk (0x200UL) /*!< SBDPD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTSECR_SBDAD_Pos (10UL) /*!< SBDAD (Bit 10) */
|
|
|
+ #define R_GPT0_GTSECR_SBDAD_Msk (0x400UL) /*!< SBDAD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTSECR_SBDDD_Pos (11UL) /*!< SBDDD (Bit 11) */
|
|
|
+ #define R_GPT0_GTSECR_SBDDD_Msk (0x800UL) /*!< SBDDD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTSECR_SPCE_Pos (16UL) /*!< SPCE (Bit 16) */
|
|
|
+ #define R_GPT0_GTSECR_SPCE_Msk (0x10000UL) /*!< SPCE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTSECR_SSCE_Pos (17UL) /*!< SSCE (Bit 17) */
|
|
|
+ #define R_GPT0_GTSECR_SSCE_Msk (0x20000UL) /*!< SSCE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTSECR_SPCD_Pos (24UL) /*!< SPCD (Bit 24) */
|
|
|
+ #define R_GPT0_GTSECR_SPCD_Msk (0x1000000UL) /*!< SPCD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTSECR_SSCD_Pos (25UL) /*!< SSCD (Bit 25) */
|
|
|
+ #define R_GPT0_GTSECR_SSCD_Msk (0x2000000UL) /*!< SSCD (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== GTBER2 ========================================================= */
|
|
|
+ #define R_GPT0_GTBER2_CCTCA_Pos (0UL) /*!< CCTCA (Bit 0) */
|
|
|
+ #define R_GPT0_GTBER2_CCTCA_Msk (0x1UL) /*!< CCTCA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTBER2_CCTCB_Pos (1UL) /*!< CCTCB (Bit 1) */
|
|
|
+ #define R_GPT0_GTBER2_CCTCB_Msk (0x2UL) /*!< CCTCB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTBER2_CCTPR_Pos (2UL) /*!< CCTPR (Bit 2) */
|
|
|
+ #define R_GPT0_GTBER2_CCTPR_Msk (0x4UL) /*!< CCTPR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTBER2_CCTADA_Pos (3UL) /*!< CCTADA (Bit 3) */
|
|
|
+ #define R_GPT0_GTBER2_CCTADA_Msk (0x8UL) /*!< CCTADA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTBER2_CCTADB_Pos (4UL) /*!< CCTADB (Bit 4) */
|
|
|
+ #define R_GPT0_GTBER2_CCTADB_Msk (0x10UL) /*!< CCTADB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTBER2_CCTDV_Pos (5UL) /*!< CCTDV (Bit 5) */
|
|
|
+ #define R_GPT0_GTBER2_CCTDV_Msk (0x20UL) /*!< CCTDV (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTBER2_CMTCA_Pos (8UL) /*!< CMTCA (Bit 8) */
|
|
|
+ #define R_GPT0_GTBER2_CMTCA_Msk (0x300UL) /*!< CMTCA (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_GPT0_GTBER2_CMTCB_Pos (10UL) /*!< CMTCB (Bit 10) */
|
|
|
+ #define R_GPT0_GTBER2_CMTCB_Msk (0xc00UL) /*!< CMTCB (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_GPT0_GTBER2_CMTADA_Pos (13UL) /*!< CMTADA (Bit 13) */
|
|
|
+ #define R_GPT0_GTBER2_CMTADA_Msk (0x2000UL) /*!< CMTADA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTBER2_CMTADB_Pos (14UL) /*!< CMTADB (Bit 14) */
|
|
|
+ #define R_GPT0_GTBER2_CMTADB_Msk (0x4000UL) /*!< CMTADB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTBER2_CPTCA_Pos (16UL) /*!< CPTCA (Bit 16) */
|
|
|
+ #define R_GPT0_GTBER2_CPTCA_Msk (0x10000UL) /*!< CPTCA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTBER2_CPTCB_Pos (17UL) /*!< CPTCB (Bit 17) */
|
|
|
+ #define R_GPT0_GTBER2_CPTCB_Msk (0x20000UL) /*!< CPTCB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTBER2_CPTPR_Pos (18UL) /*!< CPTPR (Bit 18) */
|
|
|
+ #define R_GPT0_GTBER2_CPTPR_Msk (0x40000UL) /*!< CPTPR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTBER2_CPTADA_Pos (19UL) /*!< CPTADA (Bit 19) */
|
|
|
+ #define R_GPT0_GTBER2_CPTADA_Msk (0x80000UL) /*!< CPTADA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTBER2_CPTADB_Pos (20UL) /*!< CPTADB (Bit 20) */
|
|
|
+ #define R_GPT0_GTBER2_CPTADB_Msk (0x100000UL) /*!< CPTADB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTBER2_CPTDV_Pos (21UL) /*!< CPTDV (Bit 21) */
|
|
|
+ #define R_GPT0_GTBER2_CPTDV_Msk (0x200000UL) /*!< CPTDV (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTBER2_CP3DB_Pos (24UL) /*!< CP3DB (Bit 24) */
|
|
|
+ #define R_GPT0_GTBER2_CP3DB_Msk (0x1000000UL) /*!< CP3DB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTBER2_CPBTD_Pos (25UL) /*!< CPBTD (Bit 25) */
|
|
|
+ #define R_GPT0_GTBER2_CPBTD_Msk (0x2000000UL) /*!< CPBTD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTBER2_OLTTA_Pos (26UL) /*!< OLTTA (Bit 26) */
|
|
|
+ #define R_GPT0_GTBER2_OLTTA_Msk (0xc000000UL) /*!< OLTTA (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_GPT0_GTBER2_OLTTB_Pos (28UL) /*!< OLTTB (Bit 28) */
|
|
|
+ #define R_GPT0_GTBER2_OLTTB_Msk (0x30000000UL) /*!< OLTTB (Bitfield-Mask: 0x03) */
|
|
|
+/* ======================================================== GTOLBR ========================================================= */
|
|
|
+ #define R_GPT0_GTOLBR_GTIOAB_Pos (0UL) /*!< GTIOAB (Bit 0) */
|
|
|
+ #define R_GPT0_GTOLBR_GTIOAB_Msk (0x1fUL) /*!< GTIOAB (Bitfield-Mask: 0x1f) */
|
|
|
+ #define R_GPT0_GTOLBR_GTIOBB_Pos (16UL) /*!< GTIOBB (Bit 16) */
|
|
|
+ #define R_GPT0_GTOLBR_GTIOBB_Msk (0x1f0000UL) /*!< GTIOBB (Bitfield-Mask: 0x1f) */
|
|
|
+/* ======================================================== GTICCR ========================================================= */
|
|
|
+ #define R_GPT0_GTICCR_ICAFA_Pos (0UL) /*!< ICAFA (Bit 0) */
|
|
|
+ #define R_GPT0_GTICCR_ICAFA_Msk (0x1UL) /*!< ICAFA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTICCR_ICAFB_Pos (1UL) /*!< ICAFB (Bit 1) */
|
|
|
+ #define R_GPT0_GTICCR_ICAFB_Msk (0x2UL) /*!< ICAFB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTICCR_ICAFC_Pos (2UL) /*!< ICAFC (Bit 2) */
|
|
|
+ #define R_GPT0_GTICCR_ICAFC_Msk (0x4UL) /*!< ICAFC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTICCR_ICAFD_Pos (3UL) /*!< ICAFD (Bit 3) */
|
|
|
+ #define R_GPT0_GTICCR_ICAFD_Msk (0x8UL) /*!< ICAFD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTICCR_ICAFE_Pos (4UL) /*!< ICAFE (Bit 4) */
|
|
|
+ #define R_GPT0_GTICCR_ICAFE_Msk (0x10UL) /*!< ICAFE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTICCR_ICAFF_Pos (5UL) /*!< ICAFF (Bit 5) */
|
|
|
+ #define R_GPT0_GTICCR_ICAFF_Msk (0x20UL) /*!< ICAFF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTICCR_ICAFPO_Pos (6UL) /*!< ICAFPO (Bit 6) */
|
|
|
+ #define R_GPT0_GTICCR_ICAFPO_Msk (0x40UL) /*!< ICAFPO (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTICCR_ICAFPU_Pos (7UL) /*!< ICAFPU (Bit 7) */
|
|
|
+ #define R_GPT0_GTICCR_ICAFPU_Msk (0x80UL) /*!< ICAFPU (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTICCR_ICACLK_Pos (8UL) /*!< ICACLK (Bit 8) */
|
|
|
+ #define R_GPT0_GTICCR_ICACLK_Msk (0x100UL) /*!< ICACLK (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTICCR_ICAGRP_Pos (14UL) /*!< ICAGRP (Bit 14) */
|
|
|
+ #define R_GPT0_GTICCR_ICAGRP_Msk (0xc000UL) /*!< ICAGRP (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_GPT0_GTICCR_ICBFA_Pos (16UL) /*!< ICBFA (Bit 16) */
|
|
|
+ #define R_GPT0_GTICCR_ICBFA_Msk (0x10000UL) /*!< ICBFA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTICCR_ICBFB_Pos (17UL) /*!< ICBFB (Bit 17) */
|
|
|
+ #define R_GPT0_GTICCR_ICBFB_Msk (0x20000UL) /*!< ICBFB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTICCR_ICBFC_Pos (18UL) /*!< ICBFC (Bit 18) */
|
|
|
+ #define R_GPT0_GTICCR_ICBFC_Msk (0x40000UL) /*!< ICBFC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTICCR_ICBFD_Pos (19UL) /*!< ICBFD (Bit 19) */
|
|
|
+ #define R_GPT0_GTICCR_ICBFD_Msk (0x80000UL) /*!< ICBFD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTICCR_ICBFE_Pos (20UL) /*!< ICBFE (Bit 20) */
|
|
|
+ #define R_GPT0_GTICCR_ICBFE_Msk (0x100000UL) /*!< ICBFE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTICCR_ICBFF_Pos (21UL) /*!< ICBFF (Bit 21) */
|
|
|
+ #define R_GPT0_GTICCR_ICBFF_Msk (0x200000UL) /*!< ICBFF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTICCR_ICBFPO_Pos (22UL) /*!< ICBFPO (Bit 22) */
|
|
|
+ #define R_GPT0_GTICCR_ICBFPO_Msk (0x400000UL) /*!< ICBFPO (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTICCR_ICBFPU_Pos (23UL) /*!< ICBFPU (Bit 23) */
|
|
|
+ #define R_GPT0_GTICCR_ICBFPU_Msk (0x800000UL) /*!< ICBFPU (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTICCR_ICBCLK_Pos (24UL) /*!< ICBCLK (Bit 24) */
|
|
|
+ #define R_GPT0_GTICCR_ICBCLK_Msk (0x1000000UL) /*!< ICBCLK (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT0_GTICCR_ICBGRP_Pos (30UL) /*!< ICBGRP (Bit 30) */
|
|
|
+ #define R_GPT0_GTICCR_ICBGRP_Msk (0xc0000000UL) /*!< ICBGRP (Bitfield-Mask: 0x03) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_GPT_OPS ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================= OPSCR ========================================================= */
|
|
|
+ #define R_GPT_OPS_OPSCR_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */
|
|
|
+ #define R_GPT_OPS_OPSCR_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_GPT_OPS_OPSCR_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */
|
|
|
+ #define R_GPT_OPS_OPSCR_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT_OPS_OPSCR_GODF_Pos (26UL) /*!< GODF (Bit 26) */
|
|
|
+ #define R_GPT_OPS_OPSCR_GODF_Msk (0x4000000UL) /*!< GODF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT_OPS_OPSCR_GRP_Pos (24UL) /*!< GRP (Bit 24) */
|
|
|
+ #define R_GPT_OPS_OPSCR_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_GPT_OPS_OPSCR_ALIGN_Pos (21UL) /*!< ALIGN (Bit 21) */
|
|
|
+ #define R_GPT_OPS_OPSCR_ALIGN_Msk (0x200000UL) /*!< ALIGN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT_OPS_OPSCR_RV_Pos (20UL) /*!< RV (Bit 20) */
|
|
|
+ #define R_GPT_OPS_OPSCR_RV_Msk (0x100000UL) /*!< RV (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT_OPS_OPSCR_INV_Pos (19UL) /*!< INV (Bit 19) */
|
|
|
+ #define R_GPT_OPS_OPSCR_INV_Msk (0x80000UL) /*!< INV (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT_OPS_OPSCR_N_Pos (18UL) /*!< N (Bit 18) */
|
|
|
+ #define R_GPT_OPS_OPSCR_N_Msk (0x40000UL) /*!< N (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT_OPS_OPSCR_P_Pos (17UL) /*!< P (Bit 17) */
|
|
|
+ #define R_GPT_OPS_OPSCR_P_Msk (0x20000UL) /*!< P (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT_OPS_OPSCR_FB_Pos (16UL) /*!< FB (Bit 16) */
|
|
|
+ #define R_GPT_OPS_OPSCR_FB_Msk (0x10000UL) /*!< FB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT_OPS_OPSCR_EN_Pos (8UL) /*!< EN (Bit 8) */
|
|
|
+ #define R_GPT_OPS_OPSCR_EN_Msk (0x100UL) /*!< EN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT_OPS_OPSCR_W_Pos (6UL) /*!< W (Bit 6) */
|
|
|
+ #define R_GPT_OPS_OPSCR_W_Msk (0x40UL) /*!< W (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT_OPS_OPSCR_V_Pos (5UL) /*!< V (Bit 5) */
|
|
|
+ #define R_GPT_OPS_OPSCR_V_Msk (0x20UL) /*!< V (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT_OPS_OPSCR_U_Pos (4UL) /*!< U (Bit 4) */
|
|
|
+ #define R_GPT_OPS_OPSCR_U_Msk (0x10UL) /*!< U (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT_OPS_OPSCR_WF_Pos (2UL) /*!< WF (Bit 2) */
|
|
|
+ #define R_GPT_OPS_OPSCR_WF_Msk (0x4UL) /*!< WF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT_OPS_OPSCR_VF_Pos (1UL) /*!< VF (Bit 1) */
|
|
|
+ #define R_GPT_OPS_OPSCR_VF_Msk (0x2UL) /*!< VF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT_OPS_OPSCR_UF_Pos (0UL) /*!< UF (Bit 0) */
|
|
|
+ #define R_GPT_OPS_OPSCR_UF_Msk (0x1UL) /*!< UF (Bitfield-Mask: 0x01) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_GPT_POEG0 ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================= POEGG ========================================================= */
|
|
|
+ #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */
|
|
|
+ #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */
|
|
|
+ #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */
|
|
|
+ #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT_POEG0_POEGG_DERRE_Pos (26UL) /*!< DERRE (Bit 26) */
|
|
|
+ #define R_GPT_POEG0_POEGG_DERRE_Msk (0x4000000UL) /*!< DERRE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT_POEG0_POEGG_DERRST_Pos (24UL) /*!< DERRST (Bit 24) */
|
|
|
+ #define R_GPT_POEG0_POEGG_DERRST_Msk (0x1000000UL) /*!< DERRST (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */
|
|
|
+ #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */
|
|
|
+ #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */
|
|
|
+ #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */
|
|
|
+ #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */
|
|
|
+ #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */
|
|
|
+ #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */
|
|
|
+ #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */
|
|
|
+ #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */
|
|
|
+ #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== GTONCWP ======================================================== */
|
|
|
+ #define R_GPT_POEG0_GTONCWP_WP_Pos (0UL) /*!< WP (Bit 0) */
|
|
|
+ #define R_GPT_POEG0_GTONCWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT_POEG0_GTONCWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */
|
|
|
+ #define R_GPT_POEG0_GTONCWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== GTONCCR ======================================================== */
|
|
|
+ #define R_GPT_POEG0_GTONCCR_NE_Pos (0UL) /*!< NE (Bit 0) */
|
|
|
+ #define R_GPT_POEG0_GTONCCR_NE_Msk (0x1UL) /*!< NE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_GPT_POEG0_GTONCCR_NFS_Pos (4UL) /*!< NFS (Bit 4) */
|
|
|
+ #define R_GPT_POEG0_GTONCCR_NFS_Msk (0xf0UL) /*!< NFS (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_GPT_POEG0_GTONCCR_NFV_Pos (8UL) /*!< NFV (Bit 8) */
|
|
|
+ #define R_GPT_POEG0_GTONCCR_NFV_Msk (0x100UL) /*!< NFV (Bitfield-Mask: 0x01) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_ICU ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================= IRQCR ========================================================= */
|
|
|
+ #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */
|
|
|
+ #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */
|
|
|
+ #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */
|
|
|
+ #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */
|
|
|
+/* ========================================================= NMICR ========================================================= */
|
|
|
+ #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */
|
|
|
+ #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */
|
|
|
+ #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */
|
|
|
+ #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== SWIRQ_S ======================================================== */
|
|
|
+ #define R_ICU_SWIRQ_S_SWIRQS_Pos (0UL) /*!< SWIRQS (Bit 0) */
|
|
|
+ #define R_ICU_SWIRQ_S_SWIRQS_Msk (0x1UL) /*!< SWIRQS (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= SWIRQ_NS ======================================================== */
|
|
|
+ #define R_ICU_SWIRQ_NS_SWIRQNS_Pos (0UL) /*!< SWIRQNS (Bit 0) */
|
|
|
+ #define R_ICU_SWIRQ_NS_SWIRQNS_Msk (0x1UL) /*!< SWIRQNS (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== IENMIER ======================================================== */
|
|
|
+ #define R_ICU_IENMIER_CMEN_Pos (0UL) /*!< CMEN (Bit 0) */
|
|
|
+ #define R_ICU_IENMIER_CMEN_Msk (0x1UL) /*!< CMEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_IENMIER_LMEN_Pos (1UL) /*!< LMEN (Bit 1) */
|
|
|
+ #define R_ICU_IENMIER_LMEN_Msk (0x2UL) /*!< LMEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_IENMIER_BUSEN_Pos (2UL) /*!< BUSEN (Bit 2) */
|
|
|
+ #define R_ICU_IENMIER_BUSEN_Msk (0x4UL) /*!< BUSEN (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= NMIER ========================================================= */
|
|
|
+ #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */
|
|
|
+ #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */
|
|
|
+ #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */
|
|
|
+ #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */
|
|
|
+ #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */
|
|
|
+ #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */
|
|
|
+ #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_NMIER_BUSEN_Pos (12UL) /*!< BUSEN (Bit 12) */
|
|
|
+ #define R_ICU_NMIER_BUSEN_Msk (0x1000UL) /*!< BUSEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_NMIER_CMEN_Pos (13UL) /*!< CMEN (Bit 13) */
|
|
|
+ #define R_ICU_NMIER_CMEN_Msk (0x2000UL) /*!< CMEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_NMIER_LUEN_Pos (15UL) /*!< LUEN (Bit 15) */
|
|
|
+ #define R_ICU_NMIER_LUEN_Msk (0x8000UL) /*!< LUEN (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== NMICLR ========================================================= */
|
|
|
+ #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */
|
|
|
+ #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */
|
|
|
+ #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */
|
|
|
+ #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */
|
|
|
+ #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */
|
|
|
+ #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */
|
|
|
+ #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_NMICLR_BUSCLR_Pos (12UL) /*!< BUSCLR (Bit 12) */
|
|
|
+ #define R_ICU_NMICLR_BUSCLR_Msk (0x1000UL) /*!< BUSCLR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_NMICLR_CMCLR_Pos (13UL) /*!< CMCLR (Bit 13) */
|
|
|
+ #define R_ICU_NMICLR_CMCLR_Msk (0x2000UL) /*!< CMCLR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_NMICLR_LUCLR_Pos (15UL) /*!< LUCLR (Bit 15) */
|
|
|
+ #define R_ICU_NMICLR_LUCLR_Msk (0x8000UL) /*!< LUCLR (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= NMISR ========================================================= */
|
|
|
+ #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */
|
|
|
+ #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */
|
|
|
+ #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */
|
|
|
+ #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */
|
|
|
+ #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */
|
|
|
+ #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */
|
|
|
+ #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_NMISR_BUSST_Pos (12UL) /*!< BUSST (Bit 12) */
|
|
|
+ #define R_ICU_NMISR_BUSST_Msk (0x1000UL) /*!< BUSST (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_NMISR_CMST_Pos (13UL) /*!< CMST (Bit 13) */
|
|
|
+ #define R_ICU_NMISR_CMST_Msk (0x2000UL) /*!< CMST (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_NMISR_LUST_Pos (15UL) /*!< LUST (Bit 15) */
|
|
|
+ #define R_ICU_NMISR_LUST_Msk (0x8000UL) /*!< LUST (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= WUPEN ========================================================= */
|
|
|
+ #define R_ICU_WUPEN_IRQWUPEN0_Pos (0UL) /*!< IRQWUPEN0 (Bit 0) */
|
|
|
+ #define R_ICU_WUPEN_IRQWUPEN0_Msk (0x1UL) /*!< IRQWUPEN0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_WUPEN_IRQWUPEN1_Pos (1UL) /*!< IRQWUPEN1 (Bit 1) */
|
|
|
+ #define R_ICU_WUPEN_IRQWUPEN1_Msk (0x2UL) /*!< IRQWUPEN1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_WUPEN_IRQWUPEN2_Pos (2UL) /*!< IRQWUPEN2 (Bit 2) */
|
|
|
+ #define R_ICU_WUPEN_IRQWUPEN2_Msk (0x4UL) /*!< IRQWUPEN2 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_WUPEN_IRQWUPEN3_Pos (3UL) /*!< IRQWUPEN3 (Bit 3) */
|
|
|
+ #define R_ICU_WUPEN_IRQWUPEN3_Msk (0x8UL) /*!< IRQWUPEN3 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_WUPEN_IRQWUPEN4_Pos (4UL) /*!< IRQWUPEN4 (Bit 4) */
|
|
|
+ #define R_ICU_WUPEN_IRQWUPEN4_Msk (0x10UL) /*!< IRQWUPEN4 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_WUPEN_IRQWUPEN5_Pos (5UL) /*!< IRQWUPEN5 (Bit 5) */
|
|
|
+ #define R_ICU_WUPEN_IRQWUPEN5_Msk (0x20UL) /*!< IRQWUPEN5 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_WUPEN_IRQWUPEN6_Pos (6UL) /*!< IRQWUPEN6 (Bit 6) */
|
|
|
+ #define R_ICU_WUPEN_IRQWUPEN6_Msk (0x40UL) /*!< IRQWUPEN6 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_WUPEN_IRQWUPEN7_Pos (7UL) /*!< IRQWUPEN7 (Bit 7) */
|
|
|
+ #define R_ICU_WUPEN_IRQWUPEN7_Msk (0x80UL) /*!< IRQWUPEN7 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_WUPEN_IRQWUPEN8_Pos (8UL) /*!< IRQWUPEN8 (Bit 8) */
|
|
|
+ #define R_ICU_WUPEN_IRQWUPEN8_Msk (0x100UL) /*!< IRQWUPEN8 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_WUPEN_IRQWUPEN9_Pos (9UL) /*!< IRQWUPEN9 (Bit 9) */
|
|
|
+ #define R_ICU_WUPEN_IRQWUPEN9_Msk (0x200UL) /*!< IRQWUPEN9 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_WUPEN_IRQWUPEN10_Pos (10UL) /*!< IRQWUPEN10 (Bit 10) */
|
|
|
+ #define R_ICU_WUPEN_IRQWUPEN10_Msk (0x400UL) /*!< IRQWUPEN10 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_WUPEN_IRQWUPEN11_Pos (11UL) /*!< IRQWUPEN11 (Bit 11) */
|
|
|
+ #define R_ICU_WUPEN_IRQWUPEN11_Msk (0x800UL) /*!< IRQWUPEN11 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_WUPEN_IRQWUPEN12_Pos (12UL) /*!< IRQWUPEN12 (Bit 12) */
|
|
|
+ #define R_ICU_WUPEN_IRQWUPEN12_Msk (0x1000UL) /*!< IRQWUPEN12 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_WUPEN_IRQWUPEN13_Pos (13UL) /*!< IRQWUPEN13 (Bit 13) */
|
|
|
+ #define R_ICU_WUPEN_IRQWUPEN13_Msk (0x2000UL) /*!< IRQWUPEN13 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_WUPEN_IRQWUPEN14_Pos (14UL) /*!< IRQWUPEN14 (Bit 14) */
|
|
|
+ #define R_ICU_WUPEN_IRQWUPEN14_Msk (0x4000UL) /*!< IRQWUPEN14 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_WUPEN_IRQWUPEN15_Pos (15UL) /*!< IRQWUPEN15 (Bit 15) */
|
|
|
+ #define R_ICU_WUPEN_IRQWUPEN15_Msk (0x8000UL) /*!< IRQWUPEN15 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */
|
|
|
+ #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */
|
|
|
+ #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */
|
|
|
+ #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */
|
|
|
+ #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */
|
|
|
+ #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */
|
|
|
+ #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */
|
|
|
+ #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */
|
|
|
+ #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */
|
|
|
+ #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */
|
|
|
+ #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */
|
|
|
+ #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_WUPEN_RIIC0WUPEN_Pos (31UL) /*!< RIIC0WUPEN (Bit 31) */
|
|
|
+ #define R_ICU_WUPEN_RIIC0WUPEN_Msk (0x80000000UL) /*!< RIIC0WUPEN (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== WUPEN1 ========================================================= */
|
|
|
+ #define R_ICU_WUPEN1_COMPHS0WUPEN_Pos (3UL) /*!< COMPHS0WUPEN (Bit 3) */
|
|
|
+ #define R_ICU_WUPEN1_COMPHS0WUPEN_Msk (0x8UL) /*!< COMPHS0WUPEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_WUPEN1_ULP0UWUPEN_Pos (8UL) /*!< ULP0UWUPEN (Bit 8) */
|
|
|
+ #define R_ICU_WUPEN1_ULP0UWUPEN_Msk (0x100UL) /*!< ULP0UWUPEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_WUPEN1_ULP0AWUPEN_Pos (9UL) /*!< ULP0AWUPEN (Bit 9) */
|
|
|
+ #define R_ICU_WUPEN1_ULP0AWUPEN_Msk (0x200UL) /*!< ULP0AWUPEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_WUPEN1_ULP0BWUPEN_Pos (10UL) /*!< ULP0BWUPEN (Bit 10) */
|
|
|
+ #define R_ICU_WUPEN1_ULP0BWUPEN_Msk (0x400UL) /*!< ULP0BWUPEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_WUPEN1_I3CWUPEN_Pos (11UL) /*!< I3CWUPEN (Bit 11) */
|
|
|
+ #define R_ICU_WUPEN1_I3CWUPEN_Msk (0x800UL) /*!< I3CWUPEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_WUPEN1_ULP1UWUPEN_Pos (12UL) /*!< ULP1UWUPEN (Bit 12) */
|
|
|
+ #define R_ICU_WUPEN1_ULP1UWUPEN_Msk (0x1000UL) /*!< ULP1UWUPEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_WUPEN1_ULP1AWUPEN_Pos (13UL) /*!< ULP1AWUPEN (Bit 13) */
|
|
|
+ #define R_ICU_WUPEN1_ULP1AWUPEN_Msk (0x2000UL) /*!< ULP1AWUPEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_WUPEN1_ULP1BWUPEN_Pos (14UL) /*!< ULP1BWUPEN (Bit 14) */
|
|
|
+ #define R_ICU_WUPEN1_ULP1BWUPEN_Msk (0x4000UL) /*!< ULP1BWUPEN (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= IELSR ========================================================= */
|
|
|
+ #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */
|
|
|
+ #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */
|
|
|
+ #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */
|
|
|
+ #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_IIC0 ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================= ICCR1 ========================================================= */
|
|
|
+ #define R_IIC0_ICCR1_ICE_Pos (7UL) /*!< ICE (Bit 7) */
|
|
|
+ #define R_IIC0_ICCR1_ICE_Msk (0x80UL) /*!< ICE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICCR1_IICRST_Pos (6UL) /*!< IICRST (Bit 6) */
|
|
|
+ #define R_IIC0_ICCR1_IICRST_Msk (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICCR1_CLO_Pos (5UL) /*!< CLO (Bit 5) */
|
|
|
+ #define R_IIC0_ICCR1_CLO_Msk (0x20UL) /*!< CLO (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICCR1_SOWP_Pos (4UL) /*!< SOWP (Bit 4) */
|
|
|
+ #define R_IIC0_ICCR1_SOWP_Msk (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICCR1_SCLO_Pos (3UL) /*!< SCLO (Bit 3) */
|
|
|
+ #define R_IIC0_ICCR1_SCLO_Msk (0x8UL) /*!< SCLO (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICCR1_SDAO_Pos (2UL) /*!< SDAO (Bit 2) */
|
|
|
+ #define R_IIC0_ICCR1_SDAO_Msk (0x4UL) /*!< SDAO (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICCR1_SCLI_Pos (1UL) /*!< SCLI (Bit 1) */
|
|
|
+ #define R_IIC0_ICCR1_SCLI_Msk (0x2UL) /*!< SCLI (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICCR1_SDAI_Pos (0UL) /*!< SDAI (Bit 0) */
|
|
|
+ #define R_IIC0_ICCR1_SDAI_Msk (0x1UL) /*!< SDAI (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= ICCR2 ========================================================= */
|
|
|
+ #define R_IIC0_ICCR2_BBSY_Pos (7UL) /*!< BBSY (Bit 7) */
|
|
|
+ #define R_IIC0_ICCR2_BBSY_Msk (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICCR2_MST_Pos (6UL) /*!< MST (Bit 6) */
|
|
|
+ #define R_IIC0_ICCR2_MST_Msk (0x40UL) /*!< MST (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICCR2_TRS_Pos (5UL) /*!< TRS (Bit 5) */
|
|
|
+ #define R_IIC0_ICCR2_TRS_Msk (0x20UL) /*!< TRS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICCR2_SP_Pos (3UL) /*!< SP (Bit 3) */
|
|
|
+ #define R_IIC0_ICCR2_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICCR2_RS_Pos (2UL) /*!< RS (Bit 2) */
|
|
|
+ #define R_IIC0_ICCR2_RS_Msk (0x4UL) /*!< RS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICCR2_ST_Pos (1UL) /*!< ST (Bit 1) */
|
|
|
+ #define R_IIC0_ICCR2_ST_Msk (0x2UL) /*!< ST (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= ICMR1 ========================================================= */
|
|
|
+ #define R_IIC0_ICMR1_MTWP_Pos (7UL) /*!< MTWP (Bit 7) */
|
|
|
+ #define R_IIC0_ICMR1_MTWP_Msk (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICMR1_CKS_Pos (4UL) /*!< CKS (Bit 4) */
|
|
|
+ #define R_IIC0_ICMR1_CKS_Msk (0x70UL) /*!< CKS (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_IIC0_ICMR1_BCWP_Pos (3UL) /*!< BCWP (Bit 3) */
|
|
|
+ #define R_IIC0_ICMR1_BCWP_Msk (0x8UL) /*!< BCWP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICMR1_BC_Pos (0UL) /*!< BC (Bit 0) */
|
|
|
+ #define R_IIC0_ICMR1_BC_Msk (0x7UL) /*!< BC (Bitfield-Mask: 0x07) */
|
|
|
+/* ========================================================= ICMR2 ========================================================= */
|
|
|
+ #define R_IIC0_ICMR2_DLCS_Pos (7UL) /*!< DLCS (Bit 7) */
|
|
|
+ #define R_IIC0_ICMR2_DLCS_Msk (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICMR2_SDDL_Pos (4UL) /*!< SDDL (Bit 4) */
|
|
|
+ #define R_IIC0_ICMR2_SDDL_Msk (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_IIC0_ICMR2_TMOH_Pos (2UL) /*!< TMOH (Bit 2) */
|
|
|
+ #define R_IIC0_ICMR2_TMOH_Msk (0x4UL) /*!< TMOH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICMR2_TMOL_Pos (1UL) /*!< TMOL (Bit 1) */
|
|
|
+ #define R_IIC0_ICMR2_TMOL_Msk (0x2UL) /*!< TMOL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICMR2_TMOS_Pos (0UL) /*!< TMOS (Bit 0) */
|
|
|
+ #define R_IIC0_ICMR2_TMOS_Msk (0x1UL) /*!< TMOS (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= ICMR3 ========================================================= */
|
|
|
+ #define R_IIC0_ICMR3_SMBS_Pos (7UL) /*!< SMBS (Bit 7) */
|
|
|
+ #define R_IIC0_ICMR3_SMBS_Msk (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICMR3_WAIT_Pos (6UL) /*!< WAIT (Bit 6) */
|
|
|
+ #define R_IIC0_ICMR3_WAIT_Msk (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICMR3_RDRFS_Pos (5UL) /*!< RDRFS (Bit 5) */
|
|
|
+ #define R_IIC0_ICMR3_RDRFS_Msk (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICMR3_ACKWP_Pos (4UL) /*!< ACKWP (Bit 4) */
|
|
|
+ #define R_IIC0_ICMR3_ACKWP_Msk (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICMR3_ACKBT_Pos (3UL) /*!< ACKBT (Bit 3) */
|
|
|
+ #define R_IIC0_ICMR3_ACKBT_Msk (0x8UL) /*!< ACKBT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICMR3_ACKBR_Pos (2UL) /*!< ACKBR (Bit 2) */
|
|
|
+ #define R_IIC0_ICMR3_ACKBR_Msk (0x4UL) /*!< ACKBR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICMR3_NF_Pos (0UL) /*!< NF (Bit 0) */
|
|
|
+ #define R_IIC0_ICMR3_NF_Msk (0x3UL) /*!< NF (Bitfield-Mask: 0x03) */
|
|
|
+/* ========================================================= ICFER ========================================================= */
|
|
|
+ #define R_IIC0_ICFER_FMPE_Pos (7UL) /*!< FMPE (Bit 7) */
|
|
|
+ #define R_IIC0_ICFER_FMPE_Msk (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICFER_SCLE_Pos (6UL) /*!< SCLE (Bit 6) */
|
|
|
+ #define R_IIC0_ICFER_SCLE_Msk (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICFER_NFE_Pos (5UL) /*!< NFE (Bit 5) */
|
|
|
+ #define R_IIC0_ICFER_NFE_Msk (0x20UL) /*!< NFE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICFER_NACKE_Pos (4UL) /*!< NACKE (Bit 4) */
|
|
|
+ #define R_IIC0_ICFER_NACKE_Msk (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICFER_SALE_Pos (3UL) /*!< SALE (Bit 3) */
|
|
|
+ #define R_IIC0_ICFER_SALE_Msk (0x8UL) /*!< SALE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICFER_NALE_Pos (2UL) /*!< NALE (Bit 2) */
|
|
|
+ #define R_IIC0_ICFER_NALE_Msk (0x4UL) /*!< NALE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICFER_MALE_Pos (1UL) /*!< MALE (Bit 1) */
|
|
|
+ #define R_IIC0_ICFER_MALE_Msk (0x2UL) /*!< MALE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICFER_TMOE_Pos (0UL) /*!< TMOE (Bit 0) */
|
|
|
+ #define R_IIC0_ICFER_TMOE_Msk (0x1UL) /*!< TMOE (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= ICSER ========================================================= */
|
|
|
+ #define R_IIC0_ICSER_HOAE_Pos (7UL) /*!< HOAE (Bit 7) */
|
|
|
+ #define R_IIC0_ICSER_HOAE_Msk (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICSER_DIDE_Pos (5UL) /*!< DIDE (Bit 5) */
|
|
|
+ #define R_IIC0_ICSER_DIDE_Msk (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICSER_GCAE_Pos (3UL) /*!< GCAE (Bit 3) */
|
|
|
+ #define R_IIC0_ICSER_GCAE_Msk (0x8UL) /*!< GCAE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICSER_SAR2E_Pos (2UL) /*!< SAR2E (Bit 2) */
|
|
|
+ #define R_IIC0_ICSER_SAR2E_Msk (0x4UL) /*!< SAR2E (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICSER_SAR1E_Pos (1UL) /*!< SAR1E (Bit 1) */
|
|
|
+ #define R_IIC0_ICSER_SAR1E_Msk (0x2UL) /*!< SAR1E (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICSER_SAR0E_Pos (0UL) /*!< SAR0E (Bit 0) */
|
|
|
+ #define R_IIC0_ICSER_SAR0E_Msk (0x1UL) /*!< SAR0E (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= ICIER ========================================================= */
|
|
|
+ #define R_IIC0_ICIER_TIE_Pos (7UL) /*!< TIE (Bit 7) */
|
|
|
+ #define R_IIC0_ICIER_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICIER_TEIE_Pos (6UL) /*!< TEIE (Bit 6) */
|
|
|
+ #define R_IIC0_ICIER_TEIE_Msk (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICIER_RIE_Pos (5UL) /*!< RIE (Bit 5) */
|
|
|
+ #define R_IIC0_ICIER_RIE_Msk (0x20UL) /*!< RIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICIER_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */
|
|
|
+ #define R_IIC0_ICIER_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICIER_SPIE_Pos (3UL) /*!< SPIE (Bit 3) */
|
|
|
+ #define R_IIC0_ICIER_SPIE_Msk (0x8UL) /*!< SPIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICIER_STIE_Pos (2UL) /*!< STIE (Bit 2) */
|
|
|
+ #define R_IIC0_ICIER_STIE_Msk (0x4UL) /*!< STIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICIER_ALIE_Pos (1UL) /*!< ALIE (Bit 1) */
|
|
|
+ #define R_IIC0_ICIER_ALIE_Msk (0x2UL) /*!< ALIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICIER_TMOIE_Pos (0UL) /*!< TMOIE (Bit 0) */
|
|
|
+ #define R_IIC0_ICIER_TMOIE_Msk (0x1UL) /*!< TMOIE (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= ICSR1 ========================================================= */
|
|
|
+ #define R_IIC0_ICSR1_HOA_Pos (7UL) /*!< HOA (Bit 7) */
|
|
|
+ #define R_IIC0_ICSR1_HOA_Msk (0x80UL) /*!< HOA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICSR1_DID_Pos (5UL) /*!< DID (Bit 5) */
|
|
|
+ #define R_IIC0_ICSR1_DID_Msk (0x20UL) /*!< DID (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICSR1_GCA_Pos (3UL) /*!< GCA (Bit 3) */
|
|
|
+ #define R_IIC0_ICSR1_GCA_Msk (0x8UL) /*!< GCA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICSR1_AAS2_Pos (2UL) /*!< AAS2 (Bit 2) */
|
|
|
+ #define R_IIC0_ICSR1_AAS2_Msk (0x4UL) /*!< AAS2 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICSR1_AAS1_Pos (1UL) /*!< AAS1 (Bit 1) */
|
|
|
+ #define R_IIC0_ICSR1_AAS1_Msk (0x2UL) /*!< AAS1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICSR1_AAS0_Pos (0UL) /*!< AAS0 (Bit 0) */
|
|
|
+ #define R_IIC0_ICSR1_AAS0_Msk (0x1UL) /*!< AAS0 (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= ICSR2 ========================================================= */
|
|
|
+ #define R_IIC0_ICSR2_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */
|
|
|
+ #define R_IIC0_ICSR2_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICSR2_TEND_Pos (6UL) /*!< TEND (Bit 6) */
|
|
|
+ #define R_IIC0_ICSR2_TEND_Msk (0x40UL) /*!< TEND (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICSR2_RDRF_Pos (5UL) /*!< RDRF (Bit 5) */
|
|
|
+ #define R_IIC0_ICSR2_RDRF_Msk (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICSR2_NACKF_Pos (4UL) /*!< NACKF (Bit 4) */
|
|
|
+ #define R_IIC0_ICSR2_NACKF_Msk (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICSR2_STOP_Pos (3UL) /*!< STOP (Bit 3) */
|
|
|
+ #define R_IIC0_ICSR2_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICSR2_START_Pos (2UL) /*!< START (Bit 2) */
|
|
|
+ #define R_IIC0_ICSR2_START_Msk (0x4UL) /*!< START (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICSR2_AL_Pos (1UL) /*!< AL (Bit 1) */
|
|
|
+ #define R_IIC0_ICSR2_AL_Msk (0x2UL) /*!< AL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICSR2_TMOF_Pos (0UL) /*!< TMOF (Bit 0) */
|
|
|
+ #define R_IIC0_ICSR2_TMOF_Msk (0x1UL) /*!< TMOF (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= ICBRL ========================================================= */
|
|
|
+ #define R_IIC0_ICBRL_BRL_Pos (0UL) /*!< BRL (Bit 0) */
|
|
|
+ #define R_IIC0_ICBRL_BRL_Msk (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f) */
|
|
|
+/* ========================================================= ICBRH ========================================================= */
|
|
|
+ #define R_IIC0_ICBRH_BRH_Pos (0UL) /*!< BRH (Bit 0) */
|
|
|
+ #define R_IIC0_ICBRH_BRH_Msk (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f) */
|
|
|
+/* ========================================================= ICDRT ========================================================= */
|
|
|
+ #define R_IIC0_ICDRT_ICDRT_Pos (0UL) /*!< ICDRT (Bit 0) */
|
|
|
+ #define R_IIC0_ICDRT_ICDRT_Msk (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff) */
|
|
|
+/* ========================================================= ICDRR ========================================================= */
|
|
|
+ #define R_IIC0_ICDRR_ICDRR_Pos (0UL) /*!< ICDRR (Bit 0) */
|
|
|
+ #define R_IIC0_ICDRR_ICDRR_Msk (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff) */
|
|
|
+/* ========================================================= ICWUR ========================================================= */
|
|
|
+ #define R_IIC0_ICWUR_WUE_Pos (7UL) /*!< WUE (Bit 7) */
|
|
|
+ #define R_IIC0_ICWUR_WUE_Msk (0x80UL) /*!< WUE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICWUR_WUIE_Pos (6UL) /*!< WUIE (Bit 6) */
|
|
|
+ #define R_IIC0_ICWUR_WUIE_Msk (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICWUR_WUF_Pos (5UL) /*!< WUF (Bit 5) */
|
|
|
+ #define R_IIC0_ICWUR_WUF_Msk (0x20UL) /*!< WUF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICWUR_WUACK_Pos (4UL) /*!< WUACK (Bit 4) */
|
|
|
+ #define R_IIC0_ICWUR_WUACK_Msk (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICWUR_WUAFA_Pos (0UL) /*!< WUAFA (Bit 0) */
|
|
|
+ #define R_IIC0_ICWUR_WUAFA_Msk (0x1UL) /*!< WUAFA (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== ICWUR2 ========================================================= */
|
|
|
+ #define R_IIC0_ICWUR2_WUSYF_Pos (2UL) /*!< WUSYF (Bit 2) */
|
|
|
+ #define R_IIC0_ICWUR2_WUSYF_Msk (0x4UL) /*!< WUSYF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICWUR2_WUASYF_Pos (1UL) /*!< WUASYF (Bit 1) */
|
|
|
+ #define R_IIC0_ICWUR2_WUASYF_Msk (0x2UL) /*!< WUASYF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IIC0_ICWUR2_WUSEN_Pos (0UL) /*!< WUSEN (Bit 0) */
|
|
|
+ #define R_IIC0_ICWUR2_WUSEN_Msk (0x1UL) /*!< WUSEN (Bitfield-Mask: 0x01) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_IWDT ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ======================================================== IWDTRR ========================================================= */
|
|
|
+ #define R_IWDT_IWDTRR_IWDTRR_Pos (0UL) /*!< IWDTRR (Bit 0) */
|
|
|
+ #define R_IWDT_IWDTRR_IWDTRR_Msk (0xffUL) /*!< IWDTRR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== IWDTCR ========================================================= */
|
|
|
+ #define R_IWDT_IWDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */
|
|
|
+ #define R_IWDT_IWDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_IWDT_IWDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */
|
|
|
+ #define R_IWDT_IWDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_IWDT_IWDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */
|
|
|
+ #define R_IWDT_IWDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_IWDT_IWDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */
|
|
|
+ #define R_IWDT_IWDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */
|
|
|
+/* ======================================================== IWDTSR ========================================================= */
|
|
|
+ #define R_IWDT_IWDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */
|
|
|
+ #define R_IWDT_IWDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IWDT_IWDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */
|
|
|
+ #define R_IWDT_IWDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_IWDT_IWDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */
|
|
|
+ #define R_IWDT_IWDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */
|
|
|
+/* ======================================================== IWDTRCR ======================================================== */
|
|
|
+ #define R_IWDT_IWDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */
|
|
|
+ #define R_IWDT_IWDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= IWDTCSTPR ======================================================= */
|
|
|
+ #define R_IWDT_IWDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */
|
|
|
+ #define R_IWDT_IWDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_I3C0 ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================= PRTS ========================================================== */
|
|
|
+ #define R_I3C0_PRTS_PRTMD_Pos (0UL) /*!< PRTMD (Bit 0) */
|
|
|
+ #define R_I3C0_PRTS_PRTMD_Msk (0x1UL) /*!< PRTMD (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= CECTL ========================================================= */
|
|
|
+ #define R_I3C0_CECTL_CLKE_Pos (0UL) /*!< CLKE (Bit 0) */
|
|
|
+ #define R_I3C0_CECTL_CLKE_Msk (0x1UL) /*!< CLKE (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= BCTL ========================================================== */
|
|
|
+ #define R_I3C0_BCTL_INCBA_Pos (0UL) /*!< INCBA (Bit 0) */
|
|
|
+ #define R_I3C0_BCTL_INCBA_Msk (0x1UL) /*!< INCBA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_BCTL_BMDS_Pos (7UL) /*!< BMDS (Bit 7) */
|
|
|
+ #define R_I3C0_BCTL_BMDS_Msk (0x80UL) /*!< BMDS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_BCTL_HJACKCTL_Pos (8UL) /*!< HJACKCTL (Bit 8) */
|
|
|
+ #define R_I3C0_BCTL_HJACKCTL_Msk (0x100UL) /*!< HJACKCTL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_BCTL_ABT_Pos (29UL) /*!< ABT (Bit 29) */
|
|
|
+ #define R_I3C0_BCTL_ABT_Msk (0x20000000UL) /*!< ABT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_BCTL_RSM_Pos (30UL) /*!< RSM (Bit 30) */
|
|
|
+ #define R_I3C0_BCTL_RSM_Msk (0x40000000UL) /*!< RSM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_BCTL_BUSE_Pos (31UL) /*!< BUSE (Bit 31) */
|
|
|
+ #define R_I3C0_BCTL_BUSE_Msk (0x80000000UL) /*!< BUSE (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== MSDVAD ========================================================= */
|
|
|
+ #define R_I3C0_MSDVAD_MDYAD_Pos (16UL) /*!< MDYAD (Bit 16) */
|
|
|
+ #define R_I3C0_MSDVAD_MDYAD_Msk (0x7f0000UL) /*!< MDYAD (Bitfield-Mask: 0x7f) */
|
|
|
+ #define R_I3C0_MSDVAD_MDYADV_Pos (31UL) /*!< MDYADV (Bit 31) */
|
|
|
+ #define R_I3C0_MSDVAD_MDYADV_Msk (0x80000000UL) /*!< MDYADV (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== RSTCTL ========================================================= */
|
|
|
+ #define R_I3C0_RSTCTL_RI3CRST_Pos (0UL) /*!< RI3CRST (Bit 0) */
|
|
|
+ #define R_I3C0_RSTCTL_RI3CRST_Msk (0x1UL) /*!< RI3CRST (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_RSTCTL_CMDQRST_Pos (1UL) /*!< CMDQRST (Bit 1) */
|
|
|
+ #define R_I3C0_RSTCTL_CMDQRST_Msk (0x2UL) /*!< CMDQRST (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_RSTCTL_RSPQRST_Pos (2UL) /*!< RSPQRST (Bit 2) */
|
|
|
+ #define R_I3C0_RSTCTL_RSPQRST_Msk (0x4UL) /*!< RSPQRST (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_RSTCTL_TDBRST_Pos (3UL) /*!< TDBRST (Bit 3) */
|
|
|
+ #define R_I3C0_RSTCTL_TDBRST_Msk (0x8UL) /*!< TDBRST (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_RSTCTL_RDBRST_Pos (4UL) /*!< RDBRST (Bit 4) */
|
|
|
+ #define R_I3C0_RSTCTL_RDBRST_Msk (0x10UL) /*!< RDBRST (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_RSTCTL_IBIQRST_Pos (5UL) /*!< IBIQRST (Bit 5) */
|
|
|
+ #define R_I3C0_RSTCTL_IBIQRST_Msk (0x20UL) /*!< IBIQRST (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_RSTCTL_RSQRST_Pos (6UL) /*!< RSQRST (Bit 6) */
|
|
|
+ #define R_I3C0_RSTCTL_RSQRST_Msk (0x40UL) /*!< RSQRST (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_RSTCTL_INTLRST_Pos (16UL) /*!< INTLRST (Bit 16) */
|
|
|
+ #define R_I3C0_RSTCTL_INTLRST_Msk (0x10000UL) /*!< INTLRST (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= PRSST ========================================================= */
|
|
|
+ #define R_I3C0_PRSST_CRMS_Pos (2UL) /*!< CRMS (Bit 2) */
|
|
|
+ #define R_I3C0_PRSST_CRMS_Msk (0x4UL) /*!< CRMS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_PRSST_TRMD_Pos (4UL) /*!< TRMD (Bit 4) */
|
|
|
+ #define R_I3C0_PRSST_TRMD_Msk (0x10UL) /*!< TRMD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_PRSST_PRSSTWP_Pos (7UL) /*!< PRSSTWP (Bit 7) */
|
|
|
+ #define R_I3C0_PRSST_PRSSTWP_Msk (0x80UL) /*!< PRSSTWP (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= INST ========================================================== */
|
|
|
+ #define R_I3C0_INST_INEF_Pos (10UL) /*!< INEF (Bit 10) */
|
|
|
+ #define R_I3C0_INST_INEF_Msk (0x400UL) /*!< INEF (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= INSTE ========================================================= */
|
|
|
+ #define R_I3C0_INSTE_INEE_Pos (10UL) /*!< INEE (Bit 10) */
|
|
|
+ #define R_I3C0_INSTE_INEE_Msk (0x400UL) /*!< INEE (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= INIE ========================================================== */
|
|
|
+ #define R_I3C0_INIE_INEIE_Pos (10UL) /*!< INEIE (Bit 10) */
|
|
|
+ #define R_I3C0_INIE_INEIE_Msk (0x400UL) /*!< INEIE (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== INSTFC ========================================================= */
|
|
|
+ #define R_I3C0_INSTFC_INEFC_Pos (10UL) /*!< INEFC (Bit 10) */
|
|
|
+ #define R_I3C0_INSTFC_INEFC_Msk (0x400UL) /*!< INEFC (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= DVCT ========================================================== */
|
|
|
+ #define R_I3C0_DVCT_IDX_Pos (19UL) /*!< IDX (Bit 19) */
|
|
|
+ #define R_I3C0_DVCT_IDX_Msk (0xf80000UL) /*!< IDX (Bitfield-Mask: 0x1f) */
|
|
|
+/* ======================================================== IBINCTL ======================================================== */
|
|
|
+ #define R_I3C0_IBINCTL_NRHJCTL_Pos (0UL) /*!< NRHJCTL (Bit 0) */
|
|
|
+ #define R_I3C0_IBINCTL_NRHJCTL_Msk (0x1UL) /*!< NRHJCTL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_IBINCTL_NRMRCTL_Pos (1UL) /*!< NRMRCTL (Bit 1) */
|
|
|
+ #define R_I3C0_IBINCTL_NRMRCTL_Msk (0x2UL) /*!< NRMRCTL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_IBINCTL_NRSIRCTL_Pos (3UL) /*!< NRSIRCTL (Bit 3) */
|
|
|
+ #define R_I3C0_IBINCTL_NRSIRCTL_Msk (0x8UL) /*!< NRSIRCTL (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= BFCTL ========================================================= */
|
|
|
+ #define R_I3C0_BFCTL_MALE_Pos (0UL) /*!< MALE (Bit 0) */
|
|
|
+ #define R_I3C0_BFCTL_MALE_Msk (0x1UL) /*!< MALE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_BFCTL_NALE_Pos (1UL) /*!< NALE (Bit 1) */
|
|
|
+ #define R_I3C0_BFCTL_NALE_Msk (0x2UL) /*!< NALE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_BFCTL_SALE_Pos (2UL) /*!< SALE (Bit 2) */
|
|
|
+ #define R_I3C0_BFCTL_SALE_Msk (0x4UL) /*!< SALE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_BFCTL_SCSYNE_Pos (8UL) /*!< SCSYNE (Bit 8) */
|
|
|
+ #define R_I3C0_BFCTL_SCSYNE_Msk (0x100UL) /*!< SCSYNE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_BFCTL_SMBS_Pos (12UL) /*!< SMBS (Bit 12) */
|
|
|
+ #define R_I3C0_BFCTL_SMBS_Msk (0x1000UL) /*!< SMBS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_BFCTL_FMPE_Pos (14UL) /*!< FMPE (Bit 14) */
|
|
|
+ #define R_I3C0_BFCTL_FMPE_Msk (0x4000UL) /*!< FMPE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_BFCTL_HSME_Pos (15UL) /*!< HSME (Bit 15) */
|
|
|
+ #define R_I3C0_BFCTL_HSME_Msk (0x8000UL) /*!< HSME (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= SVCTL ========================================================= */
|
|
|
+ #define R_I3C0_SVCTL_GCAE_Pos (0UL) /*!< GCAE (Bit 0) */
|
|
|
+ #define R_I3C0_SVCTL_GCAE_Msk (0x1UL) /*!< GCAE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_SVCTL_HSMCE_Pos (5UL) /*!< HSMCE (Bit 5) */
|
|
|
+ #define R_I3C0_SVCTL_HSMCE_Msk (0x20UL) /*!< HSMCE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_SVCTL_DVIDE_Pos (6UL) /*!< DVIDE (Bit 6) */
|
|
|
+ #define R_I3C0_SVCTL_DVIDE_Msk (0x40UL) /*!< DVIDE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_SVCTL_HOAE_Pos (15UL) /*!< HOAE (Bit 15) */
|
|
|
+ #define R_I3C0_SVCTL_HOAE_Msk (0x8000UL) /*!< HOAE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_SVCTL_SVAEn_Pos (16UL) /*!< SVAEn (Bit 16) */
|
|
|
+ #define R_I3C0_SVCTL_SVAEn_Msk (0x10000UL) /*!< SVAEn (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= REFCKCTL ======================================================== */
|
|
|
+ #define R_I3C0_REFCKCTL_IREFCKS_Pos (0UL) /*!< IREFCKS (Bit 0) */
|
|
|
+ #define R_I3C0_REFCKCTL_IREFCKS_Msk (0x7UL) /*!< IREFCKS (Bitfield-Mask: 0x07) */
|
|
|
+/* ========================================================= STDBR ========================================================= */
|
|
|
+ #define R_I3C0_STDBR_SBRLO_Pos (0UL) /*!< SBRLO (Bit 0) */
|
|
|
+ #define R_I3C0_STDBR_SBRLO_Msk (0xffUL) /*!< SBRLO (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_I3C0_STDBR_SBRHO_Pos (8UL) /*!< SBRHO (Bit 8) */
|
|
|
+ #define R_I3C0_STDBR_SBRHO_Msk (0xff00UL) /*!< SBRHO (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_I3C0_STDBR_SBRLP_Pos (16UL) /*!< SBRLP (Bit 16) */
|
|
|
+ #define R_I3C0_STDBR_SBRLP_Msk (0x3f0000UL) /*!< SBRLP (Bitfield-Mask: 0x3f) */
|
|
|
+ #define R_I3C0_STDBR_SBRHP_Pos (24UL) /*!< SBRHP (Bit 24) */
|
|
|
+ #define R_I3C0_STDBR_SBRHP_Msk (0x3f000000UL) /*!< SBRHP (Bitfield-Mask: 0x3f) */
|
|
|
+ #define R_I3C0_STDBR_DSBRPO_Pos (31UL) /*!< DSBRPO (Bit 31) */
|
|
|
+ #define R_I3C0_STDBR_DSBRPO_Msk (0x80000000UL) /*!< DSBRPO (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= EXTBR ========================================================= */
|
|
|
+ #define R_I3C0_EXTBR_EBRLO_Pos (0UL) /*!< EBRLO (Bit 0) */
|
|
|
+ #define R_I3C0_EXTBR_EBRLO_Msk (0xffUL) /*!< EBRLO (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_I3C0_EXTBR_EBRHO_Pos (8UL) /*!< EBRHO (Bit 8) */
|
|
|
+ #define R_I3C0_EXTBR_EBRHO_Msk (0xff00UL) /*!< EBRHO (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_I3C0_EXTBR_EBRLP_Pos (16UL) /*!< EBRLP (Bit 16) */
|
|
|
+ #define R_I3C0_EXTBR_EBRLP_Msk (0x3f0000UL) /*!< EBRLP (Bitfield-Mask: 0x3f) */
|
|
|
+ #define R_I3C0_EXTBR_EBRHP_Pos (24UL) /*!< EBRHP (Bit 24) */
|
|
|
+ #define R_I3C0_EXTBR_EBRHP_Msk (0x3f000000UL) /*!< EBRHP (Bitfield-Mask: 0x3f) */
|
|
|
+/* ======================================================== BFRECDT ======================================================== */
|
|
|
+ #define R_I3C0_BFRECDT_FRECYC_Pos (0UL) /*!< FRECYC (Bit 0) */
|
|
|
+ #define R_I3C0_BFRECDT_FRECYC_Msk (0x1ffUL) /*!< FRECYC (Bitfield-Mask: 0x1ff) */
|
|
|
+/* ======================================================== BAVLCDT ======================================================== */
|
|
|
+ #define R_I3C0_BAVLCDT_AVLCYC_Pos (0UL) /*!< AVLCYC (Bit 0) */
|
|
|
+ #define R_I3C0_BAVLCDT_AVLCYC_Msk (0x1ffUL) /*!< AVLCYC (Bitfield-Mask: 0x1ff) */
|
|
|
+/* ======================================================== BIDLCDT ======================================================== */
|
|
|
+ #define R_I3C0_BIDLCDT_IDLCYC_Pos (0UL) /*!< IDLCYC (Bit 0) */
|
|
|
+ #define R_I3C0_BIDLCDT_IDLCYC_Msk (0x3ffffUL) /*!< IDLCYC (Bitfield-Mask: 0x3ffff) */
|
|
|
+/* ======================================================== OUTCTL ========================================================= */
|
|
|
+ #define R_I3C0_OUTCTL_SDOC_Pos (0UL) /*!< SDOC (Bit 0) */
|
|
|
+ #define R_I3C0_OUTCTL_SDOC_Msk (0x1UL) /*!< SDOC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_OUTCTL_SCOC_Pos (1UL) /*!< SCOC (Bit 1) */
|
|
|
+ #define R_I3C0_OUTCTL_SCOC_Msk (0x2UL) /*!< SCOC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_OUTCTL_SOCWP_Pos (2UL) /*!< SOCWP (Bit 2) */
|
|
|
+ #define R_I3C0_OUTCTL_SOCWP_Msk (0x4UL) /*!< SOCWP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_OUTCTL_EXCYC_Pos (4UL) /*!< EXCYC (Bit 4) */
|
|
|
+ #define R_I3C0_OUTCTL_EXCYC_Msk (0x10UL) /*!< EXCYC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_OUTCTL_SDOD_Pos (8UL) /*!< SDOD (Bit 8) */
|
|
|
+ #define R_I3C0_OUTCTL_SDOD_Msk (0x700UL) /*!< SDOD (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_I3C0_OUTCTL_SDODCS_Pos (15UL) /*!< SDODCS (Bit 15) */
|
|
|
+ #define R_I3C0_OUTCTL_SDODCS_Msk (0x8000UL) /*!< SDODCS (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= INCTL ========================================================= */
|
|
|
+ #define R_I3C0_INCTL_DNFS_Pos (0UL) /*!< DNFS (Bit 0) */
|
|
|
+ #define R_I3C0_INCTL_DNFS_Msk (0xfUL) /*!< DNFS (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_I3C0_INCTL_DNFE_Pos (4UL) /*!< DNFE (Bit 4) */
|
|
|
+ #define R_I3C0_INCTL_DNFE_Msk (0x10UL) /*!< DNFE (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== TMOCTL ========================================================= */
|
|
|
+ #define R_I3C0_TMOCTL_TODTS_Pos (0UL) /*!< TODTS (Bit 0) */
|
|
|
+ #define R_I3C0_TMOCTL_TODTS_Msk (0x3UL) /*!< TODTS (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_I3C0_TMOCTL_TOLCTL_Pos (4UL) /*!< TOLCTL (Bit 4) */
|
|
|
+ #define R_I3C0_TMOCTL_TOLCTL_Msk (0x10UL) /*!< TOLCTL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_TMOCTL_TOHCTL_Pos (5UL) /*!< TOHCTL (Bit 5) */
|
|
|
+ #define R_I3C0_TMOCTL_TOHCTL_Msk (0x20UL) /*!< TOHCTL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_TMOCTL_TOMDS_Pos (6UL) /*!< TOMDS (Bit 6) */
|
|
|
+ #define R_I3C0_TMOCTL_TOMDS_Msk (0xc0UL) /*!< TOMDS (Bitfield-Mask: 0x03) */
|
|
|
+/* ========================================================= WUCTL ========================================================= */
|
|
|
+ #define R_I3C0_WUCTL_WUACKS_Pos (0UL) /*!< WUACKS (Bit 0) */
|
|
|
+ #define R_I3C0_WUCTL_WUACKS_Msk (0x1UL) /*!< WUACKS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_WUCTL_WUANFS_Pos (4UL) /*!< WUANFS (Bit 4) */
|
|
|
+ #define R_I3C0_WUCTL_WUANFS_Msk (0x10UL) /*!< WUANFS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_WUCTL_WUFSYNE_Pos (6UL) /*!< WUFSYNE (Bit 6) */
|
|
|
+ #define R_I3C0_WUCTL_WUFSYNE_Msk (0x40UL) /*!< WUFSYNE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_WUCTL_WUFE_Pos (7UL) /*!< WUFE (Bit 7) */
|
|
|
+ #define R_I3C0_WUCTL_WUFE_Msk (0x80UL) /*!< WUFE (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== ACKCTL ========================================================= */
|
|
|
+ #define R_I3C0_ACKCTL_ACKR_Pos (0UL) /*!< ACKR (Bit 0) */
|
|
|
+ #define R_I3C0_ACKCTL_ACKR_Msk (0x1UL) /*!< ACKR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_ACKCTL_ACKT_Pos (1UL) /*!< ACKT (Bit 1) */
|
|
|
+ #define R_I3C0_ACKCTL_ACKT_Msk (0x2UL) /*!< ACKT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_ACKCTL_ACKTWP_Pos (2UL) /*!< ACKTWP (Bit 2) */
|
|
|
+ #define R_I3C0_ACKCTL_ACKTWP_Msk (0x4UL) /*!< ACKTWP (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= SCSTRCTL ======================================================== */
|
|
|
+ #define R_I3C0_SCSTRCTL_ACKTWE_Pos (0UL) /*!< ACKTWE (Bit 0) */
|
|
|
+ #define R_I3C0_SCSTRCTL_ACKTWE_Msk (0x1UL) /*!< ACKTWE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_SCSTRCTL_RWE_Pos (1UL) /*!< RWE (Bit 1) */
|
|
|
+ #define R_I3C0_SCSTRCTL_RWE_Msk (0x2UL) /*!< RWE (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= SCSTLCTL ======================================================== */
|
|
|
+ #define R_I3C0_SCSTLCTL_STLCYC_Pos (0UL) /*!< STLCYC (Bit 0) */
|
|
|
+ #define R_I3C0_SCSTLCTL_STLCYC_Msk (0xffffUL) /*!< STLCYC (Bitfield-Mask: 0xffff) */
|
|
|
+ #define R_I3C0_SCSTLCTL_AAPE_Pos (28UL) /*!< AAPE (Bit 28) */
|
|
|
+ #define R_I3C0_SCSTLCTL_AAPE_Msk (0x10000000UL) /*!< AAPE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_SCSTLCTL_TRAPE_Pos (29UL) /*!< TRAPE (Bit 29) */
|
|
|
+ #define R_I3C0_SCSTLCTL_TRAPE_Msk (0x20000000UL) /*!< TRAPE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_SCSTLCTL_PARPE_Pos (30UL) /*!< PARPE (Bit 30) */
|
|
|
+ #define R_I3C0_SCSTLCTL_PARPE_Msk (0x40000000UL) /*!< PARPE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_SCSTLCTL_ACKPE_Pos (31UL) /*!< ACKPE (Bit 31) */
|
|
|
+ #define R_I3C0_SCSTLCTL_ACKPE_Msk (0x80000000UL) /*!< ACKPE (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== SVTDLG0 ======================================================== */
|
|
|
+ #define R_I3C0_SVTDLG0_STDLG_Pos (16UL) /*!< STDLG (Bit 16) */
|
|
|
+ #define R_I3C0_SVTDLG0_STDLG_Msk (0xffff0000UL) /*!< STDLG (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================== CNDCTL ========================================================= */
|
|
|
+ #define R_I3C0_CNDCTL_STCND_Pos (0UL) /*!< STCND (Bit 0) */
|
|
|
+ #define R_I3C0_CNDCTL_STCND_Msk (0x1UL) /*!< STCND (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_CNDCTL_SRCND_Pos (1UL) /*!< SRCND (Bit 1) */
|
|
|
+ #define R_I3C0_CNDCTL_SRCND_Msk (0x2UL) /*!< SRCND (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_CNDCTL_SPCND_Pos (2UL) /*!< SPCND (Bit 2) */
|
|
|
+ #define R_I3C0_CNDCTL_SPCND_Msk (0x4UL) /*!< SPCND (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== NCMDQP ========================================================= */
|
|
|
+/* ======================================================== NRSPQP ========================================================= */
|
|
|
+/* ======================================================== NTDTBP0 ======================================================== */
|
|
|
+/* ======================================================== NIBIQP ========================================================= */
|
|
|
+/* ========================================================= NRSQP ========================================================= */
|
|
|
+/* ======================================================== NQTHCTL ======================================================== */
|
|
|
+ #define R_I3C0_NQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */
|
|
|
+ #define R_I3C0_NQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_I3C0_NQTHCTL_RSPQTH_Pos (8UL) /*!< RSPQTH (Bit 8) */
|
|
|
+ #define R_I3C0_NQTHCTL_RSPQTH_Msk (0xff00UL) /*!< RSPQTH (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_I3C0_NQTHCTL_IBIDSSZ_Pos (16UL) /*!< IBIDSSZ (Bit 16) */
|
|
|
+ #define R_I3C0_NQTHCTL_IBIDSSZ_Msk (0xff0000UL) /*!< IBIDSSZ (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_I3C0_NQTHCTL_IBIQTH_Pos (24UL) /*!< IBIQTH (Bit 24) */
|
|
|
+ #define R_I3C0_NQTHCTL_IBIQTH_Msk (0xff000000UL) /*!< IBIQTH (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= NTBTHCTL0 ======================================================= */
|
|
|
+ #define R_I3C0_NTBTHCTL0_TXDBTH_Pos (0UL) /*!< TXDBTH (Bit 0) */
|
|
|
+ #define R_I3C0_NTBTHCTL0_TXDBTH_Msk (0x7UL) /*!< TXDBTH (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_I3C0_NTBTHCTL0_RXDBTH_Pos (8UL) /*!< RXDBTH (Bit 8) */
|
|
|
+ #define R_I3C0_NTBTHCTL0_RXDBTH_Msk (0x700UL) /*!< RXDBTH (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_I3C0_NTBTHCTL0_TXSTTH_Pos (16UL) /*!< TXSTTH (Bit 16) */
|
|
|
+ #define R_I3C0_NTBTHCTL0_TXSTTH_Msk (0x70000UL) /*!< TXSTTH (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_I3C0_NTBTHCTL0_RXSTTH_Pos (24UL) /*!< RXSTTH (Bit 24) */
|
|
|
+ #define R_I3C0_NTBTHCTL0_RXSTTH_Msk (0x7000000UL) /*!< RXSTTH (Bitfield-Mask: 0x07) */
|
|
|
+/* ======================================================= NRQTHCTL ======================================================== */
|
|
|
+ #define R_I3C0_NRQTHCTL_RSQTH_Pos (0UL) /*!< RSQTH (Bit 0) */
|
|
|
+ #define R_I3C0_NRQTHCTL_RSQTH_Msk (0xffUL) /*!< RSQTH (Bitfield-Mask: 0xff) */
|
|
|
+/* ========================================================== BST ========================================================== */
|
|
|
+ #define R_I3C0_BST_STCNDDF_Pos (0UL) /*!< STCNDDF (Bit 0) */
|
|
|
+ #define R_I3C0_BST_STCNDDF_Msk (0x1UL) /*!< STCNDDF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_BST_SPCNDDF_Pos (1UL) /*!< SPCNDDF (Bit 1) */
|
|
|
+ #define R_I3C0_BST_SPCNDDF_Msk (0x2UL) /*!< SPCNDDF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_BST_HDREXDF_Pos (2UL) /*!< HDREXDF (Bit 2) */
|
|
|
+ #define R_I3C0_BST_HDREXDF_Msk (0x4UL) /*!< HDREXDF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_BST_NACKDF_Pos (4UL) /*!< NACKDF (Bit 4) */
|
|
|
+ #define R_I3C0_BST_NACKDF_Msk (0x10UL) /*!< NACKDF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_BST_TENDF_Pos (8UL) /*!< TENDF (Bit 8) */
|
|
|
+ #define R_I3C0_BST_TENDF_Msk (0x100UL) /*!< TENDF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_BST_ALF_Pos (16UL) /*!< ALF (Bit 16) */
|
|
|
+ #define R_I3C0_BST_ALF_Msk (0x10000UL) /*!< ALF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_BST_TODF_Pos (20UL) /*!< TODF (Bit 20) */
|
|
|
+ #define R_I3C0_BST_TODF_Msk (0x100000UL) /*!< TODF (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= BSTE ========================================================== */
|
|
|
+ #define R_I3C0_BSTE_STCNDDE_Pos (0UL) /*!< STCNDDE (Bit 0) */
|
|
|
+ #define R_I3C0_BSTE_STCNDDE_Msk (0x1UL) /*!< STCNDDE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_BSTE_SPCNDDE_Pos (1UL) /*!< SPCNDDE (Bit 1) */
|
|
|
+ #define R_I3C0_BSTE_SPCNDDE_Msk (0x2UL) /*!< SPCNDDE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_BSTE_HDREXDE_Pos (2UL) /*!< HDREXDE (Bit 2) */
|
|
|
+ #define R_I3C0_BSTE_HDREXDE_Msk (0x4UL) /*!< HDREXDE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_BSTE_NACKDE_Pos (4UL) /*!< NACKDE (Bit 4) */
|
|
|
+ #define R_I3C0_BSTE_NACKDE_Msk (0x10UL) /*!< NACKDE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_BSTE_TENDE_Pos (8UL) /*!< TENDE (Bit 8) */
|
|
|
+ #define R_I3C0_BSTE_TENDE_Msk (0x100UL) /*!< TENDE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_BSTE_ALE_Pos (16UL) /*!< ALE (Bit 16) */
|
|
|
+ #define R_I3C0_BSTE_ALE_Msk (0x10000UL) /*!< ALE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_BSTE_TODE_Pos (20UL) /*!< TODE (Bit 20) */
|
|
|
+ #define R_I3C0_BSTE_TODE_Msk (0x100000UL) /*!< TODE (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================== BIE ========================================================== */
|
|
|
+ #define R_I3C0_BIE_STCNDDIE_Pos (0UL) /*!< STCNDDIE (Bit 0) */
|
|
|
+ #define R_I3C0_BIE_STCNDDIE_Msk (0x1UL) /*!< STCNDDIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_BIE_SPCNDDIE_Pos (1UL) /*!< SPCNDDIE (Bit 1) */
|
|
|
+ #define R_I3C0_BIE_SPCNDDIE_Msk (0x2UL) /*!< SPCNDDIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_BIE_HDREXDIE_Pos (2UL) /*!< HDREXDIE (Bit 2) */
|
|
|
+ #define R_I3C0_BIE_HDREXDIE_Msk (0x4UL) /*!< HDREXDIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_BIE_NACKDIE_Pos (4UL) /*!< NACKDIE (Bit 4) */
|
|
|
+ #define R_I3C0_BIE_NACKDIE_Msk (0x10UL) /*!< NACKDIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_BIE_TENDIE_Pos (8UL) /*!< TENDIE (Bit 8) */
|
|
|
+ #define R_I3C0_BIE_TENDIE_Msk (0x100UL) /*!< TENDIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_BIE_ALIE_Pos (16UL) /*!< ALIE (Bit 16) */
|
|
|
+ #define R_I3C0_BIE_ALIE_Msk (0x10000UL) /*!< ALIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_BIE_TODIE_Pos (20UL) /*!< TODIE (Bit 20) */
|
|
|
+ #define R_I3C0_BIE_TODIE_Msk (0x100000UL) /*!< TODIE (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= BSTFC ========================================================= */
|
|
|
+ #define R_I3C0_BSTFC_STCNDDFC_Pos (0UL) /*!< STCNDDFC (Bit 0) */
|
|
|
+ #define R_I3C0_BSTFC_STCNDDFC_Msk (0x1UL) /*!< STCNDDFC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_BSTFC_SPCNDDFC_Pos (1UL) /*!< SPCNDDFC (Bit 1) */
|
|
|
+ #define R_I3C0_BSTFC_SPCNDDFC_Msk (0x2UL) /*!< SPCNDDFC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_BSTFC_HDREXDFC_Pos (2UL) /*!< HDREXDFC (Bit 2) */
|
|
|
+ #define R_I3C0_BSTFC_HDREXDFC_Msk (0x4UL) /*!< HDREXDFC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_BSTFC_NACKDFC_Pos (4UL) /*!< NACKDFC (Bit 4) */
|
|
|
+ #define R_I3C0_BSTFC_NACKDFC_Msk (0x10UL) /*!< NACKDFC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_BSTFC_TENDFC_Pos (8UL) /*!< TENDFC (Bit 8) */
|
|
|
+ #define R_I3C0_BSTFC_TENDFC_Msk (0x100UL) /*!< TENDFC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_BSTFC_ALFC_Pos (16UL) /*!< ALFC (Bit 16) */
|
|
|
+ #define R_I3C0_BSTFC_ALFC_Msk (0x10000UL) /*!< ALFC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_BSTFC_TODFC_Pos (20UL) /*!< TODFC (Bit 20) */
|
|
|
+ #define R_I3C0_BSTFC_TODFC_Msk (0x100000UL) /*!< TODFC (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= NTST ========================================================== */
|
|
|
+ #define R_I3C0_NTST_TDBEF0_Pos (0UL) /*!< TDBEF0 (Bit 0) */
|
|
|
+ #define R_I3C0_NTST_TDBEF0_Msk (0x1UL) /*!< TDBEF0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_NTST_RDBFF0_Pos (1UL) /*!< RDBFF0 (Bit 1) */
|
|
|
+ #define R_I3C0_NTST_RDBFF0_Msk (0x2UL) /*!< RDBFF0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_NTST_IBIQEFF_Pos (2UL) /*!< IBIQEFF (Bit 2) */
|
|
|
+ #define R_I3C0_NTST_IBIQEFF_Msk (0x4UL) /*!< IBIQEFF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_NTST_CMDQEF_Pos (3UL) /*!< CMDQEF (Bit 3) */
|
|
|
+ #define R_I3C0_NTST_CMDQEF_Msk (0x8UL) /*!< CMDQEF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_NTST_RSPQFF_Pos (4UL) /*!< RSPQFF (Bit 4) */
|
|
|
+ #define R_I3C0_NTST_RSPQFF_Msk (0x10UL) /*!< RSPQFF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_NTST_TABTF_Pos (5UL) /*!< TABTF (Bit 5) */
|
|
|
+ #define R_I3C0_NTST_TABTF_Msk (0x20UL) /*!< TABTF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_NTST_TEF_Pos (9UL) /*!< TEF (Bit 9) */
|
|
|
+ #define R_I3C0_NTST_TEF_Msk (0x200UL) /*!< TEF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_NTST_RSQFF_Pos (20UL) /*!< RSQFF (Bit 20) */
|
|
|
+ #define R_I3C0_NTST_RSQFF_Msk (0x100000UL) /*!< RSQFF (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= NTSTE ========================================================= */
|
|
|
+ #define R_I3C0_NTSTE_TDBEE0_Pos (0UL) /*!< TDBEE0 (Bit 0) */
|
|
|
+ #define R_I3C0_NTSTE_TDBEE0_Msk (0x1UL) /*!< TDBEE0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_NTSTE_RDBFE0_Pos (1UL) /*!< RDBFE0 (Bit 1) */
|
|
|
+ #define R_I3C0_NTSTE_RDBFE0_Msk (0x2UL) /*!< RDBFE0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_NTSTE_IBIQEFE_Pos (2UL) /*!< IBIQEFE (Bit 2) */
|
|
|
+ #define R_I3C0_NTSTE_IBIQEFE_Msk (0x4UL) /*!< IBIQEFE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_NTSTE_CMDQEE_Pos (3UL) /*!< CMDQEE (Bit 3) */
|
|
|
+ #define R_I3C0_NTSTE_CMDQEE_Msk (0x8UL) /*!< CMDQEE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_NTSTE_RSPQFE_Pos (4UL) /*!< RSPQFE (Bit 4) */
|
|
|
+ #define R_I3C0_NTSTE_RSPQFE_Msk (0x10UL) /*!< RSPQFE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_NTSTE_TABTE_Pos (5UL) /*!< TABTE (Bit 5) */
|
|
|
+ #define R_I3C0_NTSTE_TABTE_Msk (0x20UL) /*!< TABTE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_NTSTE_TEE_Pos (9UL) /*!< TEE (Bit 9) */
|
|
|
+ #define R_I3C0_NTSTE_TEE_Msk (0x200UL) /*!< TEE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_NTSTE_RSQFE_Pos (20UL) /*!< RSQFE (Bit 20) */
|
|
|
+ #define R_I3C0_NTSTE_RSQFE_Msk (0x100000UL) /*!< RSQFE (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= NTIE ========================================================== */
|
|
|
+ #define R_I3C0_NTIE_TDBEIE0_Pos (0UL) /*!< TDBEIE0 (Bit 0) */
|
|
|
+ #define R_I3C0_NTIE_TDBEIE0_Msk (0x1UL) /*!< TDBEIE0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_NTIE_RDBFIE0_Pos (1UL) /*!< RDBFIE0 (Bit 1) */
|
|
|
+ #define R_I3C0_NTIE_RDBFIE0_Msk (0x2UL) /*!< RDBFIE0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_NTIE_IBIQEFIE_Pos (2UL) /*!< IBIQEFIE (Bit 2) */
|
|
|
+ #define R_I3C0_NTIE_IBIQEFIE_Msk (0x4UL) /*!< IBIQEFIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_NTIE_CMDQEIE_Pos (3UL) /*!< CMDQEIE (Bit 3) */
|
|
|
+ #define R_I3C0_NTIE_CMDQEIE_Msk (0x8UL) /*!< CMDQEIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_NTIE_RSPQFIE_Pos (4UL) /*!< RSPQFIE (Bit 4) */
|
|
|
+ #define R_I3C0_NTIE_RSPQFIE_Msk (0x10UL) /*!< RSPQFIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_NTIE_TABTIE_Pos (5UL) /*!< TABTIE (Bit 5) */
|
|
|
+ #define R_I3C0_NTIE_TABTIE_Msk (0x20UL) /*!< TABTIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_NTIE_TEIE_Pos (9UL) /*!< TEIE (Bit 9) */
|
|
|
+ #define R_I3C0_NTIE_TEIE_Msk (0x200UL) /*!< TEIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_NTIE_RSQFIE_Pos (20UL) /*!< RSQFIE (Bit 20) */
|
|
|
+ #define R_I3C0_NTIE_RSQFIE_Msk (0x100000UL) /*!< RSQFIE (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== NTSTFC ========================================================= */
|
|
|
+ #define R_I3C0_NTSTFC_TDBEFC0_Pos (0UL) /*!< TDBEFC0 (Bit 0) */
|
|
|
+ #define R_I3C0_NTSTFC_TDBEFC0_Msk (0x1UL) /*!< TDBEFC0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_NTSTFC_RDBFFC0_Pos (1UL) /*!< RDBFFC0 (Bit 1) */
|
|
|
+ #define R_I3C0_NTSTFC_RDBFFC0_Msk (0x2UL) /*!< RDBFFC0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_NTSTFC_IBIQEFFC_Pos (2UL) /*!< IBIQEFFC (Bit 2) */
|
|
|
+ #define R_I3C0_NTSTFC_IBIQEFFC_Msk (0x4UL) /*!< IBIQEFFC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_NTSTFC_CMDQEFC_Pos (3UL) /*!< CMDQEFC (Bit 3) */
|
|
|
+ #define R_I3C0_NTSTFC_CMDQEFC_Msk (0x8UL) /*!< CMDQEFC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_NTSTFC_RSPQFFC_Pos (4UL) /*!< RSPQFFC (Bit 4) */
|
|
|
+ #define R_I3C0_NTSTFC_RSPQFFC_Msk (0x10UL) /*!< RSPQFFC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_NTSTFC_TABTFC_Pos (5UL) /*!< TABTFC (Bit 5) */
|
|
|
+ #define R_I3C0_NTSTFC_TABTFC_Msk (0x20UL) /*!< TABTFC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_NTSTFC_TEFC_Pos (9UL) /*!< TEFC (Bit 9) */
|
|
|
+ #define R_I3C0_NTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_NTSTFC_RSQFFC_Pos (20UL) /*!< RSQFFC (Bit 20) */
|
|
|
+ #define R_I3C0_NTSTFC_RSQFFC_Msk (0x100000UL) /*!< RSQFFC (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= BCST ========================================================== */
|
|
|
+ #define R_I3C0_BCST_BFREF_Pos (0UL) /*!< BFREF (Bit 0) */
|
|
|
+ #define R_I3C0_BCST_BFREF_Msk (0x1UL) /*!< BFREF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_BCST_BAVLF_Pos (1UL) /*!< BAVLF (Bit 1) */
|
|
|
+ #define R_I3C0_BCST_BAVLF_Msk (0x2UL) /*!< BAVLF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_BCST_BIDLF_Pos (2UL) /*!< BIDLF (Bit 2) */
|
|
|
+ #define R_I3C0_BCST_BIDLF_Msk (0x4UL) /*!< BIDLF (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= SVST ========================================================== */
|
|
|
+ #define R_I3C0_SVST_GCAF_Pos (0UL) /*!< GCAF (Bit 0) */
|
|
|
+ #define R_I3C0_SVST_GCAF_Msk (0x1UL) /*!< GCAF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_SVST_HSMCF_Pos (5UL) /*!< HSMCF (Bit 5) */
|
|
|
+ #define R_I3C0_SVST_HSMCF_Msk (0x20UL) /*!< HSMCF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_SVST_DVIDF_Pos (6UL) /*!< DVIDF (Bit 6) */
|
|
|
+ #define R_I3C0_SVST_DVIDF_Msk (0x40UL) /*!< DVIDF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_SVST_HOAF_Pos (15UL) /*!< HOAF (Bit 15) */
|
|
|
+ #define R_I3C0_SVST_HOAF_Msk (0x8000UL) /*!< HOAF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_SVST_SVAFn_Pos (16UL) /*!< SVAFn (Bit 16) */
|
|
|
+ #define R_I3C0_SVST_SVAFn_Msk (0x10000UL) /*!< SVAFn (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= WUST ========================================================== */
|
|
|
+ #define R_I3C0_WUST_WUASYNF_Pos (0UL) /*!< WUASYNF (Bit 0) */
|
|
|
+ #define R_I3C0_WUST_WUASYNF_Msk (0x1UL) /*!< WUASYNF (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== DATBAS0 ======================================================== */
|
|
|
+ #define R_I3C0_DATBAS0_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */
|
|
|
+ #define R_I3C0_DATBAS0_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */
|
|
|
+ #define R_I3C0_DATBAS0_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */
|
|
|
+ #define R_I3C0_DATBAS0_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_DATBAS0_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */
|
|
|
+ #define R_I3C0_DATBAS0_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_DATBAS0_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */
|
|
|
+ #define R_I3C0_DATBAS0_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_DATBAS0_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */
|
|
|
+ #define R_I3C0_DATBAS0_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_DATBAS0_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */
|
|
|
+ #define R_I3C0_DATBAS0_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_I3C0_DATBAS0_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */
|
|
|
+ #define R_I3C0_DATBAS0_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_I3C0_DATBAS0_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */
|
|
|
+ #define R_I3C0_DATBAS0_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== DATBAS1 ======================================================== */
|
|
|
+ #define R_I3C0_DATBAS1_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */
|
|
|
+ #define R_I3C0_DATBAS1_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */
|
|
|
+ #define R_I3C0_DATBAS1_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */
|
|
|
+ #define R_I3C0_DATBAS1_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_DATBAS1_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */
|
|
|
+ #define R_I3C0_DATBAS1_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_DATBAS1_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */
|
|
|
+ #define R_I3C0_DATBAS1_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_DATBAS1_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */
|
|
|
+ #define R_I3C0_DATBAS1_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_DATBAS1_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */
|
|
|
+ #define R_I3C0_DATBAS1_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_I3C0_DATBAS1_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */
|
|
|
+ #define R_I3C0_DATBAS1_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_I3C0_DATBAS1_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */
|
|
|
+ #define R_I3C0_DATBAS1_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== DATBAS2 ======================================================== */
|
|
|
+ #define R_I3C0_DATBAS2_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */
|
|
|
+ #define R_I3C0_DATBAS2_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */
|
|
|
+ #define R_I3C0_DATBAS2_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */
|
|
|
+ #define R_I3C0_DATBAS2_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_DATBAS2_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */
|
|
|
+ #define R_I3C0_DATBAS2_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_DATBAS2_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */
|
|
|
+ #define R_I3C0_DATBAS2_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_DATBAS2_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */
|
|
|
+ #define R_I3C0_DATBAS2_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_DATBAS2_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */
|
|
|
+ #define R_I3C0_DATBAS2_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_I3C0_DATBAS2_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */
|
|
|
+ #define R_I3C0_DATBAS2_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_I3C0_DATBAS2_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */
|
|
|
+ #define R_I3C0_DATBAS2_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== DATBAS3 ======================================================== */
|
|
|
+ #define R_I3C0_DATBAS3_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */
|
|
|
+ #define R_I3C0_DATBAS3_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */
|
|
|
+ #define R_I3C0_DATBAS3_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */
|
|
|
+ #define R_I3C0_DATBAS3_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_DATBAS3_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */
|
|
|
+ #define R_I3C0_DATBAS3_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_DATBAS3_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */
|
|
|
+ #define R_I3C0_DATBAS3_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_DATBAS3_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */
|
|
|
+ #define R_I3C0_DATBAS3_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_DATBAS3_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */
|
|
|
+ #define R_I3C0_DATBAS3_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_I3C0_DATBAS3_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */
|
|
|
+ #define R_I3C0_DATBAS3_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_I3C0_DATBAS3_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */
|
|
|
+ #define R_I3C0_DATBAS3_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= EXDATBAS ======================================================== */
|
|
|
+ #define R_I3C0_EXDATBAS_EDSTAD_Pos (0UL) /*!< EDSTAD (Bit 0) */
|
|
|
+ #define R_I3C0_EXDATBAS_EDSTAD_Msk (0x7fUL) /*!< EDSTAD (Bitfield-Mask: 0x7f) */
|
|
|
+ #define R_I3C0_EXDATBAS_EDDYAD_Pos (16UL) /*!< EDDYAD (Bit 16) */
|
|
|
+ #define R_I3C0_EXDATBAS_EDDYAD_Msk (0xff0000UL) /*!< EDDYAD (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_I3C0_EXDATBAS_EDNACK_Pos (29UL) /*!< EDNACK (Bit 29) */
|
|
|
+ #define R_I3C0_EXDATBAS_EDNACK_Msk (0x60000000UL) /*!< EDNACK (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_I3C0_EXDATBAS_EDTYP_Pos (31UL) /*!< EDTYP (Bit 31) */
|
|
|
+ #define R_I3C0_EXDATBAS_EDTYP_Msk (0x80000000UL) /*!< EDTYP (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= SDATBAS0 ======================================================== */
|
|
|
+ #define R_I3C0_SDATBAS0_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */
|
|
|
+ #define R_I3C0_SDATBAS0_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */
|
|
|
+ #define R_I3C0_SDATBAS0_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */
|
|
|
+ #define R_I3C0_SDATBAS0_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_SDATBAS0_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */
|
|
|
+ #define R_I3C0_SDATBAS0_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_SDATBAS0_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */
|
|
|
+ #define R_I3C0_SDATBAS0_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */
|
|
|
+/* ======================================================= SDATBAS1 ======================================================== */
|
|
|
+ #define R_I3C0_SDATBAS1_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */
|
|
|
+ #define R_I3C0_SDATBAS1_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */
|
|
|
+ #define R_I3C0_SDATBAS1_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */
|
|
|
+ #define R_I3C0_SDATBAS1_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_SDATBAS1_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */
|
|
|
+ #define R_I3C0_SDATBAS1_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_SDATBAS1_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */
|
|
|
+ #define R_I3C0_SDATBAS1_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */
|
|
|
+/* ======================================================= SDATBAS2 ======================================================== */
|
|
|
+ #define R_I3C0_SDATBAS2_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */
|
|
|
+ #define R_I3C0_SDATBAS2_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */
|
|
|
+ #define R_I3C0_SDATBAS2_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */
|
|
|
+ #define R_I3C0_SDATBAS2_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_SDATBAS2_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */
|
|
|
+ #define R_I3C0_SDATBAS2_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_SDATBAS2_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */
|
|
|
+ #define R_I3C0_SDATBAS2_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */
|
|
|
+/* ======================================================== MSDCT0 ========================================================= */
|
|
|
+ #define R_I3C0_MSDCT0_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */
|
|
|
+ #define R_I3C0_MSDCT0_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_MSDCT0_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */
|
|
|
+ #define R_I3C0_MSDCT0_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_MSDCT0_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */
|
|
|
+ #define R_I3C0_MSDCT0_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_MSDCT0_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */
|
|
|
+ #define R_I3C0_MSDCT0_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_MSDCT0_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */
|
|
|
+ #define R_I3C0_MSDCT0_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */
|
|
|
+/* ======================================================== MSDCT1 ========================================================= */
|
|
|
+ #define R_I3C0_MSDCT1_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */
|
|
|
+ #define R_I3C0_MSDCT1_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_MSDCT1_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */
|
|
|
+ #define R_I3C0_MSDCT1_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_MSDCT1_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */
|
|
|
+ #define R_I3C0_MSDCT1_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_MSDCT1_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */
|
|
|
+ #define R_I3C0_MSDCT1_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_MSDCT1_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */
|
|
|
+ #define R_I3C0_MSDCT1_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */
|
|
|
+/* ======================================================== MSDCT2 ========================================================= */
|
|
|
+ #define R_I3C0_MSDCT2_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */
|
|
|
+ #define R_I3C0_MSDCT2_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_MSDCT2_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */
|
|
|
+ #define R_I3C0_MSDCT2_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_MSDCT2_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */
|
|
|
+ #define R_I3C0_MSDCT2_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_MSDCT2_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */
|
|
|
+ #define R_I3C0_MSDCT2_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_MSDCT2_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */
|
|
|
+ #define R_I3C0_MSDCT2_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */
|
|
|
+/* ======================================================== MSDCT3 ========================================================= */
|
|
|
+ #define R_I3C0_MSDCT3_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */
|
|
|
+ #define R_I3C0_MSDCT3_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_MSDCT3_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */
|
|
|
+ #define R_I3C0_MSDCT3_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_MSDCT3_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */
|
|
|
+ #define R_I3C0_MSDCT3_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_MSDCT3_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */
|
|
|
+ #define R_I3C0_MSDCT3_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_MSDCT3_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */
|
|
|
+ #define R_I3C0_MSDCT3_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */
|
|
|
+/* ========================================================= SVDCT ========================================================= */
|
|
|
+ #define R_I3C0_SVDCT_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */
|
|
|
+ #define R_I3C0_SVDCT_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_I3C0_SVDCT_TBCR0_Pos (8UL) /*!< TBCR0 (Bit 8) */
|
|
|
+ #define R_I3C0_SVDCT_TBCR0_Msk (0x100UL) /*!< TBCR0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_SVDCT_TBCR1_Pos (9UL) /*!< TBCR1 (Bit 9) */
|
|
|
+ #define R_I3C0_SVDCT_TBCR1_Msk (0x200UL) /*!< TBCR1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_SVDCT_TBCR2_Pos (10UL) /*!< TBCR2 (Bit 10) */
|
|
|
+ #define R_I3C0_SVDCT_TBCR2_Msk (0x400UL) /*!< TBCR2 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_SVDCT_TBCR3_Pos (11UL) /*!< TBCR3 (Bit 11) */
|
|
|
+ #define R_I3C0_SVDCT_TBCR3_Msk (0x800UL) /*!< TBCR3 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_SVDCT_TBCR76_Pos (14UL) /*!< TBCR76 (Bit 14) */
|
|
|
+ #define R_I3C0_SVDCT_TBCR76_Msk (0xc000UL) /*!< TBCR76 (Bitfield-Mask: 0x03) */
|
|
|
+/* ======================================================= SDCTPIDL ======================================================== */
|
|
|
+/* ======================================================= SDCTPIDH ======================================================== */
|
|
|
+/* ======================================================== SVDVAD0 ======================================================== */
|
|
|
+ #define R_I3C0_SVDVAD0_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */
|
|
|
+ #define R_I3C0_SVDVAD0_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */
|
|
|
+ #define R_I3C0_SVDVAD0_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */
|
|
|
+ #define R_I3C0_SVDVAD0_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_SVDVAD0_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */
|
|
|
+ #define R_I3C0_SVDVAD0_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_SVDVAD0_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */
|
|
|
+ #define R_I3C0_SVDVAD0_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== CSECMD ========================================================= */
|
|
|
+ #define R_I3C0_CSECMD_SVIRQE_Pos (0UL) /*!< SVIRQE (Bit 0) */
|
|
|
+ #define R_I3C0_CSECMD_SVIRQE_Msk (0x1UL) /*!< SVIRQE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_CSECMD_MSRQE_Pos (1UL) /*!< MSRQE (Bit 1) */
|
|
|
+ #define R_I3C0_CSECMD_MSRQE_Msk (0x2UL) /*!< MSRQE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_CSECMD_HJEVE_Pos (3UL) /*!< HJEVE (Bit 3) */
|
|
|
+ #define R_I3C0_CSECMD_HJEVE_Msk (0x8UL) /*!< HJEVE (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== CEACTST ======================================================== */
|
|
|
+ #define R_I3C0_CEACTST_ACTST_Pos (0UL) /*!< ACTST (Bit 0) */
|
|
|
+ #define R_I3C0_CEACTST_ACTST_Msk (0xfUL) /*!< ACTST (Bitfield-Mask: 0x0f) */
|
|
|
+/* ========================================================= CMWLG ========================================================= */
|
|
|
+ #define R_I3C0_CMWLG_MWLG_Pos (0UL) /*!< MWLG (Bit 0) */
|
|
|
+ #define R_I3C0_CMWLG_MWLG_Msk (0xffffUL) /*!< MWLG (Bitfield-Mask: 0xffff) */
|
|
|
+/* ========================================================= CMRLG ========================================================= */
|
|
|
+ #define R_I3C0_CMRLG_MRLG_Pos (0UL) /*!< MRLG (Bit 0) */
|
|
|
+ #define R_I3C0_CMRLG_MRLG_Msk (0xffffUL) /*!< MRLG (Bitfield-Mask: 0xffff) */
|
|
|
+ #define R_I3C0_CMRLG_IBIPSZ_Pos (16UL) /*!< IBIPSZ (Bit 16) */
|
|
|
+ #define R_I3C0_CMRLG_IBIPSZ_Msk (0xff0000UL) /*!< IBIPSZ (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== CETSTMD ======================================================== */
|
|
|
+ #define R_I3C0_CETSTMD_TSTMD_Pos (0UL) /*!< TSTMD (Bit 0) */
|
|
|
+ #define R_I3C0_CETSTMD_TSTMD_Msk (0xffUL) /*!< TSTMD (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== CGDVST ========================================================= */
|
|
|
+ #define R_I3C0_CGDVST_PNDINT_Pos (0UL) /*!< PNDINT (Bit 0) */
|
|
|
+ #define R_I3C0_CGDVST_PNDINT_Msk (0xfUL) /*!< PNDINT (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_I3C0_CGDVST_PRTE_Pos (5UL) /*!< PRTE (Bit 5) */
|
|
|
+ #define R_I3C0_CGDVST_PRTE_Msk (0x20UL) /*!< PRTE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_CGDVST_ACTMD_Pos (6UL) /*!< ACTMD (Bit 6) */
|
|
|
+ #define R_I3C0_CGDVST_ACTMD_Msk (0xc0UL) /*!< ACTMD (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_I3C0_CGDVST_VDRSV_Pos (8UL) /*!< VDRSV (Bit 8) */
|
|
|
+ #define R_I3C0_CGDVST_VDRSV_Msk (0xff00UL) /*!< VDRSV (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== CMDSPW ========================================================= */
|
|
|
+ #define R_I3C0_CMDSPW_MSWDR_Pos (0UL) /*!< MSWDR (Bit 0) */
|
|
|
+ #define R_I3C0_CMDSPW_MSWDR_Msk (0x7UL) /*!< MSWDR (Bitfield-Mask: 0x07) */
|
|
|
+/* ======================================================== CMDSPR ========================================================= */
|
|
|
+ #define R_I3C0_CMDSPR_MSRDR_Pos (0UL) /*!< MSRDR (Bit 0) */
|
|
|
+ #define R_I3C0_CMDSPR_MSRDR_Msk (0x7UL) /*!< MSRDR (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_I3C0_CMDSPR_CDTTIM_Pos (3UL) /*!< CDTTIM (Bit 3) */
|
|
|
+ #define R_I3C0_CMDSPR_CDTTIM_Msk (0x38UL) /*!< CDTTIM (Bitfield-Mask: 0x07) */
|
|
|
+/* ======================================================== CMDSPT ========================================================= */
|
|
|
+ #define R_I3C0_CMDSPT_MRTTIM_Pos (0UL) /*!< MRTTIM (Bit 0) */
|
|
|
+ #define R_I3C0_CMDSPT_MRTTIM_Msk (0xffffffUL) /*!< MRTTIM (Bitfield-Mask: 0xffffff) */
|
|
|
+ #define R_I3C0_CMDSPT_MRTE_Pos (31UL) /*!< MRTE (Bit 31) */
|
|
|
+ #define R_I3C0_CMDSPT_MRTE_Msk (0x80000000UL) /*!< MRTE (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= CETSM ========================================================= */
|
|
|
+ #define R_I3C0_CETSM_FREQ_Pos (8UL) /*!< FREQ (Bit 8) */
|
|
|
+ #define R_I3C0_CETSM_FREQ_Msk (0xff00UL) /*!< FREQ (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_I3C0_CETSM_INAC_Pos (16UL) /*!< INAC (Bit 16) */
|
|
|
+ #define R_I3C0_CETSM_INAC_Msk (0xff0000UL) /*!< INAC (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== BITCNT ========================================================= */
|
|
|
+ #define R_I3C0_BITCNT_BCNT_Pos (0UL) /*!< BCNT (Bit 0) */
|
|
|
+ #define R_I3C0_BITCNT_BCNT_Msk (0x1fUL) /*!< BCNT (Bitfield-Mask: 0x1f) */
|
|
|
+ #define R_I3C0_BITCNT_BCNTWP_Pos (7UL) /*!< BCNTWP (Bit 7) */
|
|
|
+ #define R_I3C0_BITCNT_BCNTWP_Msk (0x80UL) /*!< BCNTWP (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== NQSTLV ========================================================= */
|
|
|
+ #define R_I3C0_NQSTLV_CMDQFLV_Pos (0UL) /*!< CMDQFLV (Bit 0) */
|
|
|
+ #define R_I3C0_NQSTLV_CMDQFLV_Msk (0xffUL) /*!< CMDQFLV (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_I3C0_NQSTLV_RSPQLV_Pos (8UL) /*!< RSPQLV (Bit 8) */
|
|
|
+ #define R_I3C0_NQSTLV_RSPQLV_Msk (0xff00UL) /*!< RSPQLV (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_I3C0_NQSTLV_IBIQLV_Pos (16UL) /*!< IBIQLV (Bit 16) */
|
|
|
+ #define R_I3C0_NQSTLV_IBIQLV_Msk (0xff0000UL) /*!< IBIQLV (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_I3C0_NQSTLV_IBISCNT_Pos (24UL) /*!< IBISCNT (Bit 24) */
|
|
|
+ #define R_I3C0_NQSTLV_IBISCNT_Msk (0x1f000000UL) /*!< IBISCNT (Bitfield-Mask: 0x1f) */
|
|
|
+/* ======================================================= NDBSTLV0 ======================================================== */
|
|
|
+ #define R_I3C0_NDBSTLV0_TDBFLV_Pos (0UL) /*!< TDBFLV (Bit 0) */
|
|
|
+ #define R_I3C0_NDBSTLV0_TDBFLV_Msk (0xffUL) /*!< TDBFLV (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_I3C0_NDBSTLV0_RDBLV_Pos (8UL) /*!< RDBLV (Bit 8) */
|
|
|
+ #define R_I3C0_NDBSTLV0_RDBLV_Msk (0xff00UL) /*!< RDBLV (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= NRSQSTLV ======================================================== */
|
|
|
+ #define R_I3C0_NRSQSTLV_RSQLV_Pos (0UL) /*!< RSQLV (Bit 0) */
|
|
|
+ #define R_I3C0_NRSQSTLV_RSQLV_Msk (0xffUL) /*!< RSQLV (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== PRSTDBG ======================================================== */
|
|
|
+ #define R_I3C0_PRSTDBG_SCILV_Pos (0UL) /*!< SCILV (Bit 0) */
|
|
|
+ #define R_I3C0_PRSTDBG_SCILV_Msk (0x1UL) /*!< SCILV (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_PRSTDBG_SDILV_Pos (1UL) /*!< SDILV (Bit 1) */
|
|
|
+ #define R_I3C0_PRSTDBG_SDILV_Msk (0x2UL) /*!< SDILV (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_PRSTDBG_SCOLV_Pos (2UL) /*!< SCOLV (Bit 2) */
|
|
|
+ #define R_I3C0_PRSTDBG_SCOLV_Msk (0x4UL) /*!< SCOLV (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_I3C0_PRSTDBG_SDOLV_Pos (3UL) /*!< SDOLV (Bit 3) */
|
|
|
+ #define R_I3C0_PRSTDBG_SDOLV_Msk (0x8UL) /*!< SDOLV (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= MSERRCNT ======================================================== */
|
|
|
+ #define R_I3C0_MSERRCNT_M2ECNT_Pos (0UL) /*!< M2ECNT (Bit 0) */
|
|
|
+ #define R_I3C0_MSERRCNT_M2ECNT_Msk (0xffUL) /*!< M2ECNT (Bitfield-Mask: 0xff) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_MPU_MMPU ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================== OAD ========================================================== */
|
|
|
+ #define R_MPU_MMPU_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */
|
|
|
+ #define R_MPU_MMPU_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_MPU_MMPU_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */
|
|
|
+ #define R_MPU_MMPU_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= OADPT ========================================================= */
|
|
|
+ #define R_MPU_MMPU_OADPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */
|
|
|
+ #define R_MPU_MMPU_OADPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_MPU_MMPU_OADPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */
|
|
|
+ #define R_MPU_MMPU_OADPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_MPU_SPMON ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_MSTP ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ======================================================== MSTPCRA ======================================================== */
|
|
|
+ #define R_MSTP_MSTPCRA_MSTPA_Pos (0UL) /*!< MSTPA (Bit 0) */
|
|
|
+ #define R_MSTP_MSTPCRA_MSTPA_Msk (0x1UL) /*!< MSTPA (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== MSTPCRB ======================================================== */
|
|
|
+ #define R_MSTP_MSTPCRB_MSTPB_Pos (0UL) /*!< MSTPB (Bit 0) */
|
|
|
+ #define R_MSTP_MSTPCRB_MSTPB_Msk (0x1UL) /*!< MSTPB (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== MSTPCRC ======================================================== */
|
|
|
+ #define R_MSTP_MSTPCRC_MSTPC_Pos (0UL) /*!< MSTPC (Bit 0) */
|
|
|
+ #define R_MSTP_MSTPCRC_MSTPC_Msk (0x1UL) /*!< MSTPC (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== MSTPCRD ======================================================== */
|
|
|
+ #define R_MSTP_MSTPCRD_MSTPD_Pos (0UL) /*!< MSTPD (Bit 0) */
|
|
|
+ #define R_MSTP_MSTPCRD_MSTPD_Msk (0x1UL) /*!< MSTPD (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== MSTPCRE ======================================================== */
|
|
|
+ #define R_MSTP_MSTPCRE_MSTPE_Pos (0UL) /*!< MSTPE (Bit 0) */
|
|
|
+ #define R_MSTP_MSTPCRE_MSTPE_Msk (0x1UL) /*!< MSTPE (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= LSMRWDIS ======================================================== */
|
|
|
+ #define R_MSTP_LSMRWDIS_RTCRWDIS_Pos (0UL) /*!< RTCRWDIS (Bit 0) */
|
|
|
+ #define R_MSTP_LSMRWDIS_RTCRWDIS_Msk (0x1UL) /*!< RTCRWDIS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_MSTP_LSMRWDIS_WDTDIS_Pos (1UL) /*!< WDTDIS (Bit 1) */
|
|
|
+ #define R_MSTP_LSMRWDIS_WDTDIS_Msk (0x2UL) /*!< WDTDIS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_MSTP_LSMRWDIS_IWDTIDS_Pos (2UL) /*!< IWDTIDS (Bit 2) */
|
|
|
+ #define R_MSTP_LSMRWDIS_IWDTIDS_Msk (0x4UL) /*!< IWDTIDS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_MSTP_LSMRWDIS_WREN_Pos (7UL) /*!< WREN (Bit 7) */
|
|
|
+ #define R_MSTP_LSMRWDIS_WREN_Msk (0x80UL) /*!< WREN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_MSTP_LSMRWDIS_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */
|
|
|
+ #define R_MSTP_LSMRWDIS_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_PORT0 ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ======================================================== PCNTR1 ========================================================= */
|
|
|
+ #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */
|
|
|
+ #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */
|
|
|
+ #define R_PORT0_PCNTR1_PDR_Pos (0UL) /*!< PDR (Bit 0) */
|
|
|
+ #define R_PORT0_PCNTR1_PDR_Msk (0xffffUL) /*!< PDR (Bitfield-Mask: 0xffff) */
|
|
|
+/* ========================================================== PDR ========================================================== */
|
|
|
+ #define R_PORT0_PDR_PDR_Pos (0UL) /*!< PDR (Bit 0) */
|
|
|
+ #define R_PORT0_PDR_PDR_Msk (0x1UL) /*!< PDR (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= PODR ========================================================== */
|
|
|
+ #define R_PORT0_PODR_PODR_Pos (0UL) /*!< PODR (Bit 0) */
|
|
|
+ #define R_PORT0_PODR_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== PCNTR2 ========================================================= */
|
|
|
+ #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */
|
|
|
+ #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */
|
|
|
+ #define R_PORT0_PCNTR2_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */
|
|
|
+ #define R_PORT0_PCNTR2_PIDR_Msk (0xffffUL) /*!< PIDR (Bitfield-Mask: 0xffff) */
|
|
|
+/* ========================================================= PIDR ========================================================== */
|
|
|
+ #define R_PORT0_PIDR_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */
|
|
|
+ #define R_PORT0_PIDR_PIDR_Msk (0x1UL) /*!< PIDR (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= EIDR ========================================================== */
|
|
|
+ #define R_PORT0_EIDR_EIDR_Pos (0UL) /*!< EIDR (Bit 0) */
|
|
|
+ #define R_PORT0_EIDR_EIDR_Msk (0x1UL) /*!< EIDR (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== PCNTR3 ========================================================= */
|
|
|
+ #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */
|
|
|
+ #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */
|
|
|
+ #define R_PORT0_PCNTR3_POSR_Pos (0UL) /*!< POSR (Bit 0) */
|
|
|
+ #define R_PORT0_PCNTR3_POSR_Msk (0xffffUL) /*!< POSR (Bitfield-Mask: 0xffff) */
|
|
|
+/* ========================================================= POSR ========================================================== */
|
|
|
+ #define R_PORT0_POSR_POSR_Pos (0UL) /*!< POSR (Bit 0) */
|
|
|
+ #define R_PORT0_POSR_POSR_Msk (0x1UL) /*!< POSR (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= PORR ========================================================== */
|
|
|
+ #define R_PORT0_PORR_PORR_Pos (0UL) /*!< PORR (Bit 0) */
|
|
|
+ #define R_PORT0_PORR_PORR_Msk (0x1UL) /*!< PORR (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== PCNTR4 ========================================================= */
|
|
|
+ #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */
|
|
|
+ #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */
|
|
|
+ #define R_PORT0_PCNTR4_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */
|
|
|
+ #define R_PORT0_PCNTR4_EOSR_Msk (0xffffUL) /*!< EOSR (Bitfield-Mask: 0xffff) */
|
|
|
+/* ========================================================= EOSR ========================================================== */
|
|
|
+ #define R_PORT0_EOSR_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */
|
|
|
+ #define R_PORT0_EOSR_EOSR_Msk (0x1UL) /*!< EOSR (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= EORR ========================================================== */
|
|
|
+ #define R_PORT0_EORR_EORR_Pos (0UL) /*!< EORR (Bit 0) */
|
|
|
+ #define R_PORT0_EORR_EORR_Msk (0x1UL) /*!< EORR (Bitfield-Mask: 0x01) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_PFS ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_PMISC ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ======================================================== PFENET ========================================================= */
|
|
|
+ #define R_PMISC_PFENET_PHYMODE0_Pos (4UL) /*!< PHYMODE0 (Bit 4) */
|
|
|
+ #define R_PMISC_PFENET_PHYMODE0_Msk (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= PWPR ========================================================== */
|
|
|
+ #define R_PMISC_PWPR_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */
|
|
|
+ #define R_PMISC_PWPR_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PMISC_PWPR_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */
|
|
|
+ #define R_PMISC_PWPR_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= PWPRS ========================================================= */
|
|
|
+ #define R_PMISC_PWPRS_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */
|
|
|
+ #define R_PMISC_PWPRS_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_PMISC_PWPRS_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */
|
|
|
+ #define R_PMISC_PWPRS_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_RTC ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ======================================================== R64CNT ========================================================= */
|
|
|
+ #define R_RTC_R64CNT_F1HZ_Pos (6UL) /*!< F1HZ (Bit 6) */
|
|
|
+ #define R_RTC_R64CNT_F1HZ_Msk (0x40UL) /*!< F1HZ (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_RTC_R64CNT_F2HZ_Pos (5UL) /*!< F2HZ (Bit 5) */
|
|
|
+ #define R_RTC_R64CNT_F2HZ_Msk (0x20UL) /*!< F2HZ (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_RTC_R64CNT_F4HZ_Pos (4UL) /*!< F4HZ (Bit 4) */
|
|
|
+ #define R_RTC_R64CNT_F4HZ_Msk (0x10UL) /*!< F4HZ (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_RTC_R64CNT_F8HZ_Pos (3UL) /*!< F8HZ (Bit 3) */
|
|
|
+ #define R_RTC_R64CNT_F8HZ_Msk (0x8UL) /*!< F8HZ (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_RTC_R64CNT_F16HZ_Pos (2UL) /*!< F16HZ (Bit 2) */
|
|
|
+ #define R_RTC_R64CNT_F16HZ_Msk (0x4UL) /*!< F16HZ (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_RTC_R64CNT_F32HZ_Pos (1UL) /*!< F32HZ (Bit 1) */
|
|
|
+ #define R_RTC_R64CNT_F32HZ_Msk (0x2UL) /*!< F32HZ (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_RTC_R64CNT_F64HZ_Pos (0UL) /*!< F64HZ (Bit 0) */
|
|
|
+ #define R_RTC_R64CNT_F64HZ_Msk (0x1UL) /*!< F64HZ (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= BCNT0 ========================================================= */
|
|
|
+ #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */
|
|
|
+ #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== RSECCNT ======================================================== */
|
|
|
+ #define R_RTC_RSECCNT_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */
|
|
|
+ #define R_RTC_RSECCNT_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_RTC_RSECCNT_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */
|
|
|
+ #define R_RTC_RSECCNT_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */
|
|
|
+/* ========================================================= BCNT1 ========================================================= */
|
|
|
+ #define R_RTC_BCNT1_BCNT1_Pos (0UL) /*!< BCNT1 (Bit 0) */
|
|
|
+ #define R_RTC_BCNT1_BCNT1_Msk (0xffUL) /*!< BCNT1 (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== RMINCNT ======================================================== */
|
|
|
+ #define R_RTC_RMINCNT_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */
|
|
|
+ #define R_RTC_RMINCNT_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_RTC_RMINCNT_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */
|
|
|
+ #define R_RTC_RMINCNT_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */
|
|
|
+/* ========================================================= BCNT2 ========================================================= */
|
|
|
+ #define R_RTC_BCNT2_BCNT2_Pos (0UL) /*!< BCNT2 (Bit 0) */
|
|
|
+ #define R_RTC_BCNT2_BCNT2_Msk (0xffUL) /*!< BCNT2 (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== RHRCNT ========================================================= */
|
|
|
+ #define R_RTC_RHRCNT_PM_Pos (6UL) /*!< PM (Bit 6) */
|
|
|
+ #define R_RTC_RHRCNT_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_RTC_RHRCNT_HR10_Pos (4UL) /*!< HR10 (Bit 4) */
|
|
|
+ #define R_RTC_RHRCNT_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_RTC_RHRCNT_HR1_Pos (0UL) /*!< HR1 (Bit 0) */
|
|
|
+ #define R_RTC_RHRCNT_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */
|
|
|
+/* ========================================================= BCNT3 ========================================================= */
|
|
|
+ #define R_RTC_BCNT3_BCNT3_Pos (0UL) /*!< BCNT3 (Bit 0) */
|
|
|
+ #define R_RTC_BCNT3_BCNT3_Msk (0xffUL) /*!< BCNT3 (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== RWKCNT ========================================================= */
|
|
|
+ #define R_RTC_RWKCNT_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */
|
|
|
+ #define R_RTC_RWKCNT_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */
|
|
|
+/* ======================================================== RDAYCNT ======================================================== */
|
|
|
+ #define R_RTC_RDAYCNT_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */
|
|
|
+ #define R_RTC_RDAYCNT_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_RTC_RDAYCNT_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */
|
|
|
+ #define R_RTC_RDAYCNT_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */
|
|
|
+/* ======================================================== RMONCNT ======================================================== */
|
|
|
+ #define R_RTC_RMONCNT_MON10_Pos (4UL) /*!< MON10 (Bit 4) */
|
|
|
+ #define R_RTC_RMONCNT_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_RTC_RMONCNT_MON1_Pos (0UL) /*!< MON1 (Bit 0) */
|
|
|
+ #define R_RTC_RMONCNT_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */
|
|
|
+/* ======================================================== RYRCNT ========================================================= */
|
|
|
+ #define R_RTC_RYRCNT_YR10_Pos (4UL) /*!< YR10 (Bit 4) */
|
|
|
+ #define R_RTC_RYRCNT_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_RTC_RYRCNT_YR1_Pos (0UL) /*!< YR1 (Bit 0) */
|
|
|
+ #define R_RTC_RYRCNT_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */
|
|
|
+/* ======================================================== BCNT0AR ======================================================== */
|
|
|
+ #define R_RTC_BCNT0AR_BCNT0AR_Pos (0UL) /*!< BCNT0AR (Bit 0) */
|
|
|
+ #define R_RTC_BCNT0AR_BCNT0AR_Msk (0xffUL) /*!< BCNT0AR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== RSECAR ========================================================= */
|
|
|
+ #define R_RTC_RSECAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */
|
|
|
+ #define R_RTC_RSECAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_RTC_RSECAR_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */
|
|
|
+ #define R_RTC_RSECAR_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_RTC_RSECAR_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */
|
|
|
+ #define R_RTC_RSECAR_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */
|
|
|
+/* ======================================================== BCNT1AR ======================================================== */
|
|
|
+ #define R_RTC_BCNT1AR_BCNT1AR_Pos (0UL) /*!< BCNT1AR (Bit 0) */
|
|
|
+ #define R_RTC_BCNT1AR_BCNT1AR_Msk (0xffUL) /*!< BCNT1AR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== RMINAR ========================================================= */
|
|
|
+ #define R_RTC_RMINAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */
|
|
|
+ #define R_RTC_RMINAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_RTC_RMINAR_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */
|
|
|
+ #define R_RTC_RMINAR_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_RTC_RMINAR_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */
|
|
|
+ #define R_RTC_RMINAR_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */
|
|
|
+/* ======================================================== BCNT2AR ======================================================== */
|
|
|
+ #define R_RTC_BCNT2AR_BCNT2AR_Pos (0UL) /*!< BCNT2AR (Bit 0) */
|
|
|
+ #define R_RTC_BCNT2AR_BCNT2AR_Msk (0xffUL) /*!< BCNT2AR (Bitfield-Mask: 0xff) */
|
|
|
+/* ========================================================= RHRAR ========================================================= */
|
|
|
+ #define R_RTC_RHRAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */
|
|
|
+ #define R_RTC_RHRAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_RTC_RHRAR_PM_Pos (6UL) /*!< PM (Bit 6) */
|
|
|
+ #define R_RTC_RHRAR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_RTC_RHRAR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */
|
|
|
+ #define R_RTC_RHRAR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_RTC_RHRAR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */
|
|
|
+ #define R_RTC_RHRAR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */
|
|
|
+/* ======================================================== BCNT3AR ======================================================== */
|
|
|
+ #define R_RTC_BCNT3AR_BCNT3AR_Pos (0UL) /*!< BCNT3AR (Bit 0) */
|
|
|
+ #define R_RTC_BCNT3AR_BCNT3AR_Msk (0xffUL) /*!< BCNT3AR (Bitfield-Mask: 0xff) */
|
|
|
+/* ========================================================= RWKAR ========================================================= */
|
|
|
+ #define R_RTC_RWKAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */
|
|
|
+ #define R_RTC_RWKAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_RTC_RWKAR_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */
|
|
|
+ #define R_RTC_RWKAR_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */
|
|
|
+/* ======================================================= BCNT0AER ======================================================== */
|
|
|
+ #define R_RTC_BCNT0AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */
|
|
|
+ #define R_RTC_BCNT0AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== RDAYAR ========================================================= */
|
|
|
+ #define R_RTC_RDAYAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */
|
|
|
+ #define R_RTC_RDAYAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_RTC_RDAYAR_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */
|
|
|
+ #define R_RTC_RDAYAR_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_RTC_RDAYAR_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */
|
|
|
+ #define R_RTC_RDAYAR_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */
|
|
|
+/* ======================================================= BCNT1AER ======================================================== */
|
|
|
+ #define R_RTC_BCNT1AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */
|
|
|
+ #define R_RTC_BCNT1AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== RMONAR ========================================================= */
|
|
|
+ #define R_RTC_RMONAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */
|
|
|
+ #define R_RTC_RMONAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_RTC_RMONAR_MON10_Pos (4UL) /*!< MON10 (Bit 4) */
|
|
|
+ #define R_RTC_RMONAR_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_RTC_RMONAR_MON1_Pos (0UL) /*!< MON1 (Bit 0) */
|
|
|
+ #define R_RTC_RMONAR_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */
|
|
|
+/* ======================================================= BCNT2AER ======================================================== */
|
|
|
+ #define R_RTC_BCNT2AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */
|
|
|
+ #define R_RTC_BCNT2AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */
|
|
|
+/* ========================================================= RYRAR ========================================================= */
|
|
|
+ #define R_RTC_RYRAR_YR10_Pos (4UL) /*!< YR10 (Bit 4) */
|
|
|
+ #define R_RTC_RYRAR_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_RTC_RYRAR_YR1_Pos (0UL) /*!< YR1 (Bit 0) */
|
|
|
+ #define R_RTC_RYRAR_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */
|
|
|
+/* ======================================================= BCNT3AER ======================================================== */
|
|
|
+ #define R_RTC_BCNT3AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */
|
|
|
+ #define R_RTC_BCNT3AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== RYRAREN ======================================================== */
|
|
|
+ #define R_RTC_RYRAREN_ENB_Pos (7UL) /*!< ENB (Bit 7) */
|
|
|
+ #define R_RTC_RYRAREN_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= RCR1 ========================================================== */
|
|
|
+ #define R_RTC_RCR1_PES_Pos (4UL) /*!< PES (Bit 4) */
|
|
|
+ #define R_RTC_RCR1_PES_Msk (0xf0UL) /*!< PES (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_RTC_RCR1_RTCOS_Pos (3UL) /*!< RTCOS (Bit 3) */
|
|
|
+ #define R_RTC_RCR1_RTCOS_Msk (0x8UL) /*!< RTCOS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_RTC_RCR1_PIE_Pos (2UL) /*!< PIE (Bit 2) */
|
|
|
+ #define R_RTC_RCR1_PIE_Msk (0x4UL) /*!< PIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_RTC_RCR1_CIE_Pos (1UL) /*!< CIE (Bit 1) */
|
|
|
+ #define R_RTC_RCR1_CIE_Msk (0x2UL) /*!< CIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_RTC_RCR1_AIE_Pos (0UL) /*!< AIE (Bit 0) */
|
|
|
+ #define R_RTC_RCR1_AIE_Msk (0x1UL) /*!< AIE (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= RCR2 ========================================================== */
|
|
|
+ #define R_RTC_RCR2_CNTMD_Pos (7UL) /*!< CNTMD (Bit 7) */
|
|
|
+ #define R_RTC_RCR2_CNTMD_Msk (0x80UL) /*!< CNTMD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_RTC_RCR2_HR24_Pos (6UL) /*!< HR24 (Bit 6) */
|
|
|
+ #define R_RTC_RCR2_HR24_Msk (0x40UL) /*!< HR24 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_RTC_RCR2_AADJP_Pos (5UL) /*!< AADJP (Bit 5) */
|
|
|
+ #define R_RTC_RCR2_AADJP_Msk (0x20UL) /*!< AADJP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_RTC_RCR2_AADJE_Pos (4UL) /*!< AADJE (Bit 4) */
|
|
|
+ #define R_RTC_RCR2_AADJE_Msk (0x10UL) /*!< AADJE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_RTC_RCR2_RTCOE_Pos (3UL) /*!< RTCOE (Bit 3) */
|
|
|
+ #define R_RTC_RCR2_RTCOE_Msk (0x8UL) /*!< RTCOE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_RTC_RCR2_ADJ30_Pos (2UL) /*!< ADJ30 (Bit 2) */
|
|
|
+ #define R_RTC_RCR2_ADJ30_Msk (0x4UL) /*!< ADJ30 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_RTC_RCR2_RESET_Pos (1UL) /*!< RESET (Bit 1) */
|
|
|
+ #define R_RTC_RCR2_RESET_Msk (0x2UL) /*!< RESET (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_RTC_RCR2_START_Pos (0UL) /*!< START (Bit 0) */
|
|
|
+ #define R_RTC_RCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= RCR4 ========================================================== */
|
|
|
+ #define R_RTC_RCR4_RCKSEL_Pos (0UL) /*!< RCKSEL (Bit 0) */
|
|
|
+ #define R_RTC_RCR4_RCKSEL_Msk (0x1UL) /*!< RCKSEL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_RTC_RCR4_ROPSEL_Pos (7UL) /*!< ROPSEL (Bit 7) */
|
|
|
+ #define R_RTC_RCR4_ROPSEL_Msk (0x80UL) /*!< ROPSEL (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= RFRH ========================================================== */
|
|
|
+ #define R_RTC_RFRH_RFC16_Pos (0UL) /*!< RFC16 (Bit 0) */
|
|
|
+ #define R_RTC_RFRH_RFC16_Msk (0x1UL) /*!< RFC16 (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= RFRL ========================================================== */
|
|
|
+ #define R_RTC_RFRL_RFC_Pos (0UL) /*!< RFC (Bit 0) */
|
|
|
+ #define R_RTC_RFRL_RFC_Msk (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff) */
|
|
|
+/* ========================================================= RADJ ========================================================== */
|
|
|
+ #define R_RTC_RADJ_PMADJ_Pos (6UL) /*!< PMADJ (Bit 6) */
|
|
|
+ #define R_RTC_RADJ_PMADJ_Msk (0xc0UL) /*!< PMADJ (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_RTC_RADJ_ADJ_Pos (0UL) /*!< ADJ (Bit 0) */
|
|
|
+ #define R_RTC_RADJ_ADJ_Msk (0x3fUL) /*!< ADJ (Bitfield-Mask: 0x3f) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_SCI0 ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================== SMR ========================================================== */
|
|
|
+ #define R_SCI0_SMR_CM_Pos (7UL) /*!< CM (Bit 7) */
|
|
|
+ #define R_SCI0_SMR_CM_Msk (0x80UL) /*!< CM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SMR_CHR_Pos (6UL) /*!< CHR (Bit 6) */
|
|
|
+ #define R_SCI0_SMR_CHR_Msk (0x40UL) /*!< CHR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SMR_PE_Pos (5UL) /*!< PE (Bit 5) */
|
|
|
+ #define R_SCI0_SMR_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SMR_PM_Pos (4UL) /*!< PM (Bit 4) */
|
|
|
+ #define R_SCI0_SMR_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SMR_STOP_Pos (3UL) /*!< STOP (Bit 3) */
|
|
|
+ #define R_SCI0_SMR_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SMR_MP_Pos (2UL) /*!< MP (Bit 2) */
|
|
|
+ #define R_SCI0_SMR_MP_Msk (0x4UL) /*!< MP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SMR_CKS_Pos (0UL) /*!< CKS (Bit 0) */
|
|
|
+ #define R_SCI0_SMR_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */
|
|
|
+/* ======================================================= SMR_SMCI ======================================================== */
|
|
|
+ #define R_SCI0_SMR_SMCI_GM_Pos (7UL) /*!< GM (Bit 7) */
|
|
|
+ #define R_SCI0_SMR_SMCI_GM_Msk (0x80UL) /*!< GM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SMR_SMCI_BLK_Pos (6UL) /*!< BLK (Bit 6) */
|
|
|
+ #define R_SCI0_SMR_SMCI_BLK_Msk (0x40UL) /*!< BLK (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SMR_SMCI_PE_Pos (5UL) /*!< PE (Bit 5) */
|
|
|
+ #define R_SCI0_SMR_SMCI_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SMR_SMCI_PM_Pos (4UL) /*!< PM (Bit 4) */
|
|
|
+ #define R_SCI0_SMR_SMCI_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SMR_SMCI_BCP_Pos (2UL) /*!< BCP (Bit 2) */
|
|
|
+ #define R_SCI0_SMR_SMCI_BCP_Msk (0xcUL) /*!< BCP (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_SCI0_SMR_SMCI_CKS_Pos (0UL) /*!< CKS (Bit 0) */
|
|
|
+ #define R_SCI0_SMR_SMCI_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */
|
|
|
+/* ========================================================== BRR ========================================================== */
|
|
|
+ #define R_SCI0_BRR_BRR_Pos (0UL) /*!< BRR (Bit 0) */
|
|
|
+ #define R_SCI0_BRR_BRR_Msk (0xffUL) /*!< BRR (Bitfield-Mask: 0xff) */
|
|
|
+/* ========================================================== SCR ========================================================== */
|
|
|
+ #define R_SCI0_SCR_TIE_Pos (7UL) /*!< TIE (Bit 7) */
|
|
|
+ #define R_SCI0_SCR_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SCR_RIE_Pos (6UL) /*!< RIE (Bit 6) */
|
|
|
+ #define R_SCI0_SCR_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SCR_TE_Pos (5UL) /*!< TE (Bit 5) */
|
|
|
+ #define R_SCI0_SCR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SCR_RE_Pos (4UL) /*!< RE (Bit 4) */
|
|
|
+ #define R_SCI0_SCR_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SCR_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */
|
|
|
+ #define R_SCI0_SCR_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SCR_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */
|
|
|
+ #define R_SCI0_SCR_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SCR_CKE_Pos (0UL) /*!< CKE (Bit 0) */
|
|
|
+ #define R_SCI0_SCR_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */
|
|
|
+/* ======================================================= SCR_SMCI ======================================================== */
|
|
|
+ #define R_SCI0_SCR_SMCI_TIE_Pos (7UL) /*!< TIE (Bit 7) */
|
|
|
+ #define R_SCI0_SCR_SMCI_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SCR_SMCI_RIE_Pos (6UL) /*!< RIE (Bit 6) */
|
|
|
+ #define R_SCI0_SCR_SMCI_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SCR_SMCI_TE_Pos (5UL) /*!< TE (Bit 5) */
|
|
|
+ #define R_SCI0_SCR_SMCI_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SCR_SMCI_RE_Pos (4UL) /*!< RE (Bit 4) */
|
|
|
+ #define R_SCI0_SCR_SMCI_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SCR_SMCI_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */
|
|
|
+ #define R_SCI0_SCR_SMCI_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SCR_SMCI_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */
|
|
|
+ #define R_SCI0_SCR_SMCI_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SCR_SMCI_CKE_Pos (0UL) /*!< CKE (Bit 0) */
|
|
|
+ #define R_SCI0_SCR_SMCI_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */
|
|
|
+/* ========================================================== TDR ========================================================== */
|
|
|
+ #define R_SCI0_TDR_TDR_Pos (0UL) /*!< TDR (Bit 0) */
|
|
|
+ #define R_SCI0_TDR_TDR_Msk (0xffUL) /*!< TDR (Bitfield-Mask: 0xff) */
|
|
|
+/* ========================================================== SSR ========================================================== */
|
|
|
+ #define R_SCI0_SSR_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */
|
|
|
+ #define R_SCI0_SSR_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SSR_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */
|
|
|
+ #define R_SCI0_SSR_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SSR_ORER_Pos (5UL) /*!< ORER (Bit 5) */
|
|
|
+ #define R_SCI0_SSR_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SSR_FER_Pos (4UL) /*!< FER (Bit 4) */
|
|
|
+ #define R_SCI0_SSR_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SSR_PER_Pos (3UL) /*!< PER (Bit 3) */
|
|
|
+ #define R_SCI0_SSR_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SSR_TEND_Pos (2UL) /*!< TEND (Bit 2) */
|
|
|
+ #define R_SCI0_SSR_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SSR_MPB_Pos (1UL) /*!< MPB (Bit 1) */
|
|
|
+ #define R_SCI0_SSR_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SSR_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */
|
|
|
+ #define R_SCI0_SSR_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= SSR_FIFO ======================================================== */
|
|
|
+ #define R_SCI0_SSR_FIFO_TDFE_Pos (7UL) /*!< TDFE (Bit 7) */
|
|
|
+ #define R_SCI0_SSR_FIFO_TDFE_Msk (0x80UL) /*!< TDFE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SSR_FIFO_RDF_Pos (6UL) /*!< RDF (Bit 6) */
|
|
|
+ #define R_SCI0_SSR_FIFO_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SSR_FIFO_ORER_Pos (5UL) /*!< ORER (Bit 5) */
|
|
|
+ #define R_SCI0_SSR_FIFO_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SSR_FIFO_FER_Pos (4UL) /*!< FER (Bit 4) */
|
|
|
+ #define R_SCI0_SSR_FIFO_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SSR_FIFO_PER_Pos (3UL) /*!< PER (Bit 3) */
|
|
|
+ #define R_SCI0_SSR_FIFO_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SSR_FIFO_TEND_Pos (2UL) /*!< TEND (Bit 2) */
|
|
|
+ #define R_SCI0_SSR_FIFO_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SSR_FIFO_DR_Pos (0UL) /*!< DR (Bit 0) */
|
|
|
+ #define R_SCI0_SSR_FIFO_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= SSR_SMCI ======================================================== */
|
|
|
+ #define R_SCI0_SSR_SMCI_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */
|
|
|
+ #define R_SCI0_SSR_SMCI_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SSR_SMCI_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */
|
|
|
+ #define R_SCI0_SSR_SMCI_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SSR_SMCI_ORER_Pos (5UL) /*!< ORER (Bit 5) */
|
|
|
+ #define R_SCI0_SSR_SMCI_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SSR_SMCI_ERS_Pos (4UL) /*!< ERS (Bit 4) */
|
|
|
+ #define R_SCI0_SSR_SMCI_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SSR_SMCI_PER_Pos (3UL) /*!< PER (Bit 3) */
|
|
|
+ #define R_SCI0_SSR_SMCI_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SSR_SMCI_TEND_Pos (2UL) /*!< TEND (Bit 2) */
|
|
|
+ #define R_SCI0_SSR_SMCI_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SSR_SMCI_MPB_Pos (1UL) /*!< MPB (Bit 1) */
|
|
|
+ #define R_SCI0_SSR_SMCI_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SSR_SMCI_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */
|
|
|
+ #define R_SCI0_SSR_SMCI_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================== RDR ========================================================== */
|
|
|
+ #define R_SCI0_RDR_RDR_Pos (0UL) /*!< RDR (Bit 0) */
|
|
|
+ #define R_SCI0_RDR_RDR_Msk (0xffUL) /*!< RDR (Bitfield-Mask: 0xff) */
|
|
|
+/* ========================================================= SCMR ========================================================== */
|
|
|
+ #define R_SCI0_SCMR_BCP2_Pos (7UL) /*!< BCP2 (Bit 7) */
|
|
|
+ #define R_SCI0_SCMR_BCP2_Msk (0x80UL) /*!< BCP2 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SCMR_CHR1_Pos (4UL) /*!< CHR1 (Bit 4) */
|
|
|
+ #define R_SCI0_SCMR_CHR1_Msk (0x10UL) /*!< CHR1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SCMR_SDIR_Pos (3UL) /*!< SDIR (Bit 3) */
|
|
|
+ #define R_SCI0_SCMR_SDIR_Msk (0x8UL) /*!< SDIR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SCMR_SINV_Pos (2UL) /*!< SINV (Bit 2) */
|
|
|
+ #define R_SCI0_SCMR_SINV_Msk (0x4UL) /*!< SINV (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SCMR_SMIF_Pos (0UL) /*!< SMIF (Bit 0) */
|
|
|
+ #define R_SCI0_SCMR_SMIF_Msk (0x1UL) /*!< SMIF (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= SEMR ========================================================== */
|
|
|
+ #define R_SCI0_SEMR_RXDESEL_Pos (7UL) /*!< RXDESEL (Bit 7) */
|
|
|
+ #define R_SCI0_SEMR_RXDESEL_Msk (0x80UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SEMR_BGDM_Pos (6UL) /*!< BGDM (Bit 6) */
|
|
|
+ #define R_SCI0_SEMR_BGDM_Msk (0x40UL) /*!< BGDM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SEMR_NFEN_Pos (5UL) /*!< NFEN (Bit 5) */
|
|
|
+ #define R_SCI0_SEMR_NFEN_Msk (0x20UL) /*!< NFEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SEMR_ABCS_Pos (4UL) /*!< ABCS (Bit 4) */
|
|
|
+ #define R_SCI0_SEMR_ABCS_Msk (0x10UL) /*!< ABCS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SEMR_ABCSE_Pos (3UL) /*!< ABCSE (Bit 3) */
|
|
|
+ #define R_SCI0_SEMR_ABCSE_Msk (0x8UL) /*!< ABCSE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SEMR_BRME_Pos (2UL) /*!< BRME (Bit 2) */
|
|
|
+ #define R_SCI0_SEMR_BRME_Msk (0x4UL) /*!< BRME (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SEMR_PADIS_Pos (1UL) /*!< PADIS (Bit 1) */
|
|
|
+ #define R_SCI0_SEMR_PADIS_Msk (0x2UL) /*!< PADIS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SEMR_ACS0_Pos (0UL) /*!< ACS0 (Bit 0) */
|
|
|
+ #define R_SCI0_SEMR_ACS0_Msk (0x1UL) /*!< ACS0 (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= SNFR ========================================================== */
|
|
|
+ #define R_SCI0_SNFR_NFCS_Pos (0UL) /*!< NFCS (Bit 0) */
|
|
|
+ #define R_SCI0_SNFR_NFCS_Msk (0x7UL) /*!< NFCS (Bitfield-Mask: 0x07) */
|
|
|
+/* ========================================================= SIMR1 ========================================================= */
|
|
|
+ #define R_SCI0_SIMR1_IICDL_Pos (3UL) /*!< IICDL (Bit 3) */
|
|
|
+ #define R_SCI0_SIMR1_IICDL_Msk (0xf8UL) /*!< IICDL (Bitfield-Mask: 0x1f) */
|
|
|
+ #define R_SCI0_SIMR1_IICM_Pos (0UL) /*!< IICM (Bit 0) */
|
|
|
+ #define R_SCI0_SIMR1_IICM_Msk (0x1UL) /*!< IICM (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= SIMR2 ========================================================= */
|
|
|
+ #define R_SCI0_SIMR2_IICACKT_Pos (5UL) /*!< IICACKT (Bit 5) */
|
|
|
+ #define R_SCI0_SIMR2_IICACKT_Msk (0x20UL) /*!< IICACKT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SIMR2_IICCSC_Pos (1UL) /*!< IICCSC (Bit 1) */
|
|
|
+ #define R_SCI0_SIMR2_IICCSC_Msk (0x2UL) /*!< IICCSC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SIMR2_IICINTM_Pos (0UL) /*!< IICINTM (Bit 0) */
|
|
|
+ #define R_SCI0_SIMR2_IICINTM_Msk (0x1UL) /*!< IICINTM (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= SIMR3 ========================================================= */
|
|
|
+ #define R_SCI0_SIMR3_IICSCLS_Pos (6UL) /*!< IICSCLS (Bit 6) */
|
|
|
+ #define R_SCI0_SIMR3_IICSCLS_Msk (0xc0UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_SCI0_SIMR3_IICSDAS_Pos (4UL) /*!< IICSDAS (Bit 4) */
|
|
|
+ #define R_SCI0_SIMR3_IICSDAS_Msk (0x30UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_SCI0_SIMR3_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */
|
|
|
+ #define R_SCI0_SIMR3_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SIMR3_IICSTPREQ_Pos (2UL) /*!< IICSTPREQ (Bit 2) */
|
|
|
+ #define R_SCI0_SIMR3_IICSTPREQ_Msk (0x4UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SIMR3_IICRSTAREQ_Pos (1UL) /*!< IICRSTAREQ (Bit 1) */
|
|
|
+ #define R_SCI0_SIMR3_IICRSTAREQ_Msk (0x2UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SIMR3_IICSTAREQ_Pos (0UL) /*!< IICSTAREQ (Bit 0) */
|
|
|
+ #define R_SCI0_SIMR3_IICSTAREQ_Msk (0x1UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= SISR ========================================================== */
|
|
|
+ #define R_SCI0_SISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */
|
|
|
+ #define R_SCI0_SISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= SPMR ========================================================== */
|
|
|
+ #define R_SCI0_SPMR_CKPH_Pos (7UL) /*!< CKPH (Bit 7) */
|
|
|
+ #define R_SCI0_SPMR_CKPH_Msk (0x80UL) /*!< CKPH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SPMR_CKPOL_Pos (6UL) /*!< CKPOL (Bit 6) */
|
|
|
+ #define R_SCI0_SPMR_CKPOL_Msk (0x40UL) /*!< CKPOL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SPMR_MFF_Pos (4UL) /*!< MFF (Bit 4) */
|
|
|
+ #define R_SCI0_SPMR_MFF_Msk (0x10UL) /*!< MFF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SPMR_CSTPEN_Pos (3UL) /*!< CSTPEN (Bit 3) */
|
|
|
+ #define R_SCI0_SPMR_CSTPEN_Msk (0x8UL) /*!< CSTPEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SPMR_MSS_Pos (2UL) /*!< MSS (Bit 2) */
|
|
|
+ #define R_SCI0_SPMR_MSS_Msk (0x4UL) /*!< MSS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SPMR_CTSE_Pos (1UL) /*!< CTSE (Bit 1) */
|
|
|
+ #define R_SCI0_SPMR_CTSE_Msk (0x2UL) /*!< CTSE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SPMR_SSE_Pos (0UL) /*!< SSE (Bit 0) */
|
|
|
+ #define R_SCI0_SPMR_SSE_Msk (0x1UL) /*!< SSE (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= TDRHL ========================================================= */
|
|
|
+ #define R_SCI0_TDRHL_TDRHL_Pos (0UL) /*!< TDRHL (Bit 0) */
|
|
|
+ #define R_SCI0_TDRHL_TDRHL_Msk (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================== FTDRHL ========================================================= */
|
|
|
+ #define R_SCI0_FTDRHL_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */
|
|
|
+ #define R_SCI0_FTDRHL_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_FTDRHL_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */
|
|
|
+ #define R_SCI0_FTDRHL_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */
|
|
|
+/* ========================================================= FTDRH ========================================================= */
|
|
|
+ #define R_SCI0_FTDRH_MPBT_Pos (1UL) /*!< MPBT (Bit 1) */
|
|
|
+ #define R_SCI0_FTDRH_MPBT_Msk (0x2UL) /*!< MPBT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_FTDRH_TDATH_Pos (0UL) /*!< TDATH (Bit 0) */
|
|
|
+ #define R_SCI0_FTDRH_TDATH_Msk (0x1UL) /*!< TDATH (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= FTDRL ========================================================= */
|
|
|
+ #define R_SCI0_FTDRL_TDATL_Pos (0UL) /*!< TDATL (Bit 0) */
|
|
|
+ #define R_SCI0_FTDRL_TDATL_Msk (0xffUL) /*!< TDATL (Bitfield-Mask: 0xff) */
|
|
|
+/* ========================================================= RDRHL ========================================================= */
|
|
|
+ #define R_SCI0_RDRHL_RDRHL_Pos (0UL) /*!< RDRHL (Bit 0) */
|
|
|
+ #define R_SCI0_RDRHL_RDRHL_Msk (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================== FRDRHL ========================================================= */
|
|
|
+ #define R_SCI0_FRDRHL_RDF_Pos (14UL) /*!< RDF (Bit 14) */
|
|
|
+ #define R_SCI0_FRDRHL_RDF_Msk (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_FRDRHL_ORER_Pos (13UL) /*!< ORER (Bit 13) */
|
|
|
+ #define R_SCI0_FRDRHL_ORER_Msk (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_FRDRHL_FER_Pos (12UL) /*!< FER (Bit 12) */
|
|
|
+ #define R_SCI0_FRDRHL_FER_Msk (0x1000UL) /*!< FER (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_FRDRHL_PER_Pos (11UL) /*!< PER (Bit 11) */
|
|
|
+ #define R_SCI0_FRDRHL_PER_Msk (0x800UL) /*!< PER (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_FRDRHL_DR_Pos (10UL) /*!< DR (Bit 10) */
|
|
|
+ #define R_SCI0_FRDRHL_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_FRDRHL_MPB_Pos (9UL) /*!< MPB (Bit 9) */
|
|
|
+ #define R_SCI0_FRDRHL_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_FRDRHL_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */
|
|
|
+ #define R_SCI0_FRDRHL_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */
|
|
|
+/* ========================================================= FRDRH ========================================================= */
|
|
|
+ #define R_SCI0_FRDRH_RDF_Pos (6UL) /*!< RDF (Bit 6) */
|
|
|
+ #define R_SCI0_FRDRH_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_FRDRH_ORER_Pos (5UL) /*!< ORER (Bit 5) */
|
|
|
+ #define R_SCI0_FRDRH_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_FRDRH_FER_Pos (4UL) /*!< FER (Bit 4) */
|
|
|
+ #define R_SCI0_FRDRH_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_FRDRH_PER_Pos (3UL) /*!< PER (Bit 3) */
|
|
|
+ #define R_SCI0_FRDRH_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_FRDRH_DR_Pos (2UL) /*!< DR (Bit 2) */
|
|
|
+ #define R_SCI0_FRDRH_DR_Msk (0x4UL) /*!< DR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_FRDRH_MPB_Pos (1UL) /*!< MPB (Bit 1) */
|
|
|
+ #define R_SCI0_FRDRH_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_FRDRH_RDATH_Pos (0UL) /*!< RDATH (Bit 0) */
|
|
|
+ #define R_SCI0_FRDRH_RDATH_Msk (0x1UL) /*!< RDATH (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= FRDRL ========================================================= */
|
|
|
+ #define R_SCI0_FRDRL_RDATL_Pos (0UL) /*!< RDATL (Bit 0) */
|
|
|
+ #define R_SCI0_FRDRL_RDATL_Msk (0xffUL) /*!< RDATL (Bitfield-Mask: 0xff) */
|
|
|
+/* ========================================================= MDDR ========================================================== */
|
|
|
+ #define R_SCI0_MDDR_MDDR_Pos (0UL) /*!< MDDR (Bit 0) */
|
|
|
+ #define R_SCI0_MDDR_MDDR_Msk (0xffUL) /*!< MDDR (Bitfield-Mask: 0xff) */
|
|
|
+/* ========================================================= DCCR ========================================================== */
|
|
|
+ #define R_SCI0_DCCR_DCME_Pos (7UL) /*!< DCME (Bit 7) */
|
|
|
+ #define R_SCI0_DCCR_DCME_Msk (0x80UL) /*!< DCME (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_DCCR_IDSEL_Pos (6UL) /*!< IDSEL (Bit 6) */
|
|
|
+ #define R_SCI0_DCCR_IDSEL_Msk (0x40UL) /*!< IDSEL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_DCCR_DFER_Pos (4UL) /*!< DFER (Bit 4) */
|
|
|
+ #define R_SCI0_DCCR_DFER_Msk (0x10UL) /*!< DFER (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_DCCR_DPER_Pos (3UL) /*!< DPER (Bit 3) */
|
|
|
+ #define R_SCI0_DCCR_DPER_Msk (0x8UL) /*!< DPER (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_DCCR_DCMF_Pos (0UL) /*!< DCMF (Bit 0) */
|
|
|
+ #define R_SCI0_DCCR_DCMF_Msk (0x1UL) /*!< DCMF (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================== FCR ========================================================== */
|
|
|
+ #define R_SCI0_FCR_RSTRG_Pos (12UL) /*!< RSTRG (Bit 12) */
|
|
|
+ #define R_SCI0_FCR_RSTRG_Msk (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_SCI0_FCR_RTRG_Pos (8UL) /*!< RTRG (Bit 8) */
|
|
|
+ #define R_SCI0_FCR_RTRG_Msk (0xf00UL) /*!< RTRG (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_SCI0_FCR_TTRG_Pos (4UL) /*!< TTRG (Bit 4) */
|
|
|
+ #define R_SCI0_FCR_TTRG_Msk (0xf0UL) /*!< TTRG (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_SCI0_FCR_DRES_Pos (3UL) /*!< DRES (Bit 3) */
|
|
|
+ #define R_SCI0_FCR_DRES_Msk (0x8UL) /*!< DRES (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_FCR_TFRST_Pos (2UL) /*!< TFRST (Bit 2) */
|
|
|
+ #define R_SCI0_FCR_TFRST_Msk (0x4UL) /*!< TFRST (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_FCR_RFRST_Pos (1UL) /*!< RFRST (Bit 1) */
|
|
|
+ #define R_SCI0_FCR_RFRST_Msk (0x2UL) /*!< RFRST (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_FCR_FM_Pos (0UL) /*!< FM (Bit 0) */
|
|
|
+ #define R_SCI0_FCR_FM_Msk (0x1UL) /*!< FM (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================== FDR ========================================================== */
|
|
|
+ #define R_SCI0_FDR_T_Pos (8UL) /*!< T (Bit 8) */
|
|
|
+ #define R_SCI0_FDR_T_Msk (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f) */
|
|
|
+ #define R_SCI0_FDR_R_Pos (0UL) /*!< R (Bit 0) */
|
|
|
+ #define R_SCI0_FDR_R_Msk (0x1fUL) /*!< R (Bitfield-Mask: 0x1f) */
|
|
|
+/* ========================================================== LSR ========================================================== */
|
|
|
+ #define R_SCI0_LSR_PNUM_Pos (8UL) /*!< PNUM (Bit 8) */
|
|
|
+ #define R_SCI0_LSR_PNUM_Msk (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f) */
|
|
|
+ #define R_SCI0_LSR_FNUM_Pos (2UL) /*!< FNUM (Bit 2) */
|
|
|
+ #define R_SCI0_LSR_FNUM_Msk (0x7cUL) /*!< FNUM (Bitfield-Mask: 0x1f) */
|
|
|
+ #define R_SCI0_LSR_ORER_Pos (0UL) /*!< ORER (Bit 0) */
|
|
|
+ #define R_SCI0_LSR_ORER_Msk (0x1UL) /*!< ORER (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================== CDR ========================================================== */
|
|
|
+ #define R_SCI0_CDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */
|
|
|
+ #define R_SCI0_CDR_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */
|
|
|
+/* ========================================================= SPTR ========================================================== */
|
|
|
+ #define R_SCI0_SPTR_SPB2IO_Pos (2UL) /*!< SPB2IO (Bit 2) */
|
|
|
+ #define R_SCI0_SPTR_SPB2IO_Msk (0x4UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SPTR_SPB2DT_Pos (1UL) /*!< SPB2DT (Bit 1) */
|
|
|
+ #define R_SCI0_SPTR_SPB2DT_Msk (0x2UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SPTR_RXDMON_Pos (0UL) /*!< RXDMON (Bit 0) */
|
|
|
+ #define R_SCI0_SPTR_RXDMON_Msk (0x1UL) /*!< RXDMON (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SPTR_RINV_Pos (4UL) /*!< RINV (Bit 4) */
|
|
|
+ #define R_SCI0_SPTR_RINV_Msk (0x10UL) /*!< RINV (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SPTR_TINV_Pos (5UL) /*!< TINV (Bit 5) */
|
|
|
+ #define R_SCI0_SPTR_TINV_Msk (0x20UL) /*!< TINV (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SPTR_ASEN_Pos (6UL) /*!< ASEN (Bit 6) */
|
|
|
+ #define R_SCI0_SPTR_ASEN_Msk (0x40UL) /*!< ASEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_SPTR_ATEN_Pos (7UL) /*!< ATEN (Bit 7) */
|
|
|
+ #define R_SCI0_SPTR_ATEN_Msk (0x80UL) /*!< ATEN (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= ACTR ========================================================== */
|
|
|
+ #define R_SCI0_ACTR_AST_Pos (0UL) /*!< AST (Bit 0) */
|
|
|
+ #define R_SCI0_ACTR_AST_Msk (0x7UL) /*!< AST (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_SCI0_ACTR_AJD_Pos (3UL) /*!< AJD (Bit 3) */
|
|
|
+ #define R_SCI0_ACTR_AJD_Msk (0x8UL) /*!< AJD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_ACTR_ATT_Pos (4UL) /*!< ATT (Bit 4) */
|
|
|
+ #define R_SCI0_ACTR_ATT_Msk (0x70UL) /*!< ATT (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_SCI0_ACTR_AET_Pos (7UL) /*!< AET (Bit 7) */
|
|
|
+ #define R_SCI0_ACTR_AET_Msk (0x80UL) /*!< AET (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= ESMER ========================================================= */
|
|
|
+ #define R_SCI0_ESMER_ESME_Pos (0UL) /*!< ESME (Bit 0) */
|
|
|
+ #define R_SCI0_ESMER_ESME_Msk (0x1UL) /*!< ESME (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================== CR0 ========================================================== */
|
|
|
+ #define R_SCI0_CR0_SFSF_Pos (1UL) /*!< SFSF (Bit 1) */
|
|
|
+ #define R_SCI0_CR0_SFSF_Msk (0x2UL) /*!< SFSF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_CR0_RXDSF_Pos (2UL) /*!< RXDSF (Bit 2) */
|
|
|
+ #define R_SCI0_CR0_RXDSF_Msk (0x4UL) /*!< RXDSF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_CR0_BRME_Pos (3UL) /*!< BRME (Bit 3) */
|
|
|
+ #define R_SCI0_CR0_BRME_Msk (0x8UL) /*!< BRME (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================== CR1 ========================================================== */
|
|
|
+ #define R_SCI0_CR1_BFE_Pos (0UL) /*!< BFE (Bit 0) */
|
|
|
+ #define R_SCI0_CR1_BFE_Msk (0x1UL) /*!< BFE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_CR1_CF0RE_Pos (1UL) /*!< CF0RE (Bit 1) */
|
|
|
+ #define R_SCI0_CR1_CF0RE_Msk (0x2UL) /*!< CF0RE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_CR1_CF1DS_Pos (2UL) /*!< CF1DS (Bit 2) */
|
|
|
+ #define R_SCI0_CR1_CF1DS_Msk (0xcUL) /*!< CF1DS (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_SCI0_CR1_PIBE_Pos (4UL) /*!< PIBE (Bit 4) */
|
|
|
+ #define R_SCI0_CR1_PIBE_Msk (0x10UL) /*!< PIBE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_CR1_PIBS_Pos (5UL) /*!< PIBS (Bit 5) */
|
|
|
+ #define R_SCI0_CR1_PIBS_Msk (0xe0UL) /*!< PIBS (Bitfield-Mask: 0x07) */
|
|
|
+/* ========================================================== CR2 ========================================================== */
|
|
|
+ #define R_SCI0_CR2_DFCS_Pos (0UL) /*!< DFCS (Bit 0) */
|
|
|
+ #define R_SCI0_CR2_DFCS_Msk (0x7UL) /*!< DFCS (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_SCI0_CR2_BCCS_Pos (4UL) /*!< BCCS (Bit 4) */
|
|
|
+ #define R_SCI0_CR2_BCCS_Msk (0x30UL) /*!< BCCS (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_SCI0_CR2_RTS_Pos (6UL) /*!< RTS (Bit 6) */
|
|
|
+ #define R_SCI0_CR2_RTS_Msk (0xc0UL) /*!< RTS (Bitfield-Mask: 0x03) */
|
|
|
+/* ========================================================== CR3 ========================================================== */
|
|
|
+ #define R_SCI0_CR3_SDST_Pos (0UL) /*!< SDST (Bit 0) */
|
|
|
+ #define R_SCI0_CR3_SDST_Msk (0x1UL) /*!< SDST (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================== PCR ========================================================== */
|
|
|
+ #define R_SCI0_PCR_TXDXPS_Pos (0UL) /*!< TXDXPS (Bit 0) */
|
|
|
+ #define R_SCI0_PCR_TXDXPS_Msk (0x1UL) /*!< TXDXPS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_PCR_RXDXPS_Pos (1UL) /*!< RXDXPS (Bit 1) */
|
|
|
+ #define R_SCI0_PCR_RXDXPS_Msk (0x2UL) /*!< RXDXPS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_PCR_SHARPS_Pos (4UL) /*!< SHARPS (Bit 4) */
|
|
|
+ #define R_SCI0_PCR_SHARPS_Msk (0x10UL) /*!< SHARPS (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================== ICR ========================================================== */
|
|
|
+ #define R_SCI0_ICR_BFDIE_Pos (0UL) /*!< BFDIE (Bit 0) */
|
|
|
+ #define R_SCI0_ICR_BFDIE_Msk (0x1UL) /*!< BFDIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_ICR_CF0MIE_Pos (1UL) /*!< CF0MIE (Bit 1) */
|
|
|
+ #define R_SCI0_ICR_CF0MIE_Msk (0x2UL) /*!< CF0MIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_ICR_CF1MIE_Pos (2UL) /*!< CF1MIE (Bit 2) */
|
|
|
+ #define R_SCI0_ICR_CF1MIE_Msk (0x4UL) /*!< CF1MIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_ICR_PIBDIE_Pos (3UL) /*!< PIBDIE (Bit 3) */
|
|
|
+ #define R_SCI0_ICR_PIBDIE_Msk (0x8UL) /*!< PIBDIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_ICR_BCDIE_Pos (4UL) /*!< BCDIE (Bit 4) */
|
|
|
+ #define R_SCI0_ICR_BCDIE_Msk (0x10UL) /*!< BCDIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_ICR_AEDIE_Pos (5UL) /*!< AEDIE (Bit 5) */
|
|
|
+ #define R_SCI0_ICR_AEDIE_Msk (0x20UL) /*!< AEDIE (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================== STR ========================================================== */
|
|
|
+ #define R_SCI0_STR_BFDF_Pos (0UL) /*!< BFDF (Bit 0) */
|
|
|
+ #define R_SCI0_STR_BFDF_Msk (0x1UL) /*!< BFDF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_STR_CF0MF_Pos (1UL) /*!< CF0MF (Bit 1) */
|
|
|
+ #define R_SCI0_STR_CF0MF_Msk (0x2UL) /*!< CF0MF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_STR_CF1MF_Pos (2UL) /*!< CF1MF (Bit 2) */
|
|
|
+ #define R_SCI0_STR_CF1MF_Msk (0x4UL) /*!< CF1MF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_STR_PIBDF_Pos (3UL) /*!< PIBDF (Bit 3) */
|
|
|
+ #define R_SCI0_STR_PIBDF_Msk (0x8UL) /*!< PIBDF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_STR_BCDF_Pos (4UL) /*!< BCDF (Bit 4) */
|
|
|
+ #define R_SCI0_STR_BCDF_Msk (0x10UL) /*!< BCDF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_STR_AEDF_Pos (5UL) /*!< AEDF (Bit 5) */
|
|
|
+ #define R_SCI0_STR_AEDF_Msk (0x20UL) /*!< AEDF (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= STCR ========================================================== */
|
|
|
+ #define R_SCI0_STCR_BFDCL_Pos (0UL) /*!< BFDCL (Bit 0) */
|
|
|
+ #define R_SCI0_STCR_BFDCL_Msk (0x1UL) /*!< BFDCL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_STCR_CF0MCL_Pos (1UL) /*!< CF0MCL (Bit 1) */
|
|
|
+ #define R_SCI0_STCR_CF0MCL_Msk (0x2UL) /*!< CF0MCL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_STCR_CF1MCL_Pos (2UL) /*!< CF1MCL (Bit 2) */
|
|
|
+ #define R_SCI0_STCR_CF1MCL_Msk (0x4UL) /*!< CF1MCL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_STCR_PIBDCL_Pos (3UL) /*!< PIBDCL (Bit 3) */
|
|
|
+ #define R_SCI0_STCR_PIBDCL_Msk (0x8UL) /*!< PIBDCL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_STCR_BCDCL_Pos (4UL) /*!< BCDCL (Bit 4) */
|
|
|
+ #define R_SCI0_STCR_BCDCL_Msk (0x10UL) /*!< BCDCL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_STCR_AEDCL_Pos (5UL) /*!< AEDCL (Bit 5) */
|
|
|
+ #define R_SCI0_STCR_AEDCL_Msk (0x20UL) /*!< AEDCL (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= CF0DR ========================================================= */
|
|
|
+/* ========================================================= CF0CR ========================================================= */
|
|
|
+ #define R_SCI0_CF0CR_CF0CE0_Pos (0UL) /*!< CF0CE0 (Bit 0) */
|
|
|
+ #define R_SCI0_CF0CR_CF0CE0_Msk (0x1UL) /*!< CF0CE0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_CF0CR_CF0CE1_Pos (1UL) /*!< CF0CE1 (Bit 1) */
|
|
|
+ #define R_SCI0_CF0CR_CF0CE1_Msk (0x2UL) /*!< CF0CE1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_CF0CR_CF0CE2_Pos (2UL) /*!< CF0CE2 (Bit 2) */
|
|
|
+ #define R_SCI0_CF0CR_CF0CE2_Msk (0x4UL) /*!< CF0CE2 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_CF0CR_CF0CE3_Pos (3UL) /*!< CF0CE3 (Bit 3) */
|
|
|
+ #define R_SCI0_CF0CR_CF0CE3_Msk (0x8UL) /*!< CF0CE3 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_CF0CR_CF0CE4_Pos (4UL) /*!< CF0CE4 (Bit 4) */
|
|
|
+ #define R_SCI0_CF0CR_CF0CE4_Msk (0x10UL) /*!< CF0CE4 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_CF0CR_CF0CE5_Pos (5UL) /*!< CF0CE5 (Bit 5) */
|
|
|
+ #define R_SCI0_CF0CR_CF0CE5_Msk (0x20UL) /*!< CF0CE5 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_CF0CR_CF0CE6_Pos (6UL) /*!< CF0CE6 (Bit 6) */
|
|
|
+ #define R_SCI0_CF0CR_CF0CE6_Msk (0x40UL) /*!< CF0CE6 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_CF0CR_CF0CE7_Pos (7UL) /*!< CF0CE7 (Bit 7) */
|
|
|
+ #define R_SCI0_CF0CR_CF0CE7_Msk (0x80UL) /*!< CF0CE7 (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= CF0RR ========================================================= */
|
|
|
+/* ======================================================== PCF1DR ========================================================= */
|
|
|
+/* ======================================================== SCF1DR ========================================================= */
|
|
|
+/* ========================================================= CF1CR ========================================================= */
|
|
|
+ #define R_SCI0_CF1CR_CF1CE0_Pos (0UL) /*!< CF1CE0 (Bit 0) */
|
|
|
+ #define R_SCI0_CF1CR_CF1CE0_Msk (0x1UL) /*!< CF1CE0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_CF1CR_CF1CE1_Pos (1UL) /*!< CF1CE1 (Bit 1) */
|
|
|
+ #define R_SCI0_CF1CR_CF1CE1_Msk (0x2UL) /*!< CF1CE1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_CF1CR_CF1CE2_Pos (2UL) /*!< CF1CE2 (Bit 2) */
|
|
|
+ #define R_SCI0_CF1CR_CF1CE2_Msk (0x4UL) /*!< CF1CE2 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_CF1CR_CF1CE3_Pos (3UL) /*!< CF1CE3 (Bit 3) */
|
|
|
+ #define R_SCI0_CF1CR_CF1CE3_Msk (0x8UL) /*!< CF1CE3 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_CF1CR_CF1CE4_Pos (4UL) /*!< CF1CE4 (Bit 4) */
|
|
|
+ #define R_SCI0_CF1CR_CF1CE4_Msk (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_CF1CR_CF1CE5_Pos (5UL) /*!< CF1CE5 (Bit 5) */
|
|
|
+ #define R_SCI0_CF1CR_CF1CE5_Msk (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_CF1CR_CF1CE6_Pos (6UL) /*!< CF1CE6 (Bit 6) */
|
|
|
+ #define R_SCI0_CF1CR_CF1CE6_Msk (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_CF1CR_CF1CE7_Pos (7UL) /*!< CF1CE7 (Bit 7) */
|
|
|
+ #define R_SCI0_CF1CR_CF1CE7_Msk (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= CF1RR ========================================================= */
|
|
|
+/* ========================================================== TCR ========================================================== */
|
|
|
+ #define R_SCI0_TCR_TCST_Pos (0UL) /*!< TCST (Bit 0) */
|
|
|
+ #define R_SCI0_TCR_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================== TMR ========================================================== */
|
|
|
+ #define R_SCI0_TMR_TOMS_Pos (0UL) /*!< TOMS (Bit 0) */
|
|
|
+ #define R_SCI0_TMR_TOMS_Msk (0x3UL) /*!< TOMS (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_SCI0_TMR_TWRC_Pos (3UL) /*!< TWRC (Bit 3) */
|
|
|
+ #define R_SCI0_TMR_TWRC_Msk (0x8UL) /*!< TWRC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI0_TMR_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */
|
|
|
+ #define R_SCI0_TMR_TCSS_Msk (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07) */
|
|
|
+/* ========================================================= TPRE ========================================================== */
|
|
|
+/* ========================================================= TCNT ========================================================== */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_SDHI0 ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ======================================================== SD_CMD ========================================================= */
|
|
|
+ #define R_SDHI0_SD_CMD_CMD12AT_Pos (14UL) /*!< CMD12AT (Bit 14) */
|
|
|
+ #define R_SDHI0_SD_CMD_CMD12AT_Msk (0xc000UL) /*!< CMD12AT (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_SDHI0_SD_CMD_TRSTP_Pos (13UL) /*!< TRSTP (Bit 13) */
|
|
|
+ #define R_SDHI0_SD_CMD_TRSTP_Msk (0x2000UL) /*!< TRSTP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_CMD_CMDRW_Pos (12UL) /*!< CMDRW (Bit 12) */
|
|
|
+ #define R_SDHI0_SD_CMD_CMDRW_Msk (0x1000UL) /*!< CMDRW (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_CMD_CMDTP_Pos (11UL) /*!< CMDTP (Bit 11) */
|
|
|
+ #define R_SDHI0_SD_CMD_CMDTP_Msk (0x800UL) /*!< CMDTP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_CMD_RSPTP_Pos (8UL) /*!< RSPTP (Bit 8) */
|
|
|
+ #define R_SDHI0_SD_CMD_RSPTP_Msk (0x700UL) /*!< RSPTP (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_SDHI0_SD_CMD_ACMD_Pos (6UL) /*!< ACMD (Bit 6) */
|
|
|
+ #define R_SDHI0_SD_CMD_ACMD_Msk (0xc0UL) /*!< ACMD (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_SDHI0_SD_CMD_CMDIDX_Pos (0UL) /*!< CMDIDX (Bit 0) */
|
|
|
+ #define R_SDHI0_SD_CMD_CMDIDX_Msk (0x3fUL) /*!< CMDIDX (Bitfield-Mask: 0x3f) */
|
|
|
+/* ======================================================== SD_ARG ========================================================= */
|
|
|
+ #define R_SDHI0_SD_ARG_SD_ARG_Pos (0UL) /*!< SD_ARG (Bit 0) */
|
|
|
+ #define R_SDHI0_SD_ARG_SD_ARG_Msk (0xffffffffUL) /*!< SD_ARG (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================== SD_ARG1 ======================================================== */
|
|
|
+ #define R_SDHI0_SD_ARG1_SD_ARG1_Pos (0UL) /*!< SD_ARG1 (Bit 0) */
|
|
|
+ #define R_SDHI0_SD_ARG1_SD_ARG1_Msk (0xffffUL) /*!< SD_ARG1 (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================== SD_STOP ======================================================== */
|
|
|
+ #define R_SDHI0_SD_STOP_SEC_Pos (8UL) /*!< SEC (Bit 8) */
|
|
|
+ #define R_SDHI0_SD_STOP_SEC_Msk (0x100UL) /*!< SEC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_STOP_STP_Pos (0UL) /*!< STP (Bit 0) */
|
|
|
+ #define R_SDHI0_SD_STOP_STP_Msk (0x1UL) /*!< STP (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= SD_SECCNT ======================================================= */
|
|
|
+ #define R_SDHI0_SD_SECCNT_SD_SECCNT_Pos (0UL) /*!< SD_SECCNT (Bit 0) */
|
|
|
+ #define R_SDHI0_SD_SECCNT_SD_SECCNT_Msk (0xffffffffUL) /*!< SD_SECCNT (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================= SD_RSP10 ======================================================== */
|
|
|
+ #define R_SDHI0_SD_RSP10_SD_RSP10_Pos (0UL) /*!< SD_RSP10 (Bit 0) */
|
|
|
+ #define R_SDHI0_SD_RSP10_SD_RSP10_Msk (0xffffffffUL) /*!< SD_RSP10 (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================== SD_RSP1 ======================================================== */
|
|
|
+ #define R_SDHI0_SD_RSP1_SD_RSP1_Pos (0UL) /*!< SD_RSP1 (Bit 0) */
|
|
|
+ #define R_SDHI0_SD_RSP1_SD_RSP1_Msk (0xffffUL) /*!< SD_RSP1 (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================= SD_RSP32 ======================================================== */
|
|
|
+ #define R_SDHI0_SD_RSP32_SD_RSP32_Pos (0UL) /*!< SD_RSP32 (Bit 0) */
|
|
|
+ #define R_SDHI0_SD_RSP32_SD_RSP32_Msk (0xffffffffUL) /*!< SD_RSP32 (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================== SD_RSP3 ======================================================== */
|
|
|
+ #define R_SDHI0_SD_RSP3_SD_RSP3_Pos (0UL) /*!< SD_RSP3 (Bit 0) */
|
|
|
+ #define R_SDHI0_SD_RSP3_SD_RSP3_Msk (0xffffUL) /*!< SD_RSP3 (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================= SD_RSP54 ======================================================== */
|
|
|
+ #define R_SDHI0_SD_RSP54_SD_RSP54_Pos (0UL) /*!< SD_RSP54 (Bit 0) */
|
|
|
+ #define R_SDHI0_SD_RSP54_SD_RSP54_Msk (0xffffffffUL) /*!< SD_RSP54 (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================== SD_RSP5 ======================================================== */
|
|
|
+ #define R_SDHI0_SD_RSP5_SD_RSP5_Pos (0UL) /*!< SD_RSP5 (Bit 0) */
|
|
|
+ #define R_SDHI0_SD_RSP5_SD_RSP5_Msk (0xffffUL) /*!< SD_RSP5 (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================= SD_RSP76 ======================================================== */
|
|
|
+ #define R_SDHI0_SD_RSP76_SD_RSP76_Pos (0UL) /*!< SD_RSP76 (Bit 0) */
|
|
|
+ #define R_SDHI0_SD_RSP76_SD_RSP76_Msk (0xffffffUL) /*!< SD_RSP76 (Bitfield-Mask: 0xffffff) */
|
|
|
+/* ======================================================== SD_RSP7 ======================================================== */
|
|
|
+ #define R_SDHI0_SD_RSP7_SD_RSP7_Pos (0UL) /*!< SD_RSP7 (Bit 0) */
|
|
|
+ #define R_SDHI0_SD_RSP7_SD_RSP7_Msk (0xffUL) /*!< SD_RSP7 (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= SD_INFO1 ======================================================== */
|
|
|
+ #define R_SDHI0_SD_INFO1_SDD3MON_Pos (10UL) /*!< SDD3MON (Bit 10) */
|
|
|
+ #define R_SDHI0_SD_INFO1_SDD3MON_Msk (0x400UL) /*!< SDD3MON (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_INFO1_SDD3IN_Pos (9UL) /*!< SDD3IN (Bit 9) */
|
|
|
+ #define R_SDHI0_SD_INFO1_SDD3IN_Msk (0x200UL) /*!< SDD3IN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_INFO1_SDD3RM_Pos (8UL) /*!< SDD3RM (Bit 8) */
|
|
|
+ #define R_SDHI0_SD_INFO1_SDD3RM_Msk (0x100UL) /*!< SDD3RM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_INFO1_SDWPMON_Pos (7UL) /*!< SDWPMON (Bit 7) */
|
|
|
+ #define R_SDHI0_SD_INFO1_SDWPMON_Msk (0x80UL) /*!< SDWPMON (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_INFO1_SDCDMON_Pos (5UL) /*!< SDCDMON (Bit 5) */
|
|
|
+ #define R_SDHI0_SD_INFO1_SDCDMON_Msk (0x20UL) /*!< SDCDMON (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_INFO1_SDCDIN_Pos (4UL) /*!< SDCDIN (Bit 4) */
|
|
|
+ #define R_SDHI0_SD_INFO1_SDCDIN_Msk (0x10UL) /*!< SDCDIN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_INFO1_SDCDRM_Pos (3UL) /*!< SDCDRM (Bit 3) */
|
|
|
+ #define R_SDHI0_SD_INFO1_SDCDRM_Msk (0x8UL) /*!< SDCDRM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_INFO1_ACEND_Pos (2UL) /*!< ACEND (Bit 2) */
|
|
|
+ #define R_SDHI0_SD_INFO1_ACEND_Msk (0x4UL) /*!< ACEND (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_INFO1_RSPEND_Pos (0UL) /*!< RSPEND (Bit 0) */
|
|
|
+ #define R_SDHI0_SD_INFO1_RSPEND_Msk (0x1UL) /*!< RSPEND (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= SD_INFO2 ======================================================== */
|
|
|
+ #define R_SDHI0_SD_INFO2_ILA_Pos (15UL) /*!< ILA (Bit 15) */
|
|
|
+ #define R_SDHI0_SD_INFO2_ILA_Msk (0x8000UL) /*!< ILA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_INFO2_CBSY_Pos (14UL) /*!< CBSY (Bit 14) */
|
|
|
+ #define R_SDHI0_SD_INFO2_CBSY_Msk (0x4000UL) /*!< CBSY (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Pos (13UL) /*!< SD_CLK_CTRLEN (Bit 13) */
|
|
|
+ #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Msk (0x2000UL) /*!< SD_CLK_CTRLEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_INFO2_BWE_Pos (9UL) /*!< BWE (Bit 9) */
|
|
|
+ #define R_SDHI0_SD_INFO2_BWE_Msk (0x200UL) /*!< BWE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_INFO2_BRE_Pos (8UL) /*!< BRE (Bit 8) */
|
|
|
+ #define R_SDHI0_SD_INFO2_BRE_Msk (0x100UL) /*!< BRE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_INFO2_SDD0MON_Pos (7UL) /*!< SDD0MON (Bit 7) */
|
|
|
+ #define R_SDHI0_SD_INFO2_SDD0MON_Msk (0x80UL) /*!< SDD0MON (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_INFO2_RSPTO_Pos (6UL) /*!< RSPTO (Bit 6) */
|
|
|
+ #define R_SDHI0_SD_INFO2_RSPTO_Msk (0x40UL) /*!< RSPTO (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_INFO2_ILR_Pos (5UL) /*!< ILR (Bit 5) */
|
|
|
+ #define R_SDHI0_SD_INFO2_ILR_Msk (0x20UL) /*!< ILR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_INFO2_ILW_Pos (4UL) /*!< ILW (Bit 4) */
|
|
|
+ #define R_SDHI0_SD_INFO2_ILW_Msk (0x10UL) /*!< ILW (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_INFO2_DTO_Pos (3UL) /*!< DTO (Bit 3) */
|
|
|
+ #define R_SDHI0_SD_INFO2_DTO_Msk (0x8UL) /*!< DTO (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_INFO2_ENDE_Pos (2UL) /*!< ENDE (Bit 2) */
|
|
|
+ #define R_SDHI0_SD_INFO2_ENDE_Msk (0x4UL) /*!< ENDE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_INFO2_CRCE_Pos (1UL) /*!< CRCE (Bit 1) */
|
|
|
+ #define R_SDHI0_SD_INFO2_CRCE_Msk (0x2UL) /*!< CRCE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_INFO2_CMDE_Pos (0UL) /*!< CMDE (Bit 0) */
|
|
|
+ #define R_SDHI0_SD_INFO2_CMDE_Msk (0x1UL) /*!< CMDE (Bitfield-Mask: 0x01) */
|
|
|
+/* ===================================================== SD_INFO1_MASK ===================================================== */
|
|
|
+ #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Pos (9UL) /*!< SDD3INM (Bit 9) */
|
|
|
+ #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Msk (0x200UL) /*!< SDD3INM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Pos (8UL) /*!< SDD3RMM (Bit 8) */
|
|
|
+ #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Msk (0x100UL) /*!< SDD3RMM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Pos (4UL) /*!< SDCDINM (Bit 4) */
|
|
|
+ #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Msk (0x10UL) /*!< SDCDINM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Pos (3UL) /*!< SDCDRMM (Bit 3) */
|
|
|
+ #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Msk (0x8UL) /*!< SDCDRMM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_INFO1_MASK_ACENDM_Pos (2UL) /*!< ACENDM (Bit 2) */
|
|
|
+ #define R_SDHI0_SD_INFO1_MASK_ACENDM_Msk (0x4UL) /*!< ACENDM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Pos (0UL) /*!< RSPENDM (Bit 0) */
|
|
|
+ #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Msk (0x1UL) /*!< RSPENDM (Bitfield-Mask: 0x01) */
|
|
|
+/* ===================================================== SD_INFO2_MASK ===================================================== */
|
|
|
+ #define R_SDHI0_SD_INFO2_MASK_ILAM_Pos (15UL) /*!< ILAM (Bit 15) */
|
|
|
+ #define R_SDHI0_SD_INFO2_MASK_ILAM_Msk (0x8000UL) /*!< ILAM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_INFO2_MASK_BWEM_Pos (9UL) /*!< BWEM (Bit 9) */
|
|
|
+ #define R_SDHI0_SD_INFO2_MASK_BWEM_Msk (0x200UL) /*!< BWEM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_INFO2_MASK_BREM_Pos (8UL) /*!< BREM (Bit 8) */
|
|
|
+ #define R_SDHI0_SD_INFO2_MASK_BREM_Msk (0x100UL) /*!< BREM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Pos (6UL) /*!< RSPTOM (Bit 6) */
|
|
|
+ #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Msk (0x40UL) /*!< RSPTOM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_INFO2_MASK_ILRM_Pos (5UL) /*!< ILRM (Bit 5) */
|
|
|
+ #define R_SDHI0_SD_INFO2_MASK_ILRM_Msk (0x20UL) /*!< ILRM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_INFO2_MASK_ILWM_Pos (4UL) /*!< ILWM (Bit 4) */
|
|
|
+ #define R_SDHI0_SD_INFO2_MASK_ILWM_Msk (0x10UL) /*!< ILWM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_INFO2_MASK_DTOM_Pos (3UL) /*!< DTOM (Bit 3) */
|
|
|
+ #define R_SDHI0_SD_INFO2_MASK_DTOM_Msk (0x8UL) /*!< DTOM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_INFO2_MASK_ENDEM_Pos (2UL) /*!< ENDEM (Bit 2) */
|
|
|
+ #define R_SDHI0_SD_INFO2_MASK_ENDEM_Msk (0x4UL) /*!< ENDEM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_INFO2_MASK_CRCEM_Pos (1UL) /*!< CRCEM (Bit 1) */
|
|
|
+ #define R_SDHI0_SD_INFO2_MASK_CRCEM_Msk (0x2UL) /*!< CRCEM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_INFO2_MASK_CMDEM_Pos (0UL) /*!< CMDEM (Bit 0) */
|
|
|
+ #define R_SDHI0_SD_INFO2_MASK_CMDEM_Msk (0x1UL) /*!< CMDEM (Bitfield-Mask: 0x01) */
|
|
|
+/* ====================================================== SD_CLK_CTRL ====================================================== */
|
|
|
+ #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Pos (9UL) /*!< CLKCTRLEN (Bit 9) */
|
|
|
+ #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Msk (0x200UL) /*!< CLKCTRLEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_CLK_CTRL_CLKEN_Pos (8UL) /*!< CLKEN (Bit 8) */
|
|
|
+ #define R_SDHI0_SD_CLK_CTRL_CLKEN_Msk (0x100UL) /*!< CLKEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Pos (0UL) /*!< CLKSEL (Bit 0) */
|
|
|
+ #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Msk (0xffUL) /*!< CLKSEL (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== SD_SIZE ======================================================== */
|
|
|
+ #define R_SDHI0_SD_SIZE_LEN_Pos (0UL) /*!< LEN (Bit 0) */
|
|
|
+ #define R_SDHI0_SD_SIZE_LEN_Msk (0x3ffUL) /*!< LEN (Bitfield-Mask: 0x3ff) */
|
|
|
+/* ======================================================= SD_OPTION ======================================================= */
|
|
|
+ #define R_SDHI0_SD_OPTION_WIDTH_Pos (15UL) /*!< WIDTH (Bit 15) */
|
|
|
+ #define R_SDHI0_SD_OPTION_WIDTH_Msk (0x8000UL) /*!< WIDTH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_OPTION_WIDTH8_Pos (13UL) /*!< WIDTH8 (Bit 13) */
|
|
|
+ #define R_SDHI0_SD_OPTION_WIDTH8_Msk (0x2000UL) /*!< WIDTH8 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_OPTION_TOUTMASK_Pos (8UL) /*!< TOUTMASK (Bit 8) */
|
|
|
+ #define R_SDHI0_SD_OPTION_TOUTMASK_Msk (0x100UL) /*!< TOUTMASK (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_OPTION_TOP_Pos (4UL) /*!< TOP (Bit 4) */
|
|
|
+ #define R_SDHI0_SD_OPTION_TOP_Msk (0xf0UL) /*!< TOP (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_SDHI0_SD_OPTION_CTOP_Pos (0UL) /*!< CTOP (Bit 0) */
|
|
|
+ #define R_SDHI0_SD_OPTION_CTOP_Msk (0xfUL) /*!< CTOP (Bitfield-Mask: 0x0f) */
|
|
|
+/* ====================================================== SD_ERR_STS1 ====================================================== */
|
|
|
+ #define R_SDHI0_SD_ERR_STS1_CRCTK_Pos (12UL) /*!< CRCTK (Bit 12) */
|
|
|
+ #define R_SDHI0_SD_ERR_STS1_CRCTK_Msk (0x7000UL) /*!< CRCTK (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_SDHI0_SD_ERR_STS1_CRCTKE_Pos (11UL) /*!< CRCTKE (Bit 11) */
|
|
|
+ #define R_SDHI0_SD_ERR_STS1_CRCTKE_Msk (0x800UL) /*!< CRCTKE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_ERR_STS1_RDCRCE_Pos (10UL) /*!< RDCRCE (Bit 10) */
|
|
|
+ #define R_SDHI0_SD_ERR_STS1_RDCRCE_Msk (0x400UL) /*!< RDCRCE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Pos (9UL) /*!< RSPCRCE1 (Bit 9) */
|
|
|
+ #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Msk (0x200UL) /*!< RSPCRCE1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Pos (8UL) /*!< RSPCRCE0 (Bit 8) */
|
|
|
+ #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Msk (0x100UL) /*!< RSPCRCE0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_ERR_STS1_CRCLENE_Pos (5UL) /*!< CRCLENE (Bit 5) */
|
|
|
+ #define R_SDHI0_SD_ERR_STS1_CRCLENE_Msk (0x20UL) /*!< CRCLENE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_ERR_STS1_RDLENE_Pos (4UL) /*!< RDLENE (Bit 4) */
|
|
|
+ #define R_SDHI0_SD_ERR_STS1_RDLENE_Msk (0x10UL) /*!< RDLENE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Pos (3UL) /*!< RSPLENE1 (Bit 3) */
|
|
|
+ #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Msk (0x8UL) /*!< RSPLENE1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Pos (2UL) /*!< RSPLENE0 (Bit 2) */
|
|
|
+ #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Msk (0x4UL) /*!< RSPLENE0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_ERR_STS1_CMDE1_Pos (1UL) /*!< CMDE1 (Bit 1) */
|
|
|
+ #define R_SDHI0_SD_ERR_STS1_CMDE1_Msk (0x2UL) /*!< CMDE1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_ERR_STS1_CMDE0_Pos (0UL) /*!< CMDE0 (Bit 0) */
|
|
|
+ #define R_SDHI0_SD_ERR_STS1_CMDE0_Msk (0x1UL) /*!< CMDE0 (Bitfield-Mask: 0x01) */
|
|
|
+/* ====================================================== SD_ERR_STS2 ====================================================== */
|
|
|
+ #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Pos (6UL) /*!< CRCBSYTO (Bit 6) */
|
|
|
+ #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Msk (0x40UL) /*!< CRCBSYTO (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_ERR_STS2_CRCTO_Pos (5UL) /*!< CRCTO (Bit 5) */
|
|
|
+ #define R_SDHI0_SD_ERR_STS2_CRCTO_Msk (0x20UL) /*!< CRCTO (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_ERR_STS2_RDTO_Pos (4UL) /*!< RDTO (Bit 4) */
|
|
|
+ #define R_SDHI0_SD_ERR_STS2_RDTO_Msk (0x10UL) /*!< RDTO (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_ERR_STS2_BSYTO1_Pos (3UL) /*!< BSYTO1 (Bit 3) */
|
|
|
+ #define R_SDHI0_SD_ERR_STS2_BSYTO1_Msk (0x8UL) /*!< BSYTO1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_ERR_STS2_BSYTO0_Pos (2UL) /*!< BSYTO0 (Bit 2) */
|
|
|
+ #define R_SDHI0_SD_ERR_STS2_BSYTO0_Msk (0x4UL) /*!< BSYTO0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_ERR_STS2_RSPTO1_Pos (1UL) /*!< RSPTO1 (Bit 1) */
|
|
|
+ #define R_SDHI0_SD_ERR_STS2_RSPTO1_Msk (0x2UL) /*!< RSPTO1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SD_ERR_STS2_RSPTO0_Pos (0UL) /*!< RSPTO0 (Bit 0) */
|
|
|
+ #define R_SDHI0_SD_ERR_STS2_RSPTO0_Msk (0x1UL) /*!< RSPTO0 (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== SD_BUF0 ======================================================== */
|
|
|
+ #define R_SDHI0_SD_BUF0_SD_BUF_Pos (0UL) /*!< SD_BUF (Bit 0) */
|
|
|
+ #define R_SDHI0_SD_BUF0_SD_BUF_Msk (0xffffffffUL) /*!< SD_BUF (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================= SDIO_MODE ======================================================= */
|
|
|
+ #define R_SDHI0_SDIO_MODE_C52PUB_Pos (9UL) /*!< C52PUB (Bit 9) */
|
|
|
+ #define R_SDHI0_SDIO_MODE_C52PUB_Msk (0x200UL) /*!< C52PUB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SDIO_MODE_IOABT_Pos (8UL) /*!< IOABT (Bit 8) */
|
|
|
+ #define R_SDHI0_SDIO_MODE_IOABT_Msk (0x100UL) /*!< IOABT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SDIO_MODE_RWREQ_Pos (2UL) /*!< RWREQ (Bit 2) */
|
|
|
+ #define R_SDHI0_SDIO_MODE_RWREQ_Msk (0x4UL) /*!< RWREQ (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SDIO_MODE_INTEN_Pos (0UL) /*!< INTEN (Bit 0) */
|
|
|
+ #define R_SDHI0_SDIO_MODE_INTEN_Msk (0x1UL) /*!< INTEN (Bitfield-Mask: 0x01) */
|
|
|
+/* ====================================================== SDIO_INFO1 ======================================================= */
|
|
|
+ #define R_SDHI0_SDIO_INFO1_EXWT_Pos (15UL) /*!< EXWT (Bit 15) */
|
|
|
+ #define R_SDHI0_SDIO_INFO1_EXWT_Msk (0x8000UL) /*!< EXWT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SDIO_INFO1_EXPUB52_Pos (14UL) /*!< EXPUB52 (Bit 14) */
|
|
|
+ #define R_SDHI0_SDIO_INFO1_EXPUB52_Msk (0x4000UL) /*!< EXPUB52 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SDIO_INFO1_IOIRQ_Pos (0UL) /*!< IOIRQ (Bit 0) */
|
|
|
+ #define R_SDHI0_SDIO_INFO1_IOIRQ_Msk (0x1UL) /*!< IOIRQ (Bitfield-Mask: 0x01) */
|
|
|
+/* ==================================================== SDIO_INFO1_MASK ==================================================== */
|
|
|
+ #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Pos (15UL) /*!< EXWTM (Bit 15) */
|
|
|
+ #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Msk (0x8000UL) /*!< EXWTM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Pos (14UL) /*!< EXPUB52M (Bit 14) */
|
|
|
+ #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Msk (0x4000UL) /*!< EXPUB52M (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Pos (0UL) /*!< IOIRQM (Bit 0) */
|
|
|
+ #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Msk (0x1UL) /*!< IOIRQM (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= SD_DMAEN ======================================================== */
|
|
|
+ #define R_SDHI0_SD_DMAEN_DMAEN_Pos (1UL) /*!< DMAEN (Bit 1) */
|
|
|
+ #define R_SDHI0_SD_DMAEN_DMAEN_Msk (0x2UL) /*!< DMAEN (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= SOFT_RST ======================================================== */
|
|
|
+ #define R_SDHI0_SOFT_RST_SDRST_Pos (0UL) /*!< SDRST (Bit 0) */
|
|
|
+ #define R_SDHI0_SOFT_RST_SDRST_Msk (0x1UL) /*!< SDRST (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= SDIF_MODE ======================================================= */
|
|
|
+ #define R_SDHI0_SDIF_MODE_NOCHKCR_Pos (8UL) /*!< NOCHKCR (Bit 8) */
|
|
|
+ #define R_SDHI0_SDIF_MODE_NOCHKCR_Msk (0x100UL) /*!< NOCHKCR (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= EXT_SWAP ======================================================== */
|
|
|
+ #define R_SDHI0_EXT_SWAP_BRSWP_Pos (7UL) /*!< BRSWP (Bit 7) */
|
|
|
+ #define R_SDHI0_EXT_SWAP_BRSWP_Msk (0x80UL) /*!< BRSWP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SDHI0_EXT_SWAP_BWSWP_Pos (6UL) /*!< BWSWP (Bit 6) */
|
|
|
+ #define R_SDHI0_EXT_SWAP_BWSWP_Msk (0x40UL) /*!< BWSWP (Bitfield-Mask: 0x01) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_SPI0 ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================= SPCR ========================================================== */
|
|
|
+ #define R_SPI0_SPCR_SPRIE_Pos (7UL) /*!< SPRIE (Bit 7) */
|
|
|
+ #define R_SPI0_SPCR_SPRIE_Msk (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI0_SPCR_SPE_Pos (6UL) /*!< SPE (Bit 6) */
|
|
|
+ #define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI0_SPCR_SPTIE_Pos (5UL) /*!< SPTIE (Bit 5) */
|
|
|
+ #define R_SPI0_SPCR_SPTIE_Msk (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI0_SPCR_SPEIE_Pos (4UL) /*!< SPEIE (Bit 4) */
|
|
|
+ #define R_SPI0_SPCR_SPEIE_Msk (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI0_SPCR_MSTR_Pos (3UL) /*!< MSTR (Bit 3) */
|
|
|
+ #define R_SPI0_SPCR_MSTR_Msk (0x8UL) /*!< MSTR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI0_SPCR_MODFEN_Pos (2UL) /*!< MODFEN (Bit 2) */
|
|
|
+ #define R_SPI0_SPCR_MODFEN_Msk (0x4UL) /*!< MODFEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI0_SPCR_TXMD_Pos (1UL) /*!< TXMD (Bit 1) */
|
|
|
+ #define R_SPI0_SPCR_TXMD_Msk (0x2UL) /*!< TXMD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI0_SPCR_SPMS_Pos (0UL) /*!< SPMS (Bit 0) */
|
|
|
+ #define R_SPI0_SPCR_SPMS_Msk (0x1UL) /*!< SPMS (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= SSLP ========================================================== */
|
|
|
+ #define R_SPI0_SSLP_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */
|
|
|
+ #define R_SPI0_SSLP_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI0_SSLP_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */
|
|
|
+ #define R_SPI0_SSLP_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI0_SSLP_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */
|
|
|
+ #define R_SPI0_SSLP_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI0_SSLP_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */
|
|
|
+ #define R_SPI0_SSLP_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI0_SSLP_SSL4P_Pos (4UL) /*!< SSL4P (Bit 4) */
|
|
|
+ #define R_SPI0_SSLP_SSL4P_Msk (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI0_SSLP_SSL5P_Pos (5UL) /*!< SSL5P (Bit 5) */
|
|
|
+ #define R_SPI0_SSLP_SSL5P_Msk (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI0_SSLP_SSL6P_Pos (6UL) /*!< SSL6P (Bit 6) */
|
|
|
+ #define R_SPI0_SSLP_SSL6P_Msk (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI0_SSLP_SSL7P_Pos (7UL) /*!< SSL7P (Bit 7) */
|
|
|
+ #define R_SPI0_SSLP_SSL7P_Msk (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= SPPCR ========================================================= */
|
|
|
+ #define R_SPI0_SPPCR_MOIFE_Pos (5UL) /*!< MOIFE (Bit 5) */
|
|
|
+ #define R_SPI0_SPPCR_MOIFE_Msk (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI0_SPPCR_MOIFV_Pos (4UL) /*!< MOIFV (Bit 4) */
|
|
|
+ #define R_SPI0_SPPCR_MOIFV_Msk (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI0_SPPCR_SPLP2_Pos (1UL) /*!< SPLP2 (Bit 1) */
|
|
|
+ #define R_SPI0_SPPCR_SPLP2_Msk (0x2UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI0_SPPCR_SPLP_Pos (0UL) /*!< SPLP (Bit 0) */
|
|
|
+ #define R_SPI0_SPPCR_SPLP_Msk (0x1UL) /*!< SPLP (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= SPSR ========================================================== */
|
|
|
+ #define R_SPI0_SPSR_SPRF_Pos (7UL) /*!< SPRF (Bit 7) */
|
|
|
+ #define R_SPI0_SPSR_SPRF_Msk (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI0_SPSR_SPTEF_Pos (5UL) /*!< SPTEF (Bit 5) */
|
|
|
+ #define R_SPI0_SPSR_SPTEF_Msk (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI0_SPSR_UDRF_Pos (4UL) /*!< UDRF (Bit 4) */
|
|
|
+ #define R_SPI0_SPSR_UDRF_Msk (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI0_SPSR_PERF_Pos (3UL) /*!< PERF (Bit 3) */
|
|
|
+ #define R_SPI0_SPSR_PERF_Msk (0x8UL) /*!< PERF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI0_SPSR_MODF_Pos (2UL) /*!< MODF (Bit 2) */
|
|
|
+ #define R_SPI0_SPSR_MODF_Msk (0x4UL) /*!< MODF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI0_SPSR_IDLNF_Pos (1UL) /*!< IDLNF (Bit 1) */
|
|
|
+ #define R_SPI0_SPSR_IDLNF_Msk (0x2UL) /*!< IDLNF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI0_SPSR_OVRF_Pos (0UL) /*!< OVRF (Bit 0) */
|
|
|
+ #define R_SPI0_SPSR_OVRF_Msk (0x1UL) /*!< OVRF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI0_SPSR_CENDF_Pos (6UL) /*!< CENDF (Bit 6) */
|
|
|
+ #define R_SPI0_SPSR_CENDF_Msk (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= SPDR ========================================================== */
|
|
|
+/* ======================================================== SPDR_HA ======================================================== */
|
|
|
+/* ======================================================== SPDR_BY ======================================================== */
|
|
|
+/* ========================================================= SPSCR ========================================================= */
|
|
|
+ #define R_SPI0_SPSCR_SPSLN_Pos (0UL) /*!< SPSLN (Bit 0) */
|
|
|
+ #define R_SPI0_SPSCR_SPSLN_Msk (0x7UL) /*!< SPSLN (Bitfield-Mask: 0x07) */
|
|
|
+/* ========================================================= SPBR ========================================================== */
|
|
|
+ #define R_SPI0_SPBR_SPR_Pos (0UL) /*!< SPR (Bit 0) */
|
|
|
+ #define R_SPI0_SPBR_SPR_Msk (0xffUL) /*!< SPR (Bitfield-Mask: 0xff) */
|
|
|
+/* ========================================================= SPDCR ========================================================= */
|
|
|
+ #define R_SPI0_SPDCR_SPBYT_Pos (6UL) /*!< SPBYT (Bit 6) */
|
|
|
+ #define R_SPI0_SPDCR_SPBYT_Msk (0x40UL) /*!< SPBYT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI0_SPDCR_SPLW_Pos (5UL) /*!< SPLW (Bit 5) */
|
|
|
+ #define R_SPI0_SPDCR_SPLW_Msk (0x20UL) /*!< SPLW (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI0_SPDCR_SPRDTD_Pos (4UL) /*!< SPRDTD (Bit 4) */
|
|
|
+ #define R_SPI0_SPDCR_SPRDTD_Msk (0x10UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI0_SPDCR_SPFC_Pos (0UL) /*!< SPFC (Bit 0) */
|
|
|
+ #define R_SPI0_SPDCR_SPFC_Msk (0x3UL) /*!< SPFC (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_SPI0_SPDCR_SLSEL_Pos (2UL) /*!< SLSEL (Bit 2) */
|
|
|
+ #define R_SPI0_SPDCR_SLSEL_Msk (0xcUL) /*!< SLSEL (Bitfield-Mask: 0x03) */
|
|
|
+/* ========================================================= SPCKD ========================================================= */
|
|
|
+ #define R_SPI0_SPCKD_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */
|
|
|
+ #define R_SPI0_SPCKD_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */
|
|
|
+/* ========================================================= SSLND ========================================================= */
|
|
|
+ #define R_SPI0_SSLND_SLNDL_Pos (0UL) /*!< SLNDL (Bit 0) */
|
|
|
+ #define R_SPI0_SSLND_SLNDL_Msk (0x7UL) /*!< SLNDL (Bitfield-Mask: 0x07) */
|
|
|
+/* ========================================================= SPND ========================================================== */
|
|
|
+ #define R_SPI0_SPND_SPNDL_Pos (0UL) /*!< SPNDL (Bit 0) */
|
|
|
+ #define R_SPI0_SPND_SPNDL_Msk (0x7UL) /*!< SPNDL (Bitfield-Mask: 0x07) */
|
|
|
+/* ========================================================= SPCR2 ========================================================= */
|
|
|
+ #define R_SPI0_SPCR2_SCKASE_Pos (4UL) /*!< SCKASE (Bit 4) */
|
|
|
+ #define R_SPI0_SPCR2_SCKASE_Msk (0x10UL) /*!< SCKASE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI0_SPCR2_PTE_Pos (3UL) /*!< PTE (Bit 3) */
|
|
|
+ #define R_SPI0_SPCR2_PTE_Msk (0x8UL) /*!< PTE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI0_SPCR2_SPIIE_Pos (2UL) /*!< SPIIE (Bit 2) */
|
|
|
+ #define R_SPI0_SPCR2_SPIIE_Msk (0x4UL) /*!< SPIIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI0_SPCR2_SPOE_Pos (1UL) /*!< SPOE (Bit 1) */
|
|
|
+ #define R_SPI0_SPCR2_SPOE_Msk (0x2UL) /*!< SPOE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI0_SPCR2_SPPE_Pos (0UL) /*!< SPPE (Bit 0) */
|
|
|
+ #define R_SPI0_SPCR2_SPPE_Msk (0x1UL) /*!< SPPE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI0_SPCR2_SPTDDL_Pos (5UL) /*!< SPTDDL (Bit 5) */
|
|
|
+ #define R_SPI0_SPCR2_SPTDDL_Msk (0xe0UL) /*!< SPTDDL (Bitfield-Mask: 0x07) */
|
|
|
+/* ========================================================= SPCMD ========================================================= */
|
|
|
+ #define R_SPI0_SPCMD_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */
|
|
|
+ #define R_SPI0_SPCMD_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI0_SPCMD_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */
|
|
|
+ #define R_SPI0_SPCMD_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI0_SPCMD_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */
|
|
|
+ #define R_SPI0_SPCMD_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI0_SPCMD_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */
|
|
|
+ #define R_SPI0_SPCMD_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI0_SPCMD_SPB_Pos (8UL) /*!< SPB (Bit 8) */
|
|
|
+ #define R_SPI0_SPCMD_SPB_Msk (0xf00UL) /*!< SPB (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_SPI0_SPCMD_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */
|
|
|
+ #define R_SPI0_SPCMD_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI0_SPCMD_SSLA_Pos (4UL) /*!< SSLA (Bit 4) */
|
|
|
+ #define R_SPI0_SPCMD_SSLA_Msk (0x70UL) /*!< SSLA (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_SPI0_SPCMD_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */
|
|
|
+ #define R_SPI0_SPCMD_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_SPI0_SPCMD_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */
|
|
|
+ #define R_SPI0_SPCMD_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI0_SPCMD_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */
|
|
|
+ #define R_SPI0_SPCMD_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== SPDCR2 ========================================================= */
|
|
|
+ #define R_SPI0_SPDCR2_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */
|
|
|
+ #define R_SPI0_SPDCR2_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI0_SPDCR2_SINV_Pos (1UL) /*!< SINV (Bit 1) */
|
|
|
+ #define R_SPI0_SPDCR2_SINV_Msk (0x2UL) /*!< SINV (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= SPSSR ========================================================= */
|
|
|
+ #define R_SPI0_SPSSR_SPCP_Pos (0UL) /*!< SPCP (Bit 0) */
|
|
|
+ #define R_SPI0_SPSSR_SPCP_Msk (0x7UL) /*!< SPCP (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_SPI0_SPSSR_SPECM_Pos (4UL) /*!< SPECM (Bit 4) */
|
|
|
+ #define R_SPI0_SPSSR_SPECM_Msk (0x70UL) /*!< SPECM (Bitfield-Mask: 0x07) */
|
|
|
+/* ========================================================= SPCR3 ========================================================= */
|
|
|
+ #define R_SPI0_SPCR3_ETXMD_Pos (0UL) /*!< ETXMD (Bit 0) */
|
|
|
+ #define R_SPI0_SPCR3_ETXMD_Msk (0x1UL) /*!< ETXMD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI0_SPCR3_BFDS_Pos (1UL) /*!< BFDS (Bit 1) */
|
|
|
+ #define R_SPI0_SPCR3_BFDS_Msk (0x2UL) /*!< BFDS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI0_SPCR3_CENDIE_Pos (4UL) /*!< CENDIE (Bit 4) */
|
|
|
+ #define R_SPI0_SPCR3_CENDIE_Msk (0x10UL) /*!< CENDIE (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= SPPR ========================================================== */
|
|
|
+ #define R_SPI0_SPPR_BUFWID_Pos (4UL) /*!< BUFWID (Bit 4) */
|
|
|
+ #define R_SPI0_SPPR_BUFWID_Msk (0x10UL) /*!< BUFWID (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI0_SPPR_BUFNUM_Pos (8UL) /*!< BUFNUM (Bit 8) */
|
|
|
+ #define R_SPI0_SPPR_BUFNUM_Msk (0x700UL) /*!< BUFNUM (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_SPI0_SPPR_CMDNUM_Pos (12UL) /*!< CMDNUM (Bit 12) */
|
|
|
+ #define R_SPI0_SPPR_CMDNUM_Msk (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_SRAM ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ======================================================= SRAMPRCR ======================================================== */
|
|
|
+ #define R_SRAM_SRAMPRCR_PR_Pos (0UL) /*!< PR (Bit 0) */
|
|
|
+ #define R_SRAM_SRAMPRCR_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SRAM_SRAMPRCR_KW_Pos (8UL) /*!< KW (Bit 8) */
|
|
|
+ #define R_SRAM_SRAMPRCR_KW_Msk (0xff00UL) /*!< KW (Bitfield-Mask: 0xff) */
|
|
|
+/* ====================================================== SRAMPRCR_NS ====================================================== */
|
|
|
+ #define R_SRAM_SRAMPRCR_NS_PR_Pos (0UL) /*!< PR (Bit 0) */
|
|
|
+ #define R_SRAM_SRAMPRCR_NS_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SRAM_SRAMPRCR_NS_KW_Pos (8UL) /*!< KW (Bit 8) */
|
|
|
+ #define R_SRAM_SRAMPRCR_NS_KW_Msk (0xff00UL) /*!< KW (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= SRAMWTSC ======================================================== */
|
|
|
+ #define R_SRAM_SRAMWTSC_WTEN_Pos (0UL) /*!< WTEN (Bit 0) */
|
|
|
+ #define R_SRAM_SRAMWTSC_WTEN_Msk (0x1UL) /*!< WTEN (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== SRAMCR0 ======================================================== */
|
|
|
+ #define R_SRAM_SRAMCR0_OAD_Pos (0UL) /*!< OAD (Bit 0) */
|
|
|
+ #define R_SRAM_SRAMCR0_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SRAM_SRAMCR0_ECCMOD_Pos (2UL) /*!< ECCMOD (Bit 2) */
|
|
|
+ #define R_SRAM_SRAMCR0_ECCMOD_Msk (0xcUL) /*!< ECCMOD (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_SRAM_SRAMCR0_E1STSEN_Pos (4UL) /*!< E1STSEN (Bit 4) */
|
|
|
+ #define R_SRAM_SRAMCR0_E1STSEN_Msk (0x10UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SRAM_SRAMCR0_TSTBYP_Pos (7UL) /*!< TSTBYP (Bit 7) */
|
|
|
+ #define R_SRAM_SRAMCR0_TSTBYP_Msk (0x80UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== SRAMCR1 ======================================================== */
|
|
|
+ #define R_SRAM_SRAMCR1_OAD_Pos (0UL) /*!< OAD (Bit 0) */
|
|
|
+ #define R_SRAM_SRAMCR1_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */
|
|
|
+/* ====================================================== SRAMECCRGN0 ====================================================== */
|
|
|
+ #define R_SRAM_SRAMECCRGN0_ECCRGN_Pos (0UL) /*!< ECCRGN (Bit 0) */
|
|
|
+ #define R_SRAM_SRAMECCRGN0_ECCRGN_Msk (0x3UL) /*!< ECCRGN (Bitfield-Mask: 0x03) */
|
|
|
+/* ======================================================== SRAMESR ======================================================== */
|
|
|
+ #define R_SRAM_SRAMESR_ERR00_Pos (0UL) /*!< ERR00 (Bit 0) */
|
|
|
+ #define R_SRAM_SRAMESR_ERR00_Msk (0x1UL) /*!< ERR00 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SRAM_SRAMESR_ERR01_Pos (1UL) /*!< ERR01 (Bit 1) */
|
|
|
+ #define R_SRAM_SRAMESR_ERR01_Msk (0x2UL) /*!< ERR01 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SRAM_SRAMESR_ERR1_Pos (2UL) /*!< ERR1 (Bit 2) */
|
|
|
+ #define R_SRAM_SRAMESR_ERR1_Msk (0x4UL) /*!< ERR1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SRAM_SRAMESR_ERRS_Pos (14UL) /*!< ERRS (Bit 14) */
|
|
|
+ #define R_SRAM_SRAMESR_ERRS_Msk (0x4000UL) /*!< ERRS (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= SRAMESCLR ======================================================= */
|
|
|
+ #define R_SRAM_SRAMESCLR_CLR00_Pos (0UL) /*!< CLR00 (Bit 0) */
|
|
|
+ #define R_SRAM_SRAMESCLR_CLR00_Msk (0x1UL) /*!< CLR00 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SRAM_SRAMESCLR_CLR01_Pos (1UL) /*!< CLR01 (Bit 1) */
|
|
|
+ #define R_SRAM_SRAMESCLR_CLR01_Msk (0x2UL) /*!< CLR01 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SRAM_SRAMESCLR_CLR1_Pos (2UL) /*!< CLR1 (Bit 2) */
|
|
|
+ #define R_SRAM_SRAMESCLR_CLR1_Msk (0x4UL) /*!< CLR1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SRAM_SRAMESCLR_CLRS_Pos (14UL) /*!< CLRS (Bit 14) */
|
|
|
+ #define R_SRAM_SRAMESCLR_CLRS_Msk (0x4000UL) /*!< CLRS (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= SRAMEAR0 ======================================================== */
|
|
|
+ #define R_SRAM_SRAMEAR0_EA_Pos (3UL) /*!< EA (Bit 3) */
|
|
|
+ #define R_SRAM_SRAMEAR0_EA_Msk (0xffff8UL) /*!< EA (Bitfield-Mask: 0x1ffff) */
|
|
|
+/* ======================================================= SRAMEAR1 ======================================================== */
|
|
|
+ #define R_SRAM_SRAMEAR1_EA_Pos (3UL) /*!< EA (Bit 3) */
|
|
|
+ #define R_SRAM_SRAMEAR1_EA_Msk (0xffff8UL) /*!< EA (Bitfield-Mask: 0x1ffff) */
|
|
|
+/* ======================================================= SRAMEAR2 ======================================================== */
|
|
|
+ #define R_SRAM_SRAMEAR2_EA_Pos (3UL) /*!< EA (Bit 3) */
|
|
|
+ #define R_SRAM_SRAMEAR2_EA_Msk (0xffff8UL) /*!< EA (Bitfield-Mask: 0x1ffff) */
|
|
|
+/* ======================================================= STBRAMCR ======================================================== */
|
|
|
+ #define R_SRAM_STBRAMCR_OAD_Pos (0UL) /*!< OAD (Bit 0) */
|
|
|
+ #define R_SRAM_STBRAMCR_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= STBRAMEAR ======================================================= */
|
|
|
+ #define R_SRAM_STBRAMEAR_EA_Pos (2UL) /*!< EA (Bit 2) */
|
|
|
+ #define R_SRAM_STBRAMEAR_EA_Msk (0x3fcUL) /*!< EA (Bitfield-Mask: 0xff) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_SSI0 ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================= SSICR ========================================================= */
|
|
|
+ #define R_SSI0_SSICR_CKS_Pos (30UL) /*!< CKS (Bit 30) */
|
|
|
+ #define R_SSI0_SSICR_CKS_Msk (0x40000000UL) /*!< CKS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SSI0_SSICR_TUIEN_Pos (29UL) /*!< TUIEN (Bit 29) */
|
|
|
+ #define R_SSI0_SSICR_TUIEN_Msk (0x20000000UL) /*!< TUIEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SSI0_SSICR_TOIEN_Pos (28UL) /*!< TOIEN (Bit 28) */
|
|
|
+ #define R_SSI0_SSICR_TOIEN_Msk (0x10000000UL) /*!< TOIEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SSI0_SSICR_RUIEN_Pos (27UL) /*!< RUIEN (Bit 27) */
|
|
|
+ #define R_SSI0_SSICR_RUIEN_Msk (0x8000000UL) /*!< RUIEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SSI0_SSICR_ROIEN_Pos (26UL) /*!< ROIEN (Bit 26) */
|
|
|
+ #define R_SSI0_SSICR_ROIEN_Msk (0x4000000UL) /*!< ROIEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SSI0_SSICR_IIEN_Pos (25UL) /*!< IIEN (Bit 25) */
|
|
|
+ #define R_SSI0_SSICR_IIEN_Msk (0x2000000UL) /*!< IIEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SSI0_SSICR_FRM_Pos (22UL) /*!< FRM (Bit 22) */
|
|
|
+ #define R_SSI0_SSICR_FRM_Msk (0xc00000UL) /*!< FRM (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_SSI0_SSICR_DWL_Pos (19UL) /*!< DWL (Bit 19) */
|
|
|
+ #define R_SSI0_SSICR_DWL_Msk (0x380000UL) /*!< DWL (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_SSI0_SSICR_SWL_Pos (16UL) /*!< SWL (Bit 16) */
|
|
|
+ #define R_SSI0_SSICR_SWL_Msk (0x70000UL) /*!< SWL (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_SSI0_SSICR_MST_Pos (14UL) /*!< MST (Bit 14) */
|
|
|
+ #define R_SSI0_SSICR_MST_Msk (0x4000UL) /*!< MST (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SSI0_SSICR_BCKP_Pos (13UL) /*!< BCKP (Bit 13) */
|
|
|
+ #define R_SSI0_SSICR_BCKP_Msk (0x2000UL) /*!< BCKP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SSI0_SSICR_LRCKP_Pos (12UL) /*!< LRCKP (Bit 12) */
|
|
|
+ #define R_SSI0_SSICR_LRCKP_Msk (0x1000UL) /*!< LRCKP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SSI0_SSICR_SPDP_Pos (11UL) /*!< SPDP (Bit 11) */
|
|
|
+ #define R_SSI0_SSICR_SPDP_Msk (0x800UL) /*!< SPDP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SSI0_SSICR_SDTA_Pos (10UL) /*!< SDTA (Bit 10) */
|
|
|
+ #define R_SSI0_SSICR_SDTA_Msk (0x400UL) /*!< SDTA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SSI0_SSICR_PDTA_Pos (9UL) /*!< PDTA (Bit 9) */
|
|
|
+ #define R_SSI0_SSICR_PDTA_Msk (0x200UL) /*!< PDTA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SSI0_SSICR_DEL_Pos (8UL) /*!< DEL (Bit 8) */
|
|
|
+ #define R_SSI0_SSICR_DEL_Msk (0x100UL) /*!< DEL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SSI0_SSICR_CKDV_Pos (4UL) /*!< CKDV (Bit 4) */
|
|
|
+ #define R_SSI0_SSICR_CKDV_Msk (0xf0UL) /*!< CKDV (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_SSI0_SSICR_MUEN_Pos (3UL) /*!< MUEN (Bit 3) */
|
|
|
+ #define R_SSI0_SSICR_MUEN_Msk (0x8UL) /*!< MUEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SSI0_SSICR_TEN_Pos (1UL) /*!< TEN (Bit 1) */
|
|
|
+ #define R_SSI0_SSICR_TEN_Msk (0x2UL) /*!< TEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SSI0_SSICR_REN_Pos (0UL) /*!< REN (Bit 0) */
|
|
|
+ #define R_SSI0_SSICR_REN_Msk (0x1UL) /*!< REN (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= SSISR ========================================================= */
|
|
|
+ #define R_SSI0_SSISR_TUIRQ_Pos (29UL) /*!< TUIRQ (Bit 29) */
|
|
|
+ #define R_SSI0_SSISR_TUIRQ_Msk (0x20000000UL) /*!< TUIRQ (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SSI0_SSISR_TOIRQ_Pos (28UL) /*!< TOIRQ (Bit 28) */
|
|
|
+ #define R_SSI0_SSISR_TOIRQ_Msk (0x10000000UL) /*!< TOIRQ (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SSI0_SSISR_RUIRQ_Pos (27UL) /*!< RUIRQ (Bit 27) */
|
|
|
+ #define R_SSI0_SSISR_RUIRQ_Msk (0x8000000UL) /*!< RUIRQ (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SSI0_SSISR_ROIRQ_Pos (26UL) /*!< ROIRQ (Bit 26) */
|
|
|
+ #define R_SSI0_SSISR_ROIRQ_Msk (0x4000000UL) /*!< ROIRQ (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SSI0_SSISR_IIRQ_Pos (25UL) /*!< IIRQ (Bit 25) */
|
|
|
+ #define R_SSI0_SSISR_IIRQ_Msk (0x2000000UL) /*!< IIRQ (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SSI0_SSISR_TCHNO_Pos (5UL) /*!< TCHNO (Bit 5) */
|
|
|
+ #define R_SSI0_SSISR_TCHNO_Msk (0x60UL) /*!< TCHNO (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_SSI0_SSISR_TSWNO_Pos (4UL) /*!< TSWNO (Bit 4) */
|
|
|
+ #define R_SSI0_SSISR_TSWNO_Msk (0x10UL) /*!< TSWNO (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SSI0_SSISR_RCHNO_Pos (2UL) /*!< RCHNO (Bit 2) */
|
|
|
+ #define R_SSI0_SSISR_RCHNO_Msk (0xcUL) /*!< RCHNO (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_SSI0_SSISR_RSWNO_Pos (1UL) /*!< RSWNO (Bit 1) */
|
|
|
+ #define R_SSI0_SSISR_RSWNO_Msk (0x2UL) /*!< RSWNO (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SSI0_SSISR_IDST_Pos (0UL) /*!< IDST (Bit 0) */
|
|
|
+ #define R_SSI0_SSISR_IDST_Msk (0x1UL) /*!< IDST (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== SSIFCR ========================================================= */
|
|
|
+ #define R_SSI0_SSIFCR_AUCKE_Pos (31UL) /*!< AUCKE (Bit 31) */
|
|
|
+ #define R_SSI0_SSIFCR_AUCKE_Msk (0x80000000UL) /*!< AUCKE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SSI0_SSIFCR_SSIRST_Pos (16UL) /*!< SSIRST (Bit 16) */
|
|
|
+ #define R_SSI0_SSIFCR_SSIRST_Msk (0x10000UL) /*!< SSIRST (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SSI0_SSIFCR_TTRG_Pos (6UL) /*!< TTRG (Bit 6) */
|
|
|
+ #define R_SSI0_SSIFCR_TTRG_Msk (0xc0UL) /*!< TTRG (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_SSI0_SSIFCR_RTRG_Pos (4UL) /*!< RTRG (Bit 4) */
|
|
|
+ #define R_SSI0_SSIFCR_RTRG_Msk (0x30UL) /*!< RTRG (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_SSI0_SSIFCR_TIE_Pos (3UL) /*!< TIE (Bit 3) */
|
|
|
+ #define R_SSI0_SSIFCR_TIE_Msk (0x8UL) /*!< TIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SSI0_SSIFCR_RIE_Pos (2UL) /*!< RIE (Bit 2) */
|
|
|
+ #define R_SSI0_SSIFCR_RIE_Msk (0x4UL) /*!< RIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SSI0_SSIFCR_TFRST_Pos (1UL) /*!< TFRST (Bit 1) */
|
|
|
+ #define R_SSI0_SSIFCR_TFRST_Msk (0x2UL) /*!< TFRST (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SSI0_SSIFCR_RFRST_Pos (0UL) /*!< RFRST (Bit 0) */
|
|
|
+ #define R_SSI0_SSIFCR_RFRST_Msk (0x1UL) /*!< RFRST (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SSI0_SSIFCR_BSW_Pos (11UL) /*!< BSW (Bit 11) */
|
|
|
+ #define R_SSI0_SSIFCR_BSW_Msk (0x800UL) /*!< BSW (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== SSIFSR ========================================================= */
|
|
|
+ #define R_SSI0_SSIFSR_TDC_Pos (24UL) /*!< TDC (Bit 24) */
|
|
|
+ #define R_SSI0_SSIFSR_TDC_Msk (0x3f000000UL) /*!< TDC (Bitfield-Mask: 0x3f) */
|
|
|
+ #define R_SSI0_SSIFSR_TDE_Pos (16UL) /*!< TDE (Bit 16) */
|
|
|
+ #define R_SSI0_SSIFSR_TDE_Msk (0x10000UL) /*!< TDE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SSI0_SSIFSR_RDC_Pos (8UL) /*!< RDC (Bit 8) */
|
|
|
+ #define R_SSI0_SSIFSR_RDC_Msk (0x3f00UL) /*!< RDC (Bitfield-Mask: 0x3f) */
|
|
|
+ #define R_SSI0_SSIFSR_RDF_Pos (0UL) /*!< RDF (Bit 0) */
|
|
|
+ #define R_SSI0_SSIFSR_RDF_Msk (0x1UL) /*!< RDF (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== SSIFTDR ======================================================== */
|
|
|
+ #define R_SSI0_SSIFTDR_SSIFTDR_Pos (0UL) /*!< SSIFTDR (Bit 0) */
|
|
|
+ #define R_SSI0_SSIFTDR_SSIFTDR_Msk (0xffffffffUL) /*!< SSIFTDR (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================= SSIFTDR16 ======================================================= */
|
|
|
+/* ======================================================= SSIFTDR8 ======================================================== */
|
|
|
+/* ======================================================== SSIFRDR ======================================================== */
|
|
|
+ #define R_SSI0_SSIFRDR_SSIFRDR_Pos (0UL) /*!< SSIFRDR (Bit 0) */
|
|
|
+ #define R_SSI0_SSIFRDR_SSIFRDR_Msk (0xffffffffUL) /*!< SSIFRDR (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================= SSIFRDR16 ======================================================= */
|
|
|
+/* ======================================================= SSIFRDR8 ======================================================== */
|
|
|
+/* ======================================================== SSIOFR ========================================================= */
|
|
|
+ #define R_SSI0_SSIOFR_BCKASTP_Pos (9UL) /*!< BCKASTP (Bit 9) */
|
|
|
+ #define R_SSI0_SSIOFR_BCKASTP_Msk (0x200UL) /*!< BCKASTP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SSI0_SSIOFR_LRCONT_Pos (8UL) /*!< LRCONT (Bit 8) */
|
|
|
+ #define R_SSI0_SSIOFR_LRCONT_Msk (0x100UL) /*!< LRCONT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SSI0_SSIOFR_OMOD_Pos (0UL) /*!< OMOD (Bit 0) */
|
|
|
+ #define R_SSI0_SSIOFR_OMOD_Msk (0x3UL) /*!< OMOD (Bitfield-Mask: 0x03) */
|
|
|
+/* ======================================================== SSISCR ========================================================= */
|
|
|
+ #define R_SSI0_SSISCR_TDES_Pos (8UL) /*!< TDES (Bit 8) */
|
|
|
+ #define R_SSI0_SSISCR_TDES_Msk (0x1f00UL) /*!< TDES (Bitfield-Mask: 0x1f) */
|
|
|
+ #define R_SSI0_SSISCR_RDFS_Pos (0UL) /*!< RDFS (Bit 0) */
|
|
|
+ #define R_SSI0_SSISCR_RDFS_Msk (0x1fUL) /*!< RDFS (Bitfield-Mask: 0x1f) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_SYSTEM ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================= SBYCR ========================================================= */
|
|
|
+ #define R_SYSTEM_SBYCR_OPE_Pos (6UL) /*!< OPE (Bit 6) */
|
|
|
+ #define R_SYSTEM_SBYCR_OPE_Msk (0x40UL) /*!< OPE (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= SSCR2 ========================================================= */
|
|
|
+ #define R_SYSTEM_SSCR2_SS1RSF_Pos (0UL) /*!< SS1RSF (Bit 0) */
|
|
|
+ #define R_SYSTEM_SSCR2_SS1RSF_Msk (0x1UL) /*!< SS1RSF (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= FLSCR ========================================================= */
|
|
|
+ #define R_SYSTEM_FLSCR_FLSWCF_Pos (0UL) /*!< FLSWCF (Bit 0) */
|
|
|
+ #define R_SYSTEM_FLSCR_FLSWCF_Msk (0x1UL) /*!< FLSWCF (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== MSTPCRA ======================================================== */
|
|
|
+ #define R_SYSTEM_MSTPCRA_MSTPA_Pos (0UL) /*!< MSTPA (Bit 0) */
|
|
|
+ #define R_SYSTEM_MSTPCRA_MSTPA_Msk (0x1UL) /*!< MSTPA (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= SCKDIVCR ======================================================== */
|
|
|
+ #define R_SYSTEM_SCKDIVCR_FCK_Pos (28UL) /*!< FCK (Bit 28) */
|
|
|
+ #define R_SYSTEM_SCKDIVCR_FCK_Msk (0xf0000000UL) /*!< FCK (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_SYSTEM_SCKDIVCR_ICK_Pos (24UL) /*!< ICK (Bit 24) */
|
|
|
+ #define R_SYSTEM_SCKDIVCR_ICK_Msk (0xf000000UL) /*!< ICK (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_SYSTEM_SCKDIVCR_PCKE_Pos (20UL) /*!< PCKE (Bit 20) */
|
|
|
+ #define R_SYSTEM_SCKDIVCR_PCKE_Msk (0xf00000UL) /*!< PCKE (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_SYSTEM_SCKDIVCR_BCK_Pos (16UL) /*!< BCK (Bit 16) */
|
|
|
+ #define R_SYSTEM_SCKDIVCR_BCK_Msk (0xf0000UL) /*!< BCK (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_SYSTEM_SCKDIVCR_PCKA_Pos (12UL) /*!< PCKA (Bit 12) */
|
|
|
+ #define R_SYSTEM_SCKDIVCR_PCKA_Msk (0xf000UL) /*!< PCKA (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_SYSTEM_SCKDIVCR_PCKB_Pos (8UL) /*!< PCKB (Bit 8) */
|
|
|
+ #define R_SYSTEM_SCKDIVCR_PCKB_Msk (0xf00UL) /*!< PCKB (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_SYSTEM_SCKDIVCR_PCKC_Pos (4UL) /*!< PCKC (Bit 4) */
|
|
|
+ #define R_SYSTEM_SCKDIVCR_PCKC_Msk (0xf0UL) /*!< PCKC (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_SYSTEM_SCKDIVCR_PCKD_Pos (0UL) /*!< PCKD (Bit 0) */
|
|
|
+ #define R_SYSTEM_SCKDIVCR_PCKD_Msk (0xfUL) /*!< PCKD (Bitfield-Mask: 0x0f) */
|
|
|
+/* ======================================================= SCKDIVCR2 ======================================================= */
|
|
|
+ #define R_SYSTEM_SCKDIVCR2_CPUCK_Pos (0UL) /*!< CPUCK (Bit 0) */
|
|
|
+ #define R_SYSTEM_SCKDIVCR2_CPUCK_Msk (0xfUL) /*!< CPUCK (Bitfield-Mask: 0x0f) */
|
|
|
+/* ======================================================== SCKSCR ========================================================= */
|
|
|
+ #define R_SYSTEM_SCKSCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */
|
|
|
+ #define R_SYSTEM_SCKSCR_CKSEL_Msk (0x7UL) /*!< CKSEL (Bitfield-Mask: 0x07) */
|
|
|
+/* ======================================================== PLLCCR ========================================================= */
|
|
|
+ #define R_SYSTEM_PLLCCR_PLIDIV_Pos (0UL) /*!< PLIDIV (Bit 0) */
|
|
|
+ #define R_SYSTEM_PLLCCR_PLIDIV_Msk (0x3UL) /*!< PLIDIV (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos (4UL) /*!< PLSRCSEL (Bit 4) */
|
|
|
+ #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk (0x10UL) /*!< PLSRCSEL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_PLLCCR_PLLMULNF_Pos (6UL) /*!< PLLMULNF (Bit 6) */
|
|
|
+ #define R_SYSTEM_PLLCCR_PLLMULNF_Msk (0xc0UL) /*!< PLLMULNF (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_SYSTEM_PLLCCR_PLLMUL_Pos (8UL) /*!< PLLMUL (Bit 8) */
|
|
|
+ #define R_SYSTEM_PLLCCR_PLLMUL_Msk (0xff00UL) /*!< PLLMUL (Bitfield-Mask: 0xff) */
|
|
|
+/* ========================================================= PLLCR ========================================================= */
|
|
|
+ #define R_SYSTEM_PLLCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */
|
|
|
+ #define R_SYSTEM_PLLCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= BCKCR ========================================================= */
|
|
|
+ #define R_SYSTEM_BCKCR_BCLKDIV_Pos (0UL) /*!< BCLKDIV (Bit 0) */
|
|
|
+ #define R_SYSTEM_BCKCR_BCLKDIV_Msk (0x1UL) /*!< BCLKDIV (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== MOSCCR ========================================================= */
|
|
|
+ #define R_SYSTEM_MOSCCR_MOSTP_Pos (0UL) /*!< MOSTP (Bit 0) */
|
|
|
+ #define R_SYSTEM_MOSCCR_MOSTP_Msk (0x1UL) /*!< MOSTP (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== HOCOCR ========================================================= */
|
|
|
+ #define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */
|
|
|
+ #define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== MOCOCR ========================================================= */
|
|
|
+ #define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */
|
|
|
+ #define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== FLLCR1 ========================================================= */
|
|
|
+ #define R_SYSTEM_FLLCR1_FLLEN_Pos (0UL) /*!< FLLEN (Bit 0) */
|
|
|
+ #define R_SYSTEM_FLLCR1_FLLEN_Msk (0x1UL) /*!< FLLEN (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== FLLCR2 ========================================================= */
|
|
|
+ #define R_SYSTEM_FLLCR2_FLLCNTL_Pos (0UL) /*!< FLLCNTL (Bit 0) */
|
|
|
+ #define R_SYSTEM_FLLCR2_FLLCNTL_Msk (0x7ffUL) /*!< FLLCNTL (Bitfield-Mask: 0x7ff) */
|
|
|
+/* ========================================================= OSCSF ========================================================= */
|
|
|
+ #define R_SYSTEM_OSCSF_HOCOSF_Pos (0UL) /*!< HOCOSF (Bit 0) */
|
|
|
+ #define R_SYSTEM_OSCSF_HOCOSF_Msk (0x1UL) /*!< HOCOSF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_OSCSF_MOSCSF_Pos (3UL) /*!< MOSCSF (Bit 3) */
|
|
|
+ #define R_SYSTEM_OSCSF_MOSCSF_Msk (0x8UL) /*!< MOSCSF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_OSCSF_PLLSF_Pos (5UL) /*!< PLLSF (Bit 5) */
|
|
|
+ #define R_SYSTEM_OSCSF_PLLSF_Msk (0x20UL) /*!< PLLSF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_OSCSF_PLL2SF_Pos (6UL) /*!< PLL2SF (Bit 6) */
|
|
|
+ #define R_SYSTEM_OSCSF_PLL2SF_Msk (0x40UL) /*!< PLL2SF (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= CKOCR ========================================================= */
|
|
|
+ #define R_SYSTEM_CKOCR_CKODIV_Pos (4UL) /*!< CKODIV (Bit 4) */
|
|
|
+ #define R_SYSTEM_CKOCR_CKODIV_Msk (0x70UL) /*!< CKODIV (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_SYSTEM_CKOCR_CKOEN_Pos (7UL) /*!< CKOEN (Bit 7) */
|
|
|
+ #define R_SYSTEM_CKOCR_CKOEN_Msk (0x80UL) /*!< CKOEN (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== TRCKCR ========================================================= */
|
|
|
+ #define R_SYSTEM_TRCKCR_TRCK_Pos (0UL) /*!< TRCK (Bit 0) */
|
|
|
+ #define R_SYSTEM_TRCKCR_TRCK_Msk (0xfUL) /*!< TRCK (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_SYSTEM_TRCKCR_TRCKSEL_Pos (4UL) /*!< TRCKSEL (Bit 4) */
|
|
|
+ #define R_SYSTEM_TRCKCR_TRCKSEL_Msk (0x10UL) /*!< TRCKSEL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_TRCKCR_TRCKEN_Pos (7UL) /*!< TRCKEN (Bit 7) */
|
|
|
+ #define R_SYSTEM_TRCKCR_TRCKEN_Msk (0x80UL) /*!< TRCKEN (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== OSTDCR ========================================================= */
|
|
|
+ #define R_SYSTEM_OSTDCR_OSTDIE_Pos (0UL) /*!< OSTDIE (Bit 0) */
|
|
|
+ #define R_SYSTEM_OSTDCR_OSTDIE_Msk (0x1UL) /*!< OSTDIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_OSTDCR_OSTDE_Pos (7UL) /*!< OSTDE (Bit 7) */
|
|
|
+ #define R_SYSTEM_OSTDCR_OSTDE_Msk (0x80UL) /*!< OSTDE (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== OSTDSR ========================================================= */
|
|
|
+ #define R_SYSTEM_OSTDSR_OSTDF_Pos (0UL) /*!< OSTDF (Bit 0) */
|
|
|
+ #define R_SYSTEM_OSTDSR_OSTDF_Msk (0x1UL) /*!< OSTDF (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== OSCMONR ======================================================== */
|
|
|
+ #define R_SYSTEM_OSCMONR_MOCOMON_Pos (1UL) /*!< MOCOMON (Bit 1) */
|
|
|
+ #define R_SYSTEM_OSCMONR_MOCOMON_Msk (0x2UL) /*!< MOCOMON (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_OSCMONR_LOCOMON_Pos (2UL) /*!< LOCOMON (Bit 2) */
|
|
|
+ #define R_SYSTEM_OSCMONR_LOCOMON_Msk (0x4UL) /*!< LOCOMON (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== PLL2CCR ======================================================== */
|
|
|
+ #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos (0UL) /*!< PL2IDIV (Bit 0) */
|
|
|
+ #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk (0x3UL) /*!< PL2IDIV (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos (4UL) /*!< PL2SRCSEL (Bit 4) */
|
|
|
+ #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk (0x10UL) /*!< PL2SRCSEL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_PLL2CCR_PLL2MULNF_Pos (6UL) /*!< PLL2MULNF (Bit 6) */
|
|
|
+ #define R_SYSTEM_PLL2CCR_PLL2MULNF_Msk (0xc0UL) /*!< PLL2MULNF (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos (8UL) /*!< PLL2MUL (Bit 8) */
|
|
|
+ #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk (0xff00UL) /*!< PLL2MUL (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== PLL2CR ========================================================= */
|
|
|
+ #define R_SYSTEM_PLL2CR_PLL2STP_Pos (0UL) /*!< PLL2STP (Bit 0) */
|
|
|
+ #define R_SYSTEM_PLL2CR_PLL2STP_Msk (0x1UL) /*!< PLL2STP (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== PLLCCR2 ======================================================== */
|
|
|
+ #define R_SYSTEM_PLLCCR2_PLODIVP_Pos (0UL) /*!< PLODIVP (Bit 0) */
|
|
|
+ #define R_SYSTEM_PLLCCR2_PLODIVP_Msk (0xfUL) /*!< PLODIVP (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_SYSTEM_PLLCCR2_PLODIVQ_Pos (4UL) /*!< PLODIVQ (Bit 4) */
|
|
|
+ #define R_SYSTEM_PLLCCR2_PLODIVQ_Msk (0xf0UL) /*!< PLODIVQ (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_SYSTEM_PLLCCR2_PLODIVR_Pos (8UL) /*!< PLODIVR (Bit 8) */
|
|
|
+ #define R_SYSTEM_PLLCCR2_PLODIVR_Msk (0xf00UL) /*!< PLODIVR (Bitfield-Mask: 0x0f) */
|
|
|
+/* ======================================================= PLL2CCR2 ======================================================== */
|
|
|
+ #define R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos (0UL) /*!< PL2ODIVP (Bit 0) */
|
|
|
+ #define R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk (0xfUL) /*!< PL2ODIVP (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos (4UL) /*!< PL2ODIVQ (Bit 4) */
|
|
|
+ #define R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk (0xf0UL) /*!< PL2ODIVQ (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos (8UL) /*!< PL2ODIVR (Bit 8) */
|
|
|
+ #define R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk (0xf00UL) /*!< PL2ODIVR (Bitfield-Mask: 0x0f) */
|
|
|
+/* ======================================================== EBCKOCR ======================================================== */
|
|
|
+ #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos (0UL) /*!< EBCKOEN (Bit 0) */
|
|
|
+ #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk (0x1UL) /*!< EBCKOEN (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== SDCKOCR ======================================================== */
|
|
|
+ #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos (0UL) /*!< SDCKOEN (Bit 0) */
|
|
|
+ #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk (0x1UL) /*!< SDCKOEN (Bitfield-Mask: 0x01) */
|
|
|
+/* ====================================================== SCICKDIVCR ======================================================= */
|
|
|
+ #define R_SYSTEM_SCICKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */
|
|
|
+ #define R_SYSTEM_SCICKDIVCR_CKDIV_Msk (0x7UL) /*!< CKDIV (Bitfield-Mask: 0x07) */
|
|
|
+/* ======================================================== SCICKCR ======================================================== */
|
|
|
+ #define R_SYSTEM_SCICKCR_SCICKSEL_Pos (0UL) /*!< SCICKSEL (Bit 0) */
|
|
|
+ #define R_SYSTEM_SCICKCR_SCICKSEL_Msk (0xfUL) /*!< SCICKSEL (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_SYSTEM_SCICKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */
|
|
|
+ #define R_SYSTEM_SCICKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_SCICKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */
|
|
|
+ #define R_SYSTEM_SCICKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */
|
|
|
+/* ====================================================== SPICKDIVCR ======================================================= */
|
|
|
+ #define R_SYSTEM_SPICKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */
|
|
|
+ #define R_SYSTEM_SPICKDIVCR_CKDIV_Msk (0x7UL) /*!< CKDIV (Bitfield-Mask: 0x07) */
|
|
|
+/* ======================================================== SPICKCR ======================================================== */
|
|
|
+ #define R_SYSTEM_SPICKCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */
|
|
|
+ #define R_SYSTEM_SPICKCR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_SYSTEM_SPICKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */
|
|
|
+ #define R_SYSTEM_SPICKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_SPICKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */
|
|
|
+ #define R_SYSTEM_SPICKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */
|
|
|
+/* ====================================================== ADCCKDIVCR ======================================================= */
|
|
|
+ #define R_SYSTEM_ADCCKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */
|
|
|
+ #define R_SYSTEM_ADCCKDIVCR_CKDIV_Msk (0x7UL) /*!< CKDIV (Bitfield-Mask: 0x07) */
|
|
|
+/* ======================================================== ADCCKCR ======================================================== */
|
|
|
+ #define R_SYSTEM_ADCCKCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */
|
|
|
+ #define R_SYSTEM_ADCCKCR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_SYSTEM_ADCCKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */
|
|
|
+ #define R_SYSTEM_ADCCKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_ADCCKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */
|
|
|
+ #define R_SYSTEM_ADCCKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */
|
|
|
+/* ====================================================== GPTCKDIVCR ======================================================= */
|
|
|
+ #define R_SYSTEM_GPTCKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */
|
|
|
+ #define R_SYSTEM_GPTCKDIVCR_CKDIV_Msk (0x7UL) /*!< CKDIV (Bitfield-Mask: 0x07) */
|
|
|
+/* ======================================================== GPTCKCR ======================================================== */
|
|
|
+ #define R_SYSTEM_GPTCKCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */
|
|
|
+ #define R_SYSTEM_GPTCKCR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_SYSTEM_GPTCKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */
|
|
|
+ #define R_SYSTEM_GPTCKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_GPTCKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */
|
|
|
+ #define R_SYSTEM_GPTCKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */
|
|
|
+/* ====================================================== LCDCKDIVCR ======================================================= */
|
|
|
+ #define R_SYSTEM_LCDCKDIVCR_CKDIV_Pos (0UL) /*!< CKDIV (Bit 0) */
|
|
|
+ #define R_SYSTEM_LCDCKDIVCR_CKDIV_Msk (0x7UL) /*!< CKDIV (Bitfield-Mask: 0x07) */
|
|
|
+/* ======================================================== LCDCKCR ======================================================== */
|
|
|
+ #define R_SYSTEM_LCDCKCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */
|
|
|
+ #define R_SYSTEM_LCDCKCR_CKSEL_Msk (0xfUL) /*!< CKSEL (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_SYSTEM_LCDCKCR_CKSREQ_Pos (6UL) /*!< CKSREQ (Bit 6) */
|
|
|
+ #define R_SYSTEM_LCDCKCR_CKSREQ_Msk (0x40UL) /*!< CKSREQ (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_LCDCKCR_CKSRDY_Pos (7UL) /*!< CKSRDY (Bit 7) */
|
|
|
+ #define R_SYSTEM_LCDCKCR_CKSRDY_Msk (0x80UL) /*!< CKSRDY (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= MOCOUTCR ======================================================== */
|
|
|
+ #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos (0UL) /*!< MOCOUTRM (Bit 0) */
|
|
|
+ #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk (0xffUL) /*!< MOCOUTRM (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= HOCOUTCR ======================================================== */
|
|
|
+ #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos (0UL) /*!< HOCOUTRM (Bit 0) */
|
|
|
+ #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk (0xffUL) /*!< HOCOUTRM (Bitfield-Mask: 0xff) */
|
|
|
+/* ====================================================== USBCKDIVCR ======================================================= */
|
|
|
+ #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos (0UL) /*!< USBCKDIV (Bit 0) */
|
|
|
+ #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk (0x7UL) /*!< USBCKDIV (Bitfield-Mask: 0x07) */
|
|
|
+/* ====================================================== OCTACKDIVCR ====================================================== */
|
|
|
+ #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos (0UL) /*!< OCTACKDIV (Bit 0) */
|
|
|
+ #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk (0x7UL) /*!< OCTACKDIV (Bitfield-Mask: 0x07) */
|
|
|
+/* ===================================================== CANFDCKDIVCR ====================================================== */
|
|
|
+ #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos (0UL) /*!< CANFDCKDIV (Bit 0) */
|
|
|
+ #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk (0x7UL) /*!< CANFDCKDIV (Bitfield-Mask: 0x07) */
|
|
|
+/* ===================================================== USB60CKDIVCR ====================================================== */
|
|
|
+ #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Pos (0UL) /*!< USB60CKDIV (Bit 0) */
|
|
|
+ #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Msk (0x7UL) /*!< USB60CKDIV (Bitfield-Mask: 0x07) */
|
|
|
+/* ====================================================== I3CCKDIVCR ======================================================= */
|
|
|
+ #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Pos (0UL) /*!< I3CCKDIV (Bit 0) */
|
|
|
+ #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk (0x7UL) /*!< I3CCKDIV (Bitfield-Mask: 0x07) */
|
|
|
+/* ======================================================== USBCKCR ======================================================== */
|
|
|
+ #define R_SYSTEM_USBCKCR_USBCKSEL_Pos (0UL) /*!< USBCKSEL (Bit 0) */
|
|
|
+ #define R_SYSTEM_USBCKCR_USBCKSEL_Msk (0xfUL) /*!< USBCKSEL (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos (6UL) /*!< USBCKSREQ (Bit 6) */
|
|
|
+ #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk (0x40UL) /*!< USBCKSREQ (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos (7UL) /*!< USBCKSRDY (Bit 7) */
|
|
|
+ #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk (0x80UL) /*!< USBCKSRDY (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= OCTACKCR ======================================================== */
|
|
|
+ #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos (0UL) /*!< OCTACKSEL (Bit 0) */
|
|
|
+ #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk (0xfUL) /*!< OCTACKSEL (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos (6UL) /*!< OCTACKSREQ (Bit 6) */
|
|
|
+ #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk (0x40UL) /*!< OCTACKSREQ (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos (7UL) /*!< OCTACKSRDY (Bit 7) */
|
|
|
+ #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk (0x80UL) /*!< OCTACKSRDY (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= CANFDCKCR ======================================================= */
|
|
|
+ #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos (0UL) /*!< CANFDCKSEL (Bit 0) */
|
|
|
+ #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk (0xfUL) /*!< CANFDCKSEL (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos (6UL) /*!< CANFDCKSREQ (Bit 6) */
|
|
|
+ #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk (0x40UL) /*!< CANFDCKSREQ (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos (7UL) /*!< CANFDCKSRDY (Bit 7) */
|
|
|
+ #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk (0x80UL) /*!< CANFDCKSRDY (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= USB60CKCR ======================================================= */
|
|
|
+ #define R_SYSTEM_USB60CKCR_USB60CKSEL_Pos (0UL) /*!< USB60CKSEL (Bit 0) */
|
|
|
+ #define R_SYSTEM_USB60CKCR_USB60CKSEL_Msk (0xfUL) /*!< USB60CKSEL (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Pos (6UL) /*!< USB60CKSREQ (Bit 6) */
|
|
|
+ #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Msk (0x40UL) /*!< USB60CKSREQ (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Pos (7UL) /*!< USB60CKSRDY (Bit 7) */
|
|
|
+ #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Msk (0x80UL) /*!< USB60CKSRDY (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== I3CCKCR ======================================================== */
|
|
|
+ #define R_SYSTEM_I3CCKCR_I3CCKSEL_Pos (0UL) /*!< I3CCKSEL (Bit 0) */
|
|
|
+ #define R_SYSTEM_I3CCKCR_I3CCKSEL_Msk (0xfUL) /*!< I3CCKSEL (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_SYSTEM_I3CCKCR_I3CCKREQ_Pos (6UL) /*!< I3CCKREQ (Bit 6) */
|
|
|
+ #define R_SYSTEM_I3CCKCR_I3CCKREQ_Msk (0x40UL) /*!< I3CCKREQ (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Pos (7UL) /*!< I3CCKSRDY (Bit 7) */
|
|
|
+ #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Msk (0x80UL) /*!< I3CCKSRDY (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== MOSCSCR ======================================================== */
|
|
|
+ #define R_SYSTEM_MOSCSCR_MOSCSOKP_Pos (0UL) /*!< MOSCSOKP (Bit 0) */
|
|
|
+ #define R_SYSTEM_MOSCSCR_MOSCSOKP_Msk (0x1UL) /*!< MOSCSOKP (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== HOCOSCR ======================================================== */
|
|
|
+ #define R_SYSTEM_HOCOSCR_HOCOSOKP_Pos (0UL) /*!< HOCOSOKP (Bit 0) */
|
|
|
+ #define R_SYSTEM_HOCOSCR_HOCOSOKP_Msk (0x1UL) /*!< HOCOSOKP (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= SNZREQCR1 ======================================================= */
|
|
|
+ #define R_SYSTEM_SNZREQCR1_SNZREQEN_Pos (0UL) /*!< SNZREQEN (Bit 0) */
|
|
|
+ #define R_SYSTEM_SNZREQCR1_SNZREQEN_Msk (0x1UL) /*!< SNZREQEN (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= SNZCR ========================================================= */
|
|
|
+ #define R_SYSTEM_SNZCR_SNZE_Pos (7UL) /*!< SNZE (Bit 7) */
|
|
|
+ #define R_SYSTEM_SNZCR_SNZE_Msk (0x80UL) /*!< SNZE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_SNZCR_SNZDTCEN_Pos (1UL) /*!< SNZDTCEN (Bit 1) */
|
|
|
+ #define R_SYSTEM_SNZCR_SNZDTCEN_Msk (0x2UL) /*!< SNZDTCEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_SNZCR_RXDREQEN_Pos (0UL) /*!< RXDREQEN (Bit 0) */
|
|
|
+ #define R_SYSTEM_SNZCR_RXDREQEN_Msk (0x1UL) /*!< RXDREQEN (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== SNZEDCR ======================================================== */
|
|
|
+ #define R_SYSTEM_SNZEDCR_SCI0UMTED_Pos (7UL) /*!< SCI0UMTED (Bit 7) */
|
|
|
+ #define R_SYSTEM_SNZEDCR_SCI0UMTED_Msk (0x80UL) /*!< SCI0UMTED (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_SNZEDCR_AD1UMTED_Pos (6UL) /*!< AD1UMTED (Bit 6) */
|
|
|
+ #define R_SYSTEM_SNZEDCR_AD1UMTED_Msk (0x40UL) /*!< AD1UMTED (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_SNZEDCR_AD1MATED_Pos (5UL) /*!< AD1MATED (Bit 5) */
|
|
|
+ #define R_SYSTEM_SNZEDCR_AD1MATED_Msk (0x20UL) /*!< AD1MATED (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_SNZEDCR_AD0UMTED_Pos (4UL) /*!< AD0UMTED (Bit 4) */
|
|
|
+ #define R_SYSTEM_SNZEDCR_AD0UMTED_Msk (0x10UL) /*!< AD0UMTED (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_SNZEDCR_AD0MATED_Pos (3UL) /*!< AD0MATED (Bit 3) */
|
|
|
+ #define R_SYSTEM_SNZEDCR_AD0MATED_Msk (0x8UL) /*!< AD0MATED (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_SNZEDCR_DTCNZRED_Pos (2UL) /*!< DTCNZRED (Bit 2) */
|
|
|
+ #define R_SYSTEM_SNZEDCR_DTCNZRED_Msk (0x4UL) /*!< DTCNZRED (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_SNZEDCR_DTCZRED_Pos (1UL) /*!< DTCZRED (Bit 1) */
|
|
|
+ #define R_SYSTEM_SNZEDCR_DTCZRED_Msk (0x2UL) /*!< DTCZRED (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_SNZEDCR_AGT1UNFED_Pos (0UL) /*!< AGT1UNFED (Bit 0) */
|
|
|
+ #define R_SYSTEM_SNZEDCR_AGT1UNFED_Msk (0x1UL) /*!< AGT1UNFED (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= SNZEDCR1 ======================================================== */
|
|
|
+ #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */
|
|
|
+ #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= SNZREQCR ======================================================== */
|
|
|
+ #define R_SYSTEM_SNZREQCR_SNZREQEN30_Pos (30UL) /*!< SNZREQEN30 (Bit 30) */
|
|
|
+ #define R_SYSTEM_SNZREQCR_SNZREQEN30_Msk (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_SNZREQCR_SNZREQEN29_Pos (29UL) /*!< SNZREQEN29 (Bit 29) */
|
|
|
+ #define R_SYSTEM_SNZREQCR_SNZREQEN29_Msk (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_SNZREQCR_SNZREQEN28_Pos (28UL) /*!< SNZREQEN28 (Bit 28) */
|
|
|
+ #define R_SYSTEM_SNZREQCR_SNZREQEN28_Msk (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_SNZREQCR_SNZREQEN25_Pos (25UL) /*!< SNZREQEN25 (Bit 25) */
|
|
|
+ #define R_SYSTEM_SNZREQCR_SNZREQEN25_Msk (0x2000000UL) /*!< SNZREQEN25 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_SNZREQCR_SNZREQEN24_Pos (24UL) /*!< SNZREQEN24 (Bit 24) */
|
|
|
+ #define R_SYSTEM_SNZREQCR_SNZREQEN24_Msk (0x1000000UL) /*!< SNZREQEN24 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_SNZREQCR_SNZREQEN23_Pos (23UL) /*!< SNZREQEN23 (Bit 23) */
|
|
|
+ #define R_SYSTEM_SNZREQCR_SNZREQEN23_Msk (0x800000UL) /*!< SNZREQEN23 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_SNZREQCR_SNZREQEN22_Pos (22UL) /*!< SNZREQEN22 (Bit 22) */
|
|
|
+ #define R_SYSTEM_SNZREQCR_SNZREQEN22_Msk (0x400000UL) /*!< SNZREQEN22 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_SNZREQCR_SNZREQEN17_Pos (17UL) /*!< SNZREQEN17 (Bit 17) */
|
|
|
+ #define R_SYSTEM_SNZREQCR_SNZREQEN17_Msk (0x20000UL) /*!< SNZREQEN17 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_SNZREQCR_SNZREQEN_Pos (0UL) /*!< SNZREQEN (Bit 0) */
|
|
|
+ #define R_SYSTEM_SNZREQCR_SNZREQEN_Msk (0x1UL) /*!< SNZREQEN (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= OPCCR ========================================================= */
|
|
|
+ #define R_SYSTEM_OPCCR_OPCMTSF_Pos (4UL) /*!< OPCMTSF (Bit 4) */
|
|
|
+ #define R_SYSTEM_OPCCR_OPCMTSF_Msk (0x10UL) /*!< OPCMTSF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_OPCCR_OPCM_Pos (0UL) /*!< OPCM (Bit 0) */
|
|
|
+ #define R_SYSTEM_OPCCR_OPCM_Msk (0x3UL) /*!< OPCM (Bitfield-Mask: 0x03) */
|
|
|
+/* ======================================================= MOSCWTCR ======================================================== */
|
|
|
+ #define R_SYSTEM_MOSCWTCR_MSTS_Pos (0UL) /*!< MSTS (Bit 0) */
|
|
|
+ #define R_SYSTEM_MOSCWTCR_MSTS_Msk (0xfUL) /*!< MSTS (Bitfield-Mask: 0x0f) */
|
|
|
+/* ======================================================= HOCOWTCR ======================================================== */
|
|
|
+ #define R_SYSTEM_HOCOWTCR_HSTS_Pos (0UL) /*!< HSTS (Bit 0) */
|
|
|
+ #define R_SYSTEM_HOCOWTCR_HSTS_Msk (0x7UL) /*!< HSTS (Bitfield-Mask: 0x07) */
|
|
|
+/* ======================================================== SOPCCR ========================================================= */
|
|
|
+ #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos (4UL) /*!< SOPCMTSF (Bit 4) */
|
|
|
+ #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk (0x10UL) /*!< SOPCMTSF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_SOPCCR_SOPCM_Pos (0UL) /*!< SOPCM (Bit 0) */
|
|
|
+ #define R_SYSTEM_SOPCCR_SOPCM_Msk (0x1UL) /*!< SOPCM (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== RSTSR1 ========================================================= */
|
|
|
+ #define R_SYSTEM_RSTSR1_IWDTRF_Pos (0UL) /*!< IWDTRF (Bit 0) */
|
|
|
+ #define R_SYSTEM_RSTSR1_IWDTRF_Msk (0x1UL) /*!< IWDTRF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_RSTSR1_WDTRF_Pos (1UL) /*!< WDTRF (Bit 1) */
|
|
|
+ #define R_SYSTEM_RSTSR1_WDTRF_Msk (0x2UL) /*!< WDTRF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_RSTSR1_SWRF_Pos (2UL) /*!< SWRF (Bit 2) */
|
|
|
+ #define R_SYSTEM_RSTSR1_SWRF_Msk (0x4UL) /*!< SWRF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_RSTSR1_CLU0RF_Pos (4UL) /*!< CLU0RF (Bit 4) */
|
|
|
+ #define R_SYSTEM_RSTSR1_CLU0RF_Msk (0x10UL) /*!< CLU0RF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_RSTSR1_LM0RF_Pos (5UL) /*!< LM0RF (Bit 5) */
|
|
|
+ #define R_SYSTEM_RSTSR1_LM0RF_Msk (0x20UL) /*!< LM0RF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_RSTSR1_BUSRF_Pos (10UL) /*!< BUSRF (Bit 10) */
|
|
|
+ #define R_SYSTEM_RSTSR1_BUSRF_Msk (0x400UL) /*!< BUSRF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_RSTSR1_CMRF_Pos (14UL) /*!< CMRF (Bit 14) */
|
|
|
+ #define R_SYSTEM_RSTSR1_CMRF_Msk (0x4000UL) /*!< CMRF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_RSTSR1_WDT1RF_Pos (17UL) /*!< WDT1RF (Bit 17) */
|
|
|
+ #define R_SYSTEM_RSTSR1_WDT1RF_Msk (0x20000UL) /*!< WDT1RF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_RSTSR1_CLU1RF_Pos (20UL) /*!< CLU1RF (Bit 20) */
|
|
|
+ #define R_SYSTEM_RSTSR1_CLU1RF_Msk (0x100000UL) /*!< CLU1RF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_RSTSR1_LM1RF_Pos (21UL) /*!< LM1RF (Bit 21) */
|
|
|
+ #define R_SYSTEM_RSTSR1_LM1RF_Msk (0x200000UL) /*!< LM1RF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_RSTSR1_NWRF_Pos (22UL) /*!< NWRF (Bit 22) */
|
|
|
+ #define R_SYSTEM_RSTSR1_NWRF_Msk (0x400000UL) /*!< NWRF (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== SYRACCR ======================================================== */
|
|
|
+ #define R_SYSTEM_SYRACCR_BUSY_Pos (0UL) /*!< BUSY (Bit 0) */
|
|
|
+ #define R_SYSTEM_SYRACCR_BUSY_Msk (0x1UL) /*!< BUSY (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== LVD1CR1 ======================================================== */
|
|
|
+ #define R_SYSTEM_LVD1CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */
|
|
|
+ #define R_SYSTEM_LVD1CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_SYSTEM_LVD1CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */
|
|
|
+ #define R_SYSTEM_LVD1CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== LVD2CR1 ======================================================== */
|
|
|
+ #define R_SYSTEM_LVD2CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */
|
|
|
+ #define R_SYSTEM_LVD2CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_SYSTEM_LVD2CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */
|
|
|
+ #define R_SYSTEM_LVD2CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== LVD1SR ========================================================= */
|
|
|
+ #define R_SYSTEM_LVD1SR_DET_Pos (0UL) /*!< DET (Bit 0) */
|
|
|
+ #define R_SYSTEM_LVD1SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_LVD1SR_MON_Pos (1UL) /*!< MON (Bit 1) */
|
|
|
+ #define R_SYSTEM_LVD1SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== LVD2SR ========================================================= */
|
|
|
+ #define R_SYSTEM_LVD2SR_DET_Pos (0UL) /*!< DET (Bit 0) */
|
|
|
+ #define R_SYSTEM_LVD2SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_LVD2SR_MON_Pos (1UL) /*!< MON (Bit 1) */
|
|
|
+ #define R_SYSTEM_LVD2SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= CRVSYSCR ======================================================== */
|
|
|
+ #define R_SYSTEM_CRVSYSCR_CRVEN_Pos (0UL) /*!< CRVEN (Bit 0) */
|
|
|
+ #define R_SYSTEM_CRVSYSCR_CRVEN_Msk (0x1UL) /*!< CRVEN (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== PDCTRGD ======================================================== */
|
|
|
+ #define R_SYSTEM_PDCTRGD_PDDE_Pos (0UL) /*!< PDDE (Bit 0) */
|
|
|
+ #define R_SYSTEM_PDCTRGD_PDDE_Msk (0x1UL) /*!< PDDE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_PDCTRGD_PDCSF_Pos (6UL) /*!< PDCSF (Bit 6) */
|
|
|
+ #define R_SYSTEM_PDCTRGD_PDCSF_Msk (0x40UL) /*!< PDCSF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_PDCTRGD_PDPGSF_Pos (7UL) /*!< PDPGSF (Bit 7) */
|
|
|
+ #define R_SYSTEM_PDCTRGD_PDPGSF_Msk (0x80UL) /*!< PDPGSF (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= PDRAMSCR0 ======================================================= */
|
|
|
+/* ======================================================= PDRAMSCR1 ======================================================= */
|
|
|
+/* ======================================================= VBRSABAR ======================================================== */
|
|
|
+ #define R_SYSTEM_VBRSABAR_SABA_Pos (0UL) /*!< SABA (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBRSABAR_SABA_Msk (0xffffUL) /*!< SABA (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================= VBRPABARS ======================================================= */
|
|
|
+ #define R_SYSTEM_VBRPABARS_PABAS_Pos (0UL) /*!< PABAS (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBRPABARS_PABAS_Msk (0xffffUL) /*!< PABAS (Bitfield-Mask: 0xffff) */
|
|
|
+/* ====================================================== VBRPABARNS ======================================================= */
|
|
|
+ #define R_SYSTEM_VBRPABARNS_PABANS_Pos (0UL) /*!< PABANS (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBRPABARNS_PABANS_Msk (0xffffUL) /*!< PABANS (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================== CGFSAR ========================================================= */
|
|
|
+ #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */
|
|
|
+ #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */
|
|
|
+ #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */
|
|
|
+ #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */
|
|
|
+ #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */
|
|
|
+ #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */
|
|
|
+ #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */
|
|
|
+ #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */
|
|
|
+ #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */
|
|
|
+ #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */
|
|
|
+ #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */
|
|
|
+ #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_CGFSAR_NONSEC13_Pos (13UL) /*!< NONSEC13 (Bit 13) */
|
|
|
+ #define R_SYSTEM_CGFSAR_NONSEC13_Msk (0x2000UL) /*!< NONSEC13 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */
|
|
|
+ #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */
|
|
|
+ #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_CGFSAR_NONSEC18_Pos (18UL) /*!< NONSEC18 (Bit 18) */
|
|
|
+ #define R_SYSTEM_CGFSAR_NONSEC18_Msk (0x40000UL) /*!< NONSEC18 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_CGFSAR_NONSEC19_Pos (19UL) /*!< NONSEC19 (Bit 19) */
|
|
|
+ #define R_SYSTEM_CGFSAR_NONSEC19_Msk (0x80000UL) /*!< NONSEC19 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_CGFSAR_NONSEC20_Pos (20UL) /*!< NONSEC20 (Bit 20) */
|
|
|
+ #define R_SYSTEM_CGFSAR_NONSEC20_Msk (0x100000UL) /*!< NONSEC20 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_CGFSAR_NONSEC21_Pos (21UL) /*!< NONSEC21 (Bit 21) */
|
|
|
+ #define R_SYSTEM_CGFSAR_NONSEC21_Msk (0x200000UL) /*!< NONSEC21 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_CGFSAR_NONSEC22_Pos (22UL) /*!< NONSEC22 (Bit 22) */
|
|
|
+ #define R_SYSTEM_CGFSAR_NONSEC22_Msk (0x400000UL) /*!< NONSEC22 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_CGFSAR_NONSEC24_Pos (24UL) /*!< NONSEC24 (Bit 24) */
|
|
|
+ #define R_SYSTEM_CGFSAR_NONSEC24_Msk (0x1000000UL) /*!< NONSEC24 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_CGFSAR_NONSEC25_Pos (25UL) /*!< NONSEC25 (Bit 25) */
|
|
|
+ #define R_SYSTEM_CGFSAR_NONSEC25_Msk (0x2000000UL) /*!< NONSEC25 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_CGFSAR_NONSEC26_Pos (26UL) /*!< NONSEC26 (Bit 26) */
|
|
|
+ #define R_SYSTEM_CGFSAR_NONSEC26_Msk (0x4000000UL) /*!< NONSEC26 (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== RSTSAR ========================================================= */
|
|
|
+ #define R_SYSTEM_RSTSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */
|
|
|
+ #define R_SYSTEM_RSTSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_RSTSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */
|
|
|
+ #define R_SYSTEM_RSTSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_RSTSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */
|
|
|
+ #define R_SYSTEM_RSTSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_RSTSAR_NONSEC3_Pos (3UL) /*!< NONSEC3 (Bit 3) */
|
|
|
+ #define R_SYSTEM_RSTSAR_NONSEC3_Msk (0x8UL) /*!< NONSEC3 (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== LPMSAR ========================================================= */
|
|
|
+ #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */
|
|
|
+ #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_LPMSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */
|
|
|
+ #define R_SYSTEM_LPMSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_LPMSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */
|
|
|
+ #define R_SYSTEM_LPMSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_LPMSAR_NONSEC3_Pos (3UL) /*!< NONSEC3 (Bit 3) */
|
|
|
+ #define R_SYSTEM_LPMSAR_NONSEC3_Msk (0x8UL) /*!< NONSEC3 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_LPMSAR_NONSEC8_Pos (8UL) /*!< NONSEC8 (Bit 8) */
|
|
|
+ #define R_SYSTEM_LPMSAR_NONSEC8_Msk (0x100UL) /*!< NONSEC8 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_LPMSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */
|
|
|
+ #define R_SYSTEM_LPMSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_LPMSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */
|
|
|
+ #define R_SYSTEM_LPMSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_LPMSAR_NONSEC18_Pos (18UL) /*!< NONSEC18 (Bit 18) */
|
|
|
+ #define R_SYSTEM_LPMSAR_NONSEC18_Msk (0x40000UL) /*!< NONSEC18 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_LPMSAR_NONSEC19_Pos (19UL) /*!< NONSEC19 (Bit 19) */
|
|
|
+ #define R_SYSTEM_LPMSAR_NONSEC19_Msk (0x80000UL) /*!< NONSEC19 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_LPMSAR_NONSEC21_Pos (21UL) /*!< NONSEC21 (Bit 21) */
|
|
|
+ #define R_SYSTEM_LPMSAR_NONSEC21_Msk (0x200000UL) /*!< NONSEC21 (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== LVDSAR ========================================================= */
|
|
|
+ #define R_SYSTEM_LVDSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */
|
|
|
+ #define R_SYSTEM_LVDSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_LVDSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */
|
|
|
+ #define R_SYSTEM_LVDSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== BBFSAR ========================================================= */
|
|
|
+ #define R_SYSTEM_BBFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */
|
|
|
+ #define R_SYSTEM_BBFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_BBFSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */
|
|
|
+ #define R_SYSTEM_BBFSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_BBFSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */
|
|
|
+ #define R_SYSTEM_BBFSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_BBFSAR_NONSEC3_Pos (3UL) /*!< NONSEC3 (Bit 3) */
|
|
|
+ #define R_SYSTEM_BBFSAR_NONSEC3_Msk (0x8UL) /*!< NONSEC3 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_BBFSAR_NONSEC4_Pos (4UL) /*!< NONSEC4 (Bit 4) */
|
|
|
+ #define R_SYSTEM_BBFSAR_NONSEC4_Msk (0x10UL) /*!< NONSEC4 (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== PGCSAR ========================================================= */
|
|
|
+ #define R_SYSTEM_PGCSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */
|
|
|
+ #define R_SYSTEM_PGCSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_PGCSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */
|
|
|
+ #define R_SYSTEM_PGCSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== DPFSAR ========================================================= */
|
|
|
+ #define R_SYSTEM_DPFSAR_DPFSA16_Pos (16UL) /*!< DPFSA16 (Bit 16) */
|
|
|
+ #define R_SYSTEM_DPFSAR_DPFSA16_Msk (0x10000UL) /*!< DPFSA16 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPFSAR_DPFSA17_Pos (17UL) /*!< DPFSA17 (Bit 17) */
|
|
|
+ #define R_SYSTEM_DPFSAR_DPFSA17_Msk (0x20000UL) /*!< DPFSA17 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPFSAR_DPFSA18_Pos (18UL) /*!< DPFSA18 (Bit 18) */
|
|
|
+ #define R_SYSTEM_DPFSAR_DPFSA18_Msk (0x40000UL) /*!< DPFSA18 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPFSAR_DPFSA19_Pos (19UL) /*!< DPFSA19 (Bit 19) */
|
|
|
+ #define R_SYSTEM_DPFSAR_DPFSA19_Msk (0x80000UL) /*!< DPFSA19 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPFSAR_DPFSA20_Pos (20UL) /*!< DPFSA20 (Bit 20) */
|
|
|
+ #define R_SYSTEM_DPFSAR_DPFSA20_Msk (0x100000UL) /*!< DPFSA20 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPFSAR_DPFSA24_Pos (24UL) /*!< DPFSA24 (Bit 24) */
|
|
|
+ #define R_SYSTEM_DPFSAR_DPFSA24_Msk (0x1000000UL) /*!< DPFSA24 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPFSAR_DPFSA25_Pos (25UL) /*!< DPFSA25 (Bit 25) */
|
|
|
+ #define R_SYSTEM_DPFSAR_DPFSA25_Msk (0x2000000UL) /*!< DPFSA25 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPFSAR_DPFSA26_Pos (26UL) /*!< DPFSA26 (Bit 26) */
|
|
|
+ #define R_SYSTEM_DPFSAR_DPFSA26_Msk (0x4000000UL) /*!< DPFSA26 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPFSAR_DPFSA27_Pos (27UL) /*!< DPFSA27 (Bit 27) */
|
|
|
+ #define R_SYSTEM_DPFSAR_DPFSA27_Msk (0x8000000UL) /*!< DPFSA27 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPFSAR_DPFSA29_Pos (29UL) /*!< DPFSA29 (Bit 29) */
|
|
|
+ #define R_SYSTEM_DPFSAR_DPFSA29_Msk (0x20000000UL) /*!< DPFSA29 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPFSAR_DPFSA31_Pos (31UL) /*!< DPFSA31 (Bit 31) */
|
|
|
+ #define R_SYSTEM_DPFSAR_DPFSA31_Msk (0x80000000UL) /*!< DPFSA31 (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== RSCSAR ========================================================= */
|
|
|
+ #define R_SYSTEM_RSCSAR_RSCSA0_Pos (0UL) /*!< RSCSA0 (Bit 0) */
|
|
|
+ #define R_SYSTEM_RSCSAR_RSCSA0_Msk (0x1UL) /*!< RSCSA0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_RSCSAR_RSCSA1_Pos (1UL) /*!< RSCSA1 (Bit 1) */
|
|
|
+ #define R_SYSTEM_RSCSAR_RSCSA1_Msk (0x2UL) /*!< RSCSA1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_RSCSAR_RSCSA2_Pos (2UL) /*!< RSCSA2 (Bit 2) */
|
|
|
+ #define R_SYSTEM_RSCSAR_RSCSA2_Msk (0x4UL) /*!< RSCSA2 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_RSCSAR_RSCSA3_Pos (3UL) /*!< RSCSA3 (Bit 3) */
|
|
|
+ #define R_SYSTEM_RSCSAR_RSCSA3_Msk (0x8UL) /*!< RSCSA3 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_RSCSAR_RSCSA4_Pos (4UL) /*!< RSCSA4 (Bit 4) */
|
|
|
+ #define R_SYSTEM_RSCSAR_RSCSA4_Msk (0x10UL) /*!< RSCSA4 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_RSCSAR_RSCSA5_Pos (5UL) /*!< RSCSA5 (Bit 5) */
|
|
|
+ #define R_SYSTEM_RSCSAR_RSCSA5_Msk (0x20UL) /*!< RSCSA5 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_RSCSAR_RSCSA6_Pos (6UL) /*!< RSCSA6 (Bit 6) */
|
|
|
+ #define R_SYSTEM_RSCSAR_RSCSA6_Msk (0x40UL) /*!< RSCSA6 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_RSCSAR_RSCSA7_Pos (7UL) /*!< RSCSA7 (Bit 7) */
|
|
|
+ #define R_SYSTEM_RSCSAR_RSCSA7_Msk (0x80UL) /*!< RSCSA7 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_RSCSAR_RSCSA8_Pos (8UL) /*!< RSCSA8 (Bit 8) */
|
|
|
+ #define R_SYSTEM_RSCSAR_RSCSA8_Msk (0x100UL) /*!< RSCSA8 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_RSCSAR_RSCSA9_Pos (9UL) /*!< RSCSA9 (Bit 9) */
|
|
|
+ #define R_SYSTEM_RSCSAR_RSCSA9_Msk (0x200UL) /*!< RSCSA9 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_RSCSAR_RSCSA10_Pos (10UL) /*!< RSCSA10 (Bit 10) */
|
|
|
+ #define R_SYSTEM_RSCSAR_RSCSA10_Msk (0x400UL) /*!< RSCSA10 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_RSCSAR_RSCSA11_Pos (11UL) /*!< RSCSA11 (Bit 11) */
|
|
|
+ #define R_SYSTEM_RSCSAR_RSCSA11_Msk (0x800UL) /*!< RSCSA11 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_RSCSAR_RSCSA12_Pos (12UL) /*!< RSCSA12 (Bit 12) */
|
|
|
+ #define R_SYSTEM_RSCSAR_RSCSA12_Msk (0x1000UL) /*!< RSCSA12 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_RSCSAR_RSCSA13_Pos (13UL) /*!< RSCSA13 (Bit 13) */
|
|
|
+ #define R_SYSTEM_RSCSAR_RSCSA13_Msk (0x2000UL) /*!< RSCSA13 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_RSCSAR_RSCSA14_Pos (14UL) /*!< RSCSA14 (Bit 14) */
|
|
|
+ #define R_SYSTEM_RSCSAR_RSCSA14_Msk (0x4000UL) /*!< RSCSA14 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_RSCSAR_RSCSA16_Pos (16UL) /*!< RSCSA16 (Bit 16) */
|
|
|
+ #define R_SYSTEM_RSCSAR_RSCSA16_Msk (0x10000UL) /*!< RSCSA16 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_RSCSAR_RSCSA17_Pos (17UL) /*!< RSCSA17 (Bit 17) */
|
|
|
+ #define R_SYSTEM_RSCSAR_RSCSA17_Msk (0x20000UL) /*!< RSCSA17 (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= PRCR ========================================================== */
|
|
|
+ #define R_SYSTEM_PRCR_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */
|
|
|
+ #define R_SYSTEM_PRCR_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_PRCR_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */
|
|
|
+ #define R_SYSTEM_PRCR_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_PRCR_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */
|
|
|
+ #define R_SYSTEM_PRCR_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_PRCR_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */
|
|
|
+ #define R_SYSTEM_PRCR_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_PRCR_PRC5_Pos (5UL) /*!< PRC5 (Bit 5) */
|
|
|
+ #define R_SYSTEM_PRCR_PRC5_Msk (0x20UL) /*!< PRC5 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_PRCR_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */
|
|
|
+ #define R_SYSTEM_PRCR_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== PRCR_NS ======================================================== */
|
|
|
+ #define R_SYSTEM_PRCR_NS_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */
|
|
|
+ #define R_SYSTEM_PRCR_NS_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_PRCR_NS_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */
|
|
|
+ #define R_SYSTEM_PRCR_NS_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_PRCR_NS_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */
|
|
|
+ #define R_SYSTEM_PRCR_NS_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_PRCR_NS_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */
|
|
|
+ #define R_SYSTEM_PRCR_NS_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_PRCR_NS_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */
|
|
|
+ #define R_SYSTEM_PRCR_NS_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== LOCOCR ========================================================= */
|
|
|
+ #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */
|
|
|
+ #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= LOCOUTCR ======================================================== */
|
|
|
+ #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos (0UL) /*!< LOCOUTRM (Bit 0) */
|
|
|
+ #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk (0xffUL) /*!< LOCOUTRM (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== STCONR ========================================================= */
|
|
|
+ #define R_SYSTEM_STCONR_STCON_Pos (0UL) /*!< STCON (Bit 0) */
|
|
|
+ #define R_SYSTEM_STCONR_STCON_Msk (0x3UL) /*!< STCON (Bitfield-Mask: 0x03) */
|
|
|
+/* ======================================================== DPSBYCR ======================================================== */
|
|
|
+ #define R_SYSTEM_DPSBYCR_DCSSMODE_Pos (2UL) /*!< DCSSMODE (Bit 2) */
|
|
|
+ #define R_SYSTEM_DPSBYCR_DCSSMODE_Msk (0x4UL) /*!< DCSSMODE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSBYCR_SRKEEP_Pos (4UL) /*!< SRKEEP (Bit 4) */
|
|
|
+ #define R_SYSTEM_DPSBYCR_SRKEEP_Msk (0x10UL) /*!< SRKEEP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSBYCR_IOKEEP_Pos (6UL) /*!< IOKEEP (Bit 6) */
|
|
|
+ #define R_SYSTEM_DPSBYCR_IOKEEP_Msk (0x40UL) /*!< IOKEEP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSBYCR_DPSBY_Pos (7UL) /*!< DPSBY (Bit 7) */
|
|
|
+ #define R_SYSTEM_DPSBYCR_DPSBY_Msk (0x80UL) /*!< DPSBY (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== DPSWCR ========================================================= */
|
|
|
+ #define R_SYSTEM_DPSWCR_WTSTS_Pos (0UL) /*!< WTSTS (Bit 0) */
|
|
|
+ #define R_SYSTEM_DPSWCR_WTSTS_Msk (0xffUL) /*!< WTSTS (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== DPSIER0 ======================================================== */
|
|
|
+ #define R_SYSTEM_DPSIER0_DIRQ0E_Pos (0UL) /*!< DIRQ0E (Bit 0) */
|
|
|
+ #define R_SYSTEM_DPSIER0_DIRQ0E_Msk (0x1UL) /*!< DIRQ0E (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIER0_DIRQ1E_Pos (1UL) /*!< DIRQ1E (Bit 1) */
|
|
|
+ #define R_SYSTEM_DPSIER0_DIRQ1E_Msk (0x2UL) /*!< DIRQ1E (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIER0_DIRQ2E_Pos (2UL) /*!< DIRQ2E (Bit 2) */
|
|
|
+ #define R_SYSTEM_DPSIER0_DIRQ2E_Msk (0x4UL) /*!< DIRQ2E (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIER0_DIRQ3E_Pos (3UL) /*!< DIRQ3E (Bit 3) */
|
|
|
+ #define R_SYSTEM_DPSIER0_DIRQ3E_Msk (0x8UL) /*!< DIRQ3E (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIER0_DIRQ4E_Pos (4UL) /*!< DIRQ4E (Bit 4) */
|
|
|
+ #define R_SYSTEM_DPSIER0_DIRQ4E_Msk (0x10UL) /*!< DIRQ4E (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIER0_DIRQ5E_Pos (5UL) /*!< DIRQ5E (Bit 5) */
|
|
|
+ #define R_SYSTEM_DPSIER0_DIRQ5E_Msk (0x20UL) /*!< DIRQ5E (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIER0_DIRQ6E_Pos (6UL) /*!< DIRQ6E (Bit 6) */
|
|
|
+ #define R_SYSTEM_DPSIER0_DIRQ6E_Msk (0x40UL) /*!< DIRQ6E (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIER0_DIRQ7E_Pos (7UL) /*!< DIRQ7E (Bit 7) */
|
|
|
+ #define R_SYSTEM_DPSIER0_DIRQ7E_Msk (0x80UL) /*!< DIRQ7E (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== DPSIER1 ======================================================== */
|
|
|
+ #define R_SYSTEM_DPSIER1_DIRQ8E_Pos (0UL) /*!< DIRQ8E (Bit 0) */
|
|
|
+ #define R_SYSTEM_DPSIER1_DIRQ8E_Msk (0x1UL) /*!< DIRQ8E (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIER1_DIRQ9E_Pos (1UL) /*!< DIRQ9E (Bit 1) */
|
|
|
+ #define R_SYSTEM_DPSIER1_DIRQ9E_Msk (0x2UL) /*!< DIRQ9E (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIER1_DIRQ10E_Pos (2UL) /*!< DIRQ10E (Bit 2) */
|
|
|
+ #define R_SYSTEM_DPSIER1_DIRQ10E_Msk (0x4UL) /*!< DIRQ10E (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIER1_DIRQ11E_Pos (3UL) /*!< DIRQ11E (Bit 3) */
|
|
|
+ #define R_SYSTEM_DPSIER1_DIRQ11E_Msk (0x8UL) /*!< DIRQ11E (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIER1_DIRQ12E_Pos (4UL) /*!< DIRQ12E (Bit 4) */
|
|
|
+ #define R_SYSTEM_DPSIER1_DIRQ12E_Msk (0x10UL) /*!< DIRQ12E (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIER1_DIRQ13E_Pos (5UL) /*!< DIRQ13E (Bit 5) */
|
|
|
+ #define R_SYSTEM_DPSIER1_DIRQ13E_Msk (0x20UL) /*!< DIRQ13E (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIER1_DIRQ14E_Pos (6UL) /*!< DIRQ14E (Bit 6) */
|
|
|
+ #define R_SYSTEM_DPSIER1_DIRQ14E_Msk (0x40UL) /*!< DIRQ14E (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIER1_DIRQ15E_Pos (7UL) /*!< DIRQ15E (Bit 7) */
|
|
|
+ #define R_SYSTEM_DPSIER1_DIRQ15E_Msk (0x80UL) /*!< DIRQ15E (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== DPSIER2 ======================================================== */
|
|
|
+ #define R_SYSTEM_DPSIER2_DPVD1IE_Pos (0UL) /*!< DPVD1IE (Bit 0) */
|
|
|
+ #define R_SYSTEM_DPSIER2_DPVD1IE_Msk (0x1UL) /*!< DPVD1IE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIER2_DPVD2IE_Pos (1UL) /*!< DPVD2IE (Bit 1) */
|
|
|
+ #define R_SYSTEM_DPSIER2_DPVD2IE_Msk (0x2UL) /*!< DPVD2IE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos (2UL) /*!< DTRTCIIE (Bit 2) */
|
|
|
+ #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk (0x4UL) /*!< DTRTCIIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIER2_DRTCAIE_Pos (3UL) /*!< DRTCAIE (Bit 3) */
|
|
|
+ #define R_SYSTEM_DPSIER2_DRTCAIE_Msk (0x8UL) /*!< DRTCAIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIER2_DNMIE_Pos (4UL) /*!< DNMIE (Bit 4) */
|
|
|
+ #define R_SYSTEM_DPSIER2_DNMIE_Msk (0x10UL) /*!< DNMIE (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== DPSIER3 ======================================================== */
|
|
|
+ #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos (0UL) /*!< DUSBFSIE (Bit 0) */
|
|
|
+ #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk (0x1UL) /*!< DUSBFSIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos (1UL) /*!< DUSBHSIE (Bit 1) */
|
|
|
+ #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk (0x2UL) /*!< DUSBHSIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIER3_DULPT0IE_Pos (2UL) /*!< DULPT0IE (Bit 2) */
|
|
|
+ #define R_SYSTEM_DPSIER3_DULPT0IE_Msk (0x4UL) /*!< DULPT0IE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIER3_DULPT1IE_Pos (3UL) /*!< DULPT1IE (Bit 3) */
|
|
|
+ #define R_SYSTEM_DPSIER3_DULPT1IE_Msk (0x8UL) /*!< DULPT1IE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIER3_DIWDTIE_Pos (5UL) /*!< DIWDTIE (Bit 5) */
|
|
|
+ #define R_SYSTEM_DPSIER3_DIWDTIE_Msk (0x20UL) /*!< DIWDTIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIER3_DVBATTADIE_Pos (7UL) /*!< DVBATTADIE (Bit 7) */
|
|
|
+ #define R_SYSTEM_DPSIER3_DVBATTADIE_Msk (0x80UL) /*!< DVBATTADIE (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== DPSIFR0 ======================================================== */
|
|
|
+ #define R_SYSTEM_DPSIFR0_DIRQ0F_Pos (0UL) /*!< DIRQ0F (Bit 0) */
|
|
|
+ #define R_SYSTEM_DPSIFR0_DIRQ0F_Msk (0x1UL) /*!< DIRQ0F (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIFR0_DIRQ1F_Pos (1UL) /*!< DIRQ1F (Bit 1) */
|
|
|
+ #define R_SYSTEM_DPSIFR0_DIRQ1F_Msk (0x2UL) /*!< DIRQ1F (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIFR0_DIRQ2F_Pos (2UL) /*!< DIRQ2F (Bit 2) */
|
|
|
+ #define R_SYSTEM_DPSIFR0_DIRQ2F_Msk (0x4UL) /*!< DIRQ2F (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIFR0_DIRQ3F_Pos (3UL) /*!< DIRQ3F (Bit 3) */
|
|
|
+ #define R_SYSTEM_DPSIFR0_DIRQ3F_Msk (0x8UL) /*!< DIRQ3F (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIFR0_DIRQ4F_Pos (4UL) /*!< DIRQ4F (Bit 4) */
|
|
|
+ #define R_SYSTEM_DPSIFR0_DIRQ4F_Msk (0x10UL) /*!< DIRQ4F (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIFR0_DIRQ5F_Pos (5UL) /*!< DIRQ5F (Bit 5) */
|
|
|
+ #define R_SYSTEM_DPSIFR0_DIRQ5F_Msk (0x20UL) /*!< DIRQ5F (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIFR0_DIRQ6F_Pos (6UL) /*!< DIRQ6F (Bit 6) */
|
|
|
+ #define R_SYSTEM_DPSIFR0_DIRQ6F_Msk (0x40UL) /*!< DIRQ6F (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIFR0_DIRQ7F_Pos (7UL) /*!< DIRQ7F (Bit 7) */
|
|
|
+ #define R_SYSTEM_DPSIFR0_DIRQ7F_Msk (0x80UL) /*!< DIRQ7F (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== DPSIFR1 ======================================================== */
|
|
|
+ #define R_SYSTEM_DPSIFR1_DIRQ8F_Pos (0UL) /*!< DIRQ8F (Bit 0) */
|
|
|
+ #define R_SYSTEM_DPSIFR1_DIRQ8F_Msk (0x1UL) /*!< DIRQ8F (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIFR1_DIRQ9F_Pos (1UL) /*!< DIRQ9F (Bit 1) */
|
|
|
+ #define R_SYSTEM_DPSIFR1_DIRQ9F_Msk (0x2UL) /*!< DIRQ9F (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIFR1_DIRQ10F_Pos (2UL) /*!< DIRQ10F (Bit 2) */
|
|
|
+ #define R_SYSTEM_DPSIFR1_DIRQ10F_Msk (0x4UL) /*!< DIRQ10F (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIFR1_DIRQ11F_Pos (3UL) /*!< DIRQ11F (Bit 3) */
|
|
|
+ #define R_SYSTEM_DPSIFR1_DIRQ11F_Msk (0x8UL) /*!< DIRQ11F (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIFR1_DIRQ12F_Pos (4UL) /*!< DIRQ12F (Bit 4) */
|
|
|
+ #define R_SYSTEM_DPSIFR1_DIRQ12F_Msk (0x10UL) /*!< DIRQ12F (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIFR1_DIRQ13F_Pos (5UL) /*!< DIRQ13F (Bit 5) */
|
|
|
+ #define R_SYSTEM_DPSIFR1_DIRQ13F_Msk (0x20UL) /*!< DIRQ13F (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIFR1_DIRQ14F_Pos (6UL) /*!< DIRQ14F (Bit 6) */
|
|
|
+ #define R_SYSTEM_DPSIFR1_DIRQ14F_Msk (0x40UL) /*!< DIRQ14F (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIFR1_DIRQ15F_Pos (7UL) /*!< DIRQ15F (Bit 7) */
|
|
|
+ #define R_SYSTEM_DPSIFR1_DIRQ15F_Msk (0x80UL) /*!< DIRQ15F (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== DPSIFR2 ======================================================== */
|
|
|
+ #define R_SYSTEM_DPSIFR2_DPVD1IF_Pos (0UL) /*!< DPVD1IF (Bit 0) */
|
|
|
+ #define R_SYSTEM_DPSIFR2_DPVD1IF_Msk (0x1UL) /*!< DPVD1IF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIFR2_DPVD2IF_Pos (1UL) /*!< DPVD2IF (Bit 1) */
|
|
|
+ #define R_SYSTEM_DPSIFR2_DPVD2IF_Msk (0x2UL) /*!< DPVD2IF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos (2UL) /*!< DTRTCIIF (Bit 2) */
|
|
|
+ #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk (0x4UL) /*!< DTRTCIIF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos (3UL) /*!< DRTCAIF (Bit 3) */
|
|
|
+ #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk (0x8UL) /*!< DRTCAIF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIFR2_DNMIF_Pos (4UL) /*!< DNMIF (Bit 4) */
|
|
|
+ #define R_SYSTEM_DPSIFR2_DNMIF_Msk (0x10UL) /*!< DNMIF (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== DPSIFR3 ======================================================== */
|
|
|
+ #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos (0UL) /*!< DUSBFSIF (Bit 0) */
|
|
|
+ #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk (0x1UL) /*!< DUSBFSIF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos (1UL) /*!< DUSBHSIF (Bit 1) */
|
|
|
+ #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk (0x2UL) /*!< DUSBHSIF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIFR3_DULPT0IF_Pos (2UL) /*!< DULPT0IF (Bit 2) */
|
|
|
+ #define R_SYSTEM_DPSIFR3_DULPT0IF_Msk (0x4UL) /*!< DULPT0IF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIFR3_DULPT1IF_Pos (3UL) /*!< DULPT1IF (Bit 3) */
|
|
|
+ #define R_SYSTEM_DPSIFR3_DULPT1IF_Msk (0x8UL) /*!< DULPT1IF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIFR3_DIWDTIF_Pos (5UL) /*!< DIWDTIF (Bit 5) */
|
|
|
+ #define R_SYSTEM_DPSIFR3_DIWDTIF_Msk (0x20UL) /*!< DIWDTIF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIFR3_DVBATTADIF_Pos (7UL) /*!< DVBATTADIF (Bit 7) */
|
|
|
+ #define R_SYSTEM_DPSIFR3_DVBATTADIF_Msk (0x80UL) /*!< DVBATTADIF (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= DPSIEGR0 ======================================================== */
|
|
|
+ #define R_SYSTEM_DPSIEGR0_DIRQ0EG_Pos (0UL) /*!< DIRQ0EG (Bit 0) */
|
|
|
+ #define R_SYSTEM_DPSIEGR0_DIRQ0EG_Msk (0x1UL) /*!< DIRQ0EG (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIEGR0_DIRQ1EG_Pos (1UL) /*!< DIRQ1EG (Bit 1) */
|
|
|
+ #define R_SYSTEM_DPSIEGR0_DIRQ1EG_Msk (0x2UL) /*!< DIRQ1EG (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIEGR0_DIRQ2EG_Pos (2UL) /*!< DIRQ2EG (Bit 2) */
|
|
|
+ #define R_SYSTEM_DPSIEGR0_DIRQ2EG_Msk (0x4UL) /*!< DIRQ2EG (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIEGR0_DIRQ3EG_Pos (3UL) /*!< DIRQ3EG (Bit 3) */
|
|
|
+ #define R_SYSTEM_DPSIEGR0_DIRQ3EG_Msk (0x8UL) /*!< DIRQ3EG (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIEGR0_DIRQ4EG_Pos (4UL) /*!< DIRQ4EG (Bit 4) */
|
|
|
+ #define R_SYSTEM_DPSIEGR0_DIRQ4EG_Msk (0x10UL) /*!< DIRQ4EG (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIEGR0_DIRQ5EG_Pos (5UL) /*!< DIRQ5EG (Bit 5) */
|
|
|
+ #define R_SYSTEM_DPSIEGR0_DIRQ5EG_Msk (0x20UL) /*!< DIRQ5EG (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIEGR0_DIRQ6EG_Pos (6UL) /*!< DIRQ6EG (Bit 6) */
|
|
|
+ #define R_SYSTEM_DPSIEGR0_DIRQ6EG_Msk (0x40UL) /*!< DIRQ6EG (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIEGR0_DIRQ7EG_Pos (7UL) /*!< DIRQ7EG (Bit 7) */
|
|
|
+ #define R_SYSTEM_DPSIEGR0_DIRQ7EG_Msk (0x80UL) /*!< DIRQ7EG (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= DPSIEGR1 ======================================================== */
|
|
|
+ #define R_SYSTEM_DPSIEGR1_DIRQ8EG_Pos (0UL) /*!< DIRQ8EG (Bit 0) */
|
|
|
+ #define R_SYSTEM_DPSIEGR1_DIRQ8EG_Msk (0x1UL) /*!< DIRQ8EG (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIEGR1_DIRQ9EG_Pos (1UL) /*!< DIRQ9EG (Bit 1) */
|
|
|
+ #define R_SYSTEM_DPSIEGR1_DIRQ9EG_Msk (0x2UL) /*!< DIRQ9EG (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIEGR1_DIRQ10EG_Pos (2UL) /*!< DIRQ10EG (Bit 2) */
|
|
|
+ #define R_SYSTEM_DPSIEGR1_DIRQ10EG_Msk (0x4UL) /*!< DIRQ10EG (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIEGR1_DIRQ11EG_Pos (3UL) /*!< DIRQ11EG (Bit 3) */
|
|
|
+ #define R_SYSTEM_DPSIEGR1_DIRQ11EG_Msk (0x8UL) /*!< DIRQ11EG (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIEGR1_DIRQ12EG_Pos (4UL) /*!< DIRQ12EG (Bit 4) */
|
|
|
+ #define R_SYSTEM_DPSIEGR1_DIRQ12EG_Msk (0x10UL) /*!< DIRQ12EG (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIEGR1_DIRQ13EG_Pos (5UL) /*!< DIRQ13EG (Bit 5) */
|
|
|
+ #define R_SYSTEM_DPSIEGR1_DIRQ13EG_Msk (0x20UL) /*!< DIRQ13EG (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIEGR1_DIRQ14EG_Pos (6UL) /*!< DIRQ14EG (Bit 6) */
|
|
|
+ #define R_SYSTEM_DPSIEGR1_DIRQ14EG_Msk (0x40UL) /*!< DIRQ14EG (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIEGR1_DIRQ15EG_Pos (7UL) /*!< DIRQ15EG (Bit 7) */
|
|
|
+ #define R_SYSTEM_DPSIEGR1_DIRQ15EG_Msk (0x80UL) /*!< DIRQ15EG (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= DPSIEGR2 ======================================================== */
|
|
|
+ #define R_SYSTEM_DPSIEGR2_DPVD1EG_Pos (0UL) /*!< DPVD1EG (Bit 0) */
|
|
|
+ #define R_SYSTEM_DPSIEGR2_DPVD1EG_Msk (0x1UL) /*!< DPVD1EG (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIEGR2_DPVD2EG_Pos (1UL) /*!< DPVD2EG (Bit 1) */
|
|
|
+ #define R_SYSTEM_DPSIEGR2_DPVD2EG_Msk (0x2UL) /*!< DPVD2EG (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos (4UL) /*!< DNMIEG (Bit 4) */
|
|
|
+ #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk (0x10UL) /*!< DNMIEG (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== SYOCDCR ======================================================== */
|
|
|
+ #define R_SYSTEM_SYOCDCR_DOCDF_Pos (0UL) /*!< DOCDF (Bit 0) */
|
|
|
+ #define R_SYSTEM_SYOCDCR_DOCDF_Msk (0x1UL) /*!< DOCDF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_SYOCDCR_DBGEN_Pos (7UL) /*!< DBGEN (Bit 7) */
|
|
|
+ #define R_SYSTEM_SYOCDCR_DBGEN_Msk (0x80UL) /*!< DBGEN (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== RSTSR0 ========================================================= */
|
|
|
+ #define R_SYSTEM_RSTSR0_PORF_Pos (0UL) /*!< PORF (Bit 0) */
|
|
|
+ #define R_SYSTEM_RSTSR0_PORF_Msk (0x1UL) /*!< PORF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_RSTSR0_LVD0RF_Pos (1UL) /*!< LVD0RF (Bit 1) */
|
|
|
+ #define R_SYSTEM_RSTSR0_LVD0RF_Msk (0x2UL) /*!< LVD0RF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_RSTSR0_LVD1RF_Pos (2UL) /*!< LVD1RF (Bit 2) */
|
|
|
+ #define R_SYSTEM_RSTSR0_LVD1RF_Msk (0x4UL) /*!< LVD1RF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_RSTSR0_LVD2RF_Pos (3UL) /*!< LVD2RF (Bit 3) */
|
|
|
+ #define R_SYSTEM_RSTSR0_LVD2RF_Msk (0x8UL) /*!< LVD2RF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_RSTSR0_LVD3RF_Pos (4UL) /*!< LVD3RF (Bit 4) */
|
|
|
+ #define R_SYSTEM_RSTSR0_LVD3RF_Msk (0x10UL) /*!< LVD3RF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_RSTSR0_LVD4RF_Pos (5UL) /*!< LVD4RF (Bit 5) */
|
|
|
+ #define R_SYSTEM_RSTSR0_LVD4RF_Msk (0x20UL) /*!< LVD4RF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_RSTSR0_LVD5RF_Pos (6UL) /*!< LVD5RF (Bit 6) */
|
|
|
+ #define R_SYSTEM_RSTSR0_LVD5RF_Msk (0x40UL) /*!< LVD5RF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_RSTSR0_DPSRSTF_Pos (7UL) /*!< DPSRSTF (Bit 7) */
|
|
|
+ #define R_SYSTEM_RSTSR0_DPSRSTF_Msk (0x80UL) /*!< DPSRSTF (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== RSTSR2 ========================================================= */
|
|
|
+ #define R_SYSTEM_RSTSR2_CWSF_Pos (0UL) /*!< CWSF (Bit 0) */
|
|
|
+ #define R_SYSTEM_RSTSR2_CWSF_Msk (0x1UL) /*!< CWSF (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== RSTSR3 ========================================================= */
|
|
|
+ #define R_SYSTEM_RSTSR3_OCPRF_Pos (4UL) /*!< OCPRF (Bit 4) */
|
|
|
+ #define R_SYSTEM_RSTSR3_OCPRF_Msk (0x10UL) /*!< OCPRF (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= MOMCR ========================================================= */
|
|
|
+ #define R_SYSTEM_MOMCR_MODRV0_Pos (1UL) /*!< MODRV0 (Bit 1) */
|
|
|
+ #define R_SYSTEM_MOMCR_MODRV0_Msk (0xeUL) /*!< MODRV0 (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_SYSTEM_MOMCR_MOSEL_Pos (6UL) /*!< MOSEL (Bit 6) */
|
|
|
+ #define R_SYSTEM_MOMCR_MOSEL_Msk (0x40UL) /*!< MOSEL (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== FWEPROR ======================================================== */
|
|
|
+ #define R_SYSTEM_FWEPROR_FLWE_Pos (0UL) /*!< FLWE (Bit 0) */
|
|
|
+ #define R_SYSTEM_FWEPROR_FLWE_Msk (0x3UL) /*!< FLWE (Bitfield-Mask: 0x03) */
|
|
|
+/* ======================================================== LVCMPCR ======================================================== */
|
|
|
+ #define R_SYSTEM_LVCMPCR_LVD2E_Pos (6UL) /*!< LVD2E (Bit 6) */
|
|
|
+ #define R_SYSTEM_LVCMPCR_LVD2E_Msk (0x40UL) /*!< LVD2E (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_LVCMPCR_LVD1E_Pos (5UL) /*!< LVD1E (Bit 5) */
|
|
|
+ #define R_SYSTEM_LVCMPCR_LVD1E_Msk (0x20UL) /*!< LVD1E (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= LVD1CMPCR ======================================================= */
|
|
|
+ #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */
|
|
|
+ #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */
|
|
|
+ #define R_SYSTEM_LVD1CMPCR_LVD1E_Pos (7UL) /*!< LVD1E (Bit 7) */
|
|
|
+ #define R_SYSTEM_LVD1CMPCR_LVD1E_Msk (0x80UL) /*!< LVD1E (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= LVD2CMPCR ======================================================= */
|
|
|
+ #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Pos (0UL) /*!< LVD2LVL (Bit 0) */
|
|
|
+ #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Msk (0x1fUL) /*!< LVD2LVL (Bitfield-Mask: 0x1f) */
|
|
|
+ #define R_SYSTEM_LVD2CMPCR_LVD2E_Pos (7UL) /*!< LVD2E (Bit 7) */
|
|
|
+ #define R_SYSTEM_LVD2CMPCR_LVD2E_Msk (0x80UL) /*!< LVD2E (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== LVD1CR0 ======================================================== */
|
|
|
+ #define R_SYSTEM_LVD1CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */
|
|
|
+ #define R_SYSTEM_LVD1CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_LVD1CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */
|
|
|
+ #define R_SYSTEM_LVD1CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_LVD1CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */
|
|
|
+ #define R_SYSTEM_LVD1CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_LVD1CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */
|
|
|
+ #define R_SYSTEM_LVD1CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_SYSTEM_LVD1CR0_RI_Pos (6UL) /*!< RI (Bit 6) */
|
|
|
+ #define R_SYSTEM_LVD1CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_LVD1CR0_RN_Pos (7UL) /*!< RN (Bit 7) */
|
|
|
+ #define R_SYSTEM_LVD1CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== LVD2CR0 ======================================================== */
|
|
|
+ #define R_SYSTEM_LVD2CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */
|
|
|
+ #define R_SYSTEM_LVD2CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_LVD2CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */
|
|
|
+ #define R_SYSTEM_LVD2CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_LVD2CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */
|
|
|
+ #define R_SYSTEM_LVD2CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_LVD2CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */
|
|
|
+ #define R_SYSTEM_LVD2CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_SYSTEM_LVD2CR0_RI_Pos (6UL) /*!< RI (Bit 6) */
|
|
|
+ #define R_SYSTEM_LVD2CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_LVD2CR0_RN_Pos (7UL) /*!< RN (Bit 7) */
|
|
|
+ #define R_SYSTEM_LVD2CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */
|
|
|
+/* ====================================================== VBATTMNSELR ====================================================== */
|
|
|
+ #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos (0UL) /*!< VBATTMNSEL (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk (0x1UL) /*!< VBATTMNSEL (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= VBTBPCR1 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBPCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBPCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= LPSCR ========================================================= */
|
|
|
+ #define R_SYSTEM_LPSCR_LPMD_Pos (0UL) /*!< LPMD (Bit 0) */
|
|
|
+ #define R_SYSTEM_LPSCR_LPMD_Msk (0xfUL) /*!< LPMD (Bitfield-Mask: 0x0f) */
|
|
|
+/* ========================================================= SSCR1 ========================================================= */
|
|
|
+ #define R_SYSTEM_SSCR1_SS1FR_Pos (0UL) /*!< SS1FR (Bit 0) */
|
|
|
+ #define R_SYSTEM_SSCR1_SS1FR_Msk (0x1UL) /*!< SS1FR (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= LVOCR ========================================================= */
|
|
|
+ #define R_SYSTEM_LVOCR_LVO0E_Pos (0UL) /*!< LVO0E (Bit 0) */
|
|
|
+ #define R_SYSTEM_LVOCR_LVO0E_Msk (0x1UL) /*!< LVO0E (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_LVOCR_LVO1E_Pos (1UL) /*!< LVO1E (Bit 1) */
|
|
|
+ #define R_SYSTEM_LVOCR_LVO1E_Msk (0x2UL) /*!< LVO1E (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= SYRSTMSK0 ======================================================= */
|
|
|
+ #define R_SYSTEM_SYRSTMSK0_IWDTMASK_Pos (0UL) /*!< IWDTMASK (Bit 0) */
|
|
|
+ #define R_SYSTEM_SYRSTMSK0_IWDTMASK_Msk (0x1UL) /*!< IWDTMASK (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_SYRSTMSK0_WDT0MASK_Pos (1UL) /*!< WDT0MASK (Bit 1) */
|
|
|
+ #define R_SYSTEM_SYRSTMSK0_WDT0MASK_Msk (0x2UL) /*!< WDT0MASK (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_SYRSTMSK0_SWMASK_Pos (2UL) /*!< SWMASK (Bit 2) */
|
|
|
+ #define R_SYSTEM_SYRSTMSK0_SWMASK_Msk (0x4UL) /*!< SWMASK (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_SYRSTMSK0_CLUP0MASK_Pos (4UL) /*!< CLUP0MASK (Bit 4) */
|
|
|
+ #define R_SYSTEM_SYRSTMSK0_CLUP0MASK_Msk (0x10UL) /*!< CLUP0MASK (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_SYRSTMSK0_LM0MASK_Pos (5UL) /*!< LM0MASK (Bit 5) */
|
|
|
+ #define R_SYSTEM_SYRSTMSK0_LM0MASK_Msk (0x20UL) /*!< LM0MASK (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_SYRSTMSK0_CMMASK_Pos (6UL) /*!< CMMASK (Bit 6) */
|
|
|
+ #define R_SYSTEM_SYRSTMSK0_CMMASK_Msk (0x40UL) /*!< CMMASK (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_SYRSTMSK0_BUSMASK_Pos (7UL) /*!< BUSMASK (Bit 7) */
|
|
|
+ #define R_SYSTEM_SYRSTMSK0_BUSMASK_Msk (0x80UL) /*!< BUSMASK (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= SYRSTMSK1 ======================================================= */
|
|
|
+ #define R_SYSTEM_SYRSTMSK1_WDT1MASK_Pos (1UL) /*!< WDT1MASK (Bit 1) */
|
|
|
+ #define R_SYSTEM_SYRSTMSK1_WDT1MASK_Msk (0x2UL) /*!< WDT1MASK (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_SYRSTMSK1_CLUP1MASK_Pos (4UL) /*!< CLUP1MASK (Bit 4) */
|
|
|
+ #define R_SYSTEM_SYRSTMSK1_CLUP1MASK_Msk (0x10UL) /*!< CLUP1MASK (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_SYRSTMSK1_LM1MASK_Pos (5UL) /*!< LM1MASK (Bit 5) */
|
|
|
+ #define R_SYSTEM_SYRSTMSK1_LM1MASK_Msk (0x20UL) /*!< LM1MASK (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_SYRSTMSK1_NWMASK_Pos (7UL) /*!< NWMASK (Bit 7) */
|
|
|
+ #define R_SYSTEM_SYRSTMSK1_NWMASK_Msk (0x80UL) /*!< NWMASK (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= SYRSTMSK2 ======================================================= */
|
|
|
+ #define R_SYSTEM_SYRSTMSK2_LVD1MASK_Pos (0UL) /*!< LVD1MASK (Bit 0) */
|
|
|
+ #define R_SYSTEM_SYRSTMSK2_LVD1MASK_Msk (0x1UL) /*!< LVD1MASK (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_SYRSTMSK2_LVD2MASK_Pos (1UL) /*!< LVD2MASK (Bit 1) */
|
|
|
+ #define R_SYSTEM_SYRSTMSK2_LVD2MASK_Msk (0x2UL) /*!< LVD2MASK (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_SYRSTMSK2_LVD3MASK_Pos (2UL) /*!< LVD3MASK (Bit 2) */
|
|
|
+ #define R_SYSTEM_SYRSTMSK2_LVD3MASK_Msk (0x4UL) /*!< LVD3MASK (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_SYRSTMSK2_LVD4MASK_Pos (3UL) /*!< LVD4MASK (Bit 3) */
|
|
|
+ #define R_SYSTEM_SYRSTMSK2_LVD4MASK_Msk (0x8UL) /*!< LVD4MASK (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_SYRSTMSK2_LVD5MASK_Pos (4UL) /*!< LVD5MASK (Bit 4) */
|
|
|
+ #define R_SYSTEM_SYRSTMSK2_LVD5MASK_Msk (0x10UL) /*!< LVD5MASK (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= PLL1LDOCR ======================================================= */
|
|
|
+ #define R_SYSTEM_PLL1LDOCR_LDOSTP_Pos (0UL) /*!< LDOSTP (Bit 0) */
|
|
|
+ #define R_SYSTEM_PLL1LDOCR_LDOSTP_Msk (0x1UL) /*!< LDOSTP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_PLL1LDOCR_SKEEP_Pos (1UL) /*!< SKEEP (Bit 1) */
|
|
|
+ #define R_SYSTEM_PLL1LDOCR_SKEEP_Msk (0x2UL) /*!< SKEEP (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= PLL2LDOCR ======================================================= */
|
|
|
+ #define R_SYSTEM_PLL2LDOCR_LDOSTP_Pos (0UL) /*!< LDOSTP (Bit 0) */
|
|
|
+ #define R_SYSTEM_PLL2LDOCR_LDOSTP_Msk (0x1UL) /*!< LDOSTP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_PLL2LDOCR_SKEEP_Pos (1UL) /*!< SKEEP (Bit 1) */
|
|
|
+ #define R_SYSTEM_PLL2LDOCR_SKEEP_Msk (0x2UL) /*!< SKEEP (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= HOCOLDOCR ======================================================= */
|
|
|
+ #define R_SYSTEM_HOCOLDOCR_LDOSTP_Pos (0UL) /*!< LDOSTP (Bit 0) */
|
|
|
+ #define R_SYSTEM_HOCOLDOCR_LDOSTP_Msk (0x1UL) /*!< LDOSTP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_HOCOLDOCR_SKEEP_Pos (1UL) /*!< SKEEP (Bit 1) */
|
|
|
+ #define R_SYSTEM_HOCOLDOCR_SKEEP_Msk (0x2UL) /*!< SKEEP (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== LVD1FCR ======================================================== */
|
|
|
+ #define R_SYSTEM_LVD1FCR_RHSEL_Pos (0UL) /*!< RHSEL (Bit 0) */
|
|
|
+ #define R_SYSTEM_LVD1FCR_RHSEL_Msk (0x1UL) /*!< RHSEL (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== LVD2FCR ======================================================== */
|
|
|
+ #define R_SYSTEM_LVD2FCR_RHSEL_Pos (0UL) /*!< RHSEL (Bit 0) */
|
|
|
+ #define R_SYSTEM_LVD2FCR_RHSEL_Msk (0x1UL) /*!< RHSEL (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== SOSCCR ========================================================= */
|
|
|
+ #define R_SYSTEM_SOSCCR_SOSTP_Pos (0UL) /*!< SOSTP (Bit 0) */
|
|
|
+ #define R_SYSTEM_SOSCCR_SOSTP_Msk (0x1UL) /*!< SOSTP (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= SOMCR ========================================================= */
|
|
|
+ #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */
|
|
|
+ #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_SYSTEM_SOMCR_SOSEL_Pos (6UL) /*!< SOSEL (Bit 6) */
|
|
|
+ #define R_SYSTEM_SOMCR_SOSEL_Msk (0x40UL) /*!< SOSEL (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== VBTBER ========================================================= */
|
|
|
+ #define R_SYSTEM_VBTBER_VBAE_Pos (3UL) /*!< VBAE (Bit 3) */
|
|
|
+ #define R_SYSTEM_VBTBER_VBAE_Msk (0x8UL) /*!< VBAE (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= VBTBPCR2 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBPCR2_VDETLVL_Pos (0UL) /*!< VDETLVL (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBPCR2_VDETLVL_Msk (0x7UL) /*!< VDETLVL (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_SYSTEM_VBTBPCR2_VDETE_Pos (4UL) /*!< VDETE (Bit 4) */
|
|
|
+ #define R_SYSTEM_VBTBPCR2_VDETE_Msk (0x10UL) /*!< VDETE (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== VBTBPSR ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBPSR_VBPORF_Pos (0UL) /*!< VBPORF (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBPSR_VBPORF_Msk (0x1UL) /*!< VBPORF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_VBTBPSR_VBPORM_Pos (4UL) /*!< VBPORM (Bit 4) */
|
|
|
+ #define R_SYSTEM_VBTBPSR_VBPORM_Msk (0x10UL) /*!< VBPORM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_VBTBPSR_BPWSWM_Pos (5UL) /*!< BPWSWM (Bit 5) */
|
|
|
+ #define R_SYSTEM_VBTBPSR_BPWSWM_Msk (0x20UL) /*!< BPWSWM (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== VBTADSR ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTADSR_VBTADF0_Pos (0UL) /*!< VBTADF0 (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTADSR_VBTADF0_Msk (0x1UL) /*!< VBTADF0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_VBTADSR_VBTADF1_Pos (1UL) /*!< VBTADF1 (Bit 1) */
|
|
|
+ #define R_SYSTEM_VBTADSR_VBTADF1_Msk (0x2UL) /*!< VBTADF1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_VBTADSR_VBTADF2_Pos (2UL) /*!< VBTADF2 (Bit 2) */
|
|
|
+ #define R_SYSTEM_VBTADSR_VBTADF2_Msk (0x4UL) /*!< VBTADF2 (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= VBTADCR1 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTADCR1_VBTADIE0_Pos (0UL) /*!< VBTADIE0 (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTADCR1_VBTADIE0_Msk (0x1UL) /*!< VBTADIE0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_VBTADCR1_VBTADIE1_Pos (1UL) /*!< VBTADIE1 (Bit 1) */
|
|
|
+ #define R_SYSTEM_VBTADCR1_VBTADIE1_Msk (0x2UL) /*!< VBTADIE1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_VBTADCR1_VBTADIE2_Pos (2UL) /*!< VBTADIE2 (Bit 2) */
|
|
|
+ #define R_SYSTEM_VBTADCR1_VBTADIE2_Msk (0x4UL) /*!< VBTADIE2 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_VBTADCR1_VBTADCLE0_Pos (4UL) /*!< VBTADCLE0 (Bit 4) */
|
|
|
+ #define R_SYSTEM_VBTADCR1_VBTADCLE0_Msk (0x10UL) /*!< VBTADCLE0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_VBTADCR1_VBTADCLE1_Pos (5UL) /*!< VBTADCLE1 (Bit 5) */
|
|
|
+ #define R_SYSTEM_VBTADCR1_VBTADCLE1_Msk (0x20UL) /*!< VBTADCLE1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_VBTADCR1_VBTADCLE2_Pos (6UL) /*!< VBTADCLE2 (Bit 6) */
|
|
|
+ #define R_SYSTEM_VBTADCR1_VBTADCLE2_Msk (0x40UL) /*!< VBTADCLE2 (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= VBTADCR2 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTADCR2_VBRTCES0_Pos (0UL) /*!< VBRTCES0 (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTADCR2_VBRTCES0_Msk (0x1UL) /*!< VBRTCES0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_VBTADCR2_VBRTCES1_Pos (1UL) /*!< VBRTCES1 (Bit 1) */
|
|
|
+ #define R_SYSTEM_VBTADCR2_VBRTCES1_Msk (0x2UL) /*!< VBRTCES1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_VBTADCR2_VBRTCES2_Pos (2UL) /*!< VBRTCES2 (Bit 2) */
|
|
|
+ #define R_SYSTEM_VBTADCR2_VBRTCES2_Msk (0x4UL) /*!< VBRTCES2 (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= VBTICTLR ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos (0UL) /*!< VCH0INEN (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk (0x1UL) /*!< VCH0INEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos (1UL) /*!< VCH1INEN (Bit 1) */
|
|
|
+ #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk (0x2UL) /*!< VCH1INEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos (2UL) /*!< VCH2INEN (Bit 2) */
|
|
|
+ #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk (0x4UL) /*!< VCH2INEN (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= VBTICTLR2 ======================================================= */
|
|
|
+ #define R_SYSTEM_VBTICTLR2_VCH0NCE_Pos (0UL) /*!< VCH0NCE (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTICTLR2_VCH0NCE_Msk (0x1UL) /*!< VCH0NCE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_VBTICTLR2_VCH1NCE_Pos (1UL) /*!< VCH1NCE (Bit 1) */
|
|
|
+ #define R_SYSTEM_VBTICTLR2_VCH1NCE_Msk (0x2UL) /*!< VCH1NCE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_VBTICTLR2_VCH2NCE_Pos (2UL) /*!< VCH2NCE (Bit 2) */
|
|
|
+ #define R_SYSTEM_VBTICTLR2_VCH2NCE_Msk (0x4UL) /*!< VCH2NCE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_VBTICTLR2_VCH0EG_Pos (4UL) /*!< VCH0EG (Bit 4) */
|
|
|
+ #define R_SYSTEM_VBTICTLR2_VCH0EG_Msk (0x10UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_VBTICTLR2_VCH1EG_Pos (5UL) /*!< VCH1EG (Bit 5) */
|
|
|
+ #define R_SYSTEM_VBTICTLR2_VCH1EG_Msk (0x20UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_VBTICTLR2_VCH2EG_Pos (6UL) /*!< VCH2EG (Bit 6) */
|
|
|
+ #define R_SYSTEM_VBTICTLR2_VCH2EG_Msk (0x40UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= VBTIMONR ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTIMONR_VCH0MON_Pos (0UL) /*!< VCH0MON (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTIMONR_VCH0MON_Msk (0x1UL) /*!< VCH0MON (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_VBTIMONR_VCH1MON_Pos (1UL) /*!< VCH1MON (Bit 1) */
|
|
|
+ #define R_SYSTEM_VBTIMONR_VCH1MON_Msk (0x2UL) /*!< VCH1MON (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SYSTEM_VBTIMONR_VCH2MON_Pos (2UL) /*!< VCH2MON (Bit 2) */
|
|
|
+ #define R_SYSTEM_VBTIMONR_VCH2MON_Msk (0x4UL) /*!< VCH2MON (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== VBTBKR0 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR0_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR0_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== VBTBKR1 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR1_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR1_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== VBTBKR2 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR2_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR2_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== VBTBKR3 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR3_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR3_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== VBTBKR4 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR4_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR4_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== VBTBKR5 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR5_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR5_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== VBTBKR6 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR6_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR6_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== VBTBKR7 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR7_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR7_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== VBTBKR8 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR8_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR8_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== VBTBKR9 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR9_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR9_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR10 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR10_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR10_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR11 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR11_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR11_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR12 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR12_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR12_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR13 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR13_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR13_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR14 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR14_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR14_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR15 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR15_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR15_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR16 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR16_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR16_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR17 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR17_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR17_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR18 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR18_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR18_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR19 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR19_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR19_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR20 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR20_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR20_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR21 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR21_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR21_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR22 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR22_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR22_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR23 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR23_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR23_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR24 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR24_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR24_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR25 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR25_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR25_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR26 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR26_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR26_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR27 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR27_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR27_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR28 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR28_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR28_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR29 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR29_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR29_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR30 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR30_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR30_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR31 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR31_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR31_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR32 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR32_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR32_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR33 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR33_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR33_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR34 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR34_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR34_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR35 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR35_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR35_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR36 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR36_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR36_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR37 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR37_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR37_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR38 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR38_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR38_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR39 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR39_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR39_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR40 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR40_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR40_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR41 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR41_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR41_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR42 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR42_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR42_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR43 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR43_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR43_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR44 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR44_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR44_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR45 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR45_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR45_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR46 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR46_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR46_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR47 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR47_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR47_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR48 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR48_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR48_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR49 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR49_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR49_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR50 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR50_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR50_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR51 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR51_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR51_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR52 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR52_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR52_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR53 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR53_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR53_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR54 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR54_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR54_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR55 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR55_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR55_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR56 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR56_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR56_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR57 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR57_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR57_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR58 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR58_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR58_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR59 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR59_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR59_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR60 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR60_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR60_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR61 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR61_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR61_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR62 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR62_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR62_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR63 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR63_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR63_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR64 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR64_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR64_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR65 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR65_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR65_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR66 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR66_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR66_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR67 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR67_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR67_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR68 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR68_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR68_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR69 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR69_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR69_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR70 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR70_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR70_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR71 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR71_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR71_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR72 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR72_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR72_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR73 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR73_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR73_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR74 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR74_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR74_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR75 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR75_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR75_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR76 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR76_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR76_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR77 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR77_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR77_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR78 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR78_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR78_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR79 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR79_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR79_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR80 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR80_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR80_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR81 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR81_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR81_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR82 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR82_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR82_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR83 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR83_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR83_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR84 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR84_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR84_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR85 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR85_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR85_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR86 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR86_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR86_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR87 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR87_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR87_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR88 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR88_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR88_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR89 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR89_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR89_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR90 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR90_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR90_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR91 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR91_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR91_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR92 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR92_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR92_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR93 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR93_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR93_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR94 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR94_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR94_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR95 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR95_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR95_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR96 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR96_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR96_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR97 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR97_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR97_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR98 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR98_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR98_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR99 ======================================================== */
|
|
|
+ #define R_SYSTEM_VBTBKR99_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR99_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR100 ======================================================= */
|
|
|
+ #define R_SYSTEM_VBTBKR100_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR100_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR101 ======================================================= */
|
|
|
+ #define R_SYSTEM_VBTBKR101_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR101_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR102 ======================================================= */
|
|
|
+ #define R_SYSTEM_VBTBKR102_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR102_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR103 ======================================================= */
|
|
|
+ #define R_SYSTEM_VBTBKR103_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR103_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR104 ======================================================= */
|
|
|
+ #define R_SYSTEM_VBTBKR104_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR104_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR105 ======================================================= */
|
|
|
+ #define R_SYSTEM_VBTBKR105_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR105_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR106 ======================================================= */
|
|
|
+ #define R_SYSTEM_VBTBKR106_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR106_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR107 ======================================================= */
|
|
|
+ #define R_SYSTEM_VBTBKR107_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR107_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR108 ======================================================= */
|
|
|
+ #define R_SYSTEM_VBTBKR108_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR108_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR109 ======================================================= */
|
|
|
+ #define R_SYSTEM_VBTBKR109_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR109_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR110 ======================================================= */
|
|
|
+ #define R_SYSTEM_VBTBKR110_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR110_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR111 ======================================================= */
|
|
|
+ #define R_SYSTEM_VBTBKR111_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR111_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR112 ======================================================= */
|
|
|
+ #define R_SYSTEM_VBTBKR112_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR112_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR113 ======================================================= */
|
|
|
+ #define R_SYSTEM_VBTBKR113_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR113_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR114 ======================================================= */
|
|
|
+ #define R_SYSTEM_VBTBKR114_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR114_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR115 ======================================================= */
|
|
|
+ #define R_SYSTEM_VBTBKR115_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR115_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR116 ======================================================= */
|
|
|
+ #define R_SYSTEM_VBTBKR116_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR116_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR117 ======================================================= */
|
|
|
+ #define R_SYSTEM_VBTBKR117_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR117_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR118 ======================================================= */
|
|
|
+ #define R_SYSTEM_VBTBKR118_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR118_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR119 ======================================================= */
|
|
|
+ #define R_SYSTEM_VBTBKR119_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR119_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR120 ======================================================= */
|
|
|
+ #define R_SYSTEM_VBTBKR120_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR120_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR121 ======================================================= */
|
|
|
+ #define R_SYSTEM_VBTBKR121_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR121_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR122 ======================================================= */
|
|
|
+ #define R_SYSTEM_VBTBKR122_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR122_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR123 ======================================================= */
|
|
|
+ #define R_SYSTEM_VBTBKR123_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR123_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR124 ======================================================= */
|
|
|
+ #define R_SYSTEM_VBTBKR124_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR124_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR125 ======================================================= */
|
|
|
+ #define R_SYSTEM_VBTBKR125_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR125_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR126 ======================================================= */
|
|
|
+ #define R_SYSTEM_VBTBKR126_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR126_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= VBTBKR127 ======================================================= */
|
|
|
+ #define R_SYSTEM_VBTBKR127_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */
|
|
|
+ #define R_SYSTEM_VBTBKR127_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_TSN_CAL ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================= TSCDR ========================================================= */
|
|
|
+ #define R_TSN_CAL_TSCDR_TSCDR_Pos (0UL) /*!< TSCDR (Bit 0) */
|
|
|
+ #define R_TSN_CAL_TSCDR_TSCDR_Msk (0xffffffffUL) /*!< TSCDR (Bitfield-Mask: 0xffffffff) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_TSN_CTRL ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================= TSCR ========================================================== */
|
|
|
+ #define R_TSN_CTRL_TSCR_TSEN_Pos (7UL) /*!< TSEN (Bit 7) */
|
|
|
+ #define R_TSN_CTRL_TSCR_TSEN_Msk (0x80UL) /*!< TSEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_TSN_CTRL_TSCR_TSOE_Pos (4UL) /*!< TSOE (Bit 4) */
|
|
|
+ #define R_TSN_CTRL_TSCR_TSOE_Msk (0x10UL) /*!< TSOE (Bitfield-Mask: 0x01) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_USB_FS0 ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ======================================================== SYSCFG ========================================================= */
|
|
|
+ #define R_USB_FS0_SYSCFG_SCKE_Pos (10UL) /*!< SCKE (Bit 10) */
|
|
|
+ #define R_USB_FS0_SYSCFG_SCKE_Msk (0x400UL) /*!< SCKE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */
|
|
|
+ #define R_USB_FS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */
|
|
|
+ #define R_USB_FS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */
|
|
|
+ #define R_USB_FS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */
|
|
|
+ #define R_USB_FS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_SYSCFG_DMRPU_Pos (3UL) /*!< DMRPU (Bit 3) */
|
|
|
+ #define R_USB_FS0_SYSCFG_DMRPU_Msk (0x8UL) /*!< DMRPU (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */
|
|
|
+ #define R_USB_FS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== BUSWAIT ======================================================== */
|
|
|
+ #define R_USB_FS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */
|
|
|
+ #define R_USB_FS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */
|
|
|
+/* ======================================================== SYSSTS0 ======================================================== */
|
|
|
+ #define R_USB_FS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */
|
|
|
+ #define R_USB_FS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_USB_FS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */
|
|
|
+ #define R_USB_FS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */
|
|
|
+ #define R_USB_FS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */
|
|
|
+ #define R_USB_FS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */
|
|
|
+ #define R_USB_FS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */
|
|
|
+/* ======================================================== PLLSTA ========================================================= */
|
|
|
+ #define R_USB_FS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */
|
|
|
+ #define R_USB_FS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= DVSTCTR0 ======================================================== */
|
|
|
+ #define R_USB_FS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */
|
|
|
+ #define R_USB_FS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */
|
|
|
+ #define R_USB_FS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */
|
|
|
+ #define R_USB_FS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */
|
|
|
+ #define R_USB_FS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */
|
|
|
+ #define R_USB_FS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */
|
|
|
+ #define R_USB_FS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */
|
|
|
+ #define R_USB_FS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */
|
|
|
+ #define R_USB_FS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */
|
|
|
+ #define R_USB_FS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */
|
|
|
+/* ======================================================= TESTMODE ======================================================== */
|
|
|
+ #define R_USB_FS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */
|
|
|
+ #define R_USB_FS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */
|
|
|
+/* ======================================================== CFIFOL ========================================================= */
|
|
|
+/* ======================================================== CFIFOLL ======================================================== */
|
|
|
+/* ========================================================= CFIFO ========================================================= */
|
|
|
+/* ======================================================== CFIFOH ========================================================= */
|
|
|
+/* ======================================================== CFIFOHH ======================================================== */
|
|
|
+/* ======================================================== D0FIFOL ======================================================== */
|
|
|
+/* ======================================================= D0FIFOLL ======================================================== */
|
|
|
+/* ======================================================== D0FIFO ========================================================= */
|
|
|
+/* ======================================================== D0FIFOH ======================================================== */
|
|
|
+/* ======================================================= D0FIFOHH ======================================================== */
|
|
|
+/* ======================================================== D1FIFOL ======================================================== */
|
|
|
+/* ======================================================= D1FIFOLL ======================================================== */
|
|
|
+/* ======================================================== D1FIFO ========================================================= */
|
|
|
+/* ======================================================== D1FIFOH ======================================================== */
|
|
|
+/* ======================================================= D1FIFOHH ======================================================== */
|
|
|
+/* ======================================================= CFIFOSEL ======================================================== */
|
|
|
+ #define R_USB_FS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */
|
|
|
+ #define R_USB_FS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */
|
|
|
+ #define R_USB_FS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */
|
|
|
+ #define R_USB_FS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_USB_FS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */
|
|
|
+ #define R_USB_FS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */
|
|
|
+ #define R_USB_FS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */
|
|
|
+ #define R_USB_FS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */
|
|
|
+/* ======================================================= CFIFOCTR ======================================================== */
|
|
|
+ #define R_USB_FS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */
|
|
|
+ #define R_USB_FS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */
|
|
|
+ #define R_USB_FS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */
|
|
|
+ #define R_USB_FS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */
|
|
|
+ #define R_USB_FS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */
|
|
|
+/* ======================================================= D0FIFOSEL ======================================================= */
|
|
|
+ #define R_USB_FS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */
|
|
|
+ #define R_USB_FS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */
|
|
|
+ #define R_USB_FS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */
|
|
|
+ #define R_USB_FS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */
|
|
|
+ #define R_USB_FS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */
|
|
|
+ #define R_USB_FS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_USB_FS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */
|
|
|
+ #define R_USB_FS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */
|
|
|
+ #define R_USB_FS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */
|
|
|
+/* ======================================================= D0FIFOCTR ======================================================= */
|
|
|
+ #define R_USB_FS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */
|
|
|
+ #define R_USB_FS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */
|
|
|
+ #define R_USB_FS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */
|
|
|
+ #define R_USB_FS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */
|
|
|
+ #define R_USB_FS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */
|
|
|
+/* ======================================================= D1FIFOSEL ======================================================= */
|
|
|
+ #define R_USB_FS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */
|
|
|
+ #define R_USB_FS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */
|
|
|
+ #define R_USB_FS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */
|
|
|
+ #define R_USB_FS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */
|
|
|
+ #define R_USB_FS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */
|
|
|
+ #define R_USB_FS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_USB_FS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */
|
|
|
+ #define R_USB_FS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */
|
|
|
+ #define R_USB_FS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */
|
|
|
+/* ======================================================= D1FIFOCTR ======================================================= */
|
|
|
+ #define R_USB_FS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */
|
|
|
+ #define R_USB_FS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */
|
|
|
+ #define R_USB_FS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */
|
|
|
+ #define R_USB_FS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */
|
|
|
+ #define R_USB_FS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */
|
|
|
+/* ======================================================== INTENB0 ======================================================== */
|
|
|
+ #define R_USB_FS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */
|
|
|
+ #define R_USB_FS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */
|
|
|
+ #define R_USB_FS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */
|
|
|
+ #define R_USB_FS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */
|
|
|
+ #define R_USB_FS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */
|
|
|
+ #define R_USB_FS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */
|
|
|
+ #define R_USB_FS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */
|
|
|
+ #define R_USB_FS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */
|
|
|
+ #define R_USB_FS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== INTENB1 ======================================================== */
|
|
|
+ #define R_USB_FS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */
|
|
|
+ #define R_USB_FS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */
|
|
|
+ #define R_USB_FS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */
|
|
|
+ #define R_USB_FS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */
|
|
|
+ #define R_USB_FS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */
|
|
|
+ #define R_USB_FS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */
|
|
|
+ #define R_USB_FS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */
|
|
|
+ #define R_USB_FS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */
|
|
|
+ #define R_USB_FS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== BRDYENB ======================================================== */
|
|
|
+ #define R_USB_FS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */
|
|
|
+ #define R_USB_FS0_BRDYENB_PIPEBRDYE_Msk (0x1UL) /*!< PIPEBRDYE (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== NRDYENB ======================================================== */
|
|
|
+ #define R_USB_FS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */
|
|
|
+ #define R_USB_FS0_NRDYENB_PIPENRDYE_Msk (0x1UL) /*!< PIPENRDYE (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== BEMPENB ======================================================== */
|
|
|
+ #define R_USB_FS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */
|
|
|
+ #define R_USB_FS0_BEMPENB_PIPEBEMPE_Msk (0x1UL) /*!< PIPEBEMPE (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== SOFCFG ========================================================= */
|
|
|
+ #define R_USB_FS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */
|
|
|
+ #define R_USB_FS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */
|
|
|
+ #define R_USB_FS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */
|
|
|
+ #define R_USB_FS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */
|
|
|
+ #define R_USB_FS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== PHYSET ========================================================= */
|
|
|
+ #define R_USB_FS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */
|
|
|
+ #define R_USB_FS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */
|
|
|
+ #define R_USB_FS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */
|
|
|
+ #define R_USB_FS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_USB_FS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */
|
|
|
+ #define R_USB_FS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_USB_FS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */
|
|
|
+ #define R_USB_FS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */
|
|
|
+ #define R_USB_FS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */
|
|
|
+ #define R_USB_FS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== INTSTS0 ======================================================== */
|
|
|
+ #define R_USB_FS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */
|
|
|
+ #define R_USB_FS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */
|
|
|
+ #define R_USB_FS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */
|
|
|
+ #define R_USB_FS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */
|
|
|
+ #define R_USB_FS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */
|
|
|
+ #define R_USB_FS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */
|
|
|
+ #define R_USB_FS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */
|
|
|
+ #define R_USB_FS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */
|
|
|
+ #define R_USB_FS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */
|
|
|
+ #define R_USB_FS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */
|
|
|
+ #define R_USB_FS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_USB_FS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */
|
|
|
+ #define R_USB_FS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */
|
|
|
+ #define R_USB_FS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */
|
|
|
+/* ======================================================== INTSTS1 ======================================================== */
|
|
|
+ #define R_USB_FS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */
|
|
|
+ #define R_USB_FS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */
|
|
|
+ #define R_USB_FS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */
|
|
|
+ #define R_USB_FS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */
|
|
|
+ #define R_USB_FS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */
|
|
|
+ #define R_USB_FS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */
|
|
|
+ #define R_USB_FS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */
|
|
|
+ #define R_USB_FS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */
|
|
|
+ #define R_USB_FS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */
|
|
|
+ #define R_USB_FS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */
|
|
|
+ #define R_USB_FS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== BRDYSTS ======================================================== */
|
|
|
+ #define R_USB_FS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */
|
|
|
+ #define R_USB_FS0_BRDYSTS_PIPEBRDY_Msk (0x1UL) /*!< PIPEBRDY (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== NRDYSTS ======================================================== */
|
|
|
+ #define R_USB_FS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */
|
|
|
+ #define R_USB_FS0_NRDYSTS_PIPENRDY_Msk (0x1UL) /*!< PIPENRDY (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== BEMPSTS ======================================================== */
|
|
|
+ #define R_USB_FS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */
|
|
|
+ #define R_USB_FS0_BEMPSTS_PIPEBEMP_Msk (0x1UL) /*!< PIPEBEMP (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== FRMNUM ========================================================= */
|
|
|
+ #define R_USB_FS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */
|
|
|
+ #define R_USB_FS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */
|
|
|
+ #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */
|
|
|
+ #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */
|
|
|
+/* ======================================================== UFRMNUM ======================================================== */
|
|
|
+ #define R_USB_FS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */
|
|
|
+ #define R_USB_FS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */
|
|
|
+ #define R_USB_FS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */
|
|
|
+/* ======================================================== USBADDR ======================================================== */
|
|
|
+ #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */
|
|
|
+ #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */
|
|
|
+ #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */
|
|
|
+/* ======================================================== USBREQ ========================================================= */
|
|
|
+ #define R_USB_FS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */
|
|
|
+ #define R_USB_FS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */
|
|
|
+ #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== USBVAL ========================================================= */
|
|
|
+ #define R_USB_FS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */
|
|
|
+ #define R_USB_FS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================== USBINDX ======================================================== */
|
|
|
+ #define R_USB_FS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */
|
|
|
+ #define R_USB_FS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================== USBLENG ======================================================== */
|
|
|
+ #define R_USB_FS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */
|
|
|
+ #define R_USB_FS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================== DCPCFG ========================================================= */
|
|
|
+ #define R_USB_FS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */
|
|
|
+ #define R_USB_FS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */
|
|
|
+ #define R_USB_FS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */
|
|
|
+ #define R_USB_FS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== DCPMAXP ======================================================== */
|
|
|
+ #define R_USB_FS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */
|
|
|
+ #define R_USB_FS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_USB_FS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */
|
|
|
+ #define R_USB_FS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */
|
|
|
+/* ======================================================== DCPCTR ========================================================= */
|
|
|
+ #define R_USB_FS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */
|
|
|
+ #define R_USB_FS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */
|
|
|
+ #define R_USB_FS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */
|
|
|
+ #define R_USB_FS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */
|
|
|
+ #define R_USB_FS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */
|
|
|
+ #define R_USB_FS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */
|
|
|
+ #define R_USB_FS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */
|
|
|
+ #define R_USB_FS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */
|
|
|
+ #define R_USB_FS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */
|
|
|
+ #define R_USB_FS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */
|
|
|
+/* ======================================================== PIPESEL ======================================================== */
|
|
|
+ #define R_USB_FS0_PIPESEL_PIPESEL_Pos (0UL) /*!< PIPESEL (Bit 0) */
|
|
|
+ #define R_USB_FS0_PIPESEL_PIPESEL_Msk (0xfUL) /*!< PIPESEL (Bitfield-Mask: 0x0f) */
|
|
|
+/* ======================================================== PIPECFG ======================================================== */
|
|
|
+ #define R_USB_FS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */
|
|
|
+ #define R_USB_FS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_USB_FS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */
|
|
|
+ #define R_USB_FS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */
|
|
|
+ #define R_USB_FS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */
|
|
|
+ #define R_USB_FS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */
|
|
|
+ #define R_USB_FS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */
|
|
|
+ #define R_USB_FS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */
|
|
|
+/* ======================================================= PIPEMAXP ======================================================== */
|
|
|
+ #define R_USB_FS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */
|
|
|
+ #define R_USB_FS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_USB_FS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */
|
|
|
+ #define R_USB_FS0_PIPEMAXP_MXPS_Msk (0x1ffUL) /*!< MXPS (Bitfield-Mask: 0x1ff) */
|
|
|
+/* ======================================================= PIPEPERI ======================================================== */
|
|
|
+ #define R_USB_FS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */
|
|
|
+ #define R_USB_FS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */
|
|
|
+ #define R_USB_FS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */
|
|
|
+/* ======================================================= PIPE_CTR ======================================================== */
|
|
|
+ #define R_USB_FS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */
|
|
|
+ #define R_USB_FS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */
|
|
|
+ #define R_USB_FS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */
|
|
|
+ #define R_USB_FS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */
|
|
|
+ #define R_USB_FS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */
|
|
|
+ #define R_USB_FS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */
|
|
|
+ #define R_USB_FS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */
|
|
|
+ #define R_USB_FS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */
|
|
|
+ #define R_USB_FS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */
|
|
|
+ #define R_USB_FS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */
|
|
|
+ #define R_USB_FS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */
|
|
|
+ #define R_USB_FS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */
|
|
|
+/* ======================================================== DEVADD ========================================================= */
|
|
|
+ #define R_USB_FS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */
|
|
|
+ #define R_USB_FS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_USB_FS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */
|
|
|
+ #define R_USB_FS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_USB_FS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */
|
|
|
+ #define R_USB_FS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */
|
|
|
+/* ====================================================== USBBCCTRL0 ======================================================= */
|
|
|
+ #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Pos (9UL) /*!< PDDETSTS0 (Bit 9) */
|
|
|
+ #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Msk (0x200UL) /*!< PDDETSTS0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Pos (8UL) /*!< CHGDETSTS0 (Bit 8) */
|
|
|
+ #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL) /*!< CHGDETSTS0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Pos (7UL) /*!< BATCHGE0 (Bit 7) */
|
|
|
+ #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Msk (0x80UL) /*!< BATCHGE0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Pos (5UL) /*!< VDMSRCE0 (Bit 5) */
|
|
|
+ #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Msk (0x20UL) /*!< VDMSRCE0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Pos (4UL) /*!< IDPSINKE0 (Bit 4) */
|
|
|
+ #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Msk (0x10UL) /*!< IDPSINKE0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Pos (3UL) /*!< VDPSRCE0 (Bit 3) */
|
|
|
+ #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Msk (0x8UL) /*!< VDPSRCE0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Pos (2UL) /*!< IDMSINKE0 (Bit 2) */
|
|
|
+ #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Msk (0x4UL) /*!< IDMSINKE0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Pos (1UL) /*!< IDPSRCE0 (Bit 1) */
|
|
|
+ #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Msk (0x2UL) /*!< IDPSRCE0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_USBBCCTRL0_RPDME0_Pos (0UL) /*!< RPDME0 (Bit 0) */
|
|
|
+ #define R_USB_FS0_USBBCCTRL0_RPDME0_Msk (0x1UL) /*!< RPDME0 (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== UCKSEL ========================================================= */
|
|
|
+ #define R_USB_FS0_UCKSEL_UCKSELC_Pos (0UL) /*!< UCKSELC (Bit 0) */
|
|
|
+ #define R_USB_FS0_UCKSEL_UCKSELC_Msk (0x1UL) /*!< UCKSELC (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= USBMC ========================================================= */
|
|
|
+ #define R_USB_FS0_USBMC_VDCEN_Pos (7UL) /*!< VDCEN (Bit 7) */
|
|
|
+ #define R_USB_FS0_USBMC_VDCEN_Msk (0x80UL) /*!< VDCEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_USBMC_VDDUSBE_Pos (0UL) /*!< VDDUSBE (Bit 0) */
|
|
|
+ #define R_USB_FS0_USBMC_VDDUSBE_Msk (0x1UL) /*!< VDDUSBE (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== PHYSLEW ======================================================== */
|
|
|
+ #define R_USB_FS0_PHYSLEW_SLEWF01_Pos (3UL) /*!< SLEWF01 (Bit 3) */
|
|
|
+ #define R_USB_FS0_PHYSLEW_SLEWF01_Msk (0x8UL) /*!< SLEWF01 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_PHYSLEW_SLEWF00_Pos (2UL) /*!< SLEWF00 (Bit 2) */
|
|
|
+ #define R_USB_FS0_PHYSLEW_SLEWF00_Msk (0x4UL) /*!< SLEWF00 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_PHYSLEW_SLEWR01_Pos (1UL) /*!< SLEWR01 (Bit 1) */
|
|
|
+ #define R_USB_FS0_PHYSLEW_SLEWR01_Msk (0x2UL) /*!< SLEWR01 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_PHYSLEW_SLEWR00_Pos (0UL) /*!< SLEWR00 (Bit 0) */
|
|
|
+ #define R_USB_FS0_PHYSLEW_SLEWR00_Msk (0x1UL) /*!< SLEWR00 (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== LPCTRL ========================================================= */
|
|
|
+ #define R_USB_FS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */
|
|
|
+ #define R_USB_FS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= LPSTS ========================================================= */
|
|
|
+ #define R_USB_FS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */
|
|
|
+ #define R_USB_FS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== BCCTRL ========================================================= */
|
|
|
+ #define R_USB_FS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */
|
|
|
+ #define R_USB_FS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */
|
|
|
+ #define R_USB_FS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */
|
|
|
+ #define R_USB_FS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */
|
|
|
+ #define R_USB_FS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */
|
|
|
+ #define R_USB_FS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */
|
|
|
+ #define R_USB_FS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */
|
|
|
+ #define R_USB_FS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */
|
|
|
+ #define R_USB_FS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= PL1CTRL1 ======================================================== */
|
|
|
+ #define R_USB_FS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */
|
|
|
+ #define R_USB_FS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */
|
|
|
+ #define R_USB_FS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_USB_FS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */
|
|
|
+ #define R_USB_FS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */
|
|
|
+ #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */
|
|
|
+ #define R_USB_FS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_USB_FS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */
|
|
|
+ #define R_USB_FS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= PL1CTRL2 ======================================================== */
|
|
|
+ #define R_USB_FS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */
|
|
|
+ #define R_USB_FS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */
|
|
|
+ #define R_USB_FS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */
|
|
|
+/* ======================================================= HL1CTRL1 ======================================================== */
|
|
|
+ #define R_USB_FS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */
|
|
|
+ #define R_USB_FS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_USB_FS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */
|
|
|
+ #define R_USB_FS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= HL1CTRL2 ======================================================== */
|
|
|
+ #define R_USB_FS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */
|
|
|
+ #define R_USB_FS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */
|
|
|
+ #define R_USB_FS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */
|
|
|
+ #define R_USB_FS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_USB_FS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */
|
|
|
+ #define R_USB_FS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */
|
|
|
+/* ======================================================== DPUSR0R ======================================================== */
|
|
|
+ #define R_USB_FS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */
|
|
|
+ #define R_USB_FS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */
|
|
|
+ #define R_USB_FS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */
|
|
|
+ #define R_USB_FS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== DPUSR1R ======================================================== */
|
|
|
+ #define R_USB_FS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */
|
|
|
+ #define R_USB_FS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */
|
|
|
+ #define R_USB_FS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */
|
|
|
+ #define R_USB_FS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */
|
|
|
+ #define R_USB_FS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */
|
|
|
+ #define R_USB_FS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */
|
|
|
+ #define R_USB_FS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== DPUSR2R ======================================================== */
|
|
|
+ #define R_USB_FS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */
|
|
|
+ #define R_USB_FS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */
|
|
|
+ #define R_USB_FS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */
|
|
|
+ #define R_USB_FS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */
|
|
|
+ #define R_USB_FS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */
|
|
|
+ #define R_USB_FS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */
|
|
|
+ #define R_USB_FS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== DPUSRCR ======================================================== */
|
|
|
+ #define R_USB_FS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */
|
|
|
+ #define R_USB_FS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */
|
|
|
+ #define R_USB_FS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */
|
|
|
+/* ====================================================== DPUSR0R_FS ======================================================= */
|
|
|
+ #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Pos (23UL) /*!< DVBSTS0 (Bit 23) */
|
|
|
+ #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Msk (0x800000UL) /*!< DVBSTS0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Pos (21UL) /*!< DOVCB0 (Bit 21) */
|
|
|
+ #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Msk (0x200000UL) /*!< DOVCB0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Pos (20UL) /*!< DOVCA0 (Bit 20) */
|
|
|
+ #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Msk (0x100000UL) /*!< DOVCA0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DPUSR0R_FS_DM0_Pos (17UL) /*!< DM0 (Bit 17) */
|
|
|
+ #define R_USB_FS0_DPUSR0R_FS_DM0_Msk (0x20000UL) /*!< DM0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DPUSR0R_FS_DP0_Pos (16UL) /*!< DP0 (Bit 16) */
|
|
|
+ #define R_USB_FS0_DPUSR0R_FS_DP0_Msk (0x10000UL) /*!< DP0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Pos (4UL) /*!< FIXPHY0 (Bit 4) */
|
|
|
+ #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Msk (0x10UL) /*!< FIXPHY0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DPUSR0R_FS_DRPD0_Pos (3UL) /*!< DRPD0 (Bit 3) */
|
|
|
+ #define R_USB_FS0_DPUSR0R_FS_DRPD0_Msk (0x8UL) /*!< DRPD0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DPUSR0R_FS_RPUE0_Pos (1UL) /*!< RPUE0 (Bit 1) */
|
|
|
+ #define R_USB_FS0_DPUSR0R_FS_RPUE0_Msk (0x2UL) /*!< RPUE0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DPUSR0R_FS_SRPC0_Pos (0UL) /*!< SRPC0 (Bit 0) */
|
|
|
+ #define R_USB_FS0_DPUSR0R_FS_SRPC0_Msk (0x1UL) /*!< SRPC0 (Bitfield-Mask: 0x01) */
|
|
|
+/* ====================================================== DPUSR1R_FS ======================================================= */
|
|
|
+ #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Pos (23UL) /*!< DVBINT0 (Bit 23) */
|
|
|
+ #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Msk (0x800000UL) /*!< DVBINT0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Pos (21UL) /*!< DOVRCRB0 (Bit 21) */
|
|
|
+ #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Msk (0x200000UL) /*!< DOVRCRB0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Pos (20UL) /*!< DOVRCRA0 (Bit 20) */
|
|
|
+ #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Msk (0x100000UL) /*!< DOVRCRA0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DPUSR1R_FS_DMINT0_Pos (17UL) /*!< DMINT0 (Bit 17) */
|
|
|
+ #define R_USB_FS0_DPUSR1R_FS_DMINT0_Msk (0x20000UL) /*!< DMINT0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DPUSR1R_FS_DPINT0_Pos (16UL) /*!< DPINT0 (Bit 16) */
|
|
|
+ #define R_USB_FS0_DPUSR1R_FS_DPINT0_Msk (0x10000UL) /*!< DPINT0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Pos (7UL) /*!< DVBSE0 (Bit 7) */
|
|
|
+ #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Msk (0x80UL) /*!< DVBSE0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Pos (5UL) /*!< DOVRCRBE0 (Bit 5) */
|
|
|
+ #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Msk (0x20UL) /*!< DOVRCRBE0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Pos (4UL) /*!< DOVRCRAE0 (Bit 4) */
|
|
|
+ #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Msk (0x10UL) /*!< DOVRCRAE0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Pos (1UL) /*!< DMINTE0 (Bit 1) */
|
|
|
+ #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Msk (0x2UL) /*!< DMINTE0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Pos (0UL) /*!< DPINTE0 (Bit 0) */
|
|
|
+ #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Msk (0x1UL) /*!< DPINTE0 (Bitfield-Mask: 0x01) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_WDT ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================= WDTRR ========================================================= */
|
|
|
+ #define R_WDT_WDTRR_WDTRR_Pos (0UL) /*!< WDTRR (Bit 0) */
|
|
|
+ #define R_WDT_WDTRR_WDTRR_Msk (0xffUL) /*!< WDTRR (Bitfield-Mask: 0xff) */
|
|
|
+/* ========================================================= WDTCR ========================================================= */
|
|
|
+ #define R_WDT_WDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */
|
|
|
+ #define R_WDT_WDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_WDT_WDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */
|
|
|
+ #define R_WDT_WDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_WDT_WDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */
|
|
|
+ #define R_WDT_WDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_WDT_WDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */
|
|
|
+ #define R_WDT_WDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */
|
|
|
+/* ========================================================= WDTSR ========================================================= */
|
|
|
+ #define R_WDT_WDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */
|
|
|
+ #define R_WDT_WDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_WDT_WDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */
|
|
|
+ #define R_WDT_WDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_WDT_WDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */
|
|
|
+ #define R_WDT_WDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */
|
|
|
+/* ======================================================== WDTRCR ========================================================= */
|
|
|
+ #define R_WDT_WDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */
|
|
|
+ #define R_WDT_WDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= WDTCSTPR ======================================================== */
|
|
|
+ #define R_WDT_WDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */
|
|
|
+ #define R_WDT_WDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_TZF ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ======================================================== TZFOAD ========================================================= */
|
|
|
+ #define R_TZF_TZFOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */
|
|
|
+ #define R_TZF_TZFOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_TZF_TZFOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */
|
|
|
+ #define R_TZF_TZFOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
|
|
|
+/* ========================================================= TZFPT ========================================================= */
|
|
|
+ #define R_TZF_TZFPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */
|
|
|
+ #define R_TZF_TZFPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_TZF_TZFPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */
|
|
|
+ #define R_TZF_TZFPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_CPSCU ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================= CSAR ========================================================== */
|
|
|
+ #define R_CPSCU_CSAR_CACHESA_Pos (0UL) /*!< CACHESA (Bit 0) */
|
|
|
+ #define R_CPSCU_CSAR_CACHESA_Msk (0x1UL) /*!< CACHESA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CPSCU_CSAR_CACHELSA_Pos (1UL) /*!< CACHELSA (Bit 1) */
|
|
|
+ #define R_CPSCU_CSAR_CACHELSA_Msk (0x2UL) /*!< CACHELSA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CPSCU_CSAR_CACHEESA_Pos (2UL) /*!< CACHEESA (Bit 2) */
|
|
|
+ #define R_CPSCU_CSAR_CACHEESA_Msk (0x4UL) /*!< CACHEESA (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== SRAMSAR ======================================================== */
|
|
|
+ #define R_CPSCU_SRAMSAR_SRAMSA0_Pos (0UL) /*!< SRAMSA0 (Bit 0) */
|
|
|
+ #define R_CPSCU_SRAMSAR_SRAMSA0_Msk (0x1UL) /*!< SRAMSA0 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CPSCU_SRAMSAR_SRAMSA1_Pos (1UL) /*!< SRAMSA1 (Bit 1) */
|
|
|
+ #define R_CPSCU_SRAMSAR_SRAMSA1_Msk (0x2UL) /*!< SRAMSA1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CPSCU_SRAMSAR_SRAMSA2_Pos (2UL) /*!< SRAMSA2 (Bit 2) */
|
|
|
+ #define R_CPSCU_SRAMSAR_SRAMSA2_Msk (0x4UL) /*!< SRAMSA2 (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= STBRAMSAR ======================================================= */
|
|
|
+ #define R_CPSCU_STBRAMSAR_NSBSTBR_Pos (0UL) /*!< NSBSTBR (Bit 0) */
|
|
|
+ #define R_CPSCU_STBRAMSAR_NSBSTBR_Msk (0xfUL) /*!< NSBSTBR (Bitfield-Mask: 0x0f) */
|
|
|
+/* ======================================================== DTCSAR ========================================================= */
|
|
|
+ #define R_CPSCU_DTCSAR_DTCSTSA_Pos (0UL) /*!< DTCSTSA (Bit 0) */
|
|
|
+ #define R_CPSCU_DTCSAR_DTCSTSA_Msk (0x1UL) /*!< DTCSTSA (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== DMACSAR ======================================================== */
|
|
|
+ #define R_CPSCU_DMACSAR_DMASTSA_Pos (0UL) /*!< DMASTSA (Bit 0) */
|
|
|
+ #define R_CPSCU_DMACSAR_DMASTSA_Msk (0x1UL) /*!< DMASTSA (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== ICUSARA ======================================================== */
|
|
|
+ #define R_CPSCU_ICUSARA_SAIRQCRn_Pos (0UL) /*!< SAIRQCRn (Bit 0) */
|
|
|
+ #define R_CPSCU_ICUSARA_SAIRQCRn_Msk (0xffffUL) /*!< SAIRQCRn (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================== ICUSARB ======================================================== */
|
|
|
+ #define R_CPSCU_ICUSARB_SANMI_Pos (0UL) /*!< SANMI (Bit 0) */
|
|
|
+ #define R_CPSCU_ICUSARB_SANMI_Msk (0x1UL) /*!< SANMI (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== ICUSARC ======================================================== */
|
|
|
+ #define R_CPSCU_ICUSARC_SADMACn_Pos (0UL) /*!< SADMACn (Bit 0) */
|
|
|
+ #define R_CPSCU_ICUSARC_SADMACn_Msk (0xffUL) /*!< SADMACn (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== ICUSARD ======================================================== */
|
|
|
+ #define R_CPSCU_ICUSARD_SASELSR0_Pos (0UL) /*!< SASELSR0 (Bit 0) */
|
|
|
+ #define R_CPSCU_ICUSARD_SASELSR0_Msk (0x1UL) /*!< SASELSR0 (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== ICUSARE ======================================================== */
|
|
|
+ #define R_CPSCU_ICUSARE_SAIWDTWUP_Pos (16UL) /*!< SAIWDTWUP (Bit 16) */
|
|
|
+ #define R_CPSCU_ICUSARE_SAIWDTWUP_Msk (0x10000UL) /*!< SAIWDTWUP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CPSCU_ICUSARE_SALVD1WUP_Pos (18UL) /*!< SALVD1WUP (Bit 18) */
|
|
|
+ #define R_CPSCU_ICUSARE_SALVD1WUP_Msk (0x40000UL) /*!< SALVD1WUP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CPSCU_ICUSARE_SALVD2WUP_Pos (19UL) /*!< SALVD2WUP (Bit 19) */
|
|
|
+ #define R_CPSCU_ICUSARE_SALVD2WUP_Msk (0x80000UL) /*!< SALVD2WUP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CPSCU_ICUSARE_SAVBATTWUP_Pos (20UL) /*!< SAVBATTWUP (Bit 20) */
|
|
|
+ #define R_CPSCU_ICUSARE_SAVBATTWUP_Msk (0x100000UL) /*!< SAVBATTWUP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos (24UL) /*!< SARTCALMWUP (Bit 24) */
|
|
|
+ #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk (0x1000000UL) /*!< SARTCALMWUP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos (25UL) /*!< SARTCPRDWUP (Bit 25) */
|
|
|
+ #define R_CPSCU_ICUSARE_SARTCPRDWUP_Msk (0x2000000UL) /*!< SARTCPRDWUP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Pos (27UL) /*!< SAUSBFS0WUP (Bit 27) */
|
|
|
+ #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Msk (0x8000000UL) /*!< SAUSBFS0WUP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Pos (28UL) /*!< SAAGT1UDWUP (Bit 28) */
|
|
|
+ #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Msk (0x10000000UL) /*!< SAAGT1UDWUP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Pos (29UL) /*!< SAAGT1CAWUP (Bit 29) */
|
|
|
+ #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Msk (0x20000000UL) /*!< SAAGT1CAWUP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Pos (30UL) /*!< SAAGT1CBWUP (Bit 30) */
|
|
|
+ #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Msk (0x40000000UL) /*!< SAAGT1CBWUP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CPSCU_ICUSARE_SAIIC0WUP_Pos (31UL) /*!< SAIIC0WUP (Bit 31) */
|
|
|
+ #define R_CPSCU_ICUSARE_SAIIC0WUP_Msk (0x80000000UL) /*!< SAIIC0WUP (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== ICUSARF ======================================================== */
|
|
|
+ #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Pos (0UL) /*!< SAAGT3UDWUP (Bit 0) */
|
|
|
+ #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Msk (0x1UL) /*!< SAAGT3UDWUP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Pos (1UL) /*!< SAAGT3CAWUP (Bit 1) */
|
|
|
+ #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Msk (0x2UL) /*!< SAAGT3CAWUP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Pos (2UL) /*!< SAAGT3CBWUP (Bit 2) */
|
|
|
+ #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk (0x4UL) /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Pos (3UL) /*!< SACOMPHS0WUP (Bit 3) */
|
|
|
+ #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Msk (0x8UL) /*!< SACOMPHS0WUP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CPSCU_ICUSARF_SAULP0UWUP_Pos (8UL) /*!< SAULP0UWUP (Bit 8) */
|
|
|
+ #define R_CPSCU_ICUSARF_SAULP0UWUP_Msk (0x100UL) /*!< SAULP0UWUP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CPSCU_ICUSARF_SAULP0AWUP_Pos (9UL) /*!< SAULP0AWUP (Bit 9) */
|
|
|
+ #define R_CPSCU_ICUSARF_SAULP0AWUP_Msk (0x200UL) /*!< SAULP0AWUP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CPSCU_ICUSARF_SAULP0BWUP_Pos (10UL) /*!< SAULP0BWUP (Bit 10) */
|
|
|
+ #define R_CPSCU_ICUSARF_SAULP0BWUP_Msk (0x400UL) /*!< SAULP0BWUP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CPSCU_ICUSARF_SAI3CWUP_Pos (11UL) /*!< SAI3CWUP (Bit 11) */
|
|
|
+ #define R_CPSCU_ICUSARF_SAI3CWUP_Msk (0x800UL) /*!< SAI3CWUP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CPSCU_ICUSARF_SAULP1UWUP_Pos (12UL) /*!< SAULP1UWUP (Bit 12) */
|
|
|
+ #define R_CPSCU_ICUSARF_SAULP1UWUP_Msk (0x1000UL) /*!< SAULP1UWUP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CPSCU_ICUSARF_SAULP1AWUP_Pos (13UL) /*!< SAULP1AWUP (Bit 13) */
|
|
|
+ #define R_CPSCU_ICUSARF_SAULP1AWUP_Msk (0x2000UL) /*!< SAULP1AWUP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CPSCU_ICUSARF_SAULP1BWUP_Pos (14UL) /*!< SAULP1BWUP (Bit 14) */
|
|
|
+ #define R_CPSCU_ICUSARF_SAULP1BWUP_Msk (0x4000UL) /*!< SAULP1BWUP (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== ICUSARG ======================================================== */
|
|
|
+ #define R_CPSCU_ICUSARG_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */
|
|
|
+ #define R_CPSCU_ICUSARG_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================== ICUSARH ======================================================== */
|
|
|
+ #define R_CPSCU_ICUSARH_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */
|
|
|
+ #define R_CPSCU_ICUSARH_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================== ICUSARI ======================================================== */
|
|
|
+ #define R_CPSCU_ICUSARI_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */
|
|
|
+ #define R_CPSCU_ICUSARI_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================== BUSSARA ======================================================== */
|
|
|
+ #define R_CPSCU_BUSSARA_BUSSA0_Pos (0UL) /*!< BUSSA0 (Bit 0) */
|
|
|
+ #define R_CPSCU_BUSSARA_BUSSA0_Msk (0x1UL) /*!< BUSSA0 (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== BUSSARB ======================================================== */
|
|
|
+ #define R_CPSCU_BUSSARB_BUSSB0_Pos (0UL) /*!< BUSSB0 (Bit 0) */
|
|
|
+ #define R_CPSCU_BUSSARB_BUSSB0_Msk (0x1UL) /*!< BUSSB0 (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= MMPUSARA ======================================================== */
|
|
|
+ #define R_CPSCU_MMPUSARA_MMPUAnSA_Pos (0UL) /*!< MMPUAnSA (Bit 0) */
|
|
|
+ #define R_CPSCU_MMPUSARA_MMPUAnSA_Msk (0xffUL) /*!< MMPUAnSA (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= MMPUSARB ======================================================== */
|
|
|
+ #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */
|
|
|
+ #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= DMACCHSAR ======================================================= */
|
|
|
+ #define R_CPSCU_DMACCHSAR_DMACCHSARn_Pos (0UL) /*!< DMACCHSARn (Bit 0) */
|
|
|
+ #define R_CPSCU_DMACCHSAR_DMACCHSARn_Msk (0xffUL) /*!< DMACCHSARn (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== CPUDSAR ======================================================== */
|
|
|
+ #define R_CPSCU_CPUDSAR_CPUDSA0_Pos (0UL) /*!< CPUDSA0 (Bit 0) */
|
|
|
+ #define R_CPSCU_CPUDSAR_CPUDSA0_Msk (0x1UL) /*!< CPUDSA0 (Bitfield-Mask: 0x01) */
|
|
|
+/* ====================================================== SRAMSABAR0 ======================================================= */
|
|
|
+ #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */
|
|
|
+ #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */
|
|
|
+/* ====================================================== SRAMSABAR1 ======================================================= */
|
|
|
+ #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Pos (13UL) /*!< SRAMSABAR (Bit 13) */
|
|
|
+ #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Msk (0x1fe000UL) /*!< SRAMSABAR (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== TEVTRCR ======================================================== */
|
|
|
+ #define R_CPSCU_TEVTRCR_TEVTE_Pos (0UL) /*!< TEVTE (Bit 0) */
|
|
|
+ #define R_CPSCU_TEVTRCR_TEVTE_Msk (0x1UL) /*!< TEVTE (Bitfield-Mask: 0x01) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_DOC_B ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================= DOCR ========================================================== */
|
|
|
+ #define R_DOC_B_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */
|
|
|
+ #define R_DOC_B_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_DOC_B_DOCR_DOBW_Pos (3UL) /*!< DOBW (Bit 3) */
|
|
|
+ #define R_DOC_B_DOCR_DOBW_Msk (0x8UL) /*!< DOBW (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_DOC_B_DOCR_DCSEL_Pos (4UL) /*!< DCSEL (Bit 4) */
|
|
|
+ #define R_DOC_B_DOCR_DCSEL_Msk (0x70UL) /*!< DCSEL (Bitfield-Mask: 0x07) */
|
|
|
+/* ========================================================= DOSR ========================================================== */
|
|
|
+ #define R_DOC_B_DOSR_DOPCF_Pos (0UL) /*!< DOPCF (Bit 0) */
|
|
|
+ #define R_DOC_B_DOSR_DOPCF_Msk (0x1UL) /*!< DOPCF (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= DOSCR ========================================================= */
|
|
|
+ #define R_DOC_B_DOSCR_DOPCFCL_Pos (0UL) /*!< DOPCFCL (Bit 0) */
|
|
|
+ #define R_DOC_B_DOSCR_DOPCFCL_Msk (0x1UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= DODIR ========================================================= */
|
|
|
+/* ======================================================== DODSR0 ========================================================= */
|
|
|
+/* ======================================================== DODSR1 ========================================================= */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_SCI_B0 ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================== RDR ========================================================== */
|
|
|
+ #define R_SCI_B0_RDR_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */
|
|
|
+ #define R_SCI_B0_RDR_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */
|
|
|
+ #define R_SCI_B0_RDR_MPB_Pos (9UL) /*!< MPB (Bit 9) */
|
|
|
+ #define R_SCI_B0_RDR_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_RDR_DR_Pos (10UL) /*!< DR (Bit 10) */
|
|
|
+ #define R_SCI_B0_RDR_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_RDR_FPER_Pos (11UL) /*!< FPER (Bit 11) */
|
|
|
+ #define R_SCI_B0_RDR_FPER_Msk (0x800UL) /*!< FPER (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_RDR_FFER_Pos (12UL) /*!< FFER (Bit 12) */
|
|
|
+ #define R_SCI_B0_RDR_FFER_Msk (0x1000UL) /*!< FFER (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_RDR_ORER_Pos (24UL) /*!< ORER (Bit 24) */
|
|
|
+ #define R_SCI_B0_RDR_ORER_Msk (0x1000000UL) /*!< ORER (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_RDR_PER_Pos (27UL) /*!< PER (Bit 27) */
|
|
|
+ #define R_SCI_B0_RDR_PER_Msk (0x8000000UL) /*!< PER (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_RDR_FER_Pos (28UL) /*!< FER (Bit 28) */
|
|
|
+ #define R_SCI_B0_RDR_FER_Msk (0x10000000UL) /*!< FER (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== RDR_BY ========================================================= */
|
|
|
+ #define R_SCI_B0_RDR_BY_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */
|
|
|
+ #define R_SCI_B0_RDR_BY_RDAT_Msk (0xffUL) /*!< RDAT (Bitfield-Mask: 0xff) */
|
|
|
+/* ========================================================== TDR ========================================================== */
|
|
|
+ #define R_SCI_B0_TDR_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */
|
|
|
+ #define R_SCI_B0_TDR_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */
|
|
|
+ #define R_SCI_B0_TDR_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */
|
|
|
+ #define R_SCI_B0_TDR_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_TDR_TSYNC_Pos (12UL) /*!< TSYNC (Bit 12) */
|
|
|
+ #define R_SCI_B0_TDR_TSYNC_Msk (0x1000UL) /*!< TSYNC (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== TDR_BY ========================================================= */
|
|
|
+ #define R_SCI_B0_TDR_BY_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */
|
|
|
+ #define R_SCI_B0_TDR_BY_TDAT_Msk (0xffUL) /*!< TDAT (Bitfield-Mask: 0xff) */
|
|
|
+/* ========================================================= CCR0 ========================================================== */
|
|
|
+ #define R_SCI_B0_CCR0_RE_Pos (0UL) /*!< RE (Bit 0) */
|
|
|
+ #define R_SCI_B0_CCR0_RE_Msk (0x1UL) /*!< RE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CCR0_TE_Pos (4UL) /*!< TE (Bit 4) */
|
|
|
+ #define R_SCI_B0_CCR0_TE_Msk (0x10UL) /*!< TE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CCR0_MPIE_Pos (8UL) /*!< MPIE (Bit 8) */
|
|
|
+ #define R_SCI_B0_CCR0_MPIE_Msk (0x100UL) /*!< MPIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CCR0_DCME_Pos (9UL) /*!< DCME (Bit 9) */
|
|
|
+ #define R_SCI_B0_CCR0_DCME_Msk (0x200UL) /*!< DCME (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CCR0_IDSEL_Pos (10UL) /*!< IDSEL (Bit 10) */
|
|
|
+ #define R_SCI_B0_CCR0_IDSEL_Msk (0x400UL) /*!< IDSEL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CCR0_RIE_Pos (16UL) /*!< RIE (Bit 16) */
|
|
|
+ #define R_SCI_B0_CCR0_RIE_Msk (0x10000UL) /*!< RIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CCR0_TIE_Pos (20UL) /*!< TIE (Bit 20) */
|
|
|
+ #define R_SCI_B0_CCR0_TIE_Msk (0x100000UL) /*!< TIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CCR0_TEIE_Pos (21UL) /*!< TEIE (Bit 21) */
|
|
|
+ #define R_SCI_B0_CCR0_TEIE_Msk (0x200000UL) /*!< TEIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CCR0_SSE_Pos (24UL) /*!< SSE (Bit 24) */
|
|
|
+ #define R_SCI_B0_CCR0_SSE_Msk (0x1000000UL) /*!< SSE (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= CCR1 ========================================================== */
|
|
|
+ #define R_SCI_B0_CCR1_CTSE_Pos (0UL) /*!< CTSE (Bit 0) */
|
|
|
+ #define R_SCI_B0_CCR1_CTSE_Msk (0x1UL) /*!< CTSE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CCR1_CTSPEN_Pos (1UL) /*!< CTSPEN (Bit 1) */
|
|
|
+ #define R_SCI_B0_CCR1_CTSPEN_Msk (0x2UL) /*!< CTSPEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CCR1_SPB2DT_Pos (4UL) /*!< SPB2DT (Bit 4) */
|
|
|
+ #define R_SCI_B0_CCR1_SPB2DT_Msk (0x10UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CCR1_SPB2IO_Pos (5UL) /*!< SPB2IO (Bit 5) */
|
|
|
+ #define R_SCI_B0_CCR1_SPB2IO_Msk (0x20UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CCR1_PE_Pos (8UL) /*!< PE (Bit 8) */
|
|
|
+ #define R_SCI_B0_CCR1_PE_Msk (0x100UL) /*!< PE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CCR1_PM_Pos (9UL) /*!< PM (Bit 9) */
|
|
|
+ #define R_SCI_B0_CCR1_PM_Msk (0x200UL) /*!< PM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CCR1_TINV_Pos (12UL) /*!< TINV (Bit 12) */
|
|
|
+ #define R_SCI_B0_CCR1_TINV_Msk (0x1000UL) /*!< TINV (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CCR1_RINV_Pos (13UL) /*!< RINV (Bit 13) */
|
|
|
+ #define R_SCI_B0_CCR1_RINV_Msk (0x2000UL) /*!< RINV (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CCR1_SPLP_Pos (16UL) /*!< SPLP (Bit 16) */
|
|
|
+ #define R_SCI_B0_CCR1_SPLP_Msk (0x10000UL) /*!< SPLP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CCR1_SHARPS_Pos (20UL) /*!< SHARPS (Bit 20) */
|
|
|
+ #define R_SCI_B0_CCR1_SHARPS_Msk (0x100000UL) /*!< SHARPS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CCR1_NFCS_Pos (24UL) /*!< NFCS (Bit 24) */
|
|
|
+ #define R_SCI_B0_CCR1_NFCS_Msk (0x7000000UL) /*!< NFCS (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_SCI_B0_CCR1_NFEN_Pos (28UL) /*!< NFEN (Bit 28) */
|
|
|
+ #define R_SCI_B0_CCR1_NFEN_Msk (0x10000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= CCR2 ========================================================== */
|
|
|
+ #define R_SCI_B0_CCR2_BCP_Pos (0UL) /*!< BCP (Bit 0) */
|
|
|
+ #define R_SCI_B0_CCR2_BCP_Msk (0x7UL) /*!< BCP (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_SCI_B0_CCR2_BGDM_Pos (4UL) /*!< BGDM (Bit 4) */
|
|
|
+ #define R_SCI_B0_CCR2_BGDM_Msk (0x10UL) /*!< BGDM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CCR2_ABCS_Pos (5UL) /*!< ABCS (Bit 5) */
|
|
|
+ #define R_SCI_B0_CCR2_ABCS_Msk (0x20UL) /*!< ABCS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CCR2_ABCSE_Pos (6UL) /*!< ABCSE (Bit 6) */
|
|
|
+ #define R_SCI_B0_CCR2_ABCSE_Msk (0x40UL) /*!< ABCSE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CCR2_BRR_Pos (8UL) /*!< BRR (Bit 8) */
|
|
|
+ #define R_SCI_B0_CCR2_BRR_Msk (0xff00UL) /*!< BRR (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_SCI_B0_CCR2_BRME_Pos (16UL) /*!< BRME (Bit 16) */
|
|
|
+ #define R_SCI_B0_CCR2_BRME_Msk (0x10000UL) /*!< BRME (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CCR2_CKS_Pos (20UL) /*!< CKS (Bit 20) */
|
|
|
+ #define R_SCI_B0_CCR2_CKS_Msk (0x300000UL) /*!< CKS (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_SCI_B0_CCR2_MDDR_Pos (24UL) /*!< MDDR (Bit 24) */
|
|
|
+ #define R_SCI_B0_CCR2_MDDR_Msk (0xff000000UL) /*!< MDDR (Bitfield-Mask: 0xff) */
|
|
|
+/* ========================================================= CCR3 ========================================================== */
|
|
|
+ #define R_SCI_B0_CCR3_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */
|
|
|
+ #define R_SCI_B0_CCR3_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CCR3_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */
|
|
|
+ #define R_SCI_B0_CCR3_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CCR3_BPEN_Pos (7UL) /*!< BPEN (Bit 7) */
|
|
|
+ #define R_SCI_B0_CCR3_BPEN_Msk (0x80UL) /*!< BPEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CCR3_CHR_Pos (8UL) /*!< CHR (Bit 8) */
|
|
|
+ #define R_SCI_B0_CCR3_CHR_Msk (0x300UL) /*!< CHR (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_SCI_B0_CCR3_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */
|
|
|
+ #define R_SCI_B0_CCR3_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CCR3_SINV_Pos (13UL) /*!< SINV (Bit 13) */
|
|
|
+ #define R_SCI_B0_CCR3_SINV_Msk (0x2000UL) /*!< SINV (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CCR3_STP_Pos (14UL) /*!< STP (Bit 14) */
|
|
|
+ #define R_SCI_B0_CCR3_STP_Msk (0x4000UL) /*!< STP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CCR3_RXDESEL_Pos (15UL) /*!< RXDESEL (Bit 15) */
|
|
|
+ #define R_SCI_B0_CCR3_RXDESEL_Msk (0x8000UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CCR3_MOD_Pos (16UL) /*!< MOD (Bit 16) */
|
|
|
+ #define R_SCI_B0_CCR3_MOD_Msk (0x70000UL) /*!< MOD (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_SCI_B0_CCR3_MP_Pos (19UL) /*!< MP (Bit 19) */
|
|
|
+ #define R_SCI_B0_CCR3_MP_Msk (0x80000UL) /*!< MP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CCR3_FM_Pos (20UL) /*!< FM (Bit 20) */
|
|
|
+ #define R_SCI_B0_CCR3_FM_Msk (0x100000UL) /*!< FM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CCR3_DEN_Pos (21UL) /*!< DEN (Bit 21) */
|
|
|
+ #define R_SCI_B0_CCR3_DEN_Msk (0x200000UL) /*!< DEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CCR3_CKE_Pos (24UL) /*!< CKE (Bit 24) */
|
|
|
+ #define R_SCI_B0_CCR3_CKE_Msk (0x3000000UL) /*!< CKE (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_SCI_B0_CCR3_GM_Pos (28UL) /*!< GM (Bit 28) */
|
|
|
+ #define R_SCI_B0_CCR3_GM_Msk (0x10000000UL) /*!< GM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CCR3_BLK_Pos (29UL) /*!< BLK (Bit 29) */
|
|
|
+ #define R_SCI_B0_CCR3_BLK_Msk (0x20000000UL) /*!< BLK (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= CCR4 ========================================================== */
|
|
|
+ #define R_SCI_B0_CCR4_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */
|
|
|
+ #define R_SCI_B0_CCR4_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */
|
|
|
+ #define R_SCI_B0_CCR4_ASEN_Pos (16UL) /*!< ASEN (Bit 16) */
|
|
|
+ #define R_SCI_B0_CCR4_ASEN_Msk (0x10000UL) /*!< ASEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CCR4_ATEN_Pos (17UL) /*!< ATEN (Bit 17) */
|
|
|
+ #define R_SCI_B0_CCR4_ATEN_Msk (0x20000UL) /*!< ATEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CCR4_SCKSEL_Pos (19UL) /*!< SCKSEL (Bit 19) */
|
|
|
+ #define R_SCI_B0_CCR4_SCKSEL_Msk (0x80000UL) /*!< SCKSEL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CCR4_AST_Pos (24UL) /*!< AST (Bit 24) */
|
|
|
+ #define R_SCI_B0_CCR4_AST_Msk (0x7000000UL) /*!< AST (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_SCI_B0_CCR4_AJD_Pos (27UL) /*!< AJD (Bit 27) */
|
|
|
+ #define R_SCI_B0_CCR4_AJD_Msk (0x8000000UL) /*!< AJD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CCR4_ATT_Pos (28UL) /*!< ATT (Bit 28) */
|
|
|
+ #define R_SCI_B0_CCR4_ATT_Msk (0x70000000UL) /*!< ATT (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_SCI_B0_CCR4_AET_Pos (31UL) /*!< AET (Bit 31) */
|
|
|
+ #define R_SCI_B0_CCR4_AET_Msk (0x80000000UL) /*!< AET (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= CESR ========================================================== */
|
|
|
+ #define R_SCI_B0_CESR_RIST_Pos (0UL) /*!< RIST (Bit 0) */
|
|
|
+ #define R_SCI_B0_CESR_RIST_Msk (0x1UL) /*!< RIST (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CESR_TIST_Pos (4UL) /*!< TIST (Bit 4) */
|
|
|
+ #define R_SCI_B0_CESR_TIST_Msk (0x10UL) /*!< TIST (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================== ICR ========================================================== */
|
|
|
+ #define R_SCI_B0_ICR_IICDL_Pos (0UL) /*!< IICDL (Bit 0) */
|
|
|
+ #define R_SCI_B0_ICR_IICDL_Msk (0x1fUL) /*!< IICDL (Bitfield-Mask: 0x1f) */
|
|
|
+ #define R_SCI_B0_ICR_IICINTM_Pos (8UL) /*!< IICINTM (Bit 8) */
|
|
|
+ #define R_SCI_B0_ICR_IICINTM_Msk (0x100UL) /*!< IICINTM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_ICR_IICCSC_Pos (9UL) /*!< IICCSC (Bit 9) */
|
|
|
+ #define R_SCI_B0_ICR_IICCSC_Msk (0x200UL) /*!< IICCSC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_ICR_IICACKT_Pos (13UL) /*!< IICACKT (Bit 13) */
|
|
|
+ #define R_SCI_B0_ICR_IICACKT_Msk (0x2000UL) /*!< IICACKT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_ICR_IICSTAREQ_Pos (16UL) /*!< IICSTAREQ (Bit 16) */
|
|
|
+ #define R_SCI_B0_ICR_IICSTAREQ_Msk (0x10000UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_ICR_IICRSTAREQ_Pos (17UL) /*!< IICRSTAREQ (Bit 17) */
|
|
|
+ #define R_SCI_B0_ICR_IICRSTAREQ_Msk (0x20000UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_ICR_IICSTPREQ_Pos (18UL) /*!< IICSTPREQ (Bit 18) */
|
|
|
+ #define R_SCI_B0_ICR_IICSTPREQ_Msk (0x40000UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_ICR_IICSDAS_Pos (20UL) /*!< IICSDAS (Bit 20) */
|
|
|
+ #define R_SCI_B0_ICR_IICSDAS_Msk (0x300000UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_SCI_B0_ICR_IICSCLS_Pos (22UL) /*!< IICSCLS (Bit 22) */
|
|
|
+ #define R_SCI_B0_ICR_IICSCLS_Msk (0xc00000UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */
|
|
|
+/* ========================================================== FCR ========================================================== */
|
|
|
+ #define R_SCI_B0_FCR_DRES_Pos (0UL) /*!< DRES (Bit 0) */
|
|
|
+ #define R_SCI_B0_FCR_DRES_Msk (0x1UL) /*!< DRES (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_FCR_TTRG_Pos (8UL) /*!< TTRG (Bit 8) */
|
|
|
+ #define R_SCI_B0_FCR_TTRG_Msk (0x1f00UL) /*!< TTRG (Bitfield-Mask: 0x1f) */
|
|
|
+ #define R_SCI_B0_FCR_TFRST_Pos (15UL) /*!< TFRST (Bit 15) */
|
|
|
+ #define R_SCI_B0_FCR_TFRST_Msk (0x8000UL) /*!< TFRST (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_FCR_RTRG_Pos (16UL) /*!< RTRG (Bit 16) */
|
|
|
+ #define R_SCI_B0_FCR_RTRG_Msk (0x1f0000UL) /*!< RTRG (Bitfield-Mask: 0x1f) */
|
|
|
+ #define R_SCI_B0_FCR_RFRST_Pos (23UL) /*!< RFRST (Bit 23) */
|
|
|
+ #define R_SCI_B0_FCR_RFRST_Msk (0x800000UL) /*!< RFRST (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_FCR_RSTRG_Pos (24UL) /*!< RSTRG (Bit 24) */
|
|
|
+ #define R_SCI_B0_FCR_RSTRG_Msk (0x1f000000UL) /*!< RSTRG (Bitfield-Mask: 0x1f) */
|
|
|
+/* ========================================================== MCR ========================================================== */
|
|
|
+ #define R_SCI_B0_MCR_RMPOL_Pos (0UL) /*!< RMPOL (Bit 0) */
|
|
|
+ #define R_SCI_B0_MCR_RMPOL_Msk (0x1UL) /*!< RMPOL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_MCR_TMPOL_Pos (1UL) /*!< TMPOL (Bit 1) */
|
|
|
+ #define R_SCI_B0_MCR_TMPOL_Msk (0x2UL) /*!< TMPOL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_MCR_ERTEN_Pos (2UL) /*!< ERTEN (Bit 2) */
|
|
|
+ #define R_SCI_B0_MCR_ERTEN_Msk (0x4UL) /*!< ERTEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_MCR_SYNVAL_Pos (4UL) /*!< SYNVAL (Bit 4) */
|
|
|
+ #define R_SCI_B0_MCR_SYNVAL_Msk (0x10UL) /*!< SYNVAL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_MCR_SYNSEL_Pos (5UL) /*!< SYNSEL (Bit 5) */
|
|
|
+ #define R_SCI_B0_MCR_SYNSEL_Msk (0x20UL) /*!< SYNSEL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_MCR_SBSEL_Pos (6UL) /*!< SBSEL (Bit 6) */
|
|
|
+ #define R_SCI_B0_MCR_SBSEL_Msk (0x40UL) /*!< SBSEL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_MCR_TPLEN_Pos (8UL) /*!< TPLEN (Bit 8) */
|
|
|
+ #define R_SCI_B0_MCR_TPLEN_Msk (0xf00UL) /*!< TPLEN (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_SCI_B0_MCR_TPPAT_Pos (12UL) /*!< TPPAT (Bit 12) */
|
|
|
+ #define R_SCI_B0_MCR_TPPAT_Msk (0x3000UL) /*!< TPPAT (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_SCI_B0_MCR_RPLEN_Pos (16UL) /*!< RPLEN (Bit 16) */
|
|
|
+ #define R_SCI_B0_MCR_RPLEN_Msk (0xf0000UL) /*!< RPLEN (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_SCI_B0_MCR_RPPAT_Pos (20UL) /*!< RPPAT (Bit 20) */
|
|
|
+ #define R_SCI_B0_MCR_RPPAT_Msk (0x300000UL) /*!< RPPAT (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_SCI_B0_MCR_PFEREN_Pos (24UL) /*!< PFEREN (Bit 24) */
|
|
|
+ #define R_SCI_B0_MCR_PFEREN_Msk (0x1000000UL) /*!< PFEREN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_MCR_SYEREN_Pos (25UL) /*!< SYEREN (Bit 25) */
|
|
|
+ #define R_SCI_B0_MCR_SYEREN_Msk (0x2000000UL) /*!< SYEREN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_MCR_SBEREN_Pos (26UL) /*!< SBEREN (Bit 26) */
|
|
|
+ #define R_SCI_B0_MCR_SBEREN_Msk (0x4000000UL) /*!< SBEREN (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================== DCR ========================================================== */
|
|
|
+ #define R_SCI_B0_DCR_DEPOL_Pos (0UL) /*!< DEPOL (Bit 0) */
|
|
|
+ #define R_SCI_B0_DCR_DEPOL_Msk (0x1UL) /*!< DEPOL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_DCR_DEAST_Pos (8UL) /*!< DEAST (Bit 8) */
|
|
|
+ #define R_SCI_B0_DCR_DEAST_Msk (0x1f00UL) /*!< DEAST (Bitfield-Mask: 0x1f) */
|
|
|
+ #define R_SCI_B0_DCR_DENGT_Pos (16UL) /*!< DENGT (Bit 16) */
|
|
|
+ #define R_SCI_B0_DCR_DENGT_Msk (0x1f0000UL) /*!< DENGT (Bitfield-Mask: 0x1f) */
|
|
|
+/* ========================================================= XCR0 ========================================================== */
|
|
|
+ #define R_SCI_B0_XCR0_TCSS_Pos (0UL) /*!< TCSS (Bit 0) */
|
|
|
+ #define R_SCI_B0_XCR0_TCSS_Msk (0x3UL) /*!< TCSS (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_SCI_B0_XCR0_BFE_Pos (8UL) /*!< BFE (Bit 8) */
|
|
|
+ #define R_SCI_B0_XCR0_BFE_Msk (0x100UL) /*!< BFE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_XCR0_CF0RE_Pos (9UL) /*!< CF0RE (Bit 9) */
|
|
|
+ #define R_SCI_B0_XCR0_CF0RE_Msk (0x200UL) /*!< CF0RE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_XCR0_CF1DS_Pos (10UL) /*!< CF1DS (Bit 10) */
|
|
|
+ #define R_SCI_B0_XCR0_CF1DS_Msk (0xc00UL) /*!< CF1DS (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_SCI_B0_XCR0_PIBE_Pos (12UL) /*!< PIBE (Bit 12) */
|
|
|
+ #define R_SCI_B0_XCR0_PIBE_Msk (0x1000UL) /*!< PIBE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_XCR0_PIBS_Pos (13UL) /*!< PIBS (Bit 13) */
|
|
|
+ #define R_SCI_B0_XCR0_PIBS_Msk (0xe000UL) /*!< PIBS (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_SCI_B0_XCR0_BFOIE_Pos (16UL) /*!< BFOIE (Bit 16) */
|
|
|
+ #define R_SCI_B0_XCR0_BFOIE_Msk (0x10000UL) /*!< BFOIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_XCR0_BCDIE_Pos (17UL) /*!< BCDIE (Bit 17) */
|
|
|
+ #define R_SCI_B0_XCR0_BCDIE_Msk (0x20000UL) /*!< BCDIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_XCR0_BFDIE_Pos (20UL) /*!< BFDIE (Bit 20) */
|
|
|
+ #define R_SCI_B0_XCR0_BFDIE_Msk (0x100000UL) /*!< BFDIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_XCR0_COFIE_Pos (21UL) /*!< COFIE (Bit 21) */
|
|
|
+ #define R_SCI_B0_XCR0_COFIE_Msk (0x200000UL) /*!< COFIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_XCR0_AEDIE_Pos (22UL) /*!< AEDIE (Bit 22) */
|
|
|
+ #define R_SCI_B0_XCR0_AEDIE_Msk (0x400000UL) /*!< AEDIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_XCR0_BCCS_Pos (24UL) /*!< BCCS (Bit 24) */
|
|
|
+ #define R_SCI_B0_XCR0_BCCS_Msk (0x3000000UL) /*!< BCCS (Bitfield-Mask: 0x03) */
|
|
|
+/* ========================================================= XCR1 ========================================================== */
|
|
|
+ #define R_SCI_B0_XCR1_TCST_Pos (0UL) /*!< TCST (Bit 0) */
|
|
|
+ #define R_SCI_B0_XCR1_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_XCR1_SDST_Pos (4UL) /*!< SDST (Bit 4) */
|
|
|
+ #define R_SCI_B0_XCR1_SDST_Msk (0x10UL) /*!< SDST (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_XCR1_BMEN_Pos (5UL) /*!< BMEN (Bit 5) */
|
|
|
+ #define R_SCI_B0_XCR1_BMEN_Msk (0x20UL) /*!< BMEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_XCR1_PCF1D_Pos (8UL) /*!< PCF1D (Bit 8) */
|
|
|
+ #define R_SCI_B0_XCR1_PCF1D_Msk (0xff00UL) /*!< PCF1D (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_SCI_B0_XCR1_SCF1D_Pos (16UL) /*!< SCF1D (Bit 16) */
|
|
|
+ #define R_SCI_B0_XCR1_SCF1D_Msk (0xff0000UL) /*!< SCF1D (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_SCI_B0_XCR1_CF1CE_Pos (24UL) /*!< CF1CE (Bit 24) */
|
|
|
+ #define R_SCI_B0_XCR1_CF1CE_Msk (0xff000000UL) /*!< CF1CE (Bitfield-Mask: 0xff) */
|
|
|
+/* ========================================================= XCR2 ========================================================== */
|
|
|
+ #define R_SCI_B0_XCR2_CF0D_Pos (0UL) /*!< CF0D (Bit 0) */
|
|
|
+ #define R_SCI_B0_XCR2_CF0D_Msk (0xffUL) /*!< CF0D (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_SCI_B0_XCR2_CF0CE_Pos (8UL) /*!< CF0CE (Bit 8) */
|
|
|
+ #define R_SCI_B0_XCR2_CF0CE_Msk (0xff00UL) /*!< CF0CE (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_SCI_B0_XCR2_BFLW_Pos (16UL) /*!< BFLW (Bit 16) */
|
|
|
+ #define R_SCI_B0_XCR2_BFLW_Msk (0xffff0000UL) /*!< BFLW (Bitfield-Mask: 0xffff) */
|
|
|
+/* ========================================================== CSR ========================================================== */
|
|
|
+ #define R_SCI_B0_CSR_ERS_Pos (4UL) /*!< ERS (Bit 4) */
|
|
|
+ #define R_SCI_B0_CSR_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CSR_RXDMON_Pos (15UL) /*!< RXDMON (Bit 15) */
|
|
|
+ #define R_SCI_B0_CSR_RXDMON_Msk (0x8000UL) /*!< RXDMON (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CSR_DCMF_Pos (16UL) /*!< DCMF (Bit 16) */
|
|
|
+ #define R_SCI_B0_CSR_DCMF_Msk (0x10000UL) /*!< DCMF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CSR_DPER_Pos (17UL) /*!< DPER (Bit 17) */
|
|
|
+ #define R_SCI_B0_CSR_DPER_Msk (0x20000UL) /*!< DPER (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CSR_DFER_Pos (18UL) /*!< DFER (Bit 18) */
|
|
|
+ #define R_SCI_B0_CSR_DFER_Msk (0x40000UL) /*!< DFER (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CSR_ORER_Pos (24UL) /*!< ORER (Bit 24) */
|
|
|
+ #define R_SCI_B0_CSR_ORER_Msk (0x1000000UL) /*!< ORER (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CSR_MFF_Pos (26UL) /*!< MFF (Bit 26) */
|
|
|
+ #define R_SCI_B0_CSR_MFF_Msk (0x4000000UL) /*!< MFF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CSR_PER_Pos (27UL) /*!< PER (Bit 27) */
|
|
|
+ #define R_SCI_B0_CSR_PER_Msk (0x8000000UL) /*!< PER (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CSR_FER_Pos (28UL) /*!< FER (Bit 28) */
|
|
|
+ #define R_SCI_B0_CSR_FER_Msk (0x10000000UL) /*!< FER (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CSR_TDRE_Pos (29UL) /*!< TDRE (Bit 29) */
|
|
|
+ #define R_SCI_B0_CSR_TDRE_Msk (0x20000000UL) /*!< TDRE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CSR_TEND_Pos (30UL) /*!< TEND (Bit 30) */
|
|
|
+ #define R_SCI_B0_CSR_TEND_Msk (0x40000000UL) /*!< TEND (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CSR_RDRF_Pos (31UL) /*!< RDRF (Bit 31) */
|
|
|
+ #define R_SCI_B0_CSR_RDRF_Msk (0x80000000UL) /*!< RDRF (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================== ISR ========================================================== */
|
|
|
+ #define R_SCI_B0_ISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */
|
|
|
+ #define R_SCI_B0_ISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_ISR_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */
|
|
|
+ #define R_SCI_B0_ISR_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= FRSR ========================================================== */
|
|
|
+ #define R_SCI_B0_FRSR_DR_Pos (0UL) /*!< DR (Bit 0) */
|
|
|
+ #define R_SCI_B0_FRSR_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_FRSR_R_Pos (8UL) /*!< R (Bit 8) */
|
|
|
+ #define R_SCI_B0_FRSR_R_Msk (0x3f00UL) /*!< R (Bitfield-Mask: 0x3f) */
|
|
|
+ #define R_SCI_B0_FRSR_PNUM_Pos (16UL) /*!< PNUM (Bit 16) */
|
|
|
+ #define R_SCI_B0_FRSR_PNUM_Msk (0x3f0000UL) /*!< PNUM (Bitfield-Mask: 0x3f) */
|
|
|
+ #define R_SCI_B0_FRSR_FNUM_Pos (24UL) /*!< FNUM (Bit 24) */
|
|
|
+ #define R_SCI_B0_FRSR_FNUM_Msk (0x3f000000UL) /*!< FNUM (Bitfield-Mask: 0x3f) */
|
|
|
+/* ========================================================= FTSR ========================================================== */
|
|
|
+ #define R_SCI_B0_FTSR_T_Pos (0UL) /*!< T (Bit 0) */
|
|
|
+ #define R_SCI_B0_FTSR_T_Msk (0x3fUL) /*!< T (Bitfield-Mask: 0x3f) */
|
|
|
+/* ========================================================== MSR ========================================================== */
|
|
|
+ #define R_SCI_B0_MSR_PFER_Pos (0UL) /*!< PFER (Bit 0) */
|
|
|
+ #define R_SCI_B0_MSR_PFER_Msk (0x1UL) /*!< PFER (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_MSR_SYER_Pos (1UL) /*!< SYER (Bit 1) */
|
|
|
+ #define R_SCI_B0_MSR_SYER_Msk (0x2UL) /*!< SYER (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_MSR_SBER_Pos (2UL) /*!< SBER (Bit 2) */
|
|
|
+ #define R_SCI_B0_MSR_SBER_Msk (0x4UL) /*!< SBER (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_MSR_MER_Pos (4UL) /*!< MER (Bit 4) */
|
|
|
+ #define R_SCI_B0_MSR_MER_Msk (0x10UL) /*!< MER (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_MSR_RSYNC_Pos (6UL) /*!< RSYNC (Bit 6) */
|
|
|
+ #define R_SCI_B0_MSR_RSYNC_Msk (0x40UL) /*!< RSYNC (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= XSR0 ========================================================== */
|
|
|
+ #define R_SCI_B0_XSR0_SFSF_Pos (0UL) /*!< SFSF (Bit 0) */
|
|
|
+ #define R_SCI_B0_XSR0_SFSF_Msk (0x1UL) /*!< SFSF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_XSR0_RXDSF_Pos (1UL) /*!< RXDSF (Bit 1) */
|
|
|
+ #define R_SCI_B0_XSR0_RXDSF_Msk (0x2UL) /*!< RXDSF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_XSR0_BFOF_Pos (8UL) /*!< BFOF (Bit 8) */
|
|
|
+ #define R_SCI_B0_XSR0_BFOF_Msk (0x100UL) /*!< BFOF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_XSR0_BCDF_Pos (9UL) /*!< BCDF (Bit 9) */
|
|
|
+ #define R_SCI_B0_XSR0_BCDF_Msk (0x200UL) /*!< BCDF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_XSR0_BFDF_Pos (10UL) /*!< BFDF (Bit 10) */
|
|
|
+ #define R_SCI_B0_XSR0_BFDF_Msk (0x400UL) /*!< BFDF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_XSR0_CF0MF_Pos (11UL) /*!< CF0MF (Bit 11) */
|
|
|
+ #define R_SCI_B0_XSR0_CF0MF_Msk (0x800UL) /*!< CF0MF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_XSR0_CF1MF_Pos (12UL) /*!< CF1MF (Bit 12) */
|
|
|
+ #define R_SCI_B0_XSR0_CF1MF_Msk (0x1000UL) /*!< CF1MF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_XSR0_PIBDF_Pos (13UL) /*!< PIBDF (Bit 13) */
|
|
|
+ #define R_SCI_B0_XSR0_PIBDF_Msk (0x2000UL) /*!< PIBDF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_XSR0_COF_Pos (14UL) /*!< COF (Bit 14) */
|
|
|
+ #define R_SCI_B0_XSR0_COF_Msk (0x4000UL) /*!< COF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_XSR0_AEDF_Pos (15UL) /*!< AEDF (Bit 15) */
|
|
|
+ #define R_SCI_B0_XSR0_AEDF_Msk (0x8000UL) /*!< AEDF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_XSR0_CF0RD_Pos (16UL) /*!< CF0RD (Bit 16) */
|
|
|
+ #define R_SCI_B0_XSR0_CF0RD_Msk (0xff0000UL) /*!< CF0RD (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_SCI_B0_XSR0_CF1RD_Pos (24UL) /*!< CF1RD (Bit 24) */
|
|
|
+ #define R_SCI_B0_XSR0_CF1RD_Msk (0xff000000UL) /*!< CF1RD (Bitfield-Mask: 0xff) */
|
|
|
+/* ========================================================= XSR1 ========================================================== */
|
|
|
+ #define R_SCI_B0_XSR1_TCNT_Pos (0UL) /*!< TCNT (Bit 0) */
|
|
|
+ #define R_SCI_B0_XSR1_TCNT_Msk (0xffffUL) /*!< TCNT (Bitfield-Mask: 0xffff) */
|
|
|
+/* ========================================================= CFCLR ========================================================= */
|
|
|
+ #define R_SCI_B0_CFCLR_ERSC_Pos (4UL) /*!< ERSC (Bit 4) */
|
|
|
+ #define R_SCI_B0_CFCLR_ERSC_Msk (0x10UL) /*!< ERSC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CFCLR_DCMFC_Pos (16UL) /*!< DCMFC (Bit 16) */
|
|
|
+ #define R_SCI_B0_CFCLR_DCMFC_Msk (0x10000UL) /*!< DCMFC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CFCLR_DPERC_Pos (17UL) /*!< DPERC (Bit 17) */
|
|
|
+ #define R_SCI_B0_CFCLR_DPERC_Msk (0x20000UL) /*!< DPERC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CFCLR_DFERC_Pos (18UL) /*!< DFERC (Bit 18) */
|
|
|
+ #define R_SCI_B0_CFCLR_DFERC_Msk (0x40000UL) /*!< DFERC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CFCLR_ORERC_Pos (24UL) /*!< ORERC (Bit 24) */
|
|
|
+ #define R_SCI_B0_CFCLR_ORERC_Msk (0x1000000UL) /*!< ORERC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CFCLR_MFFC_Pos (26UL) /*!< MFFC (Bit 26) */
|
|
|
+ #define R_SCI_B0_CFCLR_MFFC_Msk (0x4000000UL) /*!< MFFC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CFCLR_PERC_Pos (27UL) /*!< PERC (Bit 27) */
|
|
|
+ #define R_SCI_B0_CFCLR_PERC_Msk (0x8000000UL) /*!< PERC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CFCLR_FERC_Pos (28UL) /*!< FERC (Bit 28) */
|
|
|
+ #define R_SCI_B0_CFCLR_FERC_Msk (0x10000000UL) /*!< FERC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CFCLR_TDREC_Pos (29UL) /*!< TDREC (Bit 29) */
|
|
|
+ #define R_SCI_B0_CFCLR_TDREC_Msk (0x20000000UL) /*!< TDREC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_CFCLR_RDRFC_Pos (31UL) /*!< RDRFC (Bit 31) */
|
|
|
+ #define R_SCI_B0_CFCLR_RDRFC_Msk (0x80000000UL) /*!< RDRFC (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== ICFCLR ========================================================= */
|
|
|
+ #define R_SCI_B0_ICFCLR_IICSTIFC_Pos (3UL) /*!< IICSTIFC (Bit 3) */
|
|
|
+ #define R_SCI_B0_ICFCLR_IICSTIFC_Msk (0x8UL) /*!< IICSTIFC (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= FFCLR ========================================================= */
|
|
|
+ #define R_SCI_B0_FFCLR_DRC_Pos (0UL) /*!< DRC (Bit 0) */
|
|
|
+ #define R_SCI_B0_FFCLR_DRC_Msk (0x1UL) /*!< DRC (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= MFCLR ========================================================= */
|
|
|
+ #define R_SCI_B0_MFCLR_PFERC_Pos (0UL) /*!< PFERC (Bit 0) */
|
|
|
+ #define R_SCI_B0_MFCLR_PFERC_Msk (0x1UL) /*!< PFERC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_MFCLR_SYERC_Pos (1UL) /*!< SYERC (Bit 1) */
|
|
|
+ #define R_SCI_B0_MFCLR_SYERC_Msk (0x2UL) /*!< SYERC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_MFCLR_SBERC_Pos (2UL) /*!< SBERC (Bit 2) */
|
|
|
+ #define R_SCI_B0_MFCLR_SBERC_Msk (0x4UL) /*!< SBERC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_MFCLR_MERC_Pos (4UL) /*!< MERC (Bit 4) */
|
|
|
+ #define R_SCI_B0_MFCLR_MERC_Msk (0x10UL) /*!< MERC (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= XFCLR ========================================================= */
|
|
|
+ #define R_SCI_B0_XFCLR_BFOC_Pos (8UL) /*!< BFOC (Bit 8) */
|
|
|
+ #define R_SCI_B0_XFCLR_BFOC_Msk (0x100UL) /*!< BFOC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_XFCLR_BCDC_Pos (9UL) /*!< BCDC (Bit 9) */
|
|
|
+ #define R_SCI_B0_XFCLR_BCDC_Msk (0x200UL) /*!< BCDC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_XFCLR_BFDC_Pos (10UL) /*!< BFDC (Bit 10) */
|
|
|
+ #define R_SCI_B0_XFCLR_BFDC_Msk (0x400UL) /*!< BFDC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_XFCLR_CF0MC_Pos (11UL) /*!< CF0MC (Bit 11) */
|
|
|
+ #define R_SCI_B0_XFCLR_CF0MC_Msk (0x800UL) /*!< CF0MC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_XFCLR_CF1MC_Pos (12UL) /*!< CF1MC (Bit 12) */
|
|
|
+ #define R_SCI_B0_XFCLR_CF1MC_Msk (0x1000UL) /*!< CF1MC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_XFCLR_PIBDC_Pos (13UL) /*!< PIBDC (Bit 13) */
|
|
|
+ #define R_SCI_B0_XFCLR_PIBDC_Msk (0x2000UL) /*!< PIBDC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_XFCLR_COFC_Pos (14UL) /*!< COFC (Bit 14) */
|
|
|
+ #define R_SCI_B0_XFCLR_COFC_Msk (0x4000UL) /*!< COFC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SCI_B0_XFCLR_AEDC_Pos (15UL) /*!< AEDC (Bit 15) */
|
|
|
+ #define R_SCI_B0_XFCLR_AEDC_Msk (0x8000UL) /*!< AEDC (Bitfield-Mask: 0x01) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_SPI_B0 ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================= SPDR ========================================================== */
|
|
|
+/* ======================================================== SPDECR ========================================================= */
|
|
|
+ #define R_SPI_B0_SPDECR_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */
|
|
|
+ #define R_SPI_B0_SPDECR_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_SPI_B0_SPDECR_SLNDL_Pos (8UL) /*!< SLNDL (Bit 8) */
|
|
|
+ #define R_SPI_B0_SPDECR_SLNDL_Msk (0x700UL) /*!< SLNDL (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_SPI_B0_SPDECR_SPNDL_Pos (16UL) /*!< SPNDL (Bit 16) */
|
|
|
+ #define R_SPI_B0_SPDECR_SPNDL_Msk (0x70000UL) /*!< SPNDL (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_SPI_B0_SPDECR_ARST_Pos (24UL) /*!< ARST (Bit 24) */
|
|
|
+ #define R_SPI_B0_SPDECR_ARST_Msk (0x7000000UL) /*!< ARST (Bitfield-Mask: 0x07) */
|
|
|
+/* ========================================================= SPCR ========================================================== */
|
|
|
+ #define R_SPI_B0_SPCR_SPE_Pos (0UL) /*!< SPE (Bit 0) */
|
|
|
+ #define R_SPI_B0_SPCR_SPE_Msk (0x1UL) /*!< SPE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCR_SPSCKSEL_Pos (7UL) /*!< SPSCKSEL (Bit 7) */
|
|
|
+ #define R_SPI_B0_SPCR_SPSCKSEL_Msk (0x80UL) /*!< SPSCKSEL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCR_SPPE_Pos (8UL) /*!< SPPE (Bit 8) */
|
|
|
+ #define R_SPI_B0_SPCR_SPPE_Msk (0x100UL) /*!< SPPE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCR_SPOE_Pos (9UL) /*!< SPOE (Bit 9) */
|
|
|
+ #define R_SPI_B0_SPCR_SPOE_Msk (0x200UL) /*!< SPOE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCR_PTE_Pos (11UL) /*!< PTE (Bit 11) */
|
|
|
+ #define R_SPI_B0_SPCR_PTE_Msk (0x800UL) /*!< PTE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCR_SCKASE_Pos (12UL) /*!< SCKASE (Bit 12) */
|
|
|
+ #define R_SPI_B0_SPCR_SCKASE_Msk (0x1000UL) /*!< SCKASE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCR_BFDS_Pos (13UL) /*!< BFDS (Bit 13) */
|
|
|
+ #define R_SPI_B0_SPCR_BFDS_Msk (0x2000UL) /*!< BFDS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCR_MODFEN_Pos (14UL) /*!< MODFEN (Bit 14) */
|
|
|
+ #define R_SPI_B0_SPCR_MODFEN_Msk (0x4000UL) /*!< MODFEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCR_SPEIE_Pos (16UL) /*!< SPEIE (Bit 16) */
|
|
|
+ #define R_SPI_B0_SPCR_SPEIE_Msk (0x10000UL) /*!< SPEIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCR_SPRIE_Pos (17UL) /*!< SPRIE (Bit 17) */
|
|
|
+ #define R_SPI_B0_SPCR_SPRIE_Msk (0x20000UL) /*!< SPRIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCR_SPIIE_Pos (18UL) /*!< SPIIE (Bit 18) */
|
|
|
+ #define R_SPI_B0_SPCR_SPIIE_Msk (0x40000UL) /*!< SPIIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCR_SPDRES_Pos (19UL) /*!< SPDRES (Bit 19) */
|
|
|
+ #define R_SPI_B0_SPCR_SPDRES_Msk (0x80000UL) /*!< SPDRES (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCR_SPTIE_Pos (20UL) /*!< SPTIE (Bit 20) */
|
|
|
+ #define R_SPI_B0_SPCR_SPTIE_Msk (0x100000UL) /*!< SPTIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCR_CENDIE_Pos (21UL) /*!< CENDIE (Bit 21) */
|
|
|
+ #define R_SPI_B0_SPCR_CENDIE_Msk (0x200000UL) /*!< CENDIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCR_SPMS_Pos (24UL) /*!< SPMS (Bit 24) */
|
|
|
+ #define R_SPI_B0_SPCR_SPMS_Msk (0x1000000UL) /*!< SPMS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCR_SPFRF_Pos (25UL) /*!< SPFRF (Bit 25) */
|
|
|
+ #define R_SPI_B0_SPCR_SPFRF_Msk (0x2000000UL) /*!< SPFRF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCR_TXMD_Pos (28UL) /*!< TXMD (Bit 28) */
|
|
|
+ #define R_SPI_B0_SPCR_TXMD_Msk (0x30000000UL) /*!< TXMD (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_SPI_B0_SPCR_MSTR_Pos (30UL) /*!< MSTR (Bit 30) */
|
|
|
+ #define R_SPI_B0_SPCR_MSTR_Msk (0x40000000UL) /*!< MSTR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCR_BPEN_Pos (31UL) /*!< BPEN (Bit 31) */
|
|
|
+ #define R_SPI_B0_SPCR_BPEN_Msk (0x80000000UL) /*!< BPEN (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= SPCR2 ========================================================= */
|
|
|
+ #define R_SPI_B0_SPCR2_RMFM_Pos (0UL) /*!< RMFM (Bit 0) */
|
|
|
+ #define R_SPI_B0_SPCR2_RMFM_Msk (0x1fUL) /*!< RMFM (Bitfield-Mask: 0x1f) */
|
|
|
+ #define R_SPI_B0_SPCR2_RMEDTG_Pos (6UL) /*!< RMEDTG (Bit 6) */
|
|
|
+ #define R_SPI_B0_SPCR2_RMEDTG_Msk (0x40UL) /*!< RMEDTG (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCR2_RMSTTG_Pos (7UL) /*!< RMSTTG (Bit 7) */
|
|
|
+ #define R_SPI_B0_SPCR2_RMSTTG_Msk (0x80UL) /*!< RMSTTG (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCR2_SPDRC_Pos (8UL) /*!< SPDRC (Bit 8) */
|
|
|
+ #define R_SPI_B0_SPCR2_SPDRC_Msk (0xff00UL) /*!< SPDRC (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_SPI_B0_SPCR2_SPLP_Pos (16UL) /*!< SPLP (Bit 16) */
|
|
|
+ #define R_SPI_B0_SPCR2_SPLP_Msk (0x10000UL) /*!< SPLP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCR2_SPLP2_Pos (17UL) /*!< SPLP2 (Bit 17) */
|
|
|
+ #define R_SPI_B0_SPCR2_SPLP2_Msk (0x20000UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCR2_MOIFV_Pos (20UL) /*!< MOIFV (Bit 20) */
|
|
|
+ #define R_SPI_B0_SPCR2_MOIFV_Msk (0x100000UL) /*!< MOIFV (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCR2_MOIFE_Pos (21UL) /*!< MOIFE (Bit 21) */
|
|
|
+ #define R_SPI_B0_SPCR2_MOIFE_Msk (0x200000UL) /*!< MOIFE (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= SPCR3 ========================================================= */
|
|
|
+ #define R_SPI_B0_SPCR3_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */
|
|
|
+ #define R_SPI_B0_SPCR3_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCR3_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */
|
|
|
+ #define R_SPI_B0_SPCR3_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCR3_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */
|
|
|
+ #define R_SPI_B0_SPCR3_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCR3_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */
|
|
|
+ #define R_SPI_B0_SPCR3_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCR3_SPBR_Pos (8UL) /*!< SPBR (Bit 8) */
|
|
|
+ #define R_SPI_B0_SPCR3_SPBR_Msk (0xff00UL) /*!< SPBR (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_SPI_B0_SPCR3_SPSLN_Pos (24UL) /*!< SPSLN (Bit 24) */
|
|
|
+ #define R_SPI_B0_SPCR3_SPSLN_Msk (0x7000000UL) /*!< SPSLN (Bitfield-Mask: 0x07) */
|
|
|
+/* ======================================================== SPCMD0 ========================================================= */
|
|
|
+ #define R_SPI_B0_SPCMD0_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */
|
|
|
+ #define R_SPI_B0_SPCMD0_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD0_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */
|
|
|
+ #define R_SPI_B0_SPCMD0_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD0_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */
|
|
|
+ #define R_SPI_B0_SPCMD0_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_SPI_B0_SPCMD0_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */
|
|
|
+ #define R_SPI_B0_SPCMD0_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD0_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */
|
|
|
+ #define R_SPI_B0_SPCMD0_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD0_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */
|
|
|
+ #define R_SPI_B0_SPCMD0_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD0_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */
|
|
|
+ #define R_SPI_B0_SPCMD0_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD0_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */
|
|
|
+ #define R_SPI_B0_SPCMD0_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD0_SPB_Pos (16UL) /*!< SPB (Bit 16) */
|
|
|
+ #define R_SPI_B0_SPCMD0_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */
|
|
|
+ #define R_SPI_B0_SPCMD0_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */
|
|
|
+ #define R_SPI_B0_SPCMD0_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */
|
|
|
+/* ======================================================== SPCMD1 ========================================================= */
|
|
|
+ #define R_SPI_B0_SPCMD1_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */
|
|
|
+ #define R_SPI_B0_SPCMD1_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD1_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */
|
|
|
+ #define R_SPI_B0_SPCMD1_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD1_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */
|
|
|
+ #define R_SPI_B0_SPCMD1_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_SPI_B0_SPCMD1_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */
|
|
|
+ #define R_SPI_B0_SPCMD1_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD1_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */
|
|
|
+ #define R_SPI_B0_SPCMD1_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD1_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */
|
|
|
+ #define R_SPI_B0_SPCMD1_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD1_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */
|
|
|
+ #define R_SPI_B0_SPCMD1_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD1_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */
|
|
|
+ #define R_SPI_B0_SPCMD1_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD1_SPB_Pos (16UL) /*!< SPB (Bit 16) */
|
|
|
+ #define R_SPI_B0_SPCMD1_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */
|
|
|
+ #define R_SPI_B0_SPCMD1_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */
|
|
|
+ #define R_SPI_B0_SPCMD1_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */
|
|
|
+/* ======================================================== SPCMD2 ========================================================= */
|
|
|
+ #define R_SPI_B0_SPCMD2_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */
|
|
|
+ #define R_SPI_B0_SPCMD2_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD2_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */
|
|
|
+ #define R_SPI_B0_SPCMD2_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD2_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */
|
|
|
+ #define R_SPI_B0_SPCMD2_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_SPI_B0_SPCMD2_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */
|
|
|
+ #define R_SPI_B0_SPCMD2_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD2_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */
|
|
|
+ #define R_SPI_B0_SPCMD2_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD2_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */
|
|
|
+ #define R_SPI_B0_SPCMD2_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD2_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */
|
|
|
+ #define R_SPI_B0_SPCMD2_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD2_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */
|
|
|
+ #define R_SPI_B0_SPCMD2_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD2_SPB_Pos (16UL) /*!< SPB (Bit 16) */
|
|
|
+ #define R_SPI_B0_SPCMD2_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */
|
|
|
+ #define R_SPI_B0_SPCMD2_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */
|
|
|
+ #define R_SPI_B0_SPCMD2_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */
|
|
|
+/* ======================================================== SPCMD3 ========================================================= */
|
|
|
+ #define R_SPI_B0_SPCMD3_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */
|
|
|
+ #define R_SPI_B0_SPCMD3_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD3_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */
|
|
|
+ #define R_SPI_B0_SPCMD3_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD3_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */
|
|
|
+ #define R_SPI_B0_SPCMD3_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_SPI_B0_SPCMD3_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */
|
|
|
+ #define R_SPI_B0_SPCMD3_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD3_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */
|
|
|
+ #define R_SPI_B0_SPCMD3_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD3_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */
|
|
|
+ #define R_SPI_B0_SPCMD3_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD3_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */
|
|
|
+ #define R_SPI_B0_SPCMD3_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD3_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */
|
|
|
+ #define R_SPI_B0_SPCMD3_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD3_SPB_Pos (16UL) /*!< SPB (Bit 16) */
|
|
|
+ #define R_SPI_B0_SPCMD3_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */
|
|
|
+ #define R_SPI_B0_SPCMD3_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */
|
|
|
+ #define R_SPI_B0_SPCMD3_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */
|
|
|
+/* ======================================================== SPCMD4 ========================================================= */
|
|
|
+ #define R_SPI_B0_SPCMD4_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */
|
|
|
+ #define R_SPI_B0_SPCMD4_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD4_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */
|
|
|
+ #define R_SPI_B0_SPCMD4_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD4_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */
|
|
|
+ #define R_SPI_B0_SPCMD4_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_SPI_B0_SPCMD4_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */
|
|
|
+ #define R_SPI_B0_SPCMD4_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD4_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */
|
|
|
+ #define R_SPI_B0_SPCMD4_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD4_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */
|
|
|
+ #define R_SPI_B0_SPCMD4_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD4_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */
|
|
|
+ #define R_SPI_B0_SPCMD4_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD4_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */
|
|
|
+ #define R_SPI_B0_SPCMD4_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD4_SPB_Pos (16UL) /*!< SPB (Bit 16) */
|
|
|
+ #define R_SPI_B0_SPCMD4_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */
|
|
|
+ #define R_SPI_B0_SPCMD4_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */
|
|
|
+ #define R_SPI_B0_SPCMD4_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */
|
|
|
+/* ======================================================== SPCMD5 ========================================================= */
|
|
|
+ #define R_SPI_B0_SPCMD5_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */
|
|
|
+ #define R_SPI_B0_SPCMD5_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD5_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */
|
|
|
+ #define R_SPI_B0_SPCMD5_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD5_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */
|
|
|
+ #define R_SPI_B0_SPCMD5_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_SPI_B0_SPCMD5_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */
|
|
|
+ #define R_SPI_B0_SPCMD5_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD5_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */
|
|
|
+ #define R_SPI_B0_SPCMD5_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD5_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */
|
|
|
+ #define R_SPI_B0_SPCMD5_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD5_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */
|
|
|
+ #define R_SPI_B0_SPCMD5_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD5_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */
|
|
|
+ #define R_SPI_B0_SPCMD5_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD5_SPB_Pos (16UL) /*!< SPB (Bit 16) */
|
|
|
+ #define R_SPI_B0_SPCMD5_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */
|
|
|
+ #define R_SPI_B0_SPCMD5_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */
|
|
|
+ #define R_SPI_B0_SPCMD5_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */
|
|
|
+/* ======================================================== SPCMD6 ========================================================= */
|
|
|
+ #define R_SPI_B0_SPCMD6_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */
|
|
|
+ #define R_SPI_B0_SPCMD6_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD6_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */
|
|
|
+ #define R_SPI_B0_SPCMD6_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD6_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */
|
|
|
+ #define R_SPI_B0_SPCMD6_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_SPI_B0_SPCMD6_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */
|
|
|
+ #define R_SPI_B0_SPCMD6_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD6_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */
|
|
|
+ #define R_SPI_B0_SPCMD6_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD6_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */
|
|
|
+ #define R_SPI_B0_SPCMD6_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD6_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */
|
|
|
+ #define R_SPI_B0_SPCMD6_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD6_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */
|
|
|
+ #define R_SPI_B0_SPCMD6_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD6_SPB_Pos (16UL) /*!< SPB (Bit 16) */
|
|
|
+ #define R_SPI_B0_SPCMD6_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */
|
|
|
+ #define R_SPI_B0_SPCMD6_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */
|
|
|
+ #define R_SPI_B0_SPCMD6_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */
|
|
|
+/* ======================================================== SPCMD7 ========================================================= */
|
|
|
+ #define R_SPI_B0_SPCMD7_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */
|
|
|
+ #define R_SPI_B0_SPCMD7_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD7_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */
|
|
|
+ #define R_SPI_B0_SPCMD7_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD7_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */
|
|
|
+ #define R_SPI_B0_SPCMD7_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_SPI_B0_SPCMD7_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */
|
|
|
+ #define R_SPI_B0_SPCMD7_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD7_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */
|
|
|
+ #define R_SPI_B0_SPCMD7_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD7_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */
|
|
|
+ #define R_SPI_B0_SPCMD7_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD7_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */
|
|
|
+ #define R_SPI_B0_SPCMD7_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD7_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */
|
|
|
+ #define R_SPI_B0_SPCMD7_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPCMD7_SPB_Pos (16UL) /*!< SPB (Bit 16) */
|
|
|
+ #define R_SPI_B0_SPCMD7_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */
|
|
|
+ #define R_SPI_B0_SPCMD7_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */
|
|
|
+ #define R_SPI_B0_SPCMD7_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */
|
|
|
+/* ========================================================= SPDCR ========================================================= */
|
|
|
+ #define R_SPI_B0_SPDCR_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */
|
|
|
+ #define R_SPI_B0_SPDCR_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPDCR_SPRDTD_Pos (3UL) /*!< SPRDTD (Bit 3) */
|
|
|
+ #define R_SPI_B0_SPDCR_SPRDTD_Msk (0x8UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPDCR_SINV_Pos (4UL) /*!< SINV (Bit 4) */
|
|
|
+ #define R_SPI_B0_SPDCR_SINV_Msk (0x10UL) /*!< SINV (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPDCR_SPFC_Pos (8UL) /*!< SPFC (Bit 8) */
|
|
|
+ #define R_SPI_B0_SPDCR_SPFC_Msk (0x300UL) /*!< SPFC (Bitfield-Mask: 0x03) */
|
|
|
+/* ======================================================== SPDCR2 ========================================================= */
|
|
|
+ #define R_SPI_B0_SPDCR2_RTRG_Pos (0UL) /*!< RTRG (Bit 0) */
|
|
|
+ #define R_SPI_B0_SPDCR2_RTRG_Msk (0x3UL) /*!< RTRG (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_SPI_B0_SPDCR2_TTRG_Pos (8UL) /*!< TTRG (Bit 8) */
|
|
|
+ #define R_SPI_B0_SPDCR2_TTRG_Msk (0x300UL) /*!< TTRG (Bitfield-Mask: 0x03) */
|
|
|
+/* ========================================================= SPSR ========================================================== */
|
|
|
+ #define R_SPI_B0_SPSR_SPCP_Pos (8UL) /*!< SPCP (Bit 8) */
|
|
|
+ #define R_SPI_B0_SPSR_SPCP_Msk (0x700UL) /*!< SPCP (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_SPI_B0_SPSR_SPECM_Pos (12UL) /*!< SPECM (Bit 12) */
|
|
|
+ #define R_SPI_B0_SPSR_SPECM_Msk (0x7000UL) /*!< SPECM (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_SPI_B0_SPSR_SPDRF_Pos (23UL) /*!< SPDRF (Bit 23) */
|
|
|
+ #define R_SPI_B0_SPSR_SPDRF_Msk (0x800000UL) /*!< SPDRF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPSR_OVRF_Pos (24UL) /*!< OVRF (Bit 24) */
|
|
|
+ #define R_SPI_B0_SPSR_OVRF_Msk (0x1000000UL) /*!< OVRF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPSR_IDLNF_Pos (25UL) /*!< IDLNF (Bit 25) */
|
|
|
+ #define R_SPI_B0_SPSR_IDLNF_Msk (0x2000000UL) /*!< IDLNF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPSR_MODF_Pos (26UL) /*!< MODF (Bit 26) */
|
|
|
+ #define R_SPI_B0_SPSR_MODF_Msk (0x4000000UL) /*!< MODF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPSR_PERF_Pos (27UL) /*!< PERF (Bit 27) */
|
|
|
+ #define R_SPI_B0_SPSR_PERF_Msk (0x8000000UL) /*!< PERF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPSR_UDRF_Pos (28UL) /*!< UDRF (Bit 28) */
|
|
|
+ #define R_SPI_B0_SPSR_UDRF_Msk (0x10000000UL) /*!< UDRF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPSR_SPTEF_Pos (29UL) /*!< SPTEF (Bit 29) */
|
|
|
+ #define R_SPI_B0_SPSR_SPTEF_Msk (0x20000000UL) /*!< SPTEF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPSR_CENDF_Pos (30UL) /*!< CENDF (Bit 30) */
|
|
|
+ #define R_SPI_B0_SPSR_CENDF_Msk (0x40000000UL) /*!< CENDF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPSR_SPRF_Pos (31UL) /*!< SPRF (Bit 31) */
|
|
|
+ #define R_SPI_B0_SPSR_SPRF_Msk (0x80000000UL) /*!< SPRF (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== SPTFSR ========================================================= */
|
|
|
+ #define R_SPI_B0_SPTFSR_TFDN_Pos (0UL) /*!< TFDN (Bit 0) */
|
|
|
+ #define R_SPI_B0_SPTFSR_TFDN_Msk (0x7UL) /*!< TFDN (Bitfield-Mask: 0x07) */
|
|
|
+/* ======================================================== SPRFSR ========================================================= */
|
|
|
+ #define R_SPI_B0_SPRFSR_RFDN_Pos (0UL) /*!< RFDN (Bit 0) */
|
|
|
+ #define R_SPI_B0_SPRFSR_RFDN_Msk (0x7UL) /*!< RFDN (Bitfield-Mask: 0x07) */
|
|
|
+/* ========================================================= SPPSR ========================================================= */
|
|
|
+ #define R_SPI_B0_SPPSR_SPEPS_Pos (0UL) /*!< SPEPS (Bit 0) */
|
|
|
+ #define R_SPI_B0_SPPSR_SPEPS_Msk (0x1UL) /*!< SPEPS (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= SPSRC ========================================================= */
|
|
|
+ #define R_SPI_B0_SPSRC_SPDRFC_Pos (23UL) /*!< SPDRFC (Bit 23) */
|
|
|
+ #define R_SPI_B0_SPSRC_SPDRFC_Msk (0x800000UL) /*!< SPDRFC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPSRC_OVRFC_Pos (24UL) /*!< OVRFC (Bit 24) */
|
|
|
+ #define R_SPI_B0_SPSRC_OVRFC_Msk (0x1000000UL) /*!< OVRFC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPSRC_MODFC_Pos (26UL) /*!< MODFC (Bit 26) */
|
|
|
+ #define R_SPI_B0_SPSRC_MODFC_Msk (0x4000000UL) /*!< MODFC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPSRC_PERFC_Pos (27UL) /*!< PERFC (Bit 27) */
|
|
|
+ #define R_SPI_B0_SPSRC_PERFC_Msk (0x8000000UL) /*!< PERFC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPSRC_UDRFC_Pos (28UL) /*!< UDRFC (Bit 28) */
|
|
|
+ #define R_SPI_B0_SPSRC_UDRFC_Msk (0x10000000UL) /*!< UDRFC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPSRC_SPTEFC_Pos (29UL) /*!< SPTEFC (Bit 29) */
|
|
|
+ #define R_SPI_B0_SPSRC_SPTEFC_Msk (0x20000000UL) /*!< SPTEFC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPSRC_CENDFC_Pos (30UL) /*!< CENDFC (Bit 30) */
|
|
|
+ #define R_SPI_B0_SPSRC_CENDFC_Msk (0x40000000UL) /*!< CENDFC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_SPI_B0_SPSRC_SPRFC_Pos (31UL) /*!< SPRFC (Bit 31) */
|
|
|
+ #define R_SPI_B0_SPSRC_SPRFC_Msk (0x80000000UL) /*!< SPRFC (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= SPFCR ========================================================= */
|
|
|
+ #define R_SPI_B0_SPFCR_SPFRST_Pos (0UL) /*!< SPFRST (Bit 0) */
|
|
|
+ #define R_SPI_B0_SPFCR_SPFRST_Msk (0x1UL) /*!< SPFRST (Bitfield-Mask: 0x01) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_USB_HS0 ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ======================================================== SYSCFG ========================================================= */
|
|
|
+ #define R_USB_HS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */
|
|
|
+ #define R_USB_HS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_SYSCFG_HSE_Pos (7UL) /*!< HSE (Bit 7) */
|
|
|
+ #define R_USB_HS0_SYSCFG_HSE_Msk (0x80UL) /*!< HSE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */
|
|
|
+ #define R_USB_HS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */
|
|
|
+ #define R_USB_HS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */
|
|
|
+ #define R_USB_HS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */
|
|
|
+ #define R_USB_HS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== BUSWAIT ======================================================== */
|
|
|
+ #define R_USB_HS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */
|
|
|
+ #define R_USB_HS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */
|
|
|
+/* ======================================================== SYSSTS0 ======================================================== */
|
|
|
+ #define R_USB_HS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */
|
|
|
+ #define R_USB_HS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */
|
|
|
+ #define R_USB_HS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */
|
|
|
+ #define R_USB_HS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */
|
|
|
+ #define R_USB_HS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_USB_HS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */
|
|
|
+ #define R_USB_HS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */
|
|
|
+/* ======================================================== PLLSTA ========================================================= */
|
|
|
+ #define R_USB_HS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */
|
|
|
+ #define R_USB_HS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= DVSTCTR0 ======================================================== */
|
|
|
+ #define R_USB_HS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */
|
|
|
+ #define R_USB_HS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */
|
|
|
+ #define R_USB_HS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */
|
|
|
+ #define R_USB_HS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */
|
|
|
+ #define R_USB_HS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */
|
|
|
+ #define R_USB_HS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */
|
|
|
+ #define R_USB_HS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */
|
|
|
+ #define R_USB_HS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */
|
|
|
+ #define R_USB_HS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */
|
|
|
+ #define R_USB_HS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */
|
|
|
+/* ======================================================= TESTMODE ======================================================== */
|
|
|
+ #define R_USB_HS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */
|
|
|
+ #define R_USB_HS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */
|
|
|
+/* ========================================================= CFIFO ========================================================= */
|
|
|
+ #define R_USB_HS0_CFIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */
|
|
|
+ #define R_USB_HS0_CFIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================== CFIFOL ========================================================= */
|
|
|
+/* ======================================================== CFIFOH ========================================================= */
|
|
|
+/* ======================================================== CFIFOLL ======================================================== */
|
|
|
+/* ======================================================== CFIFOHH ======================================================== */
|
|
|
+/* ======================================================== D0FIFO ========================================================= */
|
|
|
+ #define R_USB_HS0_D0FIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */
|
|
|
+ #define R_USB_HS0_D0FIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================== D0FIFOL ======================================================== */
|
|
|
+/* ======================================================== D0FIFOH ======================================================== */
|
|
|
+/* ======================================================= D0FIFOLL ======================================================== */
|
|
|
+/* ======================================================= D0FIFOHH ======================================================== */
|
|
|
+/* ======================================================== D1FIFO ========================================================= */
|
|
|
+ #define R_USB_HS0_D1FIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */
|
|
|
+ #define R_USB_HS0_D1FIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================== D1FIFOL ======================================================== */
|
|
|
+/* ======================================================== D1FIFOH ======================================================== */
|
|
|
+/* ======================================================= D1FIFOLL ======================================================== */
|
|
|
+/* ======================================================= D1FIFOHH ======================================================== */
|
|
|
+/* ======================================================= CFIFOSEL ======================================================== */
|
|
|
+ #define R_USB_HS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */
|
|
|
+ #define R_USB_HS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */
|
|
|
+ #define R_USB_HS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */
|
|
|
+ #define R_USB_HS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_USB_HS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */
|
|
|
+ #define R_USB_HS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */
|
|
|
+ #define R_USB_HS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */
|
|
|
+ #define R_USB_HS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */
|
|
|
+/* ======================================================= CFIFOCTR ======================================================== */
|
|
|
+ #define R_USB_HS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */
|
|
|
+ #define R_USB_HS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */
|
|
|
+ #define R_USB_HS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */
|
|
|
+ #define R_USB_HS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */
|
|
|
+ #define R_USB_HS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */
|
|
|
+/* ======================================================= D0FIFOSEL ======================================================= */
|
|
|
+ #define R_USB_HS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */
|
|
|
+ #define R_USB_HS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */
|
|
|
+ #define R_USB_HS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */
|
|
|
+ #define R_USB_HS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */
|
|
|
+ #define R_USB_HS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */
|
|
|
+ #define R_USB_HS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_USB_HS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */
|
|
|
+ #define R_USB_HS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */
|
|
|
+ #define R_USB_HS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */
|
|
|
+/* ======================================================= D0FIFOCTR ======================================================= */
|
|
|
+ #define R_USB_HS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */
|
|
|
+ #define R_USB_HS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */
|
|
|
+ #define R_USB_HS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */
|
|
|
+ #define R_USB_HS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */
|
|
|
+ #define R_USB_HS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */
|
|
|
+/* ======================================================= D1FIFOSEL ======================================================= */
|
|
|
+ #define R_USB_HS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */
|
|
|
+ #define R_USB_HS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */
|
|
|
+ #define R_USB_HS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */
|
|
|
+ #define R_USB_HS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */
|
|
|
+ #define R_USB_HS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */
|
|
|
+ #define R_USB_HS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_USB_HS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */
|
|
|
+ #define R_USB_HS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */
|
|
|
+ #define R_USB_HS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */
|
|
|
+/* ======================================================= D1FIFOCTR ======================================================= */
|
|
|
+ #define R_USB_HS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */
|
|
|
+ #define R_USB_HS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */
|
|
|
+ #define R_USB_HS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */
|
|
|
+ #define R_USB_HS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */
|
|
|
+ #define R_USB_HS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */
|
|
|
+/* ======================================================== INTENB0 ======================================================== */
|
|
|
+ #define R_USB_HS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */
|
|
|
+ #define R_USB_HS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */
|
|
|
+ #define R_USB_HS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */
|
|
|
+ #define R_USB_HS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */
|
|
|
+ #define R_USB_HS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */
|
|
|
+ #define R_USB_HS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */
|
|
|
+ #define R_USB_HS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */
|
|
|
+ #define R_USB_HS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */
|
|
|
+ #define R_USB_HS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== INTENB1 ======================================================== */
|
|
|
+ #define R_USB_HS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */
|
|
|
+ #define R_USB_HS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */
|
|
|
+ #define R_USB_HS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */
|
|
|
+ #define R_USB_HS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */
|
|
|
+ #define R_USB_HS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_INTENB1_L1RSMENDE_Pos (9UL) /*!< L1RSMENDE (Bit 9) */
|
|
|
+ #define R_USB_HS0_INTENB1_L1RSMENDE_Msk (0x200UL) /*!< L1RSMENDE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_INTENB1_LPMENDE_Pos (8UL) /*!< LPMENDE (Bit 8) */
|
|
|
+ #define R_USB_HS0_INTENB1_LPMENDE_Msk (0x100UL) /*!< LPMENDE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */
|
|
|
+ #define R_USB_HS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */
|
|
|
+ #define R_USB_HS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */
|
|
|
+ #define R_USB_HS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */
|
|
|
+ #define R_USB_HS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== BRDYENB ======================================================== */
|
|
|
+ #define R_USB_HS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */
|
|
|
+ #define R_USB_HS0_BRDYENB_PIPEBRDYE_Msk (0x3ffUL) /*!< PIPEBRDYE (Bitfield-Mask: 0x3ff) */
|
|
|
+/* ======================================================== NRDYENB ======================================================== */
|
|
|
+ #define R_USB_HS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */
|
|
|
+ #define R_USB_HS0_NRDYENB_PIPENRDYE_Msk (0x3ffUL) /*!< PIPENRDYE (Bitfield-Mask: 0x3ff) */
|
|
|
+/* ======================================================== BEMPENB ======================================================== */
|
|
|
+ #define R_USB_HS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */
|
|
|
+ #define R_USB_HS0_BEMPENB_PIPEBEMPE_Msk (0x3ffUL) /*!< PIPEBEMPE (Bitfield-Mask: 0x3ff) */
|
|
|
+/* ======================================================== SOFCFG ========================================================= */
|
|
|
+ #define R_USB_HS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */
|
|
|
+ #define R_USB_HS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */
|
|
|
+ #define R_USB_HS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */
|
|
|
+ #define R_USB_HS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */
|
|
|
+ #define R_USB_HS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== PHYSET ========================================================= */
|
|
|
+ #define R_USB_HS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */
|
|
|
+ #define R_USB_HS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */
|
|
|
+ #define R_USB_HS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */
|
|
|
+ #define R_USB_HS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_USB_HS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */
|
|
|
+ #define R_USB_HS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_USB_HS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */
|
|
|
+ #define R_USB_HS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */
|
|
|
+ #define R_USB_HS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */
|
|
|
+ #define R_USB_HS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== INTSTS0 ======================================================== */
|
|
|
+ #define R_USB_HS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */
|
|
|
+ #define R_USB_HS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */
|
|
|
+ #define R_USB_HS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */
|
|
|
+ #define R_USB_HS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */
|
|
|
+ #define R_USB_HS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */
|
|
|
+ #define R_USB_HS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */
|
|
|
+ #define R_USB_HS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */
|
|
|
+ #define R_USB_HS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */
|
|
|
+ #define R_USB_HS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */
|
|
|
+ #define R_USB_HS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */
|
|
|
+ #define R_USB_HS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_USB_HS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */
|
|
|
+ #define R_USB_HS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */
|
|
|
+ #define R_USB_HS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */
|
|
|
+/* ======================================================== INTSTS1 ======================================================== */
|
|
|
+ #define R_USB_HS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */
|
|
|
+ #define R_USB_HS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */
|
|
|
+ #define R_USB_HS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */
|
|
|
+ #define R_USB_HS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */
|
|
|
+ #define R_USB_HS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */
|
|
|
+ #define R_USB_HS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */
|
|
|
+ #define R_USB_HS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */
|
|
|
+ #define R_USB_HS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */
|
|
|
+ #define R_USB_HS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */
|
|
|
+ #define R_USB_HS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */
|
|
|
+ #define R_USB_HS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== BRDYSTS ======================================================== */
|
|
|
+ #define R_USB_HS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */
|
|
|
+ #define R_USB_HS0_BRDYSTS_PIPEBRDY_Msk (0x3ffUL) /*!< PIPEBRDY (Bitfield-Mask: 0x3ff) */
|
|
|
+/* ======================================================== NRDYSTS ======================================================== */
|
|
|
+ #define R_USB_HS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */
|
|
|
+ #define R_USB_HS0_NRDYSTS_PIPENRDY_Msk (0x3ffUL) /*!< PIPENRDY (Bitfield-Mask: 0x3ff) */
|
|
|
+/* ======================================================== BEMPSTS ======================================================== */
|
|
|
+ #define R_USB_HS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */
|
|
|
+ #define R_USB_HS0_BEMPSTS_PIPEBEMP_Msk (0x3ffUL) /*!< PIPEBEMP (Bitfield-Mask: 0x3ff) */
|
|
|
+/* ======================================================== FRMNUM ========================================================= */
|
|
|
+ #define R_USB_HS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */
|
|
|
+ #define R_USB_HS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */
|
|
|
+ #define R_USB_HS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */
|
|
|
+ #define R_USB_HS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */
|
|
|
+/* ======================================================== UFRMNUM ======================================================== */
|
|
|
+ #define R_USB_HS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */
|
|
|
+ #define R_USB_HS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */
|
|
|
+ #define R_USB_HS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */
|
|
|
+/* ======================================================== USBADDR ======================================================== */
|
|
|
+ #define R_USB_HS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */
|
|
|
+ #define R_USB_HS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */
|
|
|
+/* ======================================================== USBREQ ========================================================= */
|
|
|
+ #define R_USB_HS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */
|
|
|
+ #define R_USB_HS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_USB_HS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */
|
|
|
+ #define R_USB_HS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================== USBVAL ========================================================= */
|
|
|
+ #define R_USB_HS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */
|
|
|
+ #define R_USB_HS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================== USBINDX ======================================================== */
|
|
|
+ #define R_USB_HS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */
|
|
|
+ #define R_USB_HS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================== USBLENG ======================================================== */
|
|
|
+ #define R_USB_HS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */
|
|
|
+ #define R_USB_HS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================== DCPCFG ========================================================= */
|
|
|
+ #define R_USB_HS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */
|
|
|
+ #define R_USB_HS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */
|
|
|
+ #define R_USB_HS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */
|
|
|
+ #define R_USB_HS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== DCPMAXP ======================================================== */
|
|
|
+ #define R_USB_HS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */
|
|
|
+ #define R_USB_HS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_USB_HS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */
|
|
|
+ #define R_USB_HS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */
|
|
|
+/* ======================================================== DCPCTR ========================================================= */
|
|
|
+ #define R_USB_HS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */
|
|
|
+ #define R_USB_HS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */
|
|
|
+ #define R_USB_HS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_DCPCTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */
|
|
|
+ #define R_USB_HS0_DCPCTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_DCPCTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */
|
|
|
+ #define R_USB_HS0_DCPCTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */
|
|
|
+ #define R_USB_HS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */
|
|
|
+ #define R_USB_HS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */
|
|
|
+ #define R_USB_HS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */
|
|
|
+ #define R_USB_HS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */
|
|
|
+ #define R_USB_HS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_DCPCTR_PINGE_Pos (4UL) /*!< PINGE (Bit 4) */
|
|
|
+ #define R_USB_HS0_DCPCTR_PINGE_Msk (0x10UL) /*!< PINGE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */
|
|
|
+ #define R_USB_HS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */
|
|
|
+ #define R_USB_HS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */
|
|
|
+/* ======================================================== PIPESEL ======================================================== */
|
|
|
+/* ======================================================== PIPECFG ======================================================== */
|
|
|
+ #define R_USB_HS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */
|
|
|
+ #define R_USB_HS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_USB_HS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */
|
|
|
+ #define R_USB_HS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */
|
|
|
+ #define R_USB_HS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_PIPECFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */
|
|
|
+ #define R_USB_HS0_PIPECFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */
|
|
|
+ #define R_USB_HS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */
|
|
|
+ #define R_USB_HS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */
|
|
|
+ #define R_USB_HS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */
|
|
|
+/* ======================================================== PIPEBUF ======================================================== */
|
|
|
+ #define R_USB_HS0_PIPEBUF_BUFSIZE_Pos (10UL) /*!< BUFSIZE (Bit 10) */
|
|
|
+ #define R_USB_HS0_PIPEBUF_BUFSIZE_Msk (0x7c00UL) /*!< BUFSIZE (Bitfield-Mask: 0x1f) */
|
|
|
+ #define R_USB_HS0_PIPEBUF_BUFNMB_Pos (0UL) /*!< BUFNMB (Bit 0) */
|
|
|
+ #define R_USB_HS0_PIPEBUF_BUFNMB_Msk (0xffUL) /*!< BUFNMB (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= PIPEMAXP ======================================================== */
|
|
|
+ #define R_USB_HS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */
|
|
|
+ #define R_USB_HS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_USB_HS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */
|
|
|
+ #define R_USB_HS0_PIPEMAXP_MXPS_Msk (0x7ffUL) /*!< MXPS (Bitfield-Mask: 0x7ff) */
|
|
|
+/* ======================================================= PIPEPERI ======================================================== */
|
|
|
+ #define R_USB_HS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */
|
|
|
+ #define R_USB_HS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */
|
|
|
+ #define R_USB_HS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */
|
|
|
+/* ======================================================= PIPE_CTR ======================================================== */
|
|
|
+ #define R_USB_HS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */
|
|
|
+ #define R_USB_HS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */
|
|
|
+ #define R_USB_HS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */
|
|
|
+ #define R_USB_HS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */
|
|
|
+ #define R_USB_HS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */
|
|
|
+ #define R_USB_HS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */
|
|
|
+ #define R_USB_HS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */
|
|
|
+ #define R_USB_HS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */
|
|
|
+ #define R_USB_HS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */
|
|
|
+ #define R_USB_HS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */
|
|
|
+ #define R_USB_HS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */
|
|
|
+ #define R_USB_HS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */
|
|
|
+/* ======================================================== DEVADD ========================================================= */
|
|
|
+ #define R_USB_HS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */
|
|
|
+ #define R_USB_HS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_USB_HS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */
|
|
|
+ #define R_USB_HS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_USB_HS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */
|
|
|
+ #define R_USB_HS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */
|
|
|
+/* ======================================================== LPCTRL ========================================================= */
|
|
|
+ #define R_USB_HS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */
|
|
|
+ #define R_USB_HS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= LPSTS ========================================================= */
|
|
|
+ #define R_USB_HS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */
|
|
|
+ #define R_USB_HS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== BCCTRL ========================================================= */
|
|
|
+ #define R_USB_HS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */
|
|
|
+ #define R_USB_HS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */
|
|
|
+ #define R_USB_HS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */
|
|
|
+ #define R_USB_HS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */
|
|
|
+ #define R_USB_HS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */
|
|
|
+ #define R_USB_HS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */
|
|
|
+ #define R_USB_HS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */
|
|
|
+ #define R_USB_HS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */
|
|
|
+ #define R_USB_HS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= PL1CTRL1 ======================================================== */
|
|
|
+ #define R_USB_HS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */
|
|
|
+ #define R_USB_HS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */
|
|
|
+ #define R_USB_HS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_USB_HS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */
|
|
|
+ #define R_USB_HS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_USB_HS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */
|
|
|
+ #define R_USB_HS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */
|
|
|
+ #define R_USB_HS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_USB_HS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */
|
|
|
+ #define R_USB_HS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= PL1CTRL2 ======================================================== */
|
|
|
+ #define R_USB_HS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */
|
|
|
+ #define R_USB_HS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */
|
|
|
+ #define R_USB_HS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */
|
|
|
+/* ======================================================= HL1CTRL1 ======================================================== */
|
|
|
+ #define R_USB_HS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */
|
|
|
+ #define R_USB_HS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_USB_HS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */
|
|
|
+ #define R_USB_HS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= HL1CTRL2 ======================================================== */
|
|
|
+ #define R_USB_HS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */
|
|
|
+ #define R_USB_HS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */
|
|
|
+ #define R_USB_HS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */
|
|
|
+ #define R_USB_HS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_USB_HS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */
|
|
|
+ #define R_USB_HS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */
|
|
|
+/* ======================================================= PHYTRIM1 ======================================================== */
|
|
|
+ #define R_USB_HS0_PHYTRIM1_IMPOFFSET_Pos (12UL) /*!< IMPOFFSET (Bit 12) */
|
|
|
+ #define R_USB_HS0_PHYTRIM1_IMPOFFSET_Msk (0x7000UL) /*!< IMPOFFSET (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_USB_HS0_PHYTRIM1_HSIUP_Pos (8UL) /*!< HSIUP (Bit 8) */
|
|
|
+ #define R_USB_HS0_PHYTRIM1_HSIUP_Msk (0xf00UL) /*!< HSIUP (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_USB_HS0_PHYTRIM1_PCOMPENB_Pos (7UL) /*!< PCOMPENB (Bit 7) */
|
|
|
+ #define R_USB_HS0_PHYTRIM1_PCOMPENB_Msk (0x80UL) /*!< PCOMPENB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_PHYTRIM1_DFALL_Pos (2UL) /*!< DFALL (Bit 2) */
|
|
|
+ #define R_USB_HS0_PHYTRIM1_DFALL_Msk (0xcUL) /*!< DFALL (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_USB_HS0_PHYTRIM1_DRISE_Pos (0UL) /*!< DRISE (Bit 0) */
|
|
|
+ #define R_USB_HS0_PHYTRIM1_DRISE_Msk (0x3UL) /*!< DRISE (Bitfield-Mask: 0x03) */
|
|
|
+/* ======================================================= PHYTRIM2 ======================================================== */
|
|
|
+ #define R_USB_HS0_PHYTRIM2_DIS_Pos (12UL) /*!< DIS (Bit 12) */
|
|
|
+ #define R_USB_HS0_PHYTRIM2_DIS_Msk (0x7000UL) /*!< DIS (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_USB_HS0_PHYTRIM2_PDR_Pos (8UL) /*!< PDR (Bit 8) */
|
|
|
+ #define R_USB_HS0_PHYTRIM2_PDR_Msk (0x300UL) /*!< PDR (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_USB_HS0_PHYTRIM2_HSRXENMO_Pos (7UL) /*!< HSRXENMO (Bit 7) */
|
|
|
+ #define R_USB_HS0_PHYTRIM2_HSRXENMO_Msk (0x80UL) /*!< HSRXENMO (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_PHYTRIM2_SQU_Pos (0UL) /*!< SQU (Bit 0) */
|
|
|
+ #define R_USB_HS0_PHYTRIM2_SQU_Msk (0xfUL) /*!< SQU (Bitfield-Mask: 0x0f) */
|
|
|
+/* ======================================================== DPUSR0R ======================================================== */
|
|
|
+ #define R_USB_HS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */
|
|
|
+ #define R_USB_HS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */
|
|
|
+ #define R_USB_HS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */
|
|
|
+ #define R_USB_HS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== DPUSR1R ======================================================== */
|
|
|
+ #define R_USB_HS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */
|
|
|
+ #define R_USB_HS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */
|
|
|
+ #define R_USB_HS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */
|
|
|
+ #define R_USB_HS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */
|
|
|
+ #define R_USB_HS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */
|
|
|
+ #define R_USB_HS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */
|
|
|
+ #define R_USB_HS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== DPUSR2R ======================================================== */
|
|
|
+ #define R_USB_HS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */
|
|
|
+ #define R_USB_HS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */
|
|
|
+ #define R_USB_HS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */
|
|
|
+ #define R_USB_HS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */
|
|
|
+ #define R_USB_HS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */
|
|
|
+ #define R_USB_HS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */
|
|
|
+ #define R_USB_HS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== DPUSRCR ======================================================== */
|
|
|
+ #define R_USB_HS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */
|
|
|
+ #define R_USB_HS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_USB_HS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */
|
|
|
+ #define R_USB_HS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_XSPI ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ======================================================== WRAPCFG ======================================================== */
|
|
|
+ #define R_XSPI_WRAPCFG_CKSFTCS0_Pos (0UL) /*!< CKSFTCS0 (Bit 0) */
|
|
|
+ #define R_XSPI_WRAPCFG_CKSFTCS0_Msk (0x1fUL) /*!< CKSFTCS0 (Bitfield-Mask: 0x1f) */
|
|
|
+ #define R_XSPI_WRAPCFG_DSSFTCS0_Pos (8UL) /*!< DSSFTCS0 (Bit 8) */
|
|
|
+ #define R_XSPI_WRAPCFG_DSSFTCS0_Msk (0x1f00UL) /*!< DSSFTCS0 (Bitfield-Mask: 0x1f) */
|
|
|
+ #define R_XSPI_WRAPCFG_CKSFTCS1_Pos (16UL) /*!< CKSFTCS1 (Bit 16) */
|
|
|
+ #define R_XSPI_WRAPCFG_CKSFTCS1_Msk (0x1f0000UL) /*!< CKSFTCS1 (Bitfield-Mask: 0x1f) */
|
|
|
+ #define R_XSPI_WRAPCFG_DSSFTCS1_Pos (24UL) /*!< DSSFTCS1 (Bit 24) */
|
|
|
+ #define R_XSPI_WRAPCFG_DSSFTCS1_Msk (0x1f000000UL) /*!< DSSFTCS1 (Bitfield-Mask: 0x1f) */
|
|
|
+/* ======================================================== COMCFG ========================================================= */
|
|
|
+ #define R_XSPI_COMCFG_ARBMD_Pos (0UL) /*!< ARBMD (Bit 0) */
|
|
|
+ #define R_XSPI_COMCFG_ARBMD_Msk (0x3UL) /*!< ARBMD (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_XSPI_COMCFG_ECSINTOUTEN_Pos (4UL) /*!< ECSINTOUTEN (Bit 4) */
|
|
|
+ #define R_XSPI_COMCFG_ECSINTOUTEN_Msk (0x30UL) /*!< ECSINTOUTEN (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_XSPI_COMCFG_OEASTEX_Pos (16UL) /*!< OEASTEX (Bit 16) */
|
|
|
+ #define R_XSPI_COMCFG_OEASTEX_Msk (0x10000UL) /*!< OEASTEX (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_COMCFG_OENEGEX_Pos (17UL) /*!< OENEGEX (Bit 17) */
|
|
|
+ #define R_XSPI_COMCFG_OENEGEX_Msk (0x20000UL) /*!< OENEGEX (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== BMCFGCH ======================================================== */
|
|
|
+ #define R_XSPI_BMCFGCH_WRMD_Pos (0UL) /*!< WRMD (Bit 0) */
|
|
|
+ #define R_XSPI_BMCFGCH_WRMD_Msk (0x1UL) /*!< WRMD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_BMCFGCH_MWRCOMB_Pos (7UL) /*!< MWRCOMB (Bit 7) */
|
|
|
+ #define R_XSPI_BMCFGCH_MWRCOMB_Msk (0x80UL) /*!< MWRCOMB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_BMCFGCH_MWRSIZE_Pos (8UL) /*!< MWRSIZE (Bit 8) */
|
|
|
+ #define R_XSPI_BMCFGCH_MWRSIZE_Msk (0xff00UL) /*!< MWRSIZE (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_XSPI_BMCFGCH_PREEN_Pos (16UL) /*!< PREEN (Bit 16) */
|
|
|
+ #define R_XSPI_BMCFGCH_PREEN_Msk (0x10000UL) /*!< PREEN (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_BMCFGCH_CMBTIM_Pos (24UL) /*!< CMBTIM (Bit 24) */
|
|
|
+ #define R_XSPI_BMCFGCH_CMBTIM_Msk (0xff000000UL) /*!< CMBTIM (Bitfield-Mask: 0xff) */
|
|
|
+/* ======================================================= LIOCFGCS ======================================================== */
|
|
|
+ #define R_XSPI_LIOCFGCS_PRTMD_Pos (0UL) /*!< PRTMD (Bit 0) */
|
|
|
+ #define R_XSPI_LIOCFGCS_PRTMD_Msk (0x3ffUL) /*!< PRTMD (Bitfield-Mask: 0x3ff) */
|
|
|
+ #define R_XSPI_LIOCFGCS_LATEMD_Pos (10UL) /*!< LATEMD (Bit 10) */
|
|
|
+ #define R_XSPI_LIOCFGCS_LATEMD_Msk (0x400UL) /*!< LATEMD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_LIOCFGCS_WRMSKMD_Pos (11UL) /*!< WRMSKMD (Bit 11) */
|
|
|
+ #define R_XSPI_LIOCFGCS_WRMSKMD_Msk (0x800UL) /*!< WRMSKMD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_LIOCFGCS_CSMIN_Pos (16UL) /*!< CSMIN (Bit 16) */
|
|
|
+ #define R_XSPI_LIOCFGCS_CSMIN_Msk (0xf0000UL) /*!< CSMIN (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_XSPI_LIOCFGCS_CSASTEX_Pos (20UL) /*!< CSASTEX (Bit 20) */
|
|
|
+ #define R_XSPI_LIOCFGCS_CSASTEX_Msk (0x100000UL) /*!< CSASTEX (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_LIOCFGCS_CSNEGEX_Pos (21UL) /*!< CSNEGEX (Bit 21) */
|
|
|
+ #define R_XSPI_LIOCFGCS_CSNEGEX_Msk (0x200000UL) /*!< CSNEGEX (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_LIOCFGCS_SDRDRV_Pos (22UL) /*!< SDRDRV (Bit 22) */
|
|
|
+ #define R_XSPI_LIOCFGCS_SDRDRV_Msk (0x400000UL) /*!< SDRDRV (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_LIOCFGCS_SDRSMPMD_Pos (23UL) /*!< SDRSMPMD (Bit 23) */
|
|
|
+ #define R_XSPI_LIOCFGCS_SDRSMPMD_Msk (0x800000UL) /*!< SDRSMPMD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_LIOCFGCS_SDRSMPSFT_Pos (24UL) /*!< SDRSMPSFT (Bit 24) */
|
|
|
+ #define R_XSPI_LIOCFGCS_SDRSMPSFT_Msk (0xf000000UL) /*!< SDRSMPSFT (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_XSPI_LIOCFGCS_DDRSMPEX_Pos (28UL) /*!< DDRSMPEX (Bit 28) */
|
|
|
+ #define R_XSPI_LIOCFGCS_DDRSMPEX_Msk (0xf0000000UL) /*!< DDRSMPEX (Bitfield-Mask: 0x0f) */
|
|
|
+/* ======================================================== ABMCFG ========================================================= */
|
|
|
+ #define R_XSPI_ABMCFG_ODRMD_Pos (0UL) /*!< ODRMD (Bit 0) */
|
|
|
+ #define R_XSPI_ABMCFG_ODRMD_Msk (0x3UL) /*!< ODRMD (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_XSPI_ABMCFG_CHSEL_Pos (16UL) /*!< CHSEL (Bit 16) */
|
|
|
+ #define R_XSPI_ABMCFG_CHSEL_Msk (0xffff0000UL) /*!< CHSEL (Bitfield-Mask: 0xffff) */
|
|
|
+/* ======================================================== BMCTL0 ========================================================= */
|
|
|
+ #define R_XSPI_BMCTL0_CH0CS0ACC_Pos (0UL) /*!< CH0CS0ACC (Bit 0) */
|
|
|
+ #define R_XSPI_BMCTL0_CH0CS0ACC_Msk (0x3UL) /*!< CH0CS0ACC (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_XSPI_BMCTL0_CH0CS1ACC_Pos (2UL) /*!< CH0CS1ACC (Bit 2) */
|
|
|
+ #define R_XSPI_BMCTL0_CH0CS1ACC_Msk (0xcUL) /*!< CH0CS1ACC (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_XSPI_BMCTL0_CH1CS0ACC_Pos (4UL) /*!< CH1CS0ACC (Bit 4) */
|
|
|
+ #define R_XSPI_BMCTL0_CH1CS0ACC_Msk (0x30UL) /*!< CH1CS0ACC (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_XSPI_BMCTL0_CH1CS1ACC_Pos (6UL) /*!< CH1CS1ACC (Bit 6) */
|
|
|
+ #define R_XSPI_BMCTL0_CH1CS1ACC_Msk (0xc0UL) /*!< CH1CS1ACC (Bitfield-Mask: 0x03) */
|
|
|
+/* ======================================================== BMCTL1 ========================================================= */
|
|
|
+ #define R_XSPI_BMCTL1_MWRPUSHCH_Pos (8UL) /*!< MWRPUSHCH (Bit 8) */
|
|
|
+ #define R_XSPI_BMCTL1_MWRPUSHCH_Msk (0x100UL) /*!< MWRPUSHCH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_BMCTL1_PBUFCLRCH_Pos (10UL) /*!< PBUFCLRCH (Bit 10) */
|
|
|
+ #define R_XSPI_BMCTL1_PBUFCLRCH_Msk (0x400UL) /*!< PBUFCLRCH (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== CMCTLCH ======================================================== */
|
|
|
+ #define R_XSPI_CMCTLCH_XIPENCODE_Pos (0UL) /*!< XIPENCODE (Bit 0) */
|
|
|
+ #define R_XSPI_CMCTLCH_XIPENCODE_Msk (0xffUL) /*!< XIPENCODE (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_XSPI_CMCTLCH_XIPEXCODE_Pos (8UL) /*!< XIPEXCODE (Bit 8) */
|
|
|
+ #define R_XSPI_CMCTLCH_XIPEXCODE_Msk (0xff00UL) /*!< XIPEXCODE (Bitfield-Mask: 0xff) */
|
|
|
+ #define R_XSPI_CMCTLCH_XIPEN_Pos (16UL) /*!< XIPEN (Bit 16) */
|
|
|
+ #define R_XSPI_CMCTLCH_XIPEN_Msk (0x10000UL) /*!< XIPEN (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== CDCTL0 ========================================================= */
|
|
|
+ #define R_XSPI_CDCTL0_TRREQ_Pos (0UL) /*!< TRREQ (Bit 0) */
|
|
|
+ #define R_XSPI_CDCTL0_TRREQ_Msk (0x1UL) /*!< TRREQ (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_CDCTL0_PERMD_Pos (1UL) /*!< PERMD (Bit 1) */
|
|
|
+ #define R_XSPI_CDCTL0_PERMD_Msk (0x2UL) /*!< PERMD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_CDCTL0_CSSEL_Pos (3UL) /*!< CSSEL (Bit 3) */
|
|
|
+ #define R_XSPI_CDCTL0_CSSEL_Msk (0x8UL) /*!< CSSEL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_CDCTL0_TRNUM_Pos (4UL) /*!< TRNUM (Bit 4) */
|
|
|
+ #define R_XSPI_CDCTL0_TRNUM_Msk (0x30UL) /*!< TRNUM (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_XSPI_CDCTL0_PERITV_Pos (16UL) /*!< PERITV (Bit 16) */
|
|
|
+ #define R_XSPI_CDCTL0_PERITV_Msk (0x1f0000UL) /*!< PERITV (Bitfield-Mask: 0x1f) */
|
|
|
+ #define R_XSPI_CDCTL0_PERREP_Pos (24UL) /*!< PERREP (Bit 24) */
|
|
|
+ #define R_XSPI_CDCTL0_PERREP_Msk (0xf000000UL) /*!< PERREP (Bitfield-Mask: 0x0f) */
|
|
|
+/* ======================================================== CDCTL1 ========================================================= */
|
|
|
+ #define R_XSPI_CDCTL1_PEREXP_Pos (0UL) /*!< PEREXP (Bit 0) */
|
|
|
+ #define R_XSPI_CDCTL1_PEREXP_Msk (0xffffffffUL) /*!< PEREXP (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================== CDCTL2 ========================================================= */
|
|
|
+ #define R_XSPI_CDCTL2_PERMSK_Pos (0UL) /*!< PERMSK (Bit 0) */
|
|
|
+ #define R_XSPI_CDCTL2_PERMSK_Msk (0xffffffffUL) /*!< PERMSK (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================== LPCTL0 ========================================================= */
|
|
|
+ #define R_XSPI_LPCTL0_PATREQ_Pos (0UL) /*!< PATREQ (Bit 0) */
|
|
|
+ #define R_XSPI_LPCTL0_PATREQ_Msk (0x1UL) /*!< PATREQ (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_LPCTL0_CSSEL_Pos (3UL) /*!< CSSEL (Bit 3) */
|
|
|
+ #define R_XSPI_LPCTL0_CSSEL_Msk (0x8UL) /*!< CSSEL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_LPCTL0_XDPIN_Pos (4UL) /*!< XDPIN (Bit 4) */
|
|
|
+ #define R_XSPI_LPCTL0_XDPIN_Msk (0x30UL) /*!< XDPIN (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_XSPI_LPCTL0_XD1LEN_Pos (16UL) /*!< XD1LEN (Bit 16) */
|
|
|
+ #define R_XSPI_LPCTL0_XD1LEN_Msk (0x1f0000UL) /*!< XD1LEN (Bitfield-Mask: 0x1f) */
|
|
|
+ #define R_XSPI_LPCTL0_XD1VAL_Pos (23UL) /*!< XD1VAL (Bit 23) */
|
|
|
+ #define R_XSPI_LPCTL0_XD1VAL_Msk (0x800000UL) /*!< XD1VAL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_LPCTL0_XD2LEN_Pos (24UL) /*!< XD2LEN (Bit 24) */
|
|
|
+ #define R_XSPI_LPCTL0_XD2LEN_Msk (0x1f000000UL) /*!< XD2LEN (Bitfield-Mask: 0x1f) */
|
|
|
+ #define R_XSPI_LPCTL0_XD2VAL_Pos (31UL) /*!< XD2VAL (Bit 31) */
|
|
|
+ #define R_XSPI_LPCTL0_XD2VAL_Msk (0x80000000UL) /*!< XD2VAL (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== LPCTL1 ========================================================= */
|
|
|
+ #define R_XSPI_LPCTL1_PATREQ_Pos (0UL) /*!< PATREQ (Bit 0) */
|
|
|
+ #define R_XSPI_LPCTL1_PATREQ_Msk (0x3UL) /*!< PATREQ (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_XSPI_LPCTL1_CSSEL_Pos (3UL) /*!< CSSEL (Bit 3) */
|
|
|
+ #define R_XSPI_LPCTL1_CSSEL_Msk (0x8UL) /*!< CSSEL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_LPCTL1_RSTREP_Pos (4UL) /*!< RSTREP (Bit 4) */
|
|
|
+ #define R_XSPI_LPCTL1_RSTREP_Msk (0x30UL) /*!< RSTREP (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_XSPI_LPCTL1_RSTWID_Pos (8UL) /*!< RSTWID (Bit 8) */
|
|
|
+ #define R_XSPI_LPCTL1_RSTWID_Msk (0x700UL) /*!< RSTWID (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_XSPI_LPCTL1_RSTSU_Pos (12UL) /*!< RSTSU (Bit 12) */
|
|
|
+ #define R_XSPI_LPCTL1_RSTSU_Msk (0x7000UL) /*!< RSTSU (Bitfield-Mask: 0x07) */
|
|
|
+/* ======================================================== LIOCTL ========================================================= */
|
|
|
+ #define R_XSPI_LIOCTL_WPCS_Pos (0UL) /*!< WPCS (Bit 0) */
|
|
|
+ #define R_XSPI_LIOCTL_WPCS_Msk (0x1UL) /*!< WPCS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_LIOCTL_RSTCS_Pos (16UL) /*!< RSTCS (Bit 16) */
|
|
|
+ #define R_XSPI_LIOCTL_RSTCS_Msk (0x10000UL) /*!< RSTCS (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== VERSTT ========================================================= */
|
|
|
+ #define R_XSPI_VERSTT_VER_Pos (0UL) /*!< VER (Bit 0) */
|
|
|
+ #define R_XSPI_VERSTT_VER_Msk (0xffffffffUL) /*!< VER (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================== COMSTT ========================================================= */
|
|
|
+ #define R_XSPI_COMSTT_MEMACCCH_Pos (0UL) /*!< MEMACCCH (Bit 0) */
|
|
|
+ #define R_XSPI_COMSTT_MEMACCCH_Msk (0x1UL) /*!< MEMACCCH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_COMSTT_PBUFNECH_Pos (4UL) /*!< PBUFNECH (Bit 4) */
|
|
|
+ #define R_XSPI_COMSTT_PBUFNECH_Msk (0x10UL) /*!< PBUFNECH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_COMSTT_WRBUFNECH_Pos (6UL) /*!< WRBUFNECH (Bit 6) */
|
|
|
+ #define R_XSPI_COMSTT_WRBUFNECH_Msk (0x40UL) /*!< WRBUFNECH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_COMSTT_ECSCS_Pos (16UL) /*!< ECSCS (Bit 16) */
|
|
|
+ #define R_XSPI_COMSTT_ECSCS_Msk (0x10000UL) /*!< ECSCS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_COMSTT_INTCS_Pos (17UL) /*!< INTCS (Bit 17) */
|
|
|
+ #define R_XSPI_COMSTT_INTCS_Msk (0x20000UL) /*!< INTCS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_COMSTT_RSTOCS_Pos (18UL) /*!< RSTOCS (Bit 18) */
|
|
|
+ #define R_XSPI_COMSTT_RSTOCS_Msk (0x40000UL) /*!< RSTOCS (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== CASTTCS ======================================================== */
|
|
|
+ #define R_XSPI_CASTTCS_CASUC_Pos (0UL) /*!< CASUC (Bit 0) */
|
|
|
+ #define R_XSPI_CASTTCS_CASUC_Msk (0xffffffffUL) /*!< CASUC (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ========================================================= INTS ========================================================== */
|
|
|
+ #define R_XSPI_INTS_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */
|
|
|
+ #define R_XSPI_INTS_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_INTS_PATCMP_Pos (1UL) /*!< PATCMP (Bit 1) */
|
|
|
+ #define R_XSPI_INTS_PATCMP_Msk (0x2UL) /*!< PATCMP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_INTS_INICMP_Pos (2UL) /*!< INICMP (Bit 2) */
|
|
|
+ #define R_XSPI_INTS_INICMP_Msk (0x4UL) /*!< INICMP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_INTS_PERTO_Pos (3UL) /*!< PERTO (Bit 3) */
|
|
|
+ #define R_XSPI_INTS_PERTO_Msk (0x8UL) /*!< PERTO (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_INTS_DSTOCS_Pos (4UL) /*!< DSTOCS (Bit 4) */
|
|
|
+ #define R_XSPI_INTS_DSTOCS_Msk (0x10UL) /*!< DSTOCS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_INTS_ECSCS_Pos (8UL) /*!< ECSCS (Bit 8) */
|
|
|
+ #define R_XSPI_INTS_ECSCS_Msk (0x100UL) /*!< ECSCS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_INTS_INTCS_Pos (12UL) /*!< INTCS (Bit 12) */
|
|
|
+ #define R_XSPI_INTS_INTCS_Msk (0x1000UL) /*!< INTCS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_INTS_BRGOFCH_Pos (16UL) /*!< BRGOFCH (Bit 16) */
|
|
|
+ #define R_XSPI_INTS_BRGOFCH_Msk (0x10000UL) /*!< BRGOFCH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_INTS_BRGUFCH_Pos (18UL) /*!< BRGUFCH (Bit 18) */
|
|
|
+ #define R_XSPI_INTS_BRGUFCH_Msk (0x40000UL) /*!< BRGUFCH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_INTS_BUSERRCH_Pos (20UL) /*!< BUSERRCH (Bit 20) */
|
|
|
+ #define R_XSPI_INTS_BUSERRCH_Msk (0x100000UL) /*!< BUSERRCH (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_INTS_CAFAILCS_Pos (28UL) /*!< CAFAILCS (Bit 28) */
|
|
|
+ #define R_XSPI_INTS_CAFAILCS_Msk (0x10000000UL) /*!< CAFAILCS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_INTS_CASUCCS_Pos (30UL) /*!< CASUCCS (Bit 30) */
|
|
|
+ #define R_XSPI_INTS_CASUCCS_Msk (0x40000000UL) /*!< CASUCCS (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= INTC ========================================================== */
|
|
|
+ #define R_XSPI_INTC_CMDCMPC_Pos (0UL) /*!< CMDCMPC (Bit 0) */
|
|
|
+ #define R_XSPI_INTC_CMDCMPC_Msk (0x1UL) /*!< CMDCMPC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_INTC_PATCMPC_Pos (1UL) /*!< PATCMPC (Bit 1) */
|
|
|
+ #define R_XSPI_INTC_PATCMPC_Msk (0x2UL) /*!< PATCMPC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_INTC_INICMPC_Pos (2UL) /*!< INICMPC (Bit 2) */
|
|
|
+ #define R_XSPI_INTC_INICMPC_Msk (0x4UL) /*!< INICMPC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_INTC_PERTOC_Pos (3UL) /*!< PERTOC (Bit 3) */
|
|
|
+ #define R_XSPI_INTC_PERTOC_Msk (0x8UL) /*!< PERTOC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_INTC_DSTOCSC_Pos (4UL) /*!< DSTOCSC (Bit 4) */
|
|
|
+ #define R_XSPI_INTC_DSTOCSC_Msk (0x10UL) /*!< DSTOCSC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_INTC_ECSCSC_Pos (8UL) /*!< ECSCSC (Bit 8) */
|
|
|
+ #define R_XSPI_INTC_ECSCSC_Msk (0x100UL) /*!< ECSCSC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_INTC_INTCSC_Pos (12UL) /*!< INTCSC (Bit 12) */
|
|
|
+ #define R_XSPI_INTC_INTCSC_Msk (0x1000UL) /*!< INTCSC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_INTC_BRGOFCHC_Pos (16UL) /*!< BRGOFCHC (Bit 16) */
|
|
|
+ #define R_XSPI_INTC_BRGOFCHC_Msk (0x10000UL) /*!< BRGOFCHC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_INTC_BRGUFCHC_Pos (18UL) /*!< BRGUFCHC (Bit 18) */
|
|
|
+ #define R_XSPI_INTC_BRGUFCHC_Msk (0x40000UL) /*!< BRGUFCHC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_INTC_BUSERRCHC_Pos (20UL) /*!< BUSERRCHC (Bit 20) */
|
|
|
+ #define R_XSPI_INTC_BUSERRCHC_Msk (0x100000UL) /*!< BUSERRCHC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_INTC_CAFAILCSC_Pos (28UL) /*!< CAFAILCSC (Bit 28) */
|
|
|
+ #define R_XSPI_INTC_CAFAILCSC_Msk (0x10000000UL) /*!< CAFAILCSC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_INTC_CASUCCSC_Pos (30UL) /*!< CASUCCSC (Bit 30) */
|
|
|
+ #define R_XSPI_INTC_CASUCCSC_Msk (0x40000000UL) /*!< CASUCCSC (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= INTE ========================================================== */
|
|
|
+ #define R_XSPI_INTE_CMDCMPE_Pos (0UL) /*!< CMDCMPE (Bit 0) */
|
|
|
+ #define R_XSPI_INTE_CMDCMPE_Msk (0x1UL) /*!< CMDCMPE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_INTE_PATCMPE_Pos (1UL) /*!< PATCMPE (Bit 1) */
|
|
|
+ #define R_XSPI_INTE_PATCMPE_Msk (0x2UL) /*!< PATCMPE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_INTE_INICMPE_Pos (2UL) /*!< INICMPE (Bit 2) */
|
|
|
+ #define R_XSPI_INTE_INICMPE_Msk (0x4UL) /*!< INICMPE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_INTE_PERTOE_Pos (3UL) /*!< PERTOE (Bit 3) */
|
|
|
+ #define R_XSPI_INTE_PERTOE_Msk (0x8UL) /*!< PERTOE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_INTE_DSTOCSE_Pos (4UL) /*!< DSTOCSE (Bit 4) */
|
|
|
+ #define R_XSPI_INTE_DSTOCSE_Msk (0x10UL) /*!< DSTOCSE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_INTE_ECSCSE_Pos (8UL) /*!< ECSCSE (Bit 8) */
|
|
|
+ #define R_XSPI_INTE_ECSCSE_Msk (0x100UL) /*!< ECSCSE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_INTE_INTCSE_Pos (12UL) /*!< INTCSE (Bit 12) */
|
|
|
+ #define R_XSPI_INTE_INTCSE_Msk (0x1000UL) /*!< INTCSE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_INTE_BRGOFCHE_Pos (16UL) /*!< BRGOFCHE (Bit 16) */
|
|
|
+ #define R_XSPI_INTE_BRGOFCHE_Msk (0x10000UL) /*!< BRGOFCHE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_INTE_BRGUFCHE_Pos (18UL) /*!< BRGUFCHE (Bit 18) */
|
|
|
+ #define R_XSPI_INTE_BRGUFCHE_Msk (0x40000UL) /*!< BRGUFCHE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_INTE_BUSERRCHE_Pos (20UL) /*!< BUSERRCHE (Bit 20) */
|
|
|
+ #define R_XSPI_INTE_BUSERRCHE_Msk (0x100000UL) /*!< BUSERRCHE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_INTE_CAFAILCSE_Pos (28UL) /*!< CAFAILCSE (Bit 28) */
|
|
|
+ #define R_XSPI_INTE_CAFAILCSE_Msk (0x10000000UL) /*!< CAFAILCSE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_XSPI_INTE_CASUCCSE_Pos (30UL) /*!< CASUCCSE (Bit 30) */
|
|
|
+ #define R_XSPI_INTE_CASUCCSE_Msk (0x40000000UL) /*!< CASUCCSE (Bitfield-Mask: 0x01) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_CEU ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ========================================================= CAPSR ========================================================= */
|
|
|
+ #define R_CEU_CAPSR_CE_Pos (0UL) /*!< CE (Bit 0) */
|
|
|
+ #define R_CEU_CAPSR_CE_Msk (0x1UL) /*!< CE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CAPSR_CPKIL_Pos (16UL) /*!< CPKIL (Bit 16) */
|
|
|
+ #define R_CEU_CAPSR_CPKIL_Msk (0x10000UL) /*!< CPKIL (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= CAPCR ========================================================= */
|
|
|
+ #define R_CEU_CAPCR_CTNCP_Pos (16UL) /*!< CTNCP (Bit 16) */
|
|
|
+ #define R_CEU_CAPCR_CTNCP_Msk (0x10000UL) /*!< CTNCP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CAPCR_MTCM_Pos (20UL) /*!< MTCM (Bit 20) */
|
|
|
+ #define R_CEU_CAPCR_MTCM_Msk (0x300000UL) /*!< MTCM (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_CEU_CAPCR_FDRP_Pos (24UL) /*!< FDRP (Bit 24) */
|
|
|
+ #define R_CEU_CAPCR_FDRP_Msk (0xff000000UL) /*!< FDRP (Bitfield-Mask: 0xff) */
|
|
|
+/* ========================================================= CAMCR ========================================================= */
|
|
|
+ #define R_CEU_CAMCR_HDPOL_Pos (0UL) /*!< HDPOL (Bit 0) */
|
|
|
+ #define R_CEU_CAMCR_HDPOL_Msk (0x1UL) /*!< HDPOL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CAMCR_VDPOL_Pos (1UL) /*!< VDPOL (Bit 1) */
|
|
|
+ #define R_CEU_CAMCR_VDPOL_Msk (0x2UL) /*!< VDPOL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CAMCR_JPG_Pos (4UL) /*!< JPG (Bit 4) */
|
|
|
+ #define R_CEU_CAMCR_JPG_Msk (0x30UL) /*!< JPG (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_CEU_CAMCR_DTARY_Pos (8UL) /*!< DTARY (Bit 8) */
|
|
|
+ #define R_CEU_CAMCR_DTARY_Msk (0x300UL) /*!< DTARY (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_CEU_CAMCR_DTIF_Pos (12UL) /*!< DTIF (Bit 12) */
|
|
|
+ #define R_CEU_CAMCR_DTIF_Msk (0x1000UL) /*!< DTIF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CAMCR_FLDPOL_Pos (16UL) /*!< FLDPOL (Bit 16) */
|
|
|
+ #define R_CEU_CAMCR_FLDPOL_Msk (0x10000UL) /*!< FLDPOL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CAMCR_DSEL_Pos (24UL) /*!< DSEL (Bit 24) */
|
|
|
+ #define R_CEU_CAMCR_DSEL_Msk (0x1000000UL) /*!< DSEL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CAMCR_FLDSEL_Pos (25UL) /*!< FLDSEL (Bit 25) */
|
|
|
+ #define R_CEU_CAMCR_FLDSEL_Msk (0x2000000UL) /*!< FLDSEL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CAMCR_HDSEL_Pos (26UL) /*!< HDSEL (Bit 26) */
|
|
|
+ #define R_CEU_CAMCR_HDSEL_Msk (0x4000000UL) /*!< HDSEL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CAMCR_VDSEL_Pos (27UL) /*!< VDSEL (Bit 27) */
|
|
|
+ #define R_CEU_CAMCR_VDSEL_Msk (0x8000000UL) /*!< VDSEL (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= CMCYR ========================================================= */
|
|
|
+ #define R_CEU_CMCYR_HCYL_Pos (0UL) /*!< HCYL (Bit 0) */
|
|
|
+ #define R_CEU_CMCYR_HCYL_Msk (0x3fffUL) /*!< HCYL (Bitfield-Mask: 0x3fff) */
|
|
|
+ #define R_CEU_CMCYR_VCYL_Pos (16UL) /*!< VCYL (Bit 16) */
|
|
|
+ #define R_CEU_CMCYR_VCYL_Msk (0x3fff0000UL) /*!< VCYL (Bitfield-Mask: 0x3fff) */
|
|
|
+/* ========================================================= CAMOR ========================================================= */
|
|
|
+ #define R_CEU_CAMOR_HOFST_Pos (0UL) /*!< HOFST (Bit 0) */
|
|
|
+ #define R_CEU_CAMOR_HOFST_Msk (0x1fffUL) /*!< HOFST (Bitfield-Mask: 0x1fff) */
|
|
|
+ #define R_CEU_CAMOR_VOFST_Pos (16UL) /*!< VOFST (Bit 16) */
|
|
|
+ #define R_CEU_CAMOR_VOFST_Msk (0xfff0000UL) /*!< VOFST (Bitfield-Mask: 0xfff) */
|
|
|
+/* ========================================================= CAPWR ========================================================= */
|
|
|
+ #define R_CEU_CAPWR_HWDTH_Pos (0UL) /*!< HWDTH (Bit 0) */
|
|
|
+ #define R_CEU_CAPWR_HWDTH_Msk (0x1fffUL) /*!< HWDTH (Bitfield-Mask: 0x1fff) */
|
|
|
+ #define R_CEU_CAPWR_VWDTH_Pos (16UL) /*!< VWDTH (Bit 16) */
|
|
|
+ #define R_CEU_CAPWR_VWDTH_Msk (0xfff0000UL) /*!< VWDTH (Bitfield-Mask: 0xfff) */
|
|
|
+/* ========================================================= CAIFR ========================================================= */
|
|
|
+ #define R_CEU_CAIFR_FCI_Pos (0UL) /*!< FCI (Bit 0) */
|
|
|
+ #define R_CEU_CAIFR_FCI_Msk (0x3UL) /*!< FCI (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_CEU_CAIFR_CIM_Pos (4UL) /*!< CIM (Bit 4) */
|
|
|
+ #define R_CEU_CAIFR_CIM_Msk (0x10UL) /*!< CIM (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CAIFR_IFS_Pos (8UL) /*!< IFS (Bit 8) */
|
|
|
+ #define R_CEU_CAIFR_IFS_Msk (0x100UL) /*!< IFS (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== CRCNTR ========================================================= */
|
|
|
+ #define R_CEU_CRCNTR_RC_Pos (0UL) /*!< RC (Bit 0) */
|
|
|
+ #define R_CEU_CRCNTR_RC_Msk (0x1UL) /*!< RC (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CRCNTR_RS_Pos (1UL) /*!< RS (Bit 1) */
|
|
|
+ #define R_CEU_CRCNTR_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CRCNTR_RVS_Pos (4UL) /*!< RVS (Bit 4) */
|
|
|
+ #define R_CEU_CRCNTR_RVS_Msk (0x10UL) /*!< RVS (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== CRCMPR ========================================================= */
|
|
|
+ #define R_CEU_CRCMPR_RA_Pos (0UL) /*!< RA (Bit 0) */
|
|
|
+ #define R_CEU_CRCMPR_RA_Msk (0x1UL) /*!< RA (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= CFLCR ========================================================= */
|
|
|
+ #define R_CEU_CFLCR_HFRAC_Pos (0UL) /*!< HFRAC (Bit 0) */
|
|
|
+ #define R_CEU_CFLCR_HFRAC_Msk (0xfffUL) /*!< HFRAC (Bitfield-Mask: 0xfff) */
|
|
|
+ #define R_CEU_CFLCR_HMANT_Pos (12UL) /*!< HMANT (Bit 12) */
|
|
|
+ #define R_CEU_CFLCR_HMANT_Msk (0xf000UL) /*!< HMANT (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_CEU_CFLCR_VFRAC_Pos (16UL) /*!< VFRAC (Bit 16) */
|
|
|
+ #define R_CEU_CFLCR_VFRAC_Msk (0xfff0000UL) /*!< VFRAC (Bitfield-Mask: 0xfff) */
|
|
|
+ #define R_CEU_CFLCR_VMANT_Pos (28UL) /*!< VMANT (Bit 28) */
|
|
|
+ #define R_CEU_CFLCR_VMANT_Msk (0xf0000000UL) /*!< VMANT (Bitfield-Mask: 0x0f) */
|
|
|
+/* ========================================================= CFSZR ========================================================= */
|
|
|
+ #define R_CEU_CFSZR_HFCLP_Pos (0UL) /*!< HFCLP (Bit 0) */
|
|
|
+ #define R_CEU_CFSZR_HFCLP_Msk (0xfffUL) /*!< HFCLP (Bitfield-Mask: 0xfff) */
|
|
|
+ #define R_CEU_CFSZR_VFCLP_Pos (16UL) /*!< VFCLP (Bit 16) */
|
|
|
+ #define R_CEU_CFSZR_VFCLP_Msk (0xfff0000UL) /*!< VFCLP (Bitfield-Mask: 0xfff) */
|
|
|
+/* ========================================================= CDWDR ========================================================= */
|
|
|
+ #define R_CEU_CDWDR_CHDW_Pos (0UL) /*!< CHDW (Bit 0) */
|
|
|
+ #define R_CEU_CDWDR_CHDW_Msk (0x1fffUL) /*!< CHDW (Bitfield-Mask: 0x1fff) */
|
|
|
+/* ========================================================= CDAYR ========================================================= */
|
|
|
+ #define R_CEU_CDAYR_CAYR_Pos (0UL) /*!< CAYR (Bit 0) */
|
|
|
+ #define R_CEU_CDAYR_CAYR_Msk (0xffffffffUL) /*!< CAYR (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ========================================================= CDACR ========================================================= */
|
|
|
+ #define R_CEU_CDACR_CACR_Pos (0UL) /*!< CACR (Bit 0) */
|
|
|
+ #define R_CEU_CDACR_CACR_Msk (0xffffffffUL) /*!< CACR (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ========================================================= CDBYR ========================================================= */
|
|
|
+ #define R_CEU_CDBYR_CBYR_Pos (0UL) /*!< CBYR (Bit 0) */
|
|
|
+ #define R_CEU_CDBYR_CBYR_Msk (0xffffffffUL) /*!< CBYR (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ========================================================= CDBCR ========================================================= */
|
|
|
+ #define R_CEU_CDBCR_CBCR_Pos (0UL) /*!< CBCR (Bit 0) */
|
|
|
+ #define R_CEU_CDBCR_CBCR_Msk (0xffffffffUL) /*!< CBCR (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ========================================================= CBDSR ========================================================= */
|
|
|
+ #define R_CEU_CBDSR_CBVS_Pos (0UL) /*!< CBVS (Bit 0) */
|
|
|
+ #define R_CEU_CBDSR_CBVS_Msk (0x7fffffUL) /*!< CBVS (Bitfield-Mask: 0x7fffff) */
|
|
|
+/* ========================================================= CFWCR ========================================================= */
|
|
|
+ #define R_CEU_CFWCR_FWE_Pos (0UL) /*!< FWE (Bit 0) */
|
|
|
+ #define R_CEU_CFWCR_FWE_Msk (0x1UL) /*!< FWE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CFWCR_FWV_Pos (5UL) /*!< FWV (Bit 5) */
|
|
|
+ #define R_CEU_CFWCR_FWV_Msk (0xffffffe0UL) /*!< FWV (Bitfield-Mask: 0x7ffffff) */
|
|
|
+/* ========================================================= CLFCR ========================================================= */
|
|
|
+ #define R_CEU_CLFCR_LPF_Pos (0UL) /*!< LPF (Bit 0) */
|
|
|
+ #define R_CEU_CLFCR_LPF_Msk (0x1UL) /*!< LPF (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= CDOCR ========================================================= */
|
|
|
+ #define R_CEU_CDOCR_COBS_Pos (0UL) /*!< COBS (Bit 0) */
|
|
|
+ #define R_CEU_CDOCR_COBS_Msk (0x1UL) /*!< COBS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CDOCR_COWS_Pos (1UL) /*!< COWS (Bit 1) */
|
|
|
+ #define R_CEU_CDOCR_COWS_Msk (0x2UL) /*!< COWS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CDOCR_COLS_Pos (2UL) /*!< COLS (Bit 2) */
|
|
|
+ #define R_CEU_CDOCR_COLS_Msk (0x4UL) /*!< COLS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CDOCR_CDS_Pos (4UL) /*!< CDS (Bit 4) */
|
|
|
+ #define R_CEU_CDOCR_CDS_Msk (0x10UL) /*!< CDS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CDOCR_CBE_Pos (16UL) /*!< CBE (Bit 16) */
|
|
|
+ #define R_CEU_CDOCR_CBE_Msk (0x10000UL) /*!< CBE (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= CEIER ========================================================= */
|
|
|
+ #define R_CEU_CEIER_CPEIE_Pos (0UL) /*!< CPEIE (Bit 0) */
|
|
|
+ #define R_CEU_CEIER_CPEIE_Msk (0x1UL) /*!< CPEIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CEIER_CFEIE_Pos (1UL) /*!< CFEIE (Bit 1) */
|
|
|
+ #define R_CEU_CEIER_CFEIE_Msk (0x2UL) /*!< CFEIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CEIER_IGRWIE_Pos (4UL) /*!< IGRWIE (Bit 4) */
|
|
|
+ #define R_CEU_CEIER_IGRWIE_Msk (0x10UL) /*!< IGRWIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CEIER_HDIE_Pos (8UL) /*!< HDIE (Bit 8) */
|
|
|
+ #define R_CEU_CEIER_HDIE_Msk (0x100UL) /*!< HDIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CEIER_VDIE_Pos (9UL) /*!< VDIE (Bit 9) */
|
|
|
+ #define R_CEU_CEIER_VDIE_Msk (0x200UL) /*!< VDIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CEIER_CPBE1IE_Pos (12UL) /*!< CPBE1IE (Bit 12) */
|
|
|
+ #define R_CEU_CEIER_CPBE1IE_Msk (0x1000UL) /*!< CPBE1IE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CEIER_CPBE2IE_Pos (13UL) /*!< CPBE2IE (Bit 13) */
|
|
|
+ #define R_CEU_CEIER_CPBE2IE_Msk (0x2000UL) /*!< CPBE2IE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CEIER_CPBE3IE_Pos (14UL) /*!< CPBE3IE (Bit 14) */
|
|
|
+ #define R_CEU_CEIER_CPBE3IE_Msk (0x4000UL) /*!< CPBE3IE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CEIER_CPBE4IE_Pos (15UL) /*!< CPBE4IE (Bit 15) */
|
|
|
+ #define R_CEU_CEIER_CPBE4IE_Msk (0x8000UL) /*!< CPBE4IE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CEIER_CDTOFIE_Pos (16UL) /*!< CDTOFIE (Bit 16) */
|
|
|
+ #define R_CEU_CEIER_CDTOFIE_Msk (0x10000UL) /*!< CDTOFIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CEIER_IGHSIE_Pos (17UL) /*!< IGHSIE (Bit 17) */
|
|
|
+ #define R_CEU_CEIER_IGHSIE_Msk (0x20000UL) /*!< IGHSIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CEIER_IGVSIE_Pos (18UL) /*!< IGVSIE (Bit 18) */
|
|
|
+ #define R_CEU_CEIER_IGVSIE_Msk (0x40000UL) /*!< IGVSIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CEIER_VBPIE_Pos (20UL) /*!< VBPIE (Bit 20) */
|
|
|
+ #define R_CEU_CEIER_VBPIE_Msk (0x100000UL) /*!< VBPIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CEIER_FWFIE_Pos (23UL) /*!< FWFIE (Bit 23) */
|
|
|
+ #define R_CEU_CEIER_FWFIE_Msk (0x800000UL) /*!< FWFIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CEIER_NHDIE_Pos (24UL) /*!< NHDIE (Bit 24) */
|
|
|
+ #define R_CEU_CEIER_NHDIE_Msk (0x1000000UL) /*!< NHDIE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CEIER_NVDIE_Pos (25UL) /*!< NVDIE (Bit 25) */
|
|
|
+ #define R_CEU_CEIER_NVDIE_Msk (0x2000000UL) /*!< NVDIE (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= CETCR ========================================================= */
|
|
|
+ #define R_CEU_CETCR_CPE_Pos (0UL) /*!< CPE (Bit 0) */
|
|
|
+ #define R_CEU_CETCR_CPE_Msk (0x1UL) /*!< CPE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CETCR_CFE_Pos (1UL) /*!< CFE (Bit 1) */
|
|
|
+ #define R_CEU_CETCR_CFE_Msk (0x2UL) /*!< CFE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CETCR_IGRW_Pos (4UL) /*!< IGRW (Bit 4) */
|
|
|
+ #define R_CEU_CETCR_IGRW_Msk (0x10UL) /*!< IGRW (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CETCR_HD_Pos (8UL) /*!< HD (Bit 8) */
|
|
|
+ #define R_CEU_CETCR_HD_Msk (0x100UL) /*!< HD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CETCR_VD_Pos (9UL) /*!< VD (Bit 9) */
|
|
|
+ #define R_CEU_CETCR_VD_Msk (0x200UL) /*!< VD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CETCR_CPBE1_Pos (12UL) /*!< CPBE1 (Bit 12) */
|
|
|
+ #define R_CEU_CETCR_CPBE1_Msk (0x1000UL) /*!< CPBE1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CETCR_CPBE2_Pos (13UL) /*!< CPBE2 (Bit 13) */
|
|
|
+ #define R_CEU_CETCR_CPBE2_Msk (0x2000UL) /*!< CPBE2 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CETCR_CPBE3_Pos (14UL) /*!< CPBE3 (Bit 14) */
|
|
|
+ #define R_CEU_CETCR_CPBE3_Msk (0x4000UL) /*!< CPBE3 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CETCR_CPBE4_Pos (15UL) /*!< CPBE4 (Bit 15) */
|
|
|
+ #define R_CEU_CETCR_CPBE4_Msk (0x8000UL) /*!< CPBE4 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CETCR_CDTOF_Pos (16UL) /*!< CDTOF (Bit 16) */
|
|
|
+ #define R_CEU_CETCR_CDTOF_Msk (0x10000UL) /*!< CDTOF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CETCR_IGHS_Pos (17UL) /*!< IGHS (Bit 17) */
|
|
|
+ #define R_CEU_CETCR_IGHS_Msk (0x20000UL) /*!< IGHS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CETCR_IGVS_Pos (18UL) /*!< IGVS (Bit 18) */
|
|
|
+ #define R_CEU_CETCR_IGVS_Msk (0x40000UL) /*!< IGVS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CETCR_VBP_Pos (20UL) /*!< VBP (Bit 20) */
|
|
|
+ #define R_CEU_CETCR_VBP_Msk (0x100000UL) /*!< VBP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CETCR_FWF_Pos (23UL) /*!< FWF (Bit 23) */
|
|
|
+ #define R_CEU_CETCR_FWF_Msk (0x800000UL) /*!< FWF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CETCR_NHD_Pos (24UL) /*!< NHD (Bit 24) */
|
|
|
+ #define R_CEU_CETCR_NHD_Msk (0x1000000UL) /*!< NHD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CETCR_NVD_Pos (25UL) /*!< NVD (Bit 25) */
|
|
|
+ #define R_CEU_CETCR_NVD_Msk (0x2000000UL) /*!< NVD (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= CSTSR ========================================================= */
|
|
|
+ #define R_CEU_CSTSR_CPTON_Pos (0UL) /*!< CPTON (Bit 0) */
|
|
|
+ #define R_CEU_CSTSR_CPTON_Msk (0x1UL) /*!< CPTON (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CSTSR_CPFLD_Pos (16UL) /*!< CPFLD (Bit 16) */
|
|
|
+ #define R_CEU_CSTSR_CPFLD_Msk (0x10000UL) /*!< CPFLD (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CSTSR_CRST_Pos (24UL) /*!< CRST (Bit 24) */
|
|
|
+ #define R_CEU_CSTSR_CRST_Msk (0x1000000UL) /*!< CRST (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= CDSSR ========================================================= */
|
|
|
+ #define R_CEU_CDSSR_CDSS_Pos (0UL) /*!< CDSS (Bit 0) */
|
|
|
+ #define R_CEU_CDSSR_CDSS_Msk (0xffffffffUL) /*!< CDSS (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================== CDAYR2 ========================================================= */
|
|
|
+ #define R_CEU_CDAYR2_CAYR2_Pos (0UL) /*!< CAYR2 (Bit 0) */
|
|
|
+ #define R_CEU_CDAYR2_CAYR2_Msk (0xffffffffUL) /*!< CAYR2 (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================== CDACR2 ========================================================= */
|
|
|
+ #define R_CEU_CDACR2_CACR2_Pos (0UL) /*!< CACR2 (Bit 0) */
|
|
|
+ #define R_CEU_CDACR2_CACR2_Msk (0xffffffffUL) /*!< CACR2 (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================== CDBYR2 ========================================================= */
|
|
|
+ #define R_CEU_CDBYR2_CBYR2_Pos (0UL) /*!< CBYR2 (Bit 0) */
|
|
|
+ #define R_CEU_CDBYR2_CBYR2_Msk (0xffffffffUL) /*!< CBYR2 (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================== CDBCR2 ========================================================= */
|
|
|
+ #define R_CEU_CDBCR2_CBCR2_Pos (0UL) /*!< CBCR2 (Bit 0) */
|
|
|
+ #define R_CEU_CDBCR2_CBCR2_Msk (0xffffffffUL) /*!< CBCR2 (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ====================================================== AXIBUSCTL2 ======================================================= */
|
|
|
+ #define R_CEU_AXIBUSCTL2_AWCACHE_Pos (0UL) /*!< AWCACHE (Bit 0) */
|
|
|
+ #define R_CEU_AXIBUSCTL2_AWCACHE_Msk (0xfUL) /*!< AWCACHE (Bitfield-Mask: 0x0f) */
|
|
|
+/* ======================================================== CAMOR_B ======================================================== */
|
|
|
+ #define R_CEU_CAMOR_B_HOFST_Pos (0UL) /*!< HOFST (Bit 0) */
|
|
|
+ #define R_CEU_CAMOR_B_HOFST_Msk (0x1fffUL) /*!< HOFST (Bitfield-Mask: 0x1fff) */
|
|
|
+ #define R_CEU_CAMOR_B_VOFST_Pos (16UL) /*!< VOFST (Bit 16) */
|
|
|
+ #define R_CEU_CAMOR_B_VOFST_Msk (0xfff0000UL) /*!< VOFST (Bitfield-Mask: 0xfff) */
|
|
|
+/* ======================================================== CAPWR_B ======================================================== */
|
|
|
+ #define R_CEU_CAPWR_B_HWDTH_Pos (0UL) /*!< HWDTH (Bit 0) */
|
|
|
+ #define R_CEU_CAPWR_B_HWDTH_Msk (0x1fffUL) /*!< HWDTH (Bitfield-Mask: 0x1fff) */
|
|
|
+ #define R_CEU_CAPWR_B_VWDTH_Pos (16UL) /*!< VWDTH (Bit 16) */
|
|
|
+ #define R_CEU_CAPWR_B_VWDTH_Msk (0xfff0000UL) /*!< VWDTH (Bitfield-Mask: 0xfff) */
|
|
|
+/* ======================================================== CFLCR_B ======================================================== */
|
|
|
+ #define R_CEU_CFLCR_B_HFRAC_Pos (0UL) /*!< HFRAC (Bit 0) */
|
|
|
+ #define R_CEU_CFLCR_B_HFRAC_Msk (0xfffUL) /*!< HFRAC (Bitfield-Mask: 0xfff) */
|
|
|
+ #define R_CEU_CFLCR_B_HMANT_Pos (12UL) /*!< HMANT (Bit 12) */
|
|
|
+ #define R_CEU_CFLCR_B_HMANT_Msk (0xf000UL) /*!< HMANT (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_CEU_CFLCR_B_VFRAC_Pos (16UL) /*!< VFRAC (Bit 16) */
|
|
|
+ #define R_CEU_CFLCR_B_VFRAC_Msk (0xfff0000UL) /*!< VFRAC (Bitfield-Mask: 0xfff) */
|
|
|
+ #define R_CEU_CFLCR_B_VMANT_Pos (28UL) /*!< VMANT (Bit 28) */
|
|
|
+ #define R_CEU_CFLCR_B_VMANT_Msk (0xf0000000UL) /*!< VMANT (Bitfield-Mask: 0x0f) */
|
|
|
+/* ======================================================== CFSZR_B ======================================================== */
|
|
|
+ #define R_CEU_CFSZR_B_HFCLP_Pos (0UL) /*!< HFCLP (Bit 0) */
|
|
|
+ #define R_CEU_CFSZR_B_HFCLP_Msk (0xfffUL) /*!< HFCLP (Bitfield-Mask: 0xfff) */
|
|
|
+ #define R_CEU_CFSZR_B_VFCLP_Pos (16UL) /*!< VFCLP (Bit 16) */
|
|
|
+ #define R_CEU_CFSZR_B_VFCLP_Msk (0xfff0000UL) /*!< VFCLP (Bitfield-Mask: 0xfff) */
|
|
|
+/* ======================================================== CDWDR_B ======================================================== */
|
|
|
+ #define R_CEU_CDWDR_B_CHDW_Pos (0UL) /*!< CHDW (Bit 0) */
|
|
|
+ #define R_CEU_CDWDR_B_CHDW_Msk (0x1fffUL) /*!< CHDW (Bitfield-Mask: 0x1fff) */
|
|
|
+/* ======================================================== CDAYR_B ======================================================== */
|
|
|
+ #define R_CEU_CDAYR_B_CAYR_Pos (0UL) /*!< CAYR (Bit 0) */
|
|
|
+ #define R_CEU_CDAYR_B_CAYR_Msk (0xffffffffUL) /*!< CAYR (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================== CDACR_B ======================================================== */
|
|
|
+ #define R_CEU_CDACR_B_CACR_Pos (0UL) /*!< CACR (Bit 0) */
|
|
|
+ #define R_CEU_CDACR_B_CACR_Msk (0xffffffffUL) /*!< CACR (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================== CDBYR_B ======================================================== */
|
|
|
+ #define R_CEU_CDBYR_B_CBYR_Pos (0UL) /*!< CBYR (Bit 0) */
|
|
|
+ #define R_CEU_CDBYR_B_CBYR_Msk (0xffffffffUL) /*!< CBYR (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================== CDBCR_B ======================================================== */
|
|
|
+ #define R_CEU_CDBCR_B_CBCR_Pos (0UL) /*!< CBCR (Bit 0) */
|
|
|
+ #define R_CEU_CDBCR_B_CBCR_Msk (0xffffffffUL) /*!< CBCR (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================== CBDSR_B ======================================================== */
|
|
|
+ #define R_CEU_CBDSR_B_CBVS_Pos (0UL) /*!< CBVS (Bit 0) */
|
|
|
+ #define R_CEU_CBDSR_B_CBVS_Msk (0x7fffffUL) /*!< CBVS (Bitfield-Mask: 0x7fffff) */
|
|
|
+/* ======================================================== CLFCR_B ======================================================== */
|
|
|
+ #define R_CEU_CLFCR_B_LPF_Pos (0UL) /*!< LPF (Bit 0) */
|
|
|
+ #define R_CEU_CLFCR_B_LPF_Msk (0x1UL) /*!< LPF (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== CDOCR_B ======================================================== */
|
|
|
+ #define R_CEU_CDOCR_B_COBS_Pos (0UL) /*!< COBS (Bit 0) */
|
|
|
+ #define R_CEU_CDOCR_B_COBS_Msk (0x1UL) /*!< COBS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CDOCR_B_COWS_Pos (1UL) /*!< COWS (Bit 1) */
|
|
|
+ #define R_CEU_CDOCR_B_COWS_Msk (0x2UL) /*!< COWS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CDOCR_B_COLS_Pos (2UL) /*!< COLS (Bit 2) */
|
|
|
+ #define R_CEU_CDOCR_B_COLS_Msk (0x4UL) /*!< COLS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CDOCR_B_CDS_Pos (4UL) /*!< CDS (Bit 4) */
|
|
|
+ #define R_CEU_CDOCR_B_CDS_Msk (0x10UL) /*!< CDS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CDOCR_B_CBE_Pos (16UL) /*!< CBE (Bit 16) */
|
|
|
+ #define R_CEU_CDOCR_B_CBE_Msk (0x10000UL) /*!< CBE (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= CDAYR2_B ======================================================== */
|
|
|
+ #define R_CEU_CDAYR2_B_CAYR2_Pos (0UL) /*!< CAYR2 (Bit 0) */
|
|
|
+ #define R_CEU_CDAYR2_B_CAYR2_Msk (0xffffffffUL) /*!< CAYR2 (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================= CDACR2_B ======================================================== */
|
|
|
+ #define R_CEU_CDACR2_B_CACR2_Pos (0UL) /*!< CACR2 (Bit 0) */
|
|
|
+ #define R_CEU_CDACR2_B_CACR2_Msk (0xffffffffUL) /*!< CACR2 (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================= CDBYR2_B ======================================================== */
|
|
|
+ #define R_CEU_CDBYR2_B_CBYR2_Pos (0UL) /*!< CBYR2 (Bit 0) */
|
|
|
+ #define R_CEU_CDBYR2_B_CBYR2_Msk (0xffffffffUL) /*!< CBYR2 (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================= CDBCR2_B ======================================================== */
|
|
|
+ #define R_CEU_CDBCR2_B_CBCR2_Pos (0UL) /*!< CBCR2 (Bit 0) */
|
|
|
+ #define R_CEU_CDBCR2_B_CBCR2_Msk (0xffffffffUL) /*!< CBCR2 (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================== CAMOR_M ======================================================== */
|
|
|
+ #define R_CEU_CAMOR_M_HOFST_Pos (0UL) /*!< HOFST (Bit 0) */
|
|
|
+ #define R_CEU_CAMOR_M_HOFST_Msk (0x1fffUL) /*!< HOFST (Bitfield-Mask: 0x1fff) */
|
|
|
+ #define R_CEU_CAMOR_M_VOFST_Pos (16UL) /*!< VOFST (Bit 16) */
|
|
|
+ #define R_CEU_CAMOR_M_VOFST_Msk (0xfff0000UL) /*!< VOFST (Bitfield-Mask: 0xfff) */
|
|
|
+/* ======================================================== CAPWR_M ======================================================== */
|
|
|
+ #define R_CEU_CAPWR_M_HWDTH_Pos (0UL) /*!< HWDTH (Bit 0) */
|
|
|
+ #define R_CEU_CAPWR_M_HWDTH_Msk (0x1fffUL) /*!< HWDTH (Bitfield-Mask: 0x1fff) */
|
|
|
+ #define R_CEU_CAPWR_M_VWDTH_Pos (16UL) /*!< VWDTH (Bit 16) */
|
|
|
+ #define R_CEU_CAPWR_M_VWDTH_Msk (0xfff0000UL) /*!< VWDTH (Bitfield-Mask: 0xfff) */
|
|
|
+/* ======================================================== CFLCR_M ======================================================== */
|
|
|
+ #define R_CEU_CFLCR_M_HFRAC_Pos (0UL) /*!< HFRAC (Bit 0) */
|
|
|
+ #define R_CEU_CFLCR_M_HFRAC_Msk (0xfffUL) /*!< HFRAC (Bitfield-Mask: 0xfff) */
|
|
|
+ #define R_CEU_CFLCR_M_HMANT_Pos (12UL) /*!< HMANT (Bit 12) */
|
|
|
+ #define R_CEU_CFLCR_M_HMANT_Msk (0xf000UL) /*!< HMANT (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_CEU_CFLCR_M_VFRAC_Pos (16UL) /*!< VFRAC (Bit 16) */
|
|
|
+ #define R_CEU_CFLCR_M_VFRAC_Msk (0xfff0000UL) /*!< VFRAC (Bitfield-Mask: 0xfff) */
|
|
|
+ #define R_CEU_CFLCR_M_VMANT_Pos (28UL) /*!< VMANT (Bit 28) */
|
|
|
+ #define R_CEU_CFLCR_M_VMANT_Msk (0xf0000000UL) /*!< VMANT (Bitfield-Mask: 0x0f) */
|
|
|
+/* ======================================================== CFSZR_M ======================================================== */
|
|
|
+ #define R_CEU_CFSZR_M_HFCLP_Pos (0UL) /*!< HFCLP (Bit 0) */
|
|
|
+ #define R_CEU_CFSZR_M_HFCLP_Msk (0xfffUL) /*!< HFCLP (Bitfield-Mask: 0xfff) */
|
|
|
+ #define R_CEU_CFSZR_M_VFCLP_Pos (16UL) /*!< VFCLP (Bit 16) */
|
|
|
+ #define R_CEU_CFSZR_M_VFCLP_Msk (0xfff0000UL) /*!< VFCLP (Bitfield-Mask: 0xfff) */
|
|
|
+/* ======================================================== CDWDR_M ======================================================== */
|
|
|
+ #define R_CEU_CDWDR_M_CHDW_Pos (0UL) /*!< CHDW (Bit 0) */
|
|
|
+ #define R_CEU_CDWDR_M_CHDW_Msk (0x1fffUL) /*!< CHDW (Bitfield-Mask: 0x1fff) */
|
|
|
+/* ======================================================== CDAYR_M ======================================================== */
|
|
|
+ #define R_CEU_CDAYR_M_CAYR_Pos (0UL) /*!< CAYR (Bit 0) */
|
|
|
+ #define R_CEU_CDAYR_M_CAYR_Msk (0xffffffffUL) /*!< CAYR (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================== CDACR_M ======================================================== */
|
|
|
+ #define R_CEU_CDACR_M_CACR_Pos (0UL) /*!< CACR (Bit 0) */
|
|
|
+ #define R_CEU_CDACR_M_CACR_Msk (0xffffffffUL) /*!< CACR (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================== CDBYR_M ======================================================== */
|
|
|
+ #define R_CEU_CDBYR_M_CBYR_Pos (0UL) /*!< CBYR (Bit 0) */
|
|
|
+ #define R_CEU_CDBYR_M_CBYR_Msk (0xffffffffUL) /*!< CBYR (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================== CDBCR_M ======================================================== */
|
|
|
+ #define R_CEU_CDBCR_M_CBCR_Pos (0UL) /*!< CBCR (Bit 0) */
|
|
|
+ #define R_CEU_CDBCR_M_CBCR_Msk (0xffffffffUL) /*!< CBCR (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================== CBDSR_M ======================================================== */
|
|
|
+ #define R_CEU_CBDSR_M_CBVS_Pos (0UL) /*!< CBVS (Bit 0) */
|
|
|
+ #define R_CEU_CBDSR_M_CBVS_Msk (0x7fffffUL) /*!< CBVS (Bitfield-Mask: 0x7fffff) */
|
|
|
+/* ======================================================== CLFCR_M ======================================================== */
|
|
|
+ #define R_CEU_CLFCR_M_LPF_Pos (0UL) /*!< LPF (Bit 0) */
|
|
|
+ #define R_CEU_CLFCR_M_LPF_Msk (0x1UL) /*!< LPF (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== CDOCR_M ======================================================== */
|
|
|
+ #define R_CEU_CDOCR_M_COBS_Pos (0UL) /*!< COBS (Bit 0) */
|
|
|
+ #define R_CEU_CDOCR_M_COBS_Msk (0x1UL) /*!< COBS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CDOCR_M_COWS_Pos (1UL) /*!< COWS (Bit 1) */
|
|
|
+ #define R_CEU_CDOCR_M_COWS_Msk (0x2UL) /*!< COWS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CDOCR_M_COLS_Pos (2UL) /*!< COLS (Bit 2) */
|
|
|
+ #define R_CEU_CDOCR_M_COLS_Msk (0x4UL) /*!< COLS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CDOCR_M_CDS_Pos (4UL) /*!< CDS (Bit 4) */
|
|
|
+ #define R_CEU_CDOCR_M_CDS_Msk (0x10UL) /*!< CDS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_CEU_CDOCR_M_CBE_Pos (16UL) /*!< CBE (Bit 16) */
|
|
|
+ #define R_CEU_CDOCR_M_CBE_Msk (0x10000UL) /*!< CBE (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= CDAYR2_M ======================================================== */
|
|
|
+ #define R_CEU_CDAYR2_M_CAYR2_Pos (0UL) /*!< CAYR2 (Bit 0) */
|
|
|
+ #define R_CEU_CDAYR2_M_CAYR2_Msk (0xffffffffUL) /*!< CAYR2 (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================= CDACR2_M ======================================================== */
|
|
|
+ #define R_CEU_CDACR2_M_CACR2_Pos (0UL) /*!< CACR2 (Bit 0) */
|
|
|
+ #define R_CEU_CDACR2_M_CACR2_Msk (0xffffffffUL) /*!< CACR2 (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================= CDBYR2_M ======================================================== */
|
|
|
+ #define R_CEU_CDBYR2_M_CBYR2_Pos (0UL) /*!< CBYR2 (Bit 0) */
|
|
|
+ #define R_CEU_CDBYR2_M_CBYR2_Msk (0xffffffffUL) /*!< CBYR2 (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================= CDBCR2_M ======================================================== */
|
|
|
+ #define R_CEU_CDBCR2_M_CBCR2_Pos (0UL) /*!< CBCR2 (Bit 0) */
|
|
|
+ #define R_CEU_CDBCR2_M_CBCR2_Msk (0xffffffffUL) /*!< CBCR2 (Bitfield-Mask: 0xffffffff) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_ULPT0 ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ======================================================== ULPTCNT ======================================================== */
|
|
|
+ #define R_ULPT0_ULPTCNT_ULPTCNT_Pos (0UL) /*!< ULPTCNT (Bit 0) */
|
|
|
+ #define R_ULPT0_ULPTCNT_ULPTCNT_Msk (0xffffffffUL) /*!< ULPTCNT (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================== ULPTCMA ======================================================== */
|
|
|
+ #define R_ULPT0_ULPTCMA_ULPTCMA_Pos (0UL) /*!< ULPTCMA (Bit 0) */
|
|
|
+ #define R_ULPT0_ULPTCMA_ULPTCMA_Msk (0xffffffffUL) /*!< ULPTCMA (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================== ULPTCMB ======================================================== */
|
|
|
+ #define R_ULPT0_ULPTCMB_ULPTCMB_Pos (0UL) /*!< ULPTCMB (Bit 0) */
|
|
|
+ #define R_ULPT0_ULPTCMB_ULPTCMB_Msk (0xffffffffUL) /*!< ULPTCMB (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================== ULPTCR ========================================================= */
|
|
|
+ #define R_ULPT0_ULPTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */
|
|
|
+ #define R_ULPT0_ULPTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ULPT0_ULPTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */
|
|
|
+ #define R_ULPT0_ULPTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ULPT0_ULPTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */
|
|
|
+ #define R_ULPT0_ULPTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ULPT0_ULPTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */
|
|
|
+ #define R_ULPT0_ULPTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ULPT0_ULPTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */
|
|
|
+ #define R_ULPT0_ULPTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ULPT0_ULPTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */
|
|
|
+ #define R_ULPT0_ULPTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== ULPTMR1 ======================================================== */
|
|
|
+ #define R_ULPT0_ULPTMR1_TMOD1_Pos (1UL) /*!< TMOD1 (Bit 1) */
|
|
|
+ #define R_ULPT0_ULPTMR1_TMOD1_Msk (0x2UL) /*!< TMOD1 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ULPT0_ULPTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */
|
|
|
+ #define R_ULPT0_ULPTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ULPT0_ULPTMR1_TCK1_Pos (5UL) /*!< TCK1 (Bit 5) */
|
|
|
+ #define R_ULPT0_ULPTMR1_TCK1_Msk (0x20UL) /*!< TCK1 (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== ULPTMR2 ======================================================== */
|
|
|
+ #define R_ULPT0_ULPTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */
|
|
|
+ #define R_ULPT0_ULPTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_ULPT0_ULPTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */
|
|
|
+ #define R_ULPT0_ULPTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== ULPTMR3 ======================================================== */
|
|
|
+ #define R_ULPT0_ULPTMR3_TCNTCTL_Pos (0UL) /*!< TCNTCTL (Bit 0) */
|
|
|
+ #define R_ULPT0_ULPTMR3_TCNTCTL_Msk (0x1UL) /*!< TCNTCTL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ULPT0_ULPTMR3_TEVPOL_Pos (1UL) /*!< TEVPOL (Bit 1) */
|
|
|
+ #define R_ULPT0_ULPTMR3_TEVPOL_Msk (0x2UL) /*!< TEVPOL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ULPT0_ULPTMR3_TOPOL_Pos (2UL) /*!< TOPOL (Bit 2) */
|
|
|
+ #define R_ULPT0_ULPTMR3_TOPOL_Msk (0x4UL) /*!< TOPOL (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ULPT0_ULPTMR3_TEECTL_Pos (4UL) /*!< TEECTL (Bit 4) */
|
|
|
+ #define R_ULPT0_ULPTMR3_TEECTL_Msk (0x30UL) /*!< TEECTL (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_ULPT0_ULPTMR3_TEEPOL_Pos (6UL) /*!< TEEPOL (Bit 6) */
|
|
|
+ #define R_ULPT0_ULPTMR3_TEEPOL_Msk (0xc0UL) /*!< TEEPOL (Bitfield-Mask: 0x03) */
|
|
|
+/* ======================================================== ULPTIOC ======================================================== */
|
|
|
+ #define R_ULPT0_ULPTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */
|
|
|
+ #define R_ULPT0_ULPTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ULPT0_ULPTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */
|
|
|
+ #define R_ULPT0_ULPTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_ULPT0_ULPTIOC_TIOGT0_Pos (6UL) /*!< TIOGT0 (Bit 6) */
|
|
|
+ #define R_ULPT0_ULPTIOC_TIOGT0_Msk (0x40UL) /*!< TIOGT0 (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================== ULPTISR ======================================================== */
|
|
|
+ #define R_ULPT0_ULPTISR_RCCPSEL2_Pos (2UL) /*!< RCCPSEL2 (Bit 2) */
|
|
|
+ #define R_ULPT0_ULPTISR_RCCPSEL2_Msk (0x4UL) /*!< RCCPSEL2 (Bitfield-Mask: 0x01) */
|
|
|
+/* ======================================================= ULPTCMSR ======================================================== */
|
|
|
+ #define R_ULPT0_ULPTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */
|
|
|
+ #define R_ULPT0_ULPTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ULPT0_ULPTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */
|
|
|
+ #define R_ULPT0_ULPTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ULPT0_ULPTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */
|
|
|
+ #define R_ULPT0_ULPTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ULPT0_ULPTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */
|
|
|
+ #define R_ULPT0_ULPTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ULPT0_ULPTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */
|
|
|
+ #define R_ULPT0_ULPTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_ULPT0_ULPTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */
|
|
|
+ #define R_ULPT0_ULPTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_DEBUG_OCD ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ======================================================= FSBLSTATM ======================================================= */
|
|
|
+ #define R_DEBUG_OCD_FSBLSTATM_CS_Pos (0UL) /*!< CS (Bit 0) */
|
|
|
+ #define R_DEBUG_OCD_FSBLSTATM_CS_Msk (0x1UL) /*!< CS (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_DEBUG_OCD_FSBLSTATM_RS_Pos (1UL) /*!< RS (Bit 1) */
|
|
|
+ #define R_DEBUG_OCD_FSBLSTATM_RS_Msk (0x2UL) /*!< RS (Bitfield-Mask: 0x01) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_DOTF ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ====================================================== CONVAREAST ======================================================= */
|
|
|
+ #define R_DOTF_CONVAREAST_CONVAREAST_Pos (12UL) /*!< CONVAREAST (Bit 12) */
|
|
|
+ #define R_DOTF_CONVAREAST_CONVAREAST_Msk (0xfffff000UL) /*!< CONVAREAST (Bitfield-Mask: 0xfffff) */
|
|
|
+/* ======================================================= CONVAREAD ======================================================= */
|
|
|
+ #define R_DOTF_CONVAREAD_CONVAREAD_Pos (12UL) /*!< CONVAREAD (Bit 12) */
|
|
|
+ #define R_DOTF_CONVAREAD_CONVAREAD_Msk (0xfffff000UL) /*!< CONVAREAD (Bitfield-Mask: 0xfffff) */
|
|
|
+/* ========================================================= REG00 ========================================================= */
|
|
|
+ #define R_DOTF_REG00_B09_Pos (9UL) /*!< B09 (Bit 9) */
|
|
|
+ #define R_DOTF_REG00_B09_Msk (0x200UL) /*!< B09 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_DOTF_REG00_B16_Pos (16UL) /*!< B16 (Bit 16) */
|
|
|
+ #define R_DOTF_REG00_B16_Msk (0x10000UL) /*!< B16 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_DOTF_REG00_B17_Pos (17UL) /*!< B17 (Bit 17) */
|
|
|
+ #define R_DOTF_REG00_B17_Msk (0x20000UL) /*!< B17 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_DOTF_REG00_B20_Pos (20UL) /*!< B20 (Bit 20) */
|
|
|
+ #define R_DOTF_REG00_B20_Msk (0x100000UL) /*!< B20 (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_DOTF_REG00_B24_Pos (24UL) /*!< B24 (Bit 24) */
|
|
|
+ #define R_DOTF_REG00_B24_Msk (0x3000000UL) /*!< B24 (Bitfield-Mask: 0x03) */
|
|
|
+ #define R_DOTF_REG00_B28_Pos (28UL) /*!< B28 (Bit 28) */
|
|
|
+ #define R_DOTF_REG00_B28_Msk (0x30000000UL) /*!< B28 (Bitfield-Mask: 0x03) */
|
|
|
+/* ========================================================= REG03 ========================================================= */
|
|
|
+ #define R_DOTF_REG03_B00_Pos (0UL) /*!< B00 (Bit 0) */
|
|
|
+ #define R_DOTF_REG03_B00_Msk (0xffffffffUL) /*!< B00 (Bitfield-Mask: 0xffffffff) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_AGTX0 ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_FLAD ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ======================================================== FCKMHZ ========================================================= */
|
|
|
+ #define R_FLAD_FCKMHZ_FCKMHZ_Pos (0UL) /*!< FCKMHZ (Bit 0) */
|
|
|
+ #define R_FLAD_FCKMHZ_FCKMHZ_Msk (0xffUL) /*!< FCKMHZ (Bitfield-Mask: 0xff) */
|
|
|
+
|
|
|
+/* =========================================================================================================================== */
|
|
|
+/* ================ R_OFS_DATAFLASH ================ */
|
|
|
+/* =========================================================================================================================== */
|
|
|
+
|
|
|
+/* ======================================================= FSBLCTRL0 ======================================================= */
|
|
|
+ #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLEN_Pos (0UL) /*!< FSBLEN (Bit 0) */
|
|
|
+ #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLEN_Msk (0x7UL) /*!< FSBLEN (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLSKIPSW_Pos (3UL) /*!< FSBLSKIPSW (Bit 3) */
|
|
|
+ #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLSKIPSW_Msk (0x38UL) /*!< FSBLSKIPSW (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLSKIPDS_Pos (6UL) /*!< FSBLSKIPDS (Bit 6) */
|
|
|
+ #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLSKIPDS_Msk (0x1c0UL) /*!< FSBLSKIPDS (Bitfield-Mask: 0x07) */
|
|
|
+ #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLCLK_Pos (9UL) /*!< FSBLCLK (Bit 9) */
|
|
|
+ #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLCLK_Msk (0xe00UL) /*!< FSBLCLK (Bitfield-Mask: 0x07) */
|
|
|
+/* ======================================================= FSBLCTRL1 ======================================================= */
|
|
|
+ #define R_OFS_DATAFLASH_FSBLCTRL1_FSBLEXMD_Pos (0UL) /*!< FSBLEXMD (Bit 0) */
|
|
|
+ #define R_OFS_DATAFLASH_FSBLCTRL1_FSBLEXMD_Msk (0x3UL) /*!< FSBLEXMD (Bitfield-Mask: 0x03) */
|
|
|
+/* ======================================================= FSBLCTRL2 ======================================================= */
|
|
|
+ #define R_OFS_DATAFLASH_FSBLCTRL2_PORTPN_Pos (0UL) /*!< PORTPN (Bit 0) */
|
|
|
+ #define R_OFS_DATAFLASH_FSBLCTRL2_PORTPN_Msk (0xfUL) /*!< PORTPN (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_OFS_DATAFLASH_FSBLCTRL2_PORTGN_Pos (4UL) /*!< PORTGN (Bit 4) */
|
|
|
+ #define R_OFS_DATAFLASH_FSBLCTRL2_PORTGN_Msk (0x1f0UL) /*!< PORTGN (Bitfield-Mask: 0x1f) */
|
|
|
+/* ========================================================= SACC0 ========================================================= */
|
|
|
+/* ========================================================= SACC1 ========================================================= */
|
|
|
+/* ========================================================= SAMR ========================================================== */
|
|
|
+/* ======================================================= HOEMRTPK ======================================================== */
|
|
|
+/* ========================================================= ARCLS ========================================================= */
|
|
|
+ #define R_OFS_DATAFLASH_ARCLS_ARCS_LK_Pos (0UL) /*!< ARCS_LK (Bit 0) */
|
|
|
+ #define R_OFS_DATAFLASH_ARCLS_ARCS_LK_Msk (0x1UL) /*!< ARCS_LK (Bitfield-Mask: 0x01) */
|
|
|
+ #define R_OFS_DATAFLASH_ARCLS_ARCNS_LK_Pos (1UL) /*!< ARCNS_LK (Bit 1) */
|
|
|
+ #define R_OFS_DATAFLASH_ARCLS_ARCNS_LK_Msk (0x1eUL) /*!< ARCNS_LK (Bitfield-Mask: 0x0f) */
|
|
|
+ #define R_OFS_DATAFLASH_ARCLS_ARCBL_LK_Pos (5UL) /*!< ARCBL_LK (Bit 5) */
|
|
|
+ #define R_OFS_DATAFLASH_ARCLS_ARCBL_LK_Msk (0x20UL) /*!< ARCBL_LK (Bitfield-Mask: 0x01) */
|
|
|
+/* ========================================================= ARCCS ========================================================= */
|
|
|
+ #define R_OFS_DATAFLASH_ARCCS_CNF_ARCNS_Pos (0UL) /*!< CNF_ARCNS (Bit 0) */
|
|
|
+ #define R_OFS_DATAFLASH_ARCCS_CNF_ARCNS_Msk (0x3UL) /*!< CNF_ARCNS (Bitfield-Mask: 0x03) */
|
|
|
+/* ======================================================== ARC_SEC ======================================================== */
|
|
|
+ #define R_OFS_DATAFLASH_ARC_SEC_ARC_SEC_Pos (0UL) /*!< ARC_SEC (Bit 0) */
|
|
|
+ #define R_OFS_DATAFLASH_ARC_SEC_ARC_SEC_Msk (0xffffffffUL) /*!< ARC_SEC (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================= ARC_NSEC ======================================================== */
|
|
|
+ #define R_OFS_DATAFLASH_ARC_NSEC_ARC_NSEC_Pos (0UL) /*!< ARC_NSEC (Bit 0) */
|
|
|
+ #define R_OFS_DATAFLASH_ARC_NSEC_ARC_NSEC_Msk (0xffffffffUL) /*!< ARC_NSEC (Bitfield-Mask: 0xffffffff) */
|
|
|
+/* ======================================================= ARC_OEMBL ======================================================= */
|
|
|
+ #define R_OFS_DATAFLASH_ARC_OEMBL_ARC_OEMBL_Pos (0UL) /*!< ARC_OEMBL (Bit 0) */
|
|
|
+ #define R_OFS_DATAFLASH_ARC_OEMBL_ARC_OEMBL_Msk (0xffffffffUL) /*!< ARC_OEMBL (Bitfield-Mask: 0xffffffff) */
|
|
|
+
|
|
|
+/** @} */ /* End of group PosMask_peripherals */
|
|
|
+
|
|
|
+ #ifdef __cplusplus
|
|
|
+}
|
|
|
+ #endif
|
|
|
+
|
|
|
+#endif /* R7FA8M1AH_H */
|
|
|
+
|
|
|
+/** @} */ /* End of group R7FA8M1AH */
|
|
|
+
|
|
|
+/** @} */ /* End of group Renesas */
|
Rbb666
