CMSIS-Core (Cortex-M): Cache Functions (Level-1)

| CMSIS-Core (Cortex-M) Version 5.4.0 CMSIS-Core support for Cortex-M processor-based devices

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Cache Functions (Level-1)

Functions for level-1 instruction and data cache. More...

## Content

| I-Cache Functions
| Functions for the level-1 instruction cache.
| D-Cache Functions
| Functions for the level-1 data cache.

## Description

Functions for level-1 instruction and data cache.

Enhanced Cortex processors (like M7 and M55) include a memory system, which includes an optional Harvard level-1 data and instruction cache with ECC. The optional CPU cache has an instruction and data cache with sizes of [0;4;8;16;32;64]KB. Both instruction and data cache RAM can be configured at implementation time to have Error Correcting Code (ECC) to protect the data stored in the memory from errors.

All cache maintenance operations are executed by writing to registers in the memory mapped System Control Space (SCS) region of the internal PPB memory space.

Note
  After reset, you must invalidate each cache before enabling it.

The functions are grouped for:

- I-Cache Functions
- D-Cache Functions