CMSIS-Core (Cortex-M): Core Register Access

| CMSIS-Core (Cortex-M) Version 5.4.0 CMSIS-Core support for Cortex-M processor-based devices

- Main Page
- Usage and Description
- Reference

All Data Structures Files Functions Variables Enumerations Enumerator Groups Pages
Functions
Core Register Access

Functions to access the Cortex-M core registers. More...

## Functions

uint32_t | __get_CONTROL (void)
| Read the CONTROL register. More...
void | __set_CONTROL (uint32_t control)
| Set the CONTROL Register. More...
uint32_t | __get_IPSR (void)
| Read the IPSR register. More...
uint32_t | __get_APSR (void)
| Read the APSR register. More...
uint32_t | __get_xPSR (void)
| Read the xPSR register. More...
uint32_t | __get_PSP (void)
| Read the PSP register. More...
void | __set_PSP (uint32_t topOfProcStack)
| Set the PSP register. More...
uint32_t | __get_MSP (void)
| Read the MSP register. More...
void | __set_MSP (uint32_t topOfMainStack)
| Set the MSP register. More...
uint32_t | __get_PRIMASK (void)
| Read the PRIMASK register bit. More...
void | __set_PRIMASK (uint32_t priMask)
| Set the Priority Mask bit. More...
uint32_t | __get_BASEPRI (void)
| Read the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000]. More...
void | __set_BASEPRI (uint32_t basePri)
| Set the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000]. More...
void | __set_BASEPRI_MAX (uint32_t basePri)
| Increase the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000]. More...
uint32_t | __get_FAULTMASK (void)
| Read the FAULTMASK register [not for Cortex-M0, Cortex-M0+, or SC000]. More...
void | __set_FAULTMASK (uint32_t faultMask)
| Set the FAULTMASK register [not for Cortex-M0, Cortex-M0+, or SC000]. More...
uint32_t | __get_FPSCR (void)
| Read the FPSCR register [only Cortex-M4 and Cortex-M7]. More...
void | __set_FPSCR (uint32_t fpscr)
| Set the FPSC register [only for Cortex-M4 and Cortex-M7]. More...
void | __enable_irq (void)
| Globally enables interrupts and configurable fault handlers. More...
void | __disable_irq (void)
| Globally disables interrupts and configurable fault handlers. More...
void | __enable_fault_irq (void)
| Enables interrupts and all fault handlers [not for Cortex-M0, Cortex-M0+, or SC000]. More...
void | __disable_fault_irq (void)
| Disables interrupts and all fault handlers [not for Cortex-M0, Cortex-M0+, or SC000]. More...
uint32_t | __get_PSPLIM (void)
| Get Process Stack Pointer Limit Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. More...
void | __set_PSPLIM (uint32_t ProcStackPtrLimit)
| Set Process Stack Pointer Limit Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. More...
uint32_t | __get_MSPLIM (void)
| Get Main Stack Pointer Limit Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. More...
| __set_MSPLIM (uint32_t MainStackPtrLimit)
| Set Main Stack Pointer Limit Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. More...

## Description

Functions to access the Cortex-M core registers.

The following functions provide access to Cortex-M core registers.

## Function Documentation

void __disable_fault_irq | ( | void |  | ) |

Disables interrupts and all fault handlers [not for Cortex-M0, Cortex-M0+, or SC000].

The function disables interrupts and all fault handlers by setting FAULTMASK. The function uses the instruction CPSID f.

Remarks
  - not for Cortex-M0, Cortex-M0+, or SC000.
  - Can be executed in privileged mode only.
  - An interrupt can enter pending state even if it is disabled. Disabling an interrupt only prevents the processor from taking that interrupt.

See Also
  - __enable_fault_irq; __set_BASEPRI; __set_CONTROL; __set_FAULTMASK

void __disable_irq | ( | void |  | ) |

Globally disables interrupts and configurable fault handlers.

The function disables interrupts and all configurable fault handlers by setting PRIMASK. The function uses the instruction CPSID i.

Remarks
  - Can be executed in privileged mode only.
  - An interrupt can enter pending state even if it is disabled. Disabling an interrupt only prevents the processor from taking that interrupt.

See Also
  - __enable_irq; __set_BASEPRI; __set_CONTROL; __set_PRIMASK

void __enable_fault_irq | ( | void |  | ) |

Enables interrupts and all fault handlers [not for Cortex-M0, Cortex-M0+, or SC000].

The function enables interrupts and all fault handlers by clearing FAULTMASK. The function uses the instruction CPSIE f.

Remarks
  - not for Cortex-M0, Cortex-M0+, or SC000.
  - Can be executed in privileged mode only.

See Also
  - __disable_fault_irq; __set_BASEPRI; __set_CONTROL; __set_FAULTMASK

void __enable_irq | ( | void |  | ) |

Globally enables interrupts and configurable fault handlers.

The function enables interrupts and all configurable fault handlers by clearing PRIMASK. The function uses the instruction CPSIE i.

Remarks
  - Can be executed in privileged mode only.

See Also
  - __disable_irq; __set_BASEPRI; __set_CONTROL; __set_PRIMASK

uint32_t __get_APSR | ( | void |  | ) |

Read the APSR register.

The function reads the Application Program Status Register (APSR) using the instruction MRS.
The APSR contains the current state of the condition flags from instructions executed previously. The APSR is essential for controlling conditional branches. The following flags are used:

- N (APSR[31]) (Negative flag)
  - =1 The instruction result has a negative value (when interpreted as signed integer).
  - =0 The instruction result has a positive value or equal zero.
- Z (APSR[30]) (Zero flag)
  - =1 The instruction result is zero. Or, after a compare instruction, when the two values are the same.
- C (APSR[29]) (Carry or borrow flag)
  - =1 For unsigned additions, if an unsigned overflow occurred.
  - =inverse of borrow output status For unsigned subtract operations.
- V (APSR[28]) (Overflow flag)
  - =1 A signed overflow occurred (for signed additions or subtractions).
- Q (APSR[27]) (DSP overflow or saturation flag) [not Cortex-M0]
  - This flag is a sticky flag. Saturating and certain mutliplying instructions can set the flag, but cannot clear it.
  - =1 When saturation or an overflow occurred.
- GE (APSR[19:16]) (Greater than or Equal flags) [not Cortex-M0]
  - Can be set by the parallel add and subtract instructions.
  - Are used by the `SEL` instruction to perform byte-based selection from two registers.

Returns
  APSR register value

Remarks
  - Some instructions update all flags; some instructions update a subset of the flags.
  - If a flag is not updated, the original value is preserved.
  - Conditional instructions that are not executed have no effect on the flags.
  - The CMSIS does not provide a function to update this register.

See Also
  - __get_xPSR; APSR_Type
  - Cortex-M Reference Manuals

uint32_t __get_BASEPRI | ( | void |  | ) |

Read the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000].

The function returns the Base Priority Mask register (BASEPRI) using the instruction MRS.
BASEPRI defines the minimum priority for exception processing. When BASEPRI is set to a non-zero value, it prevents the activation of all exceptions with the same or lower priority level as the BASEPRI value.

Returns
  BASEPRI register value

Remarks
  - Not for Cortex-M0, Cortex-M0+, or SC000.

See Also
  - __set_BASEPRI; __set_BASEPRI_MAX; __get_FAULTMASK; __get_PRIMASK
  - Cortex-M Reference Manuals

uint32_t __get_CONTROL | ( | void |  | ) |

Read the CONTROL register.

The function reads the CONTROL register value using the instruction MRS.
The CONTROL register controls the stack used and the privilege level for software execution when the processor is in thread mode and, if implemented, indicates whether the FPU state is active. This register uses the following bits:

- CONTROL[2] [only Cortex-M4 and Cortex-M7]
  - =0 FPU not active
  - =1 FPU active
- CONTROL[1]
  - =0 In handler mode - MSP is selected. No alternate stack possible for handler mode.
  - =0 In thread mode - Default stack pointer MSP is used.
  - =1 In thread mode - Alternate stack pointer PSP is used.
- CONTROL[0] [not Cortex-M0]
  - =0 In thread mode and privileged state.
  - =1 In thread mode and user state.

Returns
  CONTROL register value

Remarks
  - The processor can be in user state or privileged state when running in thread mode.
  - Exception handlers always run in privileged state.
  - On reset, the processor is in thread mode with privileged access rights.

See Also
  - __set_CONTROL; CONTROL_Type
  - Cortex-M Reference Manuals

uint32_t __get_FAULTMASK | ( | void |  | ) |

Read the FAULTMASK register [not for Cortex-M0, Cortex-M0+, or SC000].

The function reads the Fault Mask register (FAULTMASK) value using the instruction MRS.
FAULTMASK prevents activation of all exceptions except for the Non-Maskable Interrupt (NMI).

Returns
  FAULTMASK register value

Remarks
  - not for Cortex-M0, Cortex-M0+, or SC000.
  - Is cleared automatically upon exiting the exception handler, except when returning from the NMI handler.

See Also
  - __set_FAULTMASK; __get_BASEPRI; __get_PRIMASK
  - Cortex-M Reference Manuals

uint32_t __get_FPSCR | ( | void |  | ) |

Read the FPSCR register [only Cortex-M4 and Cortex-M7].

The function reads the Floating-Point Status Control Register (FPSCR) value.
FPSCR provides all necessary User level controls of the floating-point system.

Returns
  - FPSCR register value, when __FPU_PRESENT=1
  - =0, when __FPU_PRESENT=0

Remarks
  - Only for Cortex-M4 and Cortex-M7.

See Also
  - __set_FPSCR
  - Cortex-M Reference Manuals

uint32_t __get_IPSR | ( | void |  | ) |

Read the IPSR register.

The function reads the Interrupt Program Status Register (IPSR) using the instruction MRS.
The ISPR contains the exception type number of the current Interrupt Service Routine (ISR). Each exception has an assocciated unique IRQn number. The following bits are used:

- ISR_NUMBER (IPSR[8:0])
  - =0 Thread mode
  - =1 Reserved
  - =2 NMI
  - =3 HardFault
  - =4 MemManage
  - =5 BusFault
  - =6 UsageFault
  - =7-10 Reserved
  - =11 SVCall
  - =12 Reserved for Debug
  - =13 Reserved
  - =14 PendSV
  - =15 SysTick
  - =16 IRQ0
  - ...
  - =n+15 IRQ(n-1)

Returns
  ISPR register value

Remarks
  - This register is read-only.

See Also
  - __get_xPSR; IPSR_Type
  - Interrupts and Exceptions (NVIC)
  - Cortex-M Reference Manuals

uint32_t __get_MSP | ( | void |  | ) |

Read the MSP register.

The function reads the Main Stack Pointer (MSP) value using the instruction MRS.
Physically two different stack pointers (SP) exist:

- The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when running exception handlers (handler mode).
- The Process Stack Pointer (PSP), which can be used only in thread mode.

Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:

- =0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded from the first 32-bit word of the vector table from the program memory.
- =1 PSP is the current stack pointer. The initial value is undefined.

Returns
  MSP Register value

Remarks
  - Only one of the two SPs is visible at a time.
  - For many applications, the system can completely rely on the MSP.
  - The PSP is normally used in designs with an OS where the stack memory for OS Kernel must be separated from the application code.

See Also
  - __set_MSP; __get_PSP; __get_CONTROL
  - Cortex-M Reference Manuals

uint32_t __get_MSPLIM | ( | void |  | ) |

Get Main Stack Pointer Limit Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode.

Returns the current value of the Main Stack Pointer Limit (MSPLIM).

Returns
  MSPLIM Register value

Note
  Only availabe for Armv8-M Architecture.

uint32_t __get_PRIMASK | ( | void |  | ) |

Read the PRIMASK register bit.

The function reads the Priority Mask register (PRIMASK) value using the instruction MRS.
PRIMASK is a 1-bit-wide interrupt mask register. When set, it blocks all interrupts apart from the non-maskable interrupt (NMI) and the hard fault exception. The PRIMASK prevents activation of all exceptions with configurable priority.

Returns
  PRIMASK register value
  - =0 no effect
  - =1 prevents the activation of all exceptions with configurable priority

See Also
  - __set_PRIMASK; __get_BASEPRI; __get_FAULTMASK
  - Cortex-M Reference Manuals

uint32_t __get_PSP | ( | void |  | ) |

Read the PSP register.

The function reads the Process Stack Pointer (PSP) value using the instruction MRS.
Physically two different stack pointers (SP) exist:

- The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when running exception handlers (handler mode).
- The Process Stack Pointer (PSP), which can be used only in thread mode.

Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:

- =0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded from the first 32-bit word of the vector table from the program memory.
- =1 PSP is the current stack pointer. The initial value is undefined.

Returns
  PSP register value

Remarks
  - Only one of the two SPs is visible at a time.
  - For many applications, the system can completely rely on the MSP.
  - The PSP is normally used in designs with an OS where the stack memory for OS Kernel must be separated from the application code.

See Also
  - __set_PSP; __get_MSP; __get_CONTROL
  - Cortex-M Reference Manuals

uint32_t __get_PSPLIM | ( | void |  | ) |

Get Process Stack Pointer Limit Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode.

Returns the current value of the Process Stack Pointer Limit (PSPLIM).

Returns
  PSPLIM Register value

Note
  Only availabe for Armv8-M Architecture.

uint32_t __get_xPSR | ( | void |  | ) |

Read the xPSR register.

The function reads the combined Program Status Register (xPSR) using the instruction MRS.
xPSR provides information about program execution and the APSR flags. It consists of the following PSRs:

- Application Program Status Register (APSR)
- Interrupt Program Status Register (IPSR)
- Execution Program Status Register (EPSR)

In addition to the flags described in __get_APSR and __get_IPSR, the register provides the following flags:

- IT (xPSR[26:25]) (If-Then condition instruction)
  - Contains up to four instructions following an IT instruction.
  - Each instruction in the block is conditional.
  - The conditions for the instructions are either all the same, or some can be the inverse of others.
- T (xPSR[24]) (Thumb bit)
  - =1 Indicates that that the processor is in Thumb state.
  - =0 Attempting to execute instructions when the T bit is 0 results in a fault or lockup.
  - The conditions for the instructions are either all the same, or some can be the inverse of others.

Returns
  xPSR register value

Remarks
  - The CMSIS does not provide functions that access EPSR.

See Also
  - __get_APSR; __get_IPSR; xPSR_Type
  - Cortex-M Reference Manuals

void __set_BASEPRI | ( | uint32_t | basePri | ) |

Set the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000].

The function sets the Base Priority Mask register (BASEPRI) value using the instruction MSR.
BASEPRI defines the minimum priority for exception processing. When BASEPRI is set to a non-zero value, it prevents the activation of all exceptions with the same or lower priority level as the BASEPRI value.

Parameters

  [in] | basePri | BASEPRI value to set

Remarks
  - Not for Cortex-M0, Cortex-M0+, or SC000.
  - Cannot be set in user state.
  - Useful for changing the masking level or disabling the masking.

See Also
  - __get_BASEPRI; __set_BASEPRI_MAX; __set_FAULTMASK; __set_PRIMASK
  - Cortex-M Reference Manuals

void __set_BASEPRI_MAX | ( | uint32_t | basePri | ) |

Increase the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000].

The function only increases the Base Priority Mask register (BASEPRI) value using the instruction MSR. The value is set only if BASEPRI masking is disabled, or the new value increases the BASEPRI priority level.
BASEPRI defines the minimum priority for exception processing.

Parameters

  [in] | basePri | BASEPRI value to set

Remarks
  - Not for Cortex-M0, Cortex-M0+, or SC000.
  - Cannot be set in user state.
  - Useful for increasing the masking level.
  - Has no effect when basePri is lower than the current value of BASEPRI.
  - Use __set_BASEPRI to lower the Base Priority Mask register.

See Also
  - __set_BASEPRI; __get_BASEPRI; __set_FAULTMASK; __set_PRIMASK
  - Cortex-M Reference Manuals

void __set_CONTROL | ( | uint32_t | control | ) |

Set the CONTROL Register.

The function sets the CONTROL register value using the instruction MSR.
The CONTROL register controls the stack used and the privilege level for software execution when the processor is in thread mode and, if implemented, indicates whether the FPU state is active. This register uses the following bits:

- CONTROL[2] [only Cortex-M4 and Cortex-M7]
  - =0 FPU not active
  - =1 FPU active
- CONTROL[1]
  - Writeable only when the processor is in thread mode and privileged state (CONTROL[0]=0).
  - =0 In handler mode - MSP is selected. No alternate stack pointer possible for handler mode.
  - =0 In thread mode - Default stack pointer MSP is used.
  - =1 In thread mode - Alternate stack pointer PSP is used.
- CONTROL[0] [not writeable for Cortex-M0]
  - Writeable only when the processor is in privileged state.
  - Can be used to switch the processor to user state (thread mode).
  - Once in user state, trigger an interrupt and change the state to privileged in the exception handler (the only way).
  - =0 In thread mode and privileged state.
  - =1 In thread mode and user state.

Parameters

  [in] | control | CONTROL register value to set

Remarks
  - The processor can be in user state or privileged state when running in thread mode.
  - Exception handlers always run in privileged state.
  - On reset, the processor is in thread mode with privileged access rights.

See Also
  - __get_CONTROL; __set_PSP; __set_MSP; CONTROL_Type
  - Cortex-M Reference Manuals

void __set_FAULTMASK | ( | uint32_t | faultMask | ) |

Set the FAULTMASK register [not for Cortex-M0, Cortex-M0+, or SC000].

The function sets the Fault Mask register (FAULTMASK) value using the instruction MSR.
FAULTMASK prevents activation of all exceptions except for Non-Maskable Interrupt (NMI). FAULTMASK can be used to escalate a configurable fault handler (BusFault, usage fault, or memory management fault) to hard fault level without invoking a hard fault. This allows the fault handler to pretend to be the hard fault handler, whith the ability to:

1. Mask BusFault by setting the BFHFNMIGN in the Configuration Control register. It can be used to test the bus system without causing a lockup.
2. Bypass the MPU, allowing accessing the MPU protected memory location without reprogramming the MPU to just carry out a few transfers for fixing faults.

Parameters

  [in] | faultMask | FAULTMASK register value to set

Remarks
  - not for Cortex-M0, Cortex-M0+, or SC000.
  - Is cleared automatically upon exiting the exception handler, except when returning from the NMI handler.
  - When set, it changes the effective current priority level to -1, so that even the hard fault handler is blocked.
  - Can be used by fault handlers to change their priority to -1 to have access to some features for hard fault exceptions (see above).
  - When set, lockups can still be caused by incorrect or undefined instructions, or by using SVC in the wrong priority level.

See Also
  - __get_FAULTMASK; __set_BASEPRI; __set_PRIMASK
  - Cortex-M Reference Manuals

void __set_FPSCR | ( | uint32_t | fpscr | ) |

Set the FPSC register [only for Cortex-M4 and Cortex-M7].

The function sets the Floating-Point Status Control Register (FPSCR) value.
FPSCR provides all necessary User level control of the floating-point system.

- N (FPSC[31]) (Negative flag)
  - =1 The instruction result has a negative value (when interpreted as signed integer).
  - =0 The instruction result has a positive value or equal zero.
- Z (FPSC[30]) (Zero flag)
  - =1 The instruction result is zero. Or, after a compare instruction, when the two values are the same.
- C (FPSC[29]) (Carry or borrow flag)
  - =1 For unsigned additions, if an unsigned overflow occurred.
  - =inverse of borrow output status For unsigned subtract operations.
- V (FPSC[28]) (Overflow flag)
  - =1 A signed overflow occurred (for signed additions or subtractions).
- AHP (FPSC[26]) (Alternative half-precision flag)
  - =1 Alternative half-precision format selected.
  - =0 IEEE half-precision format selected.
- DN (FPSC[25]) (Default NaN mode control flag)
  - =1 Any operation involving one or more NaNs returns the Default NaN.
  - =0 NaN operands propagate through to the output of a floating-point operation.
- FZ (FPSC[24]) (Flush-to-zero mode control flag)
  - =1 Flush-to-zero mode enabled.
  - =0 Flush-to-zero mode disabled. Behavior of the floating-point system is fully compliant with the IEEE 754 standard.
- RMode (FPSC[23:22]) (Rounding Mode control flags)
  - =0b00 Round to Nearest (RN) mode.
  - =0b01 Round towards Plus Infinity (RP) mode.
  - =0b10 Round towards Minus Infinity (RM) mode.
  - =0b11 Round towards Zero (RZ) mode.
  - The specified rounding mode is used by almost all floating-point instructions.
- IDC (FPSC[7]) (Input Denormal cumulative exception flags)
  - See Cumulative exception bits (FPSC[4:0]).
- IXC (FPSC[4]) (Inexact cumulative exception flag)
  - =1 Exception occurred.
  - =0 Value has to be set explicitly.
  - Flag is not cleared automatically.
- UFC (FPSC[3]) (Underflow cumulative exception flag)
  - =1 Exception occurred.
  - =0 Value has to be set explicitly.
  - Flag is not cleared automatically.
- OFC (FPSC[2]) (Overflow cumulative exception flag)
  - =1 Exception occurred.
  - =0 Value has to be set explicitly.
  - Flag is not cleared automatically.
- DZC (FPSC[1]) (Division by Zero cumulative exception flag)
  - =1 Exception occurred.
  - =0 Value has to be set explicitly.
  - Flag is not cleared automatically.
- IOC (FPSC[0]) (Invalid Operation cumulative exception flag)
  - =1 Exception occurred.
  - =0 Value has to be set explicitly.
  - Flag is not cleared automatically.

Parameters

  [in] | fpscr | FPSCR value to set

Remarks
  - Only for Cortex-M4 and Cortex-M7.
  - The variable __FPU_PRESENT has to be set to 1.

See Also
  - __get_FPSCR
  - Cortex-M Reference Manuals

void __set_MSP | ( | uint32_t | topOfMainStack | ) |

Set the MSP register.

The function sets the Main Stack Pointer (MSP) value using the instruction MSR.
Physically two different stack pointers (SP) exist:

- The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when running exception handlers (handler mode).
- The Process Stack Pointer (PSP), which can be used only in thread mode.

Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:

- =0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded from the first 32-bit word of the vector table from the program memory.
- =1 PSP is the current stack pointer. The initial value is undefined.

Parameters

  [in] | topOfMainStack | MSP value to set

Remarks
  - Only one of the two SPs is visible at a time.
  - For many applications, the system can completely rely on the MSP.
  - The PSP is normally used in designs with an OS where the stack memory for OS Kernel must be separated from the application code.

See Also
  - __get_MSP; __set_PSP; __set_CONTROL
  - Cortex-M Reference Manuals

__set_MSPLIM | ( | uint32_t | MainStackPtrLimit | ) |

Set Main Stack Pointer Limit Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode.

Assigns the given value to the Main Stack Pointer Limit (MSPLIM).

Parameters

  [in] | MainStackPtrLimit | Main Stack Pointer Limit value to set

Note
  Only availabe for Armv8-M Architecture.

void __set_PRIMASK | ( | uint32_t | priMask | ) |

Set the Priority Mask bit.

The function sets the Priority Mask register (PRIMASK) value using the instruction MSR.
PRIMASK is a 1-bit-wide interrupt mask register. When set, it blocks all interrupts apart from the non-maskable interrupt (NMI) and the hard fault exception. The PRIMASK prevents activation of all exceptions with configurable priority.

Parameters

  [in]

  priMask

  Priority Mask
  - =0 no effect
  - =1 prevents the activation of all exceptions with configurable priority

Remarks
  - When set, PRIMASK effectively changes the current priority level to 0. This is the highest programmable level.
  - When set and a fault occurs, the hard fault handler will be executed.
  - Useful for temprorarily disabling all interrupts for timing critical tasks.
  - Does not have the ability to mask BusFault or bypass MPU.

See Also
  - __get_PRIMASK; __set_BASEPRI; __set_FAULTMASK
  - Cortex-M Reference Manuals

void __set_PSP | ( | uint32_t | topOfProcStack | ) |

Set the PSP register.

The function sets the Process Stack Pointer (PSP) value using the instruction MSR.
Physically two different stack pointers (SP) exist:

- The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when running exception handlers (handler mode).
- The Process Stack Pointer (PSP), which can be used only in thread mode.

Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:

- =0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded from the first 32-bit word of the vector table from the program memory.
- =1 PSP is the current stack pointer. The initial value is undefined.

Parameters

  [in] | topOfProcStack | PSP value to set

Remarks
  - Only one of the two SPs is visible at a time.
  - For many applications, the system can completely rely on the MSP.
  - The PSP is normally used in designs with an OS where the stack memory for OS Kernel must be separated from the application code.

See Also
  - __get_PSP; __set_MSP; __set_CONTROL
  - Cortex-M Reference Manuals

void __set_PSPLIM | ( | uint32_t | ProcStackPtrLimit | ) |

Set Process Stack Pointer Limit Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode.

Assigns the given value to the Process Stack Pointer Limit (PSPLIM).

Parameters

  [in] | ProcStackPtrLimit | Process Stack Pointer Limit value to set

Note
  Only availabe for Armv8-M Architecture.