CMSIS-Core (Cortex-A): GICDistributor_Type Struct Reference

| CMSIS-Core (Cortex-A) Version 1.2.0 CMSIS-Core support for Cortex-A processor-based devices

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GICDistributor_Type Struct Reference
Generic Interrupt Controller Functions

Structure type to access the Generic Interrupt Controller Distributor (GICD)

## Data Fields

__IOM uint32_t | CTLR
| Offset: 0x000 (R/W) Distributor Control Register. More...
__IM uint32_t | TYPER
| Offset: 0x004 (R/ ) Interrupt Controller Type Register. More...
__IM uint32_t | IIDR
| Offset: 0x008 (R/ ) Distributor Implementer Identification Register. More...
__IOM uint32_t | STATUSR
| Offset: 0x010 (R/W) Error Reporting Status Register, optional. More...
__OM uint32_t | SETSPI_NSR
| Offset: 0x040 ( /W) Set SPI Register. More...
__OM uint32_t | CLRSPI_NSR
| Offset: 0x048 ( /W) Clear SPI Register. More...
__OM uint32_t | SETSPI_SR
| Offset: 0x050 ( /W) Set SPI, Secure Register. More...
__OM uint32_t | CLRSPI_SR
| Offset: 0x058 ( /W) Clear SPI, Secure Register. More...
__IOM uint32_t | IGROUPR [32]
| Offset: 0x080 (R/W) Interrupt Group Registers. More...
__IOM uint32_t | ISENABLER [32]
| Offset: 0x100 (R/W) Interrupt Set-Enable Registers. More...
__IOM uint32_t | ICENABLER [32]
| Offset: 0x180 (R/W) Interrupt Clear-Enable Registers. More...
__IOM uint32_t | ISPENDR [32]
| Offset: 0x200 (R/W) Interrupt Set-Pending Registers. More...
__IOM uint32_t | ICPENDR [32]
| Offset: 0x280 (R/W) Interrupt Clear-Pending Registers. More...
__IOM uint32_t | ISACTIVER [32]
| Offset: 0x300 (R/W) Interrupt Set-Active Registers. More...
__IOM uint32_t | ICACTIVER [32]
| Offset: 0x380 (R/W) Interrupt Clear-Active Registers. More...
__IOM uint32_t | IPRIORITYR [255]
| Offset: 0x400 (R/W) Interrupt Priority Registers. More...
__IOM uint32_t | ITARGETSR [255]
| Offset: 0x800 (R/W) Interrupt Targets Registers. More...
__IOM uint32_t | ICFGR [64]
| Offset: 0xC00 (R/W) Interrupt Configuration Registers. More...
__IOM uint32_t | IGRPMODR [32]
| Offset: 0xD00 (R/W) Interrupt Group Modifier Registers. More...
__IOM uint32_t | NSACR [64]
| Offset: 0xE00 (R/W) Non-secure Access Control Registers. More...
__OM uint32_t | SGIR
| Offset: 0xF00 ( /W) Software Generated Interrupt Register. More...
__IOM uint32_t | CPENDSGIR [4]
| Offset: 0xF10 (R/W) SGI Clear-Pending Registers. More...
__IOM uint32_t | SPENDSGIR [4]
| Offset: 0xF20 (R/W) SGI Set-Pending Registers. More...
__IOM uint64_t | IROUTER [988]
| Offset: 0x6100(R/W) Interrupt Routing Registers. More...

## Field Documentation

__IO uint32_t GICDistributor_Type::CLRSPI_NSR

Clear Non-secure SPI Pending Register

Bits | Name | Function
--- | --- | ---
[31:10] | - | Reserved.
[9:0] | INTID | The interrupt number to clear pending state from.

__IO uint32_t GICDistributor_Type::CLRSPI_SR

Clear Secure SPI Pending Register

Bits | Name | Function
--- | --- | ---
[31:10] | - | Reserved.
[9:0] | INTID | The interrupt number to clear pending state from.

__IOM uint8_t GICDistributor_Type::CPENDSGIR[16]

SGI Clear-Pending Registers Each register corresponds to one software generated interrupt (SGI).

Reading from this register reveals

- 0 - interrupt is not pending
- 1 - interrupt is pending

Writing to this register causes

- 0 - no effect
- 1 - removes the pending state

__IOM uint32_t GICDistributor_Type::CTLR

Distributor Control Register

When access is Secure, in a system that supports two Security states:

Bits | Name | Function
--- | --- | ---
[31] | RWP | Indicates whether a register write is in progress or not.
[30:8] | - | Reserved.
[7] | EINWF | Enable 1 of N Wakeup Functionality, if available.
[6] | DS | Disable Security.
[5] | ARE_NS | Affinity Routing Enable, Non-secure state.
[4] | ARE_S | Affinity Routing Enable, Secure state.
[3] | - | Reserved.
[2] | EnableGrp1S | Enable Secure Group 1 interrupts.
[1] | EnableGrp1NS | Enable Non-secure Group 1 interrupts.
[0] | EnableGrp0 | Enable Group 0 interrupts.

When access is Non-secure, in a system that supports two Security states:

Bits | Name | Function
--- | --- | ---
[31] | RWP | Indicates whether a register write is in progress or not.
[30:5] | - | Reserved.
[4] | ARE_NS | Affinity Routing Enable, Non-secure state.
[3:2] | - | Reserved.
[1] | EnableGrp1A | Enable Non-secure Group 1 interrupts.
[0] | EnableGrp1 | Enable Non-secure Group 1 interrupts.

When in a system that supports only a single Security state:

Bits | Name | Function
--- | --- | ---
[31] | RWP | Indicates whether a register write is in progress or not.
[30:8] | - | Reserved.
[7] | EINWF | Enable 1 of N Wakeup Functionality, if available.
[6] | DS | Disable Security.
[5] | - | Reserved.
[4] | ARE | Affinity Routing Enable.
[3:2] | - | Reserved.
[1] | EnableGrp1 | Enable Group 1 interrupts.
[0] | EnableGrp0 | Enable Group 0 interrupts.

__IOM uint32_t GICDistributor_Type::ICACTIVER[32]

Interrupt Clear-Active Registers

Each bit corresponds to one interrupt:

- Register index is given by INTID/32
- Bit number is given by INTID%32

Note
  Bits corresponding to unimplemented interrupts are RAZ/WI.

__IOM uint32_t GICDistributor_Type::ICENABLER[32]

Interrupt Clear-Enable Registers

Each bit corresponds to one interrupt:

- Register index is given by INTID/32
- Bit number is given by INTID%32

Note
  Bits corresponding to unimplemented interrupts are RAZ/WI.

__IOM uint32_t GICDistributor_Type::ICFGR[64]

Interrupt Configuration Registers

Each interrupt can be configured by two corresponding bits:

Bits | Name | Function
--- | --- | ---
[2*INTID%16+1] | Edge | Interrupt is: 0 - level sensitive, 1 - edge triggered
[2*INTID%16] | Model | 0 - N-N Model, 1 - 1-N Model; RAZ/WI when unsupported

__IOM uint32_t GICDistributor_Type::ICPENDR[32]

Interrupt Clear-Pending Registers

Each bit corresponds to one interrupt:

- Register index is given by INTID/32
- Bit number is given by INTID%32

Note
  Bits corresponding to unimplemented interrupts are RAZ/WI.

__IOM uint32_t GICDistributor_Type::IGROUPR[32]

Interrupt Group Registers

Each bit corresponds to one interrupt:

- Register index is given by INTID/32
- Bit number is given by INTID%32

And the value denotes:

- 0 When CTLR.DS==1, the corresponding interrupt is Group 0
  When CTLR.DS==0, the corresponding interrupt is Secure.
- 1 When CTLR.DS==1, the corresponding interrupt is Group 1.
  When CTLR.DS==0, the corresponding interrupt is Non-secure Group 1.

__IOM uint32_t GICDistributor_Type::IGRPMODR[32]

Interrupt Group Modifier Registers

Each bit corresponds to one interrupt:

- Register index is given by INTID/32
- Bit number is given by INTID%32

__IM uint32_t GICDistributor_Type::IIDR

Distributor Implementer Identification Register

Bits | Name | Function
--- | --- | ---
[31:24] | ProductID | An IMPLEMENTATION DEFINED product identifier
[23:20] | - | Reserved.
[19:16] | Variant | An IMPLEMENTATION DEFINED variant number.
[15:12] | Revision | An IMPLEMENTATION DEFINED revision number.
[11:0] | Implementer | Contains the JEP106 code of the company implemented the GICD.

__IOM uint8_t GICDistributor_Type::IPRIORITYR[1020]

Interrupt Priority Registers

A GIC might implement fewer than eight priority bits, but must implement at least bits [7:4] of each field. In each field, unimplemented bits are RAZ/WI.

Note
  A register field corresponding to an unimplemented interrupt is RAZ/WI.

__IOM uint64_t GICDistributor_Type::IROUTER[988]

Interrupt Routing Registers

Bits | Name | Function
--- | --- | ---
[63:40] | - | Reserved.
[39:32] | Aff3 | Affinity level 3, the least significant affinity level field.
[31] | IRM | Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy.
[30:24] | - | Reserved.
[23:16] | Aff2 | Affinity level 2, an intermediate affinity level field.
[15:8] | Aff1 | Affinity level 1, an intermediate affinity level field.
[7:0] | Aff0 | Affinity level 0, the most significant affinity level field.

__IOM uint32_t GICDistributor_Type::ISACTIVER[32]

Interrupt Set-Active Registers

Each bit corresponds to one interrupt:

- Register index is given by INTID/32
- Bit number is given by INTID%32

Note
  Bits corresponding to unimplemented interrupts are RAZ/WI.

__IOM uint32_t GICDistributor_Type::ISENABLER[32]

Interrupt Set-Enable Registers

Each bit corresponds to one interrupt:

- Register index is given by INTID/32
- Bit number is given by INTID%32

Note
  Bits corresponding to unimplemented interrupts are RAZ/WI.

__IOM uint32_t GICDistributor_Type::ISPENDR[32]

Interrupt Set-Pending Registers

Each bit corresponds to one interrupt:

- Register index is given by INTID/32
- Bit number is given by INTID%32

Note
  Bits corresponding to unimplemented interrupts are RAZ/WI.

__IOM uint8_t GICDistributor_Type::ITARGETSR[1020]

Interrupt Processor Targets Registers

Each bit in the target field corresponds to one CPU interface. A CPU targets field bit that corresponds to an unimplemented CPU interface is RAZ/WI.

CPU target field value | Interrupt targets
--- | ---
0bxxxxxxx1 | CPU interface 0
0bxxxxxx1x | CPU interface 1
0bxxxxx1xx | CPU interface 2
0bxxxx1xxx | CPU interface 3
0bxxx1xxxx | CPU interface 4
0bxx1xxxxx | CPU interface 5
0bx1xxxxxx | CPU interface 6
0b1xxxxxxx | CPU interface 7

__IOM uint32_t GICDistributor_Type::NSACR[64]

Non-secure Access Control Registers

Each two bits corresponds to one interrupt:

- Register index is given by INTID/16
- Bit number is given by 2*INTID%16

The possible values of each 2-bit field are:

- 00 - Non-secure accesses to all fields associated with the corresponding interrupt are permitted.
- 01 - Non-secure accesses are only permitted to requesting fields.
- 10 - As 01, additionally accesses to clearing field are permitted.
- 11 - As 10, additionally accesses to target and routing fields are permitted.

__IO uint32_t GICDistributor_Type::SETSPI_NSR

Set Non-secure SPI Pending Register

Bits | Name | Function
--- | --- | ---
[31:10] | - | Reserved.
[9:0] | INTID | The interrupt number to set pending state for.

__IO uint32_t GICDistributor_Type::SETSPI_SR

Set Secure SPI Pending Register

Bits | Name | Function
--- | --- | ---
[31:10] | - | Reserved.
[9:0] | INTID | The interrupt number to set pending state for.

__OM uint32_t GICDistributor_Type::SGIR

Software Generated Interrupt Register

Bits | Name | Function
--- | --- | ---
[31:26] | - | Reserved.
[25:24] | TargetFilterList | Determines how the Distributor processes the requested SGI.
[23:16] | CPUTargetList | When TargetListFilter is 00, this field defines the CPU interfaces to which the Distributor must forward the interrupt.
[15] | NSATT | Specifies the required group of the SGI.
[14:4] | - | Reserved.
[3:0] | INTID | The INTID of the SGI to forward to the specified CPU interfaces.

Refer to ITARGETSR for details on TargetFilterList field.

__IOM uint8_t GICDistributor_Type::SPENDSGIR[16]

SGI Set-Pending Registers Each register corresponds to one software generated interrupt (SGI).

Reading from this register reveals

- 0 - interrupt is not pending
- 1 - interrupt is pending

Writing to this register causes

- 0 - no effect
- 1 - adds the pending state

__IOM uint32_t GICDistributor_Type::STATUSR

Error Reporting Status Register

Bits | Name | Function
--- | --- | ---
[31:4] | - | Reserved.
[3] | WROD | Write to an RO location.
[2] | RWOD | Read of a WO location.
[1] | WRD | Write to a reserved location.
[0] | RRD | Read of a reserved location.

__IM uint32_t GICDistributor_Type::TYPER

Interrupt Controller Type Register

Bits | Name | Function
--- | --- | ---
[31:16] | - | Reserved.
[15:11] | LSPI | Maximum number of lockable shared interrupts.
[10] | SecurityExtn | Security Extensions: 0 - not implemented. 1 - implemented.
[9:8] | - | Reserved.
[7:5] | CPUNumber | Number of implemented CPU interfaces [=CPUNumber+1]
[4:0] | ITLinesNumber | Maximum number of interrups supported [=32*(ITLinesNumber+1)].