CMSIS-Core (Cortex-A): Core Register Access

| CMSIS-Core (Cortex-A) Version 1.2.0 CMSIS-Core support for Cortex-A processor-based devices

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Core Register Access

Functions to access the Cortex-A core registers. More...

## Content

| Auxiliary Control Register (ACTLR)
| The ACTLR provides IMPLEMENTATION DEFINED configuration and control options.
| Cache and branch predictor maintenance operations
| This section describes the cache and branch predictor maintenance operations.
| Configuration Base Address Register (CBAR)
| Takes the physical base address value of the memory-mapped SCU peripherals at reset from the external signal PERIPHBASE[31:13].
| Coprocessor Access Control Register (CPACR)
| The CPACR controls access to coprocessors CP0 to CP13.
| Current Program Status Register (CPSR)
| The Current Program Status Register (CPSR) holds processor status and control information.
| Data Fault Status Register (DFSR)
| The DFSR holds status information about the last data fault.
| Domain Access Control Register (DACR)
| DACR defines the access permission for each of the sixteen memory domains.
| Floating-Point Exception Control register (FPEXC)
| Provides a global enable for the Advanced SIMD and Floating-point (VFP) Extensions, and indicates how the state of these extensions is recorded.
| Floating-point Status and Control Register (FPSCR)
| Provides floating-point system status information and control.
| Instruction Fault Status Register (IFSR)
| The IFSR holds status information about the last instruction fault.
| Interrupt Status Register (ISR)
| The ISR shows whether an IRQ, FIQ, or external abort is pending.
| Multiprocessor Affinity Register (MPIDR)
| In a multiprocessor system, the MPIDR provides an additional processor identification mechanism for scheduling purposes, and indicates whether the implementation includes the Multiprocessing Extensions.
| Counter Frequency register (CNTFRQ)
| Indicates the clock frequency of the system counter.
| PL1 Physical Timer Control register (CNTP_CTL)
| The control register for the physical timer.
| PL1 Physical Timer Compare Value register (CNTP_CVAL)
| Holds the 64-bit compare value for the PL1 physical timer.
| PL1 Physical Timer Value register (CNTP_TVAL)
| Holds the timer value for the PL1 physical timer.
| PL1 Physical Count register (CNTPCT)
| Holds the 64-bit physical count value.
| Stack Pointer (SP/R13)
| The processor uses SP as a pointer to the active stack.
| System Control Register (SCTLR)
| The SCTLR provides the top level control of the system, including its memory system.
| TLB maintenance operations
| This section describes the TLB operations that are implemented on all Armv7-A implementations.
| Translation Table Base Registers (TTBR0/TTBR1)
| TTBRn holds the base address of translation table n, and information about the memory it occupies.
| Vector Base Address Register (VBAR)
| When high exception vectors are not selected, the VBAR holds the exception base address for exceptions that are not taken to Monitor mode or to Hyp mode.
| Monitor Vector Base Address Register (MVBAR)
| The MVBAR holds the exception base address for all exceptions that are taken to Monitor mode.

## Description