Added Cortex-M35P to documentation.

CMSIS/DoxyGen/Core/src/Overview.txt

@@ -82,6 +82,12 @@ The \ref templates_pg supplied by Arm have been tested and verified with the fol
       <th>Version</th>
       <th>Description</th>
     </tr>
+    <tr>
+      <td>V5.4.1</td>
+      <td>
+        Added: Cortex-M35P support.\n
+      </td>
+    </tr>
     <tr>
       <td>V5.1.2</td>
       <td>

CMSIS/DoxyGen/Core/src/Ref_VersionControl.txt

@@ -45,6 +45,7 @@ Possible values are:
  - 7 for a Cortex-M7
  - 23 for a Cortex-M23
  - 33 for a Cortex-M33
+ - 35 for a Cortex-M35P
  
 This define is only available for Cortex-M class controllers.
 <b>Code Example:</b>

CMSIS/DoxyGen/Core/src/Template.txt

@@ -30,6 +30,7 @@ core_cm4.h       | for the Cortex-M4 processor
 core_cm7.h       | for the Cortex-M7 processor
 core_cm23.h      | for the Cortex-M23 processor
 core_cm33.h      | for the Cortex-M33 processor
+core_cm35p.h     | for the Cortex-M35P processor
 core_sc000.h     | for the SecurCore SC000 processor
 core_sc300.h     | for the SecurCore SC300 processor
 core_armv8mbl.h  | for the Armv8-M Baseline processor
@@ -40,32 +41,36 @@ core_armv8mml.h  | for the Armv8-M Mainline processor
 The CMSIS Software Pack defines several devices that are based on the various processors. The device related CMSIS-Core files are in the directory .\\Device\\ARM
 and include CMSIS-Core processor file explained before. The following sample devices are defined in the CMSIS-Pack description file <b>ARM.CMSIS.pdsc</b>:
 
-Family             | Device            | Description
-:------------------|:------------------|:---------------------------------
-ARM Cortex-M0      | ARMCM0            | Cortex-M0 based device
-ARM Cortex-M0 plus | ARMCM0P           | Cortex-M0+ based device
-ARM Cortex-M3      | ARMCM3            | Cortex-M3 based device
-ARM Cortex-M4      | ARMCM4            | Cortex-M4 based device without floating-point hardware
-ARM Cortex-M4      | ARMCM4_FP         | Cortex-M4 based device with floating-point hardware
-ARM Cortex-M7      | ARMCM7            | Cortex-M4 based device without floating-point hardware
-ARM Cortex-M7      | ARMCM7_FP         | Cortex-M7 based device with single precision floating-point unit (FPU)
-ARM Cortex-M7      | ARMCM7_DP         | Cortex-M7 based device with double precision floating-point unit
-ARM Cortex-M7      | ARMCM7            | Cortex-M7 based device without floating-point hardware
-ARM Cortex-M23     | ARMCM23           | Cortex-M23 based device without TrustZone
-ARM Cortex-M23     | ARMCM23_TZ        | Cortex-M23 based device with TrustZone
-ARM Cortex-M33     | ARMCM33           | Cortex-M33 based device without TrustZone, SIMD, FPU
-ARM Cortex-M33     | ARMCM33_TZ        | Cortex-M33 based device with TrustZone, no SIMD, no FPU
-ARM Cortex-M33     | ARMCM33_DSP_FP    | Cortex-M23 based device with SIMD, FPU, no TrustZone
-ARM Cortex-M33     | ARMCM33_DSP_FP_TZ | Cortex-M23 based device with TrustZone, SIMD, FPU
-ARM SC000          | ARM SC000         | SC000 based device
-ARM SC300          | ARM SC300         | SC300 based device
-ARMv8-M Baseline   | ARMv8MBL          | Armv8-M Baseline based device with TrustZone
-ARMv8-M Mainline   | ARMv8MML          | Armv8-M Mainline based device with TrustZone
-ARMv8-M Mainline   | ARMv8MML_DP       | Armv8-M Mainline based device with TrustZone and double precision FPU 
-ARMv8-M Mainline   | ARMv8MML_SP       | Armv8-M Mainline based device with TrustZone and single precision FPU 
-ARMv8-M Mainline   | ARMv8MML_DSP      | Armv8-M Mainline based device with TrustZone and SIMD
-ARMv8-M Mainline   | ARMv8MML_DSP_DP   | Armv8-M Mainline based device with TrustZone, SIMD, and double precision FPU 
-ARMv8-M Mainline   | ARMv8MML_DSP_SP   | Armv8-M Mainline based device with TrustZone, SIMD, and single precision FPU 
+Family             | Device             | Description
+:------------------|:-------------------|:---------------------------------
+ARM Cortex-M0      | ARMCM0             | Cortex-M0 based device
+ARM Cortex-M0 plus | ARMCM0P            | Cortex-M0+ based device
+ARM Cortex-M3      | ARMCM3             | Cortex-M3 based device
+ARM Cortex-M4      | ARMCM4             | Cortex-M4 based device without floating-point hardware
+ARM Cortex-M4      | ARMCM4_FP          | Cortex-M4 based device with floating-point hardware
+ARM Cortex-M7      | ARMCM7             | Cortex-M4 based device without floating-point hardware
+ARM Cortex-M7      | ARMCM7_FP          | Cortex-M7 based device with single precision floating-point unit (FPU)
+ARM Cortex-M7      | ARMCM7_DP          | Cortex-M7 based device with double precision floating-point unit
+ARM Cortex-M7      | ARMCM7             | Cortex-M7 based device without floating-point hardware
+ARM Cortex-M23     | ARMCM23            | Cortex-M23 based device without TrustZone
+ARM Cortex-M23     | ARMCM23_TZ         | Cortex-M23 based device with TrustZone
+ARM Cortex-M33     | ARMCM33            | Cortex-M33 based device without TrustZone, SIMD, FPU
+ARM Cortex-M33     | ARMCM33_TZ         | Cortex-M33 based device with TrustZone, no SIMD, no FPU
+ARM Cortex-M33     | ARMCM33_DSP_FP     | Cortex-M33 based device with SIMD, FPU, no TrustZone
+ARM Cortex-M33     | ARMCM33_DSP_FP_TZ  | Cortex-M33 based device with TrustZone, SIMD, FPU
+ARM Cortex-M35P    | ARMCM35P           | Cortex-M35P based device without TrustZone, SIMD, FPU
+ARM Cortex-M35P    | ARMCM35P_TZ        | Cortex-M35P based device with TrustZone, no SIMD, no FPU
+ARM Cortex-M35P    | ARMCM35P_DSP_FP    | Cortex-M35P based device with SIMD, FPU, no TrustZone
+ARM Cortex-M35P    | ARMCM35P_DSP_FP_TZ | Cortex-M35P based device with TrustZone, SIMD, FPU
+ARM SC000          | ARM SC000          | SC000 based device
+ARM SC300          | ARM SC300          | SC300 based device
+ARMv8-M Baseline   | ARMv8MBL           | Armv8-M Baseline based device with TrustZone
+ARMv8-M Mainline   | ARMv8MML           | Armv8-M Mainline based device with TrustZone
+ARMv8-M Mainline   | ARMv8MML_DP        | Armv8-M Mainline based device with TrustZone and double precision FPU 
+ARMv8-M Mainline   | ARMv8MML_SP        | Armv8-M Mainline based device with TrustZone and single precision FPU 
+ARMv8-M Mainline   | ARMv8MML_DSP       | Armv8-M Mainline based device with TrustZone and SIMD
+ARMv8-M Mainline   | ARMv8MML_DSP_DP    | Armv8-M Mainline based device with TrustZone, SIMD, and double precision FPU 
+ARMv8-M Mainline   | ARMv8MML_DSP_SP    | Armv8-M Mainline based device with TrustZone, SIMD, and single precision FPU 
 
 
 \section template_files_sec Template Files
@@ -639,7 +644,7 @@ If these <i>\#defines</i> are missing default values are used.
     </tr>
 </table>
 
-\b core_CM33.h or \b core_ARMv8MML.h
+\b core_CM33.h or \b core_cm35p.h or \b core_ARMv8MML.h
 <table class="cmtable">
     <tr>
       <th>\#define</th>

CMSIS/DoxyGen/General/src/introduction.txt

@@ -20,8 +20,8 @@ including <a class="el" href="http://www.arm.com/products/processors/technologie
 \anchor CM_Components
 The CMSIS components are:
  - <a href="../../Core/html/index.html"><b>CMSIS-Core (Cortex-M)</b></a>: API for the Cortex-M processor core and peripherals. 
-   It provides a standardized interface for Cortex-M0, Cortex-M0+, Cortex-M3, Cortex-M4, Cortex-M7, Cortex-M23, Cortex-M33, SC000, and SC300. 
-   Also included are SIMD intrinsic functions for Cortex-M4, Cortex-M7, and Cortex-M33 SIMD instructions.
+   It provides a standardized interface for Cortex-M0, Cortex-M0+, Cortex-M3, Cortex-M4, Cortex-M7, Cortex-M23, Cortex-M33, Cortex-M35P, SC000, and SC300. 
+   Also included are SIMD intrinsic functions for Cortex-M4, Cortex-M7, Cortex-M33 and Cortex-M35P SIMD instructions.
 
  - <a href="../../Core_A/html/index.html"><b>CMSIS-Core (Cortex-A)</b></a>: API and basic run-time system for the Cortex-A5/A7/A9 processor core and peripherals. 
    
@@ -29,7 +29,7 @@ The CMSIS components are:
     and connects microcontroller peripherals with middleware that implements for example communication stacks, file systems, or graphic user interfaces.
 
  - <a href="../../DSP/html/index.html"><b>CMSIS-DSP</b></a>: DSP Library Collection with over 60 Functions for various data types: fixed-point (fractional q7, q15, q31) and single precision floating-point (32-bit).
-   The library is available for all Cortex-M cores. Implementations that are optimized for the SIMD instruction set are available for Cortex-M4, Cortex-M7, and Cortex-M33.
+   The library is available for all Cortex-M cores. Implementations that are optimized for the SIMD instruction set are available for Cortex-M4, Cortex-M7, Cortex-M33 and Cortex-M35P.
    
  - <a href="../../NN/html/index.html"><b>CMSIS-NN</b></a>: CMSIS-NN is a collection of efficient neural network kernels developed to maximize the performance and minimize the memory footprint of neural networks on Cortex-M processor cores.
  

CMSIS/DoxyGen/Pack/src/General.txt

@@ -84,6 +84,7 @@ Files relevant to CMSIS-Pack are present in the following \b ARM::CMSIS director
 - new \ref DebugFunctions "debug access functions" and \ref DebugVars "global debug variables" for sequence-based flash download
 - added \ref element_repository "repository" element for specifying origin of public repositories
 - added attributes to \ref element_release "release" element specifying repository tag and url for downloading repository content
+- added new processor Cortex-M35P
     </td>
   </tr>
   <tr>

CMSIS/DoxyGen/Pack/src/devices_schema.txt

@@ -2164,6 +2164,10 @@ These values can be used in the elements:
     <td class="XML-Token">Cortex-M33</td>
     <td><a href="http://developer.arm.com/products/processors/cortex-m/cortex-m33" target="_blank">Arm Cortex-M33</a> processor based device</td>
   </tr>
+  <tr>
+    <td class="XML-Token">Cortex-M35P</td>
+    <td><a href="http://developer.arm.com/products/processors/cortex-m/cortex-m35p" target="_blank">Arm Cortex-M35P</a> processor based device</td>
+  </tr>
   <tr>
     <td class="XML-Token">SC000</td>
     <td>SecurCore <a href="http://developer.arm.com/products/processors/cortex-m/sc000-processor" target="_blank">SC000</a> based on technology of Cortex-M0.</td>

CMSIS/DoxyGen/Pack/src/sdf_schema.txt

@@ -851,7 +851,7 @@ Depending on the context, a device type can be one of the following types:
    be a vendor-specific core type, or an older JTAG ARM core. Current cores are: \n
    "Cortex-A5", "Cortex-A7", "Cortex-A8", "Cortex-A9", "Cortex-A12", "Cortex-A15", "Cortex-A17", "Cortex-A32", "Cortex-A35",
    "Cortex-A53", "Cortex-A57", "Cortex-A72", "Cortex-A73", "Cortex-M0", "Cortex-M0+", "Cortex-M0+_JTAG-AP", "Cortex-M1",
-   "Cortex-M23", "Cortex-M3", "Cortex-M33", "Cortex-M3_JTAG-AP", "Cortex-M4", "Cortex-M7", "Cortex-R4", "Cortex-R5",
+   "Cortex-M23", "Cortex-M3", "Cortex-M33", "Cortex-M35P", "Cortex-M3_JTAG-AP", "Cortex-M4", "Cortex-M7", "Cortex-R4", "Cortex-R5",
    "Cortex-R7", "Cortex-R8", "Cortex-R52", "SC000", "SC100D", "SC200D", "SC300", "ThunderX", "ThunderX-r2", "ARMV8MBL",
    "ARMV8MML", "88FR101", "88FR111", "88FR331", "88SV581x-v7_PJ4", "88SV581x-v7_PJ4_TZ", "ARM1136JF-S",
    "ARM1136JF-S_JTAG-AP", "ARM1156T2F-S", "ARM1156T2F-S_JTAG-AP", "ARM1176JZF-S", "ARM1176JZF-S_JTAG-AP", "ARM11MPCore",

CMSIS/DoxyGen/RTOS2/src/cmsis_os2.txt

@@ -176,7 +176,7 @@ SysTick | lowest   | Kernel system timer interrupt to generate periodic timer ti
 PendSV  | lowest   | PendSV (request for system-level service) when calling certain RTX functions from \b Handler mode
 SCV     | lowest+1 | Supervisor Call used to enter the RTOS kernel from \b Thread mode
 
-Other device interrupts can be used without limitation. For Arm Cortex-M3/M4/M7/M23/M33 processors, interrupts are never disabled by RTX Kernel.
+Other device interrupts can be used without limitation. For Arm Cortex-M3/M4/M7/M23/M33/M35P processors, interrupts are never disabled by RTX Kernel.
 
 <b>Usage of interrupt priority grouping</b>
 - The interrupt priority grouping should be configured using the CMSIS-Core function NVIC_SetPriorityGrouping before calling the function 
@@ -1142,7 +1142,7 @@ The interface files to the processor hardware are:
 \note
  - The CMSIS-Core variable \c SystemCoreClock is used to configure the SysTick timer. 
 
-\subsection tpCortexM3_M4_M7_M33 Cortex-M3/M4/M7/M33 target processor
+\subsection tpCortexM3_M4_M7_M33_M35P Cortex-M3/M4/M7/M33/M35P target processor
 
 
 Hardware Requirement       | Description
@@ -1157,7 +1157,7 @@ LDREX, STREX instruction   | Atomic execution avoids the requirement to disable
 The interface files to the processor hardware are: 
  - <b>%irq_cm3.s</b> defines exception handlers for Cortex-M3 and Cortex-M4/M7 without floating point unit.
  - <b>%irq_cm4f.s</b> defines exception handlers for Cortex-M4/M7 with floating point unit.
- - <b>%irq_armv8mml_common.s</b> defines exception handlers for Cortex-M33
+ - <b>%irq_armv8mml_common.s</b> defines exception handlers for Cortex-M33/M35P
  - <b>%rtx_core_cm.h</b> defines processor specific helper functions and the interfaces to Core Registers and Core Peripherals.
  - <b>%os_tick.h</b> is the \ref CMSIS_RTOS_TickAPI that defines the interface functions to the SysTick timer.
 
@@ -1281,7 +1281,7 @@ The CMSIS-RTOS RTX v5 is delivered in source code and several examples are provi
 \section libFiles RTX v5 Library Files
 
 The CMSIS-RTOS RTX Library is available pre-compiled for ARMCC and GCC compilers and supports all Cortex-M
-processor variants in every configuration, including Arm Cortex-M23 and Cortex-M33.
+processor variants in every configuration, including Arm Cortex-M23, Cortex-M33 and Cortex-M35P.
 
 <table class="cmtable" summary="CMSIS-RTOS RTX Library Files">
     <tr>
@@ -1824,8 +1824,8 @@ The functions that call the Event Recorder are in the module \em rtx_evr.c and t
 \page functionOverview Function Overview
 
 CMSIS-RTOS2 provides multiple API interfaces:
-  - \subpage rtos_api2 is the new C function interface that supports dynamic object creation and Armv8-M (Arm Cortex-M23 and
-    Cortex-M33).
+  - \subpage rtos_api2 is the new C function interface that supports dynamic object creation and Armv8-M (Arm Cortex-M23,
+    Cortex-M33 and Cortex-M35P).
   - <a class="el" href="../../RTOS/html/functionOverview.html">CMSIS-RTOS C API v1</a> is a C function API that is backward
     compatible with CMSIS-RTOS v1.
   - \subpage rtos_apicpp is a C++ class function API (future extension).

CMSIS/DoxyGen/SVD/src/svd_schema.txt

@@ -335,6 +335,7 @@ to configure the priority of an interrupt. It is equipped with the standard Syst
         - \token{CM23}: Arm Cortex-M23
         - \token{CM3}: Arm Cortex-M3
         - \token{CM33}: Arm Cortex-M33
+        - \token{CM35P}: Arm Cortex-M35P
         - \token{SC300}: Arm Secure Core SC300
         - \token{CM4}: Arm Cortex-M4
         - \token{CM7}: Arm Cortex-M7
@@ -377,7 +378,7 @@ to configure the priority of an interrupt. It is equipped with the standard Syst
     </tr>
     <tr>
         <td>fpuPresent </td>
-        <td>Indicate whether the processor is equipped with a hardware floating point unit (FPU). Cortex-M4, Cortex-M7 and Cortex-M33 are the only available Cortex-M processor with an optional FPU. This tag is either set to \token{true} or \token{false}, \token{1} or \token{0}.</td>
+        <td>Indicate whether the processor is equipped with a hardware floating point unit (FPU). Cortex-M4, Cortex-M7, Cortex-M33 and Cortex-M35P are the only available Cortex-M processor with an optional FPU. This tag is either set to \token{true} or \token{false}, \token{1} or \token{0}.</td>
         <td>boolean </td>
         <td>1..1 </td>
     </tr>
@@ -389,8 +390,8 @@ to configure the priority of an interrupt. It is equipped with the standard Syst
     </tr>
     <tr>
         <td>dspPresent </td>
-        <td>Indicates whether the processor implements the optional SIMD DSP extensions (DSP). Cortex-M33 is the only available Cortex-M processor with an optional DSP extension. For ARMv7M SIMD DSP extensions are
-        a mandatory part of Cortex-M4 and Cortex-M7. This tag is either set to \token{true} or \token{false}, \token{1} or \token{0}.</td>. This element is mandatory for Cortex-M33 and future processors with optional
+        <td>Indicates whether the processor implements the optional SIMD DSP extensions (DSP). Cortex-M33 and Cortex-M35P are the only available Cortex-M processor with an optional DSP extension. For ARMv7M SIMD DSP extensions are
+        a mandatory part of Cortex-M4 and Cortex-M7. This tag is either set to \token{true} or \token{false}, \token{1} or \token{0}.</td>. This element is mandatory for Cortex-M33, Cortex-M35P and future processors with optional
         SIMD DSP instruction set.
         <td>boolean </td>
         <td>0..1 </td>

CMSIS/Utilities/CMSIS-SVD.xsd

@@ -1,44 +1,47 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- 
- 
+<!--
+
   Copyright (c) 2013-2016 ARM Limited. All rights reserved.
- 
+
   SPDX-License-Identifier: Apache-2.0
- 
+
   Licensed under the Apache License, Version 2.0 (the License); you may
   not use this file except in compliance with the License.
   You may obtain a copy of the License at
- 
+
   www.apache.org/licenses/LICENSE-2.0
- 
+
   Unless required by applicable law or agreed to in writing, software
   distributed under the License is distributed on an AS IS BASIS, WITHOUT
   WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
   See the License for the specific language governing permissions and
   limitations under the License.
- 
-  $Date:         03. September 2018
-  $Revision:     1.3.4
+
+  $Date:         04. September 2018
+  $Revision:     1.3.5
+
+  Version 1.3.5:
+  - add CM35P as enumeration value for cpuNameType.
 
   Version 1.3.4:
   - add dspPresent element to cpuType as SIMD instructions became optional for new processors.
-  
+
   Version 1.3.3:
   - update file header to Apache 2.0 License
   - add dimableIdentifierType, as a copy of previous identifierType adding "%s",
   - update identifierType to only allow names without %s included.
   - remove enumerationNameType.
-  - add headerEnumName to enumerationType and to dimArrayIndexType for peripheral arrays 
+  - add headerEnumName to enumerationType and to dimArrayIndexType for peripheral arrays
     overwriting hierarchically generated names
   - add dimName to dimElementGroup. Only valid in <cluster> context, ignored otherwise.
-  
+
   Version 1.3.2:
   adding dimIndexArray to peripheral-, cluster- and register-array to describe
   enumeration of array indices.
 
   Version 1.3.1:
   fixed peripheral name element type to identifierType to support %s for peripheral arrays
-  added optional protection element to addressBlockType and added p=privileged 
+  added optional protection element to addressBlockType and added p=privileged
 
   Version 1.3:
   added dim to peripherals to describe an array of peripherals.
@@ -46,16 +49,16 @@
   added protection element as part of the registerPropertiesGroup indicating
   special permissions are required for accessing a register.
   CPU Section extended with description of the Secure Attribution Unit.
-  
+
   Version 1.2:
   Cortex-M7 support items have been added as optional tags for the device header file generation:
   fpuDP, icachePresent, dcachePresent, itcmPresent, dtcmPresent
-  
+
   Version 1.1:
   For backward compatibility all additional tags have been made optional.
   Extensions may be mandatory for successful device header file generation
   Other changes are related to some restructuring of the schema.
-  
+
   Note that the memory section has been removed since this would limit the
   reuse of descriptions for a series of devices.
  -->
@@ -73,7 +76,7 @@
       <xs:pattern value="[\p{IsBasicLatin}\p{IsLatin-1Supplement}]*" />
     </xs:restriction>
   </xs:simpleType>
-  
+
   <!-- cpuType specifies a selection of Cortex-M and Secure-Cores. This list will get extended as new processors are released -->
   <xs:simpleType name="cpuNameType">
     <xs:restriction base="xs:token">
@@ -85,6 +88,7 @@
       <xs:enumeration value="CM23"/>
       <xs:enumeration value="CM3"/>
       <xs:enumeration value="CM33"/>
+      <xs:enumeration value="CM35P"/>
       <xs:enumeration value="SC300"/>
       <xs:enumeration value="CM4"/>
       <xs:enumeration value="CM7"/>
@@ -283,8 +287,8 @@
       <xs:element name="value" type="xs:integer"/>
     </xs:sequence>
   </xs:complexType>
-  <!-- register properties group specifies register size, access permission and reset value 
-       this is used in multiple locations. Settings are inherited downstream. -->  
+  <!-- register properties group specifies register size, access permission and reset value
+       this is used in multiple locations. Settings are inherited downstream. -->
   <xs:group name="registerPropertiesGroup">
     <xs:sequence>
       <xs:element name="size" type="scaledNonNegativeInteger" minOccurs="0"/>
@@ -295,7 +299,7 @@
       <xs:element name="resetMask" type="scaledNonNegativeInteger" minOccurs="0"/>
     </xs:sequence>
   </xs:group>
-  <!-- bitRangeLsbMsbStyle specifies the bit position of a field within a register 
+  <!-- bitRangeLsbMsbStyle specifies the bit position of a field within a register
        by specifying the least significant and the most significant bit position -->
   <xs:group name="bitRangeLsbMsbStyle">
     <xs:sequence>
@@ -308,12 +312,12 @@
   <xs:group name="bitRangeOffsetWidthStyle">
     <xs:sequence>
       <xs:element name="bitOffset" type="scaledNonNegativeInteger"/>
-      <xs:element name="bitWidth" type="scaledNonNegativeInteger" minOccurs="0"/>   
-    </xs:sequence> 
+      <xs:element name="bitWidth" type="scaledNonNegativeInteger" minOccurs="0"/>
+    </xs:sequence>
   </xs:group>
-  
+
   <!-- dimElementGroup specifies the number of array elements (dim), the address offset
-       between to consecutive array elements and an a comma seperated list of strings 
+       between to consecutive array elements and an a comma seperated list of strings
        being used for identifying each element in the array -->
   <xs:group name="dimElementGroup">
     <xs:sequence>
@@ -401,7 +405,7 @@
       </xs:choice>
     </xs:sequence>
   </xs:complexType>
-  
+
   <xs:complexType name="enumerationType">
     <xs:sequence>
       <!-- name specfies a reference to this enumeratedValues section for reuse purposes
@@ -409,7 +413,7 @@
       <xs:element name="name" type="identifierType" minOccurs="0"/>
       <!-- overrides the hierarchical enumeration type in the device header file. User is responsible for uniqueness across description -->
       <xs:element name="headerEnumName" type="identifierType" minOccurs="0"/>
-      <!-- usage specifies whether this enumeration is to be used for read or write or 
+      <!-- usage specifies whether this enumeration is to be used for read or write or
                                                        (read and write) accesses -->
       <xs:element name="usage" type="enumUsageType" minOccurs="0"/>
       <!-- enumeratedValue derivedFrom=<identifierType> -->
@@ -431,7 +435,7 @@
       <!-- name specifies a field's name. The System Viewer and the device header file will
            use the name of the field as identifier -->
       <xs:element name="name" type="dimableIdentifierType"/>
-      <!-- description contains reference manual level information about the function and 
+      <!-- description contains reference manual level information about the function and
            options of a field -->
       <xs:element name="description" type="stringType" minOccurs="0"/>
       <!-- alternative specifications of the bit position of the field within the register -->
@@ -554,16 +558,16 @@
       <xs:element name="alternatePeripheral" type="dimableIdentifierType" minOccurs="0"/>
       <!-- groupName assigns this peripheral to a group of peripherals. This is only used bye the System View -->
       <xs:element name="groupName" type="xs:Name" minOccurs="0"/>
-      <!-- prependToName specifies a prefix that is placed in front of each register name of this peripheral. 
+      <!-- prependToName specifies a prefix that is placed in front of each register name of this peripheral.
                          The device header file will show the registers in a C-Struct of the peripheral without the prefix. -->
       <xs:element name="prependToName" type="identifierType" minOccurs="0"/>
-      <!-- appendToName is a postfix that is appended to each register name of this peripheral. The device header 
+      <!-- appendToName is a postfix that is appended to each register name of this peripheral. The device header
                          file will sho the registers in a C-Struct of the peripheral without the postfix -->
       <xs:element name="appendToName" type="identifierType" minOccurs="0"/>
       <!-- V1.1: headerStructName specifies the name for the peripheral structure typedef
                          used in the device header generation instead of the peripheral name -->
       <xs:element name="headerStructName" type="dimableIdentifierType" minOccurs="0"/>
-      <!-- disableCondition contains a logical expression based on constants and register or bit-field values 
+      <!-- disableCondition contains a logical expression based on constants and register or bit-field values
                          if the condition is evaluated to true, the peripheral display will be disabled -->
       <xs:element name="disableCondition" type="stringType" minOccurs="0"/>
       <!-- baseAddress specifies the absolute base address of a peripheral. For derived peripherals it is mandatory
@@ -572,21 +576,21 @@
       <!-- registerPropertiesGroup elements specify the default values for register size, access permission and
                          reset value. These default values are inherited to all registers contained in this peripheral -->
       <xs:group ref="registerPropertiesGroup" minOccurs="0"/>
-      <!-- addressBlock specifies one or more address ranges that are assigned exclusively to this peripheral. 
+      <!-- addressBlock specifies one or more address ranges that are assigned exclusively to this peripheral.
                          derived peripherals may have no addressBlock, however none-derived peripherals are required to specify
                          at least one address block -->
       <xs:element name="addressBlock" type="addressBlockType" minOccurs="0" maxOccurs="unbounded"/>
       <!-- interrupt specifies can specify one or more interrtupts by name, description and value -->
       <xs:element name="interrupt" type="interruptType" minOccurs="0" maxOccurs="unbounded"/>
       <!-- registers section contains all registers owned by the peripheral. In case a peripheral gets derived it does
-                        not have its own registers section, hence this section is optional. A unique peripheral without a 
+                        not have its own registers section, hence this section is optional. A unique peripheral without a
                         registers section is not allowed -->
       <xs:element name="registers" type="registersType" minOccurs="0" maxOccurs="1">
       </xs:element>
     </xs:sequence>
     <xs:attribute name="derivedFrom" type="dimableIdentifierType" use="optional"/>
   </xs:complexType>
-  
+
   <!-- ==================================================== -->
   <!-- The top level element of a description is the device -->
   <!-- ==================================================== -->
@@ -612,7 +616,7 @@
         <!-- V1.1: the tag specifies the filename without extension of the CMSIS System Device include file.
              This tag is used by the header file generator for customizing the include statement referencing the
              CMSIS system file within the CMSIS device header file. By default the filename is "system_<device.name>"
-             In cases a device series shares a single system header file, the name of the series shall be used 
+             In cases a device series shares a single system header file, the name of the series shall be used
              instead of the individual device name. -->
         <xs:element name="headerSystemFilename" type="identifierType" minOccurs="0"/>
         <!-- V1.1: headerDefinitionPrefix specifies the string being prepended to all names of types defined in