CoreValidation: Separated DS-MDK example projects per target and compiler.

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/.settings/language.settings.xml

@@ -1,25 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<project>
-	<configuration id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1261257010" name="Cortex-A5 (AC5)">
-		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
-			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
-			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
-			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
-			<provider class="com.arm.eclipse.builder.armcc.discovery.ArmCompiler6LanguageSettingsProvider" console="false" env-hash="668963287638" id="com.arm.eclipse.builder.armcc.v6.langprovider" keep-relative-paths="false" name="ARM Compiler 6 Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
-				<language-scope id="org.eclipse.cdt.core.gcc"/>
-				<language-scope id="org.eclipse.cdt.core.g++"/>
-			</provider>
-		</extension>
-	</configuration>
-	<configuration id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1021881951" name="Cortex-A5 (AC6)">
-		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
-			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
-			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
-			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
-			<provider class="com.arm.eclipse.builder.armcc.discovery.ArmCompiler6LanguageSettingsProvider" console="false" env-hash="299109064629967612" id="com.arm.eclipse.builder.armcc.v6.langprovider" keep-relative-paths="false" name="ARM Compiler 6 Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
-				<language-scope id="org.eclipse.cdt.core.gcc"/>
-				<language-scope id="org.eclipse.cdt.core.g++"/>
-			</provider>
-		</extension>
-	</configuration>
-</project>

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/AC5/.cproject

@@ -0,0 +1,152 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1261257010">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1261257010" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1261257010" name="Debug" parent="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6">
+					<folderInfo id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1261257010." name="/" resourcePath="">
+						<toolChain id="com.arm.toolchain.baremetal.base.var.arm_compiler_5-5.1960502218" name="ARM Compiler 5" superClass="com.arm.toolchain.baremetal.base.var.arm_compiler_5-5">
+							<option id="com.arm.toolchain.ac5.option.target.cpu_fpu.1899004868" superClass="com.arm.toolchain.ac5.option.target.cpu_fpu" value="Cortex-A5.VFPv4.Neon" valueType="string"/>
+							<option id="com.arm.toolchain.ac5.option.fppcs.1215240395" name="Floating-point PCS" superClass="com.arm.toolchain.ac5.option.fppcs" value="com.arm.tool.c.compiler.option.fppcs.hard" valueType="enumerated"/>
+							<option id="com.arm.toolchain.ac5.option.inst.391027132" name="Instruction set" superClass="com.arm.toolchain.ac5.option.inst" value="com.arm.tool.c.compiler.option.inst.arm" valueType="enumerated"/>
+							<option id="com.arm.toolchain.ac5.options.libs.useMicroLib.1898820408" name="Use microlib" superClass="com.arm.toolchain.ac5.options.libs.useMicroLib" value="true" valueType="boolean"/>
+							<option id="com.arm.toolchain.ac5.option.endian.2047271088" name="Byte order" superClass="com.arm.toolchain.ac5.option.endian" value="com.arm.tool.c.compiler.option.endian.little" valueType="enumerated"/>
+							<targetPlatform id="com.arm.toolchain.baremetal.base.var.arm_compiler_5-5.1960502218.788792350" name=""/>
+							<builder buildPath="${workspace_loc:/CMSIS_CV}/Debug" id="org.eclipse.cdt.build.core.internal.builder.1105228045" keepEnvironmentInBuildfile="false" name="CDT Internal Builder" superClass="org.eclipse.cdt.build.core.internal.builder"/>
+							<tool id="com.arm.tool.c.compiler.base.var.arm_compiler_5-5.1006008870" name="ARM C Compiler 5" superClass="com.arm.tool.c.compiler.base.var.arm_compiler_5-5">
+								<option id="com.arm.tool.c.compiler.option.incpath.2039211042" name="Include path (-I)" superClass="com.arm.tool.c.compiler.option.incpath" useByScannerDiscovery="false" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/CMSIS/Core_A/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/Device/ARM/ARMCA9/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE/CMSIS_CORE_Validation&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE/Device/ARMCA9&quot;"/>
+								</option>
+								<option id="com.arm.tool.c.compiler.option.defmac.1773701319" name="Define macro (-D)" superClass="com.arm.tool.c.compiler.option.defmac" useByScannerDiscovery="false" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="_RTE_"/>
+									<listOptionValue builtIn="false" value="ARMCA9"/>
+								</option>
+								<option defaultValue="com.arm.tool.c.compiler.option.optlevel.min" id="com.arm.tool.c.compiler.option.optlevel.882659687" name="Optimization level" superClass="com.arm.tool.c.compiler.option.optlevel" useByScannerDiscovery="true" valueType="enumerated"/>
+								<option id="com.arm.tool.c.compiler.option.targetcpu.1426497902" name="Target CPU (--cpu)" superClass="com.arm.tool.c.compiler.option.targetcpu" useByScannerDiscovery="true" value="Cortex-A5.neon" valueType="string"/>
+								<option id="com.arm.tool.c.compiler.option.fppcs.1692296380" name="Floating-point PCS (--apcs)" superClass="com.arm.tool.c.compiler.option.fppcs" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.option.fppcs.hard" valueType="enumerated"/>
+								<option id="com.arm.tool.c.compiler.option.inst.743536123" name="Instruction set" superClass="com.arm.tool.c.compiler.option.inst" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.option.inst.arm" valueType="enumerated"/>
+								<option id="com.arm.tool.c.compiler.option.useMicroLib.829868509" name="Use microlib (-D__MICROLIB)" superClass="com.arm.tool.c.compiler.option.useMicroLib" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								<option id="com.arm.tool.c.compiler.option.implicit.defmac.768550198" name="Implicit Define macros" superClass="com.arm.tool.c.compiler.option.implicit.defmac" useByScannerDiscovery="true" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="_RTE_"/>
+									<listOptionValue builtIn="false" value="ARMCA5"/>
+								</option>
+								<option id="com.arm.tool.c.compiler.option.implicit.incpath.2077192262" name="Implicit Include paths" superClass="com.arm.tool.c.compiler.option.implicit.incpath" useByScannerDiscovery="false" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/CMSIS/Core_A/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/Device/ARM/ARMCA5/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE/CMSIS_CORE_Validation&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE/Device/ARMCA5&quot;"/>
+								</option>
+								<option id="com.arm.tool.c.compiler.option.debug.enableToolSpecificSettings.393339148" name="Enable tool specific settings" superClass="com.arm.tool.c.compiler.option.debug.enableToolSpecificSettings" useByScannerDiscovery="false" value="false" valueType="boolean"/>
+								<option id="com.arm.tool.c.compiler.option.endian.1534570039" name="Byte order" superClass="com.arm.tool.c.compiler.option.endian" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.option.endian.little" valueType="enumerated"/>
+								<option id="com.arm.tool.c.compile.option.lang.1180588084" name="Source language mode" superClass="com.arm.tool.c.compile.option.lang" useByScannerDiscovery="true" value="com.arm.tool.c.compile.option.lang.c99" valueType="enumerated"/>
+								<inputType id="com.arm.tool.c.compiler.input.614264250" superClass="com.arm.tool.c.compiler.input"/>
+								<inputType id="com.arm.tool.cpp.compiler.input.1314721428" superClass="com.arm.tool.cpp.compiler.input"/>
+							</tool>
+							<tool id="com.arm.tool.cpp.compiler.base.var.arm_compiler_5-5.1697853860" name="ARM C++ Compiler 5" superClass="com.arm.tool.cpp.compiler.base.var.arm_compiler_5-5">
+								<option defaultValue="com.arm.tool.c.compiler.option.optlevel.min" id="com.arm.tool.c.compiler.option.optlevel.213031284" name="Optimization level" superClass="com.arm.tool.c.compiler.option.optlevel" valueType="enumerated"/>
+								<option id="com.arm.tool.c.compiler.option.implicit.defmac.794423957" name="Implicit Define macros" superClass="com.arm.tool.c.compiler.option.implicit.defmac" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="_RTE_"/>
+									<listOptionValue builtIn="false" value="ARMCA5"/>
+								</option>
+								<option id="com.arm.tool.c.compiler.option.implicit.incpath.1172356175" name="Implicit Include paths" superClass="com.arm.tool.c.compiler.option.implicit.incpath" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/CMSIS/Core_A/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/Device/ARM/ARMCA5/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE/CMSIS_CORE_Validation&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE/Device/ARMCA5&quot;"/>
+								</option>
+							</tool>
+							<tool id="com.arm.tool.assembler.base.var.arm_compiler_5-5.941503372" name="ARM Assembler 5" superClass="com.arm.tool.assembler.base.var.arm_compiler_5-5">
+								<option id="com.arm.tool.assembler.option.incpath.240180621" name="Include Path (-i)" superClass="com.arm.tool.assembler.option.incpath" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/CMSIS/Core_A/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/Device/ARM/ARMCA9/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE/CMSIS_CORE_Validation&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE/Device/ARMCA9&quot;"/>
+								</option>
+								<option id="com.arm.tool.assembler.option.cpu.6183565" name="Target CPU (--cpu)" superClass="com.arm.tool.assembler.option.cpu" value="Cortex-A5.neon" valueType="string"/>
+								<option id="com.arm.tool.assembler.option.fppcs.1985670947" name="Floating-point PCS (--apcs)" superClass="com.arm.tool.assembler.option.fppcs" value="com.arm.tool.c.compiler.option.fppcs.hard" valueType="enumerated"/>
+								<option id="com.arm.tool.assembler.option.inst.2124977961" name="Instruction set" superClass="com.arm.tool.assembler.option.inst" value="com.arm.tool.c.compiler.option.inst.arm" valueType="enumerated"/>
+								<option id="com.arm.tool.assembler.option.useMicroLib.1202936635" name="Use microlib (--pd &quot;__MICROLIB SETA 1&quot;)" superClass="com.arm.tool.assembler.option.useMicroLib" value="true" valueType="boolean"/>
+								<option id="com.arm.tool.assembler.option.implicit.predefine.1654893854" name="Implicit Predefines" superClass="com.arm.tool.assembler.option.implicit.predefine" valueType="stringList">
+									<listOptionValue builtIn="false" value="_RTE_ SETA 1"/>
+									<listOptionValue builtIn="false" value="ARMCA5 SETA 1"/>
+								</option>
+								<option id="com.arm.tool.assembler.option.implicit.incpath.840007947" name="Implicit Include paths" superClass="com.arm.tool.assembler.option.implicit.incpath" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/CMSIS/Core_A/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/Device/ARM/ARMCA5/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE/CMSIS_CORE_Validation&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE/Device/ARMCA5&quot;"/>
+								</option>
+								<option id="com.arm.tool.assembler.option.endian.938835271" name="Byte order" superClass="com.arm.tool.assembler.option.endian" value="com.arm.tool.c.compiler.option.endian.little" valueType="enumerated"/>
+								<inputType id="com.arm.tool.assembler.input.567242146" superClass="com.arm.tool.assembler.input"/>
+							</tool>
+							<tool id="com.arm.tool.c.linker.base.var.arm_compiler_5-5.1792565798" name="ARM Linker 5" superClass="com.arm.tool.c.linker.base.var.arm_compiler_5-5">
+								<option id="com.arm.tool.c.linker.option.cpu.2055858033" name="Target CPU (--cpu)" superClass="com.arm.tool.c.linker.option.cpu" value="Cortex-A5.neon" valueType="string"/>
+								<option id="com.arm.tool.c.linker.option.useMicroLib.75487761" name="Use microlib" superClass="com.arm.tool.c.linker.option.useMicroLib" value="true" valueType="boolean"/>
+								<option id="com.arm.tool.c.linker.option.scatter.461693819" name="Scatter file (--scatter)" superClass="com.arm.tool.c.linker.option.scatter" value="${workspace_loc:/${ProjName}}/RTE/Device/ARMCA5/ARMCA5.sct" valueType="string"/>
+								<option id="com.arm.tool.c.linker.option.entry.2107333911" name="Image entry point (--entry)" superClass="com.arm.tool.c.linker.option.entry" value="Vectors" valueType="string"/>
+							</tool>
+							<tool id="com.arm.tool.librarian.base.var.arm_compiler_5-5.2146011430" name="ARM Librarian 5" superClass="com.arm.tool.librarian.base.var.arm_compiler_5-5"/>
+						</toolChain>
+					</folderInfo>
+					<sourceEntries>
+						<entry excluding="RTE/Device/ARMCA9/system_ARMCA9.h|RTE/Device/ARMCA9/system_ARMCA9.c|RTE/Device/ARMCA9/startup_ARMCA9.c|RTE/Device/ARMCA9/mmu_ARMCA9.c|RTE/Device/ARMCA9/mem_ARMCA9.h|RTE/Device/ARMCA9/ARMCA9.sct" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+					</sourceEntries>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="CMSIS_CV.com.arm.eclipse.build.project.v6.exe.base.var.arm_compiler_6-6.420431336" name="Executable" projectType="com.arm.eclipse.build.project.v6.exe.base.var.arm_compiler_6-6"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+	<storageModule moduleId="com.arm.cmsis.project">
+		<rteConfig name="CMSIS_CV_CA5_AC5.rteconfig"/>
+		<toolChainAdapter id="com.arm.cmsis.pack.build.armcc5.Armcc5ToolChainAdapter" name="Adapter for ARM C/C++ 5.x and 6.x toolchains"/>
+		<device Dcore="Cortex-A5" DcoreVersion="r0p1" Dendian="Little-endian" Dfamily="ARM Cortex A5" Dfpu="SP_FPU" Dmpu="MPU" Dname="ARMCA5" Dvendor="ARM:82" Pname=""/>
+		<files>
+			<file name="RTE/Device/ARMCA9/ARMCA9.sct" version="1.0.0"/>
+			<file name="RTE/Device/ARMCA5/ARMCA5.sct" version="1.0.0"/>
+			<file name="RTE/CMSIS_CORE_Validation/CV_Config.h" version="1.0.0"/>
+			<file name="RTE/Device/ARMCA5/mmu_ARMCA5.c" version="1.0.0"/>
+			<file name="RTE/Device/ARMCA5/system_ARMCA5.c" version="1.0.0"/>
+			<file name="RTE/Device/ARMCA9/mem_ARMCA9.h" version="1.0.0"/>
+			<file name="RTE/Device/ARMCA5/system_ARMCA5.h" version="1.0.0"/>
+			<file name="RTE/Device/ARMCA9/startup_ARMCA9.c" version="1.0.0"/>
+			<file name="RTE/Device/ARMCA5/mem_ARMCA5.h" version="1.0.0"/>
+			<file name="RTE/Device/ARMCA9/system_ARMCA9.c" version="1.0.0"/>
+			<file name="RTE/Device/ARMCA5/startup_ARMCA5.c" version="1.0.0"/>
+			<file name="RTE/Device/ARMCA9/system_ARMCA9.h" version="1.0.0"/>
+			<file name="RTE/Device/ARMCA9/mmu_ARMCA9.c" version="1.0.0"/>
+		</files>
+	</storageModule>
+	<storageModule moduleId="com.arm.projectSettings" version="5.25"/>
+	<storageModule moduleId="refreshScope" versionNumber="2">
+		<configuration configurationName="Debug">
+			<resource resourceType="PROJECT" workspacePath="/CMSIS_CV"/>
+		</configuration>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+</cproject>

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/AC5/.gitignore

@@ -0,0 +1 @@
+/Debug/

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/.project → CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/AC5/.project

@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <projectDescription>
-	<name>CMSIS_CV</name>
+	<name>CMSIS_CV_CA5_AC5</name>
 	<comment></comment>
 	<projects>
 	</projects>
@@ -56,10 +56,4 @@
 			<locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS/5.1.1-dev1/CMSIS/Core_A/Source/irq_ctrl_gic.c</locationURI>
 		</link>
 	</linkedResources>
-	<variableList>
-		<variable>
-			<name>cmsis_pack_root</name>
-			<value>file:/C:/tools/Keil_v5/ARM/PACK</value>
-		</variable>
-	</variableList>
 </projectDescription>

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/AC5/.settings/language.settings.xml

@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+	<configuration id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1261257010" name="Debug">
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+			<provider class="com.arm.eclipse.builder.armcc.discovery.ArmCompiler5LanguageSettingsProvider" console="false" env-hash="-1240597362020527380" id="com.arm.eclipse.builder.armcc.v5.langprovider" keep-relative-paths="false" name="ARM Compiler 5 Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} --list-macros &quot;${INPUTS}&quot;" prefer-non-shared="true">
+				<language-scope id="com.arm.eclipse.builder.armcc.lang.c"/>
+				<language-scope id="com.arm.eclipse.builder.armcc.lang.cpp"/>
+			</provider>
+		</extension>
+	</configuration>
+</project>

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9_GCC/RTE/CMSIS_CORE_Validation/CV_Config.h → CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/AC5/RTE/CMSIS_CORE_Validation/CV_Config.h

@@ -16,7 +16,7 @@
 // <o> Print Output Format <0=> Plain Text <1=> XML
 // <i> Set the test results output format to plain text or XML
 #ifndef PRINT_XML_REPORT
-#define PRINT_XML_REPORT            0
+#define PRINT_XML_REPORT            1
 #endif
 // <o> Buffer size for assertions results
 // <i> Set the buffer size for assertions results buffer

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/RTE/RTE_Components.h → CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/AC5/RTE/RTE_Components.h

@@ -2,8 +2,8 @@
  * Auto generated Run-Time-Environment Component Configuration File
  *      *** Do not modify ! ***
  *
- * Project: CMSIS_CV
- * RTE configuration: CMSIS_CV.rteconfig
+ * Project: CMSIS_CV_CA5_AC5
+ * RTE configuration: CMSIS_CV_CA5_AC5.rteconfig
 */
 #ifndef RTE_COMPONENTS_H
 #define RTE_COMPONENTS_H

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/.cproject → CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/AC6/.cproject

@@ -1,129 +1,49 @@
 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
 <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
 	<storageModule moduleId="org.eclipse.cdt.core.settings">
-		<cconfiguration id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1261257010">
-			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1261257010" moduleId="org.eclipse.cdt.core.settings" name="Cortex-A5 (AC5)">
+		<cconfiguration id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1021881951">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1021881951" moduleId="org.eclipse.cdt.core.settings" name="Debug">
 				<externalSettings/>
 				<extensions>
 					<extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
 				</extensions>
 			</storageModule>
 			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
-				<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1261257010" name="Cortex-A5 (AC5)" parent="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6">
-					<folderInfo id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1261257010." name="/" resourcePath="">
-						<toolChain id="com.arm.toolchain.baremetal.base.var.arm_compiler_5-5.1960502218" name="ARM Compiler 5" superClass="com.arm.toolchain.baremetal.base.var.arm_compiler_5-5">
-							<option id="com.arm.toolchain.ac5.option.target.cpu_fpu.1899004868" superClass="com.arm.toolchain.ac5.option.target.cpu_fpu" value="Cortex-A5.VFPv4.Neon" valueType="string"/>
-							<option id="com.arm.toolchain.ac5.option.fppcs.1215240395" name="Floating-point PCS" superClass="com.arm.toolchain.ac5.option.fppcs" value="com.arm.tool.c.compiler.option.fppcs.hard" valueType="enumerated"/>
-							<option id="com.arm.toolchain.ac5.option.inst.391027132" name="Instruction set" superClass="com.arm.toolchain.ac5.option.inst" value="com.arm.tool.c.compiler.option.inst.arm" valueType="enumerated"/>
-							<option id="com.arm.toolchain.ac5.options.libs.useMicroLib.1898820408" name="Use microlib" superClass="com.arm.toolchain.ac5.options.libs.useMicroLib" value="true" valueType="boolean"/>
-							<option id="com.arm.toolchain.ac5.option.endian.2047271088" name="Byte order" superClass="com.arm.toolchain.ac5.option.endian" value="com.arm.tool.c.compiler.option.endian.little" valueType="enumerated"/>
-							<targetPlatform id="com.arm.toolchain.baremetal.base.var.arm_compiler_5-5.1960502218.788792350" name=""/>
-							<builder buildPath="${workspace_loc:/CMSIS_CV}/Debug" id="org.eclipse.cdt.build.core.internal.builder.1105228045" keepEnvironmentInBuildfile="false" name="CDT Internal Builder" superClass="org.eclipse.cdt.build.core.internal.builder"/>
-							<tool id="com.arm.tool.c.compiler.base.var.arm_compiler_5-5.1006008870" name="ARM C Compiler 5" superClass="com.arm.tool.c.compiler.base.var.arm_compiler_5-5">
-								<option id="com.arm.tool.c.compiler.option.incpath.2039211042" name="Include path (-I)" superClass="com.arm.tool.c.compiler.option.incpath" valueType="includePath"/>
-								<option id="com.arm.tool.c.compiler.option.defmac.1773701319" name="Define macro (-D)" superClass="com.arm.tool.c.compiler.option.defmac" valueType="definedSymbols"/>
-								<option defaultValue="com.arm.tool.c.compiler.option.optlevel.min" id="com.arm.tool.c.compiler.option.optlevel.882659687" name="Optimization level" superClass="com.arm.tool.c.compiler.option.optlevel" valueType="enumerated"/>
-								<option id="com.arm.tool.c.compiler.option.targetcpu.1426497902" name="Target CPU (--cpu)" superClass="com.arm.tool.c.compiler.option.targetcpu" value="Cortex-A5.neon" valueType="string"/>
-								<option id="com.arm.tool.c.compiler.option.fppcs.1692296380" name="Floating-point PCS (--apcs)" superClass="com.arm.tool.c.compiler.option.fppcs" value="com.arm.tool.c.compiler.option.fppcs.hard" valueType="enumerated"/>
-								<option id="com.arm.tool.c.compiler.option.inst.743536123" name="Instruction set" superClass="com.arm.tool.c.compiler.option.inst" value="com.arm.tool.c.compiler.option.inst.arm" valueType="enumerated"/>
-								<option id="com.arm.tool.c.compiler.option.useMicroLib.829868509" name="Use microlib (-D__MICROLIB)" superClass="com.arm.tool.c.compiler.option.useMicroLib" value="true" valueType="boolean"/>
-								<option id="com.arm.tool.c.compiler.option.implicit.defmac.768550198" name="Implicit Define macros" superClass="com.arm.tool.c.compiler.option.implicit.defmac" valueType="definedSymbols">
-									<listOptionValue builtIn="false" value="_RTE_"/>
-									<listOptionValue builtIn="false" value="ARMCA5"/>
-								</option>
-								<option id="com.arm.tool.c.compiler.option.implicit.incpath.2077192262" name="Implicit Include paths" superClass="com.arm.tool.c.compiler.option.implicit.incpath" valueType="includePath">
+				<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1021881951" name="Debug" parent="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6">
+					<folderInfo id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1021881951." name="/" resourcePath="">
+						<toolChain id="com.arm.toolchain.v6.base.var.arm_compiler_6-6.1171348516" name="ARM Compiler 6" nonInternalBuilderId="com.arm.toolchain.v6.builder" superClass="com.arm.toolchain.v6.base.var.arm_compiler_6-6">
+							<option defaultValue="com.arm.tool.c.compiler.v6.base.options.debug.level.std" id="com.arm.toolchain.v6.base.options.debug.level.2082124093" name="Debug Level" superClass="com.arm.toolchain.v6.base.options.debug.level" valueType="enumerated"/>
+							<option id="com.arm.toolchain.v6.base.options.target.cpu_fpu.1043675356" superClass="com.arm.toolchain.v6.base.options.target.cpu_fpu" value="Cortex-A5.VFPv4.Neon" valueType="string"/>
+							<option id="com.arm.toolchain.v6.base.options.floatabi.1359327717" name="Float ABI" superClass="com.arm.toolchain.v6.base.options.floatabi" value="com.arm.tool.c.compiler.v6.base.option.floatabi.hard" valueType="enumerated"/>
+							<option id="com.arm.toolchain.v6.base.options.inst.394719799" name="Instruction set" superClass="com.arm.toolchain.v6.base.options.inst" value="com.arm.tool.c.compiler.v6.base.option.inst.arm" valueType="enumerated"/>
+							<option id="com.arm.toolchain.v6.base.options.libs.useMicroLib.1413293533" name="Use microlib" superClass="com.arm.toolchain.v6.base.options.libs.useMicroLib" value="true" valueType="boolean"/>
+							<option id="com.arm.toolchain.v6.base.options.endian.846610862" name="Byte order" superClass="com.arm.toolchain.v6.base.options.endian" value="com.arm.tool.c.compiler.v6.base.option.endian.little" valueType="enumerated"/>
+							<targetPlatform id="com.arm.toolchain.v6.base.var.arm_compiler_6-6.1171348516.207887278" name=""/>
+							<builder autoBuildTarget="all" buildPath="${workspace_loc:/CMSIS_CV_CA9_AC6}/Debug" cleanBuildTarget="clean" id="org.eclipse.cdt.build.core.internal.builder.1079377147" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="CDT Internal Builder" superClass="org.eclipse.cdt.build.core.internal.builder"/>
+							<tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.1485719566" name="ARM C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6">
+								<option id="com.arm.tool.c.compiler.v6.base.option.incpath.509984980" name="Include path (-I)" superClass="com.arm.tool.c.compiler.v6.base.option.incpath" useByScannerDiscovery="false" valueType="includePath">
 									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Include&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/CMSIS/Core_A/Include&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/Device/ARM/ARMCA5/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/Device/ARM/ARMCA9/Include&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE/CMSIS_CORE_Validation&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE/Device/ARMCA5&quot;"/>
-								</option>
-								<option id="com.arm.tool.c.compiler.option.debug.enableToolSpecificSettings.393339148" name="Enable tool specific settings" superClass="com.arm.tool.c.compiler.option.debug.enableToolSpecificSettings" value="false" valueType="boolean"/>
-								<option id="com.arm.tool.c.compiler.option.endian.1534570039" name="Byte order" superClass="com.arm.tool.c.compiler.option.endian" value="com.arm.tool.c.compiler.option.endian.little" valueType="enumerated"/>
-								<option id="com.arm.tool.c.compile.option.lang.1180588084" name="Source language mode" superClass="com.arm.tool.c.compile.option.lang" value="com.arm.tool.c.compile.option.lang.c99" valueType="enumerated"/>
-								<inputType id="com.arm.tool.c.compiler.input.614264250" superClass="com.arm.tool.c.compiler.input"/>
-								<inputType id="com.arm.tool.cpp.compiler.input.1314721428" superClass="com.arm.tool.cpp.compiler.input"/>
-							</tool>
-							<tool id="com.arm.tool.cpp.compiler.base.var.arm_compiler_5-5.1697853860" name="ARM C++ Compiler 5" superClass="com.arm.tool.cpp.compiler.base.var.arm_compiler_5-5">
-								<option defaultValue="com.arm.tool.c.compiler.option.optlevel.min" id="com.arm.tool.c.compiler.option.optlevel.213031284" name="Optimization level" superClass="com.arm.tool.c.compiler.option.optlevel" valueType="enumerated"/>
-								<option id="com.arm.tool.c.compiler.option.implicit.defmac.794423957" name="Implicit Define macros" superClass="com.arm.tool.c.compiler.option.implicit.defmac" valueType="definedSymbols">
-									<listOptionValue builtIn="false" value="_RTE_"/>
-									<listOptionValue builtIn="false" value="ARMCA5"/>
-								</option>
-								<option id="com.arm.tool.c.compiler.option.implicit.incpath.1172356175" name="Implicit Include paths" superClass="com.arm.tool.c.compiler.option.implicit.incpath" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE/Device/ARMCA9&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Include&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/CMSIS/Core_A/Include&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/Device/ARM/ARMCA5/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/Device/ARM/ARMCA9/Include&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE/CMSIS_CORE_Validation&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE/Device/ARMCA5&quot;"/>
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-							</tool>
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-								<option id="com.arm.tool.assembler.option.incpath.240180621" name="Include Path (-i)" superClass="com.arm.tool.assembler.option.incpath" valueType="includePath"/>
-								<option id="com.arm.tool.assembler.option.cpu.6183565" name="Target CPU (--cpu)" superClass="com.arm.tool.assembler.option.cpu" value="Cortex-A5.neon" valueType="string"/>
-								<option id="com.arm.tool.assembler.option.fppcs.1985670947" name="Floating-point PCS (--apcs)" superClass="com.arm.tool.assembler.option.fppcs" value="com.arm.tool.c.compiler.option.fppcs.hard" valueType="enumerated"/>
-								<option id="com.arm.tool.assembler.option.inst.2124977961" name="Instruction set" superClass="com.arm.tool.assembler.option.inst" value="com.arm.tool.c.compiler.option.inst.arm" valueType="enumerated"/>
-								<option id="com.arm.tool.assembler.option.useMicroLib.1202936635" name="Use microlib (--pd &quot;__MICROLIB SETA 1&quot;)" superClass="com.arm.tool.assembler.option.useMicroLib" value="true" valueType="boolean"/>
-								<option id="com.arm.tool.assembler.option.implicit.predefine.1654893854" name="Implicit Predefines" superClass="com.arm.tool.assembler.option.implicit.predefine" valueType="stringList">
-									<listOptionValue builtIn="false" value="_RTE_ SETA 1"/>
-									<listOptionValue builtIn="false" value="ARMCA5 SETA 1"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE/Device/ARMCA9&quot;"/>
 								</option>
-								<option id="com.arm.tool.assembler.option.implicit.incpath.840007947" name="Implicit Include paths" superClass="com.arm.tool.assembler.option.implicit.incpath" valueType="includePath">
-									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Include&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/CMSIS/Core_A/Include&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/Device/ARM/ARMCA5/Include&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE/CMSIS_CORE_Validation&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE/Device/ARMCA5&quot;"/>
+								<option id="com.arm.tool.c.compiler.v6.base.option.defmac.71310516" name="Define macro (-D)" superClass="com.arm.tool.c.compiler.v6.base.option.defmac" useByScannerDiscovery="false" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="_RTE_"/>
+									<listOptionValue builtIn="false" value="ARMCA9"/>
 								</option>
-								<option id="com.arm.tool.assembler.option.endian.938835271" name="Byte order" superClass="com.arm.tool.assembler.option.endian" value="com.arm.tool.c.compiler.option.endian.little" valueType="enumerated"/>
-								<inputType id="com.arm.tool.assembler.input.567242146" superClass="com.arm.tool.assembler.input"/>
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-							<tool id="com.arm.tool.c.linker.base.var.arm_compiler_5-5.1792565798" name="ARM Linker 5" superClass="com.arm.tool.c.linker.base.var.arm_compiler_5-5">
-								<option id="com.arm.tool.c.linker.option.cpu.2055858033" name="Target CPU (--cpu)" superClass="com.arm.tool.c.linker.option.cpu" value="Cortex-A5.neon" valueType="string"/>
-								<option id="com.arm.tool.c.linker.option.useMicroLib.75487761" name="Use microlib" superClass="com.arm.tool.c.linker.option.useMicroLib" value="true" valueType="boolean"/>
-								<option id="com.arm.tool.c.linker.option.scatter.461693819" name="Scatter file (--scatter)" superClass="com.arm.tool.c.linker.option.scatter" value="${workspace_loc:/${ProjName}}/RTE/Device/ARMCA5/ARMCA5.sct" valueType="string"/>
-								<option id="com.arm.tool.c.linker.option.entry.2107333911" name="Image entry point (--entry)" superClass="com.arm.tool.c.linker.option.entry" value="Vectors" valueType="string"/>
-							</tool>
-							<tool id="com.arm.tool.librarian.base.var.arm_compiler_5-5.2146011430" name="ARM Librarian 5" superClass="com.arm.tool.librarian.base.var.arm_compiler_5-5"/>
-						</toolChain>
-					</folderInfo>
-					<sourceEntries>
-						<entry excluding="RTE/Device/ARMCA7/system_ARMCA7.h|RTE/Device/ARMCA7/system_ARMCA7.c|RTE/Device/ARMCA7/startup_ARMCA7.c|RTE/Device/ARMCA7/mmu_ARMCA7.c|RTE/Device/ARMCA7/mem_ARMCA7.h|RTE/Device/ARMCA7/ARMCA7.sct" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
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-		<cconfiguration id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1021881951">
-			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1021881951" moduleId="org.eclipse.cdt.core.settings" name="Cortex-A5 (AC6)">
-				<externalSettings/>
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-					<extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
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-			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
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-							<option id="com.arm.toolchain.v6.base.options.target.cpu_fpu.1043675356" superClass="com.arm.toolchain.v6.base.options.target.cpu_fpu" value="Cortex-A5.VFPv4_D16" valueType="string"/>
-							<option id="com.arm.toolchain.v6.base.options.floatabi.1359327717" name="Float ABI" superClass="com.arm.toolchain.v6.base.options.floatabi" value="com.arm.tool.c.compiler.v6.base.option.floatabi.hard" valueType="enumerated"/>
-							<option id="com.arm.toolchain.v6.base.options.inst.394719799" name="Instruction set" superClass="com.arm.toolchain.v6.base.options.inst" value="com.arm.tool.c.compiler.v6.base.option.inst.arm" valueType="enumerated"/>
-							<option id="com.arm.toolchain.v6.base.options.libs.useMicroLib.1413293533" name="Use microlib" superClass="com.arm.toolchain.v6.base.options.libs.useMicroLib" value="true" valueType="boolean"/>
-							<option id="com.arm.toolchain.v6.base.options.endian.846610862" name="Byte order" superClass="com.arm.toolchain.v6.base.options.endian" value="com.arm.tool.c.compiler.v6.base.option.endian.little" valueType="enumerated"/>
-							<targetPlatform id="com.arm.toolchain.v6.base.var.arm_compiler_6-6.1171348516.207887278" name=""/>
-							<builder buildPath="${workspace_loc:/CMSIS_CV}/Debug" id="org.eclipse.cdt.build.core.internal.builder.512977327" keepEnvironmentInBuildfile="false" name="CDT Internal Builder" superClass="org.eclipse.cdt.build.core.internal.builder"/>
-							<tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.1485719566" name="ARM C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6">
-								<option id="com.arm.tool.c.compiler.v6.base.option.incpath.509984980" name="Include path (-I)" superClass="com.arm.tool.c.compiler.v6.base.option.incpath" useByScannerDiscovery="false" valueType="includePath"/>
-								<option id="com.arm.tool.c.compiler.v6.base.option.defmac.71310516" name="Define macro (-D)" superClass="com.arm.tool.c.compiler.v6.base.option.defmac" useByScannerDiscovery="false" valueType="definedSymbols"/>
 								<option defaultValue="com.arm.tool.c.compiler.v6.base.option.optlevel.min" id="com.arm.tool.c.compiler.v6.base.option.optlevel.1116740797" name="Optimization level" superClass="com.arm.tool.c.compiler.v6.base.option.optlevel" useByScannerDiscovery="true" valueType="enumerated"/>
 								<option defaultValue="com.arm.tool.c.compiler.v6.base.options.debug.level.std" id="com.arm.tool.c.compiler.v6.base.options.debug.level.1282091065" name="Debug Level" superClass="com.arm.tool.c.compiler.v6.base.options.debug.level" useByScannerDiscovery="true" valueType="enumerated"/>
 								<option id="com.arm.tool.c.compiler.v6.base.option.cpu.1622229999" name="CPU (-mcpu)" superClass="com.arm.tool.c.compiler.v6.base.option.cpu" useByScannerDiscovery="true" value="cortex-a5" valueType="string"/>
 								<option id="com.arm.tool.c.compiler.v6.base.option.target.715551531" name="Target (--target)" superClass="com.arm.tool.c.compiler.v6.base.option.target" useByScannerDiscovery="true" value="arm-arm-none-eabi" valueType="string"/>
-								<option id="com.arm.tool.c.compiler.v6.base.option.fpu.531976415" name="FPU (-mfpu)" superClass="com.arm.tool.c.compiler.v6.base.option.fpu" useByScannerDiscovery="true" value="vfpv4-d16" valueType="string"/>
+								<option id="com.arm.tool.c.compiler.v6.base.option.fpu.531976415" name="FPU (-mfpu)" superClass="com.arm.tool.c.compiler.v6.base.option.fpu" useByScannerDiscovery="true" value="neon-vfpv4" valueType="string"/>
 								<option id="com.arm.tool.c.compiler.v6.base.option.floatabi.1123864924" name="Float ABI (-mfloat-abi)" superClass="com.arm.tool.c.compiler.v6.base.option.floatabi" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.floatabi.hard" valueType="enumerated"/>
 								<option id="com.arm.tool.c.compiler.v6.base.option.inst.908271468" name="Instruction set" superClass="com.arm.tool.c.compiler.v6.base.option.inst" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.inst.arm" valueType="enumerated"/>
 								<option id="com.arm.tool.c.compiler.v6.base.useMicroLib.722723634" name="Use microlib (-D__MICROLIB)" superClass="com.arm.tool.c.compiler.v6.base.useMicroLib" useByScannerDiscovery="false" value="true" valueType="boolean"/>
@@ -162,11 +82,24 @@
 								</option>
 							</tool>
 							<tool id="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6.475165834" name="ARM Assembler 6" superClass="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6">
-								<option id="com.arm.tool.assembler.v6.base.option.incpath.512319760" name="Include path (-I)" superClass="com.arm.tool.assembler.v6.base.option.incpath" valueType="includePath"/>
+								<option id="com.arm.tool.assembler.v6.base.option.incpath.512319760" name="Include path (-I)" superClass="com.arm.tool.assembler.v6.base.option.incpath" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/CMSIS/Core_A/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/Device/ARM/ARMCA9/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE/CMSIS_CORE_Validation&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE/Device/ARMCA9&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/CMSIS/Core_A/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/Device/ARM/ARMCA9/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE/CMSIS_CORE_Validation&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE/Device/ARMCA9&quot;"/>
+								</option>
 								<option defaultValue="com.arm.tool.assembler.v6.base.options.debug.level.std" id="com.arm.tool.assembler.v6.base.options.debug.level.1754017057" name="Debug Level" superClass="com.arm.tool.assembler.v6.base.options.debug.level" valueType="enumerated"/>
 								<option id="com.arm.tool.assembler.v6.base.option.cpu.1440642309" name="CPU (-mcpu)" superClass="com.arm.tool.assembler.v6.base.option.cpu" value="cortex-a5" valueType="string"/>
 								<option id="com.arm.tool.assembler.v6.base.option.target.2099316555" name="Target (--target)" superClass="com.arm.tool.assembler.v6.base.option.target" value="arm-arm-none-eabi" valueType="string"/>
-								<option id="com.arm.tool.assembler.v6.base.option.fpu.959648840" name="FPU (-mfpu)" superClass="com.arm.tool.assembler.v6.base.option.fpu" value="vfpv4" valueType="string"/>
+								<option id="com.arm.tool.assembler.v6.base.option.fpu.959648840" name="FPU (-mfpu)" superClass="com.arm.tool.assembler.v6.base.option.fpu" value="neon-vfpv4" valueType="string"/>
 								<option id="com.arm.tool.assembler.v6.base.option.floatabi.1026121137" name="Float ABI (-mfloat-abi)" superClass="com.arm.tool.assembler.v6.base.option.floatabi" value="com.arm.tool.c.compiler.v6.base.option.floatabi.hard" valueType="enumerated"/>
 								<option id="com.arm.tool.assembler.v6.base.option.inst.1080491485" name="Instruction set" superClass="com.arm.tool.assembler.v6.base.option.inst" value="com.arm.tool.c.compiler.v6.base.option.inst.arm" valueType="enumerated"/>
 								<option id="com.arm.tool.assembler.v6.base.useMicroLib.505841516" name="Use microlib (--pd &quot;__MICROLIB SETA 1&quot;)" superClass="com.arm.tool.assembler.v6.base.useMicroLib" value="true" valueType="boolean"/>
@@ -210,28 +143,22 @@
 	</storageModule>
 	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
 	<storageModule moduleId="com.arm.cmsis.project">
-		<rteConfig name="CMSIS_CV.rteconfig"/>
+		<rteConfig name="CMSIS_CV_CA5_AC6.rteconfig"/>
 		<toolChainAdapter id="com.arm.cmsis.pack.build.armcc5.Armcc5ToolChainAdapter" name="Adapter for ARM C/C++ 5.x and 6.x toolchains"/>
 		<device Dcore="Cortex-A5" DcoreVersion="r0p1" Dendian="Little-endian" Dfamily="ARM Cortex A5" Dfpu="SP_FPU" Dmpu="MPU" Dname="ARMCA5" Dvendor="ARM:82" Pname=""/>
 		<files>
 			<file name="RTE/Device/ARMCA9/ARMCA9.sct" version="1.0.0"/>
-			<file name="RTE/Device/ARMCA7/ARMCA7.sct" version="1.0.0"/>
 			<file name="RTE/Device/ARMCA5/ARMCA5.sct" version="1.0.0"/>
-			<file name="RTE/Device/ARMCA7/mmu_ARMCA7.c" version="1.0.0"/>
 			<file name="RTE/CMSIS_CORE_Validation/CV_Config.h" version="1.0.0"/>
 			<file name="RTE/Device/ARMCA5/mmu_ARMCA5.c" version="1.0.0"/>
-			<file name="RTE/Device/ARMCA7/system_ARMCA7.h" version="1.0.0"/>
 			<file name="RTE/Device/ARMCA5/system_ARMCA5.c" version="1.0.0"/>
 			<file name="RTE/Device/ARMCA9/mem_ARMCA9.h" version="1.0.0"/>
 			<file name="RTE/Device/ARMCA5/system_ARMCA5.h" version="1.0.0"/>
 			<file name="RTE/Device/ARMCA9/startup_ARMCA9.c" version="1.0.0"/>
 			<file name="RTE/Device/ARMCA5/mem_ARMCA5.h" version="1.0.0"/>
-			<file name="RTE/Device/ARMCA7/mem_ARMCA7.h" version="1.0.0"/>
-			<file name="RTE/Device/ARMCA7/system_ARMCA7.c" version="1.0.0"/>
 			<file name="RTE/Device/ARMCA9/system_ARMCA9.c" version="1.0.0"/>
 			<file name="RTE/Device/ARMCA5/startup_ARMCA5.c" version="1.0.0"/>
 			<file name="RTE/Device/ARMCA9/system_ARMCA9.h" version="1.0.0"/>
-			<file name="RTE/Device/ARMCA7/startup_ARMCA7.c" version="1.0.0"/>
 			<file name="RTE/Device/ARMCA9/mmu_ARMCA9.c" version="1.0.0"/>
 		</files>
 	</storageModule>

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/AC6/.gitignore

@@ -0,0 +1 @@
+/Debug/

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/AC6/.project

@@ -0,0 +1,59 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>CMSIS_CV_CA5_AC6</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>com.arm.cmsis.pack.project.RteNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>RTE/CMSIS_CORE_Validation/CV_CoreAFunc.c</name>
+			<type>1</type>
+			<locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Source/CV_CoreAFunc.c</locationURI>
+		</link>
+		<link>
+			<name>RTE/CMSIS_CORE_Validation/CV_CoreInstr.c</name>
+			<type>1</type>
+			<locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Source/CV_CoreInstr.c</locationURI>
+		</link>
+		<link>
+			<name>RTE/CMSIS_CORE_Validation/CV_Framework.c</name>
+			<type>1</type>
+			<locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Source/CV_Framework.c</locationURI>
+		</link>
+		<link>
+			<name>RTE/CMSIS_CORE_Validation/CV_Report.c</name>
+			<type>1</type>
+			<locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Source/CV_Report.c</locationURI>
+		</link>
+		<link>
+			<name>RTE/CMSIS_CORE_Validation/cmsis_cv.c</name>
+			<type>1</type>
+			<locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Source/cmsis_cv.c</locationURI>
+		</link>
+		<link>
+			<name>RTE/Device/ARMCA5/irq_ctrl_gic.c</name>
+			<type>1</type>
+			<locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS/5.1.1-dev1/CMSIS/Core_A/Source/irq_ctrl_gic.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/AC6/.settings/language.settings.xml

@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+	<configuration id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1021881951" name="Debug">
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+			<provider class="com.arm.eclipse.builder.armcc.discovery.ArmCompiler6LanguageSettingsProvider" console="false" env-hash="1249826110038424530" id="com.arm.eclipse.builder.armcc.v6.langprovider" keep-relative-paths="false" name="ARM Compiler 6 Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+				<language-scope id="org.eclipse.cdt.core.gcc"/>
+				<language-scope id="org.eclipse.cdt.core.g++"/>
+			</provider>
+		</extension>
+	</configuration>
+</project>

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/AC6/CMSIS_CV_CA5_AC6.rteconfig

@@ -0,0 +1,55 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<configuration xmlns:xs="http://www.w3.org/2001/XMLSchema-instance">
+<toolchain Tcompiler="ARMCC" Toutput="exe"/>
+<components>
+<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="1.0.0">
+<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+<file category="doc" name="CMSIS/Documentation/Core_A/html/index.html"/>
+<file category="include" name="CMSIS/Core_A/Include/"/>
+</component>
+<component Cclass="CMSIS CORE Validation" Cgroup="CoreFunc" Cvendor="ARM" Cversion="1.0.0">
+<package name="CMSIS-CORE_Validation" url="http://www.keil.com/pack" vendor="ARM" version="1.0.0-dev1"/>
+<file category="source" condition="ARMv7-A Device" name="Source/CV_CoreAFunc.c"/>
+</component>
+<component Cclass="CMSIS CORE Validation" Cgroup="CoreInstr" Cvendor="ARM" Cversion="1.0.0">
+<package name="CMSIS-CORE_Validation" url="http://www.keil.com/pack" vendor="ARM" version="1.0.0-dev1"/>
+<file category="source" name="Source/CV_CoreInstr.c"/>
+</component>
+<component Cclass="CMSIS CORE Validation" Cgroup="Framework" Cvendor="ARM" Cversion="1.0.0">
+<package name="CMSIS-CORE_Validation" url="http://www.keil.com/pack" vendor="ARM" version="1.0.0-dev1"/>
+<file category="include" name="Include/"/>
+<file category="header" name="Include/cmsis_cv.h"/>
+<file attr="config" category="header" condition="ARMv7-A Device" name="Source/ConfigA/CV_Config.h" version="1.0.0"/>
+<file category="source" name="Source/cmsis_cv.c"/>
+<file category="source" name="Source/CV_Framework.c"/>
+<file category="source" name="Source/CV_Report.c"/>
+</component>
+<component Capiversion="1.0.0" Cclass="Device" Cgroup="IRQ Controller" Csub="GIC" Cvendor="ARM" Cversion="1.0.0" deviceDependent="1">
+<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+<file category="sourceC" deviceDependent="1" name="CMSIS/Core_A/Source/irq_ctrl_gic.c"/>
+</component>
+<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" deviceDependent="1">
+<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+<file category="include" deviceDependent="1" name="Device/ARM/ARMCA5/Include/"/>
+<file attr="config" category="sourceC" condition="ARMCC5" deviceDependent="1" name="Device/ARM/ARMCA5/Source/AC5/startup_ARMCA5.c" version="1.0.0"/>
+<file attr="config" category="linkerScript" condition="ARMCC5" deviceDependent="1" name="Device/ARM/ARMCA5/Source/AC5/ARMCA5.sct" version="1.0.0"/>
+<file attr="config" category="sourceC" condition="ARMCC6" deviceDependent="1" name="Device/ARM/ARMCA5/Source/AC6/startup_ARMCA5.c" version="1.0.0"/>
+<file attr="config" category="linkerScript" condition="ARMCC6" deviceDependent="1" name="Device/ARM/ARMCA5/Source/AC6/ARMCA5.sct" version="1.0.0"/>
+<file attr="config" category="sourceC" deviceDependent="1" name="Device/ARM/ARMCA5/Source/system_ARMCA5.c" version="1.0.0"/>
+<file attr="config" category="sourceC" deviceDependent="1" name="Device/ARM/ARMCA5/Source/mmu_ARMCA5.c" version="1.0.0"/>
+<file attr="config" category="header" deviceDependent="1" name="Device/ARM/ARMCA5/Include/system_ARMCA5.h" version="1.0.0"/>
+<file attr="config" category="header" deviceDependent="1" name="Device/ARM/ARMCA5/Include/mem_ARMCA5.h" version="1.0.0"/>
+</component>
+</components>
+<apis>
+<api Capiversion="1.0.0" Cclass="Device" Cgroup="IRQ Controller" Cvendor="ARM" Cversion="1.0.0" exclusive="1">
+<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+<file category="header" name="CMSIS/Core_A/Include/irq_ctrl.h"/>
+</api>
+</apis>
+<device Dcore="Cortex-A5" DcoreVersion="r0p1" Dendian="Little-endian" Dfamily="ARM Cortex A5" Dfpu="SP_FPU" Dmpu="MPU" Dname="ARMCA5" Dvendor="ARM:82" Pname="">
+<url>http://www.keil.com/dd2/arm/armca5</url>
+<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+</device>
+<packages useAllLatestPacks="1"/>
+</configuration>

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/AC6/RTE/CMSIS_CORE_Validation/CV_Config.h

@@ -0,0 +1,96 @@
+/*-----------------------------------------------------------------------------
+ *      Name:         CV_Config.h 
+ *      Purpose:      CV Config header
+ *----------------------------------------------------------------------------
+ *      Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+#ifndef __CV_CONFIG_H
+#define __CV_CONFIG_H
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h> Common Test Settings
+// <o> Print Output Format <0=> Plain Text <1=> XML
+// <i> Set the test results output format to plain text or XML
+#ifndef PRINT_XML_REPORT
+#define PRINT_XML_REPORT            1
+#endif
+// <o> Buffer size for assertions results
+// <i> Set the buffer size for assertions results buffer
+#define BUFFER_ASSERTIONS           128U
+// </h>
+
+// <h> Disable Test Cases
+// <i> Uncheck to disable an individual test case
+// <q00> TC_CoreInstr_NOP
+// <q01> TC_CoreInstr_REV
+// <q02> TC_CoreInstr_REV16
+// <q03> TC_CoreInstr_REVSH
+// <q04> TC_CoreInstr_ROR
+// <q05> TC_CoreInstr_RBIT
+// <q06> TC_CoreInstr_CLZ
+// <q07> TC_CoreInstr_SSAT
+// <q08> TC_CoreInstr_USAT
+//
+// <q09> TC_CoreAFunc_FPSCR
+// <q10> TC_CoreAFunc_CPSR
+// <q11> TC_CoreAFunc_Mode
+// <q12> TC_CoreAFunc_SP
+// <q13> TC_CoreAFunc_SP_usr
+// <q14> TC_CoreAFunc_FPEXC
+// <q15> TC_COREAFUNC_ACTLR
+// <q16> TC_COREAFUNC_CPACR
+// <q17> TC_COREAFUNC_DFSR
+// <q18> TC_COREAFUNC_IFSR
+// <q19> TC_COREAFUNC_ISR
+// <q20> TC_COREAFUNC_CBAR
+// <q21> TC_COREAFUNC_TTBR0
+// <q22> TC_COREAFUNC_DACR
+// <q23> TC_COREAFUNC_SCTLR
+// <q24> TC_COREAFUNC_ACTRL
+// <q25> TC_COREAFUNC_MPIDR
+// <q26> TC_COREAFUNC_VBAR
+//
+// <q27> TC_GENTIMER_CNTFRQ
+// <q28> TC_GENTIMER_CNTP_TVAL
+// <q29> TC_GENTIMER_CNTP_CTL
+#define TC_COREINSTR_NOP_EN         1
+#define TC_COREINSTR_REV_EN         1
+#define TC_COREINSTR_REV16_EN       1
+#define TC_COREINSTR_REVSH_EN       1
+#define TC_COREINSTR_ROR_EN         1
+#define TC_COREINSTR_RBIT_EN        1
+#define TC_COREINSTR_CLZ_EN         1
+#define TC_COREINSTR_SSAT_EN        1
+#define TC_COREINSTR_USAT_EN        1
+
+#define TC_COREAFUNC_IRQ            1
+#define TC_COREAFUNC_FPSCR          1
+#define TC_COREAFUNC_CPSR           1
+#define TC_COREAFUNC_MODE           1
+#define TC_COREAFUNC_SP             1
+#define TC_COREAFUNC_SP_USR         1
+#define TC_COREAFUNC_FPEXC          1
+#define TC_COREAFUNC_ACTLR          1
+#define TC_COREAFUNC_CPACR          1
+#define TC_COREAFUNC_DFSR           1
+#define TC_COREAFUNC_IFSR           1
+#define TC_COREAFUNC_ISR            1
+#define TC_COREAFUNC_CBAR           1
+#define TC_COREAFUNC_TTBR0          1
+#define TC_COREAFUNC_DACR           1
+#define TC_COREAFUNC_SCTLR          1
+#define TC_COREAFUNC_ACTRL          1
+#define TC_COREAFUNC_MPIDR          1
+#define TC_COREAFUNC_VBAR           1
+
+#define TC_GENTIMER_CNTFRQ          1
+#define TC_GENTIMER_CNTP_TVAL       1
+#define TC_GENTIMER_CNTP_CTL        1
+// </h>
+
+#endif /* __CV_CONFIG_H */
+

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/AC6/RTE/Device/ARMCA5/ARMCA5.sct

@@ -0,0 +1,77 @@
+#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-a5 -xc
+;**************************************************
+; Copyright (c) 2017 ARM Ltd.  All rights reserved.
+;**************************************************
+
+; Scatter-file for RTX Example on Versatile Express
+
+; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.
+
+; This platform has 2GB SDRAM starting at 0x80000000.
+
+#include "mem_ARMCA5.h"
+
+SDRAM __ROM_BASE __ROM_SIZE       ; load region size_region
+{
+  VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address
+  {
+      * (RESET, +FIRST)         ; Vector table and other startup code
+      * (InRoot$$Sections)      ; All (library) code that must be in a root region
+      * (+RO-CODE)              ; Application RO code (.text)
+      * (+RO-DATA)              ; Application RO data (.constdata)
+  }
+  
+  RW_DATA __RAM_BASE __RW_DATA_SIZE
+  { * (+RW) }                   ; Application RW data (.data)
+  
+  ZI_DATA (__RAM_BASE+
+           __RW_DATA_SIZE) __ZI_DATA_SIZE
+  { * (+ZI) }                   ; Application ZI data (.bss)
+  
+  ARM_LIB_HEAP  (__RAM_BASE
+                +__RW_DATA_SIZE
+                +__ZI_DATA_SIZE)    EMPTY __HEAP_SIZE        ; Heap region growing up
+  { }
+    
+  ARM_LIB_STACK (__RAM_BASE
+                +__RAM_SIZE       
+                -__FIQ_STACK_SIZE
+                -__IRQ_STACK_SIZE
+                -__SVC_STACK_SIZE
+                -__ABT_STACK_SIZE
+                -__UND_STACK_SIZE) EMPTY -__STACK_SIZE      ; Stack region growing down
+  { }              
+                
+  UND_STACK     (__RAM_BASE
+                +__RAM_SIZE
+                -__FIQ_STACK_SIZE
+                -__IRQ_STACK_SIZE
+                -__SVC_STACK_SIZE
+                -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE  ; UND mode stack
+  { }
+  
+  ABT_STACK     (__RAM_BASE
+                +__RAM_SIZE
+                -__FIQ_STACK_SIZE
+                -__IRQ_STACK_SIZE
+                -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE  ; ABT mode stack
+  { }
+  
+  SVC_STACK     (__RAM_BASE
+                +__RAM_SIZE
+                -__FIQ_STACK_SIZE
+                -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE  ; SVC mode stack
+  { }  
+  
+  IRQ_STACK     (__RAM_BASE
+                +__RAM_SIZE
+                -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE  ; IRQ mode stack
+  { }  
+  
+  FIQ_STACK     (__RAM_BASE
+                +__RAM_SIZE)       EMPTY -__FIQ_STACK_SIZE  ; FIQ mode stack
+  { }
+  
+  TTB            __TTB_BASE        EMPTY __TTB_SIZE         ; Level-1 Translation Table for MMU
+  { }                                        
+}

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/AC6/RTE/Device/ARMCA5/mem_ARMCA5.h

@@ -0,0 +1,94 @@
+/**************************************************************************//**
+ * @file     mem_ARMCA5.h
+ * @brief    Memory base and size definitions (used in scatter file)
+ * @version  V1.00
+ * @date     16 Mar 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MEM_ARMCA5_H
+#define __MEM_ARMCA5_H
+
+/*----------------------------------------------------------------------------
+  User Stack & Heap size definition
+ *----------------------------------------------------------------------------*/
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- ROM Configuration ------------------------------------
+//
+// <h> ROM Configuration
+//   <o0> ROM Base Address <0x0-0xFFFFFFFF:8>
+//   <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE       0x80000000
+#define __ROM_SIZE       0x00200000
+
+/*--------------------- RAM Configuration -----------------------------------
+// <h> RAM Configuration
+//   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>
+//   <o1> RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//   <o2> RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//   <o3> ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//   <h> Stack / Heap Configuration
+//     <o4>  Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     <o5>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     <h> Exceptional Modes
+//       <o6> UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o7> ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o8> SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o9> IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o10> FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     </h>
+//   </h>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE       0x80200000
+#define __RAM_SIZE       0x00200000
+
+#define __RW_DATA_SIZE   0x00100000
+#define __ZI_DATA_SIZE   0x000F0000
+
+#define __STACK_SIZE     0x00001000
+#define __HEAP_SIZE      0x00008000
+
+#define __UND_STACK_SIZE 0x00000100
+#define __ABT_STACK_SIZE 0x00000100
+#define __SVC_STACK_SIZE 0x00000100
+#define __IRQ_STACK_SIZE 0x00000100
+#define __FIQ_STACK_SIZE 0x00000100
+
+/*----------------------------------------------------------------------------*/
+
+/*--------------------- TTB Configuration ------------------------------------
+//
+// <h> TTB Configuration
+//   <o0> TTB Base Address <0x0-0xFFFFFFFF:8>
+//   <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __TTB_BASE       0x80500000
+#define __TTB_SIZE       0x00004000
+
+#endif /* __MEM_ARMCA5_H */

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/AC6/RTE/Device/ARMCA5/mmu_ARMCA5.c

@@ -0,0 +1,235 @@
+/**************************************************************************//**
+ * @file     mmu_ARMCA5.c
+ * @brief    MMU Configuration for ARM Cortex-A5 Device Series
+ * @version  V1.00
+ * @date     16 Mar 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 ARM Cortex-A Series memory map
+
+                                                     Memory Type
+0xffffffff |--------------------------|             ------------
+           |       FLAG SYNC          |             Device Memory
+0xfffff000 |--------------------------|             ------------
+           |         Fault            |                Fault
+0xfff00000 |--------------------------|             ------------
+           |                          |                Normal
+           |                          |
+           |      Daughterboard       |
+           |         memory           |
+           |                          |
+0x80505000 |--------------------------|             ------------
+           |TTB (L2 Sync Flags   ) 4k |                Normal
+0x80504C00 |--------------------------|             ------------
+           |TTB (L2 Peripherals-B) 16k|                Normal
+0x80504800 |--------------------------|             ------------
+           |TTB (L2 Peripherals-A) 16k|                Normal
+0x80504400 |--------------------------|             ------------
+           |TTB (L2 Priv Periphs)  4k |                Normal
+0x80504000 |--------------------------|             ------------
+           |    TTB (L1 Descriptors)  |                Normal
+0x80500000 |--------------------------|             ------------
+           |           Heap           |                Normal
+           |--------------------------|             ------------
+           |          Stack           |                Normal
+0x80400000 |--------------------------|             ------------
+           |         ZI Data          |                Normal
+0x80300000 |--------------------------|             ------------
+           |         RW Data          |                Normal
+0x80200000 |--------------------------|             ------------
+           |         RO Data          |                Normal
+           |--------------------------|             ------------
+           |         RO Code          |              USH Normal
+0x80000000 |--------------------------|             ------------
+           |      Daughterboard       |                Fault
+           |      HSB AXI buses       |
+0x40000000 |--------------------------|             ------------
+           |      Daughterboard       |                Fault
+           |  test chips peripherals  |
+0x2c002000 |--------------------------|             ------------
+           |     Private Address      |            Device Memory
+0x2c000000 |--------------------------|             ------------
+           |      Daughterboard       |                Fault
+           |  test chips peripherals  |
+0x20000000 |--------------------------|             ------------
+           |       Peripherals        |           Device Memory RW/RO
+           |                          |              & Fault
+0x00000000 |--------------------------|
+*/
+
+// L1 Cache info and restrictions about architecture of the caches (CCSIR register):
+// Write-Through support *not* available
+// Write-Back support available.
+// Read allocation support available.
+// Write allocation support available.
+
+//Note: You should use the Shareable attribute carefully.
+//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings.
+//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
+//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
+
+//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
+//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
+//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
+
+
+//Following MMU configuration is expected
+//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
+//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
+//Domain 0 is always the Client domain
+//Descriptors should place all memory in domain 0
+
+#include "ARMCA5.h"
+
+
+// L2 table pointers
+//----------------------------------------
+#define PRIVATE_TABLE_L2_BASE_4k       (0x80504000) //Map 4k Private Address space
+#define SYNC_FLAGS_TABLE_L2_BASE_4k    (0x80504C00) //Map 4k Flag synchronization
+#define PERIPHERAL_A_TABLE_L2_BASE_64k (0x80504400) //Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF
+#define PERIPHERAL_B_TABLE_L2_BASE_64k (0x80504800) //Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF
+
+//--------------------- PERIPHERALS -------------------
+#define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M)
+#define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M)
+
+//--------------------- SYNC FLAGS --------------------
+#define FLAG_SYNC     0xFFFFF000
+#define F_SYNC_BASE   0xFFF00000  //1M aligned
+
+//Import symbols from linker
+extern uint32_t Image$$VECTORS$$Base;
+extern uint32_t Image$$RW_DATA$$Base;
+extern uint32_t Image$$ZI_DATA$$Base;
+extern uint32_t Image$$TTB$$ZI$$Base;
+
+static uint32_t Sect_Normal;     //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
+static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
+static uint32_t Sect_Normal_RO;  //as Sect_Normal_Cod, but not executable
+static uint32_t Sect_Normal_RW;  //as Sect_Normal_Cod, but writeable and not executable
+static uint32_t Sect_Device_RO;  //device, non-shareable, non-executable, ro, domain 0, base addr 0
+static uint32_t Sect_Device_RW;  //as Sect_Device_RO, but writeable
+
+/* Define global descriptors */
+static uint32_t Page_L1_4k  = 0x0;  //generic
+static uint32_t Page_L1_64k = 0x0;  //generic
+static uint32_t Page_4k_Device_RW;  //Shared device, not executable, rw, domain 0
+static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0
+
+void MMU_CreateTranslationTable(void)
+{
+    mmu_region_attributes_Type region;
+
+    //Create 4GB of faulting entries
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT);
+
+    /*
+     * Generate descriptors. Refer to core_ca.h to get information about attributes
+     *
+     */
+    //Create descriptors for Vectors, RO, RW, ZI sections
+    section_normal(Sect_Normal, region);
+    section_normal_cod(Sect_Normal_Cod, region);
+    section_normal_ro(Sect_Normal_RO, region);
+    section_normal_rw(Sect_Normal_RW, region);
+    //Create descriptors for peripherals
+    section_device_ro(Sect_Device_RO, region);
+    section_device_rw(Sect_Device_RW, region);
+    //Create descriptors for 64k pages
+    page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);
+    //Create descriptors for 4k pages
+    page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);
+
+
+    /*
+     *  Define MMU flat-map regions and attributes
+     *
+     */
+
+    //Define Image
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base, 1, Sect_Normal_Cod);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base, 1, Sect_Normal_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA$$Base, 1, Sect_Normal_RW);
+
+    //all DRAM executable, rw, cacheable - applications may choose to divide memory into ro executable
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$TTB$$ZI$$Base, 2043, Sect_Normal);
+
+    //--------------------- PERIPHERALS -------------------
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_FLASH_BASE0    , 64, Sect_Device_RO);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_FLASH_BASE1    , 64, Sect_Device_RO);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_SRAM_BASE      , 64, Sect_Device_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_VRAM_BASE      , 32, Sect_Device_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_ETHERNET_BASE  , 16, Sect_Device_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_USB_BASE       , 16, Sect_Device_RW);
+
+    // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C000000-0x1C00FFFF
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, PERIPHERAL_A_FAULT      , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
+    // Define peripheral range 0x1C000000-0x1C00FFFF
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_DAP_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_SYSTEM_REG_BASE,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_SERIAL_BASE    ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_AACI_BASE      ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_MMCI_BASE      ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_KMI0_BASE      ,  2, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_UART_BASE      ,  4, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_WDT_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+
+    // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C100000-0x1C10FFFF
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, PERIPHERAL_B_FAULT      , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
+    // Define peripheral range 0x1C100000-0x1C10FFFF
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_TIMER_BASE     ,  2, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_DVI_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_RTC_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_UART4_BASE     ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_CLCD_BASE      ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+
+    // Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory
+    MMU_TTPage4k (&Image$$TTB$$ZI$$Base, __get_CBAR()            ,256,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
+    // Define private address space entry.
+    MMU_TTPage4k (&Image$$TTB$$ZI$$Base, __get_CBAR()            ,  3,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+    // Define L2CC entry.  Uncomment if PL310 is present
+    //    MMU_TTPage4k (&Image$$TTB$$ZI$$Base, VE_A5_MP_PL310_BASE     ,  1,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+
+    // Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC)
+    MMU_TTPage4k (&Image$$TTB$$ZI$$Base, F_SYNC_BASE , 256, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
+    // Define synchronization space entry.
+    MMU_TTPage4k (&Image$$TTB$$ZI$$Base, FLAG_SYNC   ,   1, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+
+    /* Set location of level 1 page table
+    ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
+    ; 13:7  - 0x0
+    ; 6     - IRGN[0] 0x0 (Inner WB WA)
+    ; 5     - NOS     0x0 (Non-shared)
+    ; 4:3   - RGN     0x1 (Outer WB WA)
+    ; 2     - IMP     0x0 (Implementation Defined)
+    ; 1     - S       0x0 (Non-shared)
+    ; 0     - IRGN[1] 0x1 (Inner WB WA) */
+    __set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 9);
+    __ISB();
+
+    /* Set up domain access control register
+    ; We set domain 0 to Client and all other domains to No Access.
+    ; All translation table entries specify domain 0 */
+    __set_DACR(1);
+    __ISB();
+}

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/AC6/RTE/Device/ARMCA5/startup_ARMCA5.c

@@ -0,0 +1,138 @@
+/******************************************************************************
+ * @file     startup_ARMCA5.c
+ * @brief    CMSIS Device System Source File for ARM Cortex-A9 Device Series
+ * @version  V1.00
+ * @date     22 Feb 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <ARMCA5.h>
+
+/*----------------------------------------------------------------------------
+  Definitions
+ *----------------------------------------------------------------------------*/
+#define USR_MODE 0x10            // User mode
+#define FIQ_MODE 0x11            // Fast Interrupt Request mode
+#define IRQ_MODE 0x12            // Interrupt Request mode
+#define SVC_MODE 0x13            // Supervisor mode
+#define ABT_MODE 0x17            // Abort mode
+#define UND_MODE 0x1B            // Undefined Instruction mode
+#define SYS_MODE 0x1F            // System mode
+
+/*----------------------------------------------------------------------------
+  Internal References
+ *----------------------------------------------------------------------------*/
+void Vectors       (void) __attribute__ ((naked, section("RESET")));
+void Reset_Handler (void) __attribute__ ((naked));
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void PAbt_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void DAbt_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void IRQ_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void FIQ_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+void Vectors(void) {
+  __ASM volatile(
+  "LDR    PC, =Reset_Handler                        \n"
+  "LDR    PC, =Undef_Handler                        \n"
+  "LDR    PC, =SVC_Handler                          \n"
+  "LDR    PC, =PAbt_Handler                         \n"
+  "LDR    PC, =DAbt_Handler                         \n"
+  "NOP                                              \n"
+  "LDR    PC, =IRQ_Handler                          \n"
+  "LDR    PC, =FIQ_Handler                          \n"
+  );
+}
+
+/*----------------------------------------------------------------------------
+  Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+  __ASM volatile(
+
+  // Mask interrupts
+  "CPSID   if                                      \n"
+
+  // Put any cores other than 0 to sleep
+  "MRC     p15, 0, R0, c0, c0, 5                   \n"  // Read MPIDR
+  "ANDS    R0, R0, #3                              \n"
+  "goToSleep:                                      \n"
+  "WFINE                                           \n"
+  "BNE     goToSleep                               \n"
+
+  // Reset SCTLR Settings
+  "MRC     p15, 0, R0, c1, c0, 0                   \n"  // Read CP15 System Control register
+  "BIC     R0, R0, #(0x1 << 12)                    \n"  // Clear I bit 12 to disable I Cache
+  "BIC     R0, R0, #(0x1 <<  2)                    \n"  // Clear C bit  2 to disable D Cache
+  "BIC     R0, R0, #0x1                            \n"  // Clear M bit  0 to disable MMU
+  "BIC     R0, R0, #(0x1 << 11)                    \n"  // Clear Z bit 11 to disable branch prediction
+  "BIC     R0, R0, #(0x1 << 13)                    \n"  // Clear V bit 13 to disable hivecs
+  "MCR     p15, 0, R0, c1, c0, 0                   \n"  // Write value back to CP15 System Control register
+  "ISB                                             \n"
+
+  // Configure ACTLR
+  "MRC     p15, 0, r0, c1, c0, 1                   \n"  // Read CP15 Auxiliary Control Register
+  "ORR     r0, r0, #(1 <<  1)                      \n"  // Enable L2 prefetch hint (UNK/WI since r4p1)
+  "MCR     p15, 0, r0, c1, c0, 1                   \n"  // Write CP15 Auxiliary Control Register
+
+  // Set Vector Base Address Register (VBAR) to point to this application's vector table
+  "LDR    R0, =Vectors                             \n"
+  "MCR    p15, 0, R0, c12, c0, 0                   \n"
+
+  // Setup Stack for each exceptional mode
+  "CPS    #0x11                                    \n"
+  "LDR    SP, =Image$$FIQ_STACK$$ZI$$Limit         \n"
+  "CPS    #0x12                                    \n"
+  "LDR    SP, =Image$$IRQ_STACK$$ZI$$Limit         \n"
+  "CPS    #0x13                                    \n"
+  "LDR    SP, =Image$$SVC_STACK$$ZI$$Limit         \n"
+  "CPS    #0x17                                    \n"
+  "LDR    SP, =Image$$ABT_STACK$$ZI$$Limit         \n"
+  "CPS    #0x1B                                    \n"
+  "LDR    SP, =Image$$UND_STACK$$ZI$$Limit         \n"
+  "CPS    #0x1F                                    \n"
+  "LDR    SP, =Image$$ARM_LIB_STACK$$ZI$$Limit     \n"
+
+  // Call SystemInit
+  "BL     SystemInit                               \n"
+
+  // Unmask interrupts
+  "CPSIE  if                                       \n"
+
+  // Call __main
+  "BL     __main                                   \n"
+  );
+}
+
+/*----------------------------------------------------------------------------
+  Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+  while(1);
+}

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/AC6/RTE/Device/ARMCA5/system_ARMCA5.c

@@ -0,0 +1,93 @@
+/******************************************************************************
+ * @file     system_ARMCA5.c
+ * @brief    CMSIS Device System Source File for ARM Cortex-A5 Device Series
+ * @version  V1.00
+ * @date     16 Mar 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+#include "irq_ctrl.h"
+
+#define  SYSTEM_CLOCK  12000000U
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  System Initialization
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+/* do not use global variables because this function is called before
+   reaching pre-main. RW section may be overwritten afterwards.          */
+
+  // Invalidate entire Unified TLB
+  __set_TLBIALL(0);
+
+  // Invalidate entire branch predictor array
+  __set_BPIALL(0);
+  __DSB();
+  __ISB();
+
+  //  Invalidate instruction cache and flush branch target cache
+  __set_ICIALLU(0);
+  __DSB();
+  __ISB();
+
+  //  Invalidate data cache
+  L1C_InvalidateDCacheAll();
+
+  // Create Translation Table
+  MMU_CreateTranslationTable();
+
+  // Enable MMU
+  MMU_Enable();
+
+  // Enable Caches
+  L1C_EnableCaches();
+  L1C_EnableBTAC();
+
+#if (__L2C_PRESENT == 1) 
+  // Enable GIC
+  L2C_Enable();
+#endif
+
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+  // Enable FPU
+  __FPU_Enable();
+#endif
+
+  // IRQ Initialize
+  IRQ_Initialize();
+}

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/AC6/RTE/Device/ARMCA5/system_ARMCA5.h

@@ -0,0 +1,65 @@
+/******************************************************************************
+ * @file     system_ARMCA5.h
+ * @brief    CMSIS Device System Header File for ARM Cortex-A Device Series
+ * @version  V1.00
+ * @date     16 Mar 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SYSTEM_ARMCA5_H
+#define __SYSTEM_ARMCA5_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+/**
+  \brief Setup the microcontroller system.
+
+   Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+  \brief  Update SystemCoreClock variable.
+
+   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/**
+  \brief  Create Translation Table.
+
+   Creates Memory Management Unit Translation Table.
+ */
+extern void MMU_CreateTranslationTable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_ARMCA5_H */

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/AC6/RTE/RTE_Components.h

@@ -0,0 +1,19 @@
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: CMSIS_CV_CA5_AC6
+ * RTE configuration: CMSIS_CV_CA5_AC6.rteconfig
+*/
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+/*
+ * Define the Device Header File:
+*/
+#define CMSIS_device_header "ARMCA5.h"
+
+#define RTE_CV_COREFUNC                       /* CORE Validation - Core Function tests enabled */
+#define RTE_CV_COREINSTR                      /* CORE Validation - Core Instruction tests enabled */
+
+#endif /* RTE_COMPONENTS_H */

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/GCC/.cproject

@@ -0,0 +1,172 @@
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+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
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+									<listOptionValue builtIn="false" value="ARMCA5"/>
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.paths.1273322408" name="Include paths (-I)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.paths" useByScannerDiscovery="true" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/CMSIS/Core_A/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/Device/ARM/ARMCA5/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE/CMSIS_CORE_Validation&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE/Device/ARMCA5&quot;"/>
+								</option>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.linker.1650363870" name="Cross ARM GNU C Linker" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.linker">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.gcsections.2017781938" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.gcsections" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.usenewlibnano.545020941" name="Use newlib-nano (--specs=nano.specs)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.usenewlibnano" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.other.132873437" name="Other linker flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.other" value="--specs=rdimon.specs" valueType="string"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.scriptfile.2065531619" name="Script files (-T)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.scriptfile" valueType="stringList">
+									<listOptionValue builtIn="false" value="ARMCA5.ld"/>
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.libs.32028998" name="Libraries (-l)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.libs" valueType="libs"/>
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.linker.input.1531565301" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.linker.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.329714974" name="Cross ARM GNU C++ Linker" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.gcsections.2003995007" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.gcsections" value="true" valueType="boolean"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.archiver.888521649" name="Cross ARM GNU Archiver" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.archiver"/>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.createflash.1457627937" name="Cross ARM GNU Create Flash Image" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.createflash"/>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.createlisting.1108787743" name="Cross ARM GNU Create Listing" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.createlisting">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.source.298982243" name="Display source (--source|-S)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.source" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.allheaders.950969910" name="Display all headers (--all-headers|-x)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.allheaders" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.demangle.634773924" name="Demangle names (--demangle|-C)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.demangle" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.linenumbers.1864228279" name="Display line numbers (--line-numbers|-l)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.linenumbers" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.wide.1502300413" name="Wide lines (--wide|-w)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.wide" value="true" valueType="boolean"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.printsize.769116872" name="Cross ARM GNU Print Size" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.printsize">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.printsize.format.444273048" name="Size format" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.printsize.format"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+					<sourceEntries>
+						<entry excluding="RTE/Device/ARMCA9/system_ARMCA9.h|RTE/Device/ARMCA9/system_ARMCA9.c|RTE/Device/ARMCA9/startup_ARMCA9.c|RTE/Device/ARMCA9/mmu_ARMCA9.c|RTE/Device/ARMCA9/mem_ARMCA9.h|RTE/Device/ARMCA9/ARMCA9.ld" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+					</sourceEntries>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="CMSIS_CV.com.arm.eclipse.build.project.v6.exe.base.var.arm_compiler_6-6.420431336" name="Executable" projectType="com.arm.eclipse.build.project.v6.exe.base.var.arm_compiler_6-6"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1902326704;ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1902326704.;ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.2036454939;ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input.1738674007">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+	<storageModule moduleId="com.arm.cmsis.project">
+		<rteConfig name="CMSIS_CV_CA5_GCC.rteconfig"/>
+		<toolChainAdapter id="com.arm.cmsis.pack.build.gnuarmeclipse.toolChainAdapter" name="Cross ARM GCC Toolchain Adapter"/>
+		<device Dcore="Cortex-A5" DcoreVersion="r0p1" Dendian="Little-endian" Dfamily="ARM Cortex A5" Dfpu="SP_FPU" Dmpu="MPU" Dname="ARMCA5" Dvendor="ARM:82" Pname=""/>
+		<files>
+			<file name="RTE/Device/ARMCA7/mmu_ARMCA7.c" version="1.0.0"/>
+			<file name="RTE/CMSIS_CORE_Validation/CV_Config.h" version="1.0.0"/>
+			<file name="RTE/Device/ARMCA5/mmu_ARMCA5.c" version="1.0.0"/>
+			<file name="RTE/Device/ARMCA7/system_ARMCA7.h" version="1.0.0"/>
+			<file name="RTE/Device/ARMCA5/system_ARMCA5.c" version="1.0.0"/>
+			<file name="RTE/Device/ARMCA9/mem_ARMCA9.h" version="1.0.0"/>
+			<file name="RTE/Device/ARMCA5/system_ARMCA5.h" version="1.0.0"/>
+			<file name="RTE/Device/ARMCA5/ARMCA5.ld" version="1.0.0"/>
+			<file name="RTE/Device/ARMCA9/startup_ARMCA9.c" version="1.0.0"/>
+			<file name="RTE/Device/ARMCA5/mem_ARMCA5.h" version="1.0.0"/>
+			<file name="RTE/Device/ARMCA7/mem_ARMCA7.h" version="1.0.0"/>
+			<file name="RTE/Device/ARMCA7/system_ARMCA7.c" version="1.0.0"/>
+			<file name="RTE/Device/ARMCA9/system_ARMCA9.c" version="1.0.0"/>
+			<file name="RTE/Device/ARMCA5/startup_ARMCA5.c" version="1.0.0"/>
+			<file name="RTE/Device/ARMCA9/ARMCA9.ld" version="1.0.0"/>
+			<file name="RTE/Device/ARMCA9/system_ARMCA9.h" version="1.0.0"/>
+			<file name="RTE/Device/ARMCA9/mmu_ARMCA9.c" version="1.0.0"/>
+		</files>
+	</storageModule>
+	<storageModule moduleId="refreshScope"/>
+</cproject>

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/GCC/.gitignore

@@ -0,0 +1 @@
+/Debug/

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/GCC/.project

@@ -0,0 +1,59 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>CMSIS_CV_CA5_GCC</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>com.arm.cmsis.pack.project.RteNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>RTE/CMSIS_CORE_Validation/CV_CoreAFunc.c</name>
+			<type>1</type>
+			<locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Source/CV_CoreAFunc.c</locationURI>
+		</link>
+		<link>
+			<name>RTE/CMSIS_CORE_Validation/CV_CoreInstr.c</name>
+			<type>1</type>
+			<locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Source/CV_CoreInstr.c</locationURI>
+		</link>
+		<link>
+			<name>RTE/CMSIS_CORE_Validation/CV_Framework.c</name>
+			<type>1</type>
+			<locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Source/CV_Framework.c</locationURI>
+		</link>
+		<link>
+			<name>RTE/CMSIS_CORE_Validation/CV_Report.c</name>
+			<type>1</type>
+			<locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Source/CV_Report.c</locationURI>
+		</link>
+		<link>
+			<name>RTE/CMSIS_CORE_Validation/cmsis_cv.c</name>
+			<type>1</type>
+			<locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Source/cmsis_cv.c</locationURI>
+		</link>
+		<link>
+			<name>RTE/Device/ARMCA5/irq_ctrl_gic.c</name>
+			<type>1</type>
+			<locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS/5.1.1-dev1/CMSIS/Core_A/Source/irq_ctrl_gic.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/GCC/.settings/language.settings.xml

@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+	<configuration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1902326704" name="Debug">
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+			<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="1707851622613763296" id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT GCC Built-in Compiler Settings Cross ARM" parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+				<language-scope id="org.eclipse.cdt.core.gcc"/>
+				<language-scope id="org.eclipse.cdt.core.g++"/>
+			</provider>
+		</extension>
+	</configuration>
+</project>

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/GCC/CMSIS_CV_CA5_GCC.rteconfig

@@ -0,0 +1,51 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<configuration xmlns:xs="http://www.w3.org/2001/XMLSchema-instance">
+<toolchain Tcompiler="GCC" Toutput="exe"/>
+<components>
+<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="1.0.0">
+<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+<file category="doc" name="CMSIS/Documentation/Core_A/html/index.html"/>
+<file category="include" name="CMSIS/Core_A/Include/"/>
+</component>
+<component Cclass="CMSIS CORE Validation" Cgroup="CoreFunc" Cvendor="ARM" Cversion="1.0.0">
+<package name="CMSIS-CORE_Validation" url="http://www.keil.com/pack" vendor="ARM" version="1.0.0-dev1"/>
+<file category="source" condition="ARMv7-A Device" name="Source/CV_CoreAFunc.c"/>
+</component>
+<component Cclass="CMSIS CORE Validation" Cgroup="CoreInstr" Cvendor="ARM" Cversion="1.0.0">
+<package name="CMSIS-CORE_Validation" url="http://www.keil.com/pack" vendor="ARM" version="1.0.0-dev1"/>
+<file category="source" name="Source/CV_CoreInstr.c"/>
+</component>
+<component Cclass="CMSIS CORE Validation" Cgroup="Framework" Cvendor="ARM" Cversion="1.0.0">
+<package name="CMSIS-CORE_Validation" url="http://www.keil.com/pack" vendor="ARM" version="1.0.0-dev1"/>
+<file category="include" name="Include/"/>
+<file category="header" name="Include/cmsis_cv.h"/>
+<file attr="config" category="header" condition="ARMv7-A Device" name="Source/ConfigA/CV_Config.h" version="1.0.0"/>
+<file category="source" name="Source/cmsis_cv.c"/>
+<file category="source" name="Source/CV_Framework.c"/>
+<file category="source" name="Source/CV_Report.c"/>
+</component>
+<component Capiversion="1.0.0" Cclass="Device" Cgroup="IRQ Controller" Csub="GIC" Cvendor="ARM" Cversion="1.0.0" deviceDependent="1">
+<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+<file category="sourceC" deviceDependent="1" name="CMSIS/Core_A/Source/irq_ctrl_gic.c"/>
+</component>
+<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" deviceDependent="1">
+<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+<file category="include" deviceDependent="1" name="Device/ARM/ARMCA5/Include/"/>
+<file attr="config" category="sourceC" deviceDependent="1" name="Device/ARM/ARMCA5/Source/system_ARMCA5.c" version="1.0.0"/>
+<file attr="config" category="sourceC" deviceDependent="1" name="Device/ARM/ARMCA5/Source/mmu_ARMCA5.c" version="1.0.0"/>
+<file attr="config" category="header" deviceDependent="1" name="Device/ARM/ARMCA5/Include/system_ARMCA5.h" version="1.0.0"/>
+<file attr="config" category="header" deviceDependent="1" name="Device/ARM/ARMCA5/Include/mem_ARMCA5.h" version="1.0.0"/>
+</component>
+</components>
+<apis>
+<api Capiversion="1.0.0" Cclass="Device" Cgroup="IRQ Controller" Cvendor="ARM" Cversion="1.0.0" exclusive="1">
+<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+<file category="header" name="CMSIS/Core_A/Include/irq_ctrl.h"/>
+</api>
+</apis>
+<device Dcore="Cortex-A5" DcoreVersion="r0p1" Dendian="Little-endian" Dfamily="ARM Cortex A5" Dfpu="SP_FPU" Dmpu="MPU" Dname="ARMCA5" Dvendor="ARM:82" Pname="">
+<url>http://www.keil.com/dd2/arm/armca5</url>
+<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+</device>
+<packages useAllLatestPacks="1"/>
+</configuration>

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/GCC/RTE/Device/ARMCA5/ARMCA5.ld

@@ -0,0 +1,181 @@
+#include "mem_ARMCA5.h" 
+
+MEMORY
+{
+  ROM (rx)   : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
+  L_TTB (rw) : ORIGIN = __TTB_BASE, LENGTH = __TTB_SIZE 
+  RAM (rwx)  : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
+}
+
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+
+        Image$$VECTORS$$Base = .;
+        * (RESET)
+        KEEP(*(.isr_vector))
+        Image$$VECTORS$$Limit = .;
+
+        *(SVC_TABLE)
+        *(.text*)
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        Image$$RO_DATA$$Base = .;
+        *(.rodata*)
+        Image$$RO_DATA$$Limit = .;
+
+        KEEP(*(.eh_frame*))
+    } > ROM
+
+    .ARM.extab : 
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > ROM
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ROM
+    __exidx_end = .;
+
+
+    .copy.table :
+    {
+        . = ALIGN(4);
+        __copy_table_start__ = .;
+        LONG (__etext)
+        LONG (__data_start__)
+        LONG (__data_end__ - __data_start__)
+        __copy_table_end__ = .;
+    } > ROM
+
+    .zero.table :
+    {
+        . = ALIGN(4);
+        __zero_table_start__ = .;
+        LONG (__bss_start__)
+        LONG (__bss_end__ - __bss_start__)
+        __zero_table_end__ = .;
+    } > ROM
+
+    __etext = .;
+        
+    .ttb :
+    {
+        Image$$TTB$$ZI$$Base = .;
+        . += __TTB_SIZE;
+        Image$$TTB$$ZI$$Limit = .;
+    } > L_TTB
+
+    .data : AT (__etext)
+    {
+        Image$$RW_DATA$$Base = .;
+        __data_start__ = .;
+        *(vtable)
+        *(.data*)
+        Image$$RW_DATA$$Limit = .;
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE (__fini_array_end = .);
+
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+
+    } > RAM
+
+    
+    .bss ALIGN(0x400):
+    {
+        Image$$ZI_DATA$$Base = .;
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        __bss_end__ = .;
+        Image$$ZI_DATA$$Limit = .;
+        __end__ = .;
+        end = __end__;
+    } > RAM
+
+#if defined(__HEAP_SIZE) && (__HEAP_SIZE > 0)    
+    .heap (NOLOAD):
+    {
+        . = ALIGN(8);
+        Image$$HEAP$$ZI$$Base = .;
+        . += __HEAP_SIZE;
+        Image$$HEAP$$ZI$$Limit = .;
+        __HeapLimit = .;
+    } > RAM  
+#endif
+
+    .stack (NOLOAD):
+    {
+        . = ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __FIQ_STACK_SIZE - __IRQ_STACK_SIZE - __SVC_STACK_SIZE - __ABT_STACK_SIZE - __UND_STACK_SIZE;
+        . = ALIGN(8);
+        
+        __StackTop = .;
+        Image$$SYS_STACK$$ZI$$Base = .;
+        . += __STACK_SIZE;
+        Image$$SYS_STACK$$ZI$$Limit = .;
+        __stack = .;
+
+        Image$$FIQ_STACK$$ZI$$Base = .;
+        . += __FIQ_STACK_SIZE;
+        Image$$FIQ_STACK$$ZI$$Limit = .;
+
+        Image$$IRQ_STACK$$ZI$$Base = .;
+        . += __IRQ_STACK_SIZE;
+        Image$$IRQ_STACK$$ZI$$Limit = .;
+
+        Image$$SVC_STACK$$ZI$$Base = .;
+        . += __SVC_STACK_SIZE;
+        Image$$SVC_STACK$$ZI$$Limit = .;
+
+        Image$$ABT_STACK$$ZI$$Base = .;
+        . += __ABT_STACK_SIZE;
+        Image$$ABT_STACK$$ZI$$Limit = .;
+
+        Image$$UND_STACK$$ZI$$Base = .;
+        . += __UND_STACK_SIZE;
+        Image$$UND_STACK$$ZI$$Limit = .;
+        
+    } > RAM
+}

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/GCC/RTE/Device/ARMCA5/mem_ARMCA5.h

@@ -0,0 +1,94 @@
+/**************************************************************************//**
+ * @file     mem_ARMCA5.h
+ * @brief    Memory base and size definitions (used in scatter file)
+ * @version  V1.00
+ * @date     16 Mar 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MEM_ARMCA5_H
+#define __MEM_ARMCA5_H
+
+/*----------------------------------------------------------------------------
+  User Stack & Heap size definition
+ *----------------------------------------------------------------------------*/
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- ROM Configuration ------------------------------------
+//
+// <h> ROM Configuration
+//   <o0> ROM Base Address <0x0-0xFFFFFFFF:8>
+//   <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE       0x80000000
+#define __ROM_SIZE       0x00200000
+
+/*--------------------- RAM Configuration -----------------------------------
+// <h> RAM Configuration
+//   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>
+//   <o1> RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//   <o2> RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//   <o3> ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//   <h> Stack / Heap Configuration
+//     <o4>  Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     <o5>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     <h> Exceptional Modes
+//       <o6> UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o7> ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o8> SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o9> IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o10> FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     </h>
+//   </h>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE       0x80200000
+#define __RAM_SIZE       0x00200000
+
+#define __RW_DATA_SIZE   0x00100000
+#define __ZI_DATA_SIZE   0x000F0000
+
+#define __STACK_SIZE     0x00001000
+#define __HEAP_SIZE      0x00008000
+
+#define __UND_STACK_SIZE 0x00000100
+#define __ABT_STACK_SIZE 0x00000100
+#define __SVC_STACK_SIZE 0x00000100
+#define __IRQ_STACK_SIZE 0x00000100
+#define __FIQ_STACK_SIZE 0x00000100
+
+/*----------------------------------------------------------------------------*/
+
+/*--------------------- TTB Configuration ------------------------------------
+//
+// <h> TTB Configuration
+//   <o0> TTB Base Address <0x0-0xFFFFFFFF:8>
+//   <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __TTB_BASE       0x80500000
+#define __TTB_SIZE       0x00004000
+
+#endif /* __MEM_ARMCA5_H */

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/GCC/RTE/Device/ARMCA5/mmu_ARMCA5.c

@@ -0,0 +1,235 @@
+/**************************************************************************//**
+ * @file     mmu_ARMCA5.c
+ * @brief    MMU Configuration for ARM Cortex-A5 Device Series
+ * @version  V1.00
+ * @date     16 Mar 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 ARM Cortex-A Series memory map
+
+                                                     Memory Type
+0xffffffff |--------------------------|             ------------
+           |       FLAG SYNC          |             Device Memory
+0xfffff000 |--------------------------|             ------------
+           |         Fault            |                Fault
+0xfff00000 |--------------------------|             ------------
+           |                          |                Normal
+           |                          |
+           |      Daughterboard       |
+           |         memory           |
+           |                          |
+0x80505000 |--------------------------|             ------------
+           |TTB (L2 Sync Flags   ) 4k |                Normal
+0x80504C00 |--------------------------|             ------------
+           |TTB (L2 Peripherals-B) 16k|                Normal
+0x80504800 |--------------------------|             ------------
+           |TTB (L2 Peripherals-A) 16k|                Normal
+0x80504400 |--------------------------|             ------------
+           |TTB (L2 Priv Periphs)  4k |                Normal
+0x80504000 |--------------------------|             ------------
+           |    TTB (L1 Descriptors)  |                Normal
+0x80500000 |--------------------------|             ------------
+           |           Heap           |                Normal
+           |--------------------------|             ------------
+           |          Stack           |                Normal
+0x80400000 |--------------------------|             ------------
+           |         ZI Data          |                Normal
+0x80300000 |--------------------------|             ------------
+           |         RW Data          |                Normal
+0x80200000 |--------------------------|             ------------
+           |         RO Data          |                Normal
+           |--------------------------|             ------------
+           |         RO Code          |              USH Normal
+0x80000000 |--------------------------|             ------------
+           |      Daughterboard       |                Fault
+           |      HSB AXI buses       |
+0x40000000 |--------------------------|             ------------
+           |      Daughterboard       |                Fault
+           |  test chips peripherals  |
+0x2c002000 |--------------------------|             ------------
+           |     Private Address      |            Device Memory
+0x2c000000 |--------------------------|             ------------
+           |      Daughterboard       |                Fault
+           |  test chips peripherals  |
+0x20000000 |--------------------------|             ------------
+           |       Peripherals        |           Device Memory RW/RO
+           |                          |              & Fault
+0x00000000 |--------------------------|
+*/
+
+// L1 Cache info and restrictions about architecture of the caches (CCSIR register):
+// Write-Through support *not* available
+// Write-Back support available.
+// Read allocation support available.
+// Write allocation support available.
+
+//Note: You should use the Shareable attribute carefully.
+//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings.
+//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
+//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
+
+//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
+//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
+//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
+
+
+//Following MMU configuration is expected
+//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
+//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
+//Domain 0 is always the Client domain
+//Descriptors should place all memory in domain 0
+
+#include "ARMCA5.h"
+
+
+// L2 table pointers
+//----------------------------------------
+#define PRIVATE_TABLE_L2_BASE_4k       (0x80504000) //Map 4k Private Address space
+#define SYNC_FLAGS_TABLE_L2_BASE_4k    (0x80504C00) //Map 4k Flag synchronization
+#define PERIPHERAL_A_TABLE_L2_BASE_64k (0x80504400) //Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF
+#define PERIPHERAL_B_TABLE_L2_BASE_64k (0x80504800) //Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF
+
+//--------------------- PERIPHERALS -------------------
+#define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M)
+#define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M)
+
+//--------------------- SYNC FLAGS --------------------
+#define FLAG_SYNC     0xFFFFF000
+#define F_SYNC_BASE   0xFFF00000  //1M aligned
+
+//Import symbols from linker
+extern uint32_t Image$$VECTORS$$Base;
+extern uint32_t Image$$RW_DATA$$Base;
+extern uint32_t Image$$ZI_DATA$$Base;
+extern uint32_t Image$$TTB$$ZI$$Base;
+
+static uint32_t Sect_Normal;     //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
+static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
+static uint32_t Sect_Normal_RO;  //as Sect_Normal_Cod, but not executable
+static uint32_t Sect_Normal_RW;  //as Sect_Normal_Cod, but writeable and not executable
+static uint32_t Sect_Device_RO;  //device, non-shareable, non-executable, ro, domain 0, base addr 0
+static uint32_t Sect_Device_RW;  //as Sect_Device_RO, but writeable
+
+/* Define global descriptors */
+static uint32_t Page_L1_4k  = 0x0;  //generic
+static uint32_t Page_L1_64k = 0x0;  //generic
+static uint32_t Page_4k_Device_RW;  //Shared device, not executable, rw, domain 0
+static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0
+
+void MMU_CreateTranslationTable(void)
+{
+    mmu_region_attributes_Type region;
+
+    //Create 4GB of faulting entries
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT);
+
+    /*
+     * Generate descriptors. Refer to core_ca.h to get information about attributes
+     *
+     */
+    //Create descriptors for Vectors, RO, RW, ZI sections
+    section_normal(Sect_Normal, region);
+    section_normal_cod(Sect_Normal_Cod, region);
+    section_normal_ro(Sect_Normal_RO, region);
+    section_normal_rw(Sect_Normal_RW, region);
+    //Create descriptors for peripherals
+    section_device_ro(Sect_Device_RO, region);
+    section_device_rw(Sect_Device_RW, region);
+    //Create descriptors for 64k pages
+    page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);
+    //Create descriptors for 4k pages
+    page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);
+
+
+    /*
+     *  Define MMU flat-map regions and attributes
+     *
+     */
+
+    //Define Image
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base, 1, Sect_Normal_Cod);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base, 1, Sect_Normal_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA$$Base, 1, Sect_Normal_RW);
+
+    //all DRAM executable, rw, cacheable - applications may choose to divide memory into ro executable
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$TTB$$ZI$$Base, 2043, Sect_Normal);
+
+    //--------------------- PERIPHERALS -------------------
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_FLASH_BASE0    , 64, Sect_Device_RO);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_FLASH_BASE1    , 64, Sect_Device_RO);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_SRAM_BASE      , 64, Sect_Device_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_VRAM_BASE      , 32, Sect_Device_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_ETHERNET_BASE  , 16, Sect_Device_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_USB_BASE       , 16, Sect_Device_RW);
+
+    // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C000000-0x1C00FFFF
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, PERIPHERAL_A_FAULT      , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
+    // Define peripheral range 0x1C000000-0x1C00FFFF
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_DAP_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_SYSTEM_REG_BASE,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_SERIAL_BASE    ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_AACI_BASE      ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_MMCI_BASE      ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_KMI0_BASE      ,  2, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_UART_BASE      ,  4, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_WDT_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+
+    // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C100000-0x1C10FFFF
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, PERIPHERAL_B_FAULT      , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
+    // Define peripheral range 0x1C100000-0x1C10FFFF
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_TIMER_BASE     ,  2, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_DVI_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_RTC_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_UART4_BASE     ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_CLCD_BASE      ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+
+    // Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory
+    MMU_TTPage4k (&Image$$TTB$$ZI$$Base, __get_CBAR()            ,256,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
+    // Define private address space entry.
+    MMU_TTPage4k (&Image$$TTB$$ZI$$Base, __get_CBAR()            ,  3,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+    // Define L2CC entry.  Uncomment if PL310 is present
+    //    MMU_TTPage4k (&Image$$TTB$$ZI$$Base, VE_A5_MP_PL310_BASE     ,  1,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+
+    // Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC)
+    MMU_TTPage4k (&Image$$TTB$$ZI$$Base, F_SYNC_BASE , 256, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
+    // Define synchronization space entry.
+    MMU_TTPage4k (&Image$$TTB$$ZI$$Base, FLAG_SYNC   ,   1, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+
+    /* Set location of level 1 page table
+    ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
+    ; 13:7  - 0x0
+    ; 6     - IRGN[0] 0x0 (Inner WB WA)
+    ; 5     - NOS     0x0 (Non-shared)
+    ; 4:3   - RGN     0x1 (Outer WB WA)
+    ; 2     - IMP     0x0 (Implementation Defined)
+    ; 1     - S       0x0 (Non-shared)
+    ; 0     - IRGN[1] 0x1 (Inner WB WA) */
+    __set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 9);
+    __ISB();
+
+    /* Set up domain access control register
+    ; We set domain 0 to Client and all other domains to No Access.
+    ; All translation table entries specify domain 0 */
+    __set_DACR(1);
+    __ISB();
+}

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/GCC/RTE/Device/ARMCA5/startup_ARMCA5.c

@@ -0,0 +1,138 @@
+/******************************************************************************
+ * @file     startup_ARMCA5.c
+ * @brief    CMSIS Device System Source File for ARM Cortex-A5 Device Series
+ * @version  V1.00
+ * @date     22 Feb 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <ARMCA5.h>
+
+/*----------------------------------------------------------------------------
+  Definitions
+ *----------------------------------------------------------------------------*/
+#define USR_MODE 0x10            // User mode
+#define FIQ_MODE 0x11            // Fast Interrupt Request mode
+#define IRQ_MODE 0x12            // Interrupt Request mode
+#define SVC_MODE 0x13            // Supervisor mode
+#define ABT_MODE 0x17            // Abort mode
+#define UND_MODE 0x1B            // Undefined Instruction mode
+#define SYS_MODE 0x1F            // System mode
+
+/*----------------------------------------------------------------------------
+  Internal References
+ *----------------------------------------------------------------------------*/
+void Vectors       (void) __attribute__ ((naked, section("RESET")));
+void Reset_Handler (void) __attribute__ ((naked));
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void PAbt_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void DAbt_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void IRQ_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void FIQ_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+void Vectors(void) {
+  __ASM volatile(
+  "LDR    PC, =Reset_Handler                        \n"
+  "LDR    PC, =Undef_Handler                        \n"
+  "LDR    PC, =SVC_Handler                          \n"
+  "LDR    PC, =PAbt_Handler                         \n"
+  "LDR    PC, =DAbt_Handler                         \n"
+  "NOP                                              \n"
+  "LDR    PC, =IRQ_Handler                          \n"
+  "LDR    PC, =FIQ_Handler                          \n"
+  );
+}
+
+/*----------------------------------------------------------------------------
+  Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+  __ASM volatile(
+
+  // Mask interrupts
+  "CPSID   if                                      \n"
+
+  // Put any cores other than 0 to sleep
+  "MRC     p15, 0, R0, c0, c0, 5                   \n"  // Read MPIDR
+  "ANDS    R0, R0, #3                              \n"
+  "goToSleep:                                      \n"
+  "WFINE                                           \n"
+  "BNE     goToSleep                               \n"
+
+  // Reset SCTLR Settings
+  "MRC     p15, 0, R0, c1, c0, 0                   \n"  // Read CP15 System Control register
+  "BIC     R0, R0, #(0x1 << 12)                    \n"  // Clear I bit 12 to disable I Cache
+  "BIC     R0, R0, #(0x1 <<  2)                    \n"  // Clear C bit  2 to disable D Cache
+  "BIC     R0, R0, #0x1                            \n"  // Clear M bit  0 to disable MMU
+  "BIC     R0, R0, #(0x1 << 11)                    \n"  // Clear Z bit 11 to disable branch prediction
+  "BIC     R0, R0, #(0x1 << 13)                    \n"  // Clear V bit 13 to disable hivecs
+  "MCR     p15, 0, R0, c1, c0, 0                   \n"  // Write value back to CP15 System Control register
+  "ISB                                             \n"
+
+  // Configure ACTLR
+  "MRC     p15, 0, r0, c1, c0, 1                   \n"  // Read CP15 Auxiliary Control Register
+  "ORR     r0, r0, #(1 <<  1)                      \n"  // Enable L2 prefetch hint (UNK/WI since r4p1)
+  "MCR     p15, 0, r0, c1, c0, 1                   \n"  // Write CP15 Auxiliary Control Register
+
+  // Set Vector Base Address Register (VBAR) to point to this application's vector table
+  "LDR    R0, =Vectors                             \n"
+  "MCR    p15, 0, R0, c12, c0, 0                   \n"
+
+  // Setup Stack for each exceptional mode
+  "CPS    #0x11                                    \n"
+  "LDR    SP, =Image$$FIQ_STACK$$ZI$$Limit         \n"
+  "CPS    #0x12                                    \n"
+  "LDR    SP, =Image$$IRQ_STACK$$ZI$$Limit         \n"
+  "CPS    #0x13                                    \n"
+  "LDR    SP, =Image$$SVC_STACK$$ZI$$Limit         \n"
+  "CPS    #0x17                                    \n"
+  "LDR    SP, =Image$$ABT_STACK$$ZI$$Limit         \n"
+  "CPS    #0x1B                                    \n"
+  "LDR    SP, =Image$$UND_STACK$$ZI$$Limit         \n"
+  "CPS    #0x1F                                    \n"
+  "LDR    SP, =Image$$SYS_STACK$$ZI$$Limit         \n"
+
+  // Call SystemInit
+  "BL     SystemInit                               \n"
+
+  // Unmask interrupts
+  "CPSIE  if                                       \n"
+
+  // Call __main
+  "BL     _start                                   \n"
+  );
+}
+
+/*----------------------------------------------------------------------------
+  Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+  while(1);
+}

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/GCC/RTE/Device/ARMCA5/system_ARMCA5.c

@@ -0,0 +1,93 @@
+/******************************************************************************
+ * @file     system_ARMCA5.c
+ * @brief    CMSIS Device System Source File for ARM Cortex-A5 Device Series
+ * @version  V1.00
+ * @date     16 Mar 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+#include "irq_ctrl.h"
+
+#define  SYSTEM_CLOCK  12000000U
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  System Initialization
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+/* do not use global variables because this function is called before
+   reaching pre-main. RW section may be overwritten afterwards.          */
+
+  // Invalidate entire Unified TLB
+  __set_TLBIALL(0);
+
+  // Invalidate entire branch predictor array
+  __set_BPIALL(0);
+  __DSB();
+  __ISB();
+
+  //  Invalidate instruction cache and flush branch target cache
+  __set_ICIALLU(0);
+  __DSB();
+  __ISB();
+
+  //  Invalidate data cache
+  L1C_InvalidateDCacheAll();
+
+  // Create Translation Table
+  MMU_CreateTranslationTable();
+
+  // Enable MMU
+  MMU_Enable();
+
+  // Enable Caches
+  L1C_EnableCaches();
+  L1C_EnableBTAC();
+
+#if (__L2C_PRESENT == 1) 
+  // Enable GIC
+  L2C_Enable();
+#endif
+
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+  // Enable FPU
+  __FPU_Enable();
+#endif
+
+  // IRQ Initialize
+  IRQ_Initialize();
+}

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/GCC/RTE/Device/ARMCA5/system_ARMCA5.h

@@ -0,0 +1,65 @@
+/******************************************************************************
+ * @file     system_ARMCA5.h
+ * @brief    CMSIS Device System Header File for ARM Cortex-A Device Series
+ * @version  V1.00
+ * @date     16 Mar 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SYSTEM_ARMCA5_H
+#define __SYSTEM_ARMCA5_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+/**
+  \brief Setup the microcontroller system.
+
+   Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+  \brief  Update SystemCoreClock variable.
+
+   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/**
+  \brief  Create Translation Table.
+
+   Creates Memory Management Unit Translation Table.
+ */
+extern void MMU_CreateTranslationTable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_ARMCA5_H */

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A5/GCC/RTE/RTE_Components.h

@@ -0,0 +1,19 @@
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: CMSIS_CV_CA5_GCC
+ * RTE configuration: CMSIS_CV_CA5_GCC.rteconfig
+*/
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+/*
+ * Define the Device Header File:
+*/
+#define CMSIS_device_header "ARMCA5.h"
+
+#define RTE_CV_COREFUNC                       /* CORE Validation - Core Function tests enabled */
+#define RTE_CV_COREINSTR                      /* CORE Validation - Core Instruction tests enabled */
+
+#endif /* RTE_COMPONENTS_H */

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/.settings/language.settings.xml

@@ -1,25 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<project>
-	<configuration id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1261257010" name="Cortex-A7 (AC5)">
-		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
-			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
-			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
-			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
-			<provider class="com.arm.eclipse.builder.armcc.discovery.ArmCompiler6LanguageSettingsProvider" console="false" env-hash="668963287638" id="com.arm.eclipse.builder.armcc.v6.langprovider" keep-relative-paths="false" name="ARM Compiler 6 Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
-				<language-scope id="org.eclipse.cdt.core.gcc"/>
-				<language-scope id="org.eclipse.cdt.core.g++"/>
-			</provider>
-		</extension>
-	</configuration>
-	<configuration id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1021881951" name="Cortex-A7 (AC6)">
-		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
-			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
-			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
-			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
-			<provider class="com.arm.eclipse.builder.armcc.discovery.ArmCompiler6LanguageSettingsProvider" console="false" env-hash="413551431901398524" id="com.arm.eclipse.builder.armcc.v6.langprovider" keep-relative-paths="false" name="ARM Compiler 6 Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
-				<language-scope id="org.eclipse.cdt.core.gcc"/>
-				<language-scope id="org.eclipse.cdt.core.g++"/>
-			</provider>
-		</extension>
-	</configuration>
-</project>

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/AC5/.cproject

@@ -0,0 +1,148 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1261257010">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1261257010" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1261257010" name="Debug" parent="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6">
+					<folderInfo id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1261257010." name="/" resourcePath="">
+						<toolChain id="com.arm.toolchain.baremetal.base.var.arm_compiler_5-5.1960502218" name="ARM Compiler 5" superClass="com.arm.toolchain.baremetal.base.var.arm_compiler_5-5">
+							<option id="com.arm.toolchain.ac5.option.target.cpu_fpu.1899004868" superClass="com.arm.toolchain.ac5.option.target.cpu_fpu" value="Cortex-A7.VFPv4.Neon" valueType="string"/>
+							<option id="com.arm.toolchain.ac5.option.fppcs.1215240395" name="Floating-point PCS" superClass="com.arm.toolchain.ac5.option.fppcs" value="com.arm.tool.c.compiler.option.fppcs.hard" valueType="enumerated"/>
+							<option id="com.arm.toolchain.ac5.option.inst.391027132" name="Instruction set" superClass="com.arm.toolchain.ac5.option.inst" value="com.arm.tool.c.compiler.option.inst.arm" valueType="enumerated"/>
+							<option id="com.arm.toolchain.ac5.options.libs.useMicroLib.1898820408" name="Use microlib" superClass="com.arm.toolchain.ac5.options.libs.useMicroLib" value="true" valueType="boolean"/>
+							<option id="com.arm.toolchain.ac5.option.endian.2047271088" name="Byte order" superClass="com.arm.toolchain.ac5.option.endian" value="com.arm.tool.c.compiler.option.endian.little" valueType="enumerated"/>
+							<targetPlatform id="com.arm.toolchain.baremetal.base.var.arm_compiler_5-5.1960502218.788792350" name=""/>
+							<builder buildPath="${workspace_loc:/CMSIS_CV}/Debug" id="org.eclipse.cdt.build.core.internal.builder.1105228045" keepEnvironmentInBuildfile="false" name="CDT Internal Builder" superClass="org.eclipse.cdt.build.core.internal.builder"/>
+							<tool id="com.arm.tool.c.compiler.base.var.arm_compiler_5-5.1006008870" name="ARM C Compiler 5" superClass="com.arm.tool.c.compiler.base.var.arm_compiler_5-5">
+								<option id="com.arm.tool.c.compiler.option.incpath.2039211042" name="Include path (-I)" superClass="com.arm.tool.c.compiler.option.incpath" useByScannerDiscovery="false" valueType="includePath"/>
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+								<option defaultValue="com.arm.tool.c.compiler.option.optlevel.min" id="com.arm.tool.c.compiler.option.optlevel.882659687" name="Optimization level" superClass="com.arm.tool.c.compiler.option.optlevel" useByScannerDiscovery="true" valueType="enumerated"/>
+								<option id="com.arm.tool.c.compiler.option.targetcpu.1426497902" name="Target CPU (--cpu)" superClass="com.arm.tool.c.compiler.option.targetcpu" useByScannerDiscovery="true" value="Cortex-A7" valueType="string"/>
+								<option id="com.arm.tool.c.compiler.option.fppcs.1692296380" name="Floating-point PCS (--apcs)" superClass="com.arm.tool.c.compiler.option.fppcs" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.option.fppcs.hard" valueType="enumerated"/>
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+								<option id="com.arm.tool.c.compiler.option.useMicroLib.829868509" name="Use microlib (-D__MICROLIB)" superClass="com.arm.tool.c.compiler.option.useMicroLib" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								<option id="com.arm.tool.c.compiler.option.implicit.defmac.768550198" name="Implicit Define macros" superClass="com.arm.tool.c.compiler.option.implicit.defmac" useByScannerDiscovery="true" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="_RTE_"/>
+									<listOptionValue builtIn="false" value="ARMCA7"/>
+								</option>
+								<option id="com.arm.tool.c.compiler.option.implicit.incpath.2077192262" name="Implicit Include paths" superClass="com.arm.tool.c.compiler.option.implicit.incpath" useByScannerDiscovery="false" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/CMSIS/Core_A/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/Device/ARM/ARMCA7/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE/CMSIS_CORE_Validation&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE/Device/ARMCA7&quot;"/>
+								</option>
+								<option id="com.arm.tool.c.compiler.option.debug.enableToolSpecificSettings.393339148" name="Enable tool specific settings" superClass="com.arm.tool.c.compiler.option.debug.enableToolSpecificSettings" useByScannerDiscovery="false" value="false" valueType="boolean"/>
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+								<inputType id="com.arm.tool.c.compiler.input.614264250" superClass="com.arm.tool.c.compiler.input"/>
+								<inputType id="com.arm.tool.cpp.compiler.input.1314721428" superClass="com.arm.tool.cpp.compiler.input"/>
+							</tool>
+							<tool id="com.arm.tool.cpp.compiler.base.var.arm_compiler_5-5.1697853860" name="ARM C++ Compiler 5" superClass="com.arm.tool.cpp.compiler.base.var.arm_compiler_5-5">
+								<option defaultValue="com.arm.tool.c.compiler.option.optlevel.min" id="com.arm.tool.c.compiler.option.optlevel.213031284" name="Optimization level" superClass="com.arm.tool.c.compiler.option.optlevel" valueType="enumerated"/>
+								<option id="com.arm.tool.c.compiler.option.implicit.defmac.794423957" name="Implicit Define macros" superClass="com.arm.tool.c.compiler.option.implicit.defmac" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="_RTE_"/>
+									<listOptionValue builtIn="false" value="ARMCA7"/>
+								</option>
+								<option id="com.arm.tool.c.compiler.option.implicit.incpath.1172356175" name="Implicit Include paths" superClass="com.arm.tool.c.compiler.option.implicit.incpath" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/CMSIS/Core_A/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/Device/ARM/ARMCA7/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE/CMSIS_CORE_Validation&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE/Device/ARMCA7&quot;"/>
+								</option>
+							</tool>
+							<tool id="com.arm.tool.assembler.base.var.arm_compiler_5-5.941503372" name="ARM Assembler 5" superClass="com.arm.tool.assembler.base.var.arm_compiler_5-5">
+								<option id="com.arm.tool.assembler.option.incpath.240180621" name="Include Path (-i)" superClass="com.arm.tool.assembler.option.incpath" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/CMSIS/Core_A/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/Device/ARM/ARMCA9/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE/CMSIS_CORE_Validation&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE/Device/ARMCA9&quot;"/>
+								</option>
+								<option id="com.arm.tool.assembler.option.cpu.6183565" name="Target CPU (--cpu)" superClass="com.arm.tool.assembler.option.cpu" value="Cortex-A7" valueType="string"/>
+								<option id="com.arm.tool.assembler.option.fppcs.1985670947" name="Floating-point PCS (--apcs)" superClass="com.arm.tool.assembler.option.fppcs" value="com.arm.tool.c.compiler.option.fppcs.hard" valueType="enumerated"/>
+								<option id="com.arm.tool.assembler.option.inst.2124977961" name="Instruction set" superClass="com.arm.tool.assembler.option.inst" value="com.arm.tool.c.compiler.option.inst.arm" valueType="enumerated"/>
+								<option id="com.arm.tool.assembler.option.useMicroLib.1202936635" name="Use microlib (--pd &quot;__MICROLIB SETA 1&quot;)" superClass="com.arm.tool.assembler.option.useMicroLib" value="true" valueType="boolean"/>
+								<option id="com.arm.tool.assembler.option.implicit.predefine.1654893854" name="Implicit Predefines" superClass="com.arm.tool.assembler.option.implicit.predefine" valueType="stringList">
+									<listOptionValue builtIn="false" value="_RTE_ SETA 1"/>
+									<listOptionValue builtIn="false" value="ARMCA7 SETA 1"/>
+								</option>
+								<option id="com.arm.tool.assembler.option.implicit.incpath.840007947" name="Implicit Include paths" superClass="com.arm.tool.assembler.option.implicit.incpath" valueType="includePath">
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+									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/Device/ARM/ARMCA7/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE/CMSIS_CORE_Validation&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE/Device/ARMCA7&quot;"/>
+								</option>
+								<option id="com.arm.tool.assembler.option.endian.938835271" name="Byte order" superClass="com.arm.tool.assembler.option.endian" value="com.arm.tool.c.compiler.option.endian.little" valueType="enumerated"/>
+								<inputType id="com.arm.tool.assembler.input.567242146" superClass="com.arm.tool.assembler.input"/>
+							</tool>
+							<tool id="com.arm.tool.c.linker.base.var.arm_compiler_5-5.1792565798" name="ARM Linker 5" superClass="com.arm.tool.c.linker.base.var.arm_compiler_5-5">
+								<option id="com.arm.tool.c.linker.option.cpu.2055858033" name="Target CPU (--cpu)" superClass="com.arm.tool.c.linker.option.cpu" value="Cortex-A7" valueType="string"/>
+								<option id="com.arm.tool.c.linker.option.useMicroLib.75487761" name="Use microlib" superClass="com.arm.tool.c.linker.option.useMicroLib" value="true" valueType="boolean"/>
+								<option id="com.arm.tool.c.linker.option.scatter.461693819" name="Scatter file (--scatter)" superClass="com.arm.tool.c.linker.option.scatter" value="${workspace_loc:/${ProjName}}/RTE/Device/ARMCA7/ARMCA7.sct" valueType="string"/>
+								<option id="com.arm.tool.c.linker.option.entry.2107333911" name="Image entry point (--entry)" superClass="com.arm.tool.c.linker.option.entry" value="Vectors" valueType="string"/>
+							</tool>
+							<tool id="com.arm.tool.librarian.base.var.arm_compiler_5-5.2146011430" name="ARM Librarian 5" superClass="com.arm.tool.librarian.base.var.arm_compiler_5-5"/>
+						</toolChain>
+					</folderInfo>
+					<sourceEntries>
+						<entry excluding="RTE/Device/ARMCA9/system_ARMCA9.h|RTE/Device/ARMCA9/system_ARMCA9.c|RTE/Device/ARMCA9/startup_ARMCA9.c|RTE/Device/ARMCA9/mmu_ARMCA9.c|RTE/Device/ARMCA9/mem_ARMCA9.h|RTE/Device/ARMCA9/ARMCA9.sct" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+					</sourceEntries>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="CMSIS_CV.com.arm.eclipse.build.project.v6.exe.base.var.arm_compiler_6-6.420431336" name="Executable" projectType="com.arm.eclipse.build.project.v6.exe.base.var.arm_compiler_6-6"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+	<storageModule moduleId="com.arm.cmsis.project">
+		<rteConfig name="CMSIS_CV_CA7_AC5.rteconfig"/>
+		<toolChainAdapter id="com.arm.cmsis.pack.build.armcc5.Armcc5ToolChainAdapter" name="Adapter for ARM C/C++ 5.x and 6.x toolchains"/>
+		<device Dcore="Cortex-A7" DcoreVersion="r0p5" Dendian="Little-endian" Dfamily="ARM Cortex A7" Dfpu="SP_FPU" Dmpu="MPU" Dname="ARMCA7" Dvendor="ARM:82" Pname=""/>
+		<files>
+			<file name="RTE/Device/ARMCA9/ARMCA9.sct" version="1.0.0"/>
+			<file name="RTE/Device/ARMCA7/ARMCA7.sct" version="1.0.0"/>
+			<file name="RTE/Device/ARMCA5/ARMCA5.sct" version="1.0.0"/>
+			<file name="RTE/Device/ARMCA7/mmu_ARMCA7.c" version="1.0.0"/>
+			<file name="RTE/CMSIS_CORE_Validation/CV_Config.h" version="1.0.0"/>
+			<file name="RTE/Device/ARMCA5/mmu_ARMCA5.c" version="1.0.0"/>
+			<file name="RTE/Device/ARMCA7/system_ARMCA7.h" version="1.0.0"/>
+			<file name="RTE/Device/ARMCA5/system_ARMCA5.c" version="1.0.0"/>
+			<file name="RTE/Device/ARMCA9/mem_ARMCA9.h" version="1.0.0"/>
+			<file name="RTE/Device/ARMCA5/system_ARMCA5.h" version="1.0.0"/>
+			<file name="RTE/Device/ARMCA9/startup_ARMCA9.c" version="1.0.0"/>
+			<file name="RTE/Device/ARMCA5/mem_ARMCA5.h" version="1.0.0"/>
+			<file name="RTE/Device/ARMCA7/mem_ARMCA7.h" version="1.0.0"/>
+			<file name="RTE/Device/ARMCA7/system_ARMCA7.c" version="1.0.0"/>
+			<file name="RTE/Device/ARMCA9/system_ARMCA9.c" version="1.0.0"/>
+			<file name="RTE/Device/ARMCA5/startup_ARMCA5.c" version="1.0.0"/>
+			<file name="RTE/Device/ARMCA9/system_ARMCA9.h" version="1.0.0"/>
+			<file name="RTE/Device/ARMCA7/startup_ARMCA7.c" version="1.0.0"/>
+			<file name="RTE/Device/ARMCA9/mmu_ARMCA9.c" version="1.0.0"/>
+		</files>
+	</storageModule>
+	<storageModule moduleId="com.arm.projectSettings" version="5.25"/>
+	<storageModule moduleId="refreshScope" versionNumber="2">
+		<configuration configurationName="Debug">
+			<resource resourceType="PROJECT" workspacePath="/CMSIS_CV"/>
+		</configuration>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+</cproject>

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/AC5/.gitignore

@@ -0,0 +1 @@
+/Debug/

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/.project → CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/AC5/.project

@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <projectDescription>
-	<name>CMSIS_CV</name>
+	<name>CMSIS_CV_CA7_AC5</name>
 	<comment></comment>
 	<projects>
 	</projects>
@@ -56,10 +56,4 @@
 			<locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS/5.1.1-dev1/CMSIS/Core_A/Source/irq_ctrl_gic.c</locationURI>
 		</link>
 	</linkedResources>
-	<variableList>
-		<variable>
-			<name>cmsis_pack_root</name>
-			<value>file:/C:/tools/Keil_v5/ARM/PACK</value>
-		</variable>
-	</variableList>
 </projectDescription>

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/AC5/.settings/language.settings.xml

@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+	<configuration id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1261257010" name="Debug">
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+			<provider class="com.arm.eclipse.builder.armcc.discovery.ArmCompiler5LanguageSettingsProvider" console="false" env-hash="-1212876469599902676" id="com.arm.eclipse.builder.armcc.v5.langprovider" keep-relative-paths="false" name="ARM Compiler 5 Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} --list-macros &quot;${INPUTS}&quot;" prefer-non-shared="true">
+				<language-scope id="com.arm.eclipse.builder.armcc.lang.c"/>
+				<language-scope id="com.arm.eclipse.builder.armcc.lang.cpp"/>
+			</provider>
+		</extension>
+	</configuration>
+</project>

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/CMSIS_CV.rteconfig → CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/AC5/CMSIS_CV_CA7_AC5.rteconfig

@@ -47,7 +47,7 @@
 <file category="header" name="CMSIS/Core_A/Include/irq_ctrl.h"/>
 </api>
 </apis>
-<device Dcore="Cortex-A7" DcoreVersion="r0p5" Dendian="Little-endian" Dfamily="ARM Cortex A7" Dfpu="DP_FPU" Dmpu="MPU" Dname="ARMCA7" Dvendor="ARM:82" Pname="">
+<device Dcore="Cortex-A7" DcoreVersion="r0p5" Dendian="Little-endian" Dfamily="ARM Cortex A7" Dfpu="SP_FPU" Dmpu="MPU" Dname="ARMCA7" Dvendor="ARM:82" Pname="">
 <url>http://www.keil.com/dd2/arm/armca7</url>
 <package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
 </device>

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/AC5/RTE/CMSIS_CORE_Validation/CV_Config.h

@@ -0,0 +1,96 @@
+/*-----------------------------------------------------------------------------
+ *      Name:         CV_Config.h 
+ *      Purpose:      CV Config header
+ *----------------------------------------------------------------------------
+ *      Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+#ifndef __CV_CONFIG_H
+#define __CV_CONFIG_H
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h> Common Test Settings
+// <o> Print Output Format <0=> Plain Text <1=> XML
+// <i> Set the test results output format to plain text or XML
+#ifndef PRINT_XML_REPORT
+#define PRINT_XML_REPORT            1
+#endif
+// <o> Buffer size for assertions results
+// <i> Set the buffer size for assertions results buffer
+#define BUFFER_ASSERTIONS           128U
+// </h>
+
+// <h> Disable Test Cases
+// <i> Uncheck to disable an individual test case
+// <q00> TC_CoreInstr_NOP
+// <q01> TC_CoreInstr_REV
+// <q02> TC_CoreInstr_REV16
+// <q03> TC_CoreInstr_REVSH
+// <q04> TC_CoreInstr_ROR
+// <q05> TC_CoreInstr_RBIT
+// <q06> TC_CoreInstr_CLZ
+// <q07> TC_CoreInstr_SSAT
+// <q08> TC_CoreInstr_USAT
+//
+// <q09> TC_CoreAFunc_FPSCR
+// <q10> TC_CoreAFunc_CPSR
+// <q11> TC_CoreAFunc_Mode
+// <q12> TC_CoreAFunc_SP
+// <q13> TC_CoreAFunc_SP_usr
+// <q14> TC_CoreAFunc_FPEXC
+// <q15> TC_COREAFUNC_ACTLR
+// <q16> TC_COREAFUNC_CPACR
+// <q17> TC_COREAFUNC_DFSR
+// <q18> TC_COREAFUNC_IFSR
+// <q19> TC_COREAFUNC_ISR
+// <q20> TC_COREAFUNC_CBAR
+// <q21> TC_COREAFUNC_TTBR0
+// <q22> TC_COREAFUNC_DACR
+// <q23> TC_COREAFUNC_SCTLR
+// <q24> TC_COREAFUNC_ACTRL
+// <q25> TC_COREAFUNC_MPIDR
+// <q26> TC_COREAFUNC_VBAR
+//
+// <q27> TC_GENTIMER_CNTFRQ
+// <q28> TC_GENTIMER_CNTP_TVAL
+// <q29> TC_GENTIMER_CNTP_CTL
+#define TC_COREINSTR_NOP_EN         1
+#define TC_COREINSTR_REV_EN         1
+#define TC_COREINSTR_REV16_EN       1
+#define TC_COREINSTR_REVSH_EN       1
+#define TC_COREINSTR_ROR_EN         1
+#define TC_COREINSTR_RBIT_EN        1
+#define TC_COREINSTR_CLZ_EN         1
+#define TC_COREINSTR_SSAT_EN        1
+#define TC_COREINSTR_USAT_EN        1
+
+#define TC_COREAFUNC_IRQ            1
+#define TC_COREAFUNC_FPSCR          1
+#define TC_COREAFUNC_CPSR           1
+#define TC_COREAFUNC_MODE           1
+#define TC_COREAFUNC_SP             1
+#define TC_COREAFUNC_SP_USR         1
+#define TC_COREAFUNC_FPEXC          1
+#define TC_COREAFUNC_ACTLR          1
+#define TC_COREAFUNC_CPACR          1
+#define TC_COREAFUNC_DFSR           1
+#define TC_COREAFUNC_IFSR           1
+#define TC_COREAFUNC_ISR            1
+#define TC_COREAFUNC_CBAR           1
+#define TC_COREAFUNC_TTBR0          1
+#define TC_COREAFUNC_DACR           1
+#define TC_COREAFUNC_SCTLR          1
+#define TC_COREAFUNC_ACTRL          1
+#define TC_COREAFUNC_MPIDR          1
+#define TC_COREAFUNC_VBAR           1
+
+#define TC_GENTIMER_CNTFRQ          1
+#define TC_GENTIMER_CNTP_TVAL       1
+#define TC_GENTIMER_CNTP_CTL        1
+// </h>
+
+#endif /* __CV_CONFIG_H */
+

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/RTE/RTE_Components.h → CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/AC5/RTE/RTE_Components.h

@@ -2,8 +2,8 @@
  * Auto generated Run-Time-Environment Component Configuration File
  *      *** Do not modify ! ***
  *
- * Project: CMSIS_CV
- * RTE configuration: CMSIS_CV.rteconfig
+ * Project: CMSIS_CV_CA7_AC5
+ * RTE configuration: CMSIS_CV_CA7_AC5.rteconfig
 */
 #ifndef RTE_COMPONENTS_H
 #define RTE_COMPONENTS_H

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/.cproject → CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/AC6/.cproject

@@ -1,126 +1,49 @@
 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
 <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
 	<storageModule moduleId="org.eclipse.cdt.core.settings">
-		<cconfiguration id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1261257010">
-			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1261257010" moduleId="org.eclipse.cdt.core.settings" name="Cortex-A7 (AC5)">
+		<cconfiguration id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1021881951">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1021881951" moduleId="org.eclipse.cdt.core.settings" name="Debug">
 				<externalSettings/>
 				<extensions>
 					<extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
 				</extensions>
 			</storageModule>
 			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
-				<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1261257010" name="Cortex-A7 (AC5)" parent="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6">
-					<folderInfo id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1261257010." name="/" resourcePath="">
-						<toolChain id="com.arm.toolchain.baremetal.base.var.arm_compiler_5-5.1960502218" name="ARM Compiler 5" superClass="com.arm.toolchain.baremetal.base.var.arm_compiler_5-5">
-							<option id="com.arm.toolchain.ac5.option.target.cpu_fpu.1899004868" superClass="com.arm.toolchain.ac5.option.target.cpu_fpu" value="Cortex-A7.VFPv4.Neon" valueType="string"/>
-							<option id="com.arm.toolchain.ac5.option.fppcs.1215240395" name="Floating-point PCS" superClass="com.arm.toolchain.ac5.option.fppcs" value="com.arm.tool.c.compiler.option.fppcs.hard" valueType="enumerated"/>
-							<option id="com.arm.toolchain.ac5.option.inst.391027132" name="Instruction set" superClass="com.arm.toolchain.ac5.option.inst" value="com.arm.tool.c.compiler.option.inst.arm" valueType="enumerated"/>
-							<option id="com.arm.toolchain.ac5.options.libs.useMicroLib.1898820408" name="Use microlib" superClass="com.arm.toolchain.ac5.options.libs.useMicroLib" value="true" valueType="boolean"/>
-							<option id="com.arm.toolchain.ac5.option.endian.2047271088" name="Byte order" superClass="com.arm.toolchain.ac5.option.endian" value="com.arm.tool.c.compiler.option.endian.little" valueType="enumerated"/>
-							<targetPlatform id="com.arm.toolchain.baremetal.base.var.arm_compiler_5-5.1960502218.788792350" name=""/>
-							<builder buildPath="${workspace_loc:/CMSIS_CV}/Debug" id="org.eclipse.cdt.build.core.internal.builder.1105228045" keepEnvironmentInBuildfile="false" name="CDT Internal Builder" superClass="org.eclipse.cdt.build.core.internal.builder"/>
-							<tool id="com.arm.tool.c.compiler.base.var.arm_compiler_5-5.1006008870" name="ARM C Compiler 5" superClass="com.arm.tool.c.compiler.base.var.arm_compiler_5-5">
-								<option id="com.arm.tool.c.compiler.option.incpath.2039211042" name="Include path (-I)" superClass="com.arm.tool.c.compiler.option.incpath" valueType="includePath"/>
-								<option id="com.arm.tool.c.compiler.option.defmac.1773701319" name="Define macro (-D)" superClass="com.arm.tool.c.compiler.option.defmac" valueType="definedSymbols"/>
-								<option defaultValue="com.arm.tool.c.compiler.option.optlevel.min" id="com.arm.tool.c.compiler.option.optlevel.882659687" name="Optimization level" superClass="com.arm.tool.c.compiler.option.optlevel" valueType="enumerated"/>
-								<option id="com.arm.tool.c.compiler.option.targetcpu.1426497902" name="Target CPU (--cpu)" superClass="com.arm.tool.c.compiler.option.targetcpu" value="Cortex-A7" valueType="string"/>
-								<option id="com.arm.tool.c.compiler.option.fppcs.1692296380" name="Floating-point PCS (--apcs)" superClass="com.arm.tool.c.compiler.option.fppcs" value="com.arm.tool.c.compiler.option.fppcs.hard" valueType="enumerated"/>
-								<option id="com.arm.tool.c.compiler.option.inst.743536123" name="Instruction set" superClass="com.arm.tool.c.compiler.option.inst" value="com.arm.tool.c.compiler.option.inst.arm" valueType="enumerated"/>
-								<option id="com.arm.tool.c.compiler.option.useMicroLib.829868509" name="Use microlib (-D__MICROLIB)" superClass="com.arm.tool.c.compiler.option.useMicroLib" value="true" valueType="boolean"/>
-								<option id="com.arm.tool.c.compiler.option.implicit.defmac.768550198" name="Implicit Define macros" superClass="com.arm.tool.c.compiler.option.implicit.defmac" valueType="definedSymbols">
-									<listOptionValue builtIn="false" value="_RTE_"/>
-									<listOptionValue builtIn="false" value="ARMCA7"/>
-								</option>
-								<option id="com.arm.tool.c.compiler.option.implicit.incpath.2077192262" name="Implicit Include paths" superClass="com.arm.tool.c.compiler.option.implicit.incpath" valueType="includePath">
+				<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1021881951" name="Debug" parent="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6">
+					<folderInfo id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1021881951." name="/" resourcePath="">
+						<toolChain id="com.arm.toolchain.v6.base.var.arm_compiler_6-6.1171348516" name="ARM Compiler 6" nonInternalBuilderId="com.arm.toolchain.v6.builder" superClass="com.arm.toolchain.v6.base.var.arm_compiler_6-6">
+							<option defaultValue="com.arm.tool.c.compiler.v6.base.options.debug.level.std" id="com.arm.toolchain.v6.base.options.debug.level.2082124093" name="Debug Level" superClass="com.arm.toolchain.v6.base.options.debug.level" valueType="enumerated"/>
+							<option id="com.arm.toolchain.v6.base.options.target.cpu_fpu.1043675356" superClass="com.arm.toolchain.v6.base.options.target.cpu_fpu" value="Cortex-A7.VFPv4.Neon" valueType="string"/>
+							<option id="com.arm.toolchain.v6.base.options.floatabi.1359327717" name="Float ABI" superClass="com.arm.toolchain.v6.base.options.floatabi" value="com.arm.tool.c.compiler.v6.base.option.floatabi.hard" valueType="enumerated"/>
+							<option id="com.arm.toolchain.v6.base.options.inst.394719799" name="Instruction set" superClass="com.arm.toolchain.v6.base.options.inst" value="com.arm.tool.c.compiler.v6.base.option.inst.arm" valueType="enumerated"/>
+							<option id="com.arm.toolchain.v6.base.options.libs.useMicroLib.1413293533" name="Use microlib" superClass="com.arm.toolchain.v6.base.options.libs.useMicroLib" value="true" valueType="boolean"/>
+							<option id="com.arm.toolchain.v6.base.options.endian.846610862" name="Byte order" superClass="com.arm.toolchain.v6.base.options.endian" value="com.arm.tool.c.compiler.v6.base.option.endian.little" valueType="enumerated"/>
+							<targetPlatform id="com.arm.toolchain.v6.base.var.arm_compiler_6-6.1171348516.207887278" name=""/>
+							<builder autoBuildTarget="all" buildPath="${workspace_loc:/CMSIS_CV_CA9_AC6}/Debug" cleanBuildTarget="clean" id="org.eclipse.cdt.build.core.internal.builder.1079377147" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="CDT Internal Builder" superClass="org.eclipse.cdt.build.core.internal.builder"/>
+							<tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.1485719566" name="ARM C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6">
+								<option id="com.arm.tool.c.compiler.v6.base.option.incpath.509984980" name="Include path (-I)" superClass="com.arm.tool.c.compiler.v6.base.option.incpath" useByScannerDiscovery="false" valueType="includePath">
 									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Include&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/CMSIS/Core_A/Include&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/Device/ARM/ARMCA7/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/Device/ARM/ARMCA9/Include&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE/CMSIS_CORE_Validation&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE/Device/ARMCA7&quot;"/>
-								</option>
-								<option id="com.arm.tool.c.compiler.option.debug.enableToolSpecificSettings.393339148" name="Enable tool specific settings" superClass="com.arm.tool.c.compiler.option.debug.enableToolSpecificSettings" value="false" valueType="boolean"/>
-								<option id="com.arm.tool.c.compiler.option.endian.1534570039" name="Byte order" superClass="com.arm.tool.c.compiler.option.endian" value="com.arm.tool.c.compiler.option.endian.little" valueType="enumerated"/>
-								<option id="com.arm.tool.c.compile.option.lang.1180588084" name="Source language mode" superClass="com.arm.tool.c.compile.option.lang" value="com.arm.tool.c.compile.option.lang.c99" valueType="enumerated"/>
-								<inputType id="com.arm.tool.c.compiler.input.614264250" superClass="com.arm.tool.c.compiler.input"/>
-								<inputType id="com.arm.tool.cpp.compiler.input.1314721428" superClass="com.arm.tool.cpp.compiler.input"/>
-							</tool>
-							<tool id="com.arm.tool.cpp.compiler.base.var.arm_compiler_5-5.1697853860" name="ARM C++ Compiler 5" superClass="com.arm.tool.cpp.compiler.base.var.arm_compiler_5-5">
-								<option defaultValue="com.arm.tool.c.compiler.option.optlevel.min" id="com.arm.tool.c.compiler.option.optlevel.213031284" name="Optimization level" superClass="com.arm.tool.c.compiler.option.optlevel" valueType="enumerated"/>
-								<option id="com.arm.tool.c.compiler.option.implicit.defmac.794423957" name="Implicit Define macros" superClass="com.arm.tool.c.compiler.option.implicit.defmac" valueType="definedSymbols">
-									<listOptionValue builtIn="false" value="_RTE_"/>
-									<listOptionValue builtIn="false" value="ARMCA7"/>
-								</option>
-								<option id="com.arm.tool.c.compiler.option.implicit.incpath.1172356175" name="Implicit Include paths" superClass="com.arm.tool.c.compiler.option.implicit.incpath" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE/Device/ARMCA9&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Include&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/CMSIS/Core_A/Include&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/Device/ARM/ARMCA7/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/Device/ARM/ARMCA9/Include&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE/CMSIS_CORE_Validation&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE/Device/ARMCA7&quot;"/>
-								</option>
-							</tool>
-							<tool id="com.arm.tool.assembler.base.var.arm_compiler_5-5.941503372" name="ARM Assembler 5" superClass="com.arm.tool.assembler.base.var.arm_compiler_5-5">
-								<option id="com.arm.tool.assembler.option.incpath.240180621" name="Include Path (-i)" superClass="com.arm.tool.assembler.option.incpath" valueType="includePath"/>
-								<option id="com.arm.tool.assembler.option.cpu.6183565" name="Target CPU (--cpu)" superClass="com.arm.tool.assembler.option.cpu" value="Cortex-A7" valueType="string"/>
-								<option id="com.arm.tool.assembler.option.fppcs.1985670947" name="Floating-point PCS (--apcs)" superClass="com.arm.tool.assembler.option.fppcs" value="com.arm.tool.c.compiler.option.fppcs.hard" valueType="enumerated"/>
-								<option id="com.arm.tool.assembler.option.inst.2124977961" name="Instruction set" superClass="com.arm.tool.assembler.option.inst" value="com.arm.tool.c.compiler.option.inst.arm" valueType="enumerated"/>
-								<option id="com.arm.tool.assembler.option.useMicroLib.1202936635" name="Use microlib (--pd &quot;__MICROLIB SETA 1&quot;)" superClass="com.arm.tool.assembler.option.useMicroLib" value="true" valueType="boolean"/>
-								<option id="com.arm.tool.assembler.option.implicit.predefine.1654893854" name="Implicit Predefines" superClass="com.arm.tool.assembler.option.implicit.predefine" valueType="stringList">
-									<listOptionValue builtIn="false" value="_RTE_ SETA 1"/>
-									<listOptionValue builtIn="false" value="ARMCA7 SETA 1"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE/Device/ARMCA9&quot;"/>
 								</option>
-								<option id="com.arm.tool.assembler.option.implicit.incpath.840007947" name="Implicit Include paths" superClass="com.arm.tool.assembler.option.implicit.incpath" valueType="includePath">
-									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Include&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/CMSIS/Core_A/Include&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/Device/ARM/ARMCA7/Include&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE/CMSIS_CORE_Validation&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE/Device/ARMCA7&quot;"/>
+								<option id="com.arm.tool.c.compiler.v6.base.option.defmac.71310516" name="Define macro (-D)" superClass="com.arm.tool.c.compiler.v6.base.option.defmac" useByScannerDiscovery="false" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="_RTE_"/>
+									<listOptionValue builtIn="false" value="ARMCA9"/>
 								</option>
-								<option id="com.arm.tool.assembler.option.endian.938835271" name="Byte order" superClass="com.arm.tool.assembler.option.endian" value="com.arm.tool.c.compiler.option.endian.little" valueType="enumerated"/>
-								<inputType id="com.arm.tool.assembler.input.567242146" superClass="com.arm.tool.assembler.input"/>
-							</tool>
-							<tool id="com.arm.tool.c.linker.base.var.arm_compiler_5-5.1792565798" name="ARM Linker 5" superClass="com.arm.tool.c.linker.base.var.arm_compiler_5-5">
-								<option id="com.arm.tool.c.linker.option.cpu.2055858033" name="Target CPU (--cpu)" superClass="com.arm.tool.c.linker.option.cpu" value="Cortex-A7" valueType="string"/>
-								<option id="com.arm.tool.c.linker.option.useMicroLib.75487761" name="Use microlib" superClass="com.arm.tool.c.linker.option.useMicroLib" value="true" valueType="boolean"/>
-								<option id="com.arm.tool.c.linker.option.scatter.461693819" name="Scatter file (--scatter)" superClass="com.arm.tool.c.linker.option.scatter" value="${workspace_loc:/${ProjName}}/RTE/Device/ARMCA7/ARMCA7.sct" valueType="string"/>
-								<option id="com.arm.tool.c.linker.option.entry.2107333911" name="Image entry point (--entry)" superClass="com.arm.tool.c.linker.option.entry" value="Vectors" valueType="string"/>
-							</tool>
-							<tool id="com.arm.tool.librarian.base.var.arm_compiler_5-5.2146011430" name="ARM Librarian 5" superClass="com.arm.tool.librarian.base.var.arm_compiler_5-5"/>
-						</toolChain>
-					</folderInfo>
-				</configuration>
-			</storageModule>
-			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
-		</cconfiguration>
-		<cconfiguration id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1021881951">
-			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1021881951" moduleId="org.eclipse.cdt.core.settings" name="Cortex-A7 (AC6)">
-				<externalSettings/>
-				<extensions>
-					<extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
-				</extensions>
-			</storageModule>
-			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
-				<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1021881951" name="Cortex-A7 (AC6)" parent="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6">
-					<folderInfo id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1021881951." name="/" resourcePath="">
-						<toolChain id="com.arm.toolchain.v6.base.var.arm_compiler_6-6.1171348516" name="ARM Compiler 6" superClass="com.arm.toolchain.v6.base.var.arm_compiler_6-6">
-							<option defaultValue="com.arm.tool.c.compiler.v6.base.options.debug.level.std" id="com.arm.toolchain.v6.base.options.debug.level.2082124093" name="Debug Level" superClass="com.arm.toolchain.v6.base.options.debug.level" valueType="enumerated"/>
-							<option id="com.arm.toolchain.v6.base.options.target.cpu_fpu.1043675356" superClass="com.arm.toolchain.v6.base.options.target.cpu_fpu" value="Cortex-A7.VFPv4" valueType="string"/>
-							<option id="com.arm.toolchain.v6.base.options.floatabi.1359327717" name="Float ABI" superClass="com.arm.toolchain.v6.base.options.floatabi" value="com.arm.tool.c.compiler.v6.base.option.floatabi.hard" valueType="enumerated"/>
-							<option id="com.arm.toolchain.v6.base.options.inst.394719799" name="Instruction set" superClass="com.arm.toolchain.v6.base.options.inst" value="com.arm.tool.c.compiler.v6.base.option.inst.arm" valueType="enumerated"/>
-							<option id="com.arm.toolchain.v6.base.options.libs.useMicroLib.1413293533" name="Use microlib" superClass="com.arm.toolchain.v6.base.options.libs.useMicroLib" value="true" valueType="boolean"/>
-							<option id="com.arm.toolchain.v6.base.options.endian.846610862" name="Byte order" superClass="com.arm.toolchain.v6.base.options.endian" value="com.arm.tool.c.compiler.v6.base.option.endian.little" valueType="enumerated"/>
-							<targetPlatform id="com.arm.toolchain.v6.base.var.arm_compiler_6-6.1171348516.207887278" name=""/>
-							<builder buildPath="${workspace_loc:/CMSIS_CV}/Debug" id="org.eclipse.cdt.build.core.internal.builder.512977327" keepEnvironmentInBuildfile="false" name="CDT Internal Builder" superClass="org.eclipse.cdt.build.core.internal.builder"/>
-							<tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.1485719566" name="ARM C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6">
-								<option id="com.arm.tool.c.compiler.v6.base.option.incpath.509984980" name="Include path (-I)" superClass="com.arm.tool.c.compiler.v6.base.option.incpath" useByScannerDiscovery="false" valueType="includePath"/>
-								<option id="com.arm.tool.c.compiler.v6.base.option.defmac.71310516" name="Define macro (-D)" superClass="com.arm.tool.c.compiler.v6.base.option.defmac" useByScannerDiscovery="false" valueType="definedSymbols"/>
 								<option defaultValue="com.arm.tool.c.compiler.v6.base.option.optlevel.min" id="com.arm.tool.c.compiler.v6.base.option.optlevel.1116740797" name="Optimization level" superClass="com.arm.tool.c.compiler.v6.base.option.optlevel" useByScannerDiscovery="true" valueType="enumerated"/>
 								<option defaultValue="com.arm.tool.c.compiler.v6.base.options.debug.level.std" id="com.arm.tool.c.compiler.v6.base.options.debug.level.1282091065" name="Debug Level" superClass="com.arm.tool.c.compiler.v6.base.options.debug.level" useByScannerDiscovery="true" valueType="enumerated"/>
 								<option id="com.arm.tool.c.compiler.v6.base.option.cpu.1622229999" name="CPU (-mcpu)" superClass="com.arm.tool.c.compiler.v6.base.option.cpu" useByScannerDiscovery="true" value="cortex-a7" valueType="string"/>
 								<option id="com.arm.tool.c.compiler.v6.base.option.target.715551531" name="Target (--target)" superClass="com.arm.tool.c.compiler.v6.base.option.target" useByScannerDiscovery="true" value="arm-arm-none-eabi" valueType="string"/>
-								<option id="com.arm.tool.c.compiler.v6.base.option.fpu.531976415" name="FPU (-mfpu)" superClass="com.arm.tool.c.compiler.v6.base.option.fpu" useByScannerDiscovery="true" value="vfpv4" valueType="string"/>
+								<option id="com.arm.tool.c.compiler.v6.base.option.fpu.531976415" name="FPU (-mfpu)" superClass="com.arm.tool.c.compiler.v6.base.option.fpu" useByScannerDiscovery="true" value="neon-vfpv4" valueType="string"/>
 								<option id="com.arm.tool.c.compiler.v6.base.option.floatabi.1123864924" name="Float ABI (-mfloat-abi)" superClass="com.arm.tool.c.compiler.v6.base.option.floatabi" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.floatabi.hard" valueType="enumerated"/>
 								<option id="com.arm.tool.c.compiler.v6.base.option.inst.908271468" name="Instruction set" superClass="com.arm.tool.c.compiler.v6.base.option.inst" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.inst.arm" valueType="enumerated"/>
 								<option id="com.arm.tool.c.compiler.v6.base.useMicroLib.722723634" name="Use microlib (-D__MICROLIB)" superClass="com.arm.tool.c.compiler.v6.base.useMicroLib" useByScannerDiscovery="false" value="true" valueType="boolean"/>
@@ -159,11 +82,24 @@
 								</option>
 							</tool>
 							<tool id="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6.475165834" name="ARM Assembler 6" superClass="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6">
-								<option id="com.arm.tool.assembler.v6.base.option.incpath.512319760" name="Include path (-I)" superClass="com.arm.tool.assembler.v6.base.option.incpath" valueType="includePath"/>
+								<option id="com.arm.tool.assembler.v6.base.option.incpath.512319760" name="Include path (-I)" superClass="com.arm.tool.assembler.v6.base.option.incpath" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/CMSIS/Core_A/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/Device/ARM/ARMCA9/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE/CMSIS_CORE_Validation&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE/Device/ARMCA9&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/CMSIS/Core_A/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${cmsis_pack_root}/ARM/CMSIS/5.1.1-dev1/Device/ARM/ARMCA9/Include&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE/CMSIS_CORE_Validation&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}/RTE/Device/ARMCA9&quot;"/>
+								</option>
 								<option defaultValue="com.arm.tool.assembler.v6.base.options.debug.level.std" id="com.arm.tool.assembler.v6.base.options.debug.level.1754017057" name="Debug Level" superClass="com.arm.tool.assembler.v6.base.options.debug.level" valueType="enumerated"/>
 								<option id="com.arm.tool.assembler.v6.base.option.cpu.1440642309" name="CPU (-mcpu)" superClass="com.arm.tool.assembler.v6.base.option.cpu" value="cortex-a7" valueType="string"/>
 								<option id="com.arm.tool.assembler.v6.base.option.target.2099316555" name="Target (--target)" superClass="com.arm.tool.assembler.v6.base.option.target" value="arm-arm-none-eabi" valueType="string"/>
-								<option id="com.arm.tool.assembler.v6.base.option.fpu.959648840" name="FPU (-mfpu)" superClass="com.arm.tool.assembler.v6.base.option.fpu" value="vfpv4" valueType="string"/>
+								<option id="com.arm.tool.assembler.v6.base.option.fpu.959648840" name="FPU (-mfpu)" superClass="com.arm.tool.assembler.v6.base.option.fpu" value="neon-vfpv4" valueType="string"/>
 								<option id="com.arm.tool.assembler.v6.base.option.floatabi.1026121137" name="Float ABI (-mfloat-abi)" superClass="com.arm.tool.assembler.v6.base.option.floatabi" value="com.arm.tool.c.compiler.v6.base.option.floatabi.hard" valueType="enumerated"/>
 								<option id="com.arm.tool.assembler.v6.base.option.inst.1080491485" name="Instruction set" superClass="com.arm.tool.assembler.v6.base.option.inst" value="com.arm.tool.c.compiler.v6.base.option.inst.arm" valueType="enumerated"/>
 								<option id="com.arm.tool.assembler.v6.base.useMicroLib.505841516" name="Use microlib (--pd &quot;__MICROLIB SETA 1&quot;)" superClass="com.arm.tool.assembler.v6.base.useMicroLib" value="true" valueType="boolean"/>
@@ -207,9 +143,9 @@
 	</storageModule>
 	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
 	<storageModule moduleId="com.arm.cmsis.project">
-		<rteConfig name="CMSIS_CV.rteconfig"/>
+		<rteConfig name="CMSIS_CV_CA7_AC6.rteconfig"/>
 		<toolChainAdapter id="com.arm.cmsis.pack.build.armcc5.Armcc5ToolChainAdapter" name="Adapter for ARM C/C++ 5.x and 6.x toolchains"/>
-		<device Dcore="Cortex-A7" DcoreVersion="r0p5" Dendian="Little-endian" Dfamily="ARM Cortex A7" Dfpu="DP_FPU" Dmpu="MPU" Dname="ARMCA7" Dvendor="ARM:82" Pname=""/>
+		<device Dcore="Cortex-A7" DcoreVersion="r0p5" Dendian="Little-endian" Dfamily="ARM Cortex A7" Dfpu="SP_FPU" Dmpu="MPU" Dname="ARMCA7" Dvendor="ARM:82" Pname=""/>
 		<files>
 			<file name="RTE/Device/ARMCA9/ARMCA9.sct" version="1.0.0"/>
 			<file name="RTE/Device/ARMCA7/ARMCA7.sct" version="1.0.0"/>

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/AC6/.gitignore

@@ -0,0 +1 @@
+/Debug/

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/AC6/.project

@@ -0,0 +1,59 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>CMSIS_CV_CA7_AC6</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>com.arm.cmsis.pack.project.RteNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>RTE/CMSIS_CORE_Validation/CV_CoreAFunc.c</name>
+			<type>1</type>
+			<locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Source/CV_CoreAFunc.c</locationURI>
+		</link>
+		<link>
+			<name>RTE/CMSIS_CORE_Validation/CV_CoreInstr.c</name>
+			<type>1</type>
+			<locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Source/CV_CoreInstr.c</locationURI>
+		</link>
+		<link>
+			<name>RTE/CMSIS_CORE_Validation/CV_Framework.c</name>
+			<type>1</type>
+			<locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Source/CV_Framework.c</locationURI>
+		</link>
+		<link>
+			<name>RTE/CMSIS_CORE_Validation/CV_Report.c</name>
+			<type>1</type>
+			<locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Source/CV_Report.c</locationURI>
+		</link>
+		<link>
+			<name>RTE/CMSIS_CORE_Validation/cmsis_cv.c</name>
+			<type>1</type>
+			<locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Source/cmsis_cv.c</locationURI>
+		</link>
+		<link>
+			<name>RTE/Device/ARMCA7/irq_ctrl_gic.c</name>
+			<type>1</type>
+			<locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS/5.1.1-dev1/CMSIS/Core_A/Source/irq_ctrl_gic.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/AC6/.settings/language.settings.xml

@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+	<configuration id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1021881951" name="Debug">
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+			<provider class="com.arm.eclipse.builder.armcc.discovery.ArmCompiler6LanguageSettingsProvider" console="false" env-hash="1217592296065668050" id="com.arm.eclipse.builder.armcc.v6.langprovider" keep-relative-paths="false" name="ARM Compiler 6 Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+				<language-scope id="org.eclipse.cdt.core.gcc"/>
+				<language-scope id="org.eclipse.cdt.core.g++"/>
+			</provider>
+		</extension>
+	</configuration>
+</project>

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/AC6/.settings/org.eclipse.cdt.managedbuilder.core.prefs

@@ -0,0 +1,5 @@
+eclipse.preferences.version=1
+environment/buildEnvironmentInclude/com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959/append=true
+environment/buildEnvironmentInclude/com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959/appendContributed=true
+environment/buildEnvironmentLibrary/com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959/append=true
+environment/buildEnvironmentLibrary/com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959/appendContributed=true

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/AC6/Abstract.txt

@@ -0,0 +1 @@
+CMSIS-CORE Validation Example Project

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/AC6/CMSIS_CV_CA7_AC6.rteconfig

@@ -0,0 +1,55 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<configuration xmlns:xs="http://www.w3.org/2001/XMLSchema-instance">
+<toolchain Tcompiler="ARMCC" Toutput="exe"/>
+<components>
+<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="1.0.0">
+<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+<file category="doc" name="CMSIS/Documentation/Core_A/html/index.html"/>
+<file category="include" name="CMSIS/Core_A/Include/"/>
+</component>
+<component Cclass="CMSIS CORE Validation" Cgroup="CoreFunc" Cvendor="ARM" Cversion="1.0.0">
+<package name="CMSIS-CORE_Validation" url="http://www.keil.com/pack" vendor="ARM" version="1.0.0-dev1"/>
+<file category="source" condition="ARMv7-A Device" name="Source/CV_CoreAFunc.c"/>
+</component>
+<component Cclass="CMSIS CORE Validation" Cgroup="CoreInstr" Cvendor="ARM" Cversion="1.0.0">
+<package name="CMSIS-CORE_Validation" url="http://www.keil.com/pack" vendor="ARM" version="1.0.0-dev1"/>
+<file category="source" name="Source/CV_CoreInstr.c"/>
+</component>
+<component Cclass="CMSIS CORE Validation" Cgroup="Framework" Cvendor="ARM" Cversion="1.0.0">
+<package name="CMSIS-CORE_Validation" url="http://www.keil.com/pack" vendor="ARM" version="1.0.0-dev1"/>
+<file category="include" name="Include/"/>
+<file category="header" name="Include/cmsis_cv.h"/>
+<file attr="config" category="header" condition="ARMv7-A Device" name="Source/ConfigA/CV_Config.h" version="1.0.0"/>
+<file category="source" name="Source/cmsis_cv.c"/>
+<file category="source" name="Source/CV_Framework.c"/>
+<file category="source" name="Source/CV_Report.c"/>
+</component>
+<component Capiversion="1.0.0" Cclass="Device" Cgroup="IRQ Controller" Csub="GIC" Cvendor="ARM" Cversion="1.0.0" deviceDependent="1">
+<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+<file category="sourceC" deviceDependent="1" name="CMSIS/Core_A/Source/irq_ctrl_gic.c"/>
+</component>
+<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" deviceDependent="1">
+<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+<file category="include" deviceDependent="1" name="Device/ARM/ARMCA7/Include/"/>
+<file attr="config" category="sourceC" condition="ARMCC5" deviceDependent="1" name="Device/ARM/ARMCA7/Source/AC5/startup_ARMCA7.c" version="1.0.0"/>
+<file attr="config" category="linkerScript" condition="ARMCC5" deviceDependent="1" name="Device/ARM/ARMCA7/Source/AC5/ARMCA7.sct" version="1.0.0"/>
+<file attr="config" category="sourceC" condition="ARMCC6" deviceDependent="1" name="Device/ARM/ARMCA7/Source/AC6/startup_ARMCA7.c" version="1.0.0"/>
+<file attr="config" category="linkerScript" condition="ARMCC6" deviceDependent="1" name="Device/ARM/ARMCA7/Source/AC6/ARMCA7.sct" version="1.0.0"/>
+<file attr="config" category="sourceC" deviceDependent="1" name="Device/ARM/ARMCA7/Source/system_ARMCA7.c" version="1.0.0"/>
+<file attr="config" category="sourceC" deviceDependent="1" name="Device/ARM/ARMCA7/Source/mmu_ARMCA7.c" version="1.0.0"/>
+<file attr="config" category="header" deviceDependent="1" name="Device/ARM/ARMCA7/Include/system_ARMCA7.h" version="1.0.0"/>
+<file attr="config" category="header" deviceDependent="1" name="Device/ARM/ARMCA7/Include/mem_ARMCA7.h" version="1.0.0"/>
+</component>
+</components>
+<apis>
+<api Capiversion="1.0.0" Cclass="Device" Cgroup="IRQ Controller" Cvendor="ARM" Cversion="1.0.0" exclusive="1">
+<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+<file category="header" name="CMSIS/Core_A/Include/irq_ctrl.h"/>
+</api>
+</apis>
+<device Dcore="Cortex-A7" DcoreVersion="r0p5" Dendian="Little-endian" Dfamily="ARM Cortex A7" Dfpu="SP_FPU" Dmpu="MPU" Dname="ARMCA7" Dvendor="ARM:82" Pname="">
+<url>http://www.keil.com/dd2/arm/armca7</url>
+<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+</device>
+<packages useAllLatestPacks="1"/>
+</configuration>

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/AC6/RTE/CMSIS_CORE_Validation/CV_Config.h

@@ -0,0 +1,96 @@
+/*-----------------------------------------------------------------------------
+ *      Name:         CV_Config.h 
+ *      Purpose:      CV Config header
+ *----------------------------------------------------------------------------
+ *      Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+#ifndef __CV_CONFIG_H
+#define __CV_CONFIG_H
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h> Common Test Settings
+// <o> Print Output Format <0=> Plain Text <1=> XML
+// <i> Set the test results output format to plain text or XML
+#ifndef PRINT_XML_REPORT
+#define PRINT_XML_REPORT            1
+#endif
+// <o> Buffer size for assertions results
+// <i> Set the buffer size for assertions results buffer
+#define BUFFER_ASSERTIONS           128U
+// </h>
+
+// <h> Disable Test Cases
+// <i> Uncheck to disable an individual test case
+// <q00> TC_CoreInstr_NOP
+// <q01> TC_CoreInstr_REV
+// <q02> TC_CoreInstr_REV16
+// <q03> TC_CoreInstr_REVSH
+// <q04> TC_CoreInstr_ROR
+// <q05> TC_CoreInstr_RBIT
+// <q06> TC_CoreInstr_CLZ
+// <q07> TC_CoreInstr_SSAT
+// <q08> TC_CoreInstr_USAT
+//
+// <q09> TC_CoreAFunc_FPSCR
+// <q10> TC_CoreAFunc_CPSR
+// <q11> TC_CoreAFunc_Mode
+// <q12> TC_CoreAFunc_SP
+// <q13> TC_CoreAFunc_SP_usr
+// <q14> TC_CoreAFunc_FPEXC
+// <q15> TC_COREAFUNC_ACTLR
+// <q16> TC_COREAFUNC_CPACR
+// <q17> TC_COREAFUNC_DFSR
+// <q18> TC_COREAFUNC_IFSR
+// <q19> TC_COREAFUNC_ISR
+// <q20> TC_COREAFUNC_CBAR
+// <q21> TC_COREAFUNC_TTBR0
+// <q22> TC_COREAFUNC_DACR
+// <q23> TC_COREAFUNC_SCTLR
+// <q24> TC_COREAFUNC_ACTRL
+// <q25> TC_COREAFUNC_MPIDR
+// <q26> TC_COREAFUNC_VBAR
+//
+// <q27> TC_GENTIMER_CNTFRQ
+// <q28> TC_GENTIMER_CNTP_TVAL
+// <q29> TC_GENTIMER_CNTP_CTL
+#define TC_COREINSTR_NOP_EN         1
+#define TC_COREINSTR_REV_EN         1
+#define TC_COREINSTR_REV16_EN       1
+#define TC_COREINSTR_REVSH_EN       1
+#define TC_COREINSTR_ROR_EN         1
+#define TC_COREINSTR_RBIT_EN        1
+#define TC_COREINSTR_CLZ_EN         1
+#define TC_COREINSTR_SSAT_EN        1
+#define TC_COREINSTR_USAT_EN        1
+
+#define TC_COREAFUNC_IRQ            1
+#define TC_COREAFUNC_FPSCR          1
+#define TC_COREAFUNC_CPSR           1
+#define TC_COREAFUNC_MODE           1
+#define TC_COREAFUNC_SP             1
+#define TC_COREAFUNC_SP_USR         1
+#define TC_COREAFUNC_FPEXC          1
+#define TC_COREAFUNC_ACTLR          1
+#define TC_COREAFUNC_CPACR          1
+#define TC_COREAFUNC_DFSR           1
+#define TC_COREAFUNC_IFSR           1
+#define TC_COREAFUNC_ISR            1
+#define TC_COREAFUNC_CBAR           1
+#define TC_COREAFUNC_TTBR0          1
+#define TC_COREAFUNC_DACR           1
+#define TC_COREAFUNC_SCTLR          1
+#define TC_COREAFUNC_ACTRL          1
+#define TC_COREAFUNC_MPIDR          1
+#define TC_COREAFUNC_VBAR           1
+
+#define TC_GENTIMER_CNTFRQ          1
+#define TC_GENTIMER_CNTP_TVAL       1
+#define TC_GENTIMER_CNTP_CTL        1
+// </h>
+
+#endif /* __CV_CONFIG_H */
+

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/AC6/RTE/Device/ARMCA7/ARMCA7.sct

@@ -0,0 +1,77 @@
+#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-a7 -xc
+;**************************************************
+; Copyright (c) 2017 ARM Ltd.  All rights reserved.
+;**************************************************
+
+; Scatter-file for RTX Example on Versatile Express
+
+; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.
+
+; This platform has 2GB SDRAM starting at 0x80000000.
+
+#include "mem_ARMCA7.h"
+
+SDRAM __ROM_BASE __ROM_SIZE       ; load region size_region
+{
+  VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address
+  {
+      * (RESET, +FIRST)         ; Vector table and other startup code
+      * (InRoot$$Sections)      ; All (library) code that must be in a root region
+      * (+RO-CODE)              ; Application RO code (.text)
+      * (+RO-DATA)              ; Application RO data (.constdata)
+  }
+  
+  RW_DATA __RAM_BASE __RW_DATA_SIZE
+  { * (+RW) }                   ; Application RW data (.data)
+  
+  ZI_DATA (__RAM_BASE+
+           __RW_DATA_SIZE) __ZI_DATA_SIZE
+  { * (+ZI) }                   ; Application ZI data (.bss)
+  
+  ARM_LIB_HEAP  (__RAM_BASE
+                +__RW_DATA_SIZE
+                +__ZI_DATA_SIZE)    EMPTY __HEAP_SIZE        ; Heap region growing up
+  { }
+    
+  ARM_LIB_STACK (__RAM_BASE
+                +__RAM_SIZE       
+                -__FIQ_STACK_SIZE
+                -__IRQ_STACK_SIZE
+                -__SVC_STACK_SIZE
+                -__ABT_STACK_SIZE
+                -__UND_STACK_SIZE) EMPTY -__STACK_SIZE      ; Stack region growing down
+  { }              
+                
+  UND_STACK     (__RAM_BASE
+                +__RAM_SIZE
+                -__FIQ_STACK_SIZE
+                -__IRQ_STACK_SIZE
+                -__SVC_STACK_SIZE
+                -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE  ; UND mode stack
+  { }
+  
+  ABT_STACK     (__RAM_BASE
+                +__RAM_SIZE
+                -__FIQ_STACK_SIZE
+                -__IRQ_STACK_SIZE
+                -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE  ; ABT mode stack
+  { }
+  
+  SVC_STACK     (__RAM_BASE
+                +__RAM_SIZE
+                -__FIQ_STACK_SIZE
+                -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE  ; SVC mode stack
+  { }  
+  
+  IRQ_STACK     (__RAM_BASE
+                +__RAM_SIZE
+                -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE  ; IRQ mode stack
+  { }  
+  
+  FIQ_STACK     (__RAM_BASE
+                +__RAM_SIZE)       EMPTY -__FIQ_STACK_SIZE  ; FIQ mode stack
+  { }
+  
+  TTB            __TTB_BASE        EMPTY __TTB_SIZE         ; Level-1 Translation Table for MMU
+  { }                                        
+}

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/AC6/RTE/Device/ARMCA7/mem_ARMCA7.h

@@ -0,0 +1,94 @@
+/**************************************************************************//**
+ * @file     mem_ARMCA7.h
+ * @brief    Memory base and size definitions (used in scatter file)
+ * @version  V1.00
+ * @date     22 Feb 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MEM_ARMCA7_H
+#define __MEM_ARMCA7_H
+
+/*----------------------------------------------------------------------------
+  User Stack & Heap size definition
+ *----------------------------------------------------------------------------*/
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- ROM Configuration ------------------------------------
+//
+// <h> ROM Configuration
+//   <o0> ROM Base Address <0x0-0xFFFFFFFF:8>
+//   <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE       0x80000000
+#define __ROM_SIZE       0x00200000
+
+/*--------------------- RAM Configuration -----------------------------------
+// <h> RAM Configuration
+//   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>
+//   <o1> RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//   <o2> RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//   <o3> ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//   <h> Stack / Heap Configuration
+//     <o4>  Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     <o5>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     <h> Exceptional Modes
+//       <o6> UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o7> ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o8> SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o9> IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o10> FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     </h>
+//   </h>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE       0x80200000
+#define __RAM_SIZE       0x00200000
+
+#define __RW_DATA_SIZE   0x00100000
+#define __ZI_DATA_SIZE   0x000F0000
+
+#define __STACK_SIZE     0x00001000
+#define __HEAP_SIZE      0x00008000
+
+#define __UND_STACK_SIZE 0x00000100
+#define __ABT_STACK_SIZE 0x00000100
+#define __SVC_STACK_SIZE 0x00000100
+#define __IRQ_STACK_SIZE 0x00000100
+#define __FIQ_STACK_SIZE 0x00000100
+
+/*----------------------------------------------------------------------------*/
+
+/*--------------------- TTB Configuration ------------------------------------
+//
+// <h> TTB Configuration
+//   <o0> TTB Base Address <0x0-0xFFFFFFFF:8>
+//   <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __TTB_BASE       0x80500000
+#define __TTB_SIZE       0x00004000
+
+#endif /* __MEM_ARMCA7_H */

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/AC6/RTE/Device/ARMCA7/mmu_ARMCA7.c

@@ -0,0 +1,235 @@
+/**************************************************************************//**
+ * @file     mmu_ARMCA7.c
+ * @brief    MMU Configuration for ARM Cortex-A7 Device Series
+ * @version  V1.00
+ * @date     22 Feb 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 ARM Cortex-A Series memory map
+
+                                                     Memory Type
+0xffffffff |--------------------------|             ------------
+           |       FLAG SYNC          |             Device Memory
+0xfffff000 |--------------------------|             ------------
+           |         Fault            |                Fault
+0xfff00000 |--------------------------|             ------------
+           |                          |                Normal
+           |                          |
+           |      Daughterboard       |
+           |         memory           |
+           |                          |
+0x80505000 |--------------------------|             ------------
+           |TTB (L2 Sync Flags   ) 4k |                Normal
+0x80504C00 |--------------------------|             ------------
+           |TTB (L2 Peripherals-B) 16k|                Normal
+0x80504800 |--------------------------|             ------------
+           |TTB (L2 Peripherals-A) 16k|                Normal
+0x80504400 |--------------------------|             ------------
+           |TTB (L2 Priv Periphs)  4k |                Normal
+0x80504000 |--------------------------|             ------------
+           |    TTB (L1 Descriptors)  |                Normal
+0x80500000 |--------------------------|             ------------
+           |           Heap           |                Normal
+           |--------------------------|             ------------
+           |          Stack           |                Normal
+0x80400000 |--------------------------|             ------------
+           |         ZI Data          |                Normal
+0x80300000 |--------------------------|             ------------
+           |         RW Data          |                Normal
+0x80200000 |--------------------------|             ------------
+           |         RO Data          |                Normal
+           |--------------------------|             ------------
+           |         RO Code          |              USH Normal
+0x80000000 |--------------------------|             ------------
+           |      Daughterboard       |                Fault
+           |      HSB AXI buses       |
+0x40000000 |--------------------------|             ------------
+           |      Daughterboard       |                Fault
+           |  test chips peripherals  |
+0x2c002000 |--------------------------|             ------------
+           |     Private Address      |            Device Memory
+0x2c000000 |--------------------------|             ------------
+           |      Daughterboard       |                Fault
+           |  test chips peripherals  |
+0x20000000 |--------------------------|             ------------
+           |       Peripherals        |           Device Memory RW/RO
+           |                          |              & Fault
+0x00000000 |--------------------------|
+*/
+
+// L1 Cache info and restrictions about architecture of the caches (CCSIR register):
+// Write-Through support *not* available
+// Write-Back support available.
+// Read allocation support available.
+// Write allocation support available.
+
+//Note: You should use the Shareable attribute carefully.
+//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings.
+//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
+//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
+
+//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
+//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
+//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
+
+
+//Following MMU configuration is expected
+//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
+//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
+//Domain 0 is always the Client domain
+//Descriptors should place all memory in domain 0
+
+#include "ARMCA7.h"
+
+
+// L2 table pointers
+//----------------------------------------
+#define PRIVATE_TABLE_L2_BASE_4k       (0x80504000) //Map 4k Private Address space
+#define SYNC_FLAGS_TABLE_L2_BASE_4k    (0x80504C00) //Map 4k Flag synchronization
+#define PERIPHERAL_A_TABLE_L2_BASE_64k (0x80504400) //Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF
+#define PERIPHERAL_B_TABLE_L2_BASE_64k (0x80504800) //Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF
+
+//--------------------- PERIPHERALS -------------------
+#define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M)
+#define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M)
+
+//--------------------- SYNC FLAGS --------------------
+#define FLAG_SYNC     0xFFFFF000
+#define F_SYNC_BASE   0xFFF00000  //1M aligned
+
+//Import symbols from linker
+extern uint32_t Image$$VECTORS$$Base;
+extern uint32_t Image$$RW_DATA$$Base;
+extern uint32_t Image$$ZI_DATA$$Base;
+extern uint32_t Image$$TTB$$ZI$$Base;
+
+static uint32_t Sect_Normal;     //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
+static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
+static uint32_t Sect_Normal_RO;  //as Sect_Normal_Cod, but not executable
+static uint32_t Sect_Normal_RW;  //as Sect_Normal_Cod, but writeable and not executable
+static uint32_t Sect_Device_RO;  //device, non-shareable, non-executable, ro, domain 0, base addr 0
+static uint32_t Sect_Device_RW;  //as Sect_Device_RO, but writeable
+
+/* Define global descriptors */
+static uint32_t Page_L1_4k  = 0x0;  //generic
+static uint32_t Page_L1_64k = 0x0;  //generic
+static uint32_t Page_4k_Device_RW;  //Shared device, not executable, rw, domain 0
+static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0
+
+void MMU_CreateTranslationTable(void)
+{
+    mmu_region_attributes_Type region;
+
+    //Create 4GB of faulting entries
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT);
+
+    /*
+     * Generate descriptors. Refer to core_ca.h to get information about attributes
+     *
+     */
+    //Create descriptors for Vectors, RO, RW, ZI sections
+    section_normal(Sect_Normal, region);
+    section_normal_cod(Sect_Normal_Cod, region);
+    section_normal_ro(Sect_Normal_RO, region);
+    section_normal_rw(Sect_Normal_RW, region);
+    //Create descriptors for peripherals
+    section_device_ro(Sect_Device_RO, region);
+    section_device_rw(Sect_Device_RW, region);
+    //Create descriptors for 64k pages
+    page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);
+    //Create descriptors for 4k pages
+    page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);
+
+
+    /*
+     *  Define MMU flat-map regions and attributes
+     *
+     */
+
+    //Define Image
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base, 1, Sect_Normal_Cod);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base, 1, Sect_Normal_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA$$Base, 1, Sect_Normal_RW);
+
+    //all DRAM executable, rw, cacheable - applications may choose to divide memory into ro executable
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$TTB$$ZI$$Base, 2043, Sect_Normal);
+
+    //--------------------- PERIPHERALS -------------------
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A7_MP_FLASH_BASE0    , 64, Sect_Device_RO);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A7_MP_FLASH_BASE1    , 64, Sect_Device_RO);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A7_MP_SRAM_BASE      , 64, Sect_Device_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A7_MP_VRAM_BASE      , 32, Sect_Device_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A7_MP_ETHERNET_BASE  , 16, Sect_Device_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A7_MP_USB_BASE       , 16, Sect_Device_RW);
+
+    // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C000000-0x1C00FFFF
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, PERIPHERAL_A_FAULT      , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
+    // Define peripheral range 0x1C000000-0x1C00FFFF
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A7_MP_DAP_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A7_MP_SYSTEM_REG_BASE,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A7_MP_SERIAL_BASE    ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A7_MP_AACI_BASE      ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A7_MP_MMCI_BASE      ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A7_MP_KMI0_BASE      ,  2, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A7_MP_UART_BASE      ,  4, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A7_MP_WDT_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+
+    // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C100000-0x1C10FFFF
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, PERIPHERAL_B_FAULT      , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
+    // Define peripheral range 0x1C100000-0x1C10FFFF
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A7_MP_TIMER_BASE     ,  2, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A7_MP_DVI_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A7_MP_RTC_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A7_MP_UART4_BASE     ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A7_MP_CLCD_BASE      ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+
+    // Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory
+    MMU_TTPage4k (&Image$$TTB$$ZI$$Base, __get_CBAR()            ,256,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
+    // Define private address space entry.
+    MMU_TTPage4k (&Image$$TTB$$ZI$$Base, __get_CBAR()            ,  3,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+    // Define L2CC entry.  Uncomment if PL310 is present
+    //    MMU_TTPage4k (&Image$$TTB$$ZI$$Base, VE_A7_MP_PL310_BASE     ,  1,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+
+    // Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC)
+    MMU_TTPage4k (&Image$$TTB$$ZI$$Base, F_SYNC_BASE , 256, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
+    // Define synchronization space entry.
+    MMU_TTPage4k (&Image$$TTB$$ZI$$Base, FLAG_SYNC   ,   1, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+
+    /* Set location of level 1 page table
+    ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
+    ; 13:7  - 0x0
+    ; 6     - IRGN[0] 0x0 (Inner WB WA)
+    ; 5     - NOS     0x0 (Non-shared)
+    ; 4:3   - RGN     0x1 (Outer WB WA)
+    ; 2     - IMP     0x0 (Implementation Defined)
+    ; 1     - S       0x0 (Non-shared)
+    ; 0     - IRGN[1] 0x1 (Inner WB WA) */
+    __set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 9);
+    __ISB();
+
+    /* Set up domain access control register
+    ; We set domain 0 to Client and all other domains to No Access.
+    ; All translation table entries specify domain 0 */
+    __set_DACR(1);
+    __ISB();
+}

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/AC6/RTE/Device/ARMCA7/startup_ARMCA7.c

@@ -0,0 +1,138 @@
+/******************************************************************************
+ * @file     startup_ARMCA7.c
+ * @brief    CMSIS Device System Source File for ARM Cortex-A9 Device Series
+ * @version  V1.00
+ * @date     22 Feb 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <ARMCA7.h>
+
+/*----------------------------------------------------------------------------
+  Definitions
+ *----------------------------------------------------------------------------*/
+#define USR_MODE 0x10            // User mode
+#define FIQ_MODE 0x11            // Fast Interrupt Request mode
+#define IRQ_MODE 0x12            // Interrupt Request mode
+#define SVC_MODE 0x13            // Supervisor mode
+#define ABT_MODE 0x17            // Abort mode
+#define UND_MODE 0x1B            // Undefined Instruction mode
+#define SYS_MODE 0x1F            // System mode
+
+/*----------------------------------------------------------------------------
+  Internal References
+ *----------------------------------------------------------------------------*/
+void Vectors       (void) __attribute__ ((naked, section("RESET")));
+void Reset_Handler (void) __attribute__ ((naked));
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void PAbt_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void DAbt_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void IRQ_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void FIQ_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+void Vectors(void) {
+  __ASM volatile(
+  "LDR    PC, =Reset_Handler                        \n"
+  "LDR    PC, =Undef_Handler                        \n"
+  "LDR    PC, =SVC_Handler                          \n"
+  "LDR    PC, =PAbt_Handler                         \n"
+  "LDR    PC, =DAbt_Handler                         \n"
+  "NOP                                              \n"
+  "LDR    PC, =IRQ_Handler                          \n"
+  "LDR    PC, =FIQ_Handler                          \n"
+  );
+}
+
+/*----------------------------------------------------------------------------
+  Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+  __ASM volatile(
+
+  // Mask interrupts
+  "CPSID   if                                      \n"
+
+  // Put any cores other than 0 to sleep
+  "MRC     p15, 0, R0, c0, c0, 5                   \n"  // Read MPIDR
+  "ANDS    R0, R0, #3                              \n"
+  "goToSleep:                                      \n"
+  "WFINE                                           \n"
+  "BNE     goToSleep                               \n"
+
+  // Reset SCTLR Settings
+  "MRC     p15, 0, R0, c1, c0, 0                   \n"  // Read CP15 System Control register
+  "BIC     R0, R0, #(0x1 << 12)                    \n"  // Clear I bit 12 to disable I Cache
+  "BIC     R0, R0, #(0x1 <<  2)                    \n"  // Clear C bit  2 to disable D Cache
+  "BIC     R0, R0, #0x1                            \n"  // Clear M bit  0 to disable MMU
+  "BIC     R0, R0, #(0x1 << 11)                    \n"  // Clear Z bit 11 to disable branch prediction
+  "BIC     R0, R0, #(0x1 << 13)                    \n"  // Clear V bit 13 to disable hivecs
+  "MCR     p15, 0, R0, c1, c0, 0                   \n"  // Write value back to CP15 System Control register
+  "ISB                                             \n"
+
+  // Configure ACTLR
+  "MRC     p15, 0, r0, c1, c0, 1                   \n"  // Read CP15 Auxiliary Control Register
+  "ORR     r0, r0, #(1 <<  1)                      \n"  // Enable L2 prefetch hint (UNK/WI since r4p1)
+  "MCR     p15, 0, r0, c1, c0, 1                   \n"  // Write CP15 Auxiliary Control Register
+
+  // Set Vector Base Address Register (VBAR) to point to this application's vector table
+  "LDR    R0, =Vectors                             \n"
+  "MCR    p15, 0, R0, c12, c0, 0                   \n"
+
+  // Setup Stack for each exceptional mode
+  "CPS    #0x11                                    \n"
+  "LDR    SP, =Image$$FIQ_STACK$$ZI$$Limit         \n"
+  "CPS    #0x12                                    \n"
+  "LDR    SP, =Image$$IRQ_STACK$$ZI$$Limit         \n"
+  "CPS    #0x13                                    \n"
+  "LDR    SP, =Image$$SVC_STACK$$ZI$$Limit         \n"
+  "CPS    #0x17                                    \n"
+  "LDR    SP, =Image$$ABT_STACK$$ZI$$Limit         \n"
+  "CPS    #0x1B                                    \n"
+  "LDR    SP, =Image$$UND_STACK$$ZI$$Limit         \n"
+  "CPS    #0x1F                                    \n"
+  "LDR    SP, =Image$$ARM_LIB_STACK$$ZI$$Limit     \n"
+
+  // Call SystemInit
+  "BL     SystemInit                               \n"
+
+  // Unmask interrupts
+  "CPSIE  if                                       \n"
+
+  // Call __main
+  "BL     __main                                   \n"
+  );
+}
+
+/*----------------------------------------------------------------------------
+  Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+  while(1);
+}

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/AC6/RTE/Device/ARMCA7/system_ARMCA7.c

@@ -0,0 +1,93 @@
+/******************************************************************************
+ * @file     system_ARMCA7.c
+ * @brief    CMSIS Device System Source File for ARM Cortex-A7 Device Series
+ * @version  V1.00
+ * @date     22 Feb 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+#include "irq_ctrl.h"
+
+#define  SYSTEM_CLOCK  12000000U
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  System Initialization
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+/* do not use global variables because this function is called before
+   reaching pre-main. RW section may be overwritten afterwards.          */
+
+  // Invalidate entire Unified TLB
+  __set_TLBIALL(0);
+
+  // Invalidate entire branch predictor array
+  __set_BPIALL(0);
+  __DSB();
+  __ISB();
+
+  //  Invalidate instruction cache and flush branch target cache
+  __set_ICIALLU(0);
+  __DSB();
+  __ISB();
+
+  //  Invalidate data cache
+  L1C_InvalidateDCacheAll();
+
+  // Create Translation Table
+  MMU_CreateTranslationTable();
+
+  // Enable MMU
+  MMU_Enable();
+
+  // Enable Caches
+  L1C_EnableCaches();
+  L1C_EnableBTAC();
+
+#if (__L2C_PRESENT == 1) 
+  // Enable GIC
+  L2C_Enable();
+#endif
+
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+  // Enable FPU
+  __FPU_Enable();
+#endif
+
+  // IRQ Initialize
+  IRQ_Initialize();
+}

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/AC6/RTE/Device/ARMCA7/system_ARMCA7.h

@@ -0,0 +1,65 @@
+/******************************************************************************
+ * @file     system_ARMCA7.h
+ * @brief    CMSIS Device System Header File for ARM Cortex-A Device Series
+ * @version  V1.00
+ * @date     22 Feb 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SYSTEM_ARMCA7_H
+#define __SYSTEM_ARMCA7_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+/**
+  \brief Setup the microcontroller system.
+
+   Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+  \brief  Update SystemCoreClock variable.
+
+   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/**
+  \brief  Create Translation Table.
+
+   Creates Memory Management Unit Translation Table.
+ */
+extern void MMU_CreateTranslationTable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_ARMCA7_H */

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/AC6/RTE/RTE_Components.h

@@ -0,0 +1,19 @@
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: CMSIS_CV_CA7_AC6
+ * RTE configuration: CMSIS_CV_CA7_AC6.rteconfig
+*/
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+/*
+ * Define the Device Header File:
+*/
+#define CMSIS_device_header "ARMCA7.h"
+
+#define RTE_CV_COREFUNC                       /* CORE Validation - Core Function tests enabled */
+#define RTE_CV_COREINSTR                      /* CORE Validation - Core Instruction tests enabled */
+
+#endif /* RTE_COMPONENTS_H */

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/AC6/main.c

@@ -0,0 +1,40 @@
+/*----------------------------------------------------------------------------
+ * Name:    main.c
+ *----------------------------------------------------------------------------*/
+
+/* Includes ------------------------------------------------------------------*/
+
+#include <stdio.h>
+
+#include "RTE_Components.h"
+#include  CMSIS_device_header
+ 
+#ifdef RTE_Compiler_EventRecorder
+#include "EventRecorder.h"
+#endif
+
+#include "cmsis_cv.h"
+
+
+/* Private functions ---------------------------------------------------------*/
+int main (void);
+
+/**
+  * @brief  Main program
+  * @param  None
+  * @retval None
+  */
+int main (void) {
+
+  // System Initialization
+  SystemCoreClockUpdate();
+#ifdef RTE_Compiler_EventRecorder
+  // Initialize and start Event Recorder
+  (void)EventRecorderInitialize(EventRecordError, 1U);
+  (void)EventRecorderEnable    (EventRecordAll, 0xFEU, 0xFEU);
+#endif
+  
+  cmsis_cv();
+  
+  for(;;) {}
+}

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/GCC/.cproject

@@ -0,0 +1,167 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1902326704">
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+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="${cross_rm} -rf" description="" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1902326704" name="Debug" parent="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug" prebuildStep="${cross_prefix}${cross_c}${cross_suffix} -x c -D_RTE_ -DARMCA7 -I../RTE/Device/ARMCA7 -E ../RTE/Device/ARMCA7/ARMCA7.ld -P -o ${OUTPUT_PREFIX}ARMCA7.ld">
+					<folderInfo id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1902326704." name="/" resourcePath="">
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+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+	<storageModule moduleId="com.arm.cmsis.project">
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+		<files>
+			<file name="RTE/Device/ARMCA7/mmu_ARMCA7.c" version="1.0.0"/>
+			<file name="RTE/CMSIS_CORE_Validation/CV_Config.h" version="1.0.0"/>
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CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/GCC/.gitignore

@@ -0,0 +1 @@
+/Debug/

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/GCC/.project

@@ -0,0 +1,59 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>CMSIS_CV_CA7_GCC</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>com.arm.cmsis.pack.project.RteNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>RTE/CMSIS_CORE_Validation/CV_CoreAFunc.c</name>
+			<type>1</type>
+			<locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Source/CV_CoreAFunc.c</locationURI>
+		</link>
+		<link>
+			<name>RTE/CMSIS_CORE_Validation/CV_CoreInstr.c</name>
+			<type>1</type>
+			<locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Source/CV_CoreInstr.c</locationURI>
+		</link>
+		<link>
+			<name>RTE/CMSIS_CORE_Validation/CV_Framework.c</name>
+			<type>1</type>
+			<locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Source/CV_Framework.c</locationURI>
+		</link>
+		<link>
+			<name>RTE/CMSIS_CORE_Validation/CV_Report.c</name>
+			<type>1</type>
+			<locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Source/CV_Report.c</locationURI>
+		</link>
+		<link>
+			<name>RTE/CMSIS_CORE_Validation/cmsis_cv.c</name>
+			<type>1</type>
+			<locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS-CORE_Validation/1.0.0-dev1/Source/cmsis_cv.c</locationURI>
+		</link>
+		<link>
+			<name>RTE/Device/ARMCA7/irq_ctrl_gic.c</name>
+			<type>1</type>
+			<locationURI>$%7Bcmsis_pack_root%7D/ARM/CMSIS/5.1.1-dev1/CMSIS/Core_A/Source/irq_ctrl_gic.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/GCC/.settings/language.settings.xml

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+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+	<configuration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1902326704" name="Debug">
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+			<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="1701345743509479328" id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT GCC Built-in Compiler Settings Cross ARM" parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+				<language-scope id="org.eclipse.cdt.core.gcc"/>
+				<language-scope id="org.eclipse.cdt.core.g++"/>
+			</provider>
+		</extension>
+	</configuration>
+</project>

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/GCC/.settings/org.eclipse.cdt.managedbuilder.core.prefs

@@ -0,0 +1,11 @@
+eclipse.preferences.version=1
+environment/buildEnvironmentInclude/ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1902326704/CPATH/delimiter=;
+environment/buildEnvironmentInclude/ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1902326704/CPATH/operation=remove
+environment/buildEnvironmentInclude/ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1902326704/C_INCLUDE_PATH/delimiter=;
+environment/buildEnvironmentInclude/ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1902326704/C_INCLUDE_PATH/operation=remove
+environment/buildEnvironmentInclude/ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1902326704/append=true
+environment/buildEnvironmentInclude/ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1902326704/appendContributed=true
+environment/buildEnvironmentLibrary/ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1902326704/LIBRARY_PATH/delimiter=;
+environment/buildEnvironmentLibrary/ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1902326704/LIBRARY_PATH/operation=remove
+environment/buildEnvironmentLibrary/ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1902326704/append=true
+environment/buildEnvironmentLibrary/ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.1902326704/appendContributed=true

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/GCC/Abstract.txt

@@ -0,0 +1 @@
+CMSIS-CORE Validation Example Project

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/GCC/CMSIS_CV_CA7_GCC.rteconfig

@@ -0,0 +1,51 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<configuration xmlns:xs="http://www.w3.org/2001/XMLSchema-instance">
+<toolchain Tcompiler="GCC" Toutput="exe"/>
+<components>
+<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="1.0.0">
+<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+<file category="doc" name="CMSIS/Documentation/Core_A/html/index.html"/>
+<file category="include" name="CMSIS/Core_A/Include/"/>
+</component>
+<component Cclass="CMSIS CORE Validation" Cgroup="CoreFunc" Cvendor="ARM" Cversion="1.0.0">
+<package name="CMSIS-CORE_Validation" url="http://www.keil.com/pack" vendor="ARM" version="1.0.0-dev1"/>
+<file category="source" condition="ARMv7-A Device" name="Source/CV_CoreAFunc.c"/>
+</component>
+<component Cclass="CMSIS CORE Validation" Cgroup="CoreInstr" Cvendor="ARM" Cversion="1.0.0">
+<package name="CMSIS-CORE_Validation" url="http://www.keil.com/pack" vendor="ARM" version="1.0.0-dev1"/>
+<file category="source" name="Source/CV_CoreInstr.c"/>
+</component>
+<component Cclass="CMSIS CORE Validation" Cgroup="Framework" Cvendor="ARM" Cversion="1.0.0">
+<package name="CMSIS-CORE_Validation" url="http://www.keil.com/pack" vendor="ARM" version="1.0.0-dev1"/>
+<file category="include" name="Include/"/>
+<file category="header" name="Include/cmsis_cv.h"/>
+<file attr="config" category="header" condition="ARMv7-A Device" name="Source/ConfigA/CV_Config.h" version="1.0.0"/>
+<file category="source" name="Source/cmsis_cv.c"/>
+<file category="source" name="Source/CV_Framework.c"/>
+<file category="source" name="Source/CV_Report.c"/>
+</component>
+<component Capiversion="1.0.0" Cclass="Device" Cgroup="IRQ Controller" Csub="GIC" Cvendor="ARM" Cversion="1.0.0" deviceDependent="1">
+<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+<file category="sourceC" deviceDependent="1" name="CMSIS/Core_A/Source/irq_ctrl_gic.c"/>
+</component>
+<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.0" deviceDependent="1">
+<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+<file category="include" deviceDependent="1" name="Device/ARM/ARMCA7/Include/"/>
+<file attr="config" category="sourceC" deviceDependent="1" name="Device/ARM/ARMCA7/Source/system_ARMCA7.c" version="1.0.0"/>
+<file attr="config" category="sourceC" deviceDependent="1" name="Device/ARM/ARMCA7/Source/mmu_ARMCA7.c" version="1.0.0"/>
+<file attr="config" category="header" deviceDependent="1" name="Device/ARM/ARMCA7/Include/system_ARMCA7.h" version="1.0.0"/>
+<file attr="config" category="header" deviceDependent="1" name="Device/ARM/ARMCA7/Include/mem_ARMCA7.h" version="1.0.0"/>
+</component>
+</components>
+<apis>
+<api Capiversion="1.0.0" Cclass="Device" Cgroup="IRQ Controller" Cvendor="ARM" Cversion="1.0.0" exclusive="1">
+<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+<file category="header" name="CMSIS/Core_A/Include/irq_ctrl.h"/>
+</api>
+</apis>
+<device Dcore="Cortex-A7" DcoreVersion="r0p5" Dendian="Little-endian" Dfamily="ARM Cortex A7" Dfpu="SP_FPU" Dmpu="MPU" Dname="ARMCA7" Dvendor="ARM:82" Pname="">
+<url>http://www.keil.com/dd2/arm/armca7</url>
+<package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/>
+</device>
+<packages useAllLatestPacks="1"/>
+</configuration>

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/GCC/RTE/Device/ARMCA7/ARMCA7.ld

@@ -0,0 +1,181 @@
+#include "mem_ARMCA7.h" 
+
+MEMORY
+{
+  ROM (rx)   : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
+  L_TTB (rw) : ORIGIN = __TTB_BASE, LENGTH = __TTB_SIZE 
+  RAM (rwx)  : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
+}
+
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+
+        Image$$VECTORS$$Base = .;
+        * (RESET)
+        KEEP(*(.isr_vector))
+        Image$$VECTORS$$Limit = .;
+
+        *(SVC_TABLE)
+        *(.text*)
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        Image$$RO_DATA$$Base = .;
+        *(.rodata*)
+        Image$$RO_DATA$$Limit = .;
+
+        KEEP(*(.eh_frame*))
+    } > ROM
+
+    .ARM.extab : 
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > ROM
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ROM
+    __exidx_end = .;
+
+
+    .copy.table :
+    {
+        . = ALIGN(4);
+        __copy_table_start__ = .;
+        LONG (__etext)
+        LONG (__data_start__)
+        LONG (__data_end__ - __data_start__)
+        __copy_table_end__ = .;
+    } > ROM
+
+    .zero.table :
+    {
+        . = ALIGN(4);
+        __zero_table_start__ = .;
+        LONG (__bss_start__)
+        LONG (__bss_end__ - __bss_start__)
+        __zero_table_end__ = .;
+    } > ROM
+
+    __etext = .;
+        
+    .ttb :
+    {
+        Image$$TTB$$ZI$$Base = .;
+        . += __TTB_SIZE;
+        Image$$TTB$$ZI$$Limit = .;
+    } > L_TTB
+
+    .data : AT (__etext)
+    {
+        Image$$RW_DATA$$Base = .;
+        __data_start__ = .;
+        *(vtable)
+        *(.data*)
+        Image$$RW_DATA$$Limit = .;
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE (__fini_array_end = .);
+
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+
+    } > RAM
+
+    
+    .bss ALIGN(0x400):
+    {
+        Image$$ZI_DATA$$Base = .;
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        __bss_end__ = .;
+        Image$$ZI_DATA$$Limit = .;
+        __end__ = .;
+        end = __end__;
+    } > RAM
+
+#if defined(__HEAP_SIZE) && (__HEAP_SIZE > 0)    
+    .heap (NOLOAD):
+    {
+        . = ALIGN(8);
+        Image$$HEAP$$ZI$$Base = .;
+        . += __HEAP_SIZE;
+        Image$$HEAP$$ZI$$Limit = .;
+        __HeapLimit = .;
+    } > RAM  
+#endif
+
+    .stack (NOLOAD):
+    {
+        . = ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __FIQ_STACK_SIZE - __IRQ_STACK_SIZE - __SVC_STACK_SIZE - __ABT_STACK_SIZE - __UND_STACK_SIZE;
+        . = ALIGN(8);
+        
+        __StackTop = .;
+        Image$$SYS_STACK$$ZI$$Base = .;
+        . += __STACK_SIZE;
+        Image$$SYS_STACK$$ZI$$Limit = .;
+        __stack = .;
+
+        Image$$FIQ_STACK$$ZI$$Base = .;
+        . += __FIQ_STACK_SIZE;
+        Image$$FIQ_STACK$$ZI$$Limit = .;
+
+        Image$$IRQ_STACK$$ZI$$Base = .;
+        . += __IRQ_STACK_SIZE;
+        Image$$IRQ_STACK$$ZI$$Limit = .;
+
+        Image$$SVC_STACK$$ZI$$Base = .;
+        . += __SVC_STACK_SIZE;
+        Image$$SVC_STACK$$ZI$$Limit = .;
+
+        Image$$ABT_STACK$$ZI$$Base = .;
+        . += __ABT_STACK_SIZE;
+        Image$$ABT_STACK$$ZI$$Limit = .;
+
+        Image$$UND_STACK$$ZI$$Base = .;
+        . += __UND_STACK_SIZE;
+        Image$$UND_STACK$$ZI$$Limit = .;
+        
+    } > RAM
+}

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/GCC/RTE/Device/ARMCA7/mem_ARMCA7.h

@@ -0,0 +1,94 @@
+/**************************************************************************//**
+ * @file     mem_ARMCA7.h
+ * @brief    Memory base and size definitions (used in scatter file)
+ * @version  V1.00
+ * @date     22 Feb 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MEM_ARMCA7_H
+#define __MEM_ARMCA7_H
+
+/*----------------------------------------------------------------------------
+  User Stack & Heap size definition
+ *----------------------------------------------------------------------------*/
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- ROM Configuration ------------------------------------
+//
+// <h> ROM Configuration
+//   <o0> ROM Base Address <0x0-0xFFFFFFFF:8>
+//   <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE       0x80000000
+#define __ROM_SIZE       0x00200000
+
+/*--------------------- RAM Configuration -----------------------------------
+// <h> RAM Configuration
+//   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>
+//   <o1> RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//   <o2> RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//   <o3> ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//   <h> Stack / Heap Configuration
+//     <o4>  Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     <o5>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     <h> Exceptional Modes
+//       <o6> UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o7> ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o8> SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o9> IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o10> FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     </h>
+//   </h>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE       0x80200000
+#define __RAM_SIZE       0x00200000
+
+#define __RW_DATA_SIZE   0x00100000
+#define __ZI_DATA_SIZE   0x000F0000
+
+#define __STACK_SIZE     0x00001000
+#define __HEAP_SIZE      0x00008000
+
+#define __UND_STACK_SIZE 0x00000100
+#define __ABT_STACK_SIZE 0x00000100
+#define __SVC_STACK_SIZE 0x00000100
+#define __IRQ_STACK_SIZE 0x00000100
+#define __FIQ_STACK_SIZE 0x00000100
+
+/*----------------------------------------------------------------------------*/
+
+/*--------------------- TTB Configuration ------------------------------------
+//
+// <h> TTB Configuration
+//   <o0> TTB Base Address <0x0-0xFFFFFFFF:8>
+//   <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __TTB_BASE       0x80500000
+#define __TTB_SIZE       0x00004000
+
+#endif /* __MEM_ARMCA7_H */

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/GCC/RTE/Device/ARMCA7/mmu_ARMCA7.c

@@ -0,0 +1,235 @@
+/**************************************************************************//**
+ * @file     mmu_ARMCA7.c
+ * @brief    MMU Configuration for ARM Cortex-A7 Device Series
+ * @version  V1.00
+ * @date     22 Feb 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 ARM Cortex-A Series memory map
+
+                                                     Memory Type
+0xffffffff |--------------------------|             ------------
+           |       FLAG SYNC          |             Device Memory
+0xfffff000 |--------------------------|             ------------
+           |         Fault            |                Fault
+0xfff00000 |--------------------------|             ------------
+           |                          |                Normal
+           |                          |
+           |      Daughterboard       |
+           |         memory           |
+           |                          |
+0x80505000 |--------------------------|             ------------
+           |TTB (L2 Sync Flags   ) 4k |                Normal
+0x80504C00 |--------------------------|             ------------
+           |TTB (L2 Peripherals-B) 16k|                Normal
+0x80504800 |--------------------------|             ------------
+           |TTB (L2 Peripherals-A) 16k|                Normal
+0x80504400 |--------------------------|             ------------
+           |TTB (L2 Priv Periphs)  4k |                Normal
+0x80504000 |--------------------------|             ------------
+           |    TTB (L1 Descriptors)  |                Normal
+0x80500000 |--------------------------|             ------------
+           |           Heap           |                Normal
+           |--------------------------|             ------------
+           |          Stack           |                Normal
+0x80400000 |--------------------------|             ------------
+           |         ZI Data          |                Normal
+0x80300000 |--------------------------|             ------------
+           |         RW Data          |                Normal
+0x80200000 |--------------------------|             ------------
+           |         RO Data          |                Normal
+           |--------------------------|             ------------
+           |         RO Code          |              USH Normal
+0x80000000 |--------------------------|             ------------
+           |      Daughterboard       |                Fault
+           |      HSB AXI buses       |
+0x40000000 |--------------------------|             ------------
+           |      Daughterboard       |                Fault
+           |  test chips peripherals  |
+0x2c002000 |--------------------------|             ------------
+           |     Private Address      |            Device Memory
+0x2c000000 |--------------------------|             ------------
+           |      Daughterboard       |                Fault
+           |  test chips peripherals  |
+0x20000000 |--------------------------|             ------------
+           |       Peripherals        |           Device Memory RW/RO
+           |                          |              & Fault
+0x00000000 |--------------------------|
+*/
+
+// L1 Cache info and restrictions about architecture of the caches (CCSIR register):
+// Write-Through support *not* available
+// Write-Back support available.
+// Read allocation support available.
+// Write allocation support available.
+
+//Note: You should use the Shareable attribute carefully.
+//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings.
+//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
+//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
+
+//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
+//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
+//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
+
+
+//Following MMU configuration is expected
+//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
+//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
+//Domain 0 is always the Client domain
+//Descriptors should place all memory in domain 0
+
+#include "ARMCA7.h"
+
+
+// L2 table pointers
+//----------------------------------------
+#define PRIVATE_TABLE_L2_BASE_4k       (0x80504000) //Map 4k Private Address space
+#define SYNC_FLAGS_TABLE_L2_BASE_4k    (0x80504C00) //Map 4k Flag synchronization
+#define PERIPHERAL_A_TABLE_L2_BASE_64k (0x80504400) //Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF
+#define PERIPHERAL_B_TABLE_L2_BASE_64k (0x80504800) //Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF
+
+//--------------------- PERIPHERALS -------------------
+#define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M)
+#define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M)
+
+//--------------------- SYNC FLAGS --------------------
+#define FLAG_SYNC     0xFFFFF000
+#define F_SYNC_BASE   0xFFF00000  //1M aligned
+
+//Import symbols from linker
+extern uint32_t Image$$VECTORS$$Base;
+extern uint32_t Image$$RW_DATA$$Base;
+extern uint32_t Image$$ZI_DATA$$Base;
+extern uint32_t Image$$TTB$$ZI$$Base;
+
+static uint32_t Sect_Normal;     //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
+static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
+static uint32_t Sect_Normal_RO;  //as Sect_Normal_Cod, but not executable
+static uint32_t Sect_Normal_RW;  //as Sect_Normal_Cod, but writeable and not executable
+static uint32_t Sect_Device_RO;  //device, non-shareable, non-executable, ro, domain 0, base addr 0
+static uint32_t Sect_Device_RW;  //as Sect_Device_RO, but writeable
+
+/* Define global descriptors */
+static uint32_t Page_L1_4k  = 0x0;  //generic
+static uint32_t Page_L1_64k = 0x0;  //generic
+static uint32_t Page_4k_Device_RW;  //Shared device, not executable, rw, domain 0
+static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0
+
+void MMU_CreateTranslationTable(void)
+{
+    mmu_region_attributes_Type region;
+
+    //Create 4GB of faulting entries
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT);
+
+    /*
+     * Generate descriptors. Refer to core_ca.h to get information about attributes
+     *
+     */
+    //Create descriptors for Vectors, RO, RW, ZI sections
+    section_normal(Sect_Normal, region);
+    section_normal_cod(Sect_Normal_Cod, region);
+    section_normal_ro(Sect_Normal_RO, region);
+    section_normal_rw(Sect_Normal_RW, region);
+    //Create descriptors for peripherals
+    section_device_ro(Sect_Device_RO, region);
+    section_device_rw(Sect_Device_RW, region);
+    //Create descriptors for 64k pages
+    page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);
+    //Create descriptors for 4k pages
+    page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);
+
+
+    /*
+     *  Define MMU flat-map regions and attributes
+     *
+     */
+
+    //Define Image
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base, 1, Sect_Normal_Cod);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base, 1, Sect_Normal_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA$$Base, 1, Sect_Normal_RW);
+
+    //all DRAM executable, rw, cacheable - applications may choose to divide memory into ro executable
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$TTB$$ZI$$Base, 2043, Sect_Normal);
+
+    //--------------------- PERIPHERALS -------------------
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A7_MP_FLASH_BASE0    , 64, Sect_Device_RO);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A7_MP_FLASH_BASE1    , 64, Sect_Device_RO);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A7_MP_SRAM_BASE      , 64, Sect_Device_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A7_MP_VRAM_BASE      , 32, Sect_Device_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A7_MP_ETHERNET_BASE  , 16, Sect_Device_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A7_MP_USB_BASE       , 16, Sect_Device_RW);
+
+    // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C000000-0x1C00FFFF
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, PERIPHERAL_A_FAULT      , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
+    // Define peripheral range 0x1C000000-0x1C00FFFF
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A7_MP_DAP_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A7_MP_SYSTEM_REG_BASE,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A7_MP_SERIAL_BASE    ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A7_MP_AACI_BASE      ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A7_MP_MMCI_BASE      ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A7_MP_KMI0_BASE      ,  2, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A7_MP_UART_BASE      ,  4, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A7_MP_WDT_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+
+    // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C100000-0x1C10FFFF
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, PERIPHERAL_B_FAULT      , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
+    // Define peripheral range 0x1C100000-0x1C10FFFF
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A7_MP_TIMER_BASE     ,  2, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A7_MP_DVI_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A7_MP_RTC_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A7_MP_UART4_BASE     ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+    MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A7_MP_CLCD_BASE      ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+
+    // Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory
+    MMU_TTPage4k (&Image$$TTB$$ZI$$Base, __get_CBAR()            ,256,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
+    // Define private address space entry.
+    MMU_TTPage4k (&Image$$TTB$$ZI$$Base, __get_CBAR()            ,  3,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+    // Define L2CC entry.  Uncomment if PL310 is present
+    //    MMU_TTPage4k (&Image$$TTB$$ZI$$Base, VE_A7_MP_PL310_BASE     ,  1,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+
+    // Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC)
+    MMU_TTPage4k (&Image$$TTB$$ZI$$Base, F_SYNC_BASE , 256, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
+    // Define synchronization space entry.
+    MMU_TTPage4k (&Image$$TTB$$ZI$$Base, FLAG_SYNC   ,   1, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+
+    /* Set location of level 1 page table
+    ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
+    ; 13:7  - 0x0
+    ; 6     - IRGN[0] 0x0 (Inner WB WA)
+    ; 5     - NOS     0x0 (Non-shared)
+    ; 4:3   - RGN     0x1 (Outer WB WA)
+    ; 2     - IMP     0x0 (Implementation Defined)
+    ; 1     - S       0x0 (Non-shared)
+    ; 0     - IRGN[1] 0x1 (Inner WB WA) */
+    __set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 9);
+    __ISB();
+
+    /* Set up domain access control register
+    ; We set domain 0 to Client and all other domains to No Access.
+    ; All translation table entries specify domain 0 */
+    __set_DACR(1);
+    __ISB();
+}

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/GCC/RTE/Device/ARMCA7/startup_ARMCA7.c

@@ -0,0 +1,138 @@
+/******************************************************************************
+ * @file     startup_ARMCA7.c
+ * @brief    CMSIS Device System Source File for ARM Cortex-A9 Device Series
+ * @version  V1.00
+ * @date     22 Feb 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <ARMCA7.h>
+
+/*----------------------------------------------------------------------------
+  Definitions
+ *----------------------------------------------------------------------------*/
+#define USR_MODE 0x10            // User mode
+#define FIQ_MODE 0x11            // Fast Interrupt Request mode
+#define IRQ_MODE 0x12            // Interrupt Request mode
+#define SVC_MODE 0x13            // Supervisor mode
+#define ABT_MODE 0x17            // Abort mode
+#define UND_MODE 0x1B            // Undefined Instruction mode
+#define SYS_MODE 0x1F            // System mode
+
+/*----------------------------------------------------------------------------
+  Internal References
+ *----------------------------------------------------------------------------*/
+void Vectors       (void) __attribute__ ((naked, section("RESET")));
+void Reset_Handler (void) __attribute__ ((naked));
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void PAbt_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void DAbt_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void IRQ_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void FIQ_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+void Vectors(void) {
+  __ASM volatile(
+  "LDR    PC, =Reset_Handler                        \n"
+  "LDR    PC, =Undef_Handler                        \n"
+  "LDR    PC, =SVC_Handler                          \n"
+  "LDR    PC, =PAbt_Handler                         \n"
+  "LDR    PC, =DAbt_Handler                         \n"
+  "NOP                                              \n"
+  "LDR    PC, =IRQ_Handler                          \n"
+  "LDR    PC, =FIQ_Handler                          \n"
+  );
+}
+
+/*----------------------------------------------------------------------------
+  Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+  __ASM volatile(
+
+  // Mask interrupts
+  "CPSID   if                                      \n"
+
+  // Put any cores other than 0 to sleep
+  "MRC     p15, 0, R0, c0, c0, 5                   \n"  // Read MPIDR
+  "ANDS    R0, R0, #3                              \n"
+  "goToSleep:                                      \n"
+  "WFINE                                           \n"
+  "BNE     goToSleep                               \n"
+
+  // Reset SCTLR Settings
+  "MRC     p15, 0, R0, c1, c0, 0                   \n"  // Read CP15 System Control register
+  "BIC     R0, R0, #(0x1 << 12)                    \n"  // Clear I bit 12 to disable I Cache
+  "BIC     R0, R0, #(0x1 <<  2)                    \n"  // Clear C bit  2 to disable D Cache
+  "BIC     R0, R0, #0x1                            \n"  // Clear M bit  0 to disable MMU
+  "BIC     R0, R0, #(0x1 << 11)                    \n"  // Clear Z bit 11 to disable branch prediction
+  "BIC     R0, R0, #(0x1 << 13)                    \n"  // Clear V bit 13 to disable hivecs
+  "MCR     p15, 0, R0, c1, c0, 0                   \n"  // Write value back to CP15 System Control register
+  "ISB                                             \n"
+
+  // Configure ACTLR
+  "MRC     p15, 0, r0, c1, c0, 1                   \n"  // Read CP15 Auxiliary Control Register
+  "ORR     r0, r0, #(1 <<  1)                      \n"  // Enable L2 prefetch hint (UNK/WI since r4p1)
+  "MCR     p15, 0, r0, c1, c0, 1                   \n"  // Write CP15 Auxiliary Control Register
+
+  // Set Vector Base Address Register (VBAR) to point to this application's vector table
+  "LDR    R0, =Vectors                             \n"
+  "MCR    p15, 0, R0, c12, c0, 0                   \n"
+
+  // Setup Stack for each exceptional mode
+  "CPS    #0x11                                    \n"
+  "LDR    SP, =Image$$FIQ_STACK$$ZI$$Limit         \n"
+  "CPS    #0x12                                    \n"
+  "LDR    SP, =Image$$IRQ_STACK$$ZI$$Limit         \n"
+  "CPS    #0x13                                    \n"
+  "LDR    SP, =Image$$SVC_STACK$$ZI$$Limit         \n"
+  "CPS    #0x17                                    \n"
+  "LDR    SP, =Image$$ABT_STACK$$ZI$$Limit         \n"
+  "CPS    #0x1B                                    \n"
+  "LDR    SP, =Image$$UND_STACK$$ZI$$Limit         \n"
+  "CPS    #0x1F                                    \n"
+  "LDR    SP, =Image$$SYS_STACK$$ZI$$Limit         \n"
+
+  // Call SystemInit
+  "BL     SystemInit                               \n"
+
+  // Unmask interrupts
+  "CPSIE  if                                       \n"
+
+  // Call __main
+  "BL     _start                                   \n"
+  );
+}
+
+/*----------------------------------------------------------------------------
+  Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+  while(1);
+}

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/GCC/RTE/Device/ARMCA7/system_ARMCA7.c

@@ -0,0 +1,93 @@
+/******************************************************************************
+ * @file     system_ARMCA7.c
+ * @brief    CMSIS Device System Source File for ARM Cortex-A7 Device Series
+ * @version  V1.00
+ * @date     22 Feb 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+#include "irq_ctrl.h"
+
+#define  SYSTEM_CLOCK  12000000U
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  System Initialization
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+/* do not use global variables because this function is called before
+   reaching pre-main. RW section may be overwritten afterwards.          */
+
+  // Invalidate entire Unified TLB
+  __set_TLBIALL(0);
+
+  // Invalidate entire branch predictor array
+  __set_BPIALL(0);
+  __DSB();
+  __ISB();
+
+  //  Invalidate instruction cache and flush branch target cache
+  __set_ICIALLU(0);
+  __DSB();
+  __ISB();
+
+  //  Invalidate data cache
+  L1C_InvalidateDCacheAll();
+
+  // Create Translation Table
+  MMU_CreateTranslationTable();
+
+  // Enable MMU
+  MMU_Enable();
+
+  // Enable Caches
+  L1C_EnableCaches();
+  L1C_EnableBTAC();
+
+#if (__L2C_PRESENT == 1) 
+  // Enable GIC
+  L2C_Enable();
+#endif
+
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+  // Enable FPU
+  __FPU_Enable();
+#endif
+
+  // IRQ Initialize
+  IRQ_Initialize();
+}

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/GCC/RTE/Device/ARMCA7/system_ARMCA7.h

@@ -0,0 +1,65 @@
+/******************************************************************************
+ * @file     system_ARMCA7.h
+ * @brief    CMSIS Device System Header File for ARM Cortex-A Device Series
+ * @version  V1.00
+ * @date     22 Feb 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SYSTEM_ARMCA7_H
+#define __SYSTEM_ARMCA7_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+/**
+  \brief Setup the microcontroller system.
+
+   Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+  \brief  Update SystemCoreClock variable.
+
+   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/**
+  \brief  Create Translation Table.
+
+   Creates Memory Management Unit Translation Table.
+ */
+extern void MMU_CreateTranslationTable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_ARMCA7_H */

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/GCC/RTE/RTE_Components.h

@@ -0,0 +1,19 @@
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: CMSIS_CV_CA7_GCC
+ * RTE configuration: CMSIS_CV_CA7_GCC.rteconfig
+*/
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+/*
+ * Define the Device Header File:
+*/
+#define CMSIS_device_header "ARMCA7.h"
+
+#define RTE_CV_COREFUNC                       /* CORE Validation - Core Function tests enabled */
+#define RTE_CV_COREINSTR                      /* CORE Validation - Core Instruction tests enabled */
+
+#endif /* RTE_COMPONENTS_H */

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A7/GCC/main.c

@@ -0,0 +1,40 @@
+/*----------------------------------------------------------------------------
+ * Name:    main.c
+ *----------------------------------------------------------------------------*/
+
+/* Includes ------------------------------------------------------------------*/
+
+#include <stdio.h>
+
+#include "RTE_Components.h"
+#include  CMSIS_device_header
+ 
+#ifdef RTE_Compiler_EventRecorder
+#include "EventRecorder.h"
+#endif
+
+#include "cmsis_cv.h"
+
+
+/* Private functions ---------------------------------------------------------*/
+int main (void);
+
+/**
+  * @brief  Main program
+  * @param  None
+  * @retval None
+  */
+int main (void) {
+
+  // System Initialization
+  SystemCoreClockUpdate();
+#ifdef RTE_Compiler_EventRecorder
+  // Initialize and start Event Recorder
+  (void)EventRecorderInitialize(EventRecordError, 1U);
+  (void)EventRecorderEnable    (EventRecordAll, 0xFEU, 0xFEU);
+#endif
+  
+  cmsis_cv();
+  
+  for(;;) {}
+}

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/.settings/language.settings.xml

@@ -1,25 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<project>
-	<configuration id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1261257010" name="Cortex-A9 (AC5)">
-		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
-			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
-			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
-			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
-			<provider class="com.arm.eclipse.builder.armcc.discovery.ArmCompiler6LanguageSettingsProvider" console="false" env-hash="668963287638" id="com.arm.eclipse.builder.armcc.v6.langprovider" keep-relative-paths="false" name="ARM Compiler 6 Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
-				<language-scope id="org.eclipse.cdt.core.gcc"/>
-				<language-scope id="org.eclipse.cdt.core.g++"/>
-			</provider>
-		</extension>
-	</configuration>
-	<configuration id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1021881951" name="Cortex-A9 (AC6)">
-		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
-			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
-			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
-			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
-			<provider class="com.arm.eclipse.builder.armcc.discovery.ArmCompiler6LanguageSettingsProvider" console="false" env-hash="308886176073646716" id="com.arm.eclipse.builder.armcc.v6.langprovider" keep-relative-paths="false" name="ARM Compiler 6 Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
-				<language-scope id="org.eclipse.cdt.core.gcc"/>
-				<language-scope id="org.eclipse.cdt.core.g++"/>
-			</provider>
-		</extension>
-	</configuration>
-</project>

CMSIS/CoreValidation/Examples/DS-MDK/Cortex-A9/AC5/.cproject

@@ -0,0 +1,149 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1261257010">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1261257010" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1261257010" name="Debug" parent="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6">
+					<folderInfo id="com.arm.eclipse.build.config.v6.exe.debug.base.var.arm_compiler_6-6.1968808959.1261257010." name="/" resourcePath="">
+						<toolChain id="com.arm.toolchain.baremetal.base.var.arm_compiler_5-5.1960502218" name="ARM Compiler 5" superClass="com.arm.toolchain.baremetal.base.var.arm_compiler_5-5">
+							<option id="com.arm.toolchain.ac5.option.target.cpu_fpu.1899004868" superClass="com.arm.toolchain.ac5.option.target.cpu_fpu" value="Cortex-A9.VFPv3_FP16.Neon" valueType="string"/>
+							<option id="com.arm.toolchain.ac5.option.fppcs.1215240395" name="Floating-point PCS" superClass="com.arm.toolchain.ac5.option.fppcs" value="com.arm.tool.c.compiler.option.fppcs.hard" valueType="enumerated"/>
+							<option id="com.arm.toolchain.ac5.option.inst.391027132" name="Instruction set" superClass="com.arm.toolchain.ac5.option.inst" value="com.arm.tool.c.compiler.option.inst.arm" valueType="enumerated"/>
+							<option id="com.arm.toolchain.ac5.options.libs.useMicroLib.1898820408" name="Use microlib" superClass="com.arm.toolchain.ac5.options.libs.useMicroLib" value="true" valueType="boolean"/>
+							<option id="com.arm.toolchain.ac5.option.endian.2047271088" name="Byte order" superClass="com.arm.toolchain.ac5.option.endian" value="com.arm.tool.c.compiler.v6.base.option.endian.little" valueType="enumerated"/>
+							<targetPlatform id="com.arm.toolchain.baremetal.base.var.arm_compiler_5-5.1960502218.788792350" name=""/>
+							<builder buildPath="${workspace_loc:/CMSIS_CV}/Debug" id="org.eclipse.cdt.build.core.internal.builder.1105228045" keepEnvironmentInBuildfile="false" name="CDT Internal Builder" superClass="org.eclipse.cdt.build.core.internal.builder"/>
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+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
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+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="CMSIS_CV.com.arm.eclipse.build.project.v6.exe.base.var.arm_compiler_6-6.420431336" name="Executable" projectType="com.arm.eclipse.build.project.v6.exe.base.var.arm_compiler_6-6"/>
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+	<storageModule moduleId="com.arm.cmsis.project">
+		<rteConfig name="CMSIS_CV_CA9_AC5.rteconfig"/>
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+			<file name="RTE/Device/ARMCA5/ARMCA5.sct" version="1.0.0"/>
+			<file name="RTE/CMSIS_CORE_Validation/CV_Config.h" version="1.0.0"/>
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+			<file name="RTE/Device/ARMCA9/startup_ARMCA9.c" version="1.0.0"/>
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+			<file name="RTE/Device/ARMCA9/mmu_ARMCA9.c" version="1.0.0"/>
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+	<storageModule moduleId="com.arm.projectSettings" version="5.25"/>
+	<storageModule moduleId="refreshScope" versionNumber="2">
+		<configuration configurationName="Debug">
+			<resource resourceType="PROJECT" workspacePath="/CMSIS_CV"/>
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+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+</cproject>