Updating company brand

- Converted ARM to Arm in all documentative text in source, header, and doxygen.
- Converted ARM to Arm in descriptive texts in pack description file.
  All identifier strings, like vendor, are kept unchanged due to compatibility reasons.
- Updated copyright year and file date.

CMSIS/Core/Include/cmsis_armcc.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     cmsis_armcc.h
- * @brief    CMSIS compiler ARMCC (ARM compiler V5) header file
- * @version  V5.0.3
- * @date     01. December 2017
+ * @brief    CMSIS compiler ARMCC (Arm Compiler 5) header file
+ * @version  V5.0.4
+ * @date     10. January 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -27,7 +27,7 @@
 
 
 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
-  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+  #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
 #endif
 
 /* CMSIS compiler control architecture macros */

CMSIS/Core/Include/cmsis_armclang.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     cmsis_armclang.h
- * @brief    CMSIS compiler ARMCLANG (ARM compiler V6) header file
- * @version  V5.0.3
- * @date     27. March 2017
+ * @brief    CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version  V5.0.4
+ * @date     10. January 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -30,7 +30,7 @@
 #pragma clang system_header   /* treat file as system include file */
 
 #ifndef __ARM_COMPAT_H
-#include <arm_compat.h>    /* Compatibility header for ARM Compiler 5 intrinsics */
+#include <arm_compat.h>    /* Compatibility header for Arm Compiler 5 intrinsics */
 #endif
 
 /* CMSIS compiler specific defines */

CMSIS/Core/Include/cmsis_compiler.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     cmsis_compiler.h
  * @brief    CMSIS compiler generic header file
- * @version  V5.0.3
- * @date     01. December 2017
+ * @version  V5.0.4
+ * @date     10. January 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -28,14 +28,14 @@
 #include <stdint.h>
 
 /*
- * ARM Compiler 4/5
+ * Arm Compiler 4/5
  */
 #if   defined ( __CC_ARM )
   #include "cmsis_armcc.h"
 
 
 /*
- * ARM Compiler 6 (armclang)
+ * Arm Compiler 6 (armclang)
  */
 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
   #include "cmsis_armclang.h"
@@ -56,7 +56,7 @@
 
 
 /*
- * TI ARM Compiler
+ * TI Arm Compiler
  */
 #elif defined ( __TI_ARM__ )
   #include <cmsis_ccs.h>

CMSIS/Core/Include/cmsis_iccarm.h

@@ -1,13 +1,13 @@
 /**************************************************************************//**
  * @file     cmsis_iccarm.h
- * @brief    CMSIS compiler ICCARM (IAR compiler) header file
- * @version  V5.0.4
- * @date     01. December 2017
+ * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version  V5.0.5
+ * @date     10. January 2018
  ******************************************************************************/
 
 //------------------------------------------------------------------------------
 //
-// Copyright (c) 2017 IAR Systems
+// Copyright (c) 2017-2018 IAR Systems
 //
 // Licensed under the Apache License, Version 2.0 (the "License")
 // you may not use this file except in compliance with the License.

CMSIS/Core/Include/core_armv8mbl.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     core_armv8mbl.h
- * @brief    CMSIS ARMv8MBL Core Peripheral Access Layer Header File
- * @version  V5.0.3
- * @date     09. August 2017
+ * @brief    CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File
+ * @version  V5.0.4
+ * @date     10. January 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -1239,8 +1239,8 @@ typedef struct
   #endif
   #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
 #else
-/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for ARMv8-M Baseline */
-/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for ARMv8-M Baseline */
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Armv8-M Baseline */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Armv8-M Baseline */
   #define NVIC_EnableIRQ              __NVIC_EnableIRQ
   #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
   #define NVIC_DisableIRQ             __NVIC_DisableIRQ
@@ -1266,7 +1266,7 @@ typedef struct
 #define NVIC_USER_IRQ_OFFSET          16
 
 
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
 /* The following MACROS handle generation of the register offset and byte masks */
 #define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
 #define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )

CMSIS/Core/Include/core_armv8mml.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     core_armv8mml.h
- * @brief    CMSIS ARMv8MML Core Peripheral Access Layer Header File
- * @version  V5.0.3
- * @date     09. August 2017
+ * @brief    CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File
+ * @version  V5.0.4
+ * @date     10. January 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -62,7 +62,7 @@
 
 #include "cmsis_version.h"
  
-/*  CMSIS ARMv8MML definitions */
+/*  CMSIS Armv8MML definitions */
 #define __ARMv8MML_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
 #define __ARMv8MML_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
 #define __ARMv8MML_CMSIS_VERSION       ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \

CMSIS/Core/Include/core_cm0.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     core_cm0.h
  * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
- * @version  V5.0.2
- * @date     19. April 2017
+ * @version  V5.0.3
+ * @date     10. January 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -599,7 +599,7 @@ typedef struct
 #define NVIC_USER_IRQ_OFFSET          16
 
 
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
 /* The following MACROS handle generation of the register offset and byte masks */
 #define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
 #define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )

CMSIS/Core/Include/core_cm0plus.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     core_cm0plus.h
  * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
- * @version  V5.0.3
- * @date     09. August 2017
+ * @version  V5.0.4
+ * @date     10. January 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -717,7 +717,7 @@ typedef struct
 #define NVIC_USER_IRQ_OFFSET          16
 
 
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
 /* The following MACROS handle generation of the register offset and byte masks */
 #define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
 #define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )

CMSIS/Core/Include/core_cm23.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     core_cm23.h
  * @brief    CMSIS Cortex-M23 Core Peripheral Access Layer Header File
- * @version  V5.0.3
- * @date     09. August 2017
+ * @version  V5.0.4
+ * @date     10. January 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -1269,7 +1269,7 @@ typedef struct
 #define NVIC_USER_IRQ_OFFSET          16
 
 
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
 /* The following MACROS handle generation of the register offset and byte masks */
 #define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
 #define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )

CMSIS/Core/Include/core_sc000.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     core_sc000.h
  * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
- * @version  V5.0.2
- * @date     19. April 2017
+ * @version  V5.0.3
+ * @date     10. January 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -727,7 +727,7 @@ typedef struct
 #define NVIC_USER_IRQ_OFFSET          16
 
 
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
 /* The following MACROS handle generation of the register offset and byte masks */
 #define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
 #define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )

CMSIS/Core/Include/core_sc300.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     core_sc300.h
  * @brief    CMSIS SC300 Core Peripheral Access Layer Header File
- * @version  V5.0.2
- * @date     19. April 2017
+ * @version  V5.0.3
+ * @date     10. January 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *

CMSIS/Core/Include/mpu_armv7.h

@@ -1,11 +1,11 @@
 /******************************************************************************
  * @file     mpu_armv7.h
- * @brief    CMSIS MPU API for ARMv7 MPU
- * @version  V5.0.3
- * @date     09. August 2017
+ * @brief    CMSIS MPU API for Armv7-M MPU
+ * @version  V5.0.4
+ * @date     10. January 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *

CMSIS/Core/Include/mpu_armv8.h

@@ -1,11 +1,11 @@
 /******************************************************************************
  * @file     mpu_armv8.h
- * @brief    CMSIS MPU API for ARMv8 MPU
- * @version  V5.0.3
- * @date     09. August 2017
+ * @brief    CMSIS MPU API for Armv8-M MPU
+ * @version  V5.0.4
+ * @date     10. January 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *

CMSIS/Core/Include/tz_context.h

@@ -1,5 +1,11 @@
+/******************************************************************************
+ * @file     tz_context.h
+ * @brief    Context Management for Armv8-M TrustZone
+ * @version  V1.0.1
+ * @date     10. January 2018
+ ******************************************************************************/
 /*
- * Copyright (c) 2015-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -14,18 +20,7 @@
  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  * See the License for the specific language governing permissions and
  * limitations under the License.
- *
- * ----------------------------------------------------------------------------
- *
- * $Date:        21. September 2016
- * $Revision:    V1.0
- *
- * Project:      TrustZone for ARMv8-M
- * Title:        Context Management for ARMv8-M TrustZone
- *
- * Version 1.0
- *    Initial Release
- *---------------------------------------------------------------------------*/
+ */
 
 #if   defined ( __ICCARM__ )
   #pragma system_include         /* treat file as system include file for MISRA check */

CMSIS/Core/Template/ARMv8-M/main_s.c

@@ -1,5 +1,11 @@
+/******************************************************************************
+ * @file     main_s.c
+ * @brief    Code template for secure main function
+ * @version  V1.1.1
+ * @date     10. January 2018
+ ******************************************************************************/
 /*
- * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -14,17 +20,8 @@
  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  * See the License for the specific language governing permissions and
  * limitations under the License.
- *
- * ----------------------------------------------------------------------
- *
- * $Date:        15. October 2016
- * $Revision:    1.1.0
- *
- * Project:      TrustZone for ARMv8-M
- * Title:        Code template for secure main function
- *
- *---------------------------------------------------------------------------*/
- 
+ */
+
 /* Use CMSE intrinsics */
 #include <arm_cmse.h>
  

CMSIS/Core/Template/ARMv8-M/tz_context.c

@@ -1,5 +1,11 @@
+/******************************************************************************
+ * @file     tz_context.c
+ * @brief    Context Management for Armv8-M TrustZone - Sample implementation
+ * @version  V1.1.1
+ * @date     10. January 2018
+ ******************************************************************************/
 /*
- * Copyright (c) 2015-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2016-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -14,17 +20,8 @@
  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  * See the License for the specific language governing permissions and
  * limitations under the License.
- *
- * ----------------------------------------------------------------------------
- *
- * $Date:        15. October 2016
- * $Revision:    1.1.0
- *
- * Project:      TrustZone for ARMv8-M
- * Title:        Context Management for ARMv8-M TrustZone - Sample implementation
- *
- *---------------------------------------------------------------------------*/
- 
+ */
+
 #include "RTE_Components.h"
 #include CMSIS_device_header
 #include "tz_context.h"

CMSIS/Core_A/Include/cmsis_armcc.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     cmsis_armcc.h
  * @brief    CMSIS compiler specific macros, functions, instructions
- * @version  V1.0.1
- * @date     07. Sep 2017
+ * @version  V1.0.2
+ * @date     10. January 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -26,7 +26,7 @@
 #define __CMSIS_ARMCC_H
 
 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
-  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+  #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
 #endif
 
 /* CMSIS compiler control architecture macros */

CMSIS/Core_A/Include/cmsis_armclang.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     cmsis_armclang.h
  * @brief    CMSIS compiler specific macros, functions, instructions
- * @version  V1.0.1
- * @date     07. Sep 2017
+ * @version  V1.0.2
+ * @date     10. January 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -28,7 +28,7 @@
 #pragma clang system_header   /* treat file as system include file */
 
 #ifndef __ARM_COMPAT_H
-#include <arm_compat.h>    /* Compatibility header for ARM Compiler 5 intrinsics */
+#include <arm_compat.h>    /* Compatibility header for Arm Compiler 5 intrinsics */
 #endif
 
 /* CMSIS compiler specific defines */

CMSIS/Core_A/Include/cmsis_compiler.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     cmsis_compiler.h
  * @brief    CMSIS compiler specific macros, functions, instructions
- * @version  V1.0.1
- * @date     01. December 2017
+ * @version  V1.0.2
+ * @date     10. January 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -28,14 +28,14 @@
 #include <stdint.h>
 
 /*
- * ARM Compiler 4/5
+ * Arm Compiler 4/5
  */
 #if   defined ( __CC_ARM )
   #include "cmsis_armcc.h"
 
 
 /*
- * ARM Compiler 6 (armclang)
+ * Arm Compiler 6 (armclang)
  */
 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
   #include "cmsis_armclang.h"
@@ -56,7 +56,7 @@
 
 
 /*
- * TI ARM Compiler
+ * TI Arm Compiler
  */
 #elif defined ( __TI_ARM__ )
   #include <cmsis_ccs.h>

CMSIS/Core_A/Include/cmsis_iccarm.h

@@ -1,13 +1,13 @@
 /**************************************************************************//**
  * @file     cmsis_iccarm.h
- * @brief    CMSIS compiler ICCARM (IAR compiler) header file
- * @version  V5.0.4
- * @date     01. December 2017
+ * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version  V5.0.5
+ * @date     10. January 2018
  ******************************************************************************/
 
 //------------------------------------------------------------------------------
 //
-// Copyright (c) 2017 IAR Systems
+// Copyright (c) 2017-2018 IAR Systems
 //
 // Licensed under the Apache License, Version 2.0 (the "License")
 // you may not use this file except in compliance with the License.

CMSIS/DSP/Include/arm_math.h

@@ -1,15 +1,11 @@
-/* ----------------------------------------------------------------------
- * Project:      CMSIS DSP Library
- * Title:        arm_math.h
- * Description:  Public header file for CMSIS DSP Library
- *
- * $Date:        19. September 2017
- * $Revision:    V.1.5.2
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
+/******************************************************************************
+ * @file     arm_math.h
+ * @brief    Public header file for CMSIS DSP LibraryU
+ * @version  V1.5.3
+ * @date     10. January 2018
+ ******************************************************************************/
 /*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ * Copyright (c) 2010-2018 Arm Limited or its affiliates. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -68,19 +64,19 @@
    * - arm_cortexM3b_math.lib (Cortex-M3, Big endian)
    * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian)
    * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian)
-   * - arm_ARMv8MBLl_math.lib (ARMv8M Baseline, Little endian)
-   * - arm_ARMv8MMLl_math.lib (ARMv8M Mainline, Little endian)
-   * - arm_ARMv8MMLlfsp_math.lib (ARMv8M Mainline, Little endian, Single Precision Floating Point Unit)
-   * - arm_ARMv8MMLld_math.lib (ARMv8M Mainline, Little endian, DSP instructions)
-   * - arm_ARMv8MMLldfsp_math.lib (ARMv8M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit)
+   * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian)
+   * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian)
+   * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit)
+   * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions)
+   * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit)
    *
    * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
    * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
    * public header file <code> arm_math.h</code> for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
-   * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or  ARM_MATH_CM3 or
+   * Define the appropriate preprocessor macro ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or
    * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
-   * For ARMv8M cores define pre processor MACRO ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML.
-   * Set Pre processor MACRO __DSP_PRESENT if ARMv8M Mainline core supports DSP instructions.
+   * For Armv8-M cores define preprocessor macro ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML.
+   * Set preprocessor macro __DSP_PRESENT if Armv8-M Mainline core supports DSP instructions.
    * 
    *
    * Examples
@@ -91,22 +87,22 @@
    * Toolchain Support
    * ------------
    *
-   * The library has been developed and tested with MDK-ARM version 5.14.0.0
+   * The library has been developed and tested with MDK version 5.14.0.0
    * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
    *
    * Building the Library
    * ------------
    *
-   * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
+   * The library installer contains a project file to rebuild libraries on MDK toolchain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
    * - arm_cortexM_math.uvprojx
    *
    *
-   * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.
+   * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above.
    *
-   * Pre-processor Macros
+   * Preprocessor Macros
    * ------------
    *
-   * Each library project have differant pre-processor macros.
+   * Each library project have different preprocessor macros.
    *
    * - UNALIGNED_SUPPORT_DISABLE:
    *
@@ -132,8 +128,8 @@
    *
    * - ARM_MATH_ARMV8MxL:
    *
-   * Define macro ARM_MATH_ARMV8MBL for building the library on ARMv8M Baseline target, ARM_MATH_ARMV8MML for building library
-   * on ARMv8M Mainline target.
+   * Define macro ARM_MATH_ARMV8MBL for building the library on Armv8-M Baseline target, ARM_MATH_ARMV8MML for building library
+   * on Armv8-M Mainline target.
    *
    * - __FPU_PRESENT:
    *
@@ -141,7 +137,7 @@
    *
    * - __DSP_PRESENT:
    *
-   * Initialize macro __DSP_PRESENT = 1 when ARMv8M Mainline core supports DSP instructions.
+   * Initialize macro __DSP_PRESENT = 1 when Armv8-M Mainline core supports DSP instructions.
    *
    * <hr>
    * CMSIS-DSP in ARM::CMSIS Pack
@@ -163,7 +159,7 @@
    * Copyright Notice
    * ------------
    *
-   * Copyright (C) 2010-2015 ARM Limited. All rights reserved.
+   * Copyright (C) 2010-2015 Arm Limited. All rights reserved.
    */
 
 
@@ -243,9 +239,9 @@
  *
  * \par Size Checking
  * By default all of the matrix functions perform size checking on the input and
- * output matrices.  For example, the matrix addition function verifies that the
+ * output matrices. For example, the matrix addition function verifies that the
  * two input matrices and the output matrix all have the same number of rows and
- * columns.  If the size check fails the functions return:
+ * columns. If the size check fails the functions return:
  * <pre>
  *     ARM_MATH_SIZE_MISMATCH
  * </pre>
@@ -259,9 +255,9 @@
  *     ARM_MATH_MATRIX_CHECK
  * </pre>
  * within the library project settings.  By default this macro is defined
- * and size checking is enabled.  By changing the project settings and
+ * and size checking is enabled. By changing the project settings and
  * undefining this macro size checking is eliminated and the functions
- * run a bit faster.  With size checking disabled the functions always
+ * run a bit faster. With size checking disabled the functions always
  * return <code>ARM_MATH_SUCCESS</code>.
  */
 

CMSIS/DoxyGen/Core/src/Overview.txt

@@ -12,8 +12,8 @@ In detail it defines:
 
 The following sections provide details about the CMSIS-Core (Cortex-M):
  - \ref using_pg describes the project setup and shows a simple program example.
- - \ref using_TrustZone_pg "Using TrustZone® for ARMv8-M" describes how to use the security extensions available in the ARMv8-M architecture.
- - \ref templates_pg describes the files of the CMSIS-Core (Cortex-M) in detail and explains how to adapt template files provided by ARM to silicon vendor devices.
+ - \ref using_TrustZone_pg "Using TrustZone® for Armv8-M" describes how to use the security extensions available in the Armv8-M architecture.
+ - \ref templates_pg describes the files of the CMSIS-Core (Cortex-M) in detail and explains how to adapt template files provided by Arm to silicon vendor devices.
  - \ref coreMISRA_Exceptions_pg describes the violations to the MISRA standard.
  - <a href="Modules.html">\b Reference </a> describe the features and functions of the \ref device_h_pg in detail.
  - <a href="Annotated.html">\b Data \b Structures </a> describe the data structures of the \ref device_h_pg in detail.
@@ -28,7 +28,7 @@ Files relevant to CMSIS-Core (Cortex-M) are present in the following <b>ARM::CMS
 |------------------------------|------------------------------------------------------------------------|
 |\b CMSIS\\Documentation\\Core | This documentation                                                     |
 |\b CMSIS\\Core\\Include       | CMSIS-Core (Cortex-M) header files (for example core_cm3.h, core_cmInstr.h, etc.) |
-|\b Device                     | \ref using_ARM_pg "ARM reference implementations" of Cortex-M devices  |
+|\b Device                     | \ref using_ARM_pg "Arm reference implementations" of Cortex-M devices  |
 |\b Device\\\_Template_Vendor  | \ref templates_pg for extension by silicon vendors                     |
 
 <hr>
@@ -36,39 +36,39 @@ Files relevant to CMSIS-Core (Cortex-M) are present in the following <b>ARM::CMS
 \section ref_v6-v8M Processor Support
 
 CMSIS supports the complete range of <a href="http://www.arm.com/products/processors/cortex-m/index.php" target="_blank"><b>Cortex-M processors</b></a> (with exception of Cortex-M1) and
-the <a href="http://www.arm.com/products/processors/instruction-set-architectures/armv8-m-architecture.php" target="_blank"><b>ARMv8-M architecture</b></a> including security extensions.
+the <a href="http://www.arm.com/products/processors/instruction-set-architectures/armv8-m-architecture.php" target="_blank"><b>Armv8-M architecture</b></a> including security extensions.
 
 \subsection ref_man_sec Cortex-M Reference Manuals
 
 The Cortex-M Device Generic User Guides contain the programmers model and detailed information about the core peripherals and are available for:
 
-- <a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0497a/DUI0497A_cortex_m0_r0p0_generic_ug.pdf" target="_blank"><b>Cortex-M0 Devices Generic User Guide</b></a> (ARMv6-M architecture)
-- <a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0662b/DUI0662B_cortex_m0p_r0p1_dgug.pdf" target="_blank"><b>Cortex-M0+ Devices Generic User Guide</b></a> (ARMv6-M architecture)
-- <a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/DUI0552A_cortex_m3_dgug.pdf" target="_blank"><b>Cortex-M3 Devices Generic User Guide</b></a> (ARMv7-M architecture)
+- <a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0497a/DUI0497A_cortex_m0_r0p0_generic_ug.pdf" target="_blank"><b>Cortex-M0 Devices Generic User Guide</b></a> (Armv6-M architecture)
+- <a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0662b/DUI0662B_cortex_m0p_r0p1_dgug.pdf" target="_blank"><b>Cortex-M0+ Devices Generic User Guide</b></a> (Armv6-M architecture)
+- <a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/DUI0552A_cortex_m3_dgug.pdf" target="_blank"><b>Cortex-M3 Devices Generic User Guide</b></a> (Armv7-M architecture)
 - <a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/DUI0553A_cortex_m4_dgug.pdf" target="_blank"><b>Cortex-M4 Devices Generic User Guide</b></a> (ARMv7-M architecture)
-- <a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0646a/DUI0646A_cortex_m7_dgug.pdf" target="_blank"><b>Cortex-M7 Devices Generic User Guide</b></a> (ARMv7-M architecture)
+- <a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0646a/DUI0646A_cortex_m7_dgug.pdf" target="_blank"><b>Cortex-M7 Devices Generic User Guide</b></a> (Armv7-M architecture)
 
 The \b Cortex-M23 and \b Cortex-M33 are described with Technical Reference Manuals that are available here:
-- <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0550c/cortex_m23_r1p0_technical_reference_manual_DDI0550C_en.pdf" target="_blank"><b>Cortex-M23 Technical Reference Manual</b></a> (ARMv8-M baseline architecture)
-- <a href="http://infocenter.arm.com/help/topic/com.arm.doc.100230_0002_00_en/cortex_m33_trm_100230_0002_00_en.pdf" target="_blank"><b>Cortex-M33 Technical Reference Manual</b></a> (ARMv8-M mainline architecture)
+- <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0550c/cortex_m23_r1p0_technical_reference_manual_DDI0550C_en.pdf" target="_blank"><b>Cortex-M23 Technical Reference Manual</b></a> (Armv8-M baseline architecture)
+- <a href="http://infocenter.arm.com/help/topic/com.arm.doc.100230_0002_00_en/cortex_m33_trm_100230_0002_00_en.pdf" target="_blank"><b>Cortex-M33 Technical Reference Manual</b></a> (Armv8-M mainline architecture)
 
-\subsection ARMv8M ARMv8-M Architecture
+\subsection ARMv8M Armv8-M Architecture
 
-ARMv8-M introduces two profiles \b baseline (for power and area constrained applications) and \b mainline (full-featured with optional SIMD, floating-point, and co-processor extensions).
-Both ARMv8-M profiles are supported by CMSIS.
+Armv8-M introduces two profiles \b baseline (for power and area constrained applications) and \b mainline (full-featured with optional SIMD, floating-point, and co-processor extensions).
+Both Armv8-M profiles are supported by CMSIS.
 
-The ARMv8-M Architecture is described in the <a href="http://developer.arm.com/products/architecture/m-profile/docs/ddi0553/latest/armv8-m-architecture-reference-manual" target="_blank"><b>ARMv8-M Architecture Reference Manual</b></a>.
+The Armv8-M Architecture is described in the <a href="http://developer.arm.com/products/architecture/m-profile/docs/ddi0553/latest/armv8-m-architecture-reference-manual" target="_blank"><b>Armv8-M Architecture Reference Manual</b></a>.
 
 <hr>
 
 \section tested_tools_sec Tested and Verified Toolchains
 
-The \ref templates_pg supplied by ARM have been tested and verified with the following toolchains:
- - ARM: ARM Compiler 5.06 update 6 (not for Cortex-M23, Cortex-M33, ARMv8-M)
- - ARM: ARM Compiler 6.9
- - ARM: ARM Compiler 6.6.2 (not for Cortex-M0, Cortex-M23, Cortex-M33, ARMv8-M)
- - GNU: GNU Tools for ARM Embedded 6.3.1 20170620
- - IAR: IAR ANSI C/C++ Compiler for ARM 8.20.1.14183
+The \ref templates_pg supplied by Arm have been tested and verified with the following toolchains:
+ - Arm: Arm Compiler 5.06 update 6 (not for Cortex-M23, Cortex-M33, Armv8-M)
+ - Arm: Arm Compiler 6.9
+ - Arm: Arm Compiler 6.6.2 (not for Cortex-M0, Cortex-M23, Cortex-M33, Armv8-M)
+ - GNU: GNU Tools for Arm Embedded 6.3.1 20170620
+ - IAR: IAR ANSI C/C++ Compiler for Arm 8.20.1.14183
 
 <hr>
 */
@@ -173,7 +173,7 @@ The \ref templates_pg supplied by ARM have been tested and verified with the fol
          Corrected: DoxyGen function parameter comments.\n
          Corrected: IAR toolchain: removed for \ref NVIC_SystemReset the attribute(noreturn).\n
          Corrected: GCC toolchain: suppressed irrelevant compiler warnings.\n
-         Added: Support files for ARM Compiler v6 (cmsis_armcc_v6.h).
+         Added: Support files for Arm Compiler v6 (cmsis_armcc_v6.h).
       </td>
     </tr>
     <tr>

CMSIS/DoxyGen/Core/src/Ref_CompilerControl.txt

@@ -12,41 +12,41 @@ The header file <b>cmsis_compiler.h</b> is also included by each \ref device_h_p
 
 /**
 \def __ARM_ARCH_6M__
-\brief Set to 1 when generating code for ARMv6-M (Cortex-M0, Cortex-M1)
+\brief Set to 1 when generating code for Armv6-M (Cortex-M0, Cortex-M1)
 \details
-The <b>\#define __ARM_ARCH_6M__</b> is set to 1 when generating code for the ARMv6-M architecture. This architecture is for example used by the Cortex-M0, Cortex-M0+, and Cortex-M1 processor.
+The <b>\#define __ARM_ARCH_6M__</b> is set to 1 when generating code for the Armv6-M architecture. This architecture is for example used by the Cortex-M0, Cortex-M0+, and Cortex-M1 processor.
 */
 #define __ARM_ARCH_6M__
 
 /**
 \def __ARM_ARCH_7M__
-\brief Set to 1 when generating code for ARMv7-M (Cortex-M3)
+\brief Set to 1 when generating code for Armv7-M (Cortex-M3)
 \details
-The <b>\#define __ARM_ARCH_7M__</b> is set to 1 when generating code for the ARMv7-M architecture. This architecture is for example used by the Cortex-M3 processor.
+The <b>\#define __ARM_ARCH_7M__</b> is set to 1 when generating code for the Armv7-M architecture. This architecture is for example used by the Cortex-M3 processor.
 */
 #define __ARM_ARCH_7M__
 
 /**
 \def __ARM_ARCH_7EM__
-\brief Set to 1 when generating code for ARMv7-M (Cortex-M4) with FPU
+\brief Set to 1 when generating code for Armv7-M (Cortex-M4) with FPU
 \details
-The <b>\#define __ARM_ARCH_7EM__</b> is set to 1 when generating code for the ARMv7-M architecture with floating point extension. This architecture is for example used by the Cortex-M4 processor with FPU
+The <b>\#define __ARM_ARCH_7EM__</b> is set to 1 when generating code for the Armv7-M architecture with floating point extension. This architecture is for example used by the Cortex-M4 processor with FPU
 */
 #define __ARM_ARCH_7EM__
 
 /**
 \def __ARM_ARCH_8M_BASE__
-\brief Set to 1 when generating code for ARMv8-M Baseline
+\brief Set to 1 when generating code for Armv8-M Baseline
 \details
-The <b>\#define __ARM_ARCH_8M_BASE__</b> is set to 1 when generating code for the ARMv8-M architecture baseline variant.
+The <b>\#define __ARM_ARCH_8M_BASE__</b> is set to 1 when generating code for the Armv8-M architecture baseline variant.
 */
 #define __ARM_ARCH_8M_BASE__
 
 /**
 \def __ARM_ARCH_8M_MAIN__
-\brief Set to 1 when generating code for ARMv8-M Mainline
+\brief Set to 1 when generating code for Armv8-M Mainline
 \details
-The <b>\#define __ARM_ARCH_8M_MAIN__</b> is set to 1 when generating code for the ARMv8-M architecture mainline variant.
+The <b>\#define __ARM_ARCH_8M_MAIN__</b> is set to 1 when generating code for the Armv8-M architecture mainline variant.
 */
 #define __ARM_ARCH_8M_MAIN__
 
@@ -229,7 +229,7 @@ Do not use this macro.
 It has been superseded by \ref __UNALIGNED_UINT32_READ, \ref __UNALIGNED_UINT32_WRITE and will be removed in the future.
 \details
 Defines a pointer to a uint32_t from an address that does not need to be aligned. This can then be used in read/write
-operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying ARM
+operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm
 processor core and compiler settings.
  
 <b> Code Example:</b>
@@ -250,7 +250,7 @@ void test (uint8_t *ptr) {
 \brief Pointer for unaligned read of a uint16_t variable.
 \details
 Defines a pointer to a uint16_t from an address that does not need to be aligned. This can then be used in read
-operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying ARM
+operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm
 processor core and compiler settings.
  
 <b> Code Example:</b>
@@ -271,7 +271,7 @@ void test (uint8_t *ptr) {
 \brief Pointer for unaligned write of a uint16_t variable.
 \details
 Defines a pointer to a uint16_t from an address that does not need to be aligned. This can then be used in write
-operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying ARM
+operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm
 processor core and compiler settings.
  
 <b> Code Example:</b>
@@ -292,7 +292,7 @@ void test (uint8_t *ptr) {
 \brief Pointer for unaligned read of a uint32_t variable.
 \details
 Defines a pointer to a uint32_t from an address that does not need to be aligned. This can then be used in read
-operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying ARM
+operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm
 processor core and compiler settings.
  
 <b> Code Example:</b>
@@ -313,7 +313,7 @@ void test (uint8_t *ptr) {
 \brief Pointer for unaligned write of a uint32_t variable.
 \details
 Defines a pointer to a uint32_t from an address that does not need to be aligned. This can then be used in write
-operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying ARM
+operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm
 processor core and compiler settings.
  
 <b> Code Example:</b>

CMSIS/DoxyGen/Core/src/Ref_CoreReg.txt

@@ -684,49 +684,49 @@ void __disable_fault_irq(void);
 
 /**
   \brief   Get Process Stack Pointer Limit
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
   Stack Pointer Limit register hence zero is returned always in non-secure
   mode.
 
   \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
   \return               PSPLIM Register value
-  \note    Only availabe for ARMv8-M Architecture. 
+  \note    Only availabe for Armv8-M Architecture. 
  */
 uint32_t __get_PSPLIM(void);
 
 /**
   \brief   Set Process Stack Pointer Limit
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
   Stack Pointer Limit register hence the write is silently ignored in non-secure
   mode.
 
   \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
-  \note    Only availabe for ARMv8-M Architecture. 
+  \note    Only availabe for Armv8-M Architecture. 
  */
 void __set_PSPLIM(uint32_t ProcStackPtrLimit);
 
 /**
   \brief   Get Main Stack Pointer Limit
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
   Stack Pointer Limit register hence zero is returned always in non-secure
   mode.
 
   \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
   \return               MSPLIM Register value
-  \note    Only availabe for ARMv8-M Architecture. 
+  \note    Only availabe for Armv8-M Architecture. 
  */
 uint32_t __get_MSPLIM(void);
 
 /**
   \brief   Set Main Stack Pointer Limit
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
   Stack Pointer Limit register hence the write is silently ignored in non-secure
   mode.
 
   \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
   \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
-  \note    Only availabe for ARMv8-M Architecture. 
+  \note    Only availabe for Armv8-M Architecture. 
  */
 __set_MSPLIM(uint32_t MainStackPtrLimit);
 

CMSIS/DoxyGen/Core/src/Ref_FPU.txt

@@ -5,7 +5,7 @@
 Some Cortex-M processors include optional floating-point arithmetic functionality, with support
 for single and double-precision arithmetic.
 The Cortex-M processor with FPU is an implementation of the single-precision and
-double-precision variant of the ARMv7-M Architecture with Floating-Point Extension (FPv5).
+double-precision variant of the Armv7-M Architecture with Floating-Point Extension (FPv5).
 
 @{
 */

CMSIS/DoxyGen/Core/src/Ref_MPU.txt

@@ -1,5 +1,5 @@
 /**
-\defgroup mpu_functions  MPU Functions for ARMv7-M
+\defgroup mpu_functions  MPU Functions for Armv7-M
 \brief Functions that relate to the Memory Protection Unit.
 \details
 The following functions support the optional Memory Protection Unit (MPU) that is available on the Cortex-M0+, M3, M4 and M7 processor.
@@ -247,10 +247,10 @@ to determine if the processor implements an MPU.
 | Bits    | Name          | Function                                                      |
 | :------ | :------------ | :------------------------------------------------------------ |
 | [31:24] | -             | Reserved.                                                     |
-| [23:16] | IREGION       | Instruction region. RAZ. ARMv7-M only supports a unified MPU. |
+| [23:16] | IREGION       | Instruction region. RAZ. Armv7-M only supports a unified MPU. |
 | [15:8]  | DREGION       | Number of regions supported by the MPU. If this field reads-as-zero the processor does not implement an MPU. |
 | [7:1]   | -             | Reserved.                                                     |
-| [0]     | SEPARATE      | Indicates support for separate instruction and data address maps. RAZ. ARMv7-M only supports a unified MPU. |
+| [0]     | SEPARATE      | Indicates support for separate instruction and data address maps. RAZ. Armv7-M only supports a unified MPU. |
 
 \var MPU_Type::CTRL
 Enables the MPU, and when the MPU is enabled, controls whether the default memory map

CMSIS/DoxyGen/Core/src/Ref_NVIC.txt

@@ -5,7 +5,7 @@
 \details
 This section explains how to use interrupts and exceptions and access functions for the Nested Vector Interrupt Controller (NVIC).
 
-ARM provides a template file <strong>startup_<em>device</em></strong> for each supported
+Arm provides a template file <strong>startup_<em>device</em></strong> for each supported
 compiler. The file must be adapted by the silicon vendor to include interrupt vectors for all device-specific 
 interrupt handlers. Each interrupt handler is defined as a <strong><em>weak</em></strong> function 
 to an dummy handler. These interrupt handlers can be used directly in application software 
@@ -24,8 +24,8 @@ The table below lists the core exception vectors of the various Cortex-M process
       <th>M7</th>
       <th>SC000</th>
       <th>SC300</th>
-      <th>ARMv8-M<br/>Baseline</th>
-      <th>ARMv8-M<br/>Mainline</th>
+      <th>Armv8-M<br/>Baseline</th>
+      <th>Armv8-M<br/>Mainline</th>
       <th>Description</th>
     </tr>
     <tr>
@@ -179,7 +179,7 @@ program memory, however \ref using_VTOR_pg it can be relocated to RAM.  The symb
 <b>__Vectors</b> is the address of the vector table in the startup code and the
 register <b>SCB->VTOR</b> holds the start address of the vector table. 
 
-An ARMv8-M implementation with TrustZone provides two vector tables: 
+An Armv8-M implementation with TrustZone provides two vector tables: 
   - vector table for Secure handlers
   - vector table for Non-Secure handlers
 
@@ -189,7 +189,7 @@ Processor Exceptions
 --------------------
 At the beginning of the vector table, the initial stack value and the 
 exception vectors of the processor are defined. The vector table below 
-shows the exception vectors of a ARMv8-M Mainline processor. Other processor
+shows the exception vectors of a Armv8-M Mainline processor. Other processor
 variants may have fewer vectors.
 
 \code
@@ -390,7 +390,7 @@ typedef enum IRQn
   MemoryManagement_IRQn    = -12,      ///<  Exception 4: Memory Management Interrupt [not on Cortex-M0 variants]
   BusFault_IRQn            = -11,      ///<  Exception 5: Bus Fault Interrupt [not on Cortex-M0 variants]
   UsageFault_IRQn          = -10,      ///<  Exception 6: Usage Fault Interrupt [not on Cortex-M0 variants]
-  SecureFault_IRQn         = -9,       ///<  Exception 7: Secure Fault Interrupt [only on ARMv8-M]
+  SecureFault_IRQn         = -9,       ///<  Exception 7: Secure Fault Interrupt [only on Armv8-M]
   SVCall_IRQn              = -5,       ///<  Exception 11: SV Call Interrupt
   DebugMonitor_IRQn        = -4,       ///<  Exception 12: Debug Monitor Interrupt [not on Cortex-M0 variants]
   PendSV_IRQn              = -2,       ///<  Exception 14: Pend SV Interrupt [not on Cortex-M0 variants]
@@ -787,7 +787,7 @@ void NVIC_SystemReset (void);
         - 0  if interrupt is assigned to Secure
         - 1  if interrupt is assigned to Non Secure
     \remarks
-        - Only available for ARMv8-M in secure state.
+        - Only available for Armv8-M in secure state.
         
     \sa     
         - \ref NVIC_ClearTargetState; NVIC_SetTargetState;
@@ -802,7 +802,7 @@ uint32_t NVIC_GetTargetState(IRQn_Type IRQn);
         - 0  if interrupt is assigned to Secure
         - 1  if interrupt is assigned to Non Secure
     \remarks
-        - Only available for ARMv8-M in secure state.
+        - Only available for Armv8-M in secure state.
         
     \sa     
         - \ref NVIC_ClearTargetState; NVIC_GetTargetState;
@@ -817,7 +817,7 @@ uint32_t NVIC_SetTargetState(IRQn_Type IRQn);
         - 0  if interrupt is assigned to Secure
         - 1  if interrupt is assigned to Non Secure
     \remarks
-        - Only available for ARMv8-M in secure state.
+        - Only available for Armv8-M in secure state.
         
     \sa     
         - \ref NVIC_GetTargetState; NVIC_SetTargetState;

CMSIS/DoxyGen/Core/src/Ref_SystemAndClock.txt

@@ -4,7 +4,7 @@
 \defgroup   system_init_gr   System and Clock Configuration
 \brief Functions for system and clock setup available in system_<i>device</i>.c.
 \details
-ARM provides a template file <b>system_<i>device</i>.c</b> that must be adapted by 
+Arm provides a template file <b>system_<i>device</i>.c</b> that must be adapted by 
 the silicon vendor to match their actual device. As a <b>minimum requirement</b>, 
 this file must provide:
  -  A device-specific system configuration function, \ref SystemInit().

CMSIS/DoxyGen/Core/src/Ref_Trustzone.txt

@@ -1,10 +1,10 @@
 /**
-\defgroup trustzone_functions TrustZone for ARMv8-M
-\brief Functions that related to optional ARMv8-M security extension
+\defgroup trustzone_functions TrustZone for Armv8-M
+\brief Functions that related to optional Armv8-M security extension
   @{
 \details
-The ARMv8-M architecture has optional ARMv8-M security extension based on ARM TrustZone technology.
-To access ARM TrustZone extensions for ARMv8-M additional CMSIS functions are provided:
+The Armv8-M architecture has optional Armv8-M security extension based on Arm TrustZone technology.
+To access Arm TrustZone extensions for Armv8-M additional CMSIS functions are provided:
  - \ref coreregister_trustzone_functions
  - \ref nvic_trustzone_functions
  - \ref systick_trustzone_functions
@@ -14,7 +14,7 @@ To access ARM TrustZone extensions for ARMv8-M additional CMSIS functions are pr
 
 /**
   \defgroup coreregister_trustzone_functions Core Register Access Functions
-  \brief Core register Access functions related to TrustZone for ARMv8-M.
+  \brief Core register Access functions related to TrustZone for Armv8-M.
   @{
 */
 
@@ -142,7 +142,7 @@ void __TZ_set_FAULTMASK_NS(uint32_t faultMask);
 
 /**
   \brief   Get Process Stack Pointer Limit (non-secure)
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
   Stack Pointer Limit register hence zero is returned always.
 
   \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
@@ -152,7 +152,7 @@ uint32_t __TZ_get_PSPLIM_NS(void);
 
 /**
   \brief   Set Process Stack Pointer (non-secure)
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
   Stack Pointer Limit register hence zero is returned always.
 
   \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
@@ -162,7 +162,7 @@ void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit);
 
 /**
   \brief   Get Main Stack Pointer Limit (non-secure)
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
   Stack Pointer Limit register hence zero is returned always.
   
   \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
@@ -172,7 +172,7 @@ uint32_t __TZ_get_MSPLIM_NS(void);
 
 /**
   \brief   Set Main Stack Pointer Limit (non-secure)
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
   Stack Pointer Limit register hence zero is returned always.
 
   \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
@@ -186,7 +186,7 @@ void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit);
 
 /**
   \defgroup nvic_trustzone_functions NVIC Functions
-  \brief Nested Vector Interrupt Controller (NVIC) functions related to TrustZone for ARMv8-M 
+  \brief Nested Vector Interrupt Controller (NVIC) functions related to TrustZone for Armv8-M 
   @{
 */
 
@@ -198,7 +198,7 @@ void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit);
            In case of a conflict between priority grouping and available
            priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
   \param [in]      PriorityGroup  Priority grouping field.
-  \note    Only available for ARMv8-M Mainline. 
+  \note    Only available for Armv8-M Mainline. 
   \sa     
     - \ref NVIC_SetPriorityGrouping
  */
@@ -208,7 +208,7 @@ void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup);
   \brief   Get Priority Grouping (non-secure)
   \details Reads the priority grouping field from the non-secure NVIC when in secure state.
   \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
-  \note    Only available for ARMv8-M Mainline. 
+  \note    Only available for Armv8-M Mainline. 
   \sa     
     - \ref NVIC_GetPriorityGrouping
  */
@@ -314,7 +314,7 @@ uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn);
 
 /**
   \defgroup systick_trustzone_functions SysTick Functions
-  \brief SysTick functions related to TrustZone for ARMv8-M.
+  \brief SysTick functions related to TrustZone for Armv8-M.
   @{
 */
 
@@ -340,7 +340,7 @@ uint32_t TZ_SysTick_Config_NS(uint32_t ticks);
 
 /**
   \defgroup sau_trustzone_functions SAU Functions
-  \brief Secure Attribution Unit (SAU) functions related to TrustZone for ARMv8-M.
+  \brief Secure Attribution Unit (SAU) functions related to TrustZone for Armv8-M.
   @{
 \details
 The Secure Attribution Unit (SAU) functions SAU 
@@ -383,7 +383,7 @@ void TZ_SAU_Disable(void);
 
 /**
   \defgroup context_trustzone_functions RTOS Context Management
-  \brief RTOS Thread Context Management for ARMv8-M TrustZone.
+  \brief RTOS Thread Context Management for Armv8-M TrustZone.
   @{
   \details The CMSIS-Core provides the file <b>tz_context.h</b> which defines an API to standardize the context memory system for real-time operating systems. For more information refer to \ref RTOS_TrustZone.
 */

CMSIS/DoxyGen/Core/src/Ref_cmInstr.txt

@@ -7,9 +7,9 @@ The following functions generate specific Cortex-M instructions that cannot be d
 Refer to the \ref ref_man_sec for detailed information about these Cortex-M instructions.
 
 \note
-When using the ARM Compiler Toolchain the following \ref intrinsic_CPU_gr are implemented using the Embedded Assembler: \ref __RRX, <Bruno: add more...>.
+When using the Arm Compiler Toolchain the following \ref intrinsic_CPU_gr are implemented using the Embedded Assembler: \ref __RRX, <Bruno: add more...>.
 The usage of the Embedded Assembler can be disabled by with <b><i>define __NO_EMBEDDED_ASM</i></b>. This avoids potential side effects of the Embedded Assembler.
-Refer to <b>Compiler User Guide - Using the Inline and Embedded Assemblers of the ARM Compiler</b> for more information. 
+Refer to <b>Compiler User Guide - Using the Inline and Embedded Assemblers of the Arm Compiler</b> for more information. 
 
 */
 /**************************************************************************************************/
@@ -260,7 +260,7 @@ uint32_t __USAT(uint32_t value, uint32_t sat);
 
     This function counts the number of leading zeros of a data value.
     
-    On ARMv6-M (Cortex-M0, Cortex-M0+, and SC000) this function is not available as a core instruction
+    On Armv6-M (Cortex-M0, Cortex-M0+, and SC000) this function is not available as a core instruction
     instruction and thus __CLZ is implemented in software.
 
     \param [in]  value  Value to count the leading zeros
@@ -352,7 +352,7 @@ void __STRT(uint32_t value, uint32_t ptr);
   \details Executes a LDAB instruction for 8 bit value.
   \param [in]    ptr  Pointer to data
   \return             value of type uint8_t at (*ptr)
-  \note    Only availabe for ARMv8-M Architecture. 
+  \note    Only availabe for Armv8-M Architecture. 
  */
 uint8_t __LDAB(volatile uint8_t *ptr);
 
@@ -361,7 +361,7 @@ uint8_t __LDAB(volatile uint8_t *ptr);
   \details Executes a LDAH instruction for 16 bit values.
   \param [in]    ptr  Pointer to data
   \return        value of type uint16_t at (*ptr)
-  \note    Only availabe for ARMv8-M Architecture. 
+  \note    Only availabe for Armv8-M Architecture. 
  */
 uint16_t __LDAH(volatile uint16_t *ptr);
 
@@ -370,7 +370,7 @@ uint16_t __LDAH(volatile uint16_t *ptr);
   \details Executes a LDA instruction for 32 bit values.
   \param [in]    ptr  Pointer to data
   \return        value of type uint32_t at (*ptr)
-  \note    Only availabe for ARMv8-M Architecture. 
+  \note    Only availabe for Armv8-M Architecture. 
  */
 uint32_t __LDA(volatile uint32_t *ptr);
 
@@ -379,7 +379,7 @@ uint32_t __LDA(volatile uint32_t *ptr);
   \details Executes a STLB instruction for 8 bit values.
   \param [in]  value  Value to store
   \param [in]    ptr  Pointer to location
-  \note    Only availabe for ARMv8-M Architecture. 
+  \note    Only availabe for Armv8-M Architecture. 
  */
 void __STLB(uint8_t value, volatile uint8_t *ptr);
 
@@ -388,7 +388,7 @@ void __STLB(uint8_t value, volatile uint8_t *ptr);
   \details Executes a STLH instruction for 16 bit values.
   \param [in]  value  Value to store
   \param [in]    ptr  Pointer to location
-  \note    Only availabe for ARMv8-M Architecture. 
+  \note    Only availabe for Armv8-M Architecture. 
  */
 void __STLH(uint16_t value, volatile uint16_t *ptr);
 
@@ -397,7 +397,7 @@ void __STLH(uint16_t value, volatile uint16_t *ptr);
   \details Executes a STL instruction for 32 bit values.
   \param [in]  value  Value to store
   \param [in]    ptr  Pointer to location
-  \note    Only availabe for ARMv8-M Architecture. 
+  \note    Only availabe for Armv8-M Architecture. 
  */
 void __STL(uint32_t value, volatile uint32_t *ptr);
 
@@ -406,7 +406,7 @@ void __STL(uint32_t value, volatile uint32_t *ptr);
   \details Executes a LDAB exclusive instruction for 8 bit value.
   \param [in]    ptr  Pointer to data
   \return             value of type uint8_t at (*ptr)
-  \note    Only availabe for ARMv8-M Architecture. 
+  \note    Only availabe for Armv8-M Architecture. 
  */
 uint8_t __LDAEXB(volatile uint32_t *ptr);
 
@@ -415,7 +415,7 @@ uint8_t __LDAEXB(volatile uint32_t *ptr);
   \details Executes a LDAH exclusive instruction for 16 bit values.
   \param [in]    ptr  Pointer to data
   \return        value of type uint16_t at (*ptr)
-  \note    Only availabe for ARMv8-M Architecture. 
+  \note    Only availabe for Armv8-M Architecture. 
  */
 uint16_t __LDAEXH(volatile uint32_t *ptr);
 
@@ -424,7 +424,7 @@ uint16_t __LDAEXH(volatile uint32_t *ptr);
   \details Executes a LDA exclusive instruction for 32 bit values.
   \param [in]    ptr  Pointer to data
   \return        value of type uint32_t at (*ptr)
-  \note    Only availabe for ARMv8-M Architecture. 
+  \note    Only availabe for Armv8-M Architecture. 
  */
 uint32_t __LDAEX(volatile uint32_t *ptr);
 
@@ -435,7 +435,7 @@ uint32_t __LDAEX(volatile uint32_t *ptr);
   \param [in]    ptr  Pointer to location
   \return          0  Function succeeded
   \return          1  Function failed
-  \note    Only availabe for ARMv8-M Architecture. 
+  \note    Only availabe for Armv8-M Architecture. 
  */
 uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr);
 
@@ -446,7 +446,7 @@ uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr);
   \param [in]    ptr  Pointer to location
   \return          0  Function succeeded
   \return          1  Function failed
-  \note    Only availabe for ARMv8-M Architecture. 
+  \note    Only availabe for Armv8-M Architecture. 
  */
 uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr);
 
@@ -457,7 +457,7 @@ uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr);
   \param [in]    ptr  Pointer to location
   \return          0  Function succeeded
   \return          1  Function failed
-  \note    Only availabe for ARMv8-M Architecture. 
+  \note    Only availabe for Armv8-M Architecture. 
  */
 uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr);
 

CMSIS/DoxyGen/Core/src/Template.txt

@@ -3,7 +3,7 @@
 
 \details
 
-ARM supplies CMSIS-Core device template files for the all supported Cortex-M processors and various compiler vendors.
+Arm supplies CMSIS-Core device template files for the all supported Cortex-M processors and various compiler vendors.
 Refer to the list of \ref tested_tools_sec for compliance.
 
 
@@ -18,7 +18,7 @@ The detailed file structure of the CMSIS-Core device templates is shown in the f
 
 \section CMSIS_Processor_files CMSIS-Core Processor Files 
 
-The CMSIS-Core processor files provided by ARM are in the directory .\\CMSIS\\Core\\Include. These header files define all processor specific attributes do not need any modifications.
+The CMSIS-Core processor files provided by Arm are in the directory .\\CMSIS\\Core\\Include. These header files define all processor specific attributes do not need any modifications.
 The <b>core_&lt;cpu&gt;.h</b> defines the core peripherals and provides helper functions that access the core registers. One file is available for each supported Cortex-M processor:
 
 Header File      | Processor
@@ -32,8 +32,8 @@ core_cm23.h      | for the Cortex-M23 processor
 core_cm33.h      | for the Cortex-M33 processor
 core_sc000.h     | for the SecurCore SC000 processor
 core_sc300.h     | for the SecurCore SC300 processor
-core_armv8mbl.h  | for the ARMv8-M Baseline processor
-core_armv8mml.h  | for the ARMv8-M Mainline processor
+core_armv8mbl.h  | for the Armv8-M Baseline processor
+core_armv8mml.h  | for the Armv8-M Mainline processor
 
 \section device_examples Device Examples
 
@@ -59,13 +59,13 @@ ARM Cortex-M33     | ARMCM33_DSP_FP    | Cortex-M23 based device with SIMD, FPU,
 ARM Cortex-M33     | ARMCM33_DSP_FP_TZ | Cortex-M23 based device with TrustZone, SIMD, FPU
 ARM SC000          | ARM SC000         | SC000 based device
 ARM SC300          | ARM SC300         | SC300 based device
-ARMv8-M Baseline   | ARMv8MBL          | ARMv8-M Baseline based device with TrustZone
-ARMv8-M Mainline   | ARMv8MML          | ARMv8-M Mainline based device with TrustZone
-ARMv8-M Mainline   | ARMv8MML_DP       | ARMv8-M Mainline based device with TrustZone and double precision FPU 
-ARMv8-M Mainline   | ARMv8MML_SP       | ARMv8-M Mainline based device with TrustZone and single precision FPU 
-ARMv8-M Mainline   | ARMv8MML_DSP      | ARMv8-M Mainline based device with TrustZone and SIMD
-ARMv8-M Mainline   | ARMv8MML_DSP_DP   | ARMv8-M Mainline based device with TrustZone, SIMD, and double precision FPU 
-ARMv8-M Mainline   | ARMv8MML_DSP_SP   | ARMv8-M Mainline based device with TrustZone, SIMD, and single precision FPU 
+ARMv8-M Baseline   | ARMv8MBL          | Armv8-M Baseline based device with TrustZone
+ARMv8-M Mainline   | ARMv8MML          | Armv8-M Mainline based device with TrustZone
+ARMv8-M Mainline   | ARMv8MML_DP       | Armv8-M Mainline based device with TrustZone and double precision FPU 
+ARMv8-M Mainline   | ARMv8MML_SP       | Armv8-M Mainline based device with TrustZone and single precision FPU 
+ARMv8-M Mainline   | ARMv8MML_DSP      | Armv8-M Mainline based device with TrustZone and SIMD
+ARMv8-M Mainline   | ARMv8MML_DSP_DP   | Armv8-M Mainline based device with TrustZone, SIMD, and double precision FPU 
+ARMv8-M Mainline   | ARMv8MML_DSP_SP   | Armv8-M Mainline based device with TrustZone, SIMD, and single precision FPU 
 
 
 \section template_files_sec Template Files
@@ -83,11 +83,11 @@ Silicon vendors add to these template files the following information:
     </tr>
     <tr>
       <td>.\\Device\\\_Template_Vendor\\Vendor\\Device\\Source\\ARM\\startup_Device.s</td>
-      <td>Startup file template for ARM C/C++ Compiler.</td>
+      <td>Startup file template for Arm C/C++ Compiler.</td>
     </tr>
     <tr>
       <td>.\\Device\\\_Template_Vendor\\Vendor\\Device\\Source\\GCC\\startup_Device.s</td>
-      <td>Startup file template for GNU GCC ARM Embedded Compiler.</td>
+      <td>Startup file template for GNU GCC Arm Embedded Compiler.</td>
     </tr>
     <tr>
       <td>.\\Device\\\_Template_Vendor\\Vendor\\Device\\Source\\IAR\\startup_Device.s</td>
@@ -203,7 +203,7 @@ EINT0_IRQHandler
 
 \section startup_s_sec startup_Device.s Template File
 
-An ARM Compiler \ref startup_s_sec for an ARMv7-M processor like Cortex-M3 is shown below.
+An Arm Compiler \ref startup_s_sec for an Armv7-M processor like Cortex-M3 is shown below.
 The files for other compiler vendors differ slightly in the syntax, but not in the overall structure.
 
 \verbinclude "Source\ARM\startup_Device.s"
@@ -827,7 +827,7 @@ The \ref system_Device_h_sec which is provided as part of the CMSIS specificatio
 /**
 \page partition_h_pg System Partition Header File partition_<device>.h
 
-The \ref partition_h_pg contains the initial setup of the TrustZone hardware in an ARMv8-M system.
+The \ref partition_h_pg contains the initial setup of the TrustZone hardware in an Armv8-M system.
 The function \ref TZ_SAU_Setup is call from \ref SystemInit and uses the settings in this file to 
 initialize the Secure Attribute Unit (SAU) and define non-secure interrupts (register NVIC_INIT_ITNS).
 The following initializations are performed:

CMSIS/DoxyGen/Core/src/Using.txt

@@ -35,7 +35,7 @@ The CMSIS-Core (Cortex-M) are device specific. In addition, the \ref startup_s_p
 The various compiler vendor tool chains may provide folders that contain the CMSIS files for each supported device.
   
 
-For example, the following files are provided in MDK-ARM to support the STM32F10x Connectivity Line device variants:
+For example, the following files are provided in MDK to support the STM32F10x Connectivity Line device variants:
 
 <table class="cmtable">
     <tr>
@@ -61,14 +61,14 @@ For example, the following files are provided in MDK-ARM to support the STM32F10
 </table>
 
 
-\note The silicon vendors create these device-specific CMSIS-Core (Cortex-M) files based on \ref templates_pg provide by ARM.
+\note The silicon vendors create these device-specific CMSIS-Core (Cortex-M) files based on \ref templates_pg provide by Arm.
 
 Thereafter, the functions described under <a href="Modules.html">\b Reference </a> can be used in the application.
 
 \b Examples
  - \subpage using_CMSIS is a simple example that shows the usage of the CMSIS layer.
  - \subpage using_VTOR_pg shows how to remap the interrupt vector table.
- - \subpage using_ARM_pg explains how to use CMSIS-Core (Cortex-M) for ARM processors.
+ - \subpage using_ARM_pg explains how to use CMSIS-Core (Cortex-M) for Arm processors.
 
 
 \page using_CMSIS Basic CMSIS Example
@@ -184,11 +184,11 @@ int main (void) {
 }
 \endcode
     
-\page using_ARM_pg Using CMSIS with generic ARM Processors
+\page using_ARM_pg Using CMSIS with generic Arm Processors
 
-ARM provides CMSIS-Core (Cortex-M) files for the supported ARM Processors and for various compiler vendors. 
-These files can be used when standard ARM processors should be used in a project.
-The table below lists the folder and device names of the ARM processors.
+Arm provides CMSIS-Core (Cortex-M) files for the supported Arm Processors and for various compiler vendors. 
+These files can be used when standard Arm processors should be used in a project.
+The table below lists the folder and device names of the Arm processors.
   
 <table class="cmtable">
     <tr>

CMSIS/DoxyGen/Core/src/UsingTrustZone.txt

@@ -1,36 +1,36 @@
 /** 
-\page using_TrustZone_pg  Using TrustZone for ARMv8-M
+\page using_TrustZone_pg  Using TrustZone for Armv8-M
 
 
 \details 
-The optional ARMv8-M security extension is similar to ARM TrustZone technology used in Cortex-A processors, but is 
-optimized for ultra-low power embedded applications. TrustZone for ARMv8-M enables of multiple software security 
+The optional Armv8-M Security Extension is similar to Arm TrustZone technology used in Cortex-A processors, but is 
+optimized for ultra-low power embedded applications. TrustZone for Armv8-M enables of multiple software security 
 domains that restrict access to secure memory and I/O only for trusted software.
 
-TrustZone for ARMv8-M:
+TrustZone for Armv8-M:
   - preserves low interrupt latencies for both Secure and Non-secure domains.
   - does not impose code overhead, cycle overhead or the complexity of a virtualization based solution.
   - introduces the Secure Gateway (SG) processor instruction for calls to the secure domain.
 
 \b Notations
 
-This manual uses the following notations to identify functions and hardware resources that are related to TrustZone for ARMv8-M:
+This manual uses the following notations to identify functions and hardware resources that are related to TrustZone for Armv8-M:
 
- - prefix \b TZ or \b __TZ indicates a function that is available only in ARMv8-M TrustZone enabled devices.
+ - prefix \b TZ or \b __TZ indicates a function that is available only in Armv8-M TrustZone enabled devices.
  - postfix \b _NS indicates a hardware resource that belongs to the Non-secure state.
  - postfix \b _S indicates a hardware resource that belongs to the Secure state.
  
   
 \section useCase_TrustZone Simplified Use Case with TrustZone
 
-An ARMv8-M TrustZone enabled device has restricted access for data, code, and I/O access to trusted 
+An Armv8-M TrustZone enabled device has restricted access for data, code, and I/O access to trusted 
 software that runs in the Secure state. Typical applications are secure IoT nodes, firmware IP protection, 
 or multi-party embedded software deployments.
 
 The figure <b>Simplified Use Case</b> shows and embedded application that is split into a <b>User Project</b> 
 (executed in Non-secure state) and a <b>Firmware Project</b> (executed in Secure state). 
 
- - <b>System Start:</b> after power on or reset, an ARMv8-M system starts code execution in the <b>Secure state</b>. The access rights for the <b>Non-secure state</b> is configured.
+ - <b>System Start:</b> after power on or reset, an Armv8-M system starts code execution in the <b>Secure state</b>. The access rights for the <b>Non-secure state</b> is configured.
 
  - <b>User Application:</b> control can be transferred to <b>Non-secure state</b> to execute user code. This code can only call functions in the <b>secure state</b> that are marked for execution with the <b>SG</b> (secure gate) instruction and memory attributes. Any attempt to access memory or peripherals that are assigned to the <b>Secure state</b> triggers a security exception.
 
@@ -40,23 +40,23 @@ The figure <b>Simplified Use Case</b> shows and embedded application that is spl
 \image html "SimpleUseCase.png" "Simplified Use Case"
 
 Program execution in the <b>Secure state</b> is further protected by TrustZone hardware from software failures.
-For example, an ARMv8-M system may implement two independent SYSTICK timers which allows to stop code execution 
+For example, an Armv8-M system may implement two independent SYSTICK timers which allows to stop code execution 
 in <b>Non-secure state</b> in case of timing violations. Also function pointer callbacks from <b>Secure state</b> 
 to <b>Non-secure state</b> protected by a special CPU instruction and the address bit 0 which prevents anciently 
 executing code in <b>Non-secure state</b>.
 
 \subsection Example_TrustZone Program Examples
 
-This CMSIS software pack contains the following program examples that show the usage of TrustZone for ARMv8-M on Cortex-M33 devices:
+This CMSIS software pack contains the following program examples that show the usage of TrustZone for Armv8-M on Cortex-M33 devices:
 
 Example                                     | Description
 :-------------------------------------------|:----------------
-TrustZone for ARMv8-M No RTOS               | bare-metal secure/non-secure programming without RTOS (shows the Simplified Use Case).
-TrustZone for ARMv8-M RTOS                  | secure/non-secure RTOS example with thread context management
-TrustZone for ARMv8-M RTOS Security Tests   | secure/non-secure RTOS example with security test cases and system recovery
+TrustZone for Armv8-M No RTOS               | bare-metal secure/non-secure programming without RTOS (shows the Simplified Use Case).
+TrustZone for Armv8-M RTOS                  | secure/non-secure RTOS example with thread context management
+TrustZone for Armv8-M RTOS Security Tests   | secure/non-secure RTOS example with security test cases and system recovery
 
-Other sample application that reflects this <a href="#SimpleUseCase"><b>Simplified Use Case</b></a> is the <b>ARMv8MBL Secure/Non-Secure example</b> that is available in 
-the Software Pack <b>Keil - ARM V2M-MPS2 Board Support PACK for Cortex-M System Design Kit Devices</b> 
+Other sample application that reflects this <a href="#SimpleUseCase"><b>Simplified Use Case</b></a> is the <b>Armv8MBL Secure/Non-Secure example</b> that is available in 
+the Software Pack <b>Keil - Arm V2M-MPS2 Board Support PACK for Cortex-M System Design Kit Devices</b> 
 (Keil:V2M-MPS2_CMx_BSP.1.2.0.pack or higher).
 
 \section Model_TrustZone Programmers Model with TrustZone
@@ -88,7 +88,7 @@ The \ref partition_h_pg defines the initial setup of the <a href="#MemoryMap_NS"
 \anchor MemoryMap_NS
 \image html "MemoryMap_NS.png" "Non-Secure Memory Map" 
 
-The figure <b>Registers</b> shows the register view of the ARMv8-M system with TrustZone. As the general purpose registers
+The figure <b>Registers</b> shows the register view of the Armv8-M system with TrustZone. As the general purpose registers
 are can be accessed from any state (secure or non-secure), function calls between the states use these registers for parameter
 and return values.
 
@@ -96,17 +96,17 @@ The register R13 is the stack pointer alias, and the actual stack pointer (PSP_N
 accessed depends on state (Secure or Non-secure) and mode (handler=exception/interrupt execution or
 thread=normal code execution). 
 
-In ARMv8-M Mainline, each stack pointer has a limit register (PSPLIM_NS, MSPLIM_NS, PSPLIM_S, MSPLIM_S)
+In Armv8-M Mainline, each stack pointer has a limit register (PSPLIM_NS, MSPLIM_NS, PSPLIM_S, MSPLIM_S)
 that traps stack overflows with the \b UsageFault exception (register UFSR bit STKOF=1).
 
-An ARMv8-M system with TrustZone has an independent \b CONTROL register for each state (Secure or Non-secure).
+An Armv8-M system with TrustZone has an independent \b CONTROL register for each state (Secure or Non-secure).
 The interrupt/exception control registers (PRIMASK, FAULTMASK, BASEPRI) are banked between the states (Secure or Non-secure),
 however the interrupt priority for the Non-Secure state can be lowered (SCB_AIRCR register bit PRIS) so that 
 secure interrupts have always higher priority.
 
 The core registers of the current state (Secure or Non-secure) are accessed using the standard \ref Core_Register_gr
 functions. In Secure state all non-secure registers are accessible using the \ref coreregister_trustzone_functions 
-related to TrustZone for ARMv8-M.
+related to TrustZone for Armv8-M.
 
 \image html "Registers.png" "Registers"
 
@@ -123,14 +123,14 @@ Refer to \ref using_pg for a general description of the CMSIS-Core (Cortex-M) fi
 
 \subsection RTOS_TrustZone RTOS Thread Context Management
 
-To provide a consistent RTOS thread context management for ARMv8-M TrustZone across the various real-time operating systems (RTOS), the CMSIS-Core (Cortex-M) includes header file <b>TZ_context.h</b> with API definitions.
+To provide a consistent RTOS thread context management for Armv8-M TrustZone across the various real-time operating systems (RTOS), the CMSIS-Core (Cortex-M) includes header file <b>TZ_context.h</b> with API definitions.
 An <i>non-secure application</i> which uses an RTOS and calls <i>secure</i> library modules requires the management of the <i>secure</i> stack space.   Since <i>secure state</i> registers cannot be accessed 
 by the RTOS that runs in <i>non-secure state</i> secure functions implement the thread context switch.
 
 As the <i>non-secure state</i> and <i>secure state</i> parts of an application are separated, the API for managing the <i>secure</i> stack space should be standardized. Otherwise the <i>secure</i> library modules
 would force the <i>non-secure state</i> application to use a matching RTOS implementation.
 
-\image html "TZ_context.png" "RTOS Thread Context Management for ARMv8-M TrustZone"
+\image html "TZ_context.png" "RTOS Thread Context Management for Armv8-M TrustZone"
 
 To allocate the context memory for threads, an RTOS kernel that runs in <i>non-secure state</i> calls the interface functions defined by the header file <b>TZ_context.h</b>. The <b>TZ_context</b> functions itself are
 part of the <i>secure state</i> application. An minimum implementation is provided as part of RTOS2 and should handle the secure stack for the thread execution. However it is also possible to implement the context memory 

CMSIS/DoxyGen/Core_A/src/Overview.txt

@@ -12,7 +12,7 @@ In detail it defines:
 
 The following sections provide details about the CMSIS-Core (Cortex-A):
  - \ref using_pg describes the project setup and shows a simple program example.
- - \ref templates_pg describes the files of the CMSIS-Core (Cortex-A) in detail and explains how to adapt template files provided by ARM to silicon vendor devices.
+ - \ref templates_pg describes the files of the CMSIS-Core (Cortex-A) in detail and explains how to adapt template files provided by Arm to silicon vendor devices.
  - \ref coreMISRA_Exceptions_pg describes the violations to the MISRA standard.
  - <a href="Modules.html">\b Reference </a> describe the features and functions of the \ref device_h_pg in detail.
  - <a href="Annotated.html">\b Data \b Structures </a> describe the data structures of the \ref device_h_pg in detail.
@@ -27,7 +27,7 @@ Files relevant to CMSIS-Core (Cortex-A) are present in the following <b>ARM::CMS
 |--------------------------------|------------------------------------------------------------------------|
 |\b CMSIS\\Documentation\\Core_A | This documentation                                                     |
 |\b CMSIS\\Core_A\\Include       | CMSIS-Core (Cortex-A) header files (for example core_ca.h, etc.)                |
-|\b Device                       | \ref using_ARM_pg "ARM reference implementations" of Cortex-A devices  |
+|\b Device                       | \ref using_ARM_pg "Arm reference implementations" of Cortex-A devices  |
 |\b Device\\\_Template_Vendor    | \ref templates_pg for extension by silicon vendors                     |
 
 <hr>
@@ -38,21 +38,21 @@ CMSIS supports a selected subset of <a href="http://www.arm.com/products/process
 
 \subsection ref_man_ca_sec Cortex-A Technical Reference Manuals
 
-The following Technical Reference Manuals describe the various ARM Cortex-A processors:
-- <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0433c/DDI0433C_cortex_a5_trm.pdf" target="_blank"><b>Cortex-A5</b></a> (ARMv7-A architecture)
-- <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0464f/DDI0464F_cortex_a7_mpcore_r0p5_trm.pdf" target="_blank"><b>Cortex-A7</b></a> (ARMv7-A architecture)
-- <a href="http://infocenter.arm.com/help/topic/com.arm.doc.100511_0401_10_en/arm_cortexa9_trm_100511_0401_10_en.pdf" target="_blank"><b>Cortex-A9</b></a> (ARMv7-A architecture)
+The following Technical Reference Manuals describe the various Arm Cortex-A processors:
+- <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0433c/DDI0433C_cortex_a5_trm.pdf" target="_blank"><b>Cortex-A5</b></a> (Armv7-A architecture)
+- <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0464f/DDI0464F_cortex_a7_mpcore_r0p5_trm.pdf" target="_blank"><b>Cortex-A7</b></a> (Armv7-A architecture)
+- <a href="http://infocenter.arm.com/help/topic/com.arm.doc.100511_0401_10_en/arm_cortexa9_trm_100511_0401_10_en.pdf" target="_blank"><b>Cortex-A9</b></a> (Armv7-A architecture)
  
 <hr>
 
 \section tested_tools_sec Tested and Verified Toolchains
 
-The \ref templates_pg supplied by ARM have been tested and verified with the following toolchains:
- - ARM: ARM Compiler 5.06 update 6
- - ARM: ARM Compiler 6.9
- - ARM: ARM Compiler 6.6.2
- - GNU: GNU Tools for ARM Embedded 6.3.1 20170620
- - IAR: IAR ANSI C/C++ Compiler for ARM 8.20.1.14183
+The \ref templates_pg supplied by Arm have been tested and verified with the following toolchains:
+ - Arm: Arm Compiler 5.06 update 6
+ - Arm: Arm Compiler 6.9
+ - Arm: Arm Compiler 6.6.2
+ - GNU: GNU Tools for Arm Embedded 6.3.1 20170620
+ - IAR: IAR ANSI C/C++ Compiler for Arm 8.20.1.14183
  
 <hr>
 */

CMSIS/DoxyGen/Core_A/src/Ref_SystemAndClock.txt

@@ -4,7 +4,7 @@
 \defgroup   system_init_gr   System and Clock Configuration
 \brief Functions for system and clock setup available in system_<i>device</i>.c.
 \details
-ARM provides a template file <b>system_<i>device</i>.c</b> that must be adapted by 
+Arm provides a template file <b>system_<i>device</i>.c</b> that must be adapted by 
 the silicon vendor to match their actual device. As a <b>minimum requirement</b>, 
 this file must provide:
  -  A device-specific system configuration function, \ref SystemInit().
@@ -17,13 +17,13 @@ a more flexible configuration of the microcontroller system.
 \note Please pay special attention to the static variable \c SystemCoreClock. This variable might be
 used throughout the whole system initialization and runtime to calculate frequency/time related values.
 Thus one must assure that the variable always reflects the actual system clock speed. Be aware that
-a value stored to \c SystemCoreClock during low level initializaton (i.e. \c SystemInit()) might get
-overwritten by C libray startup code. Thus its highly recommended to call \ref SystemCoreClockUpdate
+a value stored to \c SystemCoreClock during low level initialization (i.e. \c SystemInit()) might get
+overwritten by C library startup code. Thus its highly recommended to call \ref SystemCoreClockUpdate
 at the beginning of the user \c main() routine.
 
 \section system_init_code_ex_sec Code Example
 The code below shows the usage of the variable \ref SystemCoreClock and the functions 
-SystemInit() and SystemCoreClockUpdate() with an arbitratry ARM Cortex-A9.
+SystemInit() and SystemCoreClockUpdate() with an arbitrary Arm Cortex-A9.
     
 \code
 #include "ARMCA9.h"

CMSIS/DoxyGen/Core_A/src/Template.txt

@@ -3,7 +3,7 @@
 
 \details
 
-ARM supplies CMSIS-Core device template files for the all supported Cortex-A processors and various compiler vendors.
+Arm supplies CMSIS-Core device template files for the all supported Cortex-A processors and various compiler vendors.
 Refer to the list of \ref tested_tools_sec for compliance.
 
 These CMSIS-Core device template files include the following:
@@ -17,7 +17,7 @@ The detailed file structure of the CMSIS-Core device templates is shown in the f
 
 \section CMSIS_Processor_files CMSIS-Core Processor Files 
 
-The CMSIS-Core processor files provided by ARM are in the directory .\\CMSIS\\Core_A\\Include. These header files define all processor specific attributes do not need any modifications.
+The CMSIS-Core processor files provided by Arm are in the directory .\\CMSIS\\Core_A\\Include. These header files define all processor specific attributes do not need any modifications.
 The <b>core_&lt;cpu&gt;.h</b> defines the core peripherals and provides helper functions that access the core registers. One file is available for each supported Cortex-A processor:
 
 Header File      | Processor
@@ -52,11 +52,11 @@ Silicon vendors add to these template files the following information:
     </tr>
     <tr>
       <td>.\\Device\\\_Template_Vendor\\Vendor\\Device_A\\Source\\ARM\\startup_Device.c</td>
-      <td>Startup file template for ARM C/C++ Compiler.</td>
+      <td>Startup file template for Arm C/C++ Compiler.</td>
     </tr>   
     <tr>
       <td>.\\Device\\\_Template_Vendor\\Vendor\\Device_A\\Source\\ARM\\Device.sct</td>
-      <td>Linker scatter file template for ARM C/C++ Compiler.</td>
+      <td>Linker scatter file template for Arm C/C++ Compiler.</td>
     </tr>
     <tr>
       <td>.\\Device\\\_Template_Vendor\\Vendor\\Device_A\\Source\\system_Device.c</td>
@@ -137,7 +137,7 @@ The file exists for each supported toolchain and is the only tool-chain specific
 
 \section startup_c_sec startup_Device.c Template File
 
-An ARM Compiler specific startup file for an ARMv7-A processor like Cortex-A9 is shown below.
+An Arm Compiler specific startup file for an Armv7-A processor like Cortex-A9 is shown below.
 The files for other compiler vendors differ slightly in the syntax, but not in the overall structure.
 
 \verbinclude "Source\ARM\startup_Device.c"
@@ -186,10 +186,10 @@ The \ref device_h_pg contains the following sections that are device specific:
 \section interrupt_number_sec Interrupt Number Definition
 
 \ref device_h_pg contains the enumeration \ref IRQn_Type that defines all exceptions and interrupts of the device.
-For devices implementing an ARM GIC these are defined as:
+For devices implementing an Arm GIC these are defined as:
   - IRQn 0-15 represents software generated interrupts (SGI), local to each processor core.
   - IRQn 16-31 represents private peripheral interrupts (PPI), local to each processor core.
-  - IRQn 32-1019 represents shared peripheral interrups (SPI), routeable to all processor cores.
+  - IRQn 32-1019 represents shared peripheral interrupts (SPI), routable to all processor cores.
   - IRQn 1020-1023 represents special interrupts, refer to the GIC Architecture Specification.
   
 \b Example:

CMSIS/DoxyGen/Core_A/src/Using.txt

@@ -41,13 +41,13 @@ The \ref device_h_pg is the central include file that the application programmer
 The CMSIS-Core-A user files are device specific. In addition, the \ref startup_c_pg is also compiler vendor specific. 
 The various compiler vendor tool chains may provide folders that contain the CMSIS files for each supported device.
   
-\note The silicon vendors create these device-specific CMSIS-Core-A files based on \ref templates_pg provide by ARM.
+\note The silicon vendors create these device-specific CMSIS-Core-A files based on \ref templates_pg provide by Arm.
 
 Thereafter, the functions described under <a href="Modules.html">\b Reference </a> can be used in the application.
 
 \b Examples
  - \subpage using_CMSIS is a simple example that shows the usage of the CMSIS layer.
- - \subpage using_ARM_pg explains how to use CMSIS-Core-M for ARM processors.
+ - \subpage using_ARM_pg explains how to use CMSIS-Core-M for Arm processors.
 
 
 \page using_CMSIS Basic CMSIS Example
@@ -112,11 +112,11 @@ int main(void)
 }
 \endcode
     
-\page using_ARM_pg Using CMSIS with generic ARM Processors
+\page using_ARM_pg Using CMSIS with generic Arm Processors
 
-ARM provides CMSIS-Core-A files for the supported ARM Processors and for various compiler vendors. 
-These files can be used when standard ARM processors should be used in a project.
-The table below lists the folder and device names of the ARM processors.
+Arm provides CMSIS-Core-A files for the supported Arm Processors and for various compiler vendors. 
+These files can be used when standard Arm processors should be used in a project.
+The table below lists the folder and device names of the Arm processors.
   
 <table class="cmtable">
   <tr>

CMSIS/DoxyGen/Core_A/src/cmsis_armcc.txt

@@ -20,9 +20,9 @@ Each CMSIS compliant compiler should support the functionality described in this
 
 /**
 \def __ARM_ARCH_7A__    
-\brief Set to 1 when generating code for ARMv7-A (Cortex-A7)
+\brief Set to 1 when generating code for Armv7-A (Cortex-A7)
 \details
-The \b \#define __ARM_ARCH_7A__ is set to 1 when generating code for the ARMv7-A architecture. This architecture is for example used by the Cortex-A7 processor.
+The \b \#define __ARM_ARCH_7A__ is set to 1 when generating code for the Armv7-A architecture. This architecture is for example used by the Cortex-A7 processor.
 */
 
 /**      

CMSIS/DoxyGen/Core_A/src/core_ca.txt

@@ -345,7 +345,7 @@ Hardware Abstraction Layer.
 \defgroup FPU_functions Floating Point Unit Functions
 \ingroup CMSIS_Core_FunctionInterface
 \brief FPU Functions enable the use of Floating Point instructions and extensions.\n
-Reference: <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0406c/index.html">Architecture Reference Manual Reference Manual - ARMv7-A and ARMv7-R edition</a>.
+Reference: <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0406c/index.html">Architecture Reference Manual Reference Manual - Armv7-A and Armv7-R edition</a>.
 @{
 \fn __STATIC_INLINE __ASM void __FPU_Enable(void) 
 @}

CMSIS/DoxyGen/Core_A/src/irq_ctrl.txt

@@ -7,10 +7,10 @@
 \details This section describes the device agnostic interrupt API viable for a wide range of specific interrupt controllers.
 The IRQ Controller API allows interrupt dependend applications to be easily portable across a wide range of controllers.
 
-\note The default implementation for \ref GIC_functions "ARM GIC (Generic Interrupt Controller)" can be found in \ref irq_ctrl_gic.c.
+\note The default implementation for \ref GIC_functions "Arm GIC (Generic Interrupt Controller)" can be found in \ref irq_ctrl_gic.c.
 It uses \c weak functions thus it can easily be overwritten by an alternative user implementation if needed.
 
-The ARMv7-A architecture defines a common set of first level exceptions, see table below.
+The Armv7-A architecture defines a common set of first level exceptions, see table below.
 
 | Exception                     | CMSIS Handler | Offset | Description                                                                 |
 |-------------------------------|---------------|--------|-----------------------------------------------------------------------------|
@@ -138,7 +138,7 @@ It disables all interrupt sources, clears all pending interrupts, sets interrupt
 configures priority mask to lowest priority. IRQ and FIQ signal lines should be enabled and all interrupt handlers should
 be set to NULL.
 
-For ARM GIC the default implementation looks like the following example:
+For Arm GIC the default implementation looks like the following example:
 
 \code
 /// Number of implemented interrupt lines
@@ -166,7 +166,7 @@ int32_t IRQ_Initialize (void) {
 \details This function registers address of the interrupt handler callback function corresponding to the specified interrupt
 ID number.
 
-For ARM GIC the default implementation looks like the following example:
+For Arm GIC the default implementation looks like the following example:
 
 \code
 int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler) {
@@ -190,7 +190,7 @@ int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler) {
 \details This function retrieves address of the interrupt handler callback function corresponding to the specified interrupt
 ID number.
 
-For ARM GIC the default implementation looks like the following example:
+For Arm GIC the default implementation looks like the following example:
 
 \code
 IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn) {
@@ -212,7 +212,7 @@ IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn) {
 \fn int32_t IRQ_Enable (IRQn_ID_t irqn)
 \details This function enables forwarding of the corresponding interrupt to the CPU.
 
-For ARM GIC the default implementation looks like the following example:
+For Arm GIC the default implementation looks like the following example:
 
 \code
 int32_t IRQ_Enable (IRQn_ID_t irqn) {
@@ -235,7 +235,7 @@ int32_t IRQ_Enable (IRQn_ID_t irqn) {
 \fn int32_t IRQ_Disable (IRQn_ID_t irqn)
 \details This function disables forwarding of the corresponding interrupt to the CPU. 
 
-For ARM GIC the default implementation looks like the following example:
+For Arm GIC the default implementation looks like the following example:
 
 \code
 int32_t IRQ_Disable (IRQn_ID_t irqn) {
@@ -261,7 +261,7 @@ int32_t IRQ_Disable (IRQn_ID_t irqn) {
 Interrupt enable status can be either disabled (0) or enabled (1). Disabled status is returned for interrupts
 which cannot be identified by irqn. 
 
-For ARM GIC the default implementation looks like the following example:
+For Arm GIC the default implementation looks like the following example:
 
 \code
 uint32_t IRQ_GetEnableState (IRQn_ID_t irqn) {
@@ -285,7 +285,7 @@ uint32_t IRQ_GetEnableState (IRQn_ID_t irqn) {
 \details This function configures the interrupt triggering mode, type, secure access and target CPUs of the interrupt
 (see \ref irq_mode_defs) identified by the irqn parameter.
 
-For ARM GIC the default implementation looks like the following example:
+For Arm GIC the default implementation looks like the following example:
 
 \code
 int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode) {
@@ -364,7 +364,7 @@ int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode) {
 \details This function retrieves interrupt mode configuration of the interrupt identified by the irqn parameter.
 \ref IRQ_MODE_ERROR is returned for interrupts which cannot be identified by irqn.
 
-For ARM GIC the default implementation looks like the following example:
+For Arm GIC the default implementation looks like the following example:
 
 \code
 uint32_t IRQ_GetMode (IRQn_ID_t irqn) {
@@ -402,7 +402,7 @@ uint32_t IRQ_GetMode (IRQn_ID_t irqn) {
 \fn IRQn_ID_t IRQ_GetActiveIRQ (void)
 \details This function retrieves the interrupt ID number of current IRQ source and acknowledges the interrupt. 
 
-For ARM GIC the default implementation looks like the following example:
+For Arm GIC the default implementation looks like the following example:
 
 \code
 IRQn_ID_t IRQ_GetActiveIRQ (void) {
@@ -420,7 +420,7 @@ IRQn_ID_t IRQ_GetActiveIRQ (void) {
 \fn IRQn_ID_t IRQ_GetActiveFIQ (void)
 \details This function retrieves the interrupt ID number of current FIQ source and acknowledges the interrupt.
 
-For ARM GIC the default implementation looks like the following example:
+For Arm GIC the default implementation looks like the following example:
 
 \code
 IRQn_ID_t IRQ_GetActiveFIQ (void) {
@@ -438,7 +438,7 @@ active interrupt request is completed.
 
 The parameter irqn should specify the value previously returned by the \ref IRQ_GetActiveIRQ or \ref IRQ_GetActiveFIQ functions.
 
-For ARM GIC the default implementation looks like the following example:
+For Arm GIC the default implementation looks like the following example:
 
 \code
 int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn) {
@@ -466,7 +466,7 @@ int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn) {
 \fn int32_t IRQ_SetPending (IRQn_ID_t irqn) 
 \details This function sets the pending status of the interrupt identified by the irqn parameter.
 
-For ARM GIC the default implementation looks like the following example:
+For Arm GIC the default implementation looks like the following example:
 
 \code
 int32_t IRQ_SetPending (IRQn_ID_t irqn) {
@@ -492,7 +492,7 @@ int32_t IRQ_SetPending (IRQn_ID_t irqn) {
 Interrupt pending status can be either not pending (0) or pending (1). Not pending status is returned for interrupts which
 cannot be identified by irqn.
 
-For ARM GIC the default implementation looks like the following example:
+For Arm GIC the default implementation looks like the following example:
 
 \code
 uint32_t IRQ_GetPending (IRQn_ID_t irqn) {
@@ -514,7 +514,7 @@ uint32_t IRQ_GetPending (IRQn_ID_t irqn) {
 \fn int32_t IRQ_ClearPending (IRQn_ID_t irqn) 
 \details This function clears the pending status of the interrupt identified by the irqn parameter.
 
-For ARM GIC the default implementation looks like the following example:
+For Arm GIC the default implementation looks like the following example:
 
 \code
 int32_t IRQ_ClearPending (IRQn_ID_t irqn) {
@@ -543,7 +543,7 @@ depends on the number of implemented priority levels.
 The number of implemented priority bits can be determined by setting value \ref IRQ_PRIORITY_Msk to arbitrary irqn and by
 retrieving the actual stored value with IRQ_GetPriority function.
 
-For ARM GIC the default implementation looks like the following example:
+For Arm GIC the default implementation looks like the following example:
 
 \code
 int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority) {
@@ -569,7 +569,7 @@ int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority) {
 The valid priority value can be from zero (0) to the value of \ref IRQ_PRIORITY_Msk. \ref IRQ_PRIORITY_ERROR bit is set in
 returned value for interrupts which cannot be identified by irqn.
 
-For ARM GIC the default implementation looks like the following example:
+For Arm GIC the default implementation looks like the following example:
 
 \code
 uint32_t IRQ_GetPriority (IRQn_ID_t irqn) {
@@ -594,7 +594,7 @@ uint32_t IRQ_GetPriority (IRQn_ID_t irqn) {
 It ensures that only interrupts with a higher priority than priority threshold value are signaled to the target processor.
 Function returns error status -1 if priority masking is not supported.
 
-For ARM GIC the default implementation looks like the following example:
+For Arm GIC the default implementation looks like the following example:
 
 \code
 IRQ_SetPriorityMask (uint32_t priority) {
@@ -611,7 +611,7 @@ IRQ_SetPriorityMask (uint32_t priority) {
 
 \ref IRQ_PRIORITY_ERROR value is returned if priority masking is not supported.
 
-For ARM GIC the default implementation looks like the following example:
+For Arm GIC the default implementation looks like the following example:
 
 \code
 uint32_t IRQ_GetPriorityMask (void) {
@@ -630,7 +630,7 @@ The number of implemented group priority bits can be determined by setting value
 actual stored value with \ref IRQ_GetPriorityGroupBits function.
 Function returns error status -1 if priority grouping is not supported.
 
-For ARM GIC the default implementation looks like the following example:
+For Arm GIC the default implementation looks like the following example:
 
 \code
 int32_t IRQ_SetPriorityGroupBits (uint32_t bits) {
@@ -660,7 +660,7 @@ priority to preempt a currently active interrupt.
 
 \ref IRQ_PRIORITY_ERROR value is returned when priority grouping is not supported.
 
-For ARM GIC the default implementation looks like the following example:
+For Arm GIC the default implementation looks like the following example:
 
 \code
 uint32_t IRQ_GetPriorityGroupBits (void) {

CMSIS/DoxyGen/Core_A/src/ref_core_register.txt

@@ -13,7 +13,7 @@
 \ingroup CMSIS_core_register
 \brief The ACTLR provides IMPLEMENTATION DEFINED configuration and control options.
 \details
-The ACTLR characteristics are differs between various ARMv7-A implementations.
+The ACTLR characteristics are differs between various Armv7-A implementations.
 
 <b>Cortex-A5</b>
 
@@ -1044,7 +1044,7 @@ Consider using \ref __get_SCTLR and \ref __set_SCTLR for accessing this register
 /**
 \defgroup CMSIS_TLB TLB maintenance operations
 \ingroup CMSIS_core_register
-\brief This section describes the TLB operations that are implemented on all ARMv7-A implementations.
+\brief This section describes the TLB operations that are implemented on all Armv7-A implementations.
 \details 
 TLB maintenance operations provide a mechanism to invalidate entries from a TLB.
 

CMSIS/DoxyGen/Core_A/src/ref_gic.txt

@@ -330,7 +330,7 @@ includes control of the end of interrupt (EOI) behavior.
 
 The binary point (values 0-7) defines the amount of priority bits used as subpriority. Please
 refer to the section Interrupt prioritization in the
-<a href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0048b/index.html">ARM Generic Interrupt Controller Architecture Specificaton</a>
+<a href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0048b/index.html">Arm Generic Interrupt Controller Architecture Specificaton</a>
 for details.
 
 \var __IOM uint32_t GICInterface_Type::ABPR

CMSIS/DoxyGen/Core_A/src/ref_mmu.txt

@@ -3,7 +3,7 @@
 \defgroup MMU_functions Memory Management Unit Functions
 \ingroup CMSIS_Core_FunctionInterface
 \brief MMU Functions provide control of the Memory Management Unit using translation tables and attributes of different regions of the physical memory map.\n
-Reference: <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0406c/index.html">Architecture Reference Manual Reference Manual - ARMv7-A and ARMv7-R edition</a>.
+Reference: <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0406c/index.html">Architecture Reference Manual Reference Manual - Armv7-A and Armv7-R edition</a>.
 */
 
 /** @{ */

CMSIS/DoxyGen/DAP/src/dap.txt

@@ -3,7 +3,7 @@
 
 <b>CMSIS-DAP</b> is a specification and a implementation of a <b>Firmware</b> that supports access to the CoreSight <b>Debug Access Port</b> (DAP).\n\n
 
-The various ARM Cortex processors provide <a href="http://www.arm.com/products/system-ip/coresight/index.php" target="_blank">
+The various Arm Cortex processors provide <a href="http://www.arm.com/products/system-ip/coresight/index.php" target="_blank">
 <b>CoreSight Debug and Trace</b></a>. CMSIS-DAP supports target Devices that contain one or more Cortex processors. 
 A Device provides a Debug Access Port (DAP) typically either with a 5-pin JTAG or with a 2-pin Serial Wired Debug (SWD)
 interface that connects to a Debug Unit. CMSIS-DAP is the interface firmware for a Debug Unit that connects 
@@ -62,7 +62,7 @@ Directory                             | Description
 Debug Access
 ------------
 \note
-ARM plans to provide the <b>RDDI-DAP Access DLL</b> that connects a debugger to the CMSIS-DAP Firmware. 
+Arm plans to provide the <b>RDDI-DAP Access DLL</b> that connects a debugger to the CMSIS-DAP Firmware. 
 However as the DAP registers are standard in all Cortex devices, the debug access is well understood
 by the industry.
 

CMSIS/DoxyGen/DAP/src/dap_USB_cmds.txt

@@ -592,7 +592,7 @@ SWD/JTAG Reset, SWD<->JTAG switch and Dormant operation.
 \brief Configure SWD Protocol
 \details
 The <b>DAP_SWD_Configure Command</b> sets the SWD protocol configuration. For more information about 
-the SWD protocol refer to the <b>ARM Debug Interface v5 - Interface Specification.</b>
+the SWD protocol refer to the <b>Arm Debug Interface v5 - Interface Specification.</b>
 
 <b>DAP_SWD_Configure Command</b>:
 \code

CMSIS/DoxyGen/DAP/src/dap_config.txt

@@ -216,7 +216,7 @@ You may change this define with a compiler option.
 @{
 A CMSIS-DAP conforming Debug Unit must be validated.
 
-A CMSIS-DAP Debug Unit must be validate using the Keil MDK-ARM Debugger. 
+A CMSIS-DAP Debug Unit must be validate using the Keil MDK Debugger. 
 A validation project for MDK is provided in the folder <b>.\\Validation\\MDK</b>.
 The project <b>Blinky.uvproj</b> is a "Blinky" application and needs to be adapted for the target hardware
 that is connected to the Debug Unit. Once the adaptation is complete, you may open a Command Prompt and

CMSIS/DoxyGen/DSP/src/Change Log.txt

@@ -58,7 +58,7 @@ Modified arm_math.h, arm_bitreversal2.S
 - corrected arm_sin_f32() for very small negative input values.
 
 Modified arm_sin_f32.c
-- Updated Texas Instruments ARM compiler support.
+- Updated Texas Instruments Arm Compiler support.
 
 Updated documentation
 - function \ref arm_rfft_fast_f32.

CMSIS/DoxyGen/Doxygen_Templates/cmsis_footer.html

@@ -3,7 +3,7 @@
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
     $navpath
-    <li class="footer">Generated on $datetime for $projectname by ARM Ltd. All rights reserved.
+    <li class="footer">Generated on $datetime for $projectname by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="$relpath$doxygen.png" alt="doxygen"/></a> $doxygenversion 

CMSIS/DoxyGen/Driver/src/Driver_ETH.c

@@ -1,13 +1,3 @@
-/* -----------------------------------------------------------------------------
- * Copyright (c) 2013-2014 ARM Limited. All rights reserved.
- *  
- * $Date:        2. January 2014
- * $Revision:    V2.00
- *  
- * Project:      Ethernet Driver API
- * -------------------------------------------------------------------------- */
-
-
 /**
 \defgroup eth_interface_gr Ethernet Interface
 \brief    Ethernet common definitions (%Driver_ETH.h)

CMSIS/DoxyGen/Driver/src/Driver_ETH_MAC.c

@@ -1,13 +1,3 @@
-/* -----------------------------------------------------------------------------
- * Copyright (c) 2013-2014 ARM Limited. All rights reserved.
- *  
- * $Date:        2. January 2014
- * $Revision:    V2.00
- *  
- * Project:      Ethernet MAC Driver API
- * -------------------------------------------------------------------------- */
-
-
 /**
 \defgroup   eth_mac_interface_gr Ethernet MAC Interface
 \ingroup    eth_interface_gr

CMSIS/DoxyGen/Driver/src/Driver_ETH_PHY.c

@@ -1,13 +1,3 @@
-/* -----------------------------------------------------------------------------
- * Copyright (c) 2013-2014 ARM Limited. All rights reserved.
- *  
- * $Date:        2. January 2014
- * $Revision:    V2.00
- *  
- * Project:      Ethernet PHY Driver API
- * -------------------------------------------------------------------------- */
-
-
 /**
 \defgroup eth_phy_interface_gr Ethernet PHY Interface
 \ingroup eth_interface_gr

CMSIS/DoxyGen/Driver/src/Driver_Flash.c

@@ -1,13 +1,3 @@
-/* -----------------------------------------------------------------------------
- * Copyright (c) 2013-2014 ARM Limited. All rights reserved.
- *  
- * $Date:        2. January 2014
- * $Revision:    V2.00
- *  
- * Project:      Flash Driver API
- * -------------------------------------------------------------------------- */
-
-
 /**
 \defgroup flash_interface_gr Flash Interface
 \brief    Driver API for Flash Device Interface (%Driver_Flash.h)

CMSIS/DoxyGen/Driver/src/Driver_I2C.c

@@ -1,13 +1,3 @@
-/* -----------------------------------------------------------------------------
- * Copyright (c) 2013-2014 ARM Limited. All rights reserved.
- *  
- * $Date:        2. January 2014
- * $Revision:    V2.00
- *  
- * Project:      I2C Driver API
- * -------------------------------------------------------------------------- */
-
-
 /**
 \defgroup i2c_interface_gr I2C Interface
 \brief    Driver API for I2C Bus Peripheral (%Driver_I2C.h)

CMSIS/DoxyGen/Driver/src/Driver_MCI.c

@@ -1,13 +1,3 @@
-/* -----------------------------------------------------------------------------
- * Copyright (c) 2013-2014 ARM Limited. All rights reserved.
- *  
- * $Date:        2. January 2014
- * $Revision:    V2.00
- *  
- * Project:      MCI Driver API
- * -------------------------------------------------------------------------- */
-
-
 /**
 \defgroup mci_interface_gr MCI Interface
 \brief    Driver API for Memory Card Interface using SD/MMC interface (%Driver_MCI.h)

CMSIS/DoxyGen/Driver/src/Driver_NAND.c

@@ -1,13 +1,3 @@
-/* -----------------------------------------------------------------------------
- * Copyright (c) 2013-2014 ARM Limited. All rights reserved.
- *  
- * $Date:        2. January 2014
- * $Revision:    V2.00
- *  
- * Project:      NAND Flash Driver API
- * -------------------------------------------------------------------------- */
-
-
 /**
 \defgroup nand_interface_gr NAND Interface
 \brief    Driver API for NAND Flash Device Interface (%Driver_NAND.h).

CMSIS/DoxyGen/Driver/src/Driver_SPI.c

@@ -1,13 +1,3 @@
-/* -----------------------------------------------------------------------------
- * Copyright (c) 2013-2014 ARM Limited. All rights reserved.
- *  
- * $Date:        2. January 2014
- * $Revision:    V2.00
- *  
- * Project:      SPI Driver API
- * -------------------------------------------------------------------------- */
-
-
 /**
 \defgroup spi_interface_gr SPI Interface
 \brief Driver API for SPI Bus Peripheral (%Driver_SPI.h)

CMSIS/DoxyGen/Driver/src/Driver_Storage.c

@@ -1,13 +1,3 @@
-/* -----------------------------------------------------------------------------
- * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
- *
- * $Date:        7. March 2016
- * $Revision:    V1.00
- *
- * Project:      Storage Driver API
- * -------------------------------------------------------------------------- */
-
-
 /**
 \defgroup storage_interface_gr Storage Interface
 \brief    Driver API for Storage Device Interface (%Driver_Storage.h)
@@ -625,7 +615,7 @@ and then read it back to be verified. It handles both synchronous and
 asynchronous driver implementations.
 
 \code
-// Copyright (c) 2006-2016, ARM Limited, All Rights Reserved
+// Copyright (c) 2006-2016, Arm Limited, All Rights Reserved
 // SPDX-License-Identifier: Apache-2.0
 //
 // Licensed under the Apache License, Version 2.0 (the "License"); you may

CMSIS/DoxyGen/Driver/src/Driver_USART.c

@@ -1,13 +1,3 @@
-/* -----------------------------------------------------------------------------
- * Copyright (c) 2013-2014 ARM Limited. All rights reserved.
- *  
- * $Date:        2. January 2014
- * $Revision:    V2.00
- *  
- * Project:      USART Driver API
- * -------------------------------------------------------------------------- */
-
-
 /**
 \defgroup usart_interface_gr USART Interface
 \brief   Driver API for Universal Synchronous Asynchronous Receiver/Transmitter (%Driver_USART.h)

CMSIS/DoxyGen/Driver/src/Driver_USB.c

@@ -1,13 +1,3 @@
-/* -----------------------------------------------------------------------------
- * Copyright (c) 2013-2014 ARM Limited. All rights reserved.
- *  
- * $Date:        2. January 2014
- * $Revision:    V2.00
- *  
- * Project:      USB Driver API
- * -------------------------------------------------------------------------- */
-
-
 /**
 \defgroup usb_interface_gr USB Interface
 \brief   USB common definitions (%Driver_USB.h)

CMSIS/DoxyGen/Driver/src/Driver_USBD.c

@@ -1,13 +1,3 @@
-/* -----------------------------------------------------------------------------
- * Copyright (c) 2013-2014 ARM Limited. All rights reserved.
- *  
- * $Date:        2. January 2014
- * $Revision:    V2.00
- *  
- * Project:      USB Device Driver API
- * -------------------------------------------------------------------------- */
-
-
 /**
 \defgroup   usbd_interface_gr USB Device Interface
 \ingroup    usb_interface_gr

CMSIS/DoxyGen/Driver/src/Driver_USBH.c

@@ -1,13 +1,3 @@
-/* -----------------------------------------------------------------------------
- * Copyright (c) 2013-2014 ARM Limited. All rights reserved.
- *  
- * $Date:        2. January 2014
- * $Revision:    V2.00
- *  
- * Project:      USB Host Driver API
- * -------------------------------------------------------------------------- */
-
-
 /**
 \defgroup usbh_interface_gr USB Host Interface
 \ingroup usb_interface_gr

CMSIS/DoxyGen/General/src/introduction.txt

@@ -13,8 +13,8 @@ provides a common approach to interface to peripherals, real-time operating syst
 and middleware components. The CMSIS is intended to enable the combination of software components 
 from multiple middleware vendors. 
 
-CMSIS Version 5 supports also the <a class="el" href="http://www.arm.com/products/processors/instruction-set-architectures/armv8-m-architecture.php" target="_blank">ARMv8-M architecture</a> 
-including <a class="el" href="http://www.arm.com/products/processors/technologies/trustzone/index.php" target="_blank">TrustZone&reg; for ARMv8-M</a> hardware security extensions and the
+CMSIS Version 5 supports also the <a class="el" href="http://www.arm.com/products/processors/instruction-set-architectures/armv8-m-architecture.php" target="_blank">Armv8-M architecture</a> 
+including <a class="el" href="http://www.arm.com/products/processors/technologies/trustzone/index.php" target="_blank">TrustZone&reg; for Armv8-M</a> hardware security extensions and the
 <a class="el" href="http://www.arm.com/products/processors/cortex-m/cortex-m23-processor.php" target="_blank">Cortex-M23</a> and <a class="el" href="http://www.arm.com/products/processors/cortex-m/cortex-m33-processor.php" target="_blank">Cortex-M33</a> processors.
 
 \anchor CM_Components
@@ -35,7 +35,7 @@ The CMSIS components are:
  - <a href="../../RTOS/html/index.html"><b>CMSIS-RTOS v1</b></a>: Common API for Real-Time Operating Systems along with reference implementation based on RTX.
     It provides a standardized programming interface that is portable to many RTOS and enables software components that can work across multiple RTOS systems.
  
- - <a href="../../RTOS2/html/index.html"><b>CMSIS-RTOS v2</b></a>: extends CMSIS-RTOS v1 with support for ARMv8-M architecture, dynamic object creation,
+ - <a href="../../RTOS2/html/index.html"><b>CMSIS-RTOS v2</b></a>: extends CMSIS-RTOS v1 with support for Armv8-M architecture, dynamic object creation,
     provisions for multi-core systems, and binary compatible interface across ABI compliant compilers.
 
  - <a href="../../Pack/html/index.html"><b>CMSIS-Pack</b></a>: describes with an XML-based package description (PDSC) file the user and device relevant parts of a file collection (called a software pack) that includes source, header and library files, documentation, 
@@ -109,27 +109,27 @@ Doxygen	comment example:
 \section Validation Validation
 
 The various components of CMSIS Version 5 are validated using mainstream compilers.  To get a diverse coverage,
-ARM uses the ARM Compiler v5 (based on EDG front-end), the ARM Compiler v6 (based on LLVM front-end), and the
+Arm uses the Arm Compiler v5 (based on EDG front-end), the Arm Compiler v6 (based on LLVM front-end), and the
 GCC Compiler in the various tests. For each component, the section \b "Validation" describes the scope of the 
 various verifications. 
 
 CMSIS components are compatible with a range of C and C++ language standards. The CMSIS components comply with 
 the <a href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0036b/index.html">Application Binary 
-Interface (ABI) for the ARM Architecture</a> (exception CMSIS-RTOS v1). This ensures C API interfaces that support 
+Interface (ABI) for the Arm Architecture</a> (exception CMSIS-RTOS v1). This ensures C API interfaces that support 
 inter-operation between various toolchains.
 
 As CMSIS defines API interfaces and functions that scale to a wide range of processors and devices, the scope of 
 the run-time test coverage is limited. However, several components are validated using dedicated test suites.
 
 The CMSIS source code is checked for MISRA C:2012 conformance using PC-Lint. MISRA deviations are documented with
-reasonable effort, however ARM does not claim MISRA compliance as there is today for example no guideline enforcement 
+reasonable effort, however Arm does not claim MISRA compliance as there is today for example no guideline enforcement 
 plan. The CMSIS source code is not checked for MISRA C++:2008 conformance as there is a risk that it is incompatible 
 with C language standards, specifically warnings that may be generated by the various C compilers.
 
 
 \section License License
 
-The CMSIS is provided free of charge by ARM under Apache 2.0 license. 
+The CMSIS is provided free of charge by Arm under Apache 2.0 license. 
 View the <a href="LICENSE.txt">Apache 2.0 License</a>.
 
 
@@ -142,7 +142,7 @@ File/Directory    |Content
 \b ARM.CMSIS.pdsc |Package description file in CMSIS-Pack format.                                                         
 \b LICENSE.txt    |CMSIS License Agreement (Apache 2.0)
 \b CMSIS          |\ref CM_Components "CMSIS components" (see below)                                 
-\b Device         |CMSIS reference implementations of ARM Cortex-M processor based devices                                 
+\b Device         |CMSIS reference implementations of Arm Cortex-M processor based devices                                 
 
 CMSIS Directory
 ---------------
@@ -193,7 +193,7 @@ In addition, each CMSIS component has its own release history:
     <tr>
       <td>5.2.0</td>
       <td>
-        - CMSIS-Core (Cortex-M) 5.1.0 MPU fuctions for ARMv8-M, cmsis_iccarm.h replacing cmsis_iar.h
+        - CMSIS-Core (Cortex-M) 5.1.0 MPU functions for ARMv8-M, cmsis_iccarm.h replacing cmsis_iar.h
         - CMSIS-Core (Cortex-A) 1.1.0 cmsis_iccarm.h, additional physical timer access functions
         - CMSIS-Driver 2.6.0 Enhanced CAN and NAND driver interface.
         - CMSIS-DSP 1.5.2 Fixed diagnostics and moved SSAT/USST intrinsics to CMSIS-Core.

CMSIS/DoxyGen/Pack/src/General.txt

@@ -27,7 +27,7 @@ The \subpage pack_revisionHistory lists the main changes between versions.
 The figure above shows the following use cases for Software Packs:
   - <b>Device Family Pack (DFP):</b> contains CMSIS system/startup files, drivers, and flash algorithms for a microcontroller
     device family.
-  - <b>CMSIS Software Pack:</b> contains the generic CMSIS components (CORE, DSP Library, and RTOS implementation) supplied by ARM.
+  - <b>CMSIS Software Pack:</b> contains the generic CMSIS components (CORE, DSP Library, and RTOS implementation) supplied by Arm.
   - <b>Middleware Pack:</b> contains software components belonging to a middleware (such as source code or libraries).
   - <b>Board Support Pack (BSP):</b> contains documentation, schematics, and drivers for a certain development board.
   - <b>In-house Software Packs:</b> usually contain software components that can be distributed within a
@@ -101,7 +101,7 @@ Files relevant to CMSIS-Pack are present in the following \b ARM::CMSIS director
     <td>Modifications compared to Version 1.4.6
 - added multiple version types to tighten the schema checking depending on context
 - added new generator sections for exe, web and eclipse based generators in \<generator>
-- added new processor attributes Dtz = Trustzone and Ddsp = DSP instructions for ARMv8-M
+- added new processor attributes Dtz = Trustzone and Ddsp = DSP instructions for Armv8-M
 - added new attributes Dtz, Ddsp, Dsecure to conditions \<require>, \<deny>, \<accept>
 - added new processors Cortex-M23 and Cortex-M33 and other in DcoreEnum
 - added new attribute public to books and images to indicate public use of documents and board images

CMSIS/DoxyGen/Pack/src/boards_schema.txt

@@ -478,7 +478,7 @@ This element describes the debug interface of a board. At least debug interface
 
 \b Example
 \code
-<debugInterface adapter="JTAG/SW" connector="20-pin ARM Standard JTAG Connector (0.1 inch connector)"/>
+<debugInterface adapter="JTAG/SW" connector="20-pin Arm Standard JTAG Connector (0.1 inch connector)"/>
 <debugInterface adapter="JTAG/SW" connector="10-pin Cortex Debug Connector (0.05 inch connector)"/>
 <debugInterface adapter="JTAG/SW" connector="20-pin Cortex Debug + ETM Connector (0.05 inch connector)"/>
 <debugInterface adapter="ST-Link" connector="Mini-USB"/>
@@ -509,7 +509,7 @@ This element describes the debug interface of a board. At least debug interface
   </tr>
   <tr>
     <td>connector</td>
-    <td>String describing the debug connector. Usually one of these: \token{10-pin Cortex Debug Connector}, \token{20-pin ARM Standard JTAG Connector}, 
+    <td>String describing the debug connector. Usually one of these: \token{10-pin Cortex Debug Connector}, \token{20-pin Arm Standard JTAG Connector}, 
 	\token{20-pin Cortex Debug + ETM Connector}, \token{Mini-USB}, \token{Micro-USB}.</td>
     <td>xs:string</td>
     <td>optional</td>

CMSIS/DoxyGen/Pack/src/components_schema.txt

@@ -66,7 +66,7 @@ not used by multiple components.
     </component>
 
     <component condition="ARM_CM0" Cclass="Device" Cgroup="Startup" Cversion="3.1.1">
-      <description>System Startup for generic ARM Cortex-M0 device</description>
+      <description>System Startup for generic Arm Cortex-M0 device</description>
       <files>
         <file category="header" name="Device/ARM/ARMCM0/Include/ARMCM0.h"/>
         <file category="header" name="Device/ARM/ARMCM0/Include/system_ARMCM0.h"/>

CMSIS/DoxyGen/Pack/src/conditions_schema.txt

@@ -328,9 +328,9 @@ A \ref element_condition "condition" becomes \token{true} when:
   <tr>
     <td>Toptions</td>
     <td>Specifies compiler specific options being active. For <em>Tcompiler="ARMCC"</em> available Toptions are:
-        - <b>AC5</b>: ARM Compiler Version 5 is in used
-        - <b>AC6</b>: ARM Compiler Version 6 (aka: ARM Clang 6) is in use
-        - <b>AC6LTO</b>: ARM Compiler Version 6 with Link Time Optimization (aka: LTO) is in use
+        - <b>AC5</b>: Arm Compiler Version 5 is in used
+        - <b>AC6</b>: Arm Compiler Version 6 (armclang) is in use
+        - <b>AC6LTO</b>: Arm Compiler Version 6 with Link Time Optimization (LTO) is in use
         
         This attribute can be used to select compatible libraries for the selected compiler version or optimization mode.
     </td>
@@ -370,8 +370,8 @@ The tokens can be used in the elements:
   </tr>
   <tr>
     <td class="XML-Token">GCC</td>
-    <td>GNU Tools for ARM Embedded Processors. 
-    Refer to <a href="https://launchpad.net/gcc-arm-embedded/4.7" target="_blank">ARM GCC</a>.</td>
+    <td>GNU Tools for Arm Embedded Processors. 
+    Refer to <a href="https://launchpad.net/gcc-arm-embedded/4.7" target="_blank">Arm GCC</a>.</td>
   </tr>
   <tr>
     <td class="XML-Token">G++</td>
@@ -379,9 +379,9 @@ The tokens can be used in the elements:
   </tr>
   <tr>
     <td class="XML-Token">ARMCC</td>
-    <td>ARM compiler for C and C++. 
+    <td>Arm Compiler for C and C++. 
     Refer to <a href="http://infocenter.arm.com/help/topic/com.arm.doc.subset.swdev.coretools/index.html" target="_blank">
-    ARM Compiler from ARM</a>.</td>
+    Arm Compiler</a>.</td>
   </tr>
   <tr>
     <td class="XML-Token">IAR</td>

CMSIS/DoxyGen/Pack/src/devices_schema.txt

@@ -49,7 +49,7 @@ and finalizing with the information on the device level.
       <book      name="doc/STM32F2.PDF" title="STM32F2 Reference Manual"/>
 
       <description>
-        ARM 32-bit Cortex-M3 CPU based Microcontroller
+        Arm 32-bit Cortex-M3 CPU based Microcontroller
         - 120 MHz maximum frequency producing 150 DMIPS/1.25 DMIPS/MHz
         - Memory Protection Unit
         - Flexible static memory controller (supports Compact Flash, SRAM, PSRAM, NOR, NAND memories)
@@ -1524,7 +1524,7 @@ the attribute \elem{Pname}. If the information is relevant to all processors, no
   </tr>
   <tr>
     <td>Dtz</td>
-    <td>Specifies whether an ARMv8-M based device implements TrustZone. Use predefined values as listed in the table \ref DtzEnum "Device TZ".</td>
+    <td>Specifies whether an Armv8-M based device implements TrustZone. Use predefined values as listed in the table \ref DtzEnum "Device TZ".</td>
     <td>DtzEnum</td>
     <td>required for ARMv8-M based devices</td>
   </tr>
@@ -1841,7 +1841,7 @@ The table lists the predefined Flash algorithm style. These values can be used i
   </tr>
   <tr>
     <td class="XML-Token">Keil</td>
-    <td>\ref flashAlgorithm as defined by ARM/Keil</td>
+    <td>\ref flashAlgorithm as defined by Arm/Keil</td>
   </tr>
   <tr>
     <td class="XML-Token">IAR</td>
@@ -1873,35 +1873,35 @@ These values can be used in the elements:
   </tr>
   <tr>
     <td class="XML-Token">Cortex-M0</td>
-    <td><a href="http://www.arm.com/products/processors/cortex-m/cortex-m0.php" target="_blank">ARM Cortex-M0</a> processor based device</td>
+    <td><a href="http://www.arm.com/products/processors/cortex-m/cortex-m0.php" target="_blank">Arm Cortex-M0</a> processor based device</td>
   </tr>
   <tr>
     <td class="XML-Token">Cortex-M0+</td>
-    <td><a href="http://www.arm.com/products/processors/cortex-m/cortex-m0plus.php" target="_blank">ARM Cortex-M0+</a> processor based device</td>
+    <td><a href="http://www.arm.com/products/processors/cortex-m/cortex-m0plus.php" target="_blank">Arm Cortex-M0+</a> processor based device</td>
   </tr>
   <tr>
     <td class="XML-Token">Cortex-M1</td>
-    <td><a href="http://www.arm.com/products/processors/cortex-m/cortex-m1.php" target="_blank">ARM Cortex-M1</a> processor based device</td>
+    <td><a href="http://www.arm.com/products/processors/cortex-m/cortex-m1.php" target="_blank">Arm Cortex-M1</a> processor based device</td>
   </tr>
   <tr>
     <td class="XML-Token">Cortex-M3</td>
-    <td><a href="http://www.arm.com/products/processors/cortex-m/cortex-m3.php" target="_blank">ARM Cortex-M3</a> processor based device</td>
+    <td><a href="http://www.arm.com/products/processors/cortex-m/cortex-m3.php" target="_blank">Arm Cortex-M3</a> processor based device</td>
   </tr>
   <tr>
     <td class="XML-Token">Cortex-M4</td>
-    <td><a href="http://www.arm.com/products/processors/cortex-m/cortex-m4-processor.php" target="_blank">ARM Cortex-M4</a> processor based device</td>
+    <td><a href="http://www.arm.com/products/processors/cortex-m/cortex-m4-processor.php" target="_blank">Arm Cortex-M4</a> processor based device</td>
   </tr>
   <tr>
     <td class="XML-Token">Cortex-M7</td>
-    <td><a href="http://www.arm.com/products/processors/cortex-m/cortex-m7-processor.php" target="_blank">ARM Cortex-M7</a> processor based device</td>
+    <td><a href="http://www.arm.com/products/processors/cortex-m/cortex-m7-processor.php" target="_blank">Arm Cortex-M7</a> processor based device</td>
   </tr>
   <tr>
     <td class="XML-Token">Cortex-M23</td>
-    <td><a href="http://www.arm.com/products/processors/cortex-m/cortex-m23-processor.php" target="_blank">ARM Cortex-M23</a> processor based device</td>
+    <td><a href="http://www.arm.com/products/processors/cortex-m/cortex-m23-processor.php" target="_blank">Arm Cortex-M23</a> processor based device</td>
   </tr>
   <tr>
     <td class="XML-Token">Cortex-M33</td>
-    <td><a href="http://www.arm.com/products/processors/cortex-m/cortex-m33-processor.php" target="_blank">ARM Cortex-M33</a> processor based device</td>
+    <td><a href="http://www.arm.com/products/processors/cortex-m/cortex-m33-processor.php" target="_blank">Arm Cortex-M33</a> processor based device</td>
   </tr>
   <tr>
     <td class="XML-Token">SC000</td>
@@ -1913,75 +1913,75 @@ These values can be used in the elements:
   </tr>
   <tr>
     <td class="XML-Token">ARMV8MBL</td>
-    <td>Processor <a href="http://www.arm.com/products/processors/instruction-set-architectures/armv8-m-architecture.php" target="_blank">ARMV8MBL</a> compliant with the ARMv8-M Baseline Architecture.</td>
+    <td>Processor <a href="http://www.arm.com/products/processors/instruction-set-architectures/armv8-m-architecture.php" target="_blank">ArmV8MBL</a> compliant with the Armv8-M Baseline Architecture.</td>
   </tr>
   <tr>
     <td class="XML-Token">ARMV8MML</td>
-    <td>Processor <a href="http://www.arm.com/products/processors/instruction-set-architectures/armv8-m-architecture.php" target="_blank">ARMV8MML</a> compliant with the ARMv8-M Mainline Architecture.</td>
+    <td>Processor <a href="http://www.arm.com/products/processors/instruction-set-architectures/armv8-m-architecture.php" target="_blank">ArmV8MML</a> compliant with the Armv8-M Mainline Architecture.</td>
   </tr>
   <tr>
     <td class="XML-Token">Cortex-R4</td>
-    <td><a href="http://www.arm.com/products/processors/cortex-r/cortex-r4.php" target="_blank">ARM Cortex-R4</a> processor based device</td>
+    <td><a href="http://www.arm.com/products/processors/cortex-r/cortex-r4.php" target="_blank">Arm Cortex-R4</a> processor based device</td>
   </tr>
   <tr>
     <td class="XML-Token">Cortex-R5</td>
-    <td><a href="http://www.arm.com/products/processors/cortex-r/cortex-r5.php" target="_blank">ARM Cortex-R5</a> processor based device</td>
+    <td><a href="http://www.arm.com/products/processors/cortex-r/cortex-r5.php" target="_blank">Arm Cortex-R5</a> processor based device</td>
   </tr>
   <tr>
     <td class="XML-Token">Cortex-R7</td>
-    <td><a href="http://www.arm.com/products/processors/cortex-r/cortex-r7.php" target="_blank">ARM Cortex-R7</a> processor based device</td>
+    <td><a href="http://www.arm.com/products/processors/cortex-r/cortex-r7.php" target="_blank">Arm Cortex-R7</a> processor based device</td>
   </tr>
   <tr>
     <td class="XML-Token">Cortex-R8</td>
-    <td><a href="http://www.arm.com/products/processors/cortex-r/cortex-r8.php" target="_blank">ARM Cortex-R8</a> processor based device</td>
+    <td><a href="http://www.arm.com/products/processors/cortex-r/cortex-r8.php" target="_blank">Arm Cortex-R8</a> processor based device</td>
   </tr>
   <tr>
     <td class="XML-Token">Cortex-A5</td>
-    <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a5.php" target="_blank">ARM Cortex-A5</a> processor based device</td>
+    <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a5.php" target="_blank">Arm Cortex-A5</a> processor based device</td>
   </tr>
   <tr>
     <td class="XML-Token">Cortex-A7</td>
-    <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a7.php" target="_blank">ARM Cortex-A7</a> processor based device</td>
+    <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a7.php" target="_blank">Arm Cortex-A7</a> processor based device</td>
   </tr>
   <tr>
     <td class="XML-Token">Cortex-A8</td>
-    <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a8.php" target="_blank">ARM Cortex-A8</a> processor based device</td>
+    <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a8.php" target="_blank">Arm Cortex-A8</a> processor based device</td>
   </tr>
   <tr>
     <td class="XML-Token">Cortex-A9</td>
-    <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a9.php" target="_blank">ARM Cortex-A9</a> processor based device</td>
+    <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a9.php" target="_blank">Arm Cortex-A9</a> processor based device</td>
   </tr>
   <tr>
     <td class="XML-Token">Cortex-A15</td>
-    <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a15.php" target="_blank">ARM Cortex-A15</a> processor based device</td>
+    <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a15.php" target="_blank">Arm Cortex-A15</a> processor based device</td>
   </tr>
   <tr>
     <td class="XML-Token">Cortex-A17</td>
-    <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a17.php" target="_blank">ARM Cortex-A17</a> processor based device</td>
+    <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a17.php" target="_blank">Arm Cortex-A17</a> processor based device</td>
   </tr>
   <tr>
     <td class="XML-Token">Cortex-A32</td>
-    <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a32.php" target="_blank">ARM Cortex-A32</a> processor based device</td>
+    <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a32.php" target="_blank">Arm Cortex-A32</a> processor based device</td>
   </tr>
   <tr>
     <td class="XML-Token">Cortex-A35</td>
-    <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a35.php" target="_blank">ARM Cortex-A35</a> processor based device</td>
+    <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a35.php" target="_blank">Arm Cortex-A35</a> processor based device</td>
   </tr>
   <tr>
     <td class="XML-Token">Cortex-A53</td>
-    <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a53.php" target="_blank">ARM Cortex-A53</a> processor based device</td>
+    <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a53.php" target="_blank">Arm Cortex-A53</a> processor based device</td>
   </tr>
   <tr>
     <td class="XML-Token">Cortex-A57</td>
-    <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a57.php" target="_blank">ARM Cortex-A57</a> processor based device</td>
+    <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a57.php" target="_blank">Arm Cortex-A57</a> processor based device</td>
   </tr>
   <tr>
     <td class="XML-Token">Cortex-A72</td>
-    <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a72.php" target="_blank">ARM Cortex-A72</a> processor based device</td>
+    <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a72.php" target="_blank">Arm Cortex-A72</a> processor based device</td>
   </tr>
   <tr>
     <td class="XML-Token">Cortex-A73</td>
-    <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a73.php" target="_blank">ARM Cortex-A73</a> processor based device</td>
+    <td><a href="http://www.arm.com/products/processors/cortex-a/cortex-a73.php" target="_blank">Arm Cortex-A73</a> processor based device</td>
   </tr>
   <tr>
     <td class="XML-Token">*</td>
@@ -2265,7 +2265,7 @@ The table lists the values for debug protocol types. The values can be used in
   <tr>
     <td class="XML-Token">swd</td>
     <td>
-      ARM Serial Wire Debug (SWD) protocol.
+      Arm Serial Wire Debug (SWD) protocol.
     </td>
   </tr>
   <tr>
@@ -2715,7 +2715,7 @@ detection.
 
 \section element_dp_swd /package/devices/family/.../debugport/swd
 
-Indicates availability of an ARM Serial Wire Debug (SWD) interface for the <b>debugport</b> parent element.
+Indicates availability of an Arm Serial Wire Debug (SWD) interface for the <b>debugport</b> parent element.
 Its attributes allow the manual override of SWD port characteristics as read from the target and provide
 information for the port selection in a system with multi-drop SWD support.
 

CMSIS/DoxyGen/Pack/src/pack_creation.txt

@@ -70,7 +70,7 @@ established classes:
 - Board Support: Generic interfaces for evaluation and development boards
 - CMSIS: <i>Cortex Microcontroller Software Interface Standard</i> components
 - CMSIS Driver: Unified device drivers compliant to the CMSIS-Driver specification
-- Compiler: ARM Compiler software extensions
+- Compiler: Arm Compiler software extensions
 - Data Exchange: Software components for data exchange
 - Device: Startup and system setup components
 - File System*: File drive support and file system

CMSIS/DoxyGen/Pack/src/pack_dfp.txt

@@ -237,7 +237,7 @@ Open the file MVCM3xxx.svd in the <b>Files\\SVD</b> directory in an editor and c
   <name>MVCM3xxx</name>                  <!-- name of part-->
   <series>MVCM3xxx</series>              <!-- device series the device belongs to -->
   <version>1.2</version>                 <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
-  <description>ARM 32-bit Cortex-M3 Microcontroller based device, CPU clock up to 100 MHz.</description>
+  <description>Arm 32-bit Cortex-M3 Microcontroller based device, CPU clock up to 100 MHz.</description>
 \endcode
 </li>
 <li>
@@ -250,7 +250,7 @@ C:\temp\working_dfp>SVDConv.exe Files\SVD\MVCM3xxx.svd --generate=header –-fie
 You should see some output of SVDConv similar to this:
 \verbatim
 CMSIS-SVD SVD Consistency Checker / Header File Generator V2.86g
-Copyright (C) 2010 - 2014 ARM Ltd and ARM Germany GmbH. All rights reserved.
+Copyright (C) 2010 - 2014 Arm Ltd and Arm Germany GmbH. All rights reserved.
 Options: "Files\SVD\MVCM3xxx.svd" --generate=header --fields=macro
 Reading file: "Files\SVD\MVCM3xxx.svd"
  

CMSIS/DoxyGen/Pack/src/pack_publish.txt

@@ -53,7 +53,7 @@ maintenance purposes for example).
 
 \section cp_KeilComPack Publishing on www.keil.com/pack
 
-ARM maintains a list of available software packs. If you wish to add your packs to that list, send either your vendor.pidx
+Arm maintains a list of available software packs. If you wish to add your packs to that list, send either your vendor.pidx
 file or your PDSC file to the following email address: <a href="mailto:CMSIS@arm.com">CMSIS@arm.com</a>. The PIDX file will
 be processed and all referenced PDSC files will be validated. The following content will be processed in order to generate
 the web site (<a href="http://www.keil.com/dd2/pack">www.keil.com/dd2/pack</a>) and index file

CMSIS/DoxyGen/Pack/src/pack_swcomponents.txt

@@ -290,7 +290,7 @@ Add the following code to the already existing <b>component</b>:
           <file category="library" condition="CM4_CM7" name="MySWComp/Lib/mylib_cm4.lib"/>
 \endcode
 Note that library files should always have a condition with regards to a specific C/C++ compiler. To accomplish this, each
-processor condition has the additional requirement for the ARM C/C++ compiler.
+processor condition has the additional requirement for the Arm C/C++ compiler.
 </li>
 <li>
 Add a new version number to the header of the PDSC file so that a Pack with a new version number will be created:

CMSIS/DoxyGen/Pack/src/pdsc_format.txt

@@ -42,7 +42,7 @@ is version independent and has the format:
 
 Example filenames for software packs:
 
-Software Pack for CMSIS Version 4.0 released by ARM.
+Software Pack for CMSIS Version 4.0 released by Arm.
  - <b>ARM.CMSIS.4.0.0.pack</b>: filename of the \ref cp_SWComponents "Software Pack".
  - <b>ARM.CMSIS.pdsc</b>: filename of the <b>Pack Description</b> (*.PDSC) file.
  
@@ -94,7 +94,7 @@ assists searching for packages.
 <package schemaVersion="1.4" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="PACK.xsd">
   <vendor>ExampleVendor</vendor>
   <name>STM32F2xx_DFP</name>                                                       <!-- name of package -->
-  <description>Device Family Package for STMicroelectronics STM32F2 Family of ARM Cortex-M3 based Microcontroller</description>
+  <description>Device Family Package for STMicroelectronics STM32F2 Family of Arm Cortex-M3 based Microcontroller</description>
   <url></url>
   <supportContact>http://www.arm.com/support</supportContact>
   <license>./END_USER_LICENCE_AGREEMENT.rtf</license>

CMSIS/DoxyGen/Pack/src/xml_types.txt

@@ -105,7 +105,7 @@ a related \refelem{sequence} element to be present. The other sequences should b
 executed when no sequence definition exists in the PDSC file.
 
 \note Default debug access sequences read the System Control Space (SCS) of the processor and assume that the SCS offset is
-implemented as defined in the ARMv6-M/ARMv7-M/ARMv8-M architecture reference manual.
+implemented as defined in the Armv6-M/Armv7-M/Armv8-M architecture reference manual.
 
 <table class="cmtable" summary="Enumeration: SequenceNameEnum">
   <tr>
@@ -115,7 +115,7 @@ implemented as defined in the ARMv6-M/ARMv7-M/ARMv8-M architecture reference man
   <tr>
     <td class="XML-Token">\ref debugPortSetup</td>
     <td>Prepare the target debug port for connection; is executed before acquiring access to the debug port.<br>
-	May include for example an SWJ-DP switch sequence as defined in the ARM Debug Interface (ADI) Architecture Specification.<br>
+	May include for example an SWJ-DP switch sequence as defined in the Arm Debug Interface (ADI) Architecture Specification.<br>
     <b>This sequence must not contain debug port/access port register and target memory accesses other than:</b>
     - <b>Reading the \em DPIDR debug port register to release an SWD connection from its line reset.</b>
     - <b>Writing the \em TARGETSEL debug port register (SWD protocol v2).</b>
@@ -418,7 +418,7 @@ Initialize core debug system.
   <sequence name="DebugCoreStart">
   
     <block>
-      // System Control Space (SCS) offset as defined in ARMv6-M/ARMv7-M.
+      // System Control Space (SCS) offset as defined in Armv6-M/Armv7-M.
     
       __var SCS_Addr   = 0xE000E000;
       __var DHCSR_Addr = SCS_Addr + 0xDF0;
@@ -439,7 +439,7 @@ Un-initialize core debug system.
   <sequence name="DebugCoreStop">
   
     <block>
-      // System Control Space (SCS) offset as defined in ARMv6-M/ARMv7-M.
+      // System Control Space (SCS) offset as defined in Armv6-M/Armv7-M.
       
       __var SCS_Addr   = 0xE000E000;
       __var DHCSR_Addr = SCS_Addr + 0xDF0;
@@ -465,7 +465,7 @@ Execute a system-wide reset via software mechanisms.
   <sequence name="ResetSystem">
   
     <block>
-      // System Control Space (SCS) offset as defined in ARMv6-M/ARMv7-M.
+      // System Control Space (SCS) offset as defined in Armv6-M/Armv7-M.
 
       __var SCS_Addr   = 0xE000E000;
       __var AIRCR_Addr = SCS_Addr + 0xD0C;
@@ -486,13 +486,13 @@ Execute a system-wide reset via software mechanisms.
 
 Execute a processor reset via software mechanisms.
 
-\note This Default Debug Access Sequence is empty for ARMv6-M and ARMv8-M based processors.
+\note This Default Debug Access Sequence is empty for Armv6-M and Armv8-M based processors.
 
 \code
   <sequence name="ResetProcessor">
   
     <block>
-      // System Control Space (SCS) offset as defined in ARMv7-M.
+      // System Control Space (SCS) offset as defined in Armv7-M.
 
       __var SCS_Addr   = 0xE000E000;
       __var AIRCR_Addr = SCS_Addr + 0xD0C;
@@ -604,7 +604,7 @@ Configure the target to stop code execution after a reset.
   
     <block>
       // System Control Space (SCS) offset as defined
-      // in ARMv6-M/ARMv7-M. Reimplement this sequence
+      // in Armv6-M/Armv7-M. Reimplement this sequence
       // if the SCS is located at a different offset.
 
       __var SCS_Addr   = 0xE000E000;
@@ -633,7 +633,7 @@ Free hardware resources allocated by ResetCatchSet.
   
     <block>
       // System Control Space (SCS) offset as defined
-      // in ARMv6-M/ARMv7-M. Reimplement this sequence
+      // in Armv6-M/Armv7-M. Reimplement this sequence
       // if the SCS is located at a different offset.
       
       __var SCS_Addr   = 0xE000E000;

CMSIS/DoxyGen/RTOS/src/cmsis_os.txt

@@ -1,5 +1,5 @@
 /* ----------------------------------------------------------------------  
-* Copyright (C) 2016 ARM Limited. All rights reserved.  
+* Copyright (C) 2016 Arm Limited. All rights reserved.  
 *  
 * $Date:        14. April 2016
 * $Revision:    1.02
@@ -132,7 +132,7 @@ The following files relevant to CMSIS-RTOS are present in the <b>ARM::CMSIS</b>
     <tr>
       <td>V4.81</td>
       <td>
-       Added provisions for ARM Compiler 6.\n
+       Added provisions for Arm Compiler 6.\n
        Corrected: Message Queue behavior when osMessagePut timed out due to full queue and osMessageGet was called from ISR.\n
       </td>
     </tr>
@@ -478,7 +478,7 @@ If this is impossible, the CMSIS-RTOS rejects calls by nested ISR functions with
 /**
 \page genRTOSIF Generic RTOS Interface
 
-The CMSIS-RTOS API is a generic RTOS interface for ARM&reg; Cortex&reg;-M processor-based devices. CMSIS-RTOS provides a
+The CMSIS-RTOS API is a generic RTOS interface for Arm&reg; Cortex&reg;-M processor-based devices. CMSIS-RTOS provides a
 standardized API for software components that require RTOS functionality and gives therefore serious benefits to the users
 and the software industry.
  - CMSIS-RTOS provides basic features that are required in many applications or technologies such as UML or Java (JVM).
@@ -541,7 +541,7 @@ towards the Cortex-M processors. Optional features may be for example
 /**
 \page rtosValidation RTOS Validation
 
-ARM offers a <a class=el href="http://www.keil.com/pack" target="_blank">Software Pack</a> for the CMSIS-RTOS Validation.
+Arm offers a <a class=el href="http://www.keil.com/pack" target="_blank">Software Pack</a> for the CMSIS-RTOS Validation.
 The <b>ARM::CMSIS-RTOS_Validation</b> Pack contains the following:
 
  - Source code of a CMSIS-RTOS Validation Suite along with configuration file.
@@ -1110,7 +1110,7 @@ The CMSIS-RTOS RTX kernel uses the following interrupts:
 - PendSV (request for system-level service) when calling certain RTX functions from \b Handler mode
 
 Interrupts can be used without limitation. Interrupt priority grouping can be used with some restrictions:
-- IRQ interrupts are never disabled by RTX Kernel for ARMv7-M architectures (Cortex-M3/M4/M7).
+- IRQ interrupts are never disabled by RTX Kernel for Armv7-M architectures (Cortex-M3/M4/M7).
 - Software interrupt 0 is used by RTX and cannot be used in an application.
 - RTX uses its own SVC Handler which is automatically linked from the library. \ref svcFunctions explains how to use a custom
   SVC table.

CMSIS/DoxyGen/RTOS2/src/cmsis_os2.txt

@@ -2,7 +2,7 @@
 /**
 \mainpage
 
-The <b>CMSIS-RTOS API Version 2 (CMSIS-RTOS2)</b> is a generic RTOS interface for ARM&reg; Cortex&reg;-M processor-based
+The <b>CMSIS-RTOS API Version 2 (CMSIS-RTOS2)</b> is a generic RTOS interface for Arm&reg; Cortex&reg;-M processor-based
 devices. It provides a standardized API for software components that require RTOS functionality and gives therefore serious
 benefits to the users and the software industry:
  - CMSIS-RTOS2 provides basic features that are required in many applications.
@@ -26,7 +26,7 @@ memory management, and message exchange between threads with time limits.
 
 The CMSIS-RTOS2 addresses the following new requirements:
  - Dynamic object creation no longer requires static memory, static memory buffers are now optional.
- - Support for ARMv8-M architecture that provides a secure and non-secure state of code execution.
+ - Support for Armv8-M architecture that provides a secure and non-secure state of code execution.
  - Provisions for message passing in multi-core systems.
  - Full support of C++ run-time environments.
  - C interface which is binary compatible across
@@ -266,7 +266,7 @@ different and optimized in various aspects towards the Cortex-M processors. Opti
  - Deterministic context switching.
  - Round-robin context switching.
  - Deadlock avoidance, for example with priority inversion.
- - Zero interrupt latency by using ARMv7-M instructions LDREX and STREX.
+ - Zero interrupt latency by using Armv7-M instructions LDREX and STREX.
  
 \section usingOS2 Using a CMSIS-RTOS2 Implementation
 
@@ -338,7 +338,7 @@ modifications when using on a different CMSIS-RTOS2 implementation.
 /**
 \page rtx5_impl RTX v5 Implementation
 
-Keil RTX version 5 (RTX5) implements the CMSIS-RTOS2 as a native RTOS interface for ARM Cortex-M processor-based devices.
+Keil RTX version 5 (RTX5) implements the CMSIS-RTOS2 as a native RTOS interface for Arm Cortex-M processor-based devices.
 A translation layer to CMSIS-RTOS API v1 is provided. Therefore, RTX5 can be used in applications that where previously based
 on RTX version 4 and CMSIS-RTOS version 1 with minimal effort.
 
@@ -389,9 +389,9 @@ implementations.
 \image html manage_rte_cortex-a.png
 
 The default implementations provided along with CMSIS are 
-- ARM <a href="../../Core_A/html/group__GIC__functions.html">Generic Interrupt Controller (GIC)</a>
-- ARM Cortex-A5, Cortex-A9 <a href="../../Core_A/html/group__PTM__timer__functions.html">Private Timer (PTIM)</a>
-- ARM Cortex-A7 <a href="../../Core_A/html/group__PL1__timer__functions.html">Generic Physical Timer (GTIM)</a>
+- Arm <a href="../../Core_A/html/group__GIC__functions.html">Generic Interrupt Controller (GIC)</a>
+- Arm Cortex-A5, Cortex-A9 <a href="../../Core_A/html/group__PTM__timer__functions.html">Private Timer (PTIM)</a>
+- Arm Cortex-A7 <a href="../../Core_A/html/group__PL1__timer__functions.html">Generic Physical Timer (GTIM)</a>
 
 For devices not implementing GIC, PTIM nor GTIM please refer to the according device family pack and select the
 proper implementations.
@@ -742,7 +742,7 @@ void osRtxIdleThread (void) {
 \endcode
 
 \note
-\c __WFE() is not available in every ARM Cortex-M implementation. Check device manuals for availability. 
+\c __WFE() is not available in every Arm Cortex-M implementation. Check device manuals for availability. 
 The alternative using \c __WFI() has other issues, please take note of http://www.keil.com/support/docs/3591.htm as well.
 
 \section rtx_os_h RTX5 Header File
@@ -1079,7 +1079,7 @@ a reference for building the RTX5 libraries using a tool-chain of your choice.
 -# From the <b>Project</b> window you find the list of source files required for a complete library build.
 -# Build the library of your choice using \b Project - \b Build \b Target (or press F7).
 
-\image html own_lib_projwin.png "Project with files for ARMv8-M Mainline"
+\image html own_lib_projwin.png "Project with files for Armv8-M Mainline"
 */
 
 
@@ -1145,7 +1145,7 @@ The CMSIS-RTOS RTX v5 is delivered in source code and several examples are provi
 \section libFiles RTX v5 Library Files
 
 The CMSIS-RTOS RTX Library is available pre-compiled for ARMCC and GCC compilers and supports all Cortex-M
-processor variants in every configuration, including ARM Cortex-M23 and Cortex-M33.
+processor variants in every configuration, including Arm Cortex-M23 and Cortex-M33.
 
 <table class="cmtable" summary="CMSIS-RTOS RTX Library Files">
     <tr>
@@ -1166,27 +1166,27 @@ processor variants in every configuration, including ARM Cortex-M23 and Cortex-M
     </tr>
     <tr>
       <td>Library/ARM/RTX_V8MB.lib</td>
-      <td>CMSIS-RTOS RTX Library for ARMCC Compiler, ARMv8-M baseline.</td>
+      <td>CMSIS-RTOS RTX Library for ARMCC Compiler, Armv8-M Baseline.</td>
     </tr>
     <tr>
       <td>Library/ARM/RTX_V8MBN.lib</td>
-      <td>CMSIS-RTOS RTX Library for ARMCC Compiler, ARMv8-M baseline, non-secure.</td>
+      <td>CMSIS-RTOS RTX Library for ARMCC Compiler, Armv8-M Baseline, non-secure.</td>
     </tr>
     <tr>
       <td>Library/ARM/RTX_V8MM.lib</td>
-      <td>CMSIS-RTOS RTX Library for ARMCC Compiler, ARMv8-M mainline.</td>
+      <td>CMSIS-RTOS RTX Library for ARMCC Compiler, Armv8-M Mainline.</td>
     </tr>
     <tr>
       <td>Library/ARM/RTX_V8MMF.lib</td>
-      <td>CMSIS-RTOS RTX Library for ARMCC Compiler, ARMv8-M mainline with FPU.</td>
+      <td>CMSIS-RTOS RTX Library for ARMCC Compiler, Armv8-M Mainline with FPU.</td>
     </tr>
     <tr>
       <td>Library/ARM/RTX_V8MMFN.lib</td>
-      <td>CMSIS-RTOS RTX Library for ARMCC Compiler, ARMv8-M mainline with FPU, non-secure.</td>
+      <td>CMSIS-RTOS RTX Library for ARMCC Compiler, Armv8-M Mainline with FPU, non-secure.</td>
     </tr>
     <tr>
       <td>Library/ARM/RTX_V8MMN.lib</td>
-      <td>CMSIS-RTOS RTX Library for ARMCC Compiler, ARMv8-M mainline, non-secure.</td>
+      <td>CMSIS-RTOS RTX Library for ARMCC Compiler, Armv8-M Mainline, non-secure.</td>
     </tr>
     <tr>
       <td>Library/GCC/libRTX_CM0.a</td>
@@ -1202,27 +1202,27 @@ processor variants in every configuration, including ARM Cortex-M23 and Cortex-M
     </tr>
     <tr>
       <td>Library/GCC/libRTX_V8MB.a</td>
-      <td>CMSIS-RTOS libRTX Library for GCC Compiler, ARMv8-M baseline.</td>
+      <td>CMSIS-RTOS libRTX Library for GCC Compiler, Armv8-M Baseline.</td>
     </tr>
     <tr>
       <td>Library/GCC/libRTX_V8MBN.a</td>
-      <td>CMSIS-RTOS libRTX Library for GCC Compiler, ARMv8-M baseline, non-secure.</td>
+      <td>CMSIS-RTOS libRTX Library for GCC Compiler, Armv8-M Baseline, non-secure.</td>
     </tr>
     <tr>
       <td>Library/GCC/libRTX_V8MM.a</td>
-      <td>CMSIS-RTOS libRTX Library for GCC Compiler, ARMv8-M mainline.</td>
+      <td>CMSIS-RTOS libRTX Library for GCC Compiler, Armv8-M Mainline.</td>
     </tr>
     <tr>
       <td>Library/GCC/libRTX_V8MMF.a</td>
-      <td>CMSIS-RTOS libRTX Library for GCC Compiler, ARMv8-M mainline with FPU.</td>
+      <td>CMSIS-RTOS libRTX Library for GCC Compiler, Armv8-M Mainline with FPU.</td>
     </tr>
     <tr>
       <td>Library/GCC/libRTX_V8MMFN.a</td>
-      <td>CMSIS-RTOS libRTX Library for GCC Compiler, ARMv8-M mainline with FPU, non-secure.</td>
+      <td>CMSIS-RTOS libRTX Library for GCC Compiler, Armv8-M Mainline with FPU, non-secure.</td>
     </tr>
     <tr>
       <td>Library/GCC/libRTX_V8MMN.a</td>
-      <td>CMSIS-RTOS libRTX Library for GCC Compiler, ARMv8-M mainline, non-secure.</td>
+      <td>CMSIS-RTOS libRTX Library for GCC Compiler, Armv8-M Mainline, non-secure.</td>
     </tr>
 </table>
 */
@@ -1235,14 +1235,14 @@ processor variants in every configuration, including ARM Cortex-M23 and Cortex-M
 
 Keil RTX5 is developed and tested using the common toolchains and development environments.
 
-\subsection technicalData_Toolchain_ARM ARM Compiler (ARM/Keil MDK, uVision5)
+\subsection technicalData_Toolchain_ARM Arm Compiler (Arm/Keil MDK, uVision5)
 
-Major parts of RTX5 are developed and optimized using ARM Compiler and ARM/Keil MDK.
+Major parts of RTX5 are developed and optimized using Arm Compiler and Arm/Keil MDK.
 The current release is tested with the following versions:
 <ul>
- <li>ARM Compiler 5.06 Update 6</li>
- <li>ARM Compiler 6.6.2 (Long Term Maintenance)</li>
- <li>ARM Compiler 6.9</li>
+ <li>Arm Compiler 5.06 Update 6</li>
+ <li>Arm Compiler 6.6.2 (Long Term Maintenance)</li>
+ <li>Arm Compiler 6.9</li>
  <li>RTOS-aware debugging with uVision 5.24</li>
 </ul>
 
@@ -1260,7 +1260,7 @@ RTX5 has been ported to fully support IAR Embedded Workbench. The following rele
 RTX5 has also been ported to support GCC, maintenance mainly relays on community contribution.
 Active development is currently tested with:
 <ul>
- <li>GNU Tools for ARM Embedded 6.3.1 20170620</li>
+ <li>GNU Tools for Arm Embedded 6.3.1 20170620</li>
 </ul>
 
 \section technicalData5_ControlBlockSizes Control Block Sizes
@@ -1727,7 +1727,7 @@ The functions that call the Event Recorder are in the module \em rtx_evr.c and t
 /**
 \page rtosValidation RTOS Validation
 
-ARM offers a <a class=el href="http://www.keil.com/pack" target="_blank">Software Pack</a> for the CMSIS-RTOS Validation.
+Arm offers a <a class=el href="http://www.keil.com/pack" target="_blank">Software Pack</a> for the CMSIS-RTOS Validation.
 The <b>ARM::CMSIS-RTOS_Validation</b> Pack contains the following:
 
  - Source code of a CMSIS-RTOS Validation Suite along with configuration file.
@@ -1783,7 +1783,7 @@ Test Result: PASSED
 \page functionOverview Function Overview
 
 CMSIS-RTOS v2 provides multiple API interfaces:
-  - \subpage rtos_api2 is the new C function API that supports dynamic object creation and ARMv8-M (ARM Cortex-M23 and
+  - \subpage rtos_api2 is the new C function API that supports dynamic object creation and Armv8-M (Arm Cortex-M23 and
     Cortex-M33).
   - <a class="el" href="../../RTOS/html/functionOverview.html">CMSIS-RTOS C API v1</a> is a C function API that is backward
     compatible with CMSIS-RTOS v1.

CMSIS/DoxyGen/SVD/src/svd.txt

@@ -4,7 +4,7 @@
 Introduction
 ------------
 The CMSIS System View Description format(CMSIS-SVD) formalizes the description of the system
-contained in ARM Cortex-M processor-based microcontrollers, in particular, the memory mapped
+contained in Arm Cortex-M processor-based microcontrollers, in particular, the memory mapped
 registers of peripherals.
 The detail contained in system view descriptions is comparable to the data in device 
 reference manuals. The information ranges from high level functional 
@@ -233,7 +233,7 @@ SVDConv.exe <SVD_file> <options>
   </tr>
   <tr>
     <td> \-\-generate=partition </td>
-    <td>Generate Partition file for Cortex-M Security Extensions (ARMv8M)</td>
+    <td>Generate Partition file for Cortex-M Security Extensions (Armv8-M)</td>
     <td>Generates the device partition file. The name of the generated file is composed of <em>partition_</em> and the value of the device <em>\<name></em>
     (for example, <em>partition_CMSDK_ARMv8MBL.h</em>).
     Refer to \ref elem_device. The content of the file uses Configuration Wizard annotations and is derived 

CMSIS/DoxyGen/SVD/src/svd_schema.txt

@@ -51,11 +51,11 @@ The element \tagem{device} provides the outermost frame of the description.
   <name>ARM_Cortex_M4</name>
   <series>ARMCM4</series>
   <version>0.1</version>
-  <description>ARM Cortex-M4 based Microcontroller demonstration device</description>
+  <description>Arm Cortex-M4 based Microcontroller demonstration device</description>
   <licenseText>
-    ARM Limited (ARM) is supplying this software for use with Cortex-M \n
+    Arm Limited (Arm) is supplying this software for use with Cortex-M \n
     processor based microcontrollers.  This file can be freely distributed \n
-    within development tools that are supporting such ARM based processors. \n
+    within development tools that are supporting such Arm based processors. \n
     \n
     THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED \n
     OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF \n
@@ -80,7 +80,7 @@ The element \tagem{device} provides the outermost frame of the description.
 
 This example describes a device from the vendor \token{ARM Ltd.} using \token{ARM} as short name. 
 The device belongs to the device family \token{ARMCM4}. The device description is at version \token{0.1} and uniquely identifies the device by the name \token{ARM_Cortex_M4}. The legal disclaimer in the header files generated from
-this description is captured and formatted in accordance to the standard ARM CMSIS disclaimer. The CMSIS system file included by the
+this description is captured and formatted in accordance to the standard Arm CMSIS disclaimer. The CMSIS system file included by the
 generated device header file is named \token{system_ARMCM4.h} and all type definitions will be prepended with \token{ARM_}.
 
 The peripherals are memory mapped in a byte-addressable address space with a bus width of \token{32} bits. 
@@ -305,7 +305,7 @@ This example describes a device based on a \token{Cortex-M7} core of HW revision
 with fixed \token{little} endian memory scheme, including \token{Memory Protection Unit} and 
 \token{double precision hardware Floating Point Unit}. It has a \token{data cache} and no \token{instruction} nor
 a tightly coupled memory. The Nested Vectored Interrupt Controller uses \token{4} bits 
-to configure the priority of an interrupt. It is equipped with the standard System Tick Timer as defined by ARM.
+to configure the priority of an interrupt. It is equipped with the standard System Tick Timer as defined by Arm.
 
 \anchor elem_cpu_sc
 \b  /device/cpu
@@ -327,26 +327,26 @@ to configure the priority of an interrupt. It is equipped with the standard Syst
     <tr>
         <td>name</td>
         <td>The predefined tokens are:
-        - \token{CM0}: ARM Cortex-M0 
-        - \token{CM0PLUS}: ARM Cortex-M0+
-        - \token{CM0+}: ARM Cortex-M0+
-        - \token{CM1}: ARM Cortex-M1 
-        - \token{SC000}: ARM Secure Core SC000
-        - \token{CM23}: ARM Cortex-M23
-        - \token{CM3}: ARM Cortex-M3
-        - \token{CM33}: ARM Cortex-M33
-        - \token{SC300}: ARM Secure Core SC300
-        - \token{CM4}: ARM Cortex-M4
-        - \token{CM7}: ARM Cortex-M7
-        - \token{CA5}: ARM Cortex-A5
-        - \token{CA7}: ARM Cortex-A7
-        - \token{CA8}: ARM Cortex-A8
-        - \token{CA9}: ARM Cortex-A9
-        - \token{CA15}: ARM Cortex-A15
-        - \token{CA17}: ARM Cortex-A17
-        - \token{CA53}: ARM Cortex-A53
-        - \token{CA57}: ARM Cortex-A57
-        - \token{CA72}: ARM Cortex-A72
+        - \token{CM0}: Arm Cortex-M0 
+        - \token{CM0PLUS}: Arm Cortex-M0+
+        - \token{CM0+}: Arm Cortex-M0+
+        - \token{CM1}: Arm Cortex-M1 
+        - \token{SC000}: Arm Secure Core SC000
+        - \token{CM23}: Arm Cortex-M23
+        - \token{CM3}: Arm Cortex-M3
+        - \token{CM33}: Arm Cortex-M33
+        - \token{SC300}: Arm Secure Core SC300
+        - \token{CM4}: Arm Cortex-M4
+        - \token{CM7}: Arm Cortex-M7
+        - \token{CA5}: Arm Cortex-A5
+        - \token{CA7}: Arm Cortex-A7
+        - \token{CA8}: Arm Cortex-A8
+        - \token{CA9}: Arm Cortex-A9
+        - \token{CA15}: Arm Cortex-A15
+        - \token{CA17}: Arm Cortex-A17
+        - \token{CA53}: Arm Cortex-A53
+        - \token{CA57}: Arm Cortex-A57
+        - \token{CA72}: Arm Cortex-A72
         - \token{other}: other processor architectures
         </td>
         <td>cpuNameType </td>
@@ -360,11 +360,11 @@ to configure the priority of an interrupt. It is equipped with the standard Syst
     </tr>
     <tr>
         <td>endian </td>
-        <td>Define the endianess of the processor being one of:
+        <td>Define the endianness of the processor being one of:
          - \token{little}: little endian memory (least significant byte gets allocated at the lowest address).
          - \token{big}: byte invariant big endian data organization (most significant byte gets allocated at the lowest address).
          - \token{selectable}: little and big endian are configurable for the device and become active after the next reset.
-         - \token{other}: the endianess is neither little nor big endian.
+         - \token{other}: the endianness is neither little nor big endian.
         </td>
         <td>endianType </td>
         <td>1..1 </td>
@@ -428,7 +428,7 @@ to configure the priority of an interrupt. It is equipped with the standard Syst
     </tr>
     <tr>
         <td>vendorSystickConfig</td>
-        <td>Indicate whether the processor implements a vendor-specific System Tick Timer. If \token{false}, then the ARM-defined System Tick Timer is available. If \token{true}, then a vendor-specific System Tick Timer must be implemented. This tag is either set to \token{true} or \token{false}, \token{1} or \token{0}.</td>
+        <td>Indicate whether the processor implements a vendor-specific System Tick Timer. If \token{false}, then the Arm-defined System Tick Timer is available. If \token{true}, then a vendor-specific System Tick Timer must be implemented. This tag is either set to \token{true} or \token{false}, \token{1} or \token{0}.</td>
         <td>boolean </td>
         <td>1..1 </td>
     </tr>
@@ -2295,7 +2295,7 @@ Special requirements are described on the level where the element occurs. Click
 <device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
   <name>ARM_Cortex_M3</name>
   <version>0.1</version>
-  <description>ARM Cortex-M3 based Microcontroller demonstration device</description>
+  <description>Arm Cortex-M3 based Microcontroller demonstration device</description>
   <addressUnitBits>8</addressUnitBits>
   <width>32</width>
   <size>32</size>

CMSIS/DoxyGen/Zone/src/XML_Format.txt

@@ -174,7 +174,7 @@ The <b>system</b> element is the root element of a CMSIS-Zone system definition.
 \code
 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
 <system xmlns:xs="http://www.w3.org/2001/XMLSchema-instance">
-  <!-- ARM SoC with Cortex-M4 processor -->
+  <!-- Arm SoC with Cortex-M4 processor -->
   <device Dname="ARM32CM4128x">
     <processor Pname="Cortex-M4">
       :
@@ -503,13 +503,13 @@ The <b>processor</b> element is used to define the processing elements integrati
   </tr>
   <tr>
     <td>Dtz</td>
-    <td>Specifies whether an ARMv8M based device implements TrustZone.</td>
+    <td>Specifies whether an Armv8-M based device implements TrustZone.</td>
     <td>DtzEnum</td>
     <td>optional</td>
   </tr>
   <tr>
     <td>Ddsp</td>
-    <td>Specifies whether an ARMv8M based device supports the DSP instructions set.</td>
+    <td>Specifies whether an Armv8-M based device supports the DSP instructions set.</td>
     <td>DdspEnum</td>
     <td>optional</td>
   </tr>

CMSIS/Driver/DriverTemplates/Driver_CAN.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2015-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *

CMSIS/Driver/DriverTemplates/Driver_ETH_MAC.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *

CMSIS/Driver/DriverTemplates/Driver_ETH_PHY.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *

CMSIS/Driver/DriverTemplates/Driver_Flash.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *

CMSIS/Driver/DriverTemplates/Driver_I2C.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *

CMSIS/Driver/DriverTemplates/Driver_MCI.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *

CMSIS/Driver/DriverTemplates/Driver_SAI.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *

CMSIS/Driver/DriverTemplates/Driver_SPI.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *

CMSIS/Driver/DriverTemplates/Driver_Storage.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *

CMSIS/Driver/DriverTemplates/Driver_USART.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *

CMSIS/Driver/DriverTemplates/Driver_USBD.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *

CMSIS/Driver/DriverTemplates/Driver_USBH.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *

CMSIS/RTOS2/RTX/Config/handlers.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2018 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -124,17 +124,17 @@ void CPAbtHandler(uint32_t IFSR, uint32_t IFAR, uint32_t LR) {
 //returns amount to decrement lr by
 //this will be 0 when we have emulated the instruction and want to execute the next instruction
 //this will be 2 when we have performed some maintenance and want to retry the instruction in Thumb (state == 2)
-//this will be 4 when we have performed some maintenance and want to retry the instruction in ARM   (state == 4)
+//this will be 4 when we have performed some maintenance and want to retry the instruction in Arm   (state == 4)
 uint32_t CUndefHandler(uint32_t opcode, uint32_t state, uint32_t LR) {
     const uint32_t THUMB = 2U;
     const uint32_t ARM = 4U;
     (void)LR;
     //Lazy VFP/NEON initialisation and switching
 
-    // (ARM ARM section A7.5) VFP data processing instruction?
-    // (ARM ARM section A7.6) VFP/NEON register load/store instruction?
-    // (ARM ARM section A7.8) VFP/NEON register data transfer instruction?
-    // (ARM ARM section A7.9) VFP/NEON 64-bit register data transfer instruction?
+    // (Arm Architecture Reference Manual section A7.5) VFP data processing instruction?
+    // (Arm Architecture Reference Manual section A7.6) VFP/NEON register load/store instruction?
+    // (Arm Architecture Reference Manual section A7.8) VFP/NEON register data transfer instruction?
+    // (Arm Architecture Reference Manual section A7.9) VFP/NEON 64-bit register data transfer instruction?
     if ((state == ARM   && ((opcode & 0x0C000000U) >> 26U == 0x03U)) ||
         (state == THUMB && ((opcode & 0xEC000000U) >> 26U == 0x3BU))) {
         if (((opcode & 0x00000E00U) >> 9U) == 5U) {
@@ -143,10 +143,10 @@ uint32_t CUndefHandler(uint32_t opcode, uint32_t state, uint32_t LR) {
         }
     }
 
-    // (ARM ARM section A7.4) NEON data processing instruction?
+    // (Arm Architecture Reference Manual section A7.4) NEON data processing instruction?
     if ((state == ARM   && ((opcode & 0xFE000000U) >> 24U == 0xF2U)) ||
         (state == THUMB && ((opcode & 0xEF000000U) >> 24U == 0xEFU)) ||
-    // (ARM ARM section A7.7) NEON load/store instruction?
+    // (Arm Architecture Reference Manual section A7.7) NEON load/store instruction?
         (state == ARM   && ((opcode >> 24U) == 0xF4U)) ||
         (state == THUMB && ((opcode >> 24U) == 0xF9U))) {
             __FPU_Enable();

CMSIS/RTOS2/RTX/Source/rtx_core_c.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2018 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -36,7 +36,7 @@
      (!defined(__ARM_ARCH_7EM__))     && \
      (!defined(__ARM_ARCH_8M_BASE__)) && \
      (!defined(__ARM_ARCH_8M_MAIN__)))
-#error "Unknown ARM Architecture!"
+#error "Unknown Arm Architecture!"
 #endif
 
 #if   (defined(__ARM_ARCH_7A__) && (__ARM_ARCH_7A__ != 0))

CMSIS/RTOS2/RTX/Source/rtx_core_ca.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2018 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -52,7 +52,7 @@ typedef bool bool_t;
 
 /// xPSR_Initialization Value
 /// \param[in]  privileged      true=privileged, false=unprivileged
-/// \param[in]  thumb           true=Thumb, false=ARM
+/// \param[in]  thumb           true=Thumb, false=Arm
 /// \return                     xPSR Init Value
 __STATIC_INLINE uint32_t xPSR_InitVal (bool_t privileged, bool_t thumb) {
   uint32_t psr;

CMSIS/RTOS2/RTX/Source/rtx_core_cm.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2018 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *

CMSIS/RTOS2/RTX/Source/rtx_delay.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2018 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *

CMSIS/RTOS2/RTX/Source/rtx_evflags.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2018 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *

CMSIS/RTOS2/RTX/Source/rtx_evr.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2018 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *

CMSIS/RTOS2/RTX/Source/rtx_kernel.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2018 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *

CMSIS/RTOS2/RTX/Source/rtx_lib.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2018 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *