CMSIS-Core(A): Enhanced documentation for cache access maintenance.

CMSIS/Core_A/Include/cmsis_armcc.h

@@ -340,7 +340,7 @@ __STATIC_INLINE __ASM void __set_mode(uint32_t mode) {
   BX   r1
 }
 
-/** \brief  Set Stack Pointer
+/** \brief  Set Stack Pointer 
     \param [in]    stack  Stack Pointer value to set
  */
 __STATIC_INLINE __ASM void __set_SP(uint32_t stack)
@@ -366,7 +366,7 @@ __STATIC_INLINE __ASM void __set_SP_usr(uint32_t topOfProcStack)
   BX      LR
 }
 
-/** \brief  Get FPEXC
+/** \brief  Get FPEXC register
     \return               Floating Point Exception Control register value
  */
 __STATIC_INLINE uint32_t __get_FPEXC(void)
@@ -379,7 +379,7 @@ __STATIC_INLINE uint32_t __get_FPEXC(void)
 #endif
 }
 
-/** \brief  Set FPEXC
+/** \brief  Set FPEXC register
     \param [in]    fpexc  Floating Point Exception Control value to set
  */
 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
@@ -390,7 +390,7 @@ __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
 #endif
 }
 
-/** \brief  Get ACTLR
+/** \brief  Get ACTLR register
     \return               Auxiliary Control register value
  */
 __STATIC_INLINE uint32_t __get_ACTLR(void)
@@ -399,7 +399,7 @@ __STATIC_INLINE uint32_t __get_ACTLR(void)
   return __regACTLR;
 }
 
-/** \brief  Set ACTLR
+/** \brief  Set ACTLR register
     \param [in]    actlr  Auxiliary Control value to set
  */
 __STATIC_INLINE void __set_ACTLR(uint32_t actlr)
@@ -408,7 +408,7 @@ __STATIC_INLINE void __set_ACTLR(uint32_t actlr)
   __regACTLR = actlr;
 }
 
-/** \brief  Get CPACR
+/** \brief  Get CPACR register
     \return               Coprocessor Access Control register value
  */
 __STATIC_INLINE uint32_t __get_CPACR(void)
@@ -417,7 +417,7 @@ __STATIC_INLINE uint32_t __get_CPACR(void)
   return __regCPACR;
 }
 
-/** \brief  Set CPACR
+/** \brief  Set CPACR register
     \param [in]    cpacr  Coprocessor Access Control value to set
  */
 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
@@ -426,7 +426,7 @@ __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
   __regCPACR = cpacr;
 }
 
-/** \brief  Get CBAR
+/** \brief  Get CBAR register
     \return               Configuration Base Address register value
  */
 __STATIC_INLINE uint32_t __get_CBAR() {
@@ -434,7 +434,7 @@ __STATIC_INLINE uint32_t __get_CBAR() {
   return(__regCBAR);
 }
 
-/** \brief  Get TTBR0
+/** \brief  Get TTBR0 register
 
     This function returns the value of the Translation Table Base Register 0.
 
@@ -445,7 +445,7 @@ __STATIC_INLINE uint32_t __get_TTBR0() {
   return(__regTTBR0);
 }
 
-/** \brief  Set TTBR0
+/** \brief  Set TTBR0 register
 
     This function assigns the given value to the Translation Table Base Register 0.
 
@@ -456,7 +456,7 @@ __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
   __regTTBR0 = ttbr0;
 }
 
-/** \brief  Get DACR
+/** \brief  Get DACR register
 
     This function returns the value of the Domain Access Control Register.
 
@@ -467,7 +467,7 @@ __STATIC_INLINE uint32_t __get_DACR() {
   return(__regDACR);
 }
 
-/** \brief  Set DACR
+/** \brief  Set DACR register
 
     This function assigns the given value to the Domain Access Control Register.
 
@@ -478,10 +478,7 @@ __STATIC_INLINE void __set_DACR(uint32_t dacr) {
   __regDACR = dacr;
 }
 
-/** \brief  Set SCTLR
-
-    This function assigns the given value to the System Control Register.
-
+/** \brief  Set the \ref CMSIS_SCTLR "System Control Register" register.
     \param [in]    sctlr  System Control Register value to set
  */
 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
@@ -490,7 +487,7 @@ __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
   __regSCTLR = sctlr;
 }
 
-/** \brief  Get SCTLR
+/** \brief  Get SCTLR register
     \return               System Control Register value
  */
 __STATIC_INLINE uint32_t __get_SCTLR() {
@@ -498,7 +495,7 @@ __STATIC_INLINE uint32_t __get_SCTLR() {
   return(__regSCTLR);
 }
 
-/** \brief  Set ACTRL
+/** \brief  Set ACTRL register
     \param [in]    actrl  Auxiliary Control Register value to set
  */
 __STATIC_INLINE void __set_ACTRL(uint32_t actrl)
@@ -507,7 +504,7 @@ __STATIC_INLINE void __set_ACTRL(uint32_t actrl)
   __regACTRL = actrl;
 }
 
-/** \brief  Get ACTRL
+/** \brief  Get ACTRL register
     \return               Auxiliary Control Register value
  */
 __STATIC_INLINE uint32_t __get_ACTRL(void)
@@ -516,10 +513,7 @@ __STATIC_INLINE uint32_t __get_ACTRL(void)
   return(__regACTRL);
 }
 
-/** \brief  Get MPIDR
-
-    This function returns the value of the Multiprocessor Affinity Register.
-
+/** \brief  Get MPIDR register
     \return               Multiprocessor Affinity Register value
  */
 __STATIC_INLINE uint32_t __get_MPIDR(void)
@@ -528,10 +522,7 @@ __STATIC_INLINE uint32_t __get_MPIDR(void)
   return(__regMPIDR);
 }
 
- /** \brief  Get VBAR
-
-    This function returns the value of the Vector Base Address Register.
-
+ /** \brief  Get VBAR register
     \return               Vector Base Address Register
  */
 __STATIC_INLINE uint32_t __get_VBAR(void)
@@ -540,10 +531,7 @@ __STATIC_INLINE uint32_t __get_VBAR(void)
   return(__regVBAR);
 }
 
-/** \brief  Set VBAR
-
-    This function assigns the given value to the Vector Base Address Register.
-
+/** \brief  Set VBAR register
     \param [in]    vbar  Vector Base Address Register value to set
  */
 __STATIC_INLINE void __set_VBAR(uint32_t vbar)
@@ -552,10 +540,7 @@ __STATIC_INLINE void __set_VBAR(uint32_t vbar)
   __regVBAR = vbar;
 }
 
-/** \brief  Set CNTFRQ
-
-  This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ).
-
+/** \brief  Set CNTFRQ register
   \param [in]    value  CNTFRQ Register value to set
 */
 __STATIC_INLINE void __set_CNTFRQ(uint32_t value) {
@@ -563,10 +548,7 @@ __STATIC_INLINE void __set_CNTFRQ(uint32_t value) {
   __regCNTFRQ = value;
 }
 
-/** \brief  Set CNTP_TVAL
-
-  This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL).
-
+/** \brief  Set CNTP_TVAL register
   \param [in]    value  CNTP_TVAL Register value to set
 */
 __STATIC_INLINE void __set_CNTP_TVAL(uint32_t value) {
@@ -574,10 +556,7 @@ __STATIC_INLINE void __set_CNTP_TVAL(uint32_t value) {
   __regCNTP_TVAL = value;
 }
 
-/** \brief  Get CNTP_TVAL
-
-    This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL).
-
+/** \brief  Get CNTP_TVAL register
     \return               CNTP_TVAL Register value
  */
 __STATIC_INLINE uint32_t __get_CNTP_TVAL() {
@@ -585,10 +564,7 @@ __STATIC_INLINE uint32_t __get_CNTP_TVAL() {
   return(__regCNTP_TVAL);
 }
 
-/** \brief  Set CNTP_CTL
-
-  This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL).
-
+/** \brief  Set CNTP_CTL register
   \param [in]    value  CNTP_CTL Register value to set
 */
 __STATIC_INLINE void __set_CNTP_CTL(uint32_t value) {
@@ -596,54 +572,43 @@ __STATIC_INLINE void __set_CNTP_CTL(uint32_t value) {
   __regCNTP_CTL = value;
 }
 
-/** \brief  Set TLBIALL
-
-  TLB Invalidate All
+/** \brief  Set TLBIALL register
  */
 __STATIC_INLINE void __set_TLBIALL(uint32_t value) {
   register uint32_t __TLBIALL              __ASM("cp15:0:c8:c7:0");
   __TLBIALL = value;
 }
 
-/** \brief  Set BPIALL.
-
-  Branch Predictor Invalidate All
- */
+/** \brief  Set Branch Predictor Invalidate All register.
+* \param [in] value New register value to be set.
+*/
 __STATIC_INLINE void __set_BPIALL(uint32_t value) {
   register uint32_t __BPIALL            __ASM("cp15:0:c7:c5:6");
   __BPIALL = value;
 }
 
-/** \brief  Set ICIALLU
-
-  Instruction Cache Invalidate All
+/** \brief  Set ICIALLU register
  */
 __STATIC_INLINE void __set_ICIALLU(uint32_t value) {
   register uint32_t __ICIALLU         __ASM("cp15:0:c7:c5:0");
   __ICIALLU = value;
 }
 
-/** \brief  Set DCCMVAC
-
-  Data cache clean
+/** \brief  Set DCCMVAC register
  */
 __STATIC_INLINE void __set_DCCMVAC(uint32_t value) {
   register uint32_t __DCCMVAC         __ASM("cp15:0:c7:c10:1");
   __DCCMVAC = value;
 }
 
-/** \brief  Set DCIMVAC
-
-  Data cache invalidate
+/** \brief  Set DCIMVAC register
  */
 __STATIC_INLINE void __set_DCIMVAC(uint32_t value) {
   register uint32_t __DCIMVAC         __ASM("cp15:0:c7:c6:1");
   __DCIMVAC = value;
 }
 
-/** \brief  Set DCCIMVAC
-
-  Data cache clean and invalidate
+/** \brief  Set DCCIMVAC register
  */
 __STATIC_INLINE void __set_DCCIMVAC(uint32_t value) {
   register uint32_t __DCCIMVAC        __ASM("cp15:0:c7:c14:1");
@@ -651,8 +616,7 @@ __STATIC_INLINE void __set_DCCIMVAC(uint32_t value) {
 }
 
 /** \brief  Clean and Invalidate the entire data or unified cache
-
-  Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency
+ * \param op 0 - invalidate, 1 - clean, otherwise - invalidate and clean
  */
 __STATIC_INLINE __ASM void __L1C_CleanInvalidateCache(uint32_t op) {
         ARM

CMSIS/Core_A/Include/core_ca.h

@@ -675,60 +675,43 @@ typedef struct
  
 /* ##########################  L1 Cache functions  ################################# */
 
-/** \brief  Enable Caches
-
-  Enable Caches
- */
+/** \brief Enable Caches by setting I and C bits in \ref CMSIS_SCTLR "SCTLR" register.
+*/
 __STATIC_INLINE void L1C_EnableCaches(void) {
-  // Set I bit 12 to enable I Cache
-  // Set C bit  2 to enable D Cache
-  __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
+  __set_SCTLR( __get_SCTLR() | (1u << SCTLR_I_Pos) | (1u << SCTLR_C_Pos));
+  __ISB();
 }
 
-/** \brief  Disable Caches
-
-  Disable Caches
- */
+/** \brief Disable Caches by clearing I and C bits in \ref CMSIS_SCTLR "SCTLR" register.
+*/
 __STATIC_INLINE void L1C_DisableCaches(void) {
-  // Clear I bit 12 to disable I Cache
-  // Clear C bit  2 to disable D Cache
-  __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
+  __set_SCTLR( __get_SCTLR() & ~(1u << SCTLR_I_Pos) & ~(1u << SCTLR_C_Pos));
   __ISB();
 }
 
-/** \brief  Enable BTAC
-
-  Enable BTAC
- */
+/** \brief  Enable Branch Prediction by setting Z bit in \ref CMSIS_SCTLR "SCTLR" register.
+*/
 __STATIC_INLINE void L1C_EnableBTAC(void) {
-  // Set Z bit 11 to enable branch prediction
-  __set_SCTLR( __get_SCTLR() | (1 << 11));
+  __set_SCTLR( __get_SCTLR() | (1u << SCTLR_Z_Pos));
   __ISB();
 }
 
-/** \brief  Disable BTAC
-
-  Disable BTAC
- */
+/** \brief  Disable Branch Prediction by clearing Z bit in \ref CMSIS_SCTLR "SCTLR" register.
+*/
 __STATIC_INLINE void L1C_DisableBTAC(void) {
-  // Clear Z bit 11 to disable branch prediction
-  __set_SCTLR( __get_SCTLR() & ~(1 << 11));
+  __set_SCTLR( __get_SCTLR() & ~(1u << SCTLR_Z_Pos));
+  __ISB();
 }
 
 /** \brief  Invalidate entire branch predictor array
-
-  BPIALL. Branch Predictor Invalidate All.
- */
-
+*/
 __STATIC_INLINE void L1C_InvalidateBTAC(void) {
   __set_BPIALL(0);
   __DSB();     //ensure completion of the invalidation
   __ISB();     //ensure instruction fetch path sees new state
 }
 
-/** \brief  Invalidate the whole I$
-
-  ICIALLU. Instruction Cache Invalidate All to PoU
+/** \brief  Invalidate the whole instruction cache
 */
 __STATIC_INLINE void L1C_InvalidateICacheAll(void) {
   __set_ICIALLU(0);
@@ -736,27 +719,24 @@ __STATIC_INLINE void L1C_InvalidateICacheAll(void) {
   __ISB();     //ensure instruction fetch path sees new I cache state
 }
 
-/** \brief  Clean D$ by MVA
-
-  DCCMVAC. Data cache clean by MVA to PoC
+/** \brief  Clean data cache line by address.
+* \param va Pointer to data to clear the cache for.
 */
 __STATIC_INLINE void L1C_CleanDCacheMVA(void *va) {
   __set_DCCMVAC((uint32_t)va);
   __DMB();     //ensure the ordering of data cache maintenance operations and their effects
 }
 
-/** \brief  Invalidate D$ by MVA
-
-  DCIMVAC. Data cache invalidate by MVA to PoC
+/** \brief  Invalidate data cache line by address.
+* \param va Pointer to data to invalidate the cache for.
 */
 __STATIC_INLINE void L1C_InvalidateDCacheMVA(void *va) {
   __set_DCIMVAC((uint32_t)va);
   __DMB();     //ensure the ordering of data cache maintenance operations and their effects
 }
 
-/** \brief  Clean and Invalidate D$ by MVA
-
-  DCCIMVAC. Data cache clean and invalidate by MVA to PoC
+/** \brief  Clean and Invalidate data cache by address.
+* \param va Pointer to data to invalidate the cache for.
 */
 __STATIC_INLINE void L1C_CleanInvalidateDCacheMVA(void *va) {
   __set_DCCIMVAC((uint32_t)va);
@@ -764,37 +744,27 @@ __STATIC_INLINE void L1C_CleanInvalidateDCacheMVA(void *va) {
 }
 
 /** \brief  Clean and Invalidate the entire data or unified cache
-
-  Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
+* \param op 0 - invalidate, 1 - clean, otherwise - invalidate and clean
+* \see __L1C_CleanInvalidateCache
 */
 __STATIC_INLINE void L1C_CleanInvalidateCache(uint32_t op) {
-  __L1C_CleanInvalidateCache(op);  // compiler specific call
+  __L1C_CleanInvalidateCache(op);
 }
 
-
-/** \brief  Invalidate the whole D$
-
-  DCISW. Invalidate by Set/Way
+/** \brief  Invalidate the whole data cache.
 */
-
 __STATIC_INLINE void L1C_InvalidateDCacheAll(void) {
   L1C_CleanInvalidateCache(0);
 }
 
-/** \brief  Clean the whole D$
-
-    DCCSW. Clean by Set/Way
+/** \brief  Clean the whole data cache.
  */
-
 __STATIC_INLINE void L1C_CleanDCacheAll(void) {
   L1C_CleanInvalidateCache(1);
 }
 
-/** \brief  Clean and invalidate the whole D$
-
-    DCCISW. Clean and Invalidate by Set/Way
+/** \brief  Clean and invalidate the whole data cache.
  */
-
 __STATIC_INLINE void L1C_CleanInvalidateDCacheAll(void) {
   L1C_CleanInvalidateCache(2);
 }
@@ -802,57 +772,67 @@ __STATIC_INLINE void L1C_CleanInvalidateDCacheAll(void) {
 
 /* ##########################  L2 Cache functions  ################################# */
 #if (__L2C_PRESENT == 1U) || defined(DOXYGEN)
-//Cache Sync operation
+/** \brief Cache Sync operation by writing \ref L2C_310_TypeDef::CACHE_SYNC "CACHE_SYNC" register.
+*/
 __STATIC_INLINE void L2C_Sync(void)
 {
   L2C_310->CACHE_SYNC = 0x0;
 }
 
-//return Cache controller cache ID
+/** \brief Read cache controller cache ID from \ref L2C_310_TypeDef::CACHE_ID "CACHE_ID" register.
+ * \return L2C_310_TypeDef::CACHE_ID
+ */
 __STATIC_INLINE int L2C_GetID (void)
 {
   return L2C_310->CACHE_ID;
 }
 
-//return Cache controller cache Type
+/** \brief Read cache controller cache type from \ref L2C_310_TypeDef::CACHE_TYPE "CACHE_TYPE" register.
+*  \return L2C_310_TypeDef::CACHE_TYPE
+*/
 __STATIC_INLINE int L2C_GetType (void)
 {
   return L2C_310->CACHE_TYPE;
 }
 
-//Invalidate all cache by way
+/** \brief Invalidate all cache by way
+*/
 __STATIC_INLINE void L2C_InvAllByWay (void)
 {
   unsigned int assoc;
 
-  if (L2C_310->AUX_CNT & (1<<16))
-    assoc = 16;
-  else
-    assoc =  8;
-
-  L2C_310->INV_WAY = (1 << assoc) - 1;
-  while(L2C_310->INV_WAY & ((1 << assoc) - 1)); //poll invalidate
+  if (L2C_310->AUX_CNT & (1u << 16u)) {
+    assoc = 16u;
+  } else {
+    assoc =  8u;
+  }
+  
+  L2C_310->INV_WAY = (1u << assoc) - 1u;
+  while(L2C_310->INV_WAY & ((1u << assoc) - 1u)); //poll invalidate
 
   L2C_Sync();
 }
 
-//Clean and Invalidate all cache by way
+/** \brief Clean and Invalidate all cache by way
+*/
 __STATIC_INLINE void L2C_CleanInvAllByWay (void)
 {
   unsigned int assoc;
 
-  if (L2C_310->AUX_CNT & (1<<16))
-    assoc = 16;
-  else
-    assoc =  8;
+  if (L2C_310->AUX_CNT & (1u << 16u)) {
+    assoc = 16u;
+  } else {
+    assoc =  8u;
+  }
 
-  L2C_310->CLEAN_INV_WAY = (1 << assoc) - 1;
-  while(L2C_310->CLEAN_INV_WAY & ((1 << assoc) - 1)); //poll invalidate
+  L2C_310->CLEAN_INV_WAY = (1u << assoc) - 1u;
+  while(L2C_310->CLEAN_INV_WAY & ((1u << assoc) - 1u)); //poll invalidate
 
   L2C_Sync();
 }
 
-//Enable Cache
+/** \brief Enable Level 2 Cache
+*/
 __STATIC_INLINE void L2C_Enable(void)
 {
   L2C_310->CONTROL = 0;
@@ -863,28 +843,36 @@ __STATIC_INLINE void L2C_Enable(void)
   L2C_310->CONTROL = 0x01;
   L2C_Sync();
 }
-//Disable Cache
+
+/** \brief Disable Level 2 Cache
+*/
 __STATIC_INLINE void L2C_Disable(void)
 {
   L2C_310->CONTROL = 0x00;
   L2C_Sync();
 }
 
-//Invalidate cache by physical address
+/** \brief Invalidate cache by physical address
+* \param pa Pointer to data to invalidate cache for.
+*/
 __STATIC_INLINE void L2C_InvPa (void *pa)
 {
   L2C_310->INV_LINE_PA = (unsigned int)pa;
   L2C_Sync();
 }
 
-//Clean cache by physical address
+/** \brief Clean cache by physical address
+* \param pa Pointer to data to invalidate cache for.
+*/
 __STATIC_INLINE void L2C_CleanPa (void *pa)
 {
   L2C_310->CLEAN_LINE_PA = (unsigned int)pa;
   L2C_Sync();
 }
 
-//Clean and invalidate cache by physical address
+/** \brief Clean and invalidate cache by physical address
+* \param pa Pointer to data to invalidate cache for.
+*/
 __STATIC_INLINE void L2C_CleanInvPa (void *pa)
 {
   L2C_310->CLEAN_INV_LINE_PA = (unsigned int)pa;
@@ -1201,6 +1189,20 @@ __STATIC_INLINE void GIC_Enable(void)
   
 /* PL1 Physical Timer */
 #if (__CORTEX_A == 7U) || defined(DOXYGEN)
+  
+/** \brief Physical Timer Control register */
+typedef union
+{
+  struct
+  {
+    uint32_t ENABLE:1;      /*!< \brief bit: 0      Enables the timer. */
+    uint32_t IMASK:1;       /*!< \brief bit: 1      Timer output signal mask bit. */
+    uint32_t ISTATUS:1;     /*!< \brief bit: 2      The status of the timer. */
+    uint32_t _reserved0:29; /*!< \brief bit: 3..31  Reserved */
+  } b;                      /*!< \brief Structure used for bit  access */
+  uint32_t w;               /*!< \brief Type      used for word access */
+} CNTP_CTL_Type;
+
 /** Configures the frequency the timer shall run at.
 * \param value The timer frequency in Hz.
 */
@@ -1242,14 +1244,14 @@ __STATIC_INLINE void PTIM_SetLoadValue(uint32_t value) {
 }
 
 /** Get the load value from timers \ref Timer_Type::LOAD "LOAD" register.
-* \return timers PTIM::LOAD
+* \return Timer_Type::LOAD
 */
 __STATIC_INLINE uint32_t PTIM_GetLoadValue() {
   return(PTIM->LOAD);
 }
 
 /** Get current counter value from timers \ref Timer_Type::COUNTER "COUNTER" register.
-* \result PTIM::COUNTER
+* \result Timer_Type::COUNTER
 */
 __STATIC_INLINE uint32_t PTIM_GetCurrentValue() {
   return(PTIM->COUNTER);
@@ -1263,7 +1265,7 @@ __STATIC_INLINE void PTIM_SetControl(uint32_t value) {
 }
 
 /** Get the current timer configuration from its \ref Timer_Type::CONTROL "CONTROL" register.
-* \return PTIM::CONTROL
+* \return Timer_Type::CONTROL
 */
 __STATIC_INLINE uint32_t PTIM_GetControl(void) {
   return(PTIM->CONTROL);
@@ -2156,8 +2158,6 @@ __STATIC_INLINE void MMU_TTPage64k(uint32_t *ttb, uint32_t base_address, uint32_
 }
 
 /** \brief  Enable MMU
-
-  Enable MMU
 */
 __STATIC_INLINE void MMU_Enable(void) {
   // Set M bit 0 to enable the MMU
@@ -2168,8 +2168,6 @@ __STATIC_INLINE void MMU_Enable(void) {
 }
 
 /** \brief  Disable MMU
-
-  Disable MMU
 */
 __STATIC_INLINE void MMU_Disable(void) {
   // Clear M bit 0 to disable the MMU
@@ -2178,8 +2176,6 @@ __STATIC_INLINE void MMU_Disable(void) {
 }
 
 /** \brief  Invalidate entire unified TLB
-
-  TLBIALL. Invalidate entire unified TLB
 */
 
 __STATIC_INLINE void MMU_InvalidateTLB(void) {

CMSIS/DoxyGen/Core_A/src/cmsis_armcc.txt

@@ -238,7 +238,7 @@ struct foo {
 
 \fn __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
 \details
-  This function assigns the given value to the System Control Register.
+  This function assigns the given value to the \ref CMSIS_SCTLR "System Control Register".
 
 \fn __STATIC_INLINE uint32_t __get_SCTLR() 
 \details
@@ -281,7 +281,7 @@ struct foo {
 
 \fn __STATIC_INLINE void __set_BPIALL(uint32_t value)   
 \details
-  Branch Predictor Invalidate All
+  Write the provided value to the Branch Predictor Invalidate All (BPIALL) register.
 
 \fn __STATIC_INLINE void __set_ICIALLU(uint32_t value) 
 \details
@@ -298,6 +298,7 @@ struct foo {
 \fn __STATIC_INLINE void __set_DCCIMVAC(uint32_t value) 
 \details
   Data cache clean and invalidate
+
 */
 /**
 @} 

CMSIS/DoxyGen/Core_A/src/core_ca.txt

@@ -277,6 +277,29 @@ The macros <b>_VAL2FLD(field, value)</b> and <b>_FLD2VAL(field, value)</b> enabl
 /**
 \defgroup CMSIS_SCTLR Core Register SCTLR
 \brief Type definitions and defines for SCTLR
+\details Provides the top level control of the system, including its memory system.
+
+| Bits    | Name          | Function                                                      |
+| :------ | :------------ | :------------------------------------------------------------ |
+| [31]    | -             | Reserved.                                                     |
+| [30]    | TE            | Thumb Exception enable.                                       |
+| [29]    | AFE           | Access flag enable bit.                                       |
+| [28]    | TRE           | TEX remap enable bit.                                         |
+| [27:26] | -             | Reserved.                                                     |
+| [25]    | EE            | Exception Endianness bit.                                     |
+| [24:21] | -             | Reserved.                                                     |
+| [20]    | UWXN          | Unprivileged write permission implies PL1 Execute Never (XN). |
+| [19]    | WXN           | Write permission implies Execute Never (XN).                  |
+| [18:14] | -             | Reserved.                                                     |
+| [13]    | V             | Vectors bit.                                                  |
+| [12]    | I             | Instruction cache enable bit.                                 |
+| [11]    | Z             | Branch prediction enable bit.                                 |
+| [10]    | SW            | SWP and SWPB enable bit.                                      |
+| [9:3]   | -             | Reserved.                                                     |
+| [2]     | C             | Cache enable bit.                                             |
+| [1]     | A             | Alignment bit.                                                |
+| [0]     | M             | Address translation enable bit.                               |
+
 @{
 */
 /**
@@ -372,6 +395,7 @@ The macros <b>_VAL2FLD(field, value)</b> and <b>_FLD2VAL(field, value)</b> enabl
 \def ISR_I_Pos             
 \def ISR_F_Pos             
 */
+
 /** @} */
 /* end group CMSIS_ISR */
 
@@ -411,21 +435,34 @@ Hardware Abstraction Layer.
 \fn __STATIC_INLINE void L1C_CleanDCacheMVA(void *va) 
 \fn __STATIC_INLINE void L1C_InvalidateDCacheMVA(void *va) 
 \fn __STATIC_INLINE void L1C_CleanInvalidateDCacheMVA(void *va) 
+
 \fn __STATIC_INLINE void L1C_CleanInvalidateCache(uint32_t op) 
+\details
+Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
+
 \fn __STATIC_INLINE void L1C_InvalidateDCacheAll(void) 
 \fn __STATIC_INLINE void L1C_CleanDCacheAll(void) 
 \fn __STATIC_INLINE void L1C_CleanInvalidateDCacheAll(void) 
-\fn __STATIC_INLINE __ASM void __L1C_CleanInvalidateCache(uint32_t op) 
+\fn __STATIC_INLINE __ASM void __L1C_CleanInvalidateCache(uint32_t op)
+\details
+Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
+
+The parameter \b op defines which cleaning/invalidation strategy should be used:
+ - 0 - Cache is invalidated using DCISW register.
+ - 1 - Cache is cleaned using DCCSW register.
+ - other - Cache is invalidated and cleaned using DCCISW register.
 @}
 */
 
 /* ##########################  L2 Cache functions  ################################# */
 
-//Cache Sync operation
 /**
 \defgroup L2_chache_functions L2C-310 Cache Controller Functions 
 \details Functions to controll the Level 2 Cache.
-@{
+*/
+/** @{ */
+
+/**
 \struct L2C_310_TypeDef
 \def L2C_310
 \fn __STATIC_INLINE void L2C_Sync(void) 
@@ -438,9 +475,10 @@ Hardware Abstraction Layer.
 \fn __STATIC_INLINE void L2C_InvPa (void *pa) 
 \fn __STATIC_INLINE void L2C_CleanPa (void *pa) 
 \fn __STATIC_INLINE void L2C_CleanInvPa (void *pa) 
-@}
 */
 
+/** @} */
+
 /* ##########################  GIC functions  ###################################### */
 /**
 \defgroup GIC_functions Generic Interrupt Controller Functions
@@ -449,13 +487,11 @@ The Generic Interrupt Controller Functions grants access to the configuration, c
 status registers of an ARM Generic Interrupt Controller (ARM GIC). For detailed informations
 about its capabilities and usage constraints refere to the 
 <a href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0048b/index.html">ARM Generic Interrupt Controller Architecture Specificaton</a>.
+*/
 
-@{
-\struct  GICDistributor_Type
-\def GICDistributor
-\struct  GICInterface_Type
-\def GICInterface
+/** @{ */
 
+/**
 \fn __STATIC_INLINE void GIC_EnableDistributor(void)
 \details Globally enable the forwarding of interrupts to the CPU interfaces.
 
@@ -633,443 +669,400 @@ Initializes the distributor and the cpu interface.
 \see
 GIC_DistInit\n
 GIC_CPUInterfaceInit
-@}
+*/
 
-@{
-\var __IOM uint32_t GICDistributor_Type::D_CTLR
-\details Distributor Control Register
+/**
+\def GICDistributor
+\struct  GICDistributor_Type
+*/
 
-When access is Secure, in a system that supports two Security states:
+/**
+\def GICInterface
+\struct  GICInterface_Type
+*/
 
-| Bits    | Name          | Function                                                       |
-| :------ | :------------ | :------------------------------------------------------------- |
-| [31]    | RWP           | Indicates whether a register write is in progress or not.      |
-| [30:8]  | -             | Reserved.                                                      |
-| [7]     | EINWF         | Enable 1 of N Wakeup Functionality, if available.              |
-| [6]     | DS            | Disable Security.                                              |
-| [5]     | ARE_NS        | Affinity Routing Enable, Non-secure state.                     |
-| [4]     | ARE_S         | Affinity Routing Enable, Secure state.                         |
-| [3]     | -             | Reserved.                                                      |
-| [2]     | EnableGrp1S   | Enable Secure Group 1 interrupts.                              |
-| [1]     | EnableGrp1NS  | Enable Non-secure Group 1 interrupts.                          |
-| [0]     | EnableGrp0    | Enable Group 0 interrupts.                                     |
+/** @} */
 
-When access is Non-secure, in a system that supports two Security states:
+/* ##########################  Physical Timer functions  ############################ */
+/**
+\defgroup PL1_timer_functions Physical Timer Functions
+\brief Physical timer functions (on Cortex-A7 class devices)
+*/
+/** @{ */
 
-| Bits    | Name          | Function                                                       |
-| :------ | :------------ | :------------------------------------------------------------- |
-| [31]    | RWP           | Indicates whether a register write is in progress or not.      |
-| [30:5]  | -             | Reserved.                                                      |
-| [4]     | ARE_NS        | Affinity Routing Enable, Non-secure state.                     |
-| [3:2]   | -             | Reserved.                                                      |
-| [1]     | EnableGrp1A   | Enable Non-secure Group 1 interrupts.                          |
-| [0]     | EnableGrp1    | Enable Non-secure Group 1 interrupts.                          |
+/** \brief Physical Timer Control register */
+typedef union
+{
+  struct
+  {
+    uint32_t ENABLE:1;      /*!< \brief bit: 0      Enables the timer. */
+    uint32_t IMASK:1;       /*!< \brief bit: 1      Timer output signal mask bit. */
+    uint32_t ISTATUS:1;     /*!< \brief bit: 2      The status of the timer. */
+    uint32_t _reserved0:29; /*!< \brief bit: 3..31  Reserved */
+  } b;                      /*!< \brief Structure used for bit  access */
+  uint32_t w;               /*!< \brief Type      used for word access */
+} CNTP_CTL_Type;
+
+/** Configures the frequency the timer shall run at.
+* \param value The timer frequency in Hz.
+*/
+__STATIC_INLINE void PL1_SetCounterFrequency(uint32_t value);
 
-When in a system that supports only a single Security state:
+/** Sets the reset value of the timer.
+* \param value The value the timer is loaded with.
+*/
+__STATIC_INLINE void PL1_SetLoadValue(uint32_t value);
 
-| Bits    | Name          | Function                                                       |
-| :------ | :------------ | :------------------------------------------------------------- |
-| [31]    | RWP           | Indicates whether a register write is in progress or not.      |
-| [30:8]  | -             | Reserved.                                                      |
-| [7]     | EINWF         | Enable 1 of N Wakeup Functionality, if available.              |
-| [6]     | DS            | Disable Security.                                              |
-| [5]     | -             | Reserved.                                                      |
-| [4]     | ARE           | Affinity Routing Enable.                                       |
-| [3:2]   | -             | Reserved.                                                      |
-| [1]     | EnableGrp1    | Enable Group 1 interrupts.                                     |
-| [0]     | EnableGrp0    | Enable Group 0 interrupts.                                     |
+/** Get the current counter value.
+* \return Current counter value.
+*/
+__STATIC_INLINE uint32_t PL1_GetCurrentValue();
 
-\var __IM uint32_t GICDistributor_Type::D_TYPER
-\details Interrupt Controller Type Register
+/** Configure the timer by setting the control value.
+* \param value New \ref CNTP_CTL_Type "timer control value".
+*/
+__STATIC_INLINE void PL1_SetControl(uint32_t value);
 
-| Bits    | Name          | Function                                                       |
-| :------ | :------------ | :------------------------------------------------------------- |
-| [31:16] | -             | Reserved.                                                      |
-| [15:11] | LSPI          | Maximum number of lockable shared interrupts.                  |
-| [10]    | SecurityExtn  | Security Extensions: 0 - not implemented. 1 - implemented.     |
-| [9:8]   | -             | Reserved.                                                      |
-| [7:5]   | CPUNumber     | Number of implemented CPU interfaces [=CPUNumber+1]            |
-| [4:0]   | ITLinesNumber | Maximum number of interrups supported [=32*(ITLinesNumber+1)]. |
+/** @} */
 
-\var __IM uint32_t GICDistributor_Type::D_IIDR
-\details Distributor Implementer Identification Register
+/* ##########################  Private Timer functions  ############################ */
+/**
+\defgroup PTM_timer_functions Private Timer Functions
+\brief Private timer functions (on Cortex-A5 and -A9 class devices)
+@{
+\struct Timer_Type
+\def PTIM
+\fn __STATIC_INLINE void PTIM_SetLoadValue(uint32_t value)
+\fn __STATIC_INLINE uint32_t PTIM_GetLoadValue()
+\fn __STATIC_INLINE uint32_t PTIM_GetCurrentValue()
+\fn __STATIC_INLINE void PTIM_SetControl(uint32_t value)
+\fn __STATIC_INLINE uint32_t PTIM_GetControl(void)
+\fn __STATIC_INLINE void PTIM_ClearEventFlag(void)
+@}
+*/
 
-| Bits    | Name          | Function                                                       |
-| :------ | :------------ | :------------------------------------------------------------- |
-| [31:24] | ProductID     | An IMPLEMENTATION DEFINED product identifier                   |
-| [23:20] | -             | Reserved.                                                      |
-| [19:16] | Variant       | An IMPLEMENTATION DEFINED variant number.                      |
-| [15:12] | Revision      | An IMPLEMENTATION DEFINED revision number.                     |
-| [11:0]  | Implementer   | Contains the JEP106 code of the company implemented the GICD.  |
+/* ##########################  FPU functions  ############################ */
+/**
+\defgroup FPU_functions Floating Point Unit Functions
+\brief FPU functions
+@{
+\fn __STATIC_INLINE __ASM void __FPU_Enable(void) 
+@}
+*/
 
-\var __IOM uint8_t GICDistributor_Type::D_ITARGETSR[1020]
-\details Interrupt Processor Targets Registers
+/* ##########################  MMU functions  ###################################### */
+/**
+\defgroup MMU_functions Memory Management Unit Functions
+\brief Functions and defines that relate to the Memory Management Unit
+*/
 
-Each bit in the target field corresponds to one CPU interface. A CPU targets field bit that corresponds
-to an unimplemented CPU interface is RAZ/WI.
+/** @{ */
 
-| CPU target field value | Interrupt targets |
-| :--------------------- | :---------------- |
-| 0bxxxxxxx1             | CPU interface 0   |
-| 0bxxxxxx1x             | CPU interface 1   |
-| 0bxxxxx1xx             | CPU interface 2   |
-| 0bxxxx1xxx             | CPU interface 3   |
-| 0bxxx1xxxx             | CPU interface 4   |
-| 0bxx1xxxxx             | CPU interface 5   |
-| 0bx1xxxxxx             | CPU interface 6   |
-| 0b1xxxxxxx             | CPU interface 7   |
+/**
+\defgroup MMU_defs_gr MMU Defines and Structs
+\brief Defines and structures that relate to the Memory Management Unit
+*/
 
-\var __IOM uint32_t GICDistributor_Type::D_IGROUPR[32]
-\details Interrupt Group Registers
+/** @{ */
 
-Each bit corresponds to one interrupt:
- - Register index is given by INTID/32
- - Bit number is given by INTID%32
- 
-And the value denotes:
-- 0 When \ref GICDistributor_Type::D_CTLR "D_CTLR".DS==1, the corresponding interrupt is Group 0\n
-    When \ref GICDistributor_Type::D_CTLR "D_CTLR".DS==0, the corresponding interrupt is Secure.
-- 1 When \ref GICDistributor_Type::D_CTLR "D_CTLR".DS==1, the corresponding interrupt is Group 1.\n
-    When \ref GICDistributor_Type::D_CTLR "D_CTLR".DS==0, the corresponding interrupt is Non-secure Group 1.
- 
-\var __IO uint32_t GICDistributor_Type::D_CLRSPI_NSR
-\details Clear Non-secure SPI Pending Register
+/**
+\def SECTION_DESCRIPTOR      
+\def SECTION_B_SHIFT
+\def SECTION_C_SHIFT
+\def SECTION_TEX0_SHIFT      
+\def SECTION_TEX1_SHIFT      
+\def SECTION_TEX2_SHIFT      
+\def SECTION_XN_SHIFT        
+\def SECTION_DOMAIN_SHIFT    
+\def SECTION_P_SHIFT         
+\def SECTION_AP_SHIFT        
+\def SECTION_AP2_SHIFT       
+\def SECTION_S_SHIFT         
+\def SECTION_NG_SHIFT        
+\def SECTION_NS_SHIFT        
+\def PAGE_L1_DESCRIPTOR      
+\def PAGE_L2_4K_DESC         
+\def PAGE_L2_64K_DESC        
+\def PAGE_4K_B_SHIFT         
+\def PAGE_4K_C_SHIFT         
+\def PAGE_4K_TEX0_SHIFT      
+\def PAGE_4K_TEX1_SHIFT      
+\def PAGE_4K_TEX2_SHIFT      
+\def PAGE_64K_B_SHIFT        
+\def PAGE_64K_C_SHIFT        
+\def PAGE_64K_TEX0_SHIFT     
+\def PAGE_64K_TEX1_SHIFT     
+\def PAGE_64K_TEX2_SHIFT     
+\def PAGE_B_SHIFT            
+\def PAGE_C_SHIFT            
+\def PAGE_TEX_SHIFT          
+\def PAGE_XN_4K_SHIFT        
+\def PAGE_XN_64K_SHIFT       
+\def PAGE_DOMAIN_SHIFT       
+\def PAGE_P_SHIFT            
+\def PAGE_AP_SHIFT           
+\def PAGE_AP2_SHIFT          
+\def PAGE_S_SHIFT            
+\def PAGE_NG_SHIFT           
+\def PAGE_NS_SHIFT           
+\def OFFSET_1M               
+\def OFFSET_64K              
+\def OFFSET_4K               
+\def DESCRIPTOR_FAULT             
 
-| Bits    | Name          | Function                                          |
-| :------ | :------------ | :------------------------------------------------ | 
-| [31:10] | -             | Reserved.                                         |
-| [9:0]   | INTID         | The interrupt number to clear pending state from. |
+\enum mmu_region_size_Type
+\enum mmu_memory_Type
+\enum mmu_cacheability_Type
+\enum mmu_ecc_check_Type
+\enum mmu_execute_Type
+\enum mmu_global_Type
+\enum mmu_shared_Type
+\enum mmu_secure_Type
+\enum mmu_access_Type
 
-\var __IO uint32_t GICDistributor_Type::D_CLRSPI_SR
-\details Clear Secure SPI Pending Register
+\struct  mmu_region_attributes_Type
 
-| Bits    | Name          | Function                                          |
-| :------ | :------------ | :------------------------------------------------ | 
-| [31:10] | -             | Reserved.                                         |
-| [9:0]   | INTID         | The interrupt number to clear pending state from. |
+\def section_normal(descriptor_l1, region) 
+\def section_normal_cod(descriptor_l1, region)
+\def section_normal_ro(descriptor_l1, region)
+\def section_normal_rw(descriptor_l1, region)
+\def section_so(descriptor_l1, region)
+\def section_device_ro(descriptor_l1, region)
+\def section_device_rw(descriptor_l1, region)
+\def page4k_device_rw(descriptor_l1, descriptor_l2, region)
+\def page64k_device_rw(descriptor_l1, descriptor_l2, region) 
+*/
+/** @} */
+/* end group MMU_defs_gr */
 
-\var __IOM uint32_t GICDistributor_Type::D_IGRPMODR[32]
-\details Interrupt Group Modifier Registers
+/* start grouping functions */
+/** @{ */
 
-Each bit corresponds to one interrupt:
- - Register index is given by INTID/32
- - Bit number is given by INTID%32
- 
-\var __IOM uint64_t GICDistributor_Type::D_IROUTER[988]
-\details Interrupt Routing Registers
+/**
+\fn __STATIC_INLINE int MMU_XNSection(uint32_t *descriptor_l1, mmu_execute_Type xn)
+\details 
+  The function sets section execution-never attribute
 
-| Bits    | Name          | Function                                                      |
-| :------ | :------------ | :------------------------------------------------------------ | 
-| [63:40] | -             | Reserved.                                                     |
-| [39:32] | Aff3          | Affinity level 3, the least significant affinity level field. |
-| [31]    | IRM           | Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy. |
-| [30:24] | -             | Reserved.                                                     |
-| [23:16] | Aff2          | Affinity level 2, an intermediate affinity level field.       | 
-| [15:8]  | Aff1          | Affinity level 1, an intermediate affinity level field.       |
-| [7:0]   | Aff0          | Affinity level 0, the most significant affinity level field.  |
+\fn __STATIC_INLINE int MMU_DomainSection(uint32_t *descriptor_l1, uint8_t domain)
+\details 
+The function sets section domain.
 
-\var __IOM uint32_t GICDistributor_Type::D_NSACR[64]
-\details Non-secure Access Control Registers
+\fn __STATIC_INLINE int MMU_PSection(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
+\details
+  The function sets section parity check
 
-Each two bits corresponds to one interrupt:
- - Register index is given by INTID/16
- - Bit number is given by 2*INTID%16
+\fn __STATIC_INLINE int MMU_APSection(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
+\details 
+The function sets section access privileges
 
-The possible values of each 2-bit field are:
- - 00 - Non-secure accesses to all fields associated with the corresponding interrupt are permitted.
- - 01 - Non-secure accesses are only permitted to requesting fields.
- - 10 - As 01, additionally accesses to clearing field are permitted.
- - 11 - As 10, additionally accesses to target and routing fields are permitted.
- 
-\var __IO uint32_t GICDistributor_Type::D_SETSPI_NSR
-\details Set Non-secure SPI Pending Register
+\fn __STATIC_INLINE int MMU_SharedSection(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
+\details
+  The function sets section shareability
 
-| Bits    | Name          | Function                                          |
-| :------ | :------------ | :------------------------------------------------ | 
-| [31:10] | -             | Reserved.                                         |
-| [9:0]   | INTID         | The interrupt number to set pending state for.    |
+\fn __STATIC_INLINE int MMU_GlobalSection(uint32_t *descriptor_l1, mmu_global_Type g_bit)
+\details
+  The function sets section Global attribute
 
-\var __IO uint32_t GICDistributor_Type::D_SETSPI_SR
-\details Set Secure SPI Pending Register
+\fn __STATIC_INLINE int MMU_SecureSection(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
+\details
+  The function sets section Global attribute
 
-| Bits    | Name          | Function                                          |
-| :------ | :------------ | :------------------------------------------------ | 
-| [31:10] | -             | Reserved.                                         |
-| [9:0]   | INTID         | The interrupt number to set pending state for.    |
+\fn __STATIC_INLINE int MMU_XNPage(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
+\details
+  The function sets 4k/64k page execution-never attribute
 
-\var __IOM uint8_t GICDistributor_Type::D_SPENDSGIR[16]
-\details SGI Set-Pending Registers
-Each register corresponds to one software generated interrupt (SGI).
+\fn __STATIC_INLINE int MMU_DomainPage(uint32_t *descriptor_l1, uint8_t domain)
+\details
+  The function sets 4k/64k page domain
 
-Reading from this register reveals
- - 0 - interrupt is not pending
- - 1 - interrupt is pending
- 
-Writing to this register causes
- - 0 - no effect
- - 1 - adds the pending state
- 
-\var __IOM uint8_t GICDistributor_Type::D_CPENDSGIR[16]
-\details SGI Clear-Pending Registers
-Each register corresponds to one software generated interrupt (SGI).
+\fn __STATIC_INLINE int MMU_PPage(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
+\details
+  The function sets 4k/64k page parity check
 
-Reading from this register reveals
- - 0 - interrupt is not pending
- - 1 - interrupt is pending
- 
-Writing to this register causes
- - 0 - no effect
- - 1 - removes the pending state
+\fn __STATIC_INLINE int MMU_APPage(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
+\details
+  The function sets 4k/64k page access privileges
+\fn __STATIC_INLINE int MMU_SharedPage(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
+\details
+  The function sets 4k/64k page shareability
 
-\var __IOM uint32_t GICDistributor_Type::D_STATUSR
-\details Error Reporting Status Register
+\fn __STATIC_INLINE int MMU_GlobalPage(uint32_t *descriptor_l2, mmu_global_Type g_bit)
+\details
+  The function sets 4k/64k page Global attribute
 
-| Bits    | Name          | Function                                          |
-| :------ | :------------ | :------------------------------------------------ | 
-| [31:4]  | -             | Reserved.                                         |
-| [3]     | WROD          | Write to an RO location.                          |
-| [2]     | RWOD          | Read of a WO location.                            |
-| [1]     | WRD           | Write to a reserved location.                     |
-| [0]     | RRD           | Read of a reserved location.                      |
+\fn __STATIC_INLINE int MMU_SecurePage(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
+\details
+  The function sets 4k/64k page Global attribute
 
-\var __IOM uint32_t GICDistributor_Type::D_ISENABLER[32]
-\details Interrupt Set-Enable Registers
+\fn __STATIC_INLINE int MMU_MemorySection(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
+\details
+  The function sets section memory attributes
 
-Each bit corresponds to one interrupt:
- - Register index is given by INTID/32
- - Bit number is given by INTID%32
+\fn __STATIC_INLINE int MMU_MemoryPage(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
+\details
+  The function sets 4k/64k page memory attributes
 
-\note Bits corresponding to unimplemented interrupts are RAZ/WI.
+\fn __STATIC_INLINE int MMU_GetSectionDescriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
+\details
+  The function creates a section descriptor.
 
-\var __IOM uint32_t GICDistributor_Type::D_ICENABLER[32]
-\details Interrupt Clear-Enable Registers
+\fn __STATIC_INLINE int MMU_GetPageDescriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
+\details
+  The function creates a 4k/64k page descriptor.
+  Assumptions:
+  - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
+  - Functions always return 0
 
-Each bit corresponds to one interrupt:
- - Register index is given by INTID/32
- - Bit number is given by INTID%32
+\fn __STATIC_INLINE void MMU_TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
+\fn __STATIC_INLINE void MMU_TTPage4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
+\fn __STATIC_INLINE void MMU_TTPage64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
+\fn __STATIC_INLINE void MMU_Enable(void) 
+\details 
+   Set M bit 0 to enable the MMU
+   Set AFE bit to enable simplified access permissions model
+   Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
 
-\note Bits corresponding to unimplemented interrupts are RAZ/WI.
+\fn __STATIC_INLINE void MMU_Disable(void)
 
-\var __IOM uint32_t GICDistributor_Type::D_ISPENDR[32]
-\details Interrupt Set-Pending Registers
+\fn __STATIC_INLINE void MMU_InvalidateTLB(void) 
+*/
 
-Each bit corresponds to one interrupt:
- - Register index is given by INTID/32
- - Bit number is given by INTID%32
+/** @} */
+/* end of MMU_func_gr */
 
-\note Bits corresponding to unimplemented interrupts are RAZ/WI.
+/** @} */
+/* end of MMU_functions */
 
-\var __IOM uint32_t GICDistributor_Type::D_ICPENDR[32]
-\details Interrupt Clear-Pending Registers
+/** @} */
 
-Each bit corresponds to one interrupt:
- - Register index is given by INTID/32
- - Bit number is given by INTID%32
- 
-\note Bits corresponding to unimplemented interrupts are RAZ/WI.
+/* ########################## L2C_310_TypeDef Member ########################## */
+/**
+\var L2C_310_TypeDef::ADDRESS_FILTER_END
+\brief 
 
-\var __IOM uint32_t GICDistributor_Type::D_ICFGR[64]
-\details Interrupt Configuration Registers
+\var __IOM uint32_t L2C_310_TypeDef::ADDRESS_FILTER_START
+\brief
 
-Each interrupt can be configured by two corresponding bits:
+\var __IOM uint32_t L2C_310_TypeDef::AUX_CNT
+\brief
 
-| Bits           | Name          | Function                                                       |
-| :------------- | :------------ | :------------------------------------------------------------- |
-| [2*INTID%16+1] | Edge          | Interrupt is: 0 - level sensitive, 1 - edge triggered          |
-| [2*INTID%16]   | Model         | 0 - N-N Model, 1 - 1-N Model; RAZ/WI when unsupported          |
+\var __IM  uint32_t L2C_310_TypeDef::CACHE_ID
+\brief
 
-\var __IOM uint8_t GICDistributor_Type::D_IPRIORITYR[1020]
-\details Interrupt Priority Registers
+\var __IOM uint32_t L2C_310_TypeDef::CACHE_SYNC
+\brief
 
-A GIC might implement fewer than eight priority bits, but must implement at least bits [7:4] of each
-field. In each field, unimplemented bits are RAZ/WI.
+\var __IM  uint32_t L2C_310_TypeDef::CACHE_TYPE
+\brief
 
-\note A register field corresponding to an unimplemented interrupt is RAZ/WI.
+\var __IOM uint32_t L2C_310_TypeDef::CLEAN_INV_LINE_INDEX_WAY
+\brief
 
-\var __IOM uint32_t GICDistributor_Type::D_ISACTIVER[32]
-\details Interrupt Set-Active Registers
+\var __IOM uint32_t L2C_310_TypeDef::CLEAN_INV_LINE_PA
+\brief
 
-Each bit corresponds to one interrupt:
- - Register index is given by INTID/32
- - Bit number is given by INTID%32
- 
-\note Bits corresponding to unimplemented interrupts are RAZ/WI.
+\var __IOM uint32_t L2C_310_TypeDef::CLEAN_INV_WAY
+\brief
 
-\var __IOM uint32_t GICDistributor_Type::D_ICACTIVER[32]
-\details Interrupt Clear-Active Registers
+\var __IOM uint32_t L2C_310_TypeDef::CLEAN_LINE_INDEX_WAY
+\brief
 
-Each bit corresponds to one interrupt:
- - Register index is given by INTID/32
- - Bit number is given by INTID%32
+\var __IOM uint32_t L2C_310_TypeDef::CLEAN_LINE_PA
+\brief
 
-\note Bits corresponding to unimplemented interrupts are RAZ/WI.
+\var __IOM uint32_t L2C_310_TypeDef::CLEAN_WAY
+\brief
 
-\var __OM uint32_t GICDistributor_Type::D_SGIR
-\details Software Generated Interrupt Register
+\var __IOM uint32_t L2C_310_TypeDef::CONTROL
+\brief
 
-| Bits    | Name             | Function                                                         |
-| :------ | :------------    | :--------------------------------------------------------------- |
-| [31:26] | -                | Reserved.                                                        |
-| [25:24] | TargetFilterList | Determines how the Distributor processes the requested SGI.      |
-| [23:16] | CPUTargetList    | When TargetListFilter is 00, this field defines the CPU interfaces to which the Distributor must forward the interrupt. |
-| [15]    | NSATT            | Specifies the required group of the SGI.                         |
-| [14:4]  | -                | Reserved.                                                        |
-| [3:0]   | INTID            | The INTID of the SGI to forward to the specified CPU interfaces. |
+\var __IOM uint32_t L2C_310_TypeDef::DATA_LOCK_0_WAY
+\brief
 
-Refer to \ref GICDistributor_Type::D_ITARGETSR "D_ITARGETSR" for details on TargetFilterList field.
+\var __IOM uint32_t L2C_310_TypeDef::DATA_LOCK_1_WAY
+\brief
 
-\var __IOM uint32_t GICInterface_Type::C_CTLR
-\details CPU Interface Control Register
+\var __IOM uint32_t L2C_310_TypeDef::DATA_LOCK_2_WAY
+\brief
 
-Enables the signaling of interrupts by the CPU interface to the connected processor, and
-provides additional top-level control of the CPU interface. In a GICv2 implementation, this
-includes control of the end of interrupt (EOI) behavior.
+\var __IOM uint32_t L2C_310_TypeDef::DATA_LOCK_3_WAY
+\brief
 
-| Bits    | Name          | Function                                                       |
-| :------ | :------------ | :------------------------------------------------------------- |
-| [31:1]  | -             | Reserved.                                                      |
-| [0]     | Enable        | Interrupt signaling: 0 - Disable. 1 - Enable.                  |
+\var __IOM uint32_t L2C_310_TypeDef::DATA_LOCK_4_WAY
+\brief
 
-\var __IM uint32_t GICInterface_Type::C_IAR
-\details CPU Interface Interrupt Acknowledge Register
+\var __IOM uint32_t L2C_310_TypeDef::DATA_LOCK_5_WAY
+\brief
 
-| Bits    | Name          | Function                                                       |
-| :------ | :------------ | :------------------------------------------------------------- |
-| [31:24] | -             | Reserved.                                                      |
-| [23:0]  | INTID         | The interrupt number of the signaled interrupt.                |
+\var __IOM uint32_t L2C_310_TypeDef::DATA_LOCK_6_WAY
+\brief
 
-\var __OM uint32_t GICInterface_Type::C_EOIR
-\details CPU Interface End Of Interrupt Register
+\var __IOM uint32_t L2C_310_TypeDef::DATA_LOCK_7_WAY
+\brief
 
-| Bits    | Name          | Function                                                       |
-| :------ | :------------ | :------------------------------------------------------------- |
-| [31:24] | -             | Reserved.                                                      |
-| [23:0]  | INTID         | The interrupt number of the finished interrupt.                |
- 
- \var __IM uint32_t GICInterface_Type::C_HPPIR
-\details CPU Interface Highest Priority Pending Interrupt Register
+\var __IOM uint32_t L2C_310_TypeDef::DEBUG_CONTROL
+\brief
 
-| Bits    | Name          | Function                                                       |
-| :------ | :------------ | :------------------------------------------------------------- |
-| [31:24] | -             | Reserved.                                                      |
-| [23:0]  | INTID         | The INTID of the signaled interrupt.                           |
+\var __IOM uint32_t L2C_310_TypeDef::EVENT_CONTROL
+\brief
 
-\var  __IM uint32_t GICInterface_Type::C_IIDR
-\details CPU Interface Identification Register
+\var __IOM uint32_t L2C_310_TypeDef::EVENT_COUNTER0_CONF
+\brief
 
-| Bits    | Name          | Function                                                       |
-| :------ | :------------ | :------------------------------------------------------------- |
-| [31:20] | ProductID     | An IMPLEMENTATION DEFINED product identifier                   |
-| [19:16] | Arch_version  | The version of the GIC architecture that is implemented.       |
-| [15:12] | Revision      | An IMPLEMENTATION DEFINED revision number for the CPU interface. |
-| [11:0]  | Implementer   | Contains the JEP106 code of the company that implemented the CPU interface. |
+\var __IOM uint32_t L2C_310_TypeDef::EVENT_COUNTER1_CONF
+\brief
 
+\var __IOM uint32_t L2C_310_TypeDef::INST_LOCK_0_WAY
+\brief
 
-\var __IOM uint32_t GICInterface_Type::C_PMR
-\details CPU Interface Priority Mask Register
+\var __IOM uint32_t L2C_310_TypeDef::INST_LOCK_1_WAY
+\brief
 
-| Bits    | Name          | Function                                                       |
-| :------ | :------------ | :------------------------------------------------------------- |
-| [31:8]  | -             | Reserved.                                                      |
-| [7:0]   | Priority      | The priority mask level for the CPU interface.                 |
+\var __IOM uint32_t L2C_310_TypeDef::INST_LOCK_2_WAY
+\brief
 
-\note IMPLEMENTATION DEFINED unsupported priority bits might be RAZ/WI.
- 
-\var __IOM uint32_t GICInterface_Type::C_BPR
-\details CPU Interface Binary Point Register
+\var __IOM uint32_t L2C_310_TypeDef::INST_LOCK_3_WAY
+\brief
 
-| Bits    | Name          | Function                                                       |
-| :------ | :------------ | :------------------------------------------------------------- |
-| [31:3]  | -             | Reserved.                                                      |
-| [2:0]   | Binary_Point  | Controls how the 8-bit interrupt priority field is split into a group priority field and a subpriority field. |
+\var __IOM uint32_t L2C_310_TypeDef::INST_LOCK_4_WAY
+\brief
 
-The binary point (values 0-7) defines the amount of priority bits used as subpriority. Please
-refer to the section Interrupt prioritization in the
-<a href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0048b/index.html">ARM Generic Interrupt Controller Architecture Specificaton</a>
-for details.
+\var __IOM uint32_t L2C_310_TypeDef::INST_LOCK_5_WAY
+\brief
 
-\var __IOM uint32_t GICInterface_Type::C_ABPR
-\details CPU Interface Aliased Binary Point Register
-\see GICInterface_Type::C_BPR
+\var __IOM uint32_t L2C_310_TypeDef::INST_LOCK_6_WAY
+\brief
 
-\var __OM uint32_t GICInterface_Type::C_AEOIR
-\details CPU Interface Aliased End Of Interrupt Register
-\see GICInterface_Type::C_EOIR
+\var __IOM uint32_t L2C_310_TypeDef::INST_LOCK_7_WAY
+\brief
 
-\var __IM uint32_t GICInterface_Type::C_AHPPIR
-\details CPU Interface Aliased Highest Priority Pending Interrupt Register
-\see GICInterface_Type::C_HPPIR
+\var __OM  uint32_t L2C_310_TypeDef::INTERRUPT_CLEAR
+\brief
 
-\var __IM uint32_t GICInterface_Type::C_AIAR
-\details CPU Interface Aliased Interrupt Acknowledge Register
-\see GICInterface_Type::C_IAR
+\var __IOM uint32_t L2C_310_TypeDef::INTERRUPT_MASK
+\brief
 
-\var __IOM uint32_t GICInterface_Type::C_APR[4]
-\details CPU Interface Active Priorities Registers
-\note The register values are IMPLEMENTATION DEFINED.
+\var __IOM uint32_t L2C_310_TypeDef::INV_LINE_PA
+\brief
 
-\var __OM uint32_t GICInterface_Type::C_DIR
-\details CPU Interface Deactivate Interrupt Register
-
-| Bits    | Name  | Function                                                       |
-| :------ | :---- | :------------------------------------------------------------- |
-| [31:24] | -     | Reserved.                                                      |
-| [23:0]  | INTID | The INTID of the interrupt to be disabled.                     |
-
-\var __IOM uint32_t GICInterface_Type::C_NSAPR[4]
-\details CPU Interface Non-secure Active Priorities Registers
-\note The register values are IMPLEMENTATION DEFINED.
-\see GICInterface_Type::C_APR[4]
-
-\var __IM uint32_t GICInterface_Type::C_RPR
-\details CPU Interface Running Priority Register
-
-| Bits    | Name     | Function                                                       |
-| :------ | :------- | :------------------------------------------------------------- |
-| [31:8]  | -        | Reserved.                                                      |
-| [7:0]   | Priority | The current running priority on the CPU interface.             |
+\var __IOM uint32_t L2C_310_TypeDef::INV_WAY
+\brief
 
-\var __IOM uint32_t GICInterface_Type::C_STATUSR
-\details CPU Interface Status Register
+\var __IOM uint32_t L2C_310_TypeDef::LOCK_LINE_EN
+\brief
 
-| Bits    | Name     | Function                                                       |
-| :------ | :------- | :------------------------------------------------------------- |
-| [31:5]  | -        | Reserved.                                                      |
-| [4]     | ASV      | Attempted security violation.                                  |
-| [3]     | WROD     | Write to an RO location.                                       |
-| [2]     | RWOD     | Read of a WO location.                                         |
-| [1]     | WRD      | Write to a reserved location.                                  |
-| [0]     | RRD      | Read of a reserved location.                                   |
+\var __IM  uint32_t L2C_310_TypeDef::MASKED_INT_STATUS
+\brief
 
-@}
-*/
+\var __IM  uint32_t L2C_310_TypeDef::RAW_INT_STATUS
+\brief
 
-/* ##########################  Physical Timer functions  ############################ */
-/**
-\defgroup PL1_timer_functions Physical Timer Functions
-\brief Physical timer functions (on Cortex-A7 class devices)
-@{
-\fn __STATIC_INLINE void PL1_SetCounterFrequency(uint32_t value)
-\fn __STATIC_INLINE void PL1_SetLoadValue(uint32_t value)
-\fn __STATIC_INLINE uint32_t PL1_GetCurrentValue()
-\fn __STATIC_INLINE void PL1_SetControl(uint32_t value)
-@}
+\var __IOM uint32_t L2C_310_TypeDef::UNLOCK_ALL_BY_WAY
+\brief
 */
 
-/* ##########################  Private Timer functions  ############################ */
+/* ########################## Timer_Type Members ########################## */
 /**
-\defgroup PTM_timer_functions Private Timer Functions
-\brief Private timer functions (on Cortex-A5 and -A9 class devices)
-@{
-\struct Timer_Type
-\def PTIM
-\fn __STATIC_INLINE void PTIM_SetLoadValue(uint32_t value)
-\fn __STATIC_INLINE uint32_t PTIM_GetLoadValue()
-\fn __STATIC_INLINE uint32_t PTIM_GetCurrentValue()
-\fn __STATIC_INLINE void PTIM_SetControl(uint32_t value)
-\fn __STATIC_INLINE uint32_t PTIM_GetControl(void)
-\fn __STATIC_INLINE void PTIM_ClearEventFlag(void)
-
 \var __IOM uint32_t Timer_Type::LOAD
 \details Private Timer Load Register
 The Timer Load Register contains the value copied to the Timer Counter Register when
@@ -1114,218 +1107,498 @@ zero. If the timer interrupt is enabled, Interrupt ID 29 is set as pending in th
 Distributor after the event flag is set. The event flag is cleared when written to 1.
 
 \var __IOM uint32_t Timer_Type::WLOAD
-\details
+\details Watchdog Load Register
+
+The Watchdog Load Register contains the value copied to the Watchdog Counter
+Register when it decrements down to zero with auto reload mode enabled, in Timer
+mode. Writing to the Watchdog Load Register means that you also write to the
+Watchdog Counter Register.
 
 \var __IOM uint32_t Timer_Type::WCOUNTER
-\details
+\details Watchdog Counter Register
+
+The Watchdog Counter Register is a down counter.
+
+The behavior of the watchdog when the Watchdog Counter Register reaches zero
+depends on its current mode:
+ - Timer mode: The watchdog interrupt status event flag is set and the interrupt
+   is set as pending in the Interrupt Distributor.
+ - Watchdog mode: Tthe Watchdog reset status flag is set and the associated WDRESETREQ
+   reset request output pin is asserted.
 
 \var __IOM uint32_t Timer_Type::WCONTROL
-\details
+\details Watchdog Control Register
+
+| Bits    | Name            | Function                                                       |
+| :------ | :-------------- | :------------------------------------------------------------- |
+| [31:16] | -               | Reserved.                                                      |
+| [15:8]  | Prescaler       | The prescaler modifies the clock period for the decrementing event for the Counter Register. |
+| [7:4]   | -               | Reserved.                                                      |
+| [3]     | Watchdog Mode   | 0 - Timer mode (default), 1 - Watchdog mode                    |
+| [2]     | IT Enable       | Interrupt enable for timer mode.                               |
+| [1]     | Auto Reload     | 0 - Single shot mode, 1 - Continuous timer mode                |
+| [0]     | Watchdog Enable | 0 - Watchdog counter disabled, 1 - Watchdog timer enabled      |
 
 \var __IOM uint32_t Timer_Type::WISR
-\details
+\details Watchdog Interrupt Status Register
+
+| Bits    | Name            | Function                                                       |
+| :------ | :-------------- | :------------------------------------------------------------- |
+| [31:1]  | -               | Reserved.                                                      |
+| [0]     | Event Flag      | The event flag is a sticky bit that is automatically set when the Counter Register reaches zero in timer mode. |
 
 \var __IOM uint32_t Timer_Type::WRESET
-\details
+\details Watchdog Reset Status Register
 
-\var __IM uint32_t Timer_Type::WDISABLE
-\details
-@}
-*/
+| Bits    | Name            | Function                                                       |
+| :------ | :-------------- | :------------------------------------------------------------- |
+| [31:1]  | -               | Reserved.                                                      |
+| [0]     | Reset Flag      | The reset flag is a sticky bit that is automatically set when the Counter Register reaches zero and a reset request is sent accordingly. (In watchdog mode) | 
 
-/* ##########################  FPU functions  ############################ */
-/**
-\defgroup FPU_functions Floating Point Unit Functions
-\brief FPU functions
-@{
-\fn __STATIC_INLINE __ASM void __FPU_Enable(void) 
-@}
-*/
+\var __IM uint32_t Timer_Type::WDISABLE
+\details Watchdog Disable Register
 
-/* ##########################  MMU functions  ###################################### */
-/**
-\defgroup MMU_functions Memory Management Unit Functions
-\brief Functions and defines that relate to the Memory Management Unit
-@{
+Use the Watchdog Disable Register to switch from watchdog to timer mode. The
+software must write 0x12345678 then 0x87654321 successively to the Watchdog Disable
+Register so that the watchdog mode bit in the Watchdog Control Register is set to zero.
 */
 
+/* ########################## GICInterface_Type Member ########################## */
 /**
-\defgroup MMU_defs_gr MMU Defines and Structs
-\brief Defines and structures that relate to the Memory Management Unit
-@{
-*/
+\var __IOM uint32_t GICInterface_Type::C_CTLR
+\details CPU Interface Control Register
 
-/**
-\def SECTION_DESCRIPTOR      
-\def SECTION_B_SHIFT         
-\def SECTION_C_SHIFT         
-\def SECTION_TEX0_SHIFT      
-\def SECTION_TEX1_SHIFT      
-\def SECTION_TEX2_SHIFT      
-\def SECTION_XN_SHIFT        
-\def SECTION_DOMAIN_SHIFT    
-\def SECTION_P_SHIFT         
-\def SECTION_AP_SHIFT        
-\def SECTION_AP2_SHIFT       
-\def SECTION_S_SHIFT         
-\def SECTION_NG_SHIFT        
-\def SECTION_NS_SHIFT        
-\def PAGE_L1_DESCRIPTOR      
-\def PAGE_L2_4K_DESC         
-\def PAGE_L2_64K_DESC        
-\def PAGE_4K_B_SHIFT         
-\def PAGE_4K_C_SHIFT         
-\def PAGE_4K_TEX0_SHIFT      
-\def PAGE_4K_TEX1_SHIFT      
-\def PAGE_4K_TEX2_SHIFT      
-\def PAGE_64K_B_SHIFT        
-\def PAGE_64K_C_SHIFT        
-\def PAGE_64K_TEX0_SHIFT     
-\def PAGE_64K_TEX1_SHIFT     
-\def PAGE_64K_TEX2_SHIFT     
-\def PAGE_B_SHIFT            
-\def PAGE_C_SHIFT            
-\def PAGE_TEX_SHIFT          
-\def PAGE_XN_4K_SHIFT        
-\def PAGE_XN_64K_SHIFT       
-\def PAGE_DOMAIN_SHIFT       
-\def PAGE_P_SHIFT            
-\def PAGE_AP_SHIFT           
-\def PAGE_AP2_SHIFT          
-\def PAGE_S_SHIFT            
-\def PAGE_NG_SHIFT           
-\def PAGE_NS_SHIFT           
-\def OFFSET_1M               
-\def OFFSET_64K              
-\def OFFSET_4K               
-\def DESCRIPTOR_FAULT             
+Enables the signaling of interrupts by the CPU interface to the connected processor, and
+provides additional top-level control of the CPU interface. In a GICv2 implementation, this
+includes control of the end of interrupt (EOI) behavior.
 
-\enum mmu_region_size_Type
-\enum mmu_memory_Type
-\enum mmu_cacheability_Type
-\enum mmu_ecc_check_Type
-\enum mmu_execute_Type
-\enum mmu_global_Type
-\enum mmu_shared_Type
-\enum mmu_secure_Type
-\enum mmu_access_Type
+| Bits    | Name          | Function                                                       |
+| :------ | :------------ | :------------------------------------------------------------- |
+| [31:1]  | -             | Reserved.                                                      |
+| [0]     | Enable        | Interrupt signaling: 0 - Disable. 1 - Enable.                  |
 
-\struct  mmu_region_attributes_Type
+\var __IM uint32_t GICInterface_Type::C_IAR
+\details CPU Interface Interrupt Acknowledge Register
 
-\def section_normal(descriptor_l1, region) 
-\def section_normal_cod(descriptor_l1, region)
-\def section_normal_ro(descriptor_l1, region)
-\def section_normal_rw(descriptor_l1, region)
-\def section_so(descriptor_l1, region)
-\def section_device_ro(descriptor_l1, region)
-\def section_device_rw(descriptor_l1, region)
-\def page4k_device_rw(descriptor_l1, descriptor_l2, region)
-\def page64k_device_rw(descriptor_l1, descriptor_l2, region) 
-*/
-/** @} */
-/* end group MMU_defs_gr */
+| Bits    | Name          | Function                                                       |
+| :------ | :------------ | :------------------------------------------------------------- |
+| [31:24] | -             | Reserved.                                                      |
+| [23:0]  | INTID         | The interrupt number of the signaled interrupt.                |
 
-/* start grouping functions */
-/**
-@{
-*/
+\var __OM uint32_t GICInterface_Type::C_EOIR
+\details CPU Interface End Of Interrupt Register
 
-/**
-\fn __STATIC_INLINE int MMU_XNSection(uint32_t *descriptor_l1, mmu_execute_Type xn)
-\details 
-  The function sets section execution-never attribute
+| Bits    | Name          | Function                                                       |
+| :------ | :------------ | :------------------------------------------------------------- |
+| [31:24] | -             | Reserved.                                                      |
+| [23:0]  | INTID         | The interrupt number of the finished interrupt.                |
+ 
+ \var __IM uint32_t GICInterface_Type::C_HPPIR
+\details CPU Interface Highest Priority Pending Interrupt Register
 
-\fn __STATIC_INLINE int MMU_DomainSection(uint32_t *descriptor_l1, uint8_t domain)
-\details 
-The function sets section domain.
+| Bits    | Name          | Function                                                       |
+| :------ | :------------ | :------------------------------------------------------------- |
+| [31:24] | -             | Reserved.                                                      |
+| [23:0]  | INTID         | The INTID of the signaled interrupt.                           |
 
-\fn __STATIC_INLINE int MMU_PSection(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
-\details
-  The function sets section parity check
+\var  __IM uint32_t GICInterface_Type::C_IIDR
+\details CPU Interface Identification Register
 
-\fn __STATIC_INLINE int MMU_APSection(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
-\details 
-The function sets section access privileges
+| Bits    | Name          | Function                                                       |
+| :------ | :------------ | :------------------------------------------------------------- |
+| [31:20] | ProductID     | An IMPLEMENTATION DEFINED product identifier                   |
+| [19:16] | Arch_version  | The version of the GIC architecture that is implemented.       |
+| [15:12] | Revision      | An IMPLEMENTATION DEFINED revision number for the CPU interface. |
+| [11:0]  | Implementer   | Contains the JEP106 code of the company that implemented the CPU interface. |
 
-\fn __STATIC_INLINE int MMU_SharedSection(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
-\details
-  The function sets section shareability
 
-\fn __STATIC_INLINE int MMU_GlobalSection(uint32_t *descriptor_l1, mmu_global_Type g_bit)
-\details
-  The function sets section Global attribute
+\var __IOM uint32_t GICInterface_Type::C_PMR
+\details CPU Interface Priority Mask Register
 
-\fn __STATIC_INLINE int MMU_SecureSection(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
-\details
-  The function sets section Global attribute
+| Bits    | Name          | Function                                                       |
+| :------ | :------------ | :------------------------------------------------------------- |
+| [31:8]  | -             | Reserved.                                                      |
+| [7:0]   | Priority      | The priority mask level for the CPU interface.                 |
 
-\fn __STATIC_INLINE int MMU_XNPage(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
-\details
-  The function sets 4k/64k page execution-never attribute
+\note IMPLEMENTATION DEFINED unsupported priority bits might be RAZ/WI.
+ 
+\var __IOM uint32_t GICInterface_Type::C_BPR
+\details CPU Interface Binary Point Register
 
-\fn __STATIC_INLINE int MMU_DomainPage(uint32_t *descriptor_l1, uint8_t domain)
-\details
-  The function sets 4k/64k page domain
+| Bits    | Name          | Function                                                       |
+| :------ | :------------ | :------------------------------------------------------------- |
+| [31:3]  | -             | Reserved.                                                      |
+| [2:0]   | Binary_Point  | Controls how the 8-bit interrupt priority field is split into a group priority field and a subpriority field. |
 
-\fn __STATIC_INLINE int MMU_PPage(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
-\details
-  The function sets 4k/64k page parity check
+The binary point (values 0-7) defines the amount of priority bits used as subpriority. Please
+refer to the section Interrupt prioritization in the
+<a href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0048b/index.html">ARM Generic Interrupt Controller Architecture Specificaton</a>
+for details.
 
-\fn __STATIC_INLINE int MMU_APPage(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
-\details
-  The function sets 4k/64k page access privileges
-\fn __STATIC_INLINE int MMU_SharedPage(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
-\details
-  The function sets 4k/64k page shareability
+\var __IOM uint32_t GICInterface_Type::C_ABPR
+\details CPU Interface Aliased Binary Point Register
+\see GICInterface_Type::C_BPR
 
-\fn __STATIC_INLINE int MMU_GlobalPage(uint32_t *descriptor_l2, mmu_global_Type g_bit)
-\details
-  The function sets 4k/64k page Global attribute
+\var __OM uint32_t GICInterface_Type::C_AEOIR
+\details CPU Interface Aliased End Of Interrupt Register
+\see GICInterface_Type::C_EOIR
 
-\fn __STATIC_INLINE int MMU_SecurePage(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
-\details
-  The function sets 4k/64k page Global attribute
+\var __IM uint32_t GICInterface_Type::C_AHPPIR
+\details CPU Interface Aliased Highest Priority Pending Interrupt Register
+\see GICInterface_Type::C_HPPIR
 
-\fn __STATIC_INLINE int MMU_MemorySection(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
-\details
-  The function sets section memory attributes
+\var __IM uint32_t GICInterface_Type::C_AIAR
+\details CPU Interface Aliased Interrupt Acknowledge Register
+\see GICInterface_Type::C_IAR
 
-\fn __STATIC_INLINE int MMU_MemoryPage(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
-\details
-  The function sets 4k/64k page memory attributes
+\var __IOM uint32_t GICInterface_Type::C_APR[4]
+\details CPU Interface Active Priorities Registers
+\note The register values are IMPLEMENTATION DEFINED.
 
-\fn __STATIC_INLINE int MMU_GetSectionDescriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
-\details
-  The function creates a section descriptor.
+\var __OM uint32_t GICInterface_Type::C_DIR
+\details CPU Interface Deactivate Interrupt Register
 
-\fn __STATIC_INLINE int MMU_GetPageDescriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
-\details
-  The function creates a 4k/64k page descriptor.
-  Assumptions:
-  - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
-  - Functions always return 0
+| Bits    | Name  | Function                                                       |
+| :------ | :---- | :------------------------------------------------------------- |
+| [31:24] | -     | Reserved.                                                      |
+| [23:0]  | INTID | The INTID of the interrupt to be disabled.                     |
 
-\fn __STATIC_INLINE void MMU_TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
-\fn __STATIC_INLINE void MMU_TTPage4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
-\fn __STATIC_INLINE void MMU_TTPage64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
-\fn __STATIC_INLINE void MMU_Enable(void) 
-\details 
-   Set M bit 0 to enable the MMU
-   Set AFE bit to enable simplified access permissions model
-   Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
+\var __IOM uint32_t GICInterface_Type::C_NSAPR[4]
+\details CPU Interface Non-secure Active Priorities Registers
+\note The register values are IMPLEMENTATION DEFINED.
+\see GICInterface_Type::C_APR[4]
 
-\fn __STATIC_INLINE void MMU_Disable(void)
+\var __IM uint32_t GICInterface_Type::C_RPR
+\details CPU Interface Running Priority Register
 
-\fn __STATIC_INLINE void MMU_InvalidateTLB(void) 
+| Bits    | Name     | Function                                                       |
+| :------ | :------- | :------------------------------------------------------------- |
+| [31:8]  | -        | Reserved.                                                      |
+| [7:0]   | Priority | The current running priority on the CPU interface.             |
+
+\var __IOM uint32_t GICInterface_Type::C_STATUSR
+\details CPU Interface Status Register
+
+| Bits    | Name     | Function                                                       |
+| :------ | :------- | :------------------------------------------------------------- |
+| [31:5]  | -        | Reserved.                                                      |
+| [4]     | ASV      | Attempted security violation.                                  |
+| [3]     | WROD     | Write to an RO location.                                       |
+| [2]     | RWOD     | Read of a WO location.                                         |
+| [1]     | WRD      | Write to a reserved location.                                  |
+| [0]     | RRD      | Read of a reserved location.                                   |
 */
 
-/** @} */
-/* end of MMU_func_gr */
+/* ########################## GICDistributor_Type Member ########################## */
+/**
+\var __IOM uint32_t GICDistributor_Type::D_CTLR
+\details Distributor Control Register
 
-/** @} */
-/* end of MMU_functions */
+When access is Secure, in a system that supports two Security states:
+
+| Bits    | Name          | Function                                                       |
+| :------ | :------------ | :------------------------------------------------------------- |
+| [31]    | RWP           | Indicates whether a register write is in progress or not.      |
+| [30:8]  | -             | Reserved.                                                      |
+| [7]     | EINWF         | Enable 1 of N Wakeup Functionality, if available.              |
+| [6]     | DS            | Disable Security.                                              |
+| [5]     | ARE_NS        | Affinity Routing Enable, Non-secure state.                     |
+| [4]     | ARE_S         | Affinity Routing Enable, Secure state.                         |
+| [3]     | -             | Reserved.                                                      |
+| [2]     | EnableGrp1S   | Enable Secure Group 1 interrupts.                              |
+| [1]     | EnableGrp1NS  | Enable Non-secure Group 1 interrupts.                          |
+| [0]     | EnableGrp0    | Enable Group 0 interrupts.                                     |
+
+When access is Non-secure, in a system that supports two Security states:
+
+| Bits    | Name          | Function                                                       |
+| :------ | :------------ | :------------------------------------------------------------- |
+| [31]    | RWP           | Indicates whether a register write is in progress or not.      |
+| [30:5]  | -             | Reserved.                                                      |
+| [4]     | ARE_NS        | Affinity Routing Enable, Non-secure state.                     |
+| [3:2]   | -             | Reserved.                                                      |
+| [1]     | EnableGrp1A   | Enable Non-secure Group 1 interrupts.                          |
+| [0]     | EnableGrp1    | Enable Non-secure Group 1 interrupts.                          |
+
+When in a system that supports only a single Security state:
+
+| Bits    | Name          | Function                                                       |
+| :------ | :------------ | :------------------------------------------------------------- |
+| [31]    | RWP           | Indicates whether a register write is in progress or not.      |
+| [30:8]  | -             | Reserved.                                                      |
+| [7]     | EINWF         | Enable 1 of N Wakeup Functionality, if available.              |
+| [6]     | DS            | Disable Security.                                              |
+| [5]     | -             | Reserved.                                                      |
+| [4]     | ARE           | Affinity Routing Enable.                                       |
+| [3:2]   | -             | Reserved.                                                      |
+| [1]     | EnableGrp1    | Enable Group 1 interrupts.                                     |
+| [0]     | EnableGrp0    | Enable Group 0 interrupts.                                     |
+
+\var __IM uint32_t GICDistributor_Type::D_TYPER
+\details Interrupt Controller Type Register
+
+| Bits    | Name          | Function                                                       |
+| :------ | :------------ | :------------------------------------------------------------- |
+| [31:16] | -             | Reserved.                                                      |
+| [15:11] | LSPI          | Maximum number of lockable shared interrupts.                  |
+| [10]    | SecurityExtn  | Security Extensions: 0 - not implemented. 1 - implemented.     |
+| [9:8]   | -             | Reserved.                                                      |
+| [7:5]   | CPUNumber     | Number of implemented CPU interfaces [=CPUNumber+1]            |
+| [4:0]   | ITLinesNumber | Maximum number of interrups supported [=32*(ITLinesNumber+1)]. |
+
+\var __IM uint32_t GICDistributor_Type::D_IIDR
+\details Distributor Implementer Identification Register
+
+| Bits    | Name          | Function                                                       |
+| :------ | :------------ | :------------------------------------------------------------- |
+| [31:24] | ProductID     | An IMPLEMENTATION DEFINED product identifier                   |
+| [23:20] | -             | Reserved.                                                      |
+| [19:16] | Variant       | An IMPLEMENTATION DEFINED variant number.                      |
+| [15:12] | Revision      | An IMPLEMENTATION DEFINED revision number.                     |
+| [11:0]  | Implementer   | Contains the JEP106 code of the company implemented the GICD.  |
+
+\var __IOM uint8_t GICDistributor_Type::D_ITARGETSR[1020]
+\details Interrupt Processor Targets Registers
+
+Each bit in the target field corresponds to one CPU interface. A CPU targets field bit that corresponds
+to an unimplemented CPU interface is RAZ/WI.
 
+| CPU target field value | Interrupt targets |
+| :--------------------- | :---------------- |
+| 0bxxxxxxx1             | CPU interface 0   |
+| 0bxxxxxx1x             | CPU interface 1   |
+| 0bxxxxx1xx             | CPU interface 2   |
+| 0bxxxx1xxx             | CPU interface 3   |
+| 0bxxx1xxxx             | CPU interface 4   |
+| 0bxx1xxxxx             | CPU interface 5   |
+| 0bx1xxxxxx             | CPU interface 6   |
+| 0b1xxxxxxx             | CPU interface 7   |
+
+\var __IOM uint32_t GICDistributor_Type::D_IGROUPR[32]
+\details Interrupt Group Registers
+
+Each bit corresponds to one interrupt:
+ - Register index is given by INTID/32
+ - Bit number is given by INTID%32
+ 
+And the value denotes:
+- 0 When \ref GICDistributor_Type::D_CTLR "D_CTLR".DS==1, the corresponding interrupt is Group 0\n
+    When \ref GICDistributor_Type::D_CTLR "D_CTLR".DS==0, the corresponding interrupt is Secure.
+- 1 When \ref GICDistributor_Type::D_CTLR "D_CTLR".DS==1, the corresponding interrupt is Group 1.\n
+    When \ref GICDistributor_Type::D_CTLR "D_CTLR".DS==0, the corresponding interrupt is Non-secure Group 1.
+ 
+\var __IO uint32_t GICDistributor_Type::D_CLRSPI_NSR
+\details Clear Non-secure SPI Pending Register
+
+| Bits    | Name          | Function                                          |
+| :------ | :------------ | :------------------------------------------------ | 
+| [31:10] | -             | Reserved.                                         |
+| [9:0]   | INTID         | The interrupt number to clear pending state from. |
+
+\var __IO uint32_t GICDistributor_Type::D_CLRSPI_SR
+\details Clear Secure SPI Pending Register
+
+| Bits    | Name          | Function                                          |
+| :------ | :------------ | :------------------------------------------------ | 
+| [31:10] | -             | Reserved.                                         |
+| [9:0]   | INTID         | The interrupt number to clear pending state from. |
+
+\var __IOM uint32_t GICDistributor_Type::D_IGRPMODR[32]
+\details Interrupt Group Modifier Registers
+
+Each bit corresponds to one interrupt:
+ - Register index is given by INTID/32
+ - Bit number is given by INTID%32
+ 
+\var __IOM uint64_t GICDistributor_Type::D_IROUTER[988]
+\details Interrupt Routing Registers
+
+| Bits    | Name          | Function                                                      |
+| :------ | :------------ | :------------------------------------------------------------ | 
+| [63:40] | -             | Reserved.                                                     |
+| [39:32] | Aff3          | Affinity level 3, the least significant affinity level field. |
+| [31]    | IRM           | Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy. |
+| [30:24] | -             | Reserved.                                                     |
+| [23:16] | Aff2          | Affinity level 2, an intermediate affinity level field.       | 
+| [15:8]  | Aff1          | Affinity level 1, an intermediate affinity level field.       |
+| [7:0]   | Aff0          | Affinity level 0, the most significant affinity level field.  |
+
+\var __IOM uint32_t GICDistributor_Type::D_NSACR[64]
+\details Non-secure Access Control Registers
+
+Each two bits corresponds to one interrupt:
+ - Register index is given by INTID/16
+ - Bit number is given by 2*INTID%16
+
+The possible values of each 2-bit field are:
+ - 00 - Non-secure accesses to all fields associated with the corresponding interrupt are permitted.
+ - 01 - Non-secure accesses are only permitted to requesting fields.
+ - 10 - As 01, additionally accesses to clearing field are permitted.
+ - 11 - As 10, additionally accesses to target and routing fields are permitted.
+ 
+\var __IO uint32_t GICDistributor_Type::D_SETSPI_NSR
+\details Set Non-secure SPI Pending Register
+
+| Bits    | Name          | Function                                          |
+| :------ | :------------ | :------------------------------------------------ | 
+| [31:10] | -             | Reserved.                                         |
+| [9:0]   | INTID         | The interrupt number to set pending state for.    |
+
+\var __IO uint32_t GICDistributor_Type::D_SETSPI_SR
+\details Set Secure SPI Pending Register
+
+| Bits    | Name          | Function                                          |
+| :------ | :------------ | :------------------------------------------------ | 
+| [31:10] | -             | Reserved.                                         |
+| [9:0]   | INTID         | The interrupt number to set pending state for.    |
+
+\var __IOM uint8_t GICDistributor_Type::D_SPENDSGIR[16]
+\details SGI Set-Pending Registers
+Each register corresponds to one software generated interrupt (SGI).
+
+Reading from this register reveals
+ - 0 - interrupt is not pending
+ - 1 - interrupt is pending
+ 
+Writing to this register causes
+ - 0 - no effect
+ - 1 - adds the pending state
+ 
+\var __IOM uint8_t GICDistributor_Type::D_CPENDSGIR[16]
+\details SGI Clear-Pending Registers
+Each register corresponds to one software generated interrupt (SGI).
+
+Reading from this register reveals
+ - 0 - interrupt is not pending
+ - 1 - interrupt is pending
+ 
+Writing to this register causes
+ - 0 - no effect
+ - 1 - removes the pending state
+
+\var __IOM uint32_t GICDistributor_Type::D_STATUSR
+\details Error Reporting Status Register
+
+| Bits    | Name          | Function                                          |
+| :------ | :------------ | :------------------------------------------------ | 
+| [31:4]  | -             | Reserved.                                         |
+| [3]     | WROD          | Write to an RO location.                          |
+| [2]     | RWOD          | Read of a WO location.                            |
+| [1]     | WRD           | Write to a reserved location.                     |
+| [0]     | RRD           | Read of a reserved location.                      |
+
+\var __IOM uint32_t GICDistributor_Type::D_ISENABLER[32]
+\details Interrupt Set-Enable Registers
+
+Each bit corresponds to one interrupt:
+ - Register index is given by INTID/32
+ - Bit number is given by INTID%32
+
+\note Bits corresponding to unimplemented interrupts are RAZ/WI.
+
+\var __IOM uint32_t GICDistributor_Type::D_ICENABLER[32]
+\details Interrupt Clear-Enable Registers
+
+Each bit corresponds to one interrupt:
+ - Register index is given by INTID/32
+ - Bit number is given by INTID%32
+
+\note Bits corresponding to unimplemented interrupts are RAZ/WI.
+
+\var __IOM uint32_t GICDistributor_Type::D_ISPENDR[32]
+\details Interrupt Set-Pending Registers
+
+Each bit corresponds to one interrupt:
+ - Register index is given by INTID/32
+ - Bit number is given by INTID%32
+
+\note Bits corresponding to unimplemented interrupts are RAZ/WI.
+
+\var __IOM uint32_t GICDistributor_Type::D_ICPENDR[32]
+\details Interrupt Clear-Pending Registers
+
+Each bit corresponds to one interrupt:
+ - Register index is given by INTID/32
+ - Bit number is given by INTID%32
+ 
+\note Bits corresponding to unimplemented interrupts are RAZ/WI.
+
+\var __IOM uint32_t GICDistributor_Type::D_ICFGR[64]
+\details Interrupt Configuration Registers
+
+Each interrupt can be configured by two corresponding bits:
+
+| Bits           | Name          | Function                                                       |
+| :------------- | :------------ | :------------------------------------------------------------- |
+| [2*INTID%16+1] | Edge          | Interrupt is: 0 - level sensitive, 1 - edge triggered          |
+| [2*INTID%16]   | Model         | 0 - N-N Model, 1 - 1-N Model; RAZ/WI when unsupported          |
+
+\var __IOM uint8_t GICDistributor_Type::D_IPRIORITYR[1020]
+\details Interrupt Priority Registers
+
+A GIC might implement fewer than eight priority bits, but must implement at least bits [7:4] of each
+field. In each field, unimplemented bits are RAZ/WI.
+
+\note A register field corresponding to an unimplemented interrupt is RAZ/WI.
+
+\var __IOM uint32_t GICDistributor_Type::D_ISACTIVER[32]
+\details Interrupt Set-Active Registers
+
+Each bit corresponds to one interrupt:
+ - Register index is given by INTID/32
+ - Bit number is given by INTID%32
+ 
+\note Bits corresponding to unimplemented interrupts are RAZ/WI.
+
+\var __IOM uint32_t GICDistributor_Type::D_ICACTIVER[32]
+\details Interrupt Clear-Active Registers
+
+Each bit corresponds to one interrupt:
+ - Register index is given by INTID/32
+ - Bit number is given by INTID%32
+
+\note Bits corresponding to unimplemented interrupts are RAZ/WI.
+
+\var __OM uint32_t GICDistributor_Type::D_SGIR
+\details Software Generated Interrupt Register
+
+| Bits    | Name             | Function                                                         |
+| :------ | :------------    | :--------------------------------------------------------------- |
+| [31:26] | -                | Reserved.                                                        |
+| [25:24] | TargetFilterList | Determines how the Distributor processes the requested SGI.      |
+| [23:16] | CPUTargetList    | When TargetListFilter is 00, this field defines the CPU interfaces to which the Distributor must forward the interrupt. |
+| [15]    | NSATT            | Specifies the required group of the SGI.                         |
+| [14:4]  | -                | Reserved.                                                        |
+| [3:0]   | INTID            | The INTID of the SGI to forward to the specified CPU interfaces. |
+
+Refer to \ref GICDistributor_Type::D_ITARGETSR "D_ITARGETSR" for details on TargetFilterList field.
+*/
+
+
+/* ########################## Private Timer Member ########################## */
 /**
-@}
+
+\var uint32_t CNTP_CTL_Type::ENABLE
+\details Enables the timer.
+
+Permitted values are:
+ - 0 - Timer disabled.
+ - 1 - Timer enabled.
+
+\var uint32_t CNTP_CTL_Type::IMASK
+\details Timer output signal mask bit. 
+
+Permitted values are:
+ - 0 - Timer output signal is not masked.
+ - 1 - Timer output signal is masked.
+
+
+\var uint32_t CNTP_CTL_Type::ISTATUS
+\details The status of the timer.
+
+This bit indicates whether the timer condition is asserted:
+ - 0 - Timer condition is not asserted.
+ - 1 - Timer condition is asserted.
 */
+
 /* end of CMSIS_Core_FunctionInterface  -   currently disabled */