Core(M): Aligned PSPLIM and MSPLIM access functions among compilers and device variants.

Non-secure PSPLIM and MSPLIM are RAZ/WI if Main Extensions are not implemented.
According to an advice from ATEG team in SDDKW-43532 we shall not rely on hardware RAZ/WI behaviour.
Thus the access functions now mimic RAZ/WI behaviour if the registers are not available.
- Fixed/adopted implementation for ArmClang, GCC and IAR.
- Enhanced CoreValidation tests.
- Enhanced doxygen documentation.

CMSIS/Core/Include/cmsis_armclang.h

@@ -567,113 +567,175 @@ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
 
 /**
   \brief   Get Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+  
   \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
   \return               PSPLIM Register value
  */
 __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
 {
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
   register uint32_t result;
-
   __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
-  return(result);
+  return result;
+#endif
 }
 
-
-#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
-     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
 /**
   \brief   Get Process Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
   \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
   \return               PSPLIM Register value
  */
 __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
 {
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
   register uint32_t result;
-
   __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
-  return(result);
+  return result;
+#endif
 }
 #endif
 
 
 /**
   \brief   Set Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+  
   \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
  */
 __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
 {
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
   __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
 }
 
 
-#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
-     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
 /**
   \brief   Set Process Stack Pointer (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
   \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
  */
 __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
 {
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
   __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
 }
 #endif
 
 
 /**
   \brief   Get Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
   \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
   \return               MSPLIM Register value
  */
 __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
 {
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
   register uint32_t result;
-
   __ASM volatile ("MRS %0, msplim" : "=r" (result) );
-
-  return(result);
+  return result;
+#endif
 }
 
 
-#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
-     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
 /**
   \brief   Get Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
   \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
   \return               MSPLIM Register value
  */
 __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
 {
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
   register uint32_t result;
-
   __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
-  return(result);
+  return result;
+#endif
 }
 #endif
 
 
 /**
   \brief   Set Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
   \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
   \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
  */
 __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
 {
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
   __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
 }
 
 
-#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
-     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
 /**
   \brief   Set Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
   \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
   \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
  */
 __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
 {
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
   __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
 }
 #endif
 

CMSIS/Core/Include/cmsis_gcc.h

@@ -582,113 +582,175 @@ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
 
 /**
   \brief   Get Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+  
   \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
   \return               PSPLIM Register value
  */
 __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
 {
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
   register uint32_t result;
-
   __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
-  return(result);
+  return result;
+#endif
 }
 
-
-#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
-     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
 /**
   \brief   Get Process Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
   \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
   \return               PSPLIM Register value
  */
 __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
 {
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
   register uint32_t result;
-
   __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
-  return(result);
+  return result;
+#endif
 }
 #endif
 
 
 /**
   \brief   Set Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+  
   \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
  */
 __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
 {
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
   __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
 }
 
 
-#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
-     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
 /**
   \brief   Set Process Stack Pointer (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
   \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
  */
 __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
 {
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
   __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
 }
 #endif
 
 
 /**
   \brief   Get Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
   \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
   \return               MSPLIM Register value
  */
 __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
 {
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
   register uint32_t result;
-
   __ASM volatile ("MRS %0, msplim" : "=r" (result) );
-
-  return(result);
+  return result;
+#endif
 }
 
 
-#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
-     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
 /**
   \brief   Get Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
   \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
   \return               MSPLIM Register value
  */
 __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
 {
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
   register uint32_t result;
-
   __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
-  return(result);
+  return result;
+#endif
 }
 #endif
 
 
 /**
   \brief   Set Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
   \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
   \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
  */
 __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
 {
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
   __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
 }
 
 
-#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
-     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
 /**
   \brief   Set Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
   \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
   \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
  */
 __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
 {
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
   __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
 }
 #endif
 

CMSIS/Core/Include/cmsis_iccarm.h

@@ -284,7 +284,7 @@ __packed struct  __iar_u32 { uint32_t v; };
   #define __get_IPSR()                (__arm_rsr("IPSR"))
   #define __get_MSP()                 (__arm_rsr("MSP"))
   #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-       (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
     // without main extensions, the non-secure MSPLIM is RAZ/WI
     #define __get_MSPLIM()            (0U)
   #else
@@ -294,7 +294,7 @@ __packed struct  __iar_u32 { uint32_t v; };
   #define __get_PSP()                 (__arm_rsr("PSP"))
 
   #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-       (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
     // without main extensions, the non-secure PSPLIM is RAZ/WI
     #define __get_PSPLIM()            (0U)
   #else
@@ -310,7 +310,7 @@ __packed struct  __iar_u32 { uint32_t v; };
   #define __set_MSP(VALUE)            (__arm_wsr("MSP", (VALUE)))
 
   #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-       (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
     // without main extensions, the non-secure MSPLIM is RAZ/WI
     #define __set_MSPLIM(VALUE)       ((void)(VALUE))
   #else
@@ -319,7 +319,7 @@ __packed struct  __iar_u32 { uint32_t v; };
   #define __set_PRIMASK(VALUE)        (__arm_wsr("PRIMASK", (VALUE)))
   #define __set_PSP(VALUE)            (__arm_wsr("PSP", (VALUE)))
   #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-       (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
     // without main extensions, the non-secure PSPLIM is RAZ/WI
     #define __set_PSPLIM(VALUE)       ((void)(VALUE))
   #else

CMSIS/CoreValidation/Include/cmsis_cv.h

@@ -51,7 +51,9 @@ extern void TC_CoreInstr_USAT (void);
          (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
 
     extern void TC_CoreFunc_PSPLIM (void);
+    extern void TC_CoreFunc_PSPLIM_NS (void);
     extern void TC_CoreFunc_MSPLIM (void);
+    extern void TC_CoreFunc_MSPLIM_NS (void);
 
     #endif
     

CMSIS/CoreValidation/Source/CV_CoreFunc.c

@@ -286,6 +286,36 @@ void TC_CoreFunc_PSPLIM (void) {
 #endif
 }
 
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+/**
+\brief Test case: TC_CoreFunc_PSPLIM_NS
+\details
+- Check if __TZ_get_PSPLIM_NS and __TZ_set_PSPLIM_NS instrinsic can be used to manipulate process stack pointer limit.
+*/
+void TC_CoreFunc_PSPLIM_NS (void) {
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+  uint32_t orig;
+  uint32_t psplim;
+  uint32_t result;
+
+  orig = __TZ_get_PSPLIM_NS();
+
+  psplim = orig + 0x12345678U;
+  __TZ_set_PSPLIM_NS(psplim);
+
+  result = __TZ_get_PSPLIM_NS();
+
+  __TZ_set_PSPLIM_NS(orig);
+
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  ASSERT_TRUE(result == 0U);
+#else
+  ASSERT_TRUE(result == psplim);
+#endif
+#endif
+}
+
 /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
 /**
 \brief Test case: TC_CoreFunc_MSPLIM
@@ -324,6 +354,36 @@ void TC_CoreFunc_MSPLIM (void) {
 
 #endif
 
+/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
+/**
+\brief Test case: TC_CoreFunc_MSPLIM_NS
+\details
+- Check if __TZ_get_MSPLIM_NS and __TZ_set_MSPLIM_NS instrinsic can be used to manipulate process stack pointer limit.
+*/
+void TC_CoreFunc_MSPLIM_NS (void) {
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+  uint32_t orig;
+  uint32_t msplim;
+  uint32_t result;
+
+  orig = __TZ_get_MSPLIM_NS();
+
+  msplim = orig + 0x12345678U;
+  __TZ_set_MSPLIM_NS(msplim);
+
+  result = __TZ_get_MSPLIM_NS();
+
+  __TZ_set_MSPLIM_NS(orig);
+
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  ASSERT_TRUE(result == 0U);
+#else
+  ASSERT_TRUE(result == msplim);
+#endif
+#endif
+}
+
 /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
 /**
 \brief Test case: TC_CoreFunc_PRIMASK

CMSIS/CoreValidation/Source/Config/CV_Config.h

@@ -42,14 +42,16 @@
 // <q13> TC_CoreFunc_PSP
 // <q14> TC_CoreFunc_MSP
 // <q13> TC_CoreFunc_PSPLIM
-// <q14> TC_CoreFunc_MSPLIM
-// <q15> TC_CoreFunc_PRIMASK
-// <q16> TC_CoreFunc_FAULTMASK
-// <q17> TC_CoreFunc_BASEPRI
-// <q18> TC_CoreFunc_FPSCR
+// <q14> TC_CoreFunc_PSPLIM_NS
+// <q15> TC_CoreFunc_MSPLIM
+// <q16> TC_CoreFunc_MSPLIM_NS
+// <q17> TC_CoreFunc_PRIMASK
+// <q18> TC_CoreFunc_FAULTMASK
+// <q19> TC_CoreFunc_BASEPRI
+// <q20> TC_CoreFunc_FPSCR
 //
-// <q19> TC_MPU_SetClear
-// <q20> TC_MPU_Load
+// <q21> TC_MPU_SetClear
+// <q22> TC_MPU_Load
 #define TC_COREINSTR_NOP_EN         1
 #define TC_COREINSTR_REV_EN         1
 #define TC_COREINSTR_REV16_EN       1
@@ -67,7 +69,9 @@
 #define TC_COREFUNC_PSP_EN          1
 #define TC_COREFUNC_MSP_EN          1
 #define TC_COREFUNC_PSPLIM_EN       1
+#define TC_COREFUNC_PSPLIM_NS_EN    1
 #define TC_COREFUNC_MSPLIM_EN       1
+#define TC_COREFUNC_MSPLIM_NS_EN    1
 #define TC_COREFUNC_PRIMASK_EN      1
 #define TC_COREFUNC_FAULTMASK_EN    1
 #define TC_COREFUNC_BASEPRI_EN      1

CMSIS/CoreValidation/Source/cmsis_cv.c

@@ -41,83 +41,85 @@ static void TS_Init (void) {
  *----------------------------------------------------------------------------*/
 static TEST_CASE TC_LIST[] = {
 #ifdef RTE_CV_COREINSTR
-  TCD ( TC_CoreInstr_NOP,      TC_COREINSTR_NOP_EN      ),
-  TCD ( TC_CoreInstr_REV,      TC_COREINSTR_REV_EN      ),
-  TCD ( TC_CoreInstr_REV16,    TC_COREINSTR_REV16_EN    ),
-  TCD ( TC_CoreInstr_REVSH,    TC_COREINSTR_REVSH_EN    ),
-  TCD ( TC_CoreInstr_ROR,      TC_COREINSTR_ROR_EN      ),
-  TCD ( TC_CoreInstr_RBIT,     TC_COREINSTR_RBIT_EN     ),
-  TCD ( TC_CoreInstr_CLZ,      TC_COREINSTR_CLZ_EN      ),
-  TCD ( TC_CoreInstr_SSAT,     TC_COREINSTR_SSAT_EN     ),
-  TCD ( TC_CoreInstr_USAT,     TC_COREINSTR_USAT_EN     ),
+  TCD ( TC_CoreInstr_NOP,                     TC_COREINSTR_NOP_EN                ),
+  TCD ( TC_CoreInstr_REV,                     TC_COREINSTR_REV_EN                ),
+  TCD ( TC_CoreInstr_REV16,                   TC_COREINSTR_REV16_EN              ),
+  TCD ( TC_CoreInstr_REVSH,                   TC_COREINSTR_REVSH_EN              ),
+  TCD ( TC_CoreInstr_ROR,                     TC_COREINSTR_ROR_EN                ),
+  TCD ( TC_CoreInstr_RBIT,                    TC_COREINSTR_RBIT_EN               ),
+  TCD ( TC_CoreInstr_CLZ,                     TC_COREINSTR_CLZ_EN                ),
+  TCD ( TC_CoreInstr_SSAT,                    TC_COREINSTR_SSAT_EN               ),
+  TCD ( TC_CoreInstr_USAT,                    TC_COREINSTR_USAT_EN               ),
 #endif
 #ifdef RTE_CV_COREFUNC
   #if defined(__CORTEX_M)
-    TCD ( TC_CoreFunc_EnDisIRQ,  TC_COREFUNC_ENDISIRQ_EN  ),
-    TCD ( TC_CoreFunc_Control,   TC_COREFUNC_CONTROL_EN   ),
-    TCD ( TC_CoreFunc_IPSR,      TC_COREFUNC_IPSR_EN      ),
-    TCD ( TC_CoreFunc_APSR,      TC_COREFUNC_APSR_EN      ),
+    TCD ( TC_CoreFunc_EnDisIRQ,               TC_COREFUNC_ENDISIRQ_EN            ),
+    TCD ( TC_CoreFunc_Control,                TC_COREFUNC_CONTROL_EN             ),
+    TCD ( TC_CoreFunc_IPSR,                   TC_COREFUNC_IPSR_EN                ),
+    TCD ( TC_CoreFunc_APSR,                   TC_COREFUNC_APSR_EN                ),
 
-    TCD ( TC_CoreFunc_PSP,       TC_COREFUNC_PSP_EN       ),
-    TCD ( TC_CoreFunc_MSP,       TC_COREFUNC_MSP_EN       ),
+    TCD ( TC_CoreFunc_PSP,                    TC_COREFUNC_PSP_EN                 ),
+    TCD ( TC_CoreFunc_MSP,                    TC_COREFUNC_MSP_EN                 ),
 
     #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
          (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
 
-    TCD ( TC_CoreFunc_PSPLIM,    TC_COREFUNC_PSPLIM_EN    ),
-    TCD ( TC_CoreFunc_MSPLIM,    TC_COREFUNC_MSPLIM_EN    ),
+    TCD ( TC_CoreFunc_PSPLIM,                TC_COREFUNC_PSPLIM_EN               ),
+    TCD ( TC_CoreFunc_PSPLIM_NS,             TC_COREFUNC_PSPLIM_NS_EN            ),
+    TCD ( TC_CoreFunc_MSPLIM,                TC_COREFUNC_MSPLIM_EN               ),
+    TCD ( TC_CoreFunc_MSPLIM_NS,             TC_COREFUNC_MSPLIM_NS_EN            ),
 
     #endif
 
-    TCD ( TC_CoreFunc_PRIMASK,   TC_COREFUNC_PRIMASK_EN   ),
+    TCD ( TC_CoreFunc_PRIMASK,               TC_COREFUNC_PRIMASK_EN              ),
 
     #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
        (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
        (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
 
-      TCD ( TC_CoreFunc_FAULTMASK, TC_COREFUNC_FAULTMASK_EN ),
-      TCD ( TC_CoreFunc_BASEPRI,   TC_COREFUNC_BASEPRI_EN   ),
+      TCD ( TC_CoreFunc_FAULTMASK,           TC_COREFUNC_FAULTMASK_EN            ),
+      TCD ( TC_CoreFunc_BASEPRI,             TC_COREFUNC_BASEPRI_EN              ),
 
     #endif
 
     #if ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
        (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
 
-      TCD ( TC_CoreFunc_FPSCR,     TC_COREFUNC_FPSCR_EN     ),
+      TCD ( TC_CoreFunc_FPSCR,               TC_COREFUNC_FPSCR_EN                ),
 
     #endif
   #elif defined(__CORTEX_A)
-      TCD ( TC_CoreAFunc_IRQ,        TC_COREAFUNC_IRQ       ),
-      TCD ( TC_CoreAFunc_FPSCR,      TC_COREAFUNC_FPSCR     ),
-      TCD ( TC_CoreAFunc_CPSR,       TC_COREAFUNC_CPSR      ),
-      TCD ( TC_CoreAFunc_Mode,       TC_COREAFUNC_MODE      ),
-      TCD ( TC_CoreAFunc_SP,         TC_COREAFUNC_SP        ),
-      TCD ( TC_CoreAFunc_SP_usr,     TC_COREAFUNC_SP_USR    ),
-      TCD ( TC_CoreAFunc_FPEXC,      TC_COREAFUNC_FPEXC     ),
-      TCD ( TC_CoreAFunc_ACTLR,      TC_COREAFUNC_ACTLR     ),
-      TCD ( TC_CoreAFunc_CPACR,      TC_COREAFUNC_CPACR     ),
-      TCD ( TC_CoreAFunc_DFSR,       TC_COREAFUNC_DFSR      ),
-      TCD ( TC_CoreAFunc_IFSR,       TC_COREAFUNC_IFSR      ),
-      TCD ( TC_CoreAFunc_ISR,        TC_COREAFUNC_ISR       ),
-      TCD ( TC_CoreAFunc_CBAR,       TC_COREAFUNC_CBAR      ),
-      TCD ( TC_CoreAFunc_TTBR0,      TC_COREAFUNC_TTBR0     ),
-      TCD ( TC_CoreAFunc_DACR,       TC_COREAFUNC_DACR      ),
-      TCD ( TC_CoreAFunc_SCTLR,      TC_COREAFUNC_SCTLR     ),
-      TCD ( TC_CoreAFunc_ACTRL,      TC_COREAFUNC_ACTRL     ),
-      TCD ( TC_CoreAFunc_MPIDR,      TC_COREAFUNC_MPIDR     ),
-      TCD ( TC_CoreAFunc_VBAR,       TC_COREAFUNC_VBAR      ),
+      TCD ( TC_CoreAFunc_IRQ,                TC_COREAFUNC_IRQ                    ),
+      TCD ( TC_CoreAFunc_FPSCR,              TC_COREAFUNC_FPSCR                  ),
+      TCD ( TC_CoreAFunc_CPSR,               TC_COREAFUNC_CPSR                   ),
+      TCD ( TC_CoreAFunc_Mode,               TC_COREAFUNC_MODE                   ),
+      TCD ( TC_CoreAFunc_SP,                 TC_COREAFUNC_SP                     ),
+      TCD ( TC_CoreAFunc_SP_usr,             TC_COREAFUNC_SP_USR                 ),
+      TCD ( TC_CoreAFunc_FPEXC,              TC_COREAFUNC_FPEXC                  ),
+      TCD ( TC_CoreAFunc_ACTLR,              TC_COREAFUNC_ACTLR                  ),
+      TCD ( TC_CoreAFunc_CPACR,              TC_COREAFUNC_CPACR                  ),
+      TCD ( TC_CoreAFunc_DFSR,               TC_COREAFUNC_DFSR                   ),
+      TCD ( TC_CoreAFunc_IFSR,               TC_COREAFUNC_IFSR                   ),
+      TCD ( TC_CoreAFunc_ISR,                TC_COREAFUNC_ISR                    ),
+      TCD ( TC_CoreAFunc_CBAR,               TC_COREAFUNC_CBAR                   ),
+      TCD ( TC_CoreAFunc_TTBR0,              TC_COREAFUNC_TTBR0                  ),
+      TCD ( TC_CoreAFunc_DACR,               TC_COREAFUNC_DACR                   ),
+      TCD ( TC_CoreAFunc_SCTLR,              TC_COREAFUNC_SCTLR                  ),
+      TCD ( TC_CoreAFunc_ACTRL,              TC_COREAFUNC_ACTRL                  ),
+      TCD ( TC_CoreAFunc_MPIDR,              TC_COREAFUNC_MPIDR                  ),
+      TCD ( TC_CoreAFunc_VBAR,               TC_COREAFUNC_VBAR                   ),
   #endif
 #endif
 #ifdef RTE_CV_MPUFUNC
-  TCD ( TC_MPU_SetClear,       TC_MPU_SETCLEAR_EN       ),
-  TCD ( TC_MPU_Load,           TC_MPU_LOAD_EN           ),
+  TCD ( TC_MPU_SetClear,                     TC_MPU_SETCLEAR_EN                  ),
+  TCD ( TC_MPU_Load,                         TC_MPU_LOAD_EN                      ),
 #endif
 #ifdef RTE_CV_GENTIMER
-  TCD ( TC_GenTimer_CNTFRQ,     TC_GENTIMER_CNTFRQ    ),
-  TCD ( TC_GenTimer_CNTP_TVAL,  TC_GENTIMER_CNTP_TVAL ),
-  TCD ( TC_GenTimer_CNTP_CTL,   TC_GENTIMER_CNTP_CTL  ),
-  TCD ( TC_GenTimer_CNTPCT,     TC_GENTIMER_CNTPCT    ),
-  TCD ( TC_GenTimer_CNTP_CVAL,  TC_GENTIMER_CNTP_CVAL ),
+  TCD ( TC_GenTimer_CNTFRQ,                  TC_GENTIMER_CNTFRQ                  ),
+  TCD ( TC_GenTimer_CNTP_TVAL,               TC_GENTIMER_CNTP_TVAL               ),
+  TCD ( TC_GenTimer_CNTP_CTL,                TC_GENTIMER_CNTP_CTL                ),
+  TCD ( TC_GenTimer_CNTPCT,                  TC_GENTIMER_CNTPCT                  ),
+  TCD ( TC_GenTimer_CNTP_CVAL,               TC_GENTIMER_CNTP_CVAL               ),
 #endif
 };
 

CMSIS/CoreValidation/Tests/CV_Config.h

@@ -46,14 +46,16 @@
 // <q13> TC_CoreFunc_PSP
 // <q14> TC_CoreFunc_MSP
 // <q13> TC_CoreFunc_PSPLIM
-// <q14> TC_CoreFunc_MSPLIM
-// <q15> TC_CoreFunc_PRIMASK
-// <q16> TC_CoreFunc_FAULTMASK
-// <q17> TC_CoreFunc_BASEPRI
-// <q18> TC_CoreFunc_FPSCR
+// <q14> TC_CoreFunc_PSPLIM_NS
+// <q15> TC_CoreFunc_MSPLIM
+// <q16> TC_CoreFunc_MSPLIM_NS
+// <q17> TC_CoreFunc_PRIMASK
+// <q18> TC_CoreFunc_FAULTMASK
+// <q19> TC_CoreFunc_BASEPRI
+// <q20> TC_CoreFunc_FPSCR
 //
-// <q19> TC_MPU_SetClear
-// <q20> TC_MPU_Load
+// <q21> TC_MPU_SetClear
+// <q22> TC_MPU_Load
 #define TC_COREINSTR_NOP_EN         1
 #define TC_COREINSTR_REV_EN         1
 #define TC_COREINSTR_REV16_EN       1
@@ -70,8 +72,11 @@
 #define TC_COREFUNC_APSR_EN         1
 #define TC_COREFUNC_PSP_EN          1
 #define TC_COREFUNC_MSP_EN          1
+
 #define TC_COREFUNC_PSPLIM_EN       1
+#define TC_COREFUNC_PSPLIM_NS_EN    1
 #define TC_COREFUNC_MSPLIM_EN       1
+#define TC_COREFUNC_MSPLIM_NS_EN    1
 #define TC_COREFUNC_PRIMASK_EN      1
 #define TC_COREFUNC_FAULTMASK_EN    1
 #define TC_COREFUNC_BASEPRI_EN      1

CMSIS/CoreValidation/Tests/Cortex-M23/AC6/CV_Config.h

@@ -46,14 +46,16 @@
 // <q13> TC_CoreFunc_PSP
 // <q14> TC_CoreFunc_MSP
 // <q13> TC_CoreFunc_PSPLIM
-// <q14> TC_CoreFunc_MSPLIM
-// <q15> TC_CoreFunc_PRIMASK
-// <q16> TC_CoreFunc_FAULTMASK
-// <q17> TC_CoreFunc_BASEPRI
-// <q18> TC_CoreFunc_FPSCR
+// <q14> TC_CoreFunc_PSPLIM_NS
+// <q15> TC_CoreFunc_MSPLIM
+// <q16> TC_CoreFunc_MSPLIM_NS
+// <q17> TC_CoreFunc_PRIMASK
+// <q18> TC_CoreFunc_FAULTMASK
+// <q19> TC_CoreFunc_BASEPRI
+// <q20> TC_CoreFunc_FPSCR
 //
-// <q19> TC_MPU_SetClear
-// <q20> TC_MPU_Load
+// <q21> TC_MPU_SetClear
+// <q22> TC_MPU_Load
 #define TC_COREINSTR_NOP_EN         1
 #define TC_COREINSTR_REV_EN         1
 #define TC_COREINSTR_REV16_EN       1
@@ -70,8 +72,11 @@
 #define TC_COREFUNC_APSR_EN         1
 #define TC_COREFUNC_PSP_EN          1
 #define TC_COREFUNC_MSP_EN          1
+
 #define TC_COREFUNC_PSPLIM_EN       1
+#define TC_COREFUNC_PSPLIM_NS_EN    1
 #define TC_COREFUNC_MSPLIM_EN       1
+#define TC_COREFUNC_MSPLIM_NS_EN    1
 #define TC_COREFUNC_PRIMASK_EN      1
 #define TC_COREFUNC_FAULTMASK_EN    1
 #define TC_COREFUNC_BASEPRI_EN      1

CMSIS/CoreValidation/Tests/Cortex-M23/GCC/CV_Config.h

@@ -46,14 +46,16 @@
 // <q13> TC_CoreFunc_PSP
 // <q14> TC_CoreFunc_MSP
 // <q13> TC_CoreFunc_PSPLIM
-// <q14> TC_CoreFunc_MSPLIM
-// <q15> TC_CoreFunc_PRIMASK
-// <q16> TC_CoreFunc_FAULTMASK
-// <q17> TC_CoreFunc_BASEPRI
-// <q18> TC_CoreFunc_FPSCR
+// <q14> TC_CoreFunc_PSPLIM_NS
+// <q15> TC_CoreFunc_MSPLIM
+// <q16> TC_CoreFunc_MSPLIM_NS
+// <q17> TC_CoreFunc_PRIMASK
+// <q18> TC_CoreFunc_FAULTMASK
+// <q19> TC_CoreFunc_BASEPRI
+// <q20> TC_CoreFunc_FPSCR
 //
-// <q19> TC_MPU_SetClear
-// <q20> TC_MPU_Load
+// <q21> TC_MPU_SetClear
+// <q22> TC_MPU_Load
 #define TC_COREINSTR_NOP_EN         1
 #define TC_COREINSTR_REV_EN         1
 #define TC_COREINSTR_REV16_EN       1
@@ -70,8 +72,11 @@
 #define TC_COREFUNC_APSR_EN         1
 #define TC_COREFUNC_PSP_EN          1
 #define TC_COREFUNC_MSP_EN          1
+
 #define TC_COREFUNC_PSPLIM_EN       1
+#define TC_COREFUNC_PSPLIM_NS_EN    1
 #define TC_COREFUNC_MSPLIM_EN       1
+#define TC_COREFUNC_MSPLIM_NS_EN    1
 #define TC_COREFUNC_PRIMASK_EN      1
 #define TC_COREFUNC_FAULTMASK_EN    1
 #define TC_COREFUNC_BASEPRI_EN      1

CMSIS/CoreValidation/Tests/Cortex-M23/IAR/CV_Config.h

@@ -46,14 +46,16 @@
 // <q13> TC_CoreFunc_PSP
 // <q14> TC_CoreFunc_MSP
 // <q13> TC_CoreFunc_PSPLIM
-// <q14> TC_CoreFunc_MSPLIM
-// <q15> TC_CoreFunc_PRIMASK
-// <q16> TC_CoreFunc_FAULTMASK
-// <q17> TC_CoreFunc_BASEPRI
-// <q18> TC_CoreFunc_FPSCR
+// <q14> TC_CoreFunc_PSPLIM_NS
+// <q15> TC_CoreFunc_MSPLIM
+// <q16> TC_CoreFunc_MSPLIM_NS
+// <q17> TC_CoreFunc_PRIMASK
+// <q18> TC_CoreFunc_FAULTMASK
+// <q19> TC_CoreFunc_BASEPRI
+// <q20> TC_CoreFunc_FPSCR
 //
-// <q19> TC_MPU_SetClear
-// <q20> TC_MPU_Load
+// <q21> TC_MPU_SetClear
+// <q22> TC_MPU_Load
 #define TC_COREINSTR_NOP_EN         1
 #define TC_COREINSTR_REV_EN         1
 #define TC_COREINSTR_REV16_EN       1
@@ -70,8 +72,11 @@
 #define TC_COREFUNC_APSR_EN         1
 #define TC_COREFUNC_PSP_EN          1
 #define TC_COREFUNC_MSP_EN          1
+
 #define TC_COREFUNC_PSPLIM_EN       1
+#define TC_COREFUNC_PSPLIM_NS_EN    1
 #define TC_COREFUNC_MSPLIM_EN       1
+#define TC_COREFUNC_MSPLIM_NS_EN    1
 #define TC_COREFUNC_PRIMASK_EN      1
 #define TC_COREFUNC_FAULTMASK_EN    1
 #define TC_COREFUNC_BASEPRI_EN      1

CMSIS/CoreValidation/Tests/Cortex-M23NS/AC6/CV_Config.h

@@ -46,14 +46,16 @@
 // <q13> TC_CoreFunc_PSP
 // <q14> TC_CoreFunc_MSP
 // <q13> TC_CoreFunc_PSPLIM
-// <q14> TC_CoreFunc_MSPLIM
-// <q15> TC_CoreFunc_PRIMASK
-// <q16> TC_CoreFunc_FAULTMASK
-// <q17> TC_CoreFunc_BASEPRI
-// <q18> TC_CoreFunc_FPSCR
+// <q14> TC_CoreFunc_PSPLIM_NS
+// <q15> TC_CoreFunc_MSPLIM
+// <q16> TC_CoreFunc_MSPLIM_NS
+// <q17> TC_CoreFunc_PRIMASK
+// <q18> TC_CoreFunc_FAULTMASK
+// <q19> TC_CoreFunc_BASEPRI
+// <q20> TC_CoreFunc_FPSCR
 //
-// <q19> TC_MPU_SetClear
-// <q20> TC_MPU_Load
+// <q21> TC_MPU_SetClear
+// <q22> TC_MPU_Load
 #define TC_COREINSTR_NOP_EN         1
 #define TC_COREINSTR_REV_EN         1
 #define TC_COREINSTR_REV16_EN       1
@@ -70,8 +72,11 @@
 #define TC_COREFUNC_APSR_EN         1
 #define TC_COREFUNC_PSP_EN          1
 #define TC_COREFUNC_MSP_EN          1
+
 #define TC_COREFUNC_PSPLIM_EN       1
+#define TC_COREFUNC_PSPLIM_NS_EN    1
 #define TC_COREFUNC_MSPLIM_EN       1
+#define TC_COREFUNC_MSPLIM_NS_EN    1
 #define TC_COREFUNC_PRIMASK_EN      1
 #define TC_COREFUNC_FAULTMASK_EN    1
 #define TC_COREFUNC_BASEPRI_EN      1

CMSIS/CoreValidation/Tests/Cortex-M23NS/GCC/CV_Config.h

@@ -46,14 +46,16 @@
 // <q13> TC_CoreFunc_PSP
 // <q14> TC_CoreFunc_MSP
 // <q13> TC_CoreFunc_PSPLIM
-// <q14> TC_CoreFunc_MSPLIM
-// <q15> TC_CoreFunc_PRIMASK
-// <q16> TC_CoreFunc_FAULTMASK
-// <q17> TC_CoreFunc_BASEPRI
-// <q18> TC_CoreFunc_FPSCR
+// <q14> TC_CoreFunc_PSPLIM_NS
+// <q15> TC_CoreFunc_MSPLIM
+// <q16> TC_CoreFunc_MSPLIM_NS
+// <q17> TC_CoreFunc_PRIMASK
+// <q18> TC_CoreFunc_FAULTMASK
+// <q19> TC_CoreFunc_BASEPRI
+// <q20> TC_CoreFunc_FPSCR
 //
-// <q19> TC_MPU_SetClear
-// <q20> TC_MPU_Load
+// <q21> TC_MPU_SetClear
+// <q22> TC_MPU_Load
 #define TC_COREINSTR_NOP_EN         1
 #define TC_COREINSTR_REV_EN         1
 #define TC_COREINSTR_REV16_EN       1
@@ -70,8 +72,11 @@
 #define TC_COREFUNC_APSR_EN         1
 #define TC_COREFUNC_PSP_EN          1
 #define TC_COREFUNC_MSP_EN          1
+
 #define TC_COREFUNC_PSPLIM_EN       1
+#define TC_COREFUNC_PSPLIM_NS_EN    1
 #define TC_COREFUNC_MSPLIM_EN       1
+#define TC_COREFUNC_MSPLIM_NS_EN    1
 #define TC_COREFUNC_PRIMASK_EN      1
 #define TC_COREFUNC_FAULTMASK_EN    1
 #define TC_COREFUNC_BASEPRI_EN      1

CMSIS/CoreValidation/Tests/Cortex-M23NS/IAR/CV_Config.h

@@ -46,14 +46,16 @@
 // <q13> TC_CoreFunc_PSP
 // <q14> TC_CoreFunc_MSP
 // <q13> TC_CoreFunc_PSPLIM
-// <q14> TC_CoreFunc_MSPLIM
-// <q15> TC_CoreFunc_PRIMASK
-// <q16> TC_CoreFunc_FAULTMASK
-// <q17> TC_CoreFunc_BASEPRI
-// <q18> TC_CoreFunc_FPSCR
+// <q14> TC_CoreFunc_PSPLIM_NS
+// <q15> TC_CoreFunc_MSPLIM
+// <q16> TC_CoreFunc_MSPLIM_NS
+// <q17> TC_CoreFunc_PRIMASK
+// <q18> TC_CoreFunc_FAULTMASK
+// <q19> TC_CoreFunc_BASEPRI
+// <q20> TC_CoreFunc_FPSCR
 //
-// <q19> TC_MPU_SetClear
-// <q20> TC_MPU_Load
+// <q21> TC_MPU_SetClear
+// <q22> TC_MPU_Load
 #define TC_COREINSTR_NOP_EN         1
 #define TC_COREINSTR_REV_EN         1
 #define TC_COREINSTR_REV16_EN       1
@@ -70,8 +72,11 @@
 #define TC_COREFUNC_APSR_EN         1
 #define TC_COREFUNC_PSP_EN          1
 #define TC_COREFUNC_MSP_EN          1
+
 #define TC_COREFUNC_PSPLIM_EN       1
+#define TC_COREFUNC_PSPLIM_NS_EN    1
 #define TC_COREFUNC_MSPLIM_EN       1
+#define TC_COREFUNC_MSPLIM_NS_EN    1
 #define TC_COREFUNC_PRIMASK_EN      1
 #define TC_COREFUNC_FAULTMASK_EN    1
 #define TC_COREFUNC_BASEPRI_EN      1

CMSIS/CoreValidation/Tests/Cortex-M23S/AC6/CV_Config.h

@@ -46,14 +46,16 @@
 // <q13> TC_CoreFunc_PSP
 // <q14> TC_CoreFunc_MSP
 // <q13> TC_CoreFunc_PSPLIM
-// <q14> TC_CoreFunc_MSPLIM
-// <q15> TC_CoreFunc_PRIMASK
-// <q16> TC_CoreFunc_FAULTMASK
-// <q17> TC_CoreFunc_BASEPRI
-// <q18> TC_CoreFunc_FPSCR
+// <q14> TC_CoreFunc_PSPLIM_NS
+// <q15> TC_CoreFunc_MSPLIM
+// <q16> TC_CoreFunc_MSPLIM_NS
+// <q17> TC_CoreFunc_PRIMASK
+// <q18> TC_CoreFunc_FAULTMASK
+// <q19> TC_CoreFunc_BASEPRI
+// <q20> TC_CoreFunc_FPSCR
 //
-// <q19> TC_MPU_SetClear
-// <q20> TC_MPU_Load
+// <q21> TC_MPU_SetClear
+// <q22> TC_MPU_Load
 #define TC_COREINSTR_NOP_EN         1
 #define TC_COREINSTR_REV_EN         1
 #define TC_COREINSTR_REV16_EN       1
@@ -70,8 +72,11 @@
 #define TC_COREFUNC_APSR_EN         1
 #define TC_COREFUNC_PSP_EN          1
 #define TC_COREFUNC_MSP_EN          1
+
 #define TC_COREFUNC_PSPLIM_EN       1
+#define TC_COREFUNC_PSPLIM_NS_EN    1
 #define TC_COREFUNC_MSPLIM_EN       1
+#define TC_COREFUNC_MSPLIM_NS_EN    1
 #define TC_COREFUNC_PRIMASK_EN      1
 #define TC_COREFUNC_FAULTMASK_EN    1
 #define TC_COREFUNC_BASEPRI_EN      1

CMSIS/CoreValidation/Tests/Cortex-M23S/GCC/CV_Config.h

@@ -46,14 +46,16 @@
 // <q13> TC_CoreFunc_PSP
 // <q14> TC_CoreFunc_MSP
 // <q13> TC_CoreFunc_PSPLIM
-// <q14> TC_CoreFunc_MSPLIM
-// <q15> TC_CoreFunc_PRIMASK
-// <q16> TC_CoreFunc_FAULTMASK
-// <q17> TC_CoreFunc_BASEPRI
-// <q18> TC_CoreFunc_FPSCR
+// <q14> TC_CoreFunc_PSPLIM_NS
+// <q15> TC_CoreFunc_MSPLIM
+// <q16> TC_CoreFunc_MSPLIM_NS
+// <q17> TC_CoreFunc_PRIMASK
+// <q18> TC_CoreFunc_FAULTMASK
+// <q19> TC_CoreFunc_BASEPRI
+// <q20> TC_CoreFunc_FPSCR
 //
-// <q19> TC_MPU_SetClear
-// <q20> TC_MPU_Load
+// <q21> TC_MPU_SetClear
+// <q22> TC_MPU_Load
 #define TC_COREINSTR_NOP_EN         1
 #define TC_COREINSTR_REV_EN         1
 #define TC_COREINSTR_REV16_EN       1
@@ -70,8 +72,11 @@
 #define TC_COREFUNC_APSR_EN         1
 #define TC_COREFUNC_PSP_EN          1
 #define TC_COREFUNC_MSP_EN          1
+
 #define TC_COREFUNC_PSPLIM_EN       1
+#define TC_COREFUNC_PSPLIM_NS_EN    1
 #define TC_COREFUNC_MSPLIM_EN       1
+#define TC_COREFUNC_MSPLIM_NS_EN    1
 #define TC_COREFUNC_PRIMASK_EN      1
 #define TC_COREFUNC_FAULTMASK_EN    1
 #define TC_COREFUNC_BASEPRI_EN      1

CMSIS/CoreValidation/Tests/Cortex-M23S/IAR/CV_Config.h

@@ -46,14 +46,16 @@
 // <q13> TC_CoreFunc_PSP
 // <q14> TC_CoreFunc_MSP
 // <q13> TC_CoreFunc_PSPLIM
-// <q14> TC_CoreFunc_MSPLIM
-// <q15> TC_CoreFunc_PRIMASK
-// <q16> TC_CoreFunc_FAULTMASK
-// <q17> TC_CoreFunc_BASEPRI
-// <q18> TC_CoreFunc_FPSCR
+// <q14> TC_CoreFunc_PSPLIM_NS
+// <q15> TC_CoreFunc_MSPLIM
+// <q16> TC_CoreFunc_MSPLIM_NS
+// <q17> TC_CoreFunc_PRIMASK
+// <q18> TC_CoreFunc_FAULTMASK
+// <q19> TC_CoreFunc_BASEPRI
+// <q20> TC_CoreFunc_FPSCR
 //
-// <q19> TC_MPU_SetClear
-// <q20> TC_MPU_Load
+// <q21> TC_MPU_SetClear
+// <q22> TC_MPU_Load
 #define TC_COREINSTR_NOP_EN         1
 #define TC_COREINSTR_REV_EN         1
 #define TC_COREINSTR_REV16_EN       1
@@ -70,8 +72,11 @@
 #define TC_COREFUNC_APSR_EN         1
 #define TC_COREFUNC_PSP_EN          1
 #define TC_COREFUNC_MSP_EN          1
+
 #define TC_COREFUNC_PSPLIM_EN       1
+#define TC_COREFUNC_PSPLIM_NS_EN    1
 #define TC_COREFUNC_MSPLIM_EN       1
+#define TC_COREFUNC_MSPLIM_NS_EN    1
 #define TC_COREFUNC_PRIMASK_EN      1
 #define TC_COREFUNC_FAULTMASK_EN    1
 #define TC_COREFUNC_BASEPRI_EN      1

CMSIS/CoreValidation/Tests/Cortex-M33/AC6/CV_Config.h

@@ -46,14 +46,16 @@
 // <q13> TC_CoreFunc_PSP
 // <q14> TC_CoreFunc_MSP
 // <q13> TC_CoreFunc_PSPLIM
-// <q14> TC_CoreFunc_MSPLIM
-// <q15> TC_CoreFunc_PRIMASK
-// <q16> TC_CoreFunc_FAULTMASK
-// <q17> TC_CoreFunc_BASEPRI
-// <q18> TC_CoreFunc_FPSCR
+// <q14> TC_CoreFunc_PSPLIM_NS
+// <q15> TC_CoreFunc_MSPLIM
+// <q16> TC_CoreFunc_MSPLIM_NS
+// <q17> TC_CoreFunc_PRIMASK
+// <q18> TC_CoreFunc_FAULTMASK
+// <q19> TC_CoreFunc_BASEPRI
+// <q20> TC_CoreFunc_FPSCR
 //
-// <q19> TC_MPU_SetClear
-// <q20> TC_MPU_Load
+// <q21> TC_MPU_SetClear
+// <q22> TC_MPU_Load
 #define TC_COREINSTR_NOP_EN         1
 #define TC_COREINSTR_REV_EN         1
 #define TC_COREINSTR_REV16_EN       1
@@ -70,8 +72,11 @@
 #define TC_COREFUNC_APSR_EN         1
 #define TC_COREFUNC_PSP_EN          1
 #define TC_COREFUNC_MSP_EN          1
+
 #define TC_COREFUNC_PSPLIM_EN       1
+#define TC_COREFUNC_PSPLIM_NS_EN    1
 #define TC_COREFUNC_MSPLIM_EN       1
+#define TC_COREFUNC_MSPLIM_NS_EN    1
 #define TC_COREFUNC_PRIMASK_EN      1
 #define TC_COREFUNC_FAULTMASK_EN    1
 #define TC_COREFUNC_BASEPRI_EN      1

CMSIS/CoreValidation/Tests/Cortex-M33/GCC/CV_Config.h

@@ -46,14 +46,16 @@
 // <q13> TC_CoreFunc_PSP
 // <q14> TC_CoreFunc_MSP
 // <q13> TC_CoreFunc_PSPLIM
-// <q14> TC_CoreFunc_MSPLIM
-// <q15> TC_CoreFunc_PRIMASK
-// <q16> TC_CoreFunc_FAULTMASK
-// <q17> TC_CoreFunc_BASEPRI
-// <q18> TC_CoreFunc_FPSCR
+// <q14> TC_CoreFunc_PSPLIM_NS
+// <q15> TC_CoreFunc_MSPLIM
+// <q16> TC_CoreFunc_MSPLIM_NS
+// <q17> TC_CoreFunc_PRIMASK
+// <q18> TC_CoreFunc_FAULTMASK
+// <q19> TC_CoreFunc_BASEPRI
+// <q20> TC_CoreFunc_FPSCR
 //
-// <q19> TC_MPU_SetClear
-// <q20> TC_MPU_Load
+// <q21> TC_MPU_SetClear
+// <q22> TC_MPU_Load
 #define TC_COREINSTR_NOP_EN         1
 #define TC_COREINSTR_REV_EN         1
 #define TC_COREINSTR_REV16_EN       1
@@ -70,8 +72,11 @@
 #define TC_COREFUNC_APSR_EN         1
 #define TC_COREFUNC_PSP_EN          1
 #define TC_COREFUNC_MSP_EN          1
+
 #define TC_COREFUNC_PSPLIM_EN       1
+#define TC_COREFUNC_PSPLIM_NS_EN    1
 #define TC_COREFUNC_MSPLIM_EN       1
+#define TC_COREFUNC_MSPLIM_NS_EN    1
 #define TC_COREFUNC_PRIMASK_EN      1
 #define TC_COREFUNC_FAULTMASK_EN    1
 #define TC_COREFUNC_BASEPRI_EN      1

CMSIS/CoreValidation/Tests/Cortex-M33/IAR/CV_Config.h

@@ -46,14 +46,16 @@
 // <q13> TC_CoreFunc_PSP
 // <q14> TC_CoreFunc_MSP
 // <q13> TC_CoreFunc_PSPLIM
-// <q14> TC_CoreFunc_MSPLIM
-// <q15> TC_CoreFunc_PRIMASK
-// <q16> TC_CoreFunc_FAULTMASK
-// <q17> TC_CoreFunc_BASEPRI
-// <q18> TC_CoreFunc_FPSCR
+// <q14> TC_CoreFunc_PSPLIM_NS
+// <q15> TC_CoreFunc_MSPLIM
+// <q16> TC_CoreFunc_MSPLIM_NS
+// <q17> TC_CoreFunc_PRIMASK
+// <q18> TC_CoreFunc_FAULTMASK
+// <q19> TC_CoreFunc_BASEPRI
+// <q20> TC_CoreFunc_FPSCR
 //
-// <q19> TC_MPU_SetClear
-// <q20> TC_MPU_Load
+// <q21> TC_MPU_SetClear
+// <q22> TC_MPU_Load
 #define TC_COREINSTR_NOP_EN         1
 #define TC_COREINSTR_REV_EN         1
 #define TC_COREINSTR_REV16_EN       1
@@ -70,8 +72,11 @@
 #define TC_COREFUNC_APSR_EN         1
 #define TC_COREFUNC_PSP_EN          1
 #define TC_COREFUNC_MSP_EN          1
+
 #define TC_COREFUNC_PSPLIM_EN       1
+#define TC_COREFUNC_PSPLIM_NS_EN    1
 #define TC_COREFUNC_MSPLIM_EN       1
+#define TC_COREFUNC_MSPLIM_NS_EN    1
 #define TC_COREFUNC_PRIMASK_EN      1
 #define TC_COREFUNC_FAULTMASK_EN    1
 #define TC_COREFUNC_BASEPRI_EN      1

CMSIS/CoreValidation/Tests/Cortex-M33NS/AC6/CV_Config.h

@@ -46,14 +46,16 @@
 // <q13> TC_CoreFunc_PSP
 // <q14> TC_CoreFunc_MSP
 // <q13> TC_CoreFunc_PSPLIM
-// <q14> TC_CoreFunc_MSPLIM
-// <q15> TC_CoreFunc_PRIMASK
-// <q16> TC_CoreFunc_FAULTMASK
-// <q17> TC_CoreFunc_BASEPRI
-// <q18> TC_CoreFunc_FPSCR
+// <q14> TC_CoreFunc_PSPLIM_NS
+// <q15> TC_CoreFunc_MSPLIM
+// <q16> TC_CoreFunc_MSPLIM_NS
+// <q17> TC_CoreFunc_PRIMASK
+// <q18> TC_CoreFunc_FAULTMASK
+// <q19> TC_CoreFunc_BASEPRI
+// <q20> TC_CoreFunc_FPSCR
 //
-// <q19> TC_MPU_SetClear
-// <q20> TC_MPU_Load
+// <q21> TC_MPU_SetClear
+// <q22> TC_MPU_Load
 #define TC_COREINSTR_NOP_EN         1
 #define TC_COREINSTR_REV_EN         1
 #define TC_COREINSTR_REV16_EN       1
@@ -70,8 +72,11 @@
 #define TC_COREFUNC_APSR_EN         1
 #define TC_COREFUNC_PSP_EN          1
 #define TC_COREFUNC_MSP_EN          1
+
 #define TC_COREFUNC_PSPLIM_EN       1
+#define TC_COREFUNC_PSPLIM_NS_EN    1
 #define TC_COREFUNC_MSPLIM_EN       1
+#define TC_COREFUNC_MSPLIM_NS_EN    1
 #define TC_COREFUNC_PRIMASK_EN      1
 #define TC_COREFUNC_FAULTMASK_EN    1
 #define TC_COREFUNC_BASEPRI_EN      1

CMSIS/CoreValidation/Tests/Cortex-M33NS/GCC/CV_Config.h

@@ -46,14 +46,16 @@
 // <q13> TC_CoreFunc_PSP
 // <q14> TC_CoreFunc_MSP
 // <q13> TC_CoreFunc_PSPLIM
-// <q14> TC_CoreFunc_MSPLIM
-// <q15> TC_CoreFunc_PRIMASK
-// <q16> TC_CoreFunc_FAULTMASK
-// <q17> TC_CoreFunc_BASEPRI
-// <q18> TC_CoreFunc_FPSCR
+// <q14> TC_CoreFunc_PSPLIM_NS
+// <q15> TC_CoreFunc_MSPLIM
+// <q16> TC_CoreFunc_MSPLIM_NS
+// <q17> TC_CoreFunc_PRIMASK
+// <q18> TC_CoreFunc_FAULTMASK
+// <q19> TC_CoreFunc_BASEPRI
+// <q20> TC_CoreFunc_FPSCR
 //
-// <q19> TC_MPU_SetClear
-// <q20> TC_MPU_Load
+// <q21> TC_MPU_SetClear
+// <q22> TC_MPU_Load
 #define TC_COREINSTR_NOP_EN         1
 #define TC_COREINSTR_REV_EN         1
 #define TC_COREINSTR_REV16_EN       1
@@ -70,8 +72,11 @@
 #define TC_COREFUNC_APSR_EN         1
 #define TC_COREFUNC_PSP_EN          1
 #define TC_COREFUNC_MSP_EN          1
+
 #define TC_COREFUNC_PSPLIM_EN       1
+#define TC_COREFUNC_PSPLIM_NS_EN    1
 #define TC_COREFUNC_MSPLIM_EN       1
+#define TC_COREFUNC_MSPLIM_NS_EN    1
 #define TC_COREFUNC_PRIMASK_EN      1
 #define TC_COREFUNC_FAULTMASK_EN    1
 #define TC_COREFUNC_BASEPRI_EN      1

CMSIS/CoreValidation/Tests/Cortex-M33NS/IAR/CV_Config.h

@@ -46,14 +46,16 @@
 // <q13> TC_CoreFunc_PSP
 // <q14> TC_CoreFunc_MSP
 // <q13> TC_CoreFunc_PSPLIM
-// <q14> TC_CoreFunc_MSPLIM
-// <q15> TC_CoreFunc_PRIMASK
-// <q16> TC_CoreFunc_FAULTMASK
-// <q17> TC_CoreFunc_BASEPRI
-// <q18> TC_CoreFunc_FPSCR
+// <q14> TC_CoreFunc_PSPLIM_NS
+// <q15> TC_CoreFunc_MSPLIM
+// <q16> TC_CoreFunc_MSPLIM_NS
+// <q17> TC_CoreFunc_PRIMASK
+// <q18> TC_CoreFunc_FAULTMASK
+// <q19> TC_CoreFunc_BASEPRI
+// <q20> TC_CoreFunc_FPSCR
 //
-// <q19> TC_MPU_SetClear
-// <q20> TC_MPU_Load
+// <q21> TC_MPU_SetClear
+// <q22> TC_MPU_Load
 #define TC_COREINSTR_NOP_EN         1
 #define TC_COREINSTR_REV_EN         1
 #define TC_COREINSTR_REV16_EN       1
@@ -70,8 +72,11 @@
 #define TC_COREFUNC_APSR_EN         1
 #define TC_COREFUNC_PSP_EN          1
 #define TC_COREFUNC_MSP_EN          1
+
 #define TC_COREFUNC_PSPLIM_EN       1
+#define TC_COREFUNC_PSPLIM_NS_EN    1
 #define TC_COREFUNC_MSPLIM_EN       1
+#define TC_COREFUNC_MSPLIM_NS_EN    1
 #define TC_COREFUNC_PRIMASK_EN      1
 #define TC_COREFUNC_FAULTMASK_EN    1
 #define TC_COREFUNC_BASEPRI_EN      1

CMSIS/CoreValidation/Tests/Cortex-M33S/AC6/CV_Config.h

@@ -46,14 +46,16 @@
 // <q13> TC_CoreFunc_PSP
 // <q14> TC_CoreFunc_MSP
 // <q13> TC_CoreFunc_PSPLIM
-// <q14> TC_CoreFunc_MSPLIM
-// <q15> TC_CoreFunc_PRIMASK
-// <q16> TC_CoreFunc_FAULTMASK
-// <q17> TC_CoreFunc_BASEPRI
-// <q18> TC_CoreFunc_FPSCR
+// <q14> TC_CoreFunc_PSPLIM_NS
+// <q15> TC_CoreFunc_MSPLIM
+// <q16> TC_CoreFunc_MSPLIM_NS
+// <q17> TC_CoreFunc_PRIMASK
+// <q18> TC_CoreFunc_FAULTMASK
+// <q19> TC_CoreFunc_BASEPRI
+// <q20> TC_CoreFunc_FPSCR
 //
-// <q19> TC_MPU_SetClear
-// <q20> TC_MPU_Load
+// <q21> TC_MPU_SetClear
+// <q22> TC_MPU_Load
 #define TC_COREINSTR_NOP_EN         1
 #define TC_COREINSTR_REV_EN         1
 #define TC_COREINSTR_REV16_EN       1
@@ -70,8 +72,11 @@
 #define TC_COREFUNC_APSR_EN         1
 #define TC_COREFUNC_PSP_EN          1
 #define TC_COREFUNC_MSP_EN          1
+
 #define TC_COREFUNC_PSPLIM_EN       1
+#define TC_COREFUNC_PSPLIM_NS_EN    1
 #define TC_COREFUNC_MSPLIM_EN       1
+#define TC_COREFUNC_MSPLIM_NS_EN    1
 #define TC_COREFUNC_PRIMASK_EN      1
 #define TC_COREFUNC_FAULTMASK_EN    1
 #define TC_COREFUNC_BASEPRI_EN      1

CMSIS/CoreValidation/Tests/Cortex-M33S/GCC/CV_Config.h

@@ -46,14 +46,16 @@
 // <q13> TC_CoreFunc_PSP
 // <q14> TC_CoreFunc_MSP
 // <q13> TC_CoreFunc_PSPLIM
-// <q14> TC_CoreFunc_MSPLIM
-// <q15> TC_CoreFunc_PRIMASK
-// <q16> TC_CoreFunc_FAULTMASK
-// <q17> TC_CoreFunc_BASEPRI
-// <q18> TC_CoreFunc_FPSCR
+// <q14> TC_CoreFunc_PSPLIM_NS
+// <q15> TC_CoreFunc_MSPLIM
+// <q16> TC_CoreFunc_MSPLIM_NS
+// <q17> TC_CoreFunc_PRIMASK
+// <q18> TC_CoreFunc_FAULTMASK
+// <q19> TC_CoreFunc_BASEPRI
+// <q20> TC_CoreFunc_FPSCR
 //
-// <q19> TC_MPU_SetClear
-// <q20> TC_MPU_Load
+// <q21> TC_MPU_SetClear
+// <q22> TC_MPU_Load
 #define TC_COREINSTR_NOP_EN         1
 #define TC_COREINSTR_REV_EN         1
 #define TC_COREINSTR_REV16_EN       1
@@ -70,8 +72,11 @@
 #define TC_COREFUNC_APSR_EN         1
 #define TC_COREFUNC_PSP_EN          1
 #define TC_COREFUNC_MSP_EN          1
+
 #define TC_COREFUNC_PSPLIM_EN       1
+#define TC_COREFUNC_PSPLIM_NS_EN    1
 #define TC_COREFUNC_MSPLIM_EN       1
+#define TC_COREFUNC_MSPLIM_NS_EN    1
 #define TC_COREFUNC_PRIMASK_EN      1
 #define TC_COREFUNC_FAULTMASK_EN    1
 #define TC_COREFUNC_BASEPRI_EN      1

CMSIS/CoreValidation/Tests/Cortex-M33S/IAR/CV_Config.h

@@ -46,14 +46,16 @@
 // <q13> TC_CoreFunc_PSP
 // <q14> TC_CoreFunc_MSP
 // <q13> TC_CoreFunc_PSPLIM
-// <q14> TC_CoreFunc_MSPLIM
-// <q15> TC_CoreFunc_PRIMASK
-// <q16> TC_CoreFunc_FAULTMASK
-// <q17> TC_CoreFunc_BASEPRI
-// <q18> TC_CoreFunc_FPSCR
+// <q14> TC_CoreFunc_PSPLIM_NS
+// <q15> TC_CoreFunc_MSPLIM
+// <q16> TC_CoreFunc_MSPLIM_NS
+// <q17> TC_CoreFunc_PRIMASK
+// <q18> TC_CoreFunc_FAULTMASK
+// <q19> TC_CoreFunc_BASEPRI
+// <q20> TC_CoreFunc_FPSCR
 //
-// <q19> TC_MPU_SetClear
-// <q20> TC_MPU_Load
+// <q21> TC_MPU_SetClear
+// <q22> TC_MPU_Load
 #define TC_COREINSTR_NOP_EN         1
 #define TC_COREINSTR_REV_EN         1
 #define TC_COREINSTR_REV16_EN       1
@@ -70,8 +72,11 @@
 #define TC_COREFUNC_APSR_EN         1
 #define TC_COREFUNC_PSP_EN          1
 #define TC_COREFUNC_MSP_EN          1
+
 #define TC_COREFUNC_PSPLIM_EN       1
+#define TC_COREFUNC_PSPLIM_NS_EN    1
 #define TC_COREFUNC_MSPLIM_EN       1
+#define TC_COREFUNC_MSPLIM_NS_EN    1
 #define TC_COREFUNC_PRIMASK_EN      1
 #define TC_COREFUNC_FAULTMASK_EN    1
 #define TC_COREFUNC_BASEPRI_EN      1

CMSIS/DoxyGen/Core/src/Ref_CoreReg.txt

@@ -684,6 +684,10 @@ void __disable_fault_irq(void);
 
 /**
   \brief   Get Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
   \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
   \return               PSPLIM Register value
   \note    Only availabe for ARMv8-M Architecture. 
@@ -692,6 +696,10 @@ uint32_t __get_PSPLIM(void);
 
 /**
   \brief   Set Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
   \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
   \note    Only availabe for ARMv8-M Architecture. 
@@ -700,6 +708,10 @@ void __set_PSPLIM(uint32_t ProcStackPtrLimit);
 
 /**
   \brief   Get Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
   \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
   \return               MSPLIM Register value
   \note    Only availabe for ARMv8-M Architecture. 
@@ -708,6 +720,10 @@ uint32_t __get_MSPLIM(void);
 
 /**
   \brief   Set Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
   \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
   \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
   \note    Only availabe for ARMv8-M Architecture. 

CMSIS/DoxyGen/Core/src/Ref_Trustzone.txt

@@ -142,33 +142,41 @@ void __TZ_set_FAULTMASK_NS(uint32_t faultMask);
 
 /**
   \brief   Get Process Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
   \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
-  \return               PSPLIM register value
-  \note    Only available for ARMv8-M Mainline. 
+  \return               PSPLIM register value 
  */
 uint32_t __TZ_get_PSPLIM_NS(void);
 
 /**
   \brief   Set Process Stack Pointer (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
   \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
-  \note    Only available for ARMv8-M Mainline. 
  */
 void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit);
 
 /**
   \brief   Get Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+  
   \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
   \return               MSPLIM register value
-  \note    Only available for ARMv8-M Mainline. 
  */
 uint32_t __TZ_get_MSPLIM_NS(void);
 
 /**
   \brief   Set Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
   \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
   \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
-  \note    Only available for ARMv8-M Mainline. 
  */
 void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit);