Merge branch 'develop'

.gitattributes

@@ -15,3 +15,6 @@
 # Denote all files that are truly binary and should not be modified.
 *.png binary
 *.jpg binary
+# Script files
+*.py text eol=lf
+*.sh text eol=lf

.github/fileheader.json

@@ -0,0 +1,16 @@
+{
+	"problemMatcher": [
+		{
+			"owner": "fileheader",
+			"severity": "error",
+			"pattern": [
+				{
+					"regexp": "^(.*):(\\d+):(.*)$",
+					"file": 1,
+					"line": 2,
+					"message": 3
+				}
+			]
+		}
+	]
+}

.github/linkchecker.json

@@ -0,0 +1,16 @@
+{
+	"problemMatcher": [
+		{
+			"owner": "fileheader",
+			"severity": "error",
+			"pattern": [
+				{
+					"regexp": "^(.*):(\\d+);(.*);(.*)$",
+					"file": 1,
+					"line": 2,
+					"message": 4
+				}
+			]
+		}
+	]
+}

.github/workflows/codeql-analysis.yml

@@ -4,10 +4,19 @@ on:
   workflow_dispatch:
   push:
     branches: [ develop ]
+    paths:
+      - 'CMSIS/Core/**'
+      - 'CMSIS/Core_A/**'
+      - 'CMSIS/CoreValidation/**'
+      - 'Device/ARM/**'
   pull_request:
-    # The branches below must be a subset of the branches above
     branches: [ develop ]
-
+    paths:
+      - '.github/workflows/codeql-analysis.yml'
+      - 'CMSIS/Core/**'
+      - 'CMSIS/Core_A/**'
+      - 'CMSIS/CoreValidation/**'
+      - 'Device/ARM/**'
 jobs:
   analyze:
     name: Analyze

.github/workflows/fileheader.yml

@@ -0,0 +1,37 @@
+name: File header
+
+on:
+  pull_request:
+    branches: [ develop ]
+    paths:
+      - 'CMSIS/Core/**'
+      - 'CMSIS/Core_A/**'
+      - 'CMSIS/RTOS2/Include/**'
+      - 'CMSIS/RTOS2/Source/**'
+      - 'Device/**'
+
+permissions:
+  contents: read
+  pull-requests: write
+
+jobs:
+  check:
+    name: Check file header
+    runs-on: ubuntu-latest
+    steps:
+    - name: Checkout repository
+      uses: actions/checkout@v2
+      with:
+        ref: ${{ github.event.pull_request.head.sha }}
+        fetch-depth: ${{ github.event.pull_request.commits }}
+    - id: files
+      uses: jitterbit/get-changed-files@v1
+    - name: Check changed files
+      run: |
+        echo "::add-matcher::.github/fileheader.json"
+        RC=0
+        for changed_file in ${{ steps.files.outputs.added_modified }}; do
+          ./CMSIS/Utilities/check_header.sh ${changed_file} || RC=1
+        done
+        echo "::remove-matcher owner=fileheader::"
+        exit $RC

.github/workflows/gh-pages.yaml

@@ -1,10 +1,17 @@
 name: Publish Documentation
 on:
   workflow_dispatch:
+  pull_request:
+    branches: [ develop ]
+    paths:
+      - '.github/workflows/gh-pages.yaml'
+      - 'CMSIS/Utilities/check_links.sh'
+      - 'CMSIS/DoxyGen/**'
   push:
-    branches:
-      - develop
+    branches: [ develop ]
     paths:
+      - '.github/workflows/gh-pages.yaml'
+      - 'CMSIS/Utilities/check_links.sh'
       - 'CMSIS/DoxyGen/**'
 jobs:
   docs:
@@ -21,16 +28,31 @@ jobs:
         run: |
           sudo apt-get update
           sudo apt-get install --no-install-recommends -y mscgen=0.20-12
+      - name: Install linkchecker
+        run: |
+          sudo pip install LinkChecker
       - name: Generate doxygen
         run: CMSIS/DoxyGen/gen_doc.sh
+      - name: Run linkchecker
+        run: |
+          echo "::add-matcher::.github/linkchecker.json"
+          CMSIS/Utilities/check_links.sh CMSIS/Documentation/index.html
+      - name: Upload documentation
+        if: ${{ github.event_name == 'pull_request' }}
+        uses: actions/upload-artifact@v2
+        with:
+          path: CMSIS/Documentation/**
       - name: Archive documentation
+        if: ${{ github.event_name == 'push' || github.event_name == 'workflow_dispatch' }}
         run: |
           cd CMSIS/Documentation
           tar -cvjf /tmp/doc.tbz2 .
       - uses: actions/checkout@v2
+        if: ${{ github.event_name == 'push' || github.event_name == 'workflow_dispatch' }}
         with:
           ref: gh-pages
       - name: Publish documentation
+        if: ${{ github.event_name == 'push' || github.event_name == 'workflow_dispatch' }}
         run: |
           rm -r develop
           mkdir develop

.github/workflows/packdesc.yml

@@ -0,0 +1,30 @@
+name: Pack Description
+
+on:
+  pull_request:
+    branches: [ develop ]
+    paths:
+      - 'ARM.CMSIS.pdsc'
+
+permissions:
+  contents: read
+  pull-requests: write
+
+jobs:
+  check:
+    name: Check pack description schema
+    runs-on: ubuntu-latest
+    steps:
+    - name: Install xmllint
+      run: |
+        sudo apt-get install libxml2-utils
+    - name: Checkout repository
+      uses: actions/checkout@v2
+      with:
+        ref: ${{ github.event.pull_request.head.sha }}
+    - name: Run xmllint
+      run: |
+        curl https://raw.githubusercontent.com/Open-CMSIS-Pack/Open-CMSIS-Pack-Spec/main/schema/PACK.xsd -o CMSIS/Utilities/PACK.xsd
+        echo "::add-matcher::.github/xmllint.json"
+        xmllint --noout --schema "$(realpath -m ./CMSIS/Utilities/PACK.xsd)" "ARM.CMSIS.pdsc"
+        echo "::remove-matcher owner=xmllint::"

.github/workflows/release.yaml

@@ -32,7 +32,7 @@ jobs:
           mkdir ${RELEASE}
           rm latest
           ln -s ${RELEASE} latest
-          cd RELEASE
+          cd ${RELEASE}
           tar -xvjf /tmp/doc.tbz2
           git config user.name github-actions
           git config user.email github-actions@github.com

.github/xmllint.json

@@ -0,0 +1,16 @@
+{
+  "problemMatcher": [
+    {
+      "owner": "xmllint",
+      "severity": "error",
+      "pattern": [
+        {
+          "regexp": "^(.*):(\\d+):(.*)$",
+          "file": 1,
+          "line": 2,
+          "message": 3
+        }
+      ]
+    }
+  ]
+}

.gitignore

@@ -15,3 +15,8 @@ CMSIS/RTOS/RTX/LIB/**/*.lib
 CMSIS/RTOS2/RTX/Library/**/*.a
 CMSIS/RTOS2/RTX/Library/**/*.lib
 output
+.DS_Store
+internal.cp310-win_amd64.pyd
+CMSIS/Utilities/Darwin64
+CMSIS/Utilities/Linux64
+CMSIS/Utilities/Win32

CMSIS/Core/Include/cmsis_version.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     cmsis_version.h
  * @brief    CMSIS Core(M) Version definitions
- * @version  V5.0.4
- * @date     23. July 2019
+ * @version  V5.0.5
+ * @date     02. February 2022
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2022 ARM Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -33,7 +33,7 @@
 
 /*  CMSIS Version definitions */
 #define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
-#define __CM_CMSIS_VERSION_SUB   ( 4U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION_SUB   ( 6U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
 #define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
                                    __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
 #endif

CMSIS/Core/Include/core_armv81mml.h

@@ -1,8 +1,8 @@
 /**************************************************************************//**
  * @file     core_armv81mml.h
  * @brief    CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File
- * @version  V1.4.1
- * @date     04. June 2021
+ * @version  V1.4.2
+ * @date     13. October 2021
  ******************************************************************************/
 /*
  * Copyright (c) 2018-2021 Arm Limited. All rights reserved.
@@ -526,7 +526,7 @@ typedef struct
   __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
   __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
   __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
-  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
   __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
   __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
   __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
@@ -535,7 +535,10 @@ typedef struct
   __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
   __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
   __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
-        uint32_t RESERVED3[92U];
+        uint32_t RESERVED7[21U];
+  __IOM uint32_t SFSR;                   /*!< Offset: 0x0E4 (R/W)  Secure Fault Status Register */
+  __IOM uint32_t SFAR;                   /*!< Offset: 0x0E8 (R/W)  Secure Fault Address Register */
+        uint32_t RESERVED3[69U];
   __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
   __IOM uint32_t RFSR;                   /*!< Offset: 0x204 (R/W)  RAS Fault Status Register */
         uint32_t RESERVED4[14U];
@@ -1490,15 +1493,14 @@ typedef struct
         uint32_t RESERVED11[108];
   __IOM uint32_t AUTHSTATUS;                        /*!< Offset: 0xFB8 (R/W)  PMU Authentication Status Register */
   __IOM uint32_t DEVARCH;                           /*!< Offset: 0xFBC (R/W)  PMU Device Architecture Register */
-        uint32_t RESERVED12[4];
+        uint32_t RESERVED12[3];
   __IOM uint32_t DEVTYPE;                           /*!< Offset: 0xFCC (R/W)  PMU Device Type Register */
   __IOM uint32_t PIDR4;                             /*!< Offset: 0xFD0 (R/W)  PMU Peripheral Identification Register 4 */
         uint32_t RESERVED13[3];
   __IOM uint32_t PIDR0;                             /*!< Offset: 0xFE0 (R/W)  PMU Peripheral Identification Register 0 */
-  __IOM uint32_t PIDR1;                             /*!< Offset: 0xFE0 (R/W)  PMU Peripheral Identification Register 1 */
-  __IOM uint32_t PIDR2;                             /*!< Offset: 0xFE0 (R/W)  PMU Peripheral Identification Register 2 */
-  __IOM uint32_t PIDR3;                             /*!< Offset: 0xFE0 (R/W)  PMU Peripheral Identification Register 3 */
-        uint32_t RESERVED14[3];
+  __IOM uint32_t PIDR1;                             /*!< Offset: 0xFE4 (R/W)  PMU Peripheral Identification Register 1 */
+  __IOM uint32_t PIDR2;                             /*!< Offset: 0xFE8 (R/W)  PMU Peripheral Identification Register 2 */
+  __IOM uint32_t PIDR3;                             /*!< Offset: 0xFEC (R/W)  PMU Peripheral Identification Register 3 */
   __IOM uint32_t CIDR0;                             /*!< Offset: 0xFF0 (R/W)  PMU Component Identification Register 0 */
   __IOM uint32_t CIDR1;                             /*!< Offset: 0xFF4 (R/W)  PMU Component Identification Register 1 */
   __IOM uint32_t CIDR2;                             /*!< Offset: 0xFF8 (R/W)  PMU Component Identification Register 2 */
@@ -3158,6 +3160,15 @@ typedef struct
 /*@} */
 
 
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_register_aliases     Backwards Compatibility Aliases
+  \brief      Register alias definitions for backwards compatibility.
+  @{
+ */
+#define ID_ADR  (ID_AFR)    /*!< SCB Auxiliary Feature Register */
+/*@} */
+
 
 /*******************************************************************************
  *                Hardware Abstraction Layer

CMSIS/Core/Include/core_armv8mml.h

@@ -1,8 +1,8 @@
 /**************************************************************************//**
  * @file     core_armv8mml.h
  * @brief    CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File
- * @version  V5.2.2
- * @date     04. June 2021
+ * @version  V5.2.3
+ * @date     13. October 2021
  ******************************************************************************/
 /*
  * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
@@ -519,7 +519,7 @@ typedef struct
   __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
   __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
   __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
-  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
   __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
   __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
   __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
@@ -528,7 +528,10 @@ typedef struct
   __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
   __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
   __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
-        uint32_t RESERVED3[92U];
+        uint32_t RESERVED7[21U];
+  __IOM uint32_t SFSR;                   /*!< Offset: 0x0E4 (R/W)  Secure Fault Status Register */
+  __IOM uint32_t SFAR;                   /*!< Offset: 0x0E8 (R/W)  Secure Fault Address Register */
+        uint32_t RESERVED3[69U];
   __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
         uint32_t RESERVED4[15U];
   __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
@@ -2182,6 +2185,15 @@ typedef struct
 /*@} */
 
 
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_register_aliases     Backwards Compatibility Aliases
+  \brief      Register alias definitions for backwards compatibility.
+  @{
+ */
+#define ID_ADR  (ID_AFR)    /*!< SCB Auxiliary Feature Register */
+/*@} */
+
 
 /*******************************************************************************
  *                Hardware Abstraction Layer

CMSIS/Core/Include/core_cm33.h

@@ -1,8 +1,8 @@
 /**************************************************************************//**
  * @file     core_cm33.h
  * @brief    CMSIS Cortex-M33 Core Peripheral Access Layer Header File
- * @version  V5.2.2
- * @date     04. June 2021
+ * @version  V5.2.3
+ * @date     13. October 2021
  ******************************************************************************/
 /*
  * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
@@ -519,7 +519,7 @@ typedef struct
   __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
   __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
   __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
-  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
   __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
   __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
   __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
@@ -528,7 +528,10 @@ typedef struct
   __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
   __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
   __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
-        uint32_t RESERVED3[92U];
+        uint32_t RESERVED7[21U];
+  __IOM uint32_t SFSR;                   /*!< Offset: 0x0E4 (R/W)  Secure Fault Status Register */
+  __IOM uint32_t SFAR;                   /*!< Offset: 0x0E8 (R/W)  Secure Fault Address Register */
+        uint32_t RESERVED3[69U];
   __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
         uint32_t RESERVED4[15U];
   __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
@@ -2257,6 +2260,15 @@ typedef struct
 /*@} */
 
 
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_register_aliases     Backwards Compatibility Aliases
+  \brief      Register alias definitions for backwards compatibility.
+  @{
+ */
+#define ID_ADR  (ID_AFR)    /*!< SCB Auxiliary Feature Register */
+/*@} */
+
 
 /*******************************************************************************
  *                Hardware Abstraction Layer

CMSIS/Core/Include/core_cm35p.h

@@ -1,8 +1,8 @@
 /**************************************************************************//**
  * @file     core_cm35p.h
  * @brief    CMSIS Cortex-M35P Core Peripheral Access Layer Header File
- * @version  V1.1.2
- * @date     04. June 2021
+ * @version  V1.1.3
+ * @date     13. October 2021
  ******************************************************************************/
 /*
  * Copyright (c) 2018-2021 Arm Limited. All rights reserved.
@@ -519,7 +519,7 @@ typedef struct
   __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
   __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
   __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
-  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
   __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
   __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
   __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
@@ -528,7 +528,10 @@ typedef struct
   __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
   __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
   __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
-        uint32_t RESERVED3[92U];
+        uint32_t RESERVED7[21U];
+  __IOM uint32_t SFSR;                   /*!< Offset: 0x0E4 (R/W)  Secure Fault Status Register */
+  __IOM uint32_t SFAR;                   /*!< Offset: 0x0E8 (R/W)  Secure Fault Address Register */
+        uint32_t RESERVED3[69U];
   __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
         uint32_t RESERVED4[15U];
   __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
@@ -2257,6 +2260,15 @@ typedef struct
 /*@} */
 
 
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_register_aliases     Backwards Compatibility Aliases
+  \brief      Register alias definitions for backwards compatibility.
+  @{
+ */
+#define ID_ADR  (ID_AFR)    /*!< SCB Auxiliary Feature Register */
+/*@} */
+
 
 /*******************************************************************************
  *                Hardware Abstraction Layer

CMSIS/Core/Include/core_cm55.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     core_cm55.h
  * @brief    CMSIS Cortex-M55 Core Peripheral Access Layer Header File
- * @version  V1.2.1
- * @date     04. June 2021
+ * @version  V1.2.4
+ * @date     21. April 2022
  ******************************************************************************/
 /*
- * Copyright (c) 2018-2021 Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2022 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -58,7 +58,7 @@
  *                 CMSIS definitions
  ******************************************************************************/
 /**
-  \ingroup Cortex_CM55
+  \ingroup Cortex_M55
   @{
  */
 
@@ -303,9 +303,11 @@
   Core Register contain:
   - Core Register
   - Core NVIC Register
+  - Core EWIC Register
   - Core SCB Register
   - Core SysTick Register
   - Core Debug Register
+  - Core PMU Register
   - Core MPU Register
   - Core SAU Register
   - Core FPU Register
@@ -526,7 +528,7 @@ typedef struct
   __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
   __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
   __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
-  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
   __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
   __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
   __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
@@ -535,7 +537,10 @@ typedef struct
   __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
   __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
   __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
-        uint32_t RESERVED3[92U];
+        uint32_t RESERVED7[21U];
+  __IOM uint32_t SFSR;                   /*!< Offset: 0x0E4 (R/W)  Secure Fault Status Register */
+  __IOM uint32_t SFAR;                   /*!< Offset: 0x0E8 (R/W)  Secure Fault Address Register */
+        uint32_t RESERVED3[69U];
   __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
   __IOM uint32_t RFSR;                   /*!< Offset: 0x204 (R/W)  RAS Fault Status Register */
         uint32_t RESERVED4[14U];
@@ -987,13 +992,13 @@ typedef struct
 
 /**
   \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-  \brief    Type definitions for the System Control and ID Register not in the SCB
+  \defgroup CMSIS_ICB Implementation Control Block register (ICB)
+  \brief    Type definitions for the Implementation Control Block Register
   @{
  */
 
 /**
-  \brief  Structure type to access the System Control and ID Register not in the SCB.
+  \brief  Structure type to access the Implementation Control Block (ICB).
  */
 typedef struct
 {
@@ -1001,13 +1006,56 @@ typedef struct
   __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
   __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
   __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
-} SCnSCB_Type;
+} ICB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define ICB_ACTLR_DISCRITAXIRUW_Pos     27U                                               /*!< ACTLR: DISCRITAXIRUW Position */
+#define ICB_ACTLR_DISCRITAXIRUW_Msk     (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos)              /*!< ACTLR: DISCRITAXIRUW Mask */
+
+#define ICB_ACTLR_DISDI_Pos             16U                                               /*!< ACTLR: DISDI Position */
+#define ICB_ACTLR_DISDI_Msk             (3UL << ICB_ACTLR_DISDI_Pos)                      /*!< ACTLR: DISDI Mask */
+
+#define ICB_ACTLR_DISCRITAXIRUR_Pos     15U                                               /*!< ACTLR: DISCRITAXIRUR Position */
+#define ICB_ACTLR_DISCRITAXIRUR_Msk     (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos)              /*!< ACTLR: DISCRITAXIRUR Mask */
+
+#define ICB_ACTLR_EVENTBUSEN_Pos        14U                                               /*!< ACTLR: EVENTBUSEN Position */
+#define ICB_ACTLR_EVENTBUSEN_Msk        (1UL << ICB_ACTLR_EVENTBUSEN_Pos)                 /*!< ACTLR: EVENTBUSEN Mask */
+
+#define ICB_ACTLR_EVENTBUSEN_S_Pos      13U                                               /*!< ACTLR: EVENTBUSEN_S Position */
+#define ICB_ACTLR_EVENTBUSEN_S_Msk      (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos)               /*!< ACTLR: EVENTBUSEN_S Mask */
+
+#define ICB_ACTLR_DISITMATBFLUSH_Pos    12U                                               /*!< ACTLR: DISITMATBFLUSH Position */
+#define ICB_ACTLR_DISITMATBFLUSH_Msk    (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos)             /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define ICB_ACTLR_DISNWAMODE_Pos        11U                                               /*!< ACTLR: DISNWAMODE Position */
+#define ICB_ACTLR_DISNWAMODE_Msk        (1UL << ICB_ACTLR_DISNWAMODE_Pos)                 /*!< ACTLR: DISNWAMODE Mask */
+
+#define ICB_ACTLR_FPEXCODIS_Pos         10U                                               /*!< ACTLR: FPEXCODIS Position */
+#define ICB_ACTLR_FPEXCODIS_Msk         (1UL << ICB_ACTLR_FPEXCODIS_Pos)                  /*!< ACTLR: FPEXCODIS Mask */
+
+#define ICB_ACTLR_DISOLAP_Pos            7U                                               /*!< ACTLR: DISOLAP Position */
+#define ICB_ACTLR_DISOLAP_Msk           (1UL << ICB_ACTLR_DISOLAP_Pos)                    /*!< ACTLR: DISOLAP Mask */
+
+#define ICB_ACTLR_DISOLAPS_Pos           6U                                               /*!< ACTLR: DISOLAPS Position */
+#define ICB_ACTLR_DISOLAPS_Msk          (1UL << ICB_ACTLR_DISOLAPS_Pos)                   /*!< ACTLR: DISOLAPS Mask */
+
+#define ICB_ACTLR_DISLOBR_Pos            5U                                               /*!< ACTLR: DISLOBR Position */
+#define ICB_ACTLR_DISLOBR_Msk           (1UL << ICB_ACTLR_DISLOBR_Pos)                    /*!< ACTLR: DISLOBR Mask */
+
+#define ICB_ACTLR_DISLO_Pos              4U                                               /*!< ACTLR: DISLO Position */
+#define ICB_ACTLR_DISLO_Msk             (1UL << ICB_ACTLR_DISLO_Pos)                      /*!< ACTLR: DISLO Mask */
+
+#define ICB_ACTLR_DISLOLEP_Pos           3U                                               /*!< ACTLR: DISLOLEP Position */
+#define ICB_ACTLR_DISLOLEP_Msk          (1UL << ICB_ACTLR_DISLOLEP_Pos)                   /*!< ACTLR: DISLOLEP Mask */
+
+#define ICB_ACTLR_DISFOLD_Pos            2U                                               /*!< ACTLR: DISFOLD Position */
+#define ICB_ACTLR_DISFOLD_Msk           (1UL << ICB_ACTLR_DISFOLD_Pos)                    /*!< ACTLR: DISFOLD Mask */
 
 /* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+#define ICB_ICTR_INTLINESNUM_Pos         0U                                               /*!< ICTR: INTLINESNUM Position */
+#define ICB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/)           /*!< ICTR: INTLINESNUM Mask */
 
-/*@} end of group CMSIS_SCnotSCB */
+/*@} end of group CMSIS_ICB */
 
 
 /**
@@ -1349,6 +1397,133 @@ typedef struct
 /*@}*/ /* end of group CMSIS_DWT */
 
 
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup MemSysCtl_Type     Memory System Control Registers (IMPLEMENTATION DEFINED)
+  \brief    Type definitions for the Memory System Control Registers (MEMSYSCTL)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory System Control Registers (MEMSYSCTL).
+ */
+typedef struct
+{
+  __IOM uint32_t MSCR;                   /*!< Offset: 0x000 (R/W)  Memory System Control Register */
+  __IOM uint32_t PFCR;                   /*!< Offset: 0x004 (R/W)  Prefetcher Control Register */
+        uint32_t RESERVED1[2U];
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x010 (R/W)  ITCM Control Register */
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x014 (R/W)  DTCM Control Register */
+  __IOM uint32_t PAHBCR;                 /*!< Offset: 0x018 (R/W)  P-AHB Control Register */
+        uint32_t RESERVED2[313U];
+  __IOM uint32_t ITGU_CTRL;              /*!< Offset: 0x500 (R/W)  ITGU Control Register */
+  __IOM uint32_t ITGU_CFG;               /*!< Offset: 0x504 (R/W)  ITGU Configuration Register */
+        uint32_t RESERVED3[2U];
+  __IOM uint32_t ITGU_LUT[16U];          /*!< Offset: 0x510 (R/W)  ITGU Look Up Table Register */
+        uint32_t RESERVED4[44U];
+  __IOM uint32_t DTGU_CTRL;              /*!< Offset: 0x600 (R/W)  DTGU Control Registers */
+  __IOM uint32_t DTGU_CFG;               /*!< Offset: 0x604 (R/W)  DTGU Configuration Register */
+        uint32_t RESERVED5[2U];
+  __IOM uint32_t DTGU_LUT[16U];          /*!< Offset: 0x610 (R/W)  DTGU Look Up Table Register */
+} MemSysCtl_Type;
+
+/* MEMSYSCTL Memory System Control Register (MSCR) Register Definitions */
+#define MEMSYSCTL_MSCR_CPWRDN_Pos          17U                                         /*!< MEMSYSCTL MSCR: CPWRDN Position */
+#define MEMSYSCTL_MSCR_CPWRDN_Msk          (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos)        /*!< MEMSYSCTL MSCR: CPWRDN Mask */
+
+#define MEMSYSCTL_MSCR_DCCLEAN_Pos         16U                                         /*!< MEMSYSCTL MSCR: DCCLEAN Position */
+#define MEMSYSCTL_MSCR_DCCLEAN_Msk         (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos)       /*!< MEMSYSCTL MSCR: DCCLEAN Mask */
+
+#define MEMSYSCTL_MSCR_ICACTIVE_Pos        13U                                         /*!< MEMSYSCTL MSCR: ICACTIVE Position */
+#define MEMSYSCTL_MSCR_ICACTIVE_Msk        (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos)      /*!< MEMSYSCTL MSCR: ICACTIVE Mask */
+
+#define MEMSYSCTL_MSCR_DCACTIVE_Pos        12U                                         /*!< MEMSYSCTL MSCR: DCACTIVE Position */
+#define MEMSYSCTL_MSCR_DCACTIVE_Msk        (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos)      /*!< MEMSYSCTL MSCR: DCACTIVE Mask */
+
+#define MEMSYSCTL_MSCR_TECCCHKDIS_Pos       4U                                         /*!< MEMSYSCTL MSCR: TECCCHKDIS Position */
+#define MEMSYSCTL_MSCR_TECCCHKDIS_Msk      (0x1UL << MEMSYSCTL_MSCR_TECCCHKDIS_Pos)    /*!< MEMSYSCTL MSCR: TECCCHKDIS Mask */
+
+#define MEMSYSCTL_MSCR_EVECCFAULT_Pos       3U                                         /*!< MEMSYSCTL MSCR: EVECCFAULT Position */
+#define MEMSYSCTL_MSCR_EVECCFAULT_Msk      (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos)    /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */
+
+#define MEMSYSCTL_MSCR_FORCEWT_Pos          2U                                         /*!< MEMSYSCTL MSCR: FORCEWT Position */
+#define MEMSYSCTL_MSCR_FORCEWT_Msk         (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos)       /*!< MEMSYSCTL MSCR: FORCEWT Mask */
+
+#define MEMSYSCTL_MSCR_ECCEN_Pos            1U                                         /*!< MEMSYSCTL MSCR: ECCEN Position */
+#define MEMSYSCTL_MSCR_ECCEN_Msk           (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos)         /*!< MEMSYSCTL MSCR: ECCEN Mask */
+
+/* MEMSYSCTL Prefetcher Control Register (PFCR) Register Definitions */
+#define MEMSYSCTL_PFCR_MAX_OS_Pos           7U                                         /*!< MEMSYSCTL PFCR: MAX_OS Position */
+#define MEMSYSCTL_PFCR_MAX_OS_Msk          (0x7UL << MEMSYSCTL_PFCR_MAX_OS_Pos)        /*!< MEMSYSCTL PFCR: MAX_OS Mask */
+
+#define MEMSYSCTL_PFCR_MAX_LA_Pos           4U                                         /*!< MEMSYSCTL PFCR: MAX_LA Position */
+#define MEMSYSCTL_PFCR_MAX_LA_Msk          (0x7UL << MEMSYSCTL_PFCR_MAX_LA_Pos)        /*!< MEMSYSCTL PFCR: MAX_LA Mask */
+
+#define MEMSYSCTL_PFCR_MIN_LA_Pos           1U                                         /*!< MEMSYSCTL PFCR: MIN_LA Position */
+#define MEMSYSCTL_PFCR_MIN_LA_Msk          (0x7UL << MEMSYSCTL_PFCR_MIN_LA_Pos)        /*!< MEMSYSCTL PFCR: MIN_LA Mask */
+
+#define MEMSYSCTL_PFCR_ENABLE_Pos           0U                                         /*!< MEMSYSCTL PFCR: ENABLE Position */
+#define MEMSYSCTL_PFCR_ENABLE_Msk          (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/)    /*!< MEMSYSCTL PFCR: ENABLE Mask */
+
+/* MEMSYSCTL ITCM Control Register (ITCMCR) Register Definitions */
+#define MEMSYSCTL_ITCMCR_SZ_Pos             3U                                         /*!< MEMSYSCTL ITCMCR: SZ Position */
+#define MEMSYSCTL_ITCMCR_SZ_Msk            (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos)          /*!< MEMSYSCTL ITCMCR: SZ Mask */
+
+#define MEMSYSCTL_ITCMCR_EN_Pos             0U                                         /*!< MEMSYSCTL ITCMCR: EN Position */
+#define MEMSYSCTL_ITCMCR_EN_Msk            (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/)      /*!< MEMSYSCTL ITCMCR: EN Mask */
+
+/* MEMSYSCTL DTCM Control Register (DTCMCR) Register Definitions */
+#define MEMSYSCTL_DTCMCR_SZ_Pos             3U                                         /*!< MEMSYSCTL DTCMCR: SZ Position */
+#define MEMSYSCTL_DTCMCR_SZ_Msk            (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos)          /*!< MEMSYSCTL DTCMCR: SZ Mask */
+
+#define MEMSYSCTL_DTCMCR_EN_Pos             0U                                         /*!< MEMSYSCTL DTCMCR: EN Position */
+#define MEMSYSCTL_DTCMCR_EN_Msk            (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/)      /*!< MEMSYSCTL DTCMCR: EN Mask */
+
+/* MEMSYSCTL P-AHB Control Register (PAHBCR) Register Definitions */
+#define MEMSYSCTL_PAHBCR_SZ_Pos             1U                                         /*!< MEMSYSCTL PAHBCR: SZ Position */
+#define MEMSYSCTL_PAHBCR_SZ_Msk            (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos)          /*!< MEMSYSCTL PAHBCR: SZ Mask */
+
+#define MEMSYSCTL_PAHBCR_EN_Pos             0U                                         /*!< MEMSYSCTL PAHBCR: EN Position */
+#define MEMSYSCTL_PAHBCR_EN_Msk            (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/)      /*!< MEMSYSCTL PAHBCR: EN Mask */
+
+/* MEMSYSCTL ITGU Control Register (ITGU_CTRL) Register Definitions */
+#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos       1U                                         /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */
+#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk      (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos)    /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */
+
+#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos       0U                                         /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */
+#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk      (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */
+
+/* MEMSYSCTL ITGU Configuration Register (ITGU_CFG) Register Definitions */
+#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos     31U                                         /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */
+#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk     (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos)   /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */
+
+#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos      8U                                         /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */
+#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk     (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos)   /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */
+
+#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos        0U                                         /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */
+#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk       (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */
+
+/* MEMSYSCTL DTGU Control Registers (DTGU_CTRL) Register Definitions */
+#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos       1U                                         /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */
+#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk      (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos)    /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */
+
+#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos       0U                                         /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */
+#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk      (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */
+
+/* MEMSYSCTL DTGU Configuration Register (DTGU_CFG) Register Definitions */
+#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos     31U                                         /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */
+#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk     (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos)   /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */
+
+#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos      8U                                         /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */
+#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk     (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos)   /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */
+
+#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos        0U                                         /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */
+#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk       (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */
+
+
+/*@}*/ /* end of group MemSysCtl_Type */
+
+
 /**
   \ingroup  CMSIS_core_register
   \defgroup PwrModCtl_Type     Power Mode Control Registers
@@ -1361,26 +1536,315 @@ typedef struct
  */
 typedef struct
 {
-  __IOM uint32_t CPDLPSTATE;
-  __IOM uint32_t DPDLPSTATE;
+  __IOM uint32_t CPDLPSTATE;             /*!< Offset: 0x000 (R/W)  Core Power Domain Low Power State Register */
+  __IOM uint32_t DPDLPSTATE;             /*!< Offset: 0x004 (R/W)  Debug Power Domain Low Power State Register */
 } PwrModCtl_Type;
 
-
 /* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */
-#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos                 0U                           /*!< PWRMODCTL CPDLPSTATE CLPSTATE Position */
-#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk                 3UL                          /*!< PWRMODCTL CPDLPSTATE CLPSTATE Mask */
+#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos   8U                                              /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */
+#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk  (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos)     /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */
 
-#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos                 4U                           /*!< PWRMODCTL CPDLPSTATE ELPSTATE Position */
-#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk                 3UL                          /*!< PWRMODCTL CPDLPSTATE ELPSTATE Mask */
+#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos   4U                                              /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */
+#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk  (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos)     /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */
 
-#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos                 8U                           /*!< PWRMODCTL CPDLPSTATE RLPSTATE Position */
-#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk                 3UL                          /*!< PWRMODCTL CPDLPSTATE RLPSTATE Mask */
+#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos   0U                                              /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */
+#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk  (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */
 
 /* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */
-#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos                 0U                           /*!< PWRMODCTL DPDLPSTATE DLPSTATE Position */
-#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk                 3UL                          /*!< PWRMODCTL DPDLPSTATE DLPSTATE Mask */
+#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos   0U                                              /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */
+#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk  (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */
 
-/*@}*/ /* end of group CMSIS_PWRMODCTL */
+/*@}*/ /* end of group PwrModCtl_Type */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup EWIC_Type     External Wakeup Interrupt Controller Registers
+  \brief    Type definitions for the External Wakeup Interrupt Controller Registers (EWIC)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the External Wakeup Interrupt Controller Registers (EWIC).
+ */
+typedef struct
+{
+  __OM  uint32_t EVENTSPR;               /*!< Offset: 0x000 ( /W)  Event Set Pending Register */
+        uint32_t RESERVED0[31U];
+  __IM  uint32_t EVENTMASKA;             /*!< Offset: 0x080 (R/W)  Event Mask A Register */
+  __IM  uint32_t EVENTMASK[15];          /*!< Offset: 0x084 (R/W)  Event Mask Register */
+} EWIC_Type;
+
+/* EWIC External Wakeup Interrupt Controller (EVENTSPR) Register Definitions */
+#define EWIC_EVENTSPR_EDBGREQ_Pos   2U                                                 /*!< EWIC EVENTSPR: EDBGREQ Position */
+#define EWIC_EVENTSPR_EDBGREQ_Msk  (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos)                /*!< EWIC EVENTSPR: EDBGREQ Mask */
+
+#define EWIC_EVENTSPR_NMI_Pos   1U                                                     /*!< EWIC EVENTSPR: NMI Position */
+#define EWIC_EVENTSPR_NMI_Msk  (0x1UL << EWIC_EVENTSPR_NMI_Pos)                        /*!< EWIC EVENTSPR: NMI Mask */
+
+#define EWIC_EVENTSPR_EVENT_Pos   0U                                                   /*!< EWIC EVENTSPR: EVENT Position */
+#define EWIC_EVENTSPR_EVENT_Msk  (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/)                /*!< EWIC EVENTSPR: EVENT Mask */
+
+/* EWIC External Wakeup Interrupt Controller (EVENTMASKA) Register Definitions */
+#define EWIC_EVENTMASKA_EDBGREQ_Pos   2U                                               /*!< EWIC EVENTMASKA: EDBGREQ Position */
+#define EWIC_EVENTMASKA_EDBGREQ_Msk  (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos)            /*!< EWIC EVENTMASKA: EDBGREQ Mask */
+
+#define EWIC_EVENTMASKA_NMI_Pos   1U                                                   /*!< EWIC EVENTMASKA: NMI Position */
+#define EWIC_EVENTMASKA_NMI_Msk  (0x1UL << EWIC_EVENTMASKA_NMI_Pos)                    /*!< EWIC EVENTMASKA: NMI Mask */
+
+#define EWIC_EVENTMASKA_EVENT_Pos   0U                                                 /*!< EWIC EVENTMASKA: EVENT Position */
+#define EWIC_EVENTMASKA_EVENT_Msk  (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/)            /*!< EWIC EVENTMASKA: EVENT Mask */
+
+/* EWIC External Wakeup Interrupt Controller (EVENTMASK) Register Definitions */
+#define EWIC_EVENTMASK_IRQ_Pos   0U                                                    /*!< EWIC EVENTMASKA: IRQ Position */
+#define EWIC_EVENTMASK_IRQ_Msk  (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/)          /*!< EWIC EVENTMASKA: IRQ Mask */
+
+/*@}*/ /* end of group EWIC_Type */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup ErrBnk_Type     Error Banking Registers (IMPLEMENTATION DEFINED)
+  \brief    Type definitions for the Error Banking Registers (ERRBNK)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Error Banking Registers (ERRBNK).
+ */
+typedef struct
+{
+  __IOM uint32_t IEBR0;                  /*!< Offset: 0x000 (R/W)  Instruction Cache Error Bank Register 0 */
+  __IOM uint32_t IEBR1;                  /*!< Offset: 0x004 (R/W)  Instruction Cache Error Bank Register 1 */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t DEBR0;                  /*!< Offset: 0x010 (R/W)  Data Cache Error Bank Register 0 */
+  __IOM uint32_t DEBR1;                  /*!< Offset: 0x014 (R/W)  Data Cache Error Bank Register 1 */
+        uint32_t RESERVED1[2U];
+  __IOM uint32_t TEBR0;                  /*!< Offset: 0x020 (R/W)  TCM Error Bank Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t TEBR1;                  /*!< Offset: 0x028 (R/W)  TCM Error Bank Register 1 */
+} ErrBnk_Type;
+
+/* ERRBNK Instruction Cache Error Bank Register 0 (IEBR0) Register Definitions */
+#define ERRBNK_IEBR0_SWDEF_Pos             30U                                         /*!< ERRBNK IEBR0: SWDEF Position */
+#define ERRBNK_IEBR0_SWDEF_Msk             (0x3UL << ERRBNK_IEBR0_SWDEF_Pos)           /*!< ERRBNK IEBR0: SWDEF Mask */
+
+#define ERRBNK_IEBR0_BANK_Pos              16U                                         /*!< ERRBNK IEBR0: BANK Position */
+#define ERRBNK_IEBR0_BANK_Msk              (0x1UL << ERRBNK_IEBR0_BANK_Pos)            /*!< ERRBNK IEBR0: BANK Mask */
+
+#define ERRBNK_IEBR0_LOCATION_Pos           2U                                         /*!< ERRBNK IEBR0: LOCATION Position */
+#define ERRBNK_IEBR0_LOCATION_Msk          (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos)     /*!< ERRBNK IEBR0: LOCATION Mask */
+
+#define ERRBNK_IEBR0_LOCKED_Pos             1U                                         /*!< ERRBNK IEBR0: LOCKED Position */
+#define ERRBNK_IEBR0_LOCKED_Msk            (0x1UL << ERRBNK_IEBR0_LOCKED_Pos)          /*!< ERRBNK IEBR0: LOCKED Mask */
+
+#define ERRBNK_IEBR0_VALID_Pos              0U                                         /*!< ERRBNK IEBR0: VALID Position */
+#define ERRBNK_IEBR0_VALID_Msk             (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/)       /*!< ERRBNK IEBR0: VALID Mask */
+
+/* ERRBNK Instruction Cache Error Bank Register 1 (IEBR1) Register Definitions */
+#define ERRBNK_IEBR1_SWDEF_Pos             30U                                         /*!< ERRBNK IEBR1: SWDEF Position */
+#define ERRBNK_IEBR1_SWDEF_Msk             (0x3UL << ERRBNK_IEBR1_SWDEF_Pos)           /*!< ERRBNK IEBR1: SWDEF Mask */
+
+#define ERRBNK_IEBR1_BANK_Pos              16U                                         /*!< ERRBNK IEBR1: BANK Position */
+#define ERRBNK_IEBR1_BANK_Msk              (0x1UL << ERRBNK_IEBR1_BANK_Pos)            /*!< ERRBNK IEBR1: BANK Mask */
+
+#define ERRBNK_IEBR1_LOCATION_Pos           2U                                         /*!< ERRBNK IEBR1: LOCATION Position */
+#define ERRBNK_IEBR1_LOCATION_Msk          (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos)     /*!< ERRBNK IEBR1: LOCATION Mask */
+
+#define ERRBNK_IEBR1_LOCKED_Pos             1U                                         /*!< ERRBNK IEBR1: LOCKED Position */
+#define ERRBNK_IEBR1_LOCKED_Msk            (0x1UL << ERRBNK_IEBR1_LOCKED_Pos)          /*!< ERRBNK IEBR1: LOCKED Mask */
+
+#define ERRBNK_IEBR1_VALID_Pos              0U                                         /*!< ERRBNK IEBR1: VALID Position */
+#define ERRBNK_IEBR1_VALID_Msk             (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/)       /*!< ERRBNK IEBR1: VALID Mask */
+
+/* ERRBNK Data Cache Error Bank Register 0 (DEBR0) Register Definitions */
+#define ERRBNK_DEBR0_SWDEF_Pos             30U                                         /*!< ERRBNK DEBR0: SWDEF Position */
+#define ERRBNK_DEBR0_SWDEF_Msk             (0x3UL << ERRBNK_DEBR0_SWDEF_Pos)           /*!< ERRBNK DEBR0: SWDEF Mask */
+
+#define ERRBNK_DEBR0_TYPE_Pos              17U                                         /*!< ERRBNK DEBR0: TYPE Position */
+#define ERRBNK_DEBR0_TYPE_Msk              (0x1UL << ERRBNK_DEBR0_TYPE_Pos)            /*!< ERRBNK DEBR0: TYPE Mask */
+
+#define ERRBNK_DEBR0_BANK_Pos              16U                                         /*!< ERRBNK DEBR0: BANK Position */
+#define ERRBNK_DEBR0_BANK_Msk              (0x1UL << ERRBNK_DEBR0_BANK_Pos)            /*!< ERRBNK DEBR0: BANK Mask */
+
+#define ERRBNK_DEBR0_LOCATION_Pos           2U                                         /*!< ERRBNK DEBR0: LOCATION Position */
+#define ERRBNK_DEBR0_LOCATION_Msk          (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos)     /*!< ERRBNK DEBR0: LOCATION Mask */
+
+#define ERRBNK_DEBR0_LOCKED_Pos             1U                                         /*!< ERRBNK DEBR0: LOCKED Position */
+#define ERRBNK_DEBR0_LOCKED_Msk            (0x1UL << ERRBNK_DEBR0_LOCKED_Pos)          /*!< ERRBNK DEBR0: LOCKED Mask */
+
+#define ERRBNK_DEBR0_VALID_Pos              0U                                         /*!< ERRBNK DEBR0: VALID Position */
+#define ERRBNK_DEBR0_VALID_Msk             (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/)       /*!< ERRBNK DEBR0: VALID Mask */
+
+/* ERRBNK Data Cache Error Bank Register 1 (DEBR1) Register Definitions */
+#define ERRBNK_DEBR1_SWDEF_Pos             30U                                         /*!< ERRBNK DEBR1: SWDEF Position */
+#define ERRBNK_DEBR1_SWDEF_Msk             (0x3UL << ERRBNK_DEBR1_SWDEF_Pos)           /*!< ERRBNK DEBR1: SWDEF Mask */
+
+#define ERRBNK_DEBR1_TYPE_Pos              17U                                         /*!< ERRBNK DEBR1: TYPE Position */
+#define ERRBNK_DEBR1_TYPE_Msk              (0x1UL << ERRBNK_DEBR1_TYPE_Pos)            /*!< ERRBNK DEBR1: TYPE Mask */
+
+#define ERRBNK_DEBR1_BANK_Pos              16U                                         /*!< ERRBNK DEBR1: BANK Position */
+#define ERRBNK_DEBR1_BANK_Msk              (0x1UL << ERRBNK_DEBR1_BANK_Pos)            /*!< ERRBNK DEBR1: BANK Mask */
+
+#define ERRBNK_DEBR1_LOCATION_Pos           2U                                         /*!< ERRBNK DEBR1: LOCATION Position */
+#define ERRBNK_DEBR1_LOCATION_Msk          (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos)     /*!< ERRBNK DEBR1: LOCATION Mask */
+
+#define ERRBNK_DEBR1_LOCKED_Pos             1U                                         /*!< ERRBNK DEBR1: LOCKED Position */
+#define ERRBNK_DEBR1_LOCKED_Msk            (0x1UL << ERRBNK_DEBR1_LOCKED_Pos)          /*!< ERRBNK DEBR1: LOCKED Mask */
+
+#define ERRBNK_DEBR1_VALID_Pos              0U                                         /*!< ERRBNK DEBR1: VALID Position */
+#define ERRBNK_DEBR1_VALID_Msk             (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/)       /*!< ERRBNK DEBR1: VALID Mask */
+
+/* ERRBNK TCM Error Bank Register 0 (TEBR0) Register Definitions */
+#define ERRBNK_TEBR0_SWDEF_Pos             30U                                         /*!< ERRBNK TEBR0: SWDEF Position */
+#define ERRBNK_TEBR0_SWDEF_Msk             (0x3UL << ERRBNK_TEBR0_SWDEF_Pos)           /*!< ERRBNK TEBR0: SWDEF Mask */
+
+#define ERRBNK_TEBR0_POISON_Pos            28U                                         /*!< ERRBNK TEBR0: POISON Position */
+#define ERRBNK_TEBR0_POISON_Msk            (0x1UL << ERRBNK_TEBR0_POISON_Pos)          /*!< ERRBNK TEBR0: POISON Mask */
+
+#define ERRBNK_TEBR0_TYPE_Pos              27U                                         /*!< ERRBNK TEBR0: TYPE Position */
+#define ERRBNK_TEBR0_TYPE_Msk              (0x1UL << ERRBNK_TEBR0_TYPE_Pos)            /*!< ERRBNK TEBR0: TYPE Mask */
+
+#define ERRBNK_TEBR0_BANK_Pos              24U                                         /*!< ERRBNK TEBR0: BANK Position */
+#define ERRBNK_TEBR0_BANK_Msk              (0x3UL << ERRBNK_TEBR0_BANK_Pos)            /*!< ERRBNK TEBR0: BANK Mask */
+
+#define ERRBNK_TEBR0_LOCATION_Pos           2U                                         /*!< ERRBNK TEBR0: LOCATION Position */
+#define ERRBNK_TEBR0_LOCATION_Msk          (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos)   /*!< ERRBNK TEBR0: LOCATION Mask */
+
+#define ERRBNK_TEBR0_LOCKED_Pos             1U                                         /*!< ERRBNK TEBR0: LOCKED Position */
+#define ERRBNK_TEBR0_LOCKED_Msk            (0x1UL << ERRBNK_TEBR0_LOCKED_Pos)          /*!< ERRBNK TEBR0: LOCKED Mask */
+
+#define ERRBNK_TEBR0_VALID_Pos              0U                                         /*!< ERRBNK TEBR0: VALID Position */
+#define ERRBNK_TEBR0_VALID_Msk             (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/)       /*!< ERRBNK TEBR0: VALID Mask */
+
+/* ERRBNK TCM Error Bank Register 1 (TEBR1) Register Definitions */
+#define ERRBNK_TEBR1_SWDEF_Pos             30U                                         /*!< ERRBNK TEBR1: SWDEF Position */
+#define ERRBNK_TEBR1_SWDEF_Msk             (0x3UL << ERRBNK_TEBR1_SWDEF_Pos)           /*!< ERRBNK TEBR1: SWDEF Mask */
+
+#define ERRBNK_TEBR1_POISON_Pos            28U                                         /*!< ERRBNK TEBR1: POISON Position */
+#define ERRBNK_TEBR1_POISON_Msk            (0x1UL << ERRBNK_TEBR1_POISON_Pos)          /*!< ERRBNK TEBR1: POISON Mask */
+
+#define ERRBNK_TEBR1_TYPE_Pos              27U                                         /*!< ERRBNK TEBR1: TYPE Position */
+#define ERRBNK_TEBR1_TYPE_Msk              (0x1UL << ERRBNK_TEBR1_TYPE_Pos)            /*!< ERRBNK TEBR1: TYPE Mask */
+
+#define ERRBNK_TEBR1_BANK_Pos              24U                                         /*!< ERRBNK TEBR1: BANK Position */
+#define ERRBNK_TEBR1_BANK_Msk              (0x3UL << ERRBNK_TEBR1_BANK_Pos)            /*!< ERRBNK TEBR1: BANK Mask */
+
+#define ERRBNK_TEBR1_LOCATION_Pos           2U                                         /*!< ERRBNK TEBR1: LOCATION Position */
+#define ERRBNK_TEBR1_LOCATION_Msk          (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos)   /*!< ERRBNK TEBR1: LOCATION Mask */
+
+#define ERRBNK_TEBR1_LOCKED_Pos             1U                                         /*!< ERRBNK TEBR1: LOCKED Position */
+#define ERRBNK_TEBR1_LOCKED_Msk            (0x1UL << ERRBNK_TEBR1_LOCKED_Pos)          /*!< ERRBNK TEBR1: LOCKED Mask */
+
+#define ERRBNK_TEBR1_VALID_Pos              0U                                         /*!< ERRBNK TEBR1: VALID Position */
+#define ERRBNK_TEBR1_VALID_Msk             (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/)       /*!< ERRBNK TEBR1: VALID Mask */
+
+/*@}*/ /* end of group ErrBnk_Type */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup PrcCfgInf_Type     Processor Configuration Information Registers (IMPLEMENTATION DEFINED)
+  \brief    Type definitions for the Processor Configuration Information Registerss (PRCCFGINF)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Processor Configuration Information Registerss (PRCCFGINF).
+ */
+typedef struct
+{
+  __OM  uint32_t CFGINFOSEL;             /*!< Offset: 0x000 ( /W)  Processor Configuration Information Selection Register */
+  __IM  uint32_t CFGINFORD;              /*!< Offset: 0x004 (R/ )  Processor Configuration Information Read Data Register */
+} PrcCfgInf_Type;
+
+/* PRCCFGINF Processor Configuration Information Selection Register (CFGINFOSEL) Definitions */
+
+/* PRCCFGINF Processor Configuration Information Read Data Register (CFGINFORD) Definitions */
+
+/*@}*/ /* end of group PrcCfgInf_Type */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup STL_Type     Software Test Library Observation Registers
+  \brief    Type definitions for the Software Test Library Observation Registerss (STL)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Software Test Library Observation Registerss (STL).
+ */
+typedef struct
+{
+  __IM  uint32_t STLNVICPENDOR;          /*!< Offset: 0x000 (R/ )  NVIC Pending Priority Tree Register */
+  __IM  uint32_t STLNVICACTVOR;          /*!< Offset: 0x004 (R/ )  NVIC Active Priority Tree Register */
+        uint32_t RESERVED0[2U];
+  __OM  uint32_t STLIDMPUSR;             /*!< Offset: 0x010 ( /W)  MPU Sanple Register */
+  __IM  uint32_t STLIMPUOR;              /*!< Offset: 0x014 (R/ )  MPU Region Hit Register */
+  __IM  uint32_t STLD0MPUOR;             /*!< Offset: 0x018 (R/ )  MPU Memory Attributes Register 0 */
+  __IM  uint32_t STLD1MPUOR;             /*!< Offset: 0x01C (R/ )  MPU Memory Attributes Register 1 */
+
+} STL_Type;
+
+/* STL Software Test Library Observation Register (STLNVICPENDOR) Definitions */
+#define STL_STLNVICPENDOR_VALID_Pos        18U                                         /*!< STL STLNVICPENDOR: VALID Position */
+#define STL_STLNVICPENDOR_VALID_Msk        (0x1UL << STL_STLNVICPENDOR_VALID_Pos)      /*!< STL STLNVICPENDOR: VALID Mask */
+
+#define STL_STLNVICPENDOR_TARGET_Pos       17U                                         /*!< STL STLNVICPENDOR: TARGET Position */
+#define STL_STLNVICPENDOR_TARGET_Msk       (0x1UL << STL_STLNVICPENDOR_TARGET_Pos)     /*!< STL STLNVICPENDOR: TARGET Mask */
+
+#define STL_STLNVICPENDOR_PRIORITY_Pos      9U                                         /*!< STL STLNVICPENDOR: PRIORITY Position */
+#define STL_STLNVICPENDOR_PRIORITY_Msk     (0xFFUL << STL_STLNVICPENDOR_PRIORITY_Pos)  /*!< STL STLNVICPENDOR: PRIORITY Mask */
+
+#define STL_STLNVICPENDOR_INTNUM_Pos        0U                                         /*!< STL STLNVICPENDOR: INTNUM Position */
+#define STL_STLNVICPENDOR_INTNUM_Msk       (0x1FFUL /*<< STL_STLNVICPENDOR_INTNUM_Pos*/) /*!< STL STLNVICPENDOR: INTNUM Mask */
+
+/* STL Software Test Library Observation Register (STLNVICACTVOR) Definitions */
+#define STL_STLNVICACTVOR_VALID_Pos        18U                                         /*!< STL STLNVICACTVOR: VALID Position */
+#define STL_STLNVICACTVOR_VALID_Msk        (0x1UL << STL_STLNVICACTVOR_VALID_Pos)      /*!< STL STLNVICACTVOR: VALID Mask */
+
+#define STL_STLNVICACTVOR_TARGET_Pos       17U                                         /*!< STL STLNVICACTVOR: TARGET Position */
+#define STL_STLNVICACTVOR_TARGET_Msk       (0x1UL << STL_STLNVICACTVOR_TARGET_Pos)     /*!< STL STLNVICACTVOR: TARGET Mask */
+
+#define STL_STLNVICACTVOR_PRIORITY_Pos      9U                                         /*!< STL STLNVICACTVOR: PRIORITY Position */
+#define STL_STLNVICACTVOR_PRIORITY_Msk     (0xFFUL << STL_STLNVICACTVOR_PRIORITY_Pos)  /*!< STL STLNVICACTVOR: PRIORITY Mask */
+
+#define STL_STLNVICACTVOR_INTNUM_Pos        0U                                         /*!< STL STLNVICACTVOR: INTNUM Position */
+#define STL_STLNVICACTVOR_INTNUM_Msk       (0x1FFUL /*<< STL_STLNVICACTVOR_INTNUM_Pos*/) /*!< STL STLNVICACTVOR: INTNUM Mask */
+
+/* STL Software Test Library Observation Register (STLIDMPUSR) Definitions */
+#define STL_STLIDMPUSR_ADDR_Pos             5U                                         /*!< STL STLIDMPUSR: ADDR Position */
+#define STL_STLIDMPUSR_ADDR_Msk            (0x7FFFFFFUL << STL_STLIDMPUSR_ADDR_Pos)    /*!< STL STLIDMPUSR: ADDR Mask */
+
+#define STL_STLIDMPUSR_INSTR_Pos            2U                                         /*!< STL STLIDMPUSR: INSTR Position */
+#define STL_STLIDMPUSR_INSTR_Msk           (0x1UL << STL_STLIDMPUSR_INSTR_Pos)         /*!< STL STLIDMPUSR: INSTR Mask */
+
+#define STL_STLIDMPUSR_DATA_Pos             1U                                         /*!< STL STLIDMPUSR: DATA Position */
+#define STL_STLIDMPUSR_DATA_Msk            (0x1UL << STL_STLIDMPUSR_DATA_Pos)          /*!< STL STLIDMPUSR: DATA Mask */
+
+/* STL Software Test Library Observation Register (STLIMPUOR) Definitions */
+#define STL_STLIMPUOR_HITREGION_Pos         9U                                         /*!< STL STLIMPUOR: HITREGION Position */
+#define STL_STLIMPUOR_HITREGION_Msk        (0xFFUL << STL_STLIMPUOR_HITREGION_Pos)     /*!< STL STLIMPUOR: HITREGION Mask */
+
+#define STL_STLIMPUOR_ATTR_Pos              0U                                         /*!< STL STLIMPUOR: ATTR Position */
+#define STL_STLIMPUOR_ATTR_Msk             (0x1FFUL /*<< STL_STLIMPUOR_ATTR_Pos*/)     /*!< STL STLIMPUOR: ATTR Mask */
+
+/* STL Software Test Library Observation Register (STLD0MPUOR) Definitions */
+#define STL_STLD0MPUOR_HITREGION_Pos        9U                                         /*!< STL STLD0MPUOR: HITREGION Position */
+#define STL_STLD0MPUOR_HITREGION_Msk       (0xFFUL << STL_STLD0MPUOR_HITREGION_Pos)    /*!< STL STLD0MPUOR: HITREGION Mask */
+
+#define STL_STLD0MPUOR_ATTR_Pos             0U                                         /*!< STL STLD0MPUOR: ATTR Position */
+#define STL_STLD0MPUOR_ATTR_Msk            (0x1FFUL /*<< STL_STLD0MPUOR_ATTR_Pos*/)    /*!< STL STLD0MPUOR: ATTR Mask */
+
+/* STL Software Test Library Observation Register (STLD1MPUOR) Definitions */
+#define STL_STLD1MPUOR_HITREGION_Pos        9U                                         /*!< STL STLD1MPUOR: HITREGION Position */
+#define STL_STLD1MPUOR_HITREGION_Msk       (0xFFUL << STL_STLD1MPUOR_HITREGION_Pos)    /*!< STL STLD1MPUOR: HITREGION Mask */
+
+#define STL_STLD1MPUOR_ATTR_Pos             0U                                         /*!< STL STLD1MPUOR: ATTR Position */
+#define STL_STLD1MPUOR_ATTR_Msk            (0x1FFUL /*<< STL_STLD1MPUOR_ATTR_Pos*/)    /*!< STL STLD1MPUOR: ATTR Mask */
+
+/*@}*/ /* end of group STL_Type */
 
 
 /**
@@ -1524,15 +1988,14 @@ typedef struct
         uint32_t RESERVED11[108];
   __IOM uint32_t AUTHSTATUS;                        /*!< Offset: 0xFB8 (R/W)  PMU Authentication Status Register */
   __IOM uint32_t DEVARCH;                           /*!< Offset: 0xFBC (R/W)  PMU Device Architecture Register */
-        uint32_t RESERVED12[4];
+        uint32_t RESERVED12[3];
   __IOM uint32_t DEVTYPE;                           /*!< Offset: 0xFCC (R/W)  PMU Device Type Register */
   __IOM uint32_t PIDR4;                             /*!< Offset: 0xFD0 (R/W)  PMU Peripheral Identification Register 4 */
         uint32_t RESERVED13[3];
   __IOM uint32_t PIDR0;                             /*!< Offset: 0xFE0 (R/W)  PMU Peripheral Identification Register 0 */
-  __IOM uint32_t PIDR1;                             /*!< Offset: 0xFE0 (R/W)  PMU Peripheral Identification Register 1 */
-  __IOM uint32_t PIDR2;                             /*!< Offset: 0xFE0 (R/W)  PMU Peripheral Identification Register 2 */
-  __IOM uint32_t PIDR3;                             /*!< Offset: 0xFE0 (R/W)  PMU Peripheral Identification Register 3 */
-        uint32_t RESERVED14[3];
+  __IOM uint32_t PIDR1;                             /*!< Offset: 0xFE4 (R/W)  PMU Peripheral Identification Register 1 */
+  __IOM uint32_t PIDR2;                             /*!< Offset: 0xFE8 (R/W)  PMU Peripheral Identification Register 2 */
+  __IOM uint32_t PIDR3;                             /*!< Offset: 0xFEC (R/W)  PMU Peripheral Identification Register 3 */
   __IOM uint32_t CIDR0;                             /*!< Offset: 0xFF0 (R/W)  PMU Component Identification Register 0 */
   __IOM uint32_t CIDR1;                             /*!< Offset: 0xFF4 (R/W)  PMU Component Identification Register 1 */
   __IOM uint32_t CIDR2;                             /*!< Offset: 0xFF8 (R/W)  PMU Component Identification Register 2 */
@@ -3127,7 +3590,12 @@ typedef struct
   #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
   #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
   #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define MEMSYSCTL_BASE      (0xE001E000UL)                             /*!< Memory System Control Base Address */
+  #define ERRBNK_BASE         (0xE001E100UL)                             /*!< Error Banking Base Address */
   #define PWRMODCTL_BASE      (0xE001E300UL)                             /*!< Power Mode Control Base Address */
+  #define EWIC_BASE           (0xE001E400UL)                             /*!< External Wakeup Interrupt Controller Base Address */
+  #define PRCCFGINF_BASE      (0xE001E700UL)                             /*!< Processor Configuration Information Base Address */
+  #define STL_BASE            (0xE001E800UL)                             /*!< Software Test Library Base Address */
   #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
   #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< \deprecated Core Debug Base Address */
   #define DCB_BASE            (0xE000EDF0UL)                             /*!< DCB Base Address */
@@ -3136,14 +3604,19 @@ typedef struct
   #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
   #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
 
-  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
+  #define ICB                 ((ICB_Type       *)     SCS_BASE         ) /*!< System control Register not in SCB */
   #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
   #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
   #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
   #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
   #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
   #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define MEMSYSCTL           ((MemSysCtl_Type *)     MEMSYSCTL_BASE   ) /*!< Memory System Control configuration struct */
+  #define ERRBNK              ((ErrBnk_Type    *)     ERRBNK_BASE      ) /*!< Error Banking configuration struct */
   #define PWRMODCTL           ((PwrModCtl_Type *)     PWRMODCTL_BASE   ) /*!< Power Mode Control configuration struct */
+  #define EWIC                ((EWIC_Type      *)     EWIC_BASE        ) /*!< EWIC configuration struct */
+  #define PRCCFGINF           ((PrcCfgInf_Type *)     PRCCFGINF_BASE   ) /*!< Processor Configuration Information configuration struct */
+  #define STL                 ((STL_Type       *)     STL_BASE         ) /*!< Software Test Library configuration struct */
   #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< \deprecated Core Debug configuration struct */
   #define DCB                 ((DCB_Type       *)     DCB_BASE         ) /*!< DCB configuration struct */
   #define DIB                 ((DIB_Type       *)     DIB_BASE         ) /*!< DIB configuration struct */
@@ -3175,7 +3648,7 @@ typedef struct
   #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
   #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
 
-  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
+  #define ICB_NS              ((ICB_Type       *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
   #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
   #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
   #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
@@ -3195,6 +3668,69 @@ typedef struct
 /*@} */
 
 
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_register_aliases     Backwards Compatibility Aliases
+  \brief      Register alias definitions for backwards compatibility.
+  @{
+ */
+#define ID_ADR  (ID_AFR)    /*!< SCB Auxiliary Feature Register */
+
+/* 'SCnSCB' is deprecated and replaced by 'ICB' */
+typedef ICB_Type SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISCRITAXIRUW_Pos   (ICB_ACTLR_DISCRITAXIRUW_Pos)
+#define SCnSCB_ACTLR_DISCRITAXIRUW_Msk   (ICB_ACTLR_DISCRITAXIRUW_Msk)
+
+#define SCnSCB_ACTLR_DISDI_Pos           (ICB_ACTLR_DISDI_Pos)
+#define SCnSCB_ACTLR_DISDI_Msk           (ICB_ACTLR_DISDI_Msk)
+
+#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos   (ICB_ACTLR_DISCRITAXIRUR_Pos)
+#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk   (ICB_ACTLR_DISCRITAXIRUR_Msk)
+
+#define SCnSCB_ACTLR_EVENTBUSEN_Pos      (ICB_ACTLR_EVENTBUSEN_Pos)
+#define SCnSCB_ACTLR_EVENTBUSEN_Msk      (ICB_ACTLR_EVENTBUSEN_Msk)
+
+#define SCnSCB_ACTLR_EVENTBUSEN_S_Pos    (ICB_ACTLR_EVENTBUSEN_S_Pos)
+#define SCnSCB_ACTLR_EVENTBUSEN_S_Msk    (ICB_ACTLR_EVENTBUSEN_S_Msk)
+
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos  (ICB_ACTLR_DISITMATBFLUSH_Pos)
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk  (ICB_ACTLR_DISITMATBFLUSH_Msk)
+
+#define SCnSCB_ACTLR_DISNWAMODE_Pos      (ICB_ACTLR_DISNWAMODE_Pos)
+#define SCnSCB_ACTLR_DISNWAMODE_Msk      (ICB_ACTLR_DISNWAMODE_Msk)
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos       (ICB_ACTLR_FPEXCODIS_Pos)
+#define SCnSCB_ACTLR_FPEXCODIS_Msk       (ICB_ACTLR_FPEXCODIS_Msk)
+
+#define SCnSCB_ACTLR_DISOLAP_Pos         (ICB_ACTLR_DISOLAP_Pos)
+#define SCnSCB_ACTLR_DISOLAP_Msk         (ICB_ACTLR_DISOLAP_Msk)
+
+#define SCnSCB_ACTLR_DISOLAPS_Pos        (ICB_ACTLR_DISOLAPS_Pos)
+#define SCnSCB_ACTLR_DISOLAPS_Msk        (ICB_ACTLR_DISOLAPS_Msk)
+
+#define SCnSCB_ACTLR_DISLOBR_Pos         (ICB_ACTLR_DISLOBR_Pos)
+#define SCnSCB_ACTLR_DISLOBR_Msk         (ICB_ACTLR_DISLOBR_Msk)
+
+#define SCnSCB_ACTLR_DISLO_Pos           (ICB_ACTLR_DISLO_Pos)
+#define SCnSCB_ACTLR_DISLO_Msk           (ICB_ACTLR_DISLO_Msk)
+
+#define SCnSCB_ACTLR_DISLOLEP_Pos        (ICB_ACTLR_DISLOLEP_Pos)
+#define SCnSCB_ACTLR_DISLOLEP_Msk        (ICB_ACTLR_DISLOLEP_Msk)
+
+#define SCnSCB_ACTLR_DISFOLD_Pos         (ICB_ACTLR_DISFOLD_Pos)
+#define SCnSCB_ACTLR_DISFOLD_Msk         (ICB_ACTLR_DISFOLD_Msk)
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos      (ICB_ICTR_INTLINESNUM_Pos)
+#define SCnSCB_ICTR_INTLINESNUM_Msk      (ICB_ICTR_INTLINESNUM_Msk)
+
+#define SCnSCB                           (ICB)
+#define SCnSCB_NS                        (ICB_NS)
+
+/*@} */
+
 
 /*******************************************************************************
  *                Hardware Abstraction Layer
@@ -3888,6 +4424,9 @@ __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
 #define ARMCM55_PMU_NWAMODE_ENTER                    0xC200             /*!< No write-allocate mode entry */
 #define ARMCM55_PMU_NWAMODE                          0xC201             /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */
 #define ARMCM55_PMU_SAHB_ACCESS                      0xC300             /*!< Read or write access on the S-AHB interface to the TCM */
+#define ARMCM55_PMU_PAHB_ACCESS                      0xC301             /*!< Read or write access to the P-AHB write interface */
+#define ARMCM55_PMU_AXI_WRITE_ACCESS                 0xC302             /*!< Any beat access to M-AXI write interface */
+#define ARMCM55_PMU_AXI_READ_ACCESS                  0xC303             /*!< Any beat access to M-AXI read interface */
 #define ARMCM55_PMU_DOSTIMEOUT_DOUBLE                0xC400             /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */
 #define ARMCM55_PMU_DOSTIMEOUT_TRIPLE                0xC401             /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */
 

CMSIS/Core/Include/core_cm85.h

@@ -0,0 +1,4672 @@
+/**************************************************************************//**
+ * @file     core_cm85.h
+ * @brief    CMSIS Cortex-M85 Core Peripheral Access Layer Header File
+ * @version  V1.0.4
+ * @date     21. April 2022
+ ******************************************************************************/
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include                        /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header                   /* treat file as system include file */
+#elif defined ( __GNUC__ )
+  #pragma GCC diagnostic ignored "-Wpedantic"   /* disable pedantic warning due to unnamed structs/unions */
+#endif
+
+#ifndef __CORE_CM85_H_GENERIC
+#define __CORE_CM85_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M85
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS CM85 definitions */
+
+#define __CORTEX_M                      (85U)                                 /*!< Cortex-M Core */
+
+#if defined ( __CC_ARM )
+  #error Legacy Arm Compiler does not support Armv8.1-M target architecture.
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_FP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED       0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM85_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM85_H_DEPENDANT
+#define __CORE_CM85_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM85_REV
+    #define __CM85_REV               0x0001U
+    #warning "__CM85_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #if __FPU_PRESENT != 0U
+    #ifndef __FPU_DP
+      #define __FPU_DP             0U
+      #warning "__FPU_DP not defined in device header file; using default!"
+    #endif
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ICACHE_PRESENT
+    #define __ICACHE_PRESENT          0U
+    #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DCACHE_PRESENT
+    #define __DCACHE_PRESENT          0U
+    #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT             1U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __PMU_PRESENT
+    #define __PMU_PRESENT             0U
+    #warning "__PMU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #if __PMU_PRESENT != 0U
+    #ifndef __PMU_NUM_EVENTCNT
+      #define __PMU_NUM_EVENTCNT      8U
+      #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!"
+    #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2)
+    #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */
+    #endif
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DSP_PRESENT
+    #define __DSP_PRESENT             0U
+    #warning "__DSP_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M85 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core EWIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core PMU Register
+  - Core MPU Register
+  - Core SAU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:1;               /*!< bit:     20  Reserved */
+    uint32_t B:1;                        /*!< bit:     21  BTI active       (read 0) */
+    uint32_t _reserved2:2;               /*!< bit: 22..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_B_Pos                         21U                                            /*!< xPSR: B Position */
+#define xPSR_B_Msk                         (1UL << xPSR_B_Pos)                            /*!< xPSR: B Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */
+    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */
+    uint32_t BTI_EN:1;                   /*!< bit:      4  Privileged branch target identification enable */
+    uint32_t UBTI_EN:1;                  /*!< bit:      5  Unprivileged branch target identification enable */
+    uint32_t PAC_EN:1;                   /*!< bit:      6  Privileged pointer authentication enable */
+    uint32_t UPAC_EN:1;                  /*!< bit:      7  Unprivileged pointer authentication enable */
+    uint32_t _reserved1:24;              /*!< bit:  8..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_UPAC_EN_Pos                 7U                                            /*!< CONTROL: UPAC_EN Position */
+#define CONTROL_UPAC_EN_Msk                (1UL << CONTROL_UPAC_EN_Pos)                   /*!< CONTROL: UPAC_EN Mask */
+
+#define CONTROL_PAC_EN_Pos                  6U                                            /*!< CONTROL: PAC_EN Position */
+#define CONTROL_PAC_EN_Msk                 (1UL << CONTROL_PAC_EN_Pos)                    /*!< CONTROL: PAC_EN Mask */
+
+#define CONTROL_UBTI_EN_Pos                 5U                                            /*!< CONTROL: UBTI_EN Position */
+#define CONTROL_UBTI_EN_Msk                (1UL << CONTROL_UBTI_EN_Pos)                   /*!< CONTROL: UBTI_EN Mask */
+
+#define CONTROL_BTI_EN_Pos                  4U                                            /*!< CONTROL: BTI_EN Position */
+#define CONTROL_BTI_EN_Msk                 (1UL << CONTROL_BTI_EN_Pos)                    /*!< CONTROL: BTI_EN Mask */
+
+#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED6[580U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
+        uint32_t RESERVED7[21U];
+  __IOM uint32_t SFSR;                   /*!< Offset: 0x0E4 (R/W)  Secure Fault Status Register */
+  __IOM uint32_t SFAR;                   /*!< Offset: 0x0E8 (R/W)  Secure Fault Address Register */
+        uint32_t RESERVED3[69U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+  __IOM uint32_t RFSR;                   /*!< Offset: 0x204 (R/W)  RAS Fault Status Register */
+        uint32_t RESERVED4[14U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+  __OM  uint32_t BPIALL;                 /*!< Offset: 0x278 ( /W)  Branch Predictor Invalidate All */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_IESB_Pos                  5U                                            /*!< SCB AIRCR: Implicit ESB Enable Position */
+#define SCB_AIRCR_IESB_Msk                 (1UL << SCB_AIRCR_IESB_Pos)                    /*!< SCB AIRCR: Implicit ESB Enable Mask */
+
+#define SCB_AIRCR_DIT_Pos                   4U                                            /*!< SCB AIRCR: Data Independent Timing Position */
+#define SCB_AIRCR_DIT_Msk                  (1UL << SCB_AIRCR_DIT_Pos)                     /*!< SCB AIRCR: Data Independent Timing Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_TRD_Pos                    20U                                            /*!< SCB CCR: TRD Position */
+#define SCB_CCR_TRD_Msk                    (1UL << SCB_CCR_TRD_Pos)                       /*!< SCB CCR: TRD Mask */
+
+#define SCB_CCR_LOB_Pos                    19U                                            /*!< SCB CCR: LOB Position */
+#define SCB_CCR_LOB_Msk                    (1UL << SCB_CCR_LOB_Pos)                       /*!< SCB CCR: LOB Mask */
+
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_CFSR_MEMFAULTSR_Pos + 7U)                 /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_CFSR_MEMFAULTSR_Pos + 5U)                 /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_CFSR_MEMFAULTSR_Pos + 4U)                 /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_CFSR_MEMFAULTSR_Pos + 3U)                 /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_CFSR_MEMFAULTSR_Pos + 1U)                 /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_CFSR_MEMFAULTSR_Pos + 0U)                 /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_PMU_Pos                    5U                                            /*!< SCB DFSR: PMU Position */
+#define SCB_DFSR_PMU_Msk                   (1UL << SCB_DFSR_PMU_Pos)                      /*!< SCB DFSR: PMU Mask */
+
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CP7_Pos                   7U                                            /*!< SCB NSACR: CP7 Position */
+#define SCB_NSACR_CP7_Msk                  (1UL << SCB_NSACR_CP7_Pos)                     /*!< SCB NSACR: CP7 Mask */
+
+#define SCB_NSACR_CP6_Pos                   6U                                            /*!< SCB NSACR: CP6 Position */
+#define SCB_NSACR_CP6_Msk                  (1UL << SCB_NSACR_CP6_Pos)                     /*!< SCB NSACR: CP6 Mask */
+
+#define SCB_NSACR_CP5_Pos                   5U                                            /*!< SCB NSACR: CP5 Position */
+#define SCB_NSACR_CP5_Msk                  (1UL << SCB_NSACR_CP5_Pos)                     /*!< SCB NSACR: CP5 Mask */
+
+#define SCB_NSACR_CP4_Pos                   4U                                            /*!< SCB NSACR: CP4 Position */
+#define SCB_NSACR_CP4_Msk                  (1UL << SCB_NSACR_CP4_Pos)                     /*!< SCB NSACR: CP4 Mask */
+
+#define SCB_NSACR_CP3_Pos                   3U                                            /*!< SCB NSACR: CP3 Position */
+#define SCB_NSACR_CP3_Msk                  (1UL << SCB_NSACR_CP3_Pos)                     /*!< SCB NSACR: CP3 Mask */
+
+#define SCB_NSACR_CP2_Pos                   2U                                            /*!< SCB NSACR: CP2 Position */
+#define SCB_NSACR_CP2_Msk                  (1UL << SCB_NSACR_CP2_Pos)                     /*!< SCB NSACR: CP2 Mask */
+
+#define SCB_NSACR_CP1_Pos                   1U                                            /*!< SCB NSACR: CP1 Position */
+#define SCB_NSACR_CP1_Msk                  (1UL << SCB_NSACR_CP1_Pos)                     /*!< SCB NSACR: CP1 Mask */
+
+#define SCB_NSACR_CP0_Pos                   0U                                            /*!< SCB NSACR: CP0 Position */
+#define SCB_NSACR_CP0_Msk                  (1UL /*<< SCB_NSACR_CP0_Pos*/)                 /*!< SCB NSACR: CP0 Mask */
+
+/* SCB Debug Feature Register 0 Definitions */
+#define SCB_ID_DFR_UDE_Pos                 28U                                            /*!< SCB ID_DFR: UDE Position */
+#define SCB_ID_DFR_UDE_Msk                 (0xFUL << SCB_ID_DFR_UDE_Pos)                  /*!< SCB ID_DFR: UDE Mask */
+
+#define SCB_ID_DFR_MProfDbg_Pos            20U                                            /*!< SCB ID_DFR: MProfDbg Position */
+#define SCB_ID_DFR_MProfDbg_Msk            (0xFUL << SCB_ID_DFR_MProfDbg_Pos)             /*!< SCB ID_DFR: MProfDbg Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB RAS Fault Status Register Definitions */
+#define SCB_RFSR_V_Pos                     31U                                            /*!< SCB RFSR: V Position */
+#define SCB_RFSR_V_Msk                     (1UL << SCB_RFSR_V_Pos)                        /*!< SCB RFSR: V Mask */
+
+#define SCB_RFSR_IS_Pos                    16U                                            /*!< SCB RFSR: IS Position */
+#define SCB_RFSR_IS_Msk                    (0x7FFFUL << SCB_RFSR_IS_Pos)                  /*!< SCB RFSR: IS Mask */
+
+#define SCB_RFSR_UET_Pos                    0U                                            /*!< SCB RFSR: UET Position */
+#define SCB_RFSR_UET_Msk                   (3UL /*<< SCB_RFSR_UET_Pos*/)                  /*!< SCB RFSR: UET Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ICB Implementation Control Block register (ICB)
+  \brief    Type definitions for the Implementation Control Block Register
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Implementation Control Block (ICB).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
+} ICB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define ICB_ACTLR_DISCRITAXIRUW_Pos     27U                                               /*!< ACTLR: DISCRITAXIRUW Position */
+#define ICB_ACTLR_DISCRITAXIRUW_Msk     (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos)              /*!< ACTLR: DISCRITAXIRUW Mask */
+
+#define ICB_ACTLR_DISCRITAXIRUR_Pos     15U                                               /*!< ACTLR: DISCRITAXIRUR Position */
+#define ICB_ACTLR_DISCRITAXIRUR_Msk     (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos)              /*!< ACTLR: DISCRITAXIRUR Mask */
+
+#define ICB_ACTLR_EVENTBUSEN_Pos        14U                                               /*!< ACTLR: EVENTBUSEN Position */
+#define ICB_ACTLR_EVENTBUSEN_Msk        (1UL << ICB_ACTLR_EVENTBUSEN_Pos)                 /*!< ACTLR: EVENTBUSEN Mask */
+
+#define ICB_ACTLR_EVENTBUSEN_S_Pos      13U                                               /*!< ACTLR: EVENTBUSEN_S Position */
+#define ICB_ACTLR_EVENTBUSEN_S_Msk      (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos)               /*!< ACTLR: EVENTBUSEN_S Mask */
+
+#define ICB_ACTLR_DISITMATBFLUSH_Pos    12U                                               /*!< ACTLR: DISITMATBFLUSH Position */
+#define ICB_ACTLR_DISITMATBFLUSH_Msk    (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos)             /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define ICB_ACTLR_DISNWAMODE_Pos        11U                                               /*!< ACTLR: DISNWAMODE Position */
+#define ICB_ACTLR_DISNWAMODE_Msk        (1UL << ICB_ACTLR_DISNWAMODE_Pos)                 /*!< ACTLR: DISNWAMODE Mask */
+
+#define ICB_ACTLR_FPEXCODIS_Pos         10U                                               /*!< ACTLR: FPEXCODIS Position */
+#define ICB_ACTLR_FPEXCODIS_Msk         (1UL << ICB_ACTLR_FPEXCODIS_Pos)                  /*!< ACTLR: FPEXCODIS Mask */
+
+/* Interrupt Controller Type Register Definitions */
+#define ICB_ICTR_INTLINESNUM_Pos         0U                                               /*!< ICTR: INTLINESNUM Position */
+#define ICB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/)           /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_ICB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[32U];
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
+        uint32_t RESERVED6[3U];
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  ITM Device Type Register */
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+        uint32_t RESERVED32[934U];
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+        uint32_t RESERVED33[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup MemSysCtl_Type     Memory System Control Registers (IMPLEMENTATION DEFINED)
+  \brief    Type definitions for the Memory System Control Registers (MEMSYSCTL)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory System Control Registers (MEMSYSCTL).
+ */
+typedef struct
+{
+  __IOM uint32_t MSCR;                   /*!< Offset: 0x000 (R/W)  Memory System Control Register */
+  __IOM uint32_t PFCR;                   /*!< Offset: 0x004 (R/W)  Prefetcher Control Register */
+        uint32_t RESERVED1[2U];
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x010 (R/W)  ITCM Control Register */
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x014 (R/W)  DTCM Control Register */
+  __IOM uint32_t PAHBCR;                 /*!< Offset: 0x018 (R/W)  P-AHB Control Register */
+        uint32_t RESERVED2[313U];
+  __IOM uint32_t ITGU_CTRL;              /*!< Offset: 0x500 (R/W)  ITGU Control Register */
+  __IOM uint32_t ITGU_CFG;               /*!< Offset: 0x504 (R/W)  ITGU Configuration Register */
+        uint32_t RESERVED3[2U];
+  __IOM uint32_t ITGU_LUT[16U];          /*!< Offset: 0x510 (R/W)  ITGU Look Up Table Register */
+        uint32_t RESERVED4[44U];
+  __IOM uint32_t DTGU_CTRL;              /*!< Offset: 0x600 (R/W)  DTGU Control Registers */
+  __IOM uint32_t DTGU_CFG;               /*!< Offset: 0x604 (R/W)  DTGU Configuration Register */
+        uint32_t RESERVED5[2U];
+  __IOM uint32_t DTGU_LUT[16U];          /*!< Offset: 0x610 (R/W)  DTGU Look Up Table Register */
+} MemSysCtl_Type;
+
+/* MEMSYSCTL Memory System Control Register (MSCR) Register Definitions */
+#define MEMSYSCTL_MSCR_CPWRDN_Pos          17U                                         /*!< MEMSYSCTL MSCR: CPWRDN Position */
+#define MEMSYSCTL_MSCR_CPWRDN_Msk          (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos)        /*!< MEMSYSCTL MSCR: CPWRDN Mask */
+
+#define MEMSYSCTL_MSCR_DCCLEAN_Pos         16U                                         /*!< MEMSYSCTL MSCR: DCCLEAN Position */
+#define MEMSYSCTL_MSCR_DCCLEAN_Msk         (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos)       /*!< MEMSYSCTL MSCR: DCCLEAN Mask */
+
+#define MEMSYSCTL_MSCR_ICACTIVE_Pos        13U                                         /*!< MEMSYSCTL MSCR: ICACTIVE Position */
+#define MEMSYSCTL_MSCR_ICACTIVE_Msk        (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos)      /*!< MEMSYSCTL MSCR: ICACTIVE Mask */
+
+#define MEMSYSCTL_MSCR_DCACTIVE_Pos        12U                                         /*!< MEMSYSCTL MSCR: DCACTIVE Position */
+#define MEMSYSCTL_MSCR_DCACTIVE_Msk        (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos)      /*!< MEMSYSCTL MSCR: DCACTIVE Mask */
+
+#define MEMSYSCTL_MSCR_EVECCFAULT_Pos       3U                                         /*!< MEMSYSCTL MSCR: EVECCFAULT Position */
+#define MEMSYSCTL_MSCR_EVECCFAULT_Msk      (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos)    /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */
+
+#define MEMSYSCTL_MSCR_FORCEWT_Pos          2U                                         /*!< MEMSYSCTL MSCR: FORCEWT Position */
+#define MEMSYSCTL_MSCR_FORCEWT_Msk         (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos)       /*!< MEMSYSCTL MSCR: FORCEWT Mask */
+
+#define MEMSYSCTL_MSCR_ECCEN_Pos            1U                                         /*!< MEMSYSCTL MSCR: ECCEN Position */
+#define MEMSYSCTL_MSCR_ECCEN_Msk           (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos)         /*!< MEMSYSCTL MSCR: ECCEN Mask */
+
+/* MEMSYSCTL Prefetcher Control Register (PFCR) Register Definitions */
+#define MEMSYSCTL_PFCR_DIS_NLP_Pos          7U                                         /*!< MEMSYSCTL PFCR: DIS_NLP Position */
+#define MEMSYSCTL_PFCR_DIS_NLP_Msk         (0x1UL << MEMSYSCTL_PFCR_DIS_NLP_Pos)       /*!< MEMSYSCTL PFCR: DIS_NLP Mask */
+
+#define MEMSYSCTL_PFCR_ENABLE_Pos           0U                                         /*!< MEMSYSCTL PFCR: ENABLE Position */
+#define MEMSYSCTL_PFCR_ENABLE_Msk          (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/)    /*!< MEMSYSCTL PFCR: ENABLE Mask */
+
+/* MEMSYSCTL ITCM Control Register (ITCMCR) Register Definitions */
+#define MEMSYSCTL_ITCMCR_SZ_Pos             3U                                         /*!< MEMSYSCTL ITCMCR: SZ Position */
+#define MEMSYSCTL_ITCMCR_SZ_Msk            (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos)          /*!< MEMSYSCTL ITCMCR: SZ Mask */
+
+#define MEMSYSCTL_ITCMCR_EN_Pos             0U                                         /*!< MEMSYSCTL ITCMCR: EN Position */
+#define MEMSYSCTL_ITCMCR_EN_Msk            (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/)      /*!< MEMSYSCTL ITCMCR: EN Mask */
+
+/* MEMSYSCTL DTCM Control Register (DTCMCR) Register Definitions */
+#define MEMSYSCTL_DTCMCR_SZ_Pos             3U                                         /*!< MEMSYSCTL DTCMCR: SZ Position */
+#define MEMSYSCTL_DTCMCR_SZ_Msk            (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos)          /*!< MEMSYSCTL DTCMCR: SZ Mask */
+
+#define MEMSYSCTL_DTCMCR_EN_Pos             0U                                         /*!< MEMSYSCTL DTCMCR: EN Position */
+#define MEMSYSCTL_DTCMCR_EN_Msk            (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/)      /*!< MEMSYSCTL DTCMCR: EN Mask */
+
+/* MEMSYSCTL P-AHB Control Register (PAHBCR) Register Definitions */
+#define MEMSYSCTL_PAHBCR_SZ_Pos             1U                                         /*!< MEMSYSCTL PAHBCR: SZ Position */
+#define MEMSYSCTL_PAHBCR_SZ_Msk            (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos)          /*!< MEMSYSCTL PAHBCR: SZ Mask */
+
+#define MEMSYSCTL_PAHBCR_EN_Pos             0U                                         /*!< MEMSYSCTL PAHBCR: EN Position */
+#define MEMSYSCTL_PAHBCR_EN_Msk            (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/)      /*!< MEMSYSCTL PAHBCR: EN Mask */
+
+/* MEMSYSCTL ITGU Control Register (ITGU_CTRL) Register Definitions */
+#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos       1U                                         /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */
+#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk      (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos)    /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */
+
+#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos       0U                                         /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */
+#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk      (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */
+
+/* MEMSYSCTL ITGU Configuration Register (ITGU_CFG) Register Definitions */
+#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos     31U                                         /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */
+#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk     (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos)   /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */
+
+#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos      8U                                         /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */
+#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk     (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos)   /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */
+
+#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos        0U                                         /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */
+#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk       (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */
+
+/* MEMSYSCTL DTGU Control Registers (DTGU_CTRL) Register Definitions */
+#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos       1U                                         /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */
+#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk      (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos)    /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */
+
+#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos       0U                                         /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */
+#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk      (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */
+
+/* MEMSYSCTL DTGU Configuration Register (DTGU_CFG) Register Definitions */
+#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos     31U                                         /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */
+#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk     (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos)   /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */
+
+#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos      8U                                         /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */
+#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk     (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos)   /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */
+
+#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos        0U                                         /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */
+#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk       (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */
+
+
+/*@}*/ /* end of group MemSysCtl_Type */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup PwrModCtl_Type     Power Mode Control Registers
+  \brief    Type definitions for the Power Mode Control Registers (PWRMODCTL)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Power Mode Control Registers (PWRMODCTL).
+ */
+typedef struct
+{
+  __IOM uint32_t CPDLPSTATE;             /*!< Offset: 0x000 (R/W)  Core Power Domain Low Power State Register */
+  __IOM uint32_t DPDLPSTATE;             /*!< Offset: 0x004 (R/W)  Debug Power Domain Low Power State Register */
+} PwrModCtl_Type;
+
+/* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */
+#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos   8U                                              /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */
+#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk  (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos)     /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */
+
+#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos   4U                                              /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */
+#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk  (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos)     /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */
+
+#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos   0U                                              /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */
+#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk  (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */
+
+/* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */
+#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos   0U                                              /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */
+#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk  (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */
+
+/*@}*/ /* end of group PwrModCtl_Type */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup EWIC_Type     External Wakeup Interrupt Controller Registers
+  \brief    Type definitions for the External Wakeup Interrupt Controller Registers (EWIC)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the External Wakeup Interrupt Controller Registers (EWIC).
+ */
+typedef struct
+{
+  __OM  uint32_t EVENTSPR;               /*!< Offset: 0x000 ( /W)  Event Set Pending Register */
+        uint32_t RESERVED0[31U];
+  __IM  uint32_t EVENTMASKA;             /*!< Offset: 0x080 (R/W)  Event Mask A Register */
+  __IM  uint32_t EVENTMASK[15];          /*!< Offset: 0x084 (R/W)  Event Mask Register */
+} EWIC_Type;
+
+/* EWIC External Wakeup Interrupt Controller (EVENTSPR) Register Definitions */
+#define EWIC_EVENTSPR_EDBGREQ_Pos   2U                                                 /*!< EWIC EVENTSPR: EDBGREQ Position */
+#define EWIC_EVENTSPR_EDBGREQ_Msk  (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos)                /*!< EWIC EVENTSPR: EDBGREQ Mask */
+
+#define EWIC_EVENTSPR_NMI_Pos   1U                                                     /*!< EWIC EVENTSPR: NMI Position */
+#define EWIC_EVENTSPR_NMI_Msk  (0x1UL << EWIC_EVENTSPR_NMI_Pos)                        /*!< EWIC EVENTSPR: NMI Mask */
+
+#define EWIC_EVENTSPR_EVENT_Pos   0U                                                   /*!< EWIC EVENTSPR: EVENT Position */
+#define EWIC_EVENTSPR_EVENT_Msk  (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/)                /*!< EWIC EVENTSPR: EVENT Mask */
+
+/* EWIC External Wakeup Interrupt Controller (EVENTMASKA) Register Definitions */
+#define EWIC_EVENTMASKA_EDBGREQ_Pos   2U                                               /*!< EWIC EVENTMASKA: EDBGREQ Position */
+#define EWIC_EVENTMASKA_EDBGREQ_Msk  (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos)            /*!< EWIC EVENTMASKA: EDBGREQ Mask */
+
+#define EWIC_EVENTMASKA_NMI_Pos   1U                                                   /*!< EWIC EVENTMASKA: NMI Position */
+#define EWIC_EVENTMASKA_NMI_Msk  (0x1UL << EWIC_EVENTMASKA_NMI_Pos)                    /*!< EWIC EVENTMASKA: NMI Mask */
+
+#define EWIC_EVENTMASKA_EVENT_Pos   0U                                                 /*!< EWIC EVENTMASKA: EVENT Position */
+#define EWIC_EVENTMASKA_EVENT_Msk  (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/)            /*!< EWIC EVENTMASKA: EVENT Mask */
+
+/* EWIC External Wakeup Interrupt Controller (EVENTMASK) Register Definitions */
+#define EWIC_EVENTMASK_IRQ_Pos   0U                                                    /*!< EWIC EVENTMASKA: IRQ Position */
+#define EWIC_EVENTMASK_IRQ_Msk  (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/)          /*!< EWIC EVENTMASKA: IRQ Mask */
+
+/*@}*/ /* end of group EWIC_Type */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup ErrBnk_Type     Error Banking Registers (IMPLEMENTATION DEFINED)
+  \brief    Type definitions for the Error Banking Registers (ERRBNK)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Error Banking Registers (ERRBNK).
+ */
+typedef struct
+{
+  __IOM uint32_t IEBR0;                  /*!< Offset: 0x000 (R/W)  Instruction Cache Error Bank Register 0 */
+  __IOM uint32_t IEBR1;                  /*!< Offset: 0x004 (R/W)  Instruction Cache Error Bank Register 1 */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t DEBR0;                  /*!< Offset: 0x010 (R/W)  Data Cache Error Bank Register 0 */
+  __IOM uint32_t DEBR1;                  /*!< Offset: 0x014 (R/W)  Data Cache Error Bank Register 1 */
+        uint32_t RESERVED1[2U];
+  __IOM uint32_t TEBR0;                  /*!< Offset: 0x020 (R/W)  TCM Error Bank Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t TEBR1;                  /*!< Offset: 0x028 (R/W)  TCM Error Bank Register 1 */
+} ErrBnk_Type;
+
+/* ERRBNK Instruction Cache Error Bank Register 0 (IEBR0) Register Definitions */
+#define ERRBNK_IEBR0_SWDEF_Pos             30U                                         /*!< ERRBNK IEBR0: SWDEF Position */
+#define ERRBNK_IEBR0_SWDEF_Msk             (0x3UL << ERRBNK_IEBR0_SWDEF_Pos)           /*!< ERRBNK IEBR0: SWDEF Mask */
+
+#define ERRBNK_IEBR0_BANK_Pos              16U                                         /*!< ERRBNK IEBR0: BANK Position */
+#define ERRBNK_IEBR0_BANK_Msk              (0x1UL << ERRBNK_IEBR0_BANK_Pos)            /*!< ERRBNK IEBR0: BANK Mask */
+
+#define ERRBNK_IEBR0_LOCATION_Pos           2U                                         /*!< ERRBNK IEBR0: LOCATION Position */
+#define ERRBNK_IEBR0_LOCATION_Msk          (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos)     /*!< ERRBNK IEBR0: LOCATION Mask */
+
+#define ERRBNK_IEBR0_LOCKED_Pos             1U                                         /*!< ERRBNK IEBR0: LOCKED Position */
+#define ERRBNK_IEBR0_LOCKED_Msk            (0x1UL << ERRBNK_IEBR0_LOCKED_Pos)          /*!< ERRBNK IEBR0: LOCKED Mask */
+
+#define ERRBNK_IEBR0_VALID_Pos              0U                                         /*!< ERRBNK IEBR0: VALID Position */
+#define ERRBNK_IEBR0_VALID_Msk             (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/)       /*!< ERRBNK IEBR0: VALID Mask */
+
+/* ERRBNK Instruction Cache Error Bank Register 1 (IEBR1) Register Definitions */
+#define ERRBNK_IEBR1_SWDEF_Pos             30U                                         /*!< ERRBNK IEBR1: SWDEF Position */
+#define ERRBNK_IEBR1_SWDEF_Msk             (0x3UL << ERRBNK_IEBR1_SWDEF_Pos)           /*!< ERRBNK IEBR1: SWDEF Mask */
+
+#define ERRBNK_IEBR1_BANK_Pos              16U                                         /*!< ERRBNK IEBR1: BANK Position */
+#define ERRBNK_IEBR1_BANK_Msk              (0x1UL << ERRBNK_IEBR1_BANK_Pos)            /*!< ERRBNK IEBR1: BANK Mask */
+
+#define ERRBNK_IEBR1_LOCATION_Pos           2U                                         /*!< ERRBNK IEBR1: LOCATION Position */
+#define ERRBNK_IEBR1_LOCATION_Msk          (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos)     /*!< ERRBNK IEBR1: LOCATION Mask */
+
+#define ERRBNK_IEBR1_LOCKED_Pos             1U                                         /*!< ERRBNK IEBR1: LOCKED Position */
+#define ERRBNK_IEBR1_LOCKED_Msk            (0x1UL << ERRBNK_IEBR1_LOCKED_Pos)          /*!< ERRBNK IEBR1: LOCKED Mask */
+
+#define ERRBNK_IEBR1_VALID_Pos              0U                                         /*!< ERRBNK IEBR1: VALID Position */
+#define ERRBNK_IEBR1_VALID_Msk             (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/)       /*!< ERRBNK IEBR1: VALID Mask */
+
+/* ERRBNK Data Cache Error Bank Register 0 (DEBR0) Register Definitions */
+#define ERRBNK_DEBR0_SWDEF_Pos             30U                                         /*!< ERRBNK DEBR0: SWDEF Position */
+#define ERRBNK_DEBR0_SWDEF_Msk             (0x3UL << ERRBNK_DEBR0_SWDEF_Pos)           /*!< ERRBNK DEBR0: SWDEF Mask */
+
+#define ERRBNK_DEBR0_TYPE_Pos              17U                                         /*!< ERRBNK DEBR0: TYPE Position */
+#define ERRBNK_DEBR0_TYPE_Msk              (0x1UL << ERRBNK_DEBR0_TYPE_Pos)            /*!< ERRBNK DEBR0: TYPE Mask */
+
+#define ERRBNK_DEBR0_BANK_Pos              16U                                         /*!< ERRBNK DEBR0: BANK Position */
+#define ERRBNK_DEBR0_BANK_Msk              (0x1UL << ERRBNK_DEBR0_BANK_Pos)            /*!< ERRBNK DEBR0: BANK Mask */
+
+#define ERRBNK_DEBR0_LOCATION_Pos           2U                                         /*!< ERRBNK DEBR0: LOCATION Position */
+#define ERRBNK_DEBR0_LOCATION_Msk          (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos)     /*!< ERRBNK DEBR0: LOCATION Mask */
+
+#define ERRBNK_DEBR0_LOCKED_Pos             1U                                         /*!< ERRBNK DEBR0: LOCKED Position */
+#define ERRBNK_DEBR0_LOCKED_Msk            (0x1UL << ERRBNK_DEBR0_LOCKED_Pos)          /*!< ERRBNK DEBR0: LOCKED Mask */
+
+#define ERRBNK_DEBR0_VALID_Pos              0U                                         /*!< ERRBNK DEBR0: VALID Position */
+#define ERRBNK_DEBR0_VALID_Msk             (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/)       /*!< ERRBNK DEBR0: VALID Mask */
+
+/* ERRBNK Data Cache Error Bank Register 1 (DEBR1) Register Definitions */
+#define ERRBNK_DEBR1_SWDEF_Pos             30U                                         /*!< ERRBNK DEBR1: SWDEF Position */
+#define ERRBNK_DEBR1_SWDEF_Msk             (0x3UL << ERRBNK_DEBR1_SWDEF_Pos)           /*!< ERRBNK DEBR1: SWDEF Mask */
+
+#define ERRBNK_DEBR1_TYPE_Pos              17U                                         /*!< ERRBNK DEBR1: TYPE Position */
+#define ERRBNK_DEBR1_TYPE_Msk              (0x1UL << ERRBNK_DEBR1_TYPE_Pos)            /*!< ERRBNK DEBR1: TYPE Mask */
+
+#define ERRBNK_DEBR1_BANK_Pos              16U                                         /*!< ERRBNK DEBR1: BANK Position */
+#define ERRBNK_DEBR1_BANK_Msk              (0x1UL << ERRBNK_DEBR1_BANK_Pos)            /*!< ERRBNK DEBR1: BANK Mask */
+
+#define ERRBNK_DEBR1_LOCATION_Pos           2U                                         /*!< ERRBNK DEBR1: LOCATION Position */
+#define ERRBNK_DEBR1_LOCATION_Msk          (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos)     /*!< ERRBNK DEBR1: LOCATION Mask */
+
+#define ERRBNK_DEBR1_LOCKED_Pos             1U                                         /*!< ERRBNK DEBR1: LOCKED Position */
+#define ERRBNK_DEBR1_LOCKED_Msk            (0x1UL << ERRBNK_DEBR1_LOCKED_Pos)          /*!< ERRBNK DEBR1: LOCKED Mask */
+
+#define ERRBNK_DEBR1_VALID_Pos              0U                                         /*!< ERRBNK DEBR1: VALID Position */
+#define ERRBNK_DEBR1_VALID_Msk             (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/)       /*!< ERRBNK DEBR1: VALID Mask */
+
+/* ERRBNK TCM Error Bank Register 0 (TEBR0) Register Definitions */
+#define ERRBNK_TEBR0_SWDEF_Pos             30U                                         /*!< ERRBNK TEBR0: SWDEF Position */
+#define ERRBNK_TEBR0_SWDEF_Msk             (0x3UL << ERRBNK_TEBR0_SWDEF_Pos)           /*!< ERRBNK TEBR0: SWDEF Mask */
+
+#define ERRBNK_TEBR0_POISON_Pos            28U                                         /*!< ERRBNK TEBR0: POISON Position */
+#define ERRBNK_TEBR0_POISON_Msk            (0x1UL << ERRBNK_TEBR0_POISON_Pos)          /*!< ERRBNK TEBR0: POISON Mask */
+
+#define ERRBNK_TEBR0_TYPE_Pos              27U                                         /*!< ERRBNK TEBR0: TYPE Position */
+#define ERRBNK_TEBR0_TYPE_Msk              (0x1UL << ERRBNK_TEBR0_TYPE_Pos)            /*!< ERRBNK TEBR0: TYPE Mask */
+
+#define ERRBNK_TEBR0_BANK_Pos              24U                                         /*!< ERRBNK TEBR0: BANK Position */
+#define ERRBNK_TEBR0_BANK_Msk              (0x3UL << ERRBNK_TEBR0_BANK_Pos)            /*!< ERRBNK TEBR0: BANK Mask */
+
+#define ERRBNK_TEBR0_LOCATION_Pos           2U                                         /*!< ERRBNK TEBR0: LOCATION Position */
+#define ERRBNK_TEBR0_LOCATION_Msk          (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos)   /*!< ERRBNK TEBR0: LOCATION Mask */
+
+#define ERRBNK_TEBR0_LOCKED_Pos             1U                                         /*!< ERRBNK TEBR0: LOCKED Position */
+#define ERRBNK_TEBR0_LOCKED_Msk            (0x1UL << ERRBNK_TEBR0_LOCKED_Pos)          /*!< ERRBNK TEBR0: LOCKED Mask */
+
+#define ERRBNK_TEBR0_VALID_Pos              0U                                         /*!< ERRBNK TEBR0: VALID Position */
+#define ERRBNK_TEBR0_VALID_Msk             (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/)       /*!< ERRBNK TEBR0: VALID Mask */
+
+/* ERRBNK TCM Error Bank Register 1 (TEBR1) Register Definitions */
+#define ERRBNK_TEBR1_SWDEF_Pos             30U                                         /*!< ERRBNK TEBR1: SWDEF Position */
+#define ERRBNK_TEBR1_SWDEF_Msk             (0x3UL << ERRBNK_TEBR1_SWDEF_Pos)           /*!< ERRBNK TEBR1: SWDEF Mask */
+
+#define ERRBNK_TEBR1_POISON_Pos            28U                                         /*!< ERRBNK TEBR1: POISON Position */
+#define ERRBNK_TEBR1_POISON_Msk            (0x1UL << ERRBNK_TEBR1_POISON_Pos)          /*!< ERRBNK TEBR1: POISON Mask */
+
+#define ERRBNK_TEBR1_TYPE_Pos              27U                                         /*!< ERRBNK TEBR1: TYPE Position */
+#define ERRBNK_TEBR1_TYPE_Msk              (0x1UL << ERRBNK_TEBR1_TYPE_Pos)            /*!< ERRBNK TEBR1: TYPE Mask */
+
+#define ERRBNK_TEBR1_BANK_Pos              24U                                         /*!< ERRBNK TEBR1: BANK Position */
+#define ERRBNK_TEBR1_BANK_Msk              (0x3UL << ERRBNK_TEBR1_BANK_Pos)            /*!< ERRBNK TEBR1: BANK Mask */
+
+#define ERRBNK_TEBR1_LOCATION_Pos           2U                                         /*!< ERRBNK TEBR1: LOCATION Position */
+#define ERRBNK_TEBR1_LOCATION_Msk          (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos)   /*!< ERRBNK TEBR1: LOCATION Mask */
+
+#define ERRBNK_TEBR1_LOCKED_Pos             1U                                         /*!< ERRBNK TEBR1: LOCKED Position */
+#define ERRBNK_TEBR1_LOCKED_Msk            (0x1UL << ERRBNK_TEBR1_LOCKED_Pos)          /*!< ERRBNK TEBR1: LOCKED Mask */
+
+#define ERRBNK_TEBR1_VALID_Pos              0U                                         /*!< ERRBNK TEBR1: VALID Position */
+#define ERRBNK_TEBR1_VALID_Msk             (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/)       /*!< ERRBNK TEBR1: VALID Mask */
+
+/*@}*/ /* end of group ErrBnk_Type */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup PrcCfgInf_Type     Processor Configuration Information Registers (IMPLEMENTATION DEFINED)
+  \brief    Type definitions for the Processor Configuration Information Registerss (PRCCFGINF)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Processor Configuration Information Registerss (PRCCFGINF).
+ */
+typedef struct
+{
+  __OM  uint32_t CFGINFOSEL;             /*!< Offset: 0x000 ( /W)  Processor Configuration Information Selection Register */
+  __IM  uint32_t CFGINFORD;              /*!< Offset: 0x004 (R/ )  Processor Configuration Information Read Data Register */
+} PrcCfgInf_Type;
+
+/* PRCCFGINF Processor Configuration Information Selection Register (CFGINFOSEL) Definitions */
+
+/* PRCCFGINF Processor Configuration Information Read Data Register (CFGINFORD) Definitions */
+
+/*@}*/ /* end of group PrcCfgInf_Type */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Sizes Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Sizes Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
+        uint32_t RESERVED3[809U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  Software Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  Software Lock Status Register */
+        uint32_t RESERVED4[4U];
+  __IM  uint32_t TYPE;                   /*!< Offset: 0xFC8 (R/ )  Device Identifier Register */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos              0U                                         /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk             (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)    /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFmt_Pos                  0U                                         /*!< TPI FFCR: EnFmt Position */
+#define TPI_FFCR_EnFmt_Msk                 (0x3UL << /*TPI_FFCR_EnFmt_Pos*/)           /*!< TPI FFCR: EnFmt Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos                0U                                         /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk               (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)        /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos                     1U                                         /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk                    (0x1UL << TPI_LSR_nTT_Pos)                  /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos                     1U                                         /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk                    (0x1UL << TPI_LSR_SLK_Pos)                  /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos                     0U                                         /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk                    (0x1UL /*<< TPI_LSR_SLI_Pos*/)              /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_PMU     Performance Monitoring Unit (PMU)
+  \brief    Type definitions for the Performance Monitoring Unit (PMU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Performance Monitoring Unit (PMU).
+ */
+typedef struct
+{
+  __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT];        /*!< Offset: 0x0 (R/W)    PMU Event Counter Registers */
+#if __PMU_NUM_EVENTCNT<31
+        uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT];
+#endif
+  __IOM uint32_t CCNTR;                             /*!< Offset: 0x7C (R/W)   PMU Cycle Counter Register */
+        uint32_t RESERVED1[224];
+  __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT];       /*!< Offset: 0x400 (R/W)  PMU Event Type and Filter Registers */
+#if __PMU_NUM_EVENTCNT<31
+        uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT];
+#endif
+  __IOM uint32_t CCFILTR;                           /*!< Offset: 0x47C (R/W)  PMU Cycle Counter Filter Register */
+        uint32_t RESERVED3[480];
+  __IOM uint32_t CNTENSET;                          /*!< Offset: 0xC00 (R/W)  PMU Count Enable Set Register */
+        uint32_t RESERVED4[7];
+  __IOM uint32_t CNTENCLR;                          /*!< Offset: 0xC20 (R/W)  PMU Count Enable Clear Register */
+        uint32_t RESERVED5[7];
+  __IOM uint32_t INTENSET;                          /*!< Offset: 0xC40 (R/W)  PMU Interrupt Enable Set Register */
+        uint32_t RESERVED6[7];
+  __IOM uint32_t INTENCLR;                          /*!< Offset: 0xC60 (R/W)  PMU Interrupt Enable Clear Register */
+        uint32_t RESERVED7[7];
+  __IOM uint32_t OVSCLR;                            /*!< Offset: 0xC80 (R/W)  PMU Overflow Flag Status Clear Register */
+        uint32_t RESERVED8[7];
+  __IOM uint32_t SWINC;                             /*!< Offset: 0xCA0 (R/W)  PMU Software Increment Register */
+        uint32_t RESERVED9[7];
+  __IOM uint32_t OVSSET;                            /*!< Offset: 0xCC0 (R/W)  PMU Overflow Flag Status Set Register */
+        uint32_t RESERVED10[79];
+  __IOM uint32_t TYPE;                              /*!< Offset: 0xE00 (R/W)  PMU Type Register */
+  __IOM uint32_t CTRL;                              /*!< Offset: 0xE04 (R/W)  PMU Control Register */
+        uint32_t RESERVED11[108];
+  __IOM uint32_t AUTHSTATUS;                        /*!< Offset: 0xFB8 (R/W)  PMU Authentication Status Register */
+  __IOM uint32_t DEVARCH;                           /*!< Offset: 0xFBC (R/W)  PMU Device Architecture Register */
+        uint32_t RESERVED12[3];
+  __IOM uint32_t DEVTYPE;                           /*!< Offset: 0xFCC (R/W)  PMU Device Type Register */
+  __IOM uint32_t PIDR4;                             /*!< Offset: 0xFD0 (R/W)  PMU Peripheral Identification Register 4 */
+        uint32_t RESERVED13[3];
+  __IOM uint32_t PIDR0;                             /*!< Offset: 0xFE0 (R/W)  PMU Peripheral Identification Register 0 */
+  __IOM uint32_t PIDR1;                             /*!< Offset: 0xFE4 (R/W)  PMU Peripheral Identification Register 1 */
+  __IOM uint32_t PIDR2;                             /*!< Offset: 0xFE8 (R/W)  PMU Peripheral Identification Register 2 */
+  __IOM uint32_t PIDR3;                             /*!< Offset: 0xFEC (R/W)  PMU Peripheral Identification Register 3 */
+  __IOM uint32_t CIDR0;                             /*!< Offset: 0xFF0 (R/W)  PMU Component Identification Register 0 */
+  __IOM uint32_t CIDR1;                             /*!< Offset: 0xFF4 (R/W)  PMU Component Identification Register 1 */
+  __IOM uint32_t CIDR2;                             /*!< Offset: 0xFF8 (R/W)  PMU Component Identification Register 2 */
+  __IOM uint32_t CIDR3;                             /*!< Offset: 0xFFC (R/W)  PMU Component Identification Register 3 */
+} PMU_Type;
+
+/** \brief PMU Event Counter Registers (0-30) Definitions  */
+
+#define PMU_EVCNTR_CNT_Pos                    0U                                           /*!< PMU EVCNTR: Counter Position */
+#define PMU_EVCNTR_CNT_Msk                   (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/)         /*!< PMU EVCNTR: Counter Mask */
+
+/** \brief PMU Event Type and Filter Registers (0-30) Definitions  */
+
+#define PMU_EVTYPER_EVENTTOCNT_Pos            0U                                           /*!< PMU EVTYPER: Event to Count Position */
+#define PMU_EVTYPER_EVENTTOCNT_Msk           (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/)     /*!< PMU EVTYPER: Event to Count Mask */
+
+/** \brief PMU Count Enable Set Register Definitions */
+
+#define PMU_CNTENSET_CNT0_ENABLE_Pos          0U                                           /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */
+#define PMU_CNTENSET_CNT0_ENABLE_Msk         (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/)     /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT1_ENABLE_Pos          1U                                           /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */
+#define PMU_CNTENSET_CNT1_ENABLE_Msk         (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos)         /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT2_ENABLE_Pos          2U                                           /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */
+#define PMU_CNTENSET_CNT2_ENABLE_Msk         (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos)         /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT3_ENABLE_Pos          3U                                           /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */
+#define PMU_CNTENSET_CNT3_ENABLE_Msk         (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos)         /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT4_ENABLE_Pos          4U                                           /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */
+#define PMU_CNTENSET_CNT4_ENABLE_Msk         (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos)         /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT5_ENABLE_Pos          5U                                           /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */
+#define PMU_CNTENSET_CNT5_ENABLE_Msk         (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos)         /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT6_ENABLE_Pos          6U                                           /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */
+#define PMU_CNTENSET_CNT6_ENABLE_Msk         (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos)         /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT7_ENABLE_Pos          7U                                           /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */
+#define PMU_CNTENSET_CNT7_ENABLE_Msk         (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos)         /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT8_ENABLE_Pos          8U                                           /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */
+#define PMU_CNTENSET_CNT8_ENABLE_Msk         (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos)         /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT9_ENABLE_Pos          9U                                           /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */
+#define PMU_CNTENSET_CNT9_ENABLE_Msk         (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos)         /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT10_ENABLE_Pos         10U                                          /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */
+#define PMU_CNTENSET_CNT10_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT11_ENABLE_Pos         11U                                          /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */
+#define PMU_CNTENSET_CNT11_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT12_ENABLE_Pos         12U                                          /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */
+#define PMU_CNTENSET_CNT12_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT13_ENABLE_Pos         13U                                          /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */
+#define PMU_CNTENSET_CNT13_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT14_ENABLE_Pos         14U                                          /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */
+#define PMU_CNTENSET_CNT14_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT15_ENABLE_Pos         15U                                          /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */
+#define PMU_CNTENSET_CNT15_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT16_ENABLE_Pos         16U                                          /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */
+#define PMU_CNTENSET_CNT16_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT17_ENABLE_Pos         17U                                          /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */
+#define PMU_CNTENSET_CNT17_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT18_ENABLE_Pos         18U                                          /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */
+#define PMU_CNTENSET_CNT18_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT19_ENABLE_Pos         19U                                          /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */
+#define PMU_CNTENSET_CNT19_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT20_ENABLE_Pos         20U                                          /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */
+#define PMU_CNTENSET_CNT20_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT21_ENABLE_Pos         21U                                          /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */
+#define PMU_CNTENSET_CNT21_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT22_ENABLE_Pos         22U                                          /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */
+#define PMU_CNTENSET_CNT22_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT23_ENABLE_Pos         23U                                          /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */
+#define PMU_CNTENSET_CNT23_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT24_ENABLE_Pos         24U                                          /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */
+#define PMU_CNTENSET_CNT24_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT25_ENABLE_Pos         25U                                          /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */
+#define PMU_CNTENSET_CNT25_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT26_ENABLE_Pos         26U                                          /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */
+#define PMU_CNTENSET_CNT26_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT27_ENABLE_Pos         27U                                          /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */
+#define PMU_CNTENSET_CNT27_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT28_ENABLE_Pos         28U                                          /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */
+#define PMU_CNTENSET_CNT28_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT29_ENABLE_Pos         29U                                          /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */
+#define PMU_CNTENSET_CNT29_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT30_ENABLE_Pos         30U                                          /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */
+#define PMU_CNTENSET_CNT30_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */
+
+#define PMU_CNTENSET_CCNTR_ENABLE_Pos         31U                                          /*!< PMU CNTENSET: Cycle Counter Enable Set Position */
+#define PMU_CNTENSET_CCNTR_ENABLE_Msk        (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos)        /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */
+
+/** \brief PMU Count Enable Clear Register Definitions */
+
+#define PMU_CNTENSET_CNT0_ENABLE_Pos          0U                                           /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */
+#define PMU_CNTENCLR_CNT0_ENABLE_Msk         (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/)     /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT1_ENABLE_Pos          1U                                           /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */
+#define PMU_CNTENCLR_CNT1_ENABLE_Msk         (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos)         /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */
+
+#define PMU_CNTENCLR_CNT2_ENABLE_Pos          2U                                           /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */
+#define PMU_CNTENCLR_CNT2_ENABLE_Msk         (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos)         /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT3_ENABLE_Pos          3U                                           /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */
+#define PMU_CNTENCLR_CNT3_ENABLE_Msk         (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos)         /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT4_ENABLE_Pos          4U                                           /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */
+#define PMU_CNTENCLR_CNT4_ENABLE_Msk         (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos)         /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT5_ENABLE_Pos          5U                                           /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */
+#define PMU_CNTENCLR_CNT5_ENABLE_Msk         (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos)         /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT6_ENABLE_Pos          6U                                           /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */
+#define PMU_CNTENCLR_CNT6_ENABLE_Msk         (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos)         /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT7_ENABLE_Pos          7U                                           /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */
+#define PMU_CNTENCLR_CNT7_ENABLE_Msk         (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos)         /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT8_ENABLE_Pos          8U                                           /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */
+#define PMU_CNTENCLR_CNT8_ENABLE_Msk         (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos)         /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT9_ENABLE_Pos          9U                                           /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */
+#define PMU_CNTENCLR_CNT9_ENABLE_Msk         (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos)         /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT10_ENABLE_Pos         10U                                          /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */
+#define PMU_CNTENCLR_CNT10_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT11_ENABLE_Pos         11U                                          /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */
+#define PMU_CNTENCLR_CNT11_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT12_ENABLE_Pos         12U                                          /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */
+#define PMU_CNTENCLR_CNT12_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT13_ENABLE_Pos         13U                                          /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */
+#define PMU_CNTENCLR_CNT13_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT14_ENABLE_Pos         14U                                          /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */
+#define PMU_CNTENCLR_CNT14_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT15_ENABLE_Pos         15U                                          /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */
+#define PMU_CNTENCLR_CNT15_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT16_ENABLE_Pos         16U                                          /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */
+#define PMU_CNTENCLR_CNT16_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT17_ENABLE_Pos         17U                                          /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */
+#define PMU_CNTENCLR_CNT17_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT18_ENABLE_Pos         18U                                          /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */
+#define PMU_CNTENCLR_CNT18_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT19_ENABLE_Pos         19U                                          /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */
+#define PMU_CNTENCLR_CNT19_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT20_ENABLE_Pos         20U                                          /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */
+#define PMU_CNTENCLR_CNT20_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT21_ENABLE_Pos         21U                                          /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */
+#define PMU_CNTENCLR_CNT21_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT22_ENABLE_Pos         22U                                          /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */
+#define PMU_CNTENCLR_CNT22_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT23_ENABLE_Pos         23U                                          /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */
+#define PMU_CNTENCLR_CNT23_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT24_ENABLE_Pos         24U                                          /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */
+#define PMU_CNTENCLR_CNT24_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT25_ENABLE_Pos         25U                                          /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */
+#define PMU_CNTENCLR_CNT25_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT26_ENABLE_Pos         26U                                          /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */
+#define PMU_CNTENCLR_CNT26_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT27_ENABLE_Pos         27U                                          /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */
+#define PMU_CNTENCLR_CNT27_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT28_ENABLE_Pos         28U                                          /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */
+#define PMU_CNTENCLR_CNT28_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT29_ENABLE_Pos         29U                                          /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */
+#define PMU_CNTENCLR_CNT29_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT30_ENABLE_Pos         30U                                          /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */
+#define PMU_CNTENCLR_CNT30_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CCNTR_ENABLE_Pos         31U                                          /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */
+#define PMU_CNTENCLR_CCNTR_ENABLE_Msk        (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos)        /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */
+
+/** \brief PMU Interrupt Enable Set Register Definitions */
+
+#define PMU_INTENSET_CNT0_ENABLE_Pos          0U                                           /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT0_ENABLE_Msk         (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/)     /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT1_ENABLE_Pos          1U                                           /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT1_ENABLE_Msk         (1UL << PMU_INTENSET_CNT1_ENABLE_Pos)         /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT2_ENABLE_Pos          2U                                           /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT2_ENABLE_Msk         (1UL << PMU_INTENSET_CNT2_ENABLE_Pos)         /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT3_ENABLE_Pos          3U                                           /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT3_ENABLE_Msk         (1UL << PMU_INTENSET_CNT3_ENABLE_Pos)         /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT4_ENABLE_Pos          4U                                           /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT4_ENABLE_Msk         (1UL << PMU_INTENSET_CNT4_ENABLE_Pos)         /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT5_ENABLE_Pos          5U                                           /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT5_ENABLE_Msk         (1UL << PMU_INTENSET_CNT5_ENABLE_Pos)         /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT6_ENABLE_Pos          6U                                           /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT6_ENABLE_Msk         (1UL << PMU_INTENSET_CNT6_ENABLE_Pos)         /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT7_ENABLE_Pos          7U                                           /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT7_ENABLE_Msk         (1UL << PMU_INTENSET_CNT7_ENABLE_Pos)         /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT8_ENABLE_Pos          8U                                           /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT8_ENABLE_Msk         (1UL << PMU_INTENSET_CNT8_ENABLE_Pos)         /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT9_ENABLE_Pos          9U                                           /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT9_ENABLE_Msk         (1UL << PMU_INTENSET_CNT9_ENABLE_Pos)         /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT10_ENABLE_Pos         10U                                          /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT10_ENABLE_Msk        (1UL << PMU_INTENSET_CNT10_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT11_ENABLE_Pos         11U                                          /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT11_ENABLE_Msk        (1UL << PMU_INTENSET_CNT11_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT12_ENABLE_Pos         12U                                          /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT12_ENABLE_Msk        (1UL << PMU_INTENSET_CNT12_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT13_ENABLE_Pos         13U                                          /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT13_ENABLE_Msk        (1UL << PMU_INTENSET_CNT13_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT14_ENABLE_Pos         14U                                          /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT14_ENABLE_Msk        (1UL << PMU_INTENSET_CNT14_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT15_ENABLE_Pos         15U                                          /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT15_ENABLE_Msk        (1UL << PMU_INTENSET_CNT15_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT16_ENABLE_Pos         16U                                          /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT16_ENABLE_Msk        (1UL << PMU_INTENSET_CNT16_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT17_ENABLE_Pos         17U                                          /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT17_ENABLE_Msk        (1UL << PMU_INTENSET_CNT17_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT18_ENABLE_Pos         18U                                          /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT18_ENABLE_Msk        (1UL << PMU_INTENSET_CNT18_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT19_ENABLE_Pos         19U                                          /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT19_ENABLE_Msk        (1UL << PMU_INTENSET_CNT19_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT20_ENABLE_Pos         20U                                          /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT20_ENABLE_Msk        (1UL << PMU_INTENSET_CNT20_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT21_ENABLE_Pos         21U                                          /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT21_ENABLE_Msk        (1UL << PMU_INTENSET_CNT21_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT22_ENABLE_Pos         22U                                          /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT22_ENABLE_Msk        (1UL << PMU_INTENSET_CNT22_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT23_ENABLE_Pos         23U                                          /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT23_ENABLE_Msk        (1UL << PMU_INTENSET_CNT23_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT24_ENABLE_Pos         24U                                          /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT24_ENABLE_Msk        (1UL << PMU_INTENSET_CNT24_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT25_ENABLE_Pos         25U                                          /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT25_ENABLE_Msk        (1UL << PMU_INTENSET_CNT25_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT26_ENABLE_Pos         26U                                          /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT26_ENABLE_Msk        (1UL << PMU_INTENSET_CNT26_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT27_ENABLE_Pos         27U                                          /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT27_ENABLE_Msk        (1UL << PMU_INTENSET_CNT27_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT28_ENABLE_Pos         28U                                          /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT28_ENABLE_Msk        (1UL << PMU_INTENSET_CNT28_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT29_ENABLE_Pos         29U                                          /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT29_ENABLE_Msk        (1UL << PMU_INTENSET_CNT29_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT30_ENABLE_Pos         30U                                          /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT30_ENABLE_Msk        (1UL << PMU_INTENSET_CNT30_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CYCCNT_ENABLE_Pos        31U                                          /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */
+#define PMU_INTENSET_CCYCNT_ENABLE_Msk       (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos)       /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */
+
+/** \brief PMU Interrupt Enable Clear Register Definitions */
+
+#define PMU_INTENSET_CNT0_ENABLE_Pos          0U                                           /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT0_ENABLE_Msk         (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/)     /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT1_ENABLE_Pos          1U                                           /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT1_ENABLE_Msk         (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos)         /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */
+
+#define PMU_INTENCLR_CNT2_ENABLE_Pos          2U                                           /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT2_ENABLE_Msk         (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos)         /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT3_ENABLE_Pos          3U                                           /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT3_ENABLE_Msk         (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos)         /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT4_ENABLE_Pos          4U                                           /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT4_ENABLE_Msk         (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos)         /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT5_ENABLE_Pos          5U                                           /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT5_ENABLE_Msk         (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos)         /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT6_ENABLE_Pos          6U                                           /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT6_ENABLE_Msk         (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos)         /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT7_ENABLE_Pos          7U                                           /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT7_ENABLE_Msk         (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos)         /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT8_ENABLE_Pos          8U                                           /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT8_ENABLE_Msk         (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos)         /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT9_ENABLE_Pos          9U                                           /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT9_ENABLE_Msk         (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos)         /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT10_ENABLE_Pos         10U                                          /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT10_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT11_ENABLE_Pos         11U                                          /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT11_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT12_ENABLE_Pos         12U                                          /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT12_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT13_ENABLE_Pos         13U                                          /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT13_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT14_ENABLE_Pos         14U                                          /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT14_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT15_ENABLE_Pos         15U                                          /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT15_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT16_ENABLE_Pos         16U                                          /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT16_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT17_ENABLE_Pos         17U                                          /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT17_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT18_ENABLE_Pos         18U                                          /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT18_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT19_ENABLE_Pos         19U                                          /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT19_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT20_ENABLE_Pos         20U                                          /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT20_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT21_ENABLE_Pos         21U                                          /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT21_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT22_ENABLE_Pos         22U                                          /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT22_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT23_ENABLE_Pos         23U                                          /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT23_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT24_ENABLE_Pos         24U                                          /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT24_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT25_ENABLE_Pos         25U                                          /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT25_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT26_ENABLE_Pos         26U                                          /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT26_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT27_ENABLE_Pos         27U                                          /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT27_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT28_ENABLE_Pos         28U                                          /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT28_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT29_ENABLE_Pos         29U                                          /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT29_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT30_ENABLE_Pos         30U                                          /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT30_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CYCCNT_ENABLE_Pos        31U                                          /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CYCCNT_ENABLE_Msk       (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos)       /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */
+
+/** \brief PMU Overflow Flag Status Set Register Definitions */
+
+#define PMU_OVSSET_CNT0_STATUS_Pos            0U                                           /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */
+#define PMU_OVSSET_CNT0_STATUS_Msk           (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/)       /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT1_STATUS_Pos            1U                                           /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */
+#define PMU_OVSSET_CNT1_STATUS_Msk           (1UL << PMU_OVSSET_CNT1_STATUS_Pos)           /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT2_STATUS_Pos            2U                                           /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */
+#define PMU_OVSSET_CNT2_STATUS_Msk           (1UL << PMU_OVSSET_CNT2_STATUS_Pos)           /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT3_STATUS_Pos            3U                                           /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */
+#define PMU_OVSSET_CNT3_STATUS_Msk           (1UL << PMU_OVSSET_CNT3_STATUS_Pos)           /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT4_STATUS_Pos            4U                                           /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */
+#define PMU_OVSSET_CNT4_STATUS_Msk           (1UL << PMU_OVSSET_CNT4_STATUS_Pos)           /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT5_STATUS_Pos            5U                                           /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */
+#define PMU_OVSSET_CNT5_STATUS_Msk           (1UL << PMU_OVSSET_CNT5_STATUS_Pos)           /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT6_STATUS_Pos            6U                                           /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */
+#define PMU_OVSSET_CNT6_STATUS_Msk           (1UL << PMU_OVSSET_CNT6_STATUS_Pos)           /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT7_STATUS_Pos            7U                                           /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */
+#define PMU_OVSSET_CNT7_STATUS_Msk           (1UL << PMU_OVSSET_CNT7_STATUS_Pos)           /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT8_STATUS_Pos            8U                                           /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */
+#define PMU_OVSSET_CNT8_STATUS_Msk           (1UL << PMU_OVSSET_CNT8_STATUS_Pos)           /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT9_STATUS_Pos            9U                                           /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */
+#define PMU_OVSSET_CNT9_STATUS_Msk           (1UL << PMU_OVSSET_CNT9_STATUS_Pos)           /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT10_STATUS_Pos           10U                                          /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */
+#define PMU_OVSSET_CNT10_STATUS_Msk          (1UL << PMU_OVSSET_CNT10_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT11_STATUS_Pos           11U                                          /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */
+#define PMU_OVSSET_CNT11_STATUS_Msk          (1UL << PMU_OVSSET_CNT11_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT12_STATUS_Pos           12U                                          /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */
+#define PMU_OVSSET_CNT12_STATUS_Msk          (1UL << PMU_OVSSET_CNT12_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT13_STATUS_Pos           13U                                          /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */
+#define PMU_OVSSET_CNT13_STATUS_Msk          (1UL << PMU_OVSSET_CNT13_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT14_STATUS_Pos           14U                                          /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */
+#define PMU_OVSSET_CNT14_STATUS_Msk          (1UL << PMU_OVSSET_CNT14_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT15_STATUS_Pos           15U                                          /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */
+#define PMU_OVSSET_CNT15_STATUS_Msk          (1UL << PMU_OVSSET_CNT15_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT16_STATUS_Pos           16U                                          /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */
+#define PMU_OVSSET_CNT16_STATUS_Msk          (1UL << PMU_OVSSET_CNT16_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT17_STATUS_Pos           17U                                          /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */
+#define PMU_OVSSET_CNT17_STATUS_Msk          (1UL << PMU_OVSSET_CNT17_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT18_STATUS_Pos           18U                                          /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */
+#define PMU_OVSSET_CNT18_STATUS_Msk          (1UL << PMU_OVSSET_CNT18_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT19_STATUS_Pos           19U                                          /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */
+#define PMU_OVSSET_CNT19_STATUS_Msk          (1UL << PMU_OVSSET_CNT19_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT20_STATUS_Pos           20U                                          /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */
+#define PMU_OVSSET_CNT20_STATUS_Msk          (1UL << PMU_OVSSET_CNT20_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT21_STATUS_Pos           21U                                          /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */
+#define PMU_OVSSET_CNT21_STATUS_Msk          (1UL << PMU_OVSSET_CNT21_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT22_STATUS_Pos           22U                                          /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */
+#define PMU_OVSSET_CNT22_STATUS_Msk          (1UL << PMU_OVSSET_CNT22_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT23_STATUS_Pos           23U                                          /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */
+#define PMU_OVSSET_CNT23_STATUS_Msk          (1UL << PMU_OVSSET_CNT23_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT24_STATUS_Pos           24U                                          /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */
+#define PMU_OVSSET_CNT24_STATUS_Msk          (1UL << PMU_OVSSET_CNT24_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT25_STATUS_Pos           25U                                          /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */
+#define PMU_OVSSET_CNT25_STATUS_Msk          (1UL << PMU_OVSSET_CNT25_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT26_STATUS_Pos           26U                                          /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */
+#define PMU_OVSSET_CNT26_STATUS_Msk          (1UL << PMU_OVSSET_CNT26_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT27_STATUS_Pos           27U                                          /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */
+#define PMU_OVSSET_CNT27_STATUS_Msk          (1UL << PMU_OVSSET_CNT27_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT28_STATUS_Pos           28U                                          /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */
+#define PMU_OVSSET_CNT28_STATUS_Msk          (1UL << PMU_OVSSET_CNT28_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT29_STATUS_Pos           29U                                          /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */
+#define PMU_OVSSET_CNT29_STATUS_Msk          (1UL << PMU_OVSSET_CNT29_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT30_STATUS_Pos           30U                                          /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */
+#define PMU_OVSSET_CNT30_STATUS_Msk          (1UL << PMU_OVSSET_CNT30_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */
+
+#define PMU_OVSSET_CYCCNT_STATUS_Pos          31U                                          /*!< PMU OVSSET: Cycle Counter Overflow Set Position */
+#define PMU_OVSSET_CYCCNT_STATUS_Msk         (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos)         /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */
+
+/** \brief PMU Overflow Flag Status Clear Register Definitions */
+
+#define PMU_OVSCLR_CNT0_STATUS_Pos            0U                                           /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */
+#define PMU_OVSCLR_CNT0_STATUS_Msk           (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/)       /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT1_STATUS_Pos            1U                                           /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */
+#define PMU_OVSCLR_CNT1_STATUS_Msk           (1UL << PMU_OVSCLR_CNT1_STATUS_Pos)           /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */
+
+#define PMU_OVSCLR_CNT2_STATUS_Pos            2U                                           /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */
+#define PMU_OVSCLR_CNT2_STATUS_Msk           (1UL << PMU_OVSCLR_CNT2_STATUS_Pos)           /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT3_STATUS_Pos            3U                                           /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */
+#define PMU_OVSCLR_CNT3_STATUS_Msk           (1UL << PMU_OVSCLR_CNT3_STATUS_Pos)           /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT4_STATUS_Pos            4U                                           /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */
+#define PMU_OVSCLR_CNT4_STATUS_Msk           (1UL << PMU_OVSCLR_CNT4_STATUS_Pos)           /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT5_STATUS_Pos            5U                                           /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */
+#define PMU_OVSCLR_CNT5_STATUS_Msk           (1UL << PMU_OVSCLR_CNT5_STATUS_Pos)           /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT6_STATUS_Pos            6U                                           /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */
+#define PMU_OVSCLR_CNT6_STATUS_Msk           (1UL << PMU_OVSCLR_CNT6_STATUS_Pos)           /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT7_STATUS_Pos            7U                                           /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */
+#define PMU_OVSCLR_CNT7_STATUS_Msk           (1UL << PMU_OVSCLR_CNT7_STATUS_Pos)           /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT8_STATUS_Pos            8U                                           /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */
+#define PMU_OVSCLR_CNT8_STATUS_Msk           (1UL << PMU_OVSCLR_CNT8_STATUS_Pos)           /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT9_STATUS_Pos            9U                                           /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */
+#define PMU_OVSCLR_CNT9_STATUS_Msk           (1UL << PMU_OVSCLR_CNT9_STATUS_Pos)           /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT10_STATUS_Pos           10U                                          /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */
+#define PMU_OVSCLR_CNT10_STATUS_Msk          (1UL << PMU_OVSCLR_CNT10_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT11_STATUS_Pos           11U                                          /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */
+#define PMU_OVSCLR_CNT11_STATUS_Msk          (1UL << PMU_OVSCLR_CNT11_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT12_STATUS_Pos           12U                                          /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */
+#define PMU_OVSCLR_CNT12_STATUS_Msk          (1UL << PMU_OVSCLR_CNT12_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT13_STATUS_Pos           13U                                          /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */
+#define PMU_OVSCLR_CNT13_STATUS_Msk          (1UL << PMU_OVSCLR_CNT13_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT14_STATUS_Pos           14U                                          /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */
+#define PMU_OVSCLR_CNT14_STATUS_Msk          (1UL << PMU_OVSCLR_CNT14_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT15_STATUS_Pos           15U                                          /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */
+#define PMU_OVSCLR_CNT15_STATUS_Msk          (1UL << PMU_OVSCLR_CNT15_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT16_STATUS_Pos           16U                                          /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */
+#define PMU_OVSCLR_CNT16_STATUS_Msk          (1UL << PMU_OVSCLR_CNT16_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT17_STATUS_Pos           17U                                          /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */
+#define PMU_OVSCLR_CNT17_STATUS_Msk          (1UL << PMU_OVSCLR_CNT17_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT18_STATUS_Pos           18U                                          /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */
+#define PMU_OVSCLR_CNT18_STATUS_Msk          (1UL << PMU_OVSCLR_CNT18_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT19_STATUS_Pos           19U                                          /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */
+#define PMU_OVSCLR_CNT19_STATUS_Msk          (1UL << PMU_OVSCLR_CNT19_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT20_STATUS_Pos           20U                                          /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */
+#define PMU_OVSCLR_CNT20_STATUS_Msk          (1UL << PMU_OVSCLR_CNT20_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT21_STATUS_Pos           21U                                          /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */
+#define PMU_OVSCLR_CNT21_STATUS_Msk          (1UL << PMU_OVSCLR_CNT21_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT22_STATUS_Pos           22U                                          /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */
+#define PMU_OVSCLR_CNT22_STATUS_Msk          (1UL << PMU_OVSCLR_CNT22_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT23_STATUS_Pos           23U                                          /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */
+#define PMU_OVSCLR_CNT23_STATUS_Msk          (1UL << PMU_OVSCLR_CNT23_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT24_STATUS_Pos           24U                                          /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */
+#define PMU_OVSCLR_CNT24_STATUS_Msk          (1UL << PMU_OVSCLR_CNT24_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT25_STATUS_Pos           25U                                          /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */
+#define PMU_OVSCLR_CNT25_STATUS_Msk          (1UL << PMU_OVSCLR_CNT25_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT26_STATUS_Pos           26U                                          /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */
+#define PMU_OVSCLR_CNT26_STATUS_Msk          (1UL << PMU_OVSCLR_CNT26_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT27_STATUS_Pos           27U                                          /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */
+#define PMU_OVSCLR_CNT27_STATUS_Msk          (1UL << PMU_OVSCLR_CNT27_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT28_STATUS_Pos           28U                                          /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */
+#define PMU_OVSCLR_CNT28_STATUS_Msk          (1UL << PMU_OVSCLR_CNT28_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT29_STATUS_Pos           29U                                          /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */
+#define PMU_OVSCLR_CNT29_STATUS_Msk          (1UL << PMU_OVSCLR_CNT29_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT30_STATUS_Pos           30U                                          /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */
+#define PMU_OVSCLR_CNT30_STATUS_Msk          (1UL << PMU_OVSCLR_CNT30_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CYCCNT_STATUS_Pos          31U                                          /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */
+#define PMU_OVSCLR_CYCCNT_STATUS_Msk         (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos)         /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */
+
+/** \brief PMU Software Increment Counter */
+
+#define PMU_SWINC_CNT0_Pos                    0U                                           /*!< PMU SWINC: Event Counter 0 Software Increment Position */
+#define PMU_SWINC_CNT0_Msk                   (1UL /*<< PMU_SWINC_CNT0_Pos */)              /*!< PMU SWINC: Event Counter 0 Software Increment Mask */
+
+#define PMU_SWINC_CNT1_Pos                    1U                                           /*!< PMU SWINC: Event Counter 1 Software Increment Position */
+#define PMU_SWINC_CNT1_Msk                   (1UL << PMU_SWINC_CNT1_Pos)                   /*!< PMU SWINC: Event Counter 1 Software Increment Mask */
+
+#define PMU_SWINC_CNT2_Pos                    2U                                           /*!< PMU SWINC: Event Counter 2 Software Increment Position */
+#define PMU_SWINC_CNT2_Msk                   (1UL << PMU_SWINC_CNT2_Pos)                   /*!< PMU SWINC: Event Counter 2 Software Increment Mask */
+
+#define PMU_SWINC_CNT3_Pos                    3U                                           /*!< PMU SWINC: Event Counter 3 Software Increment Position */
+#define PMU_SWINC_CNT3_Msk                   (1UL << PMU_SWINC_CNT3_Pos)                   /*!< PMU SWINC: Event Counter 3 Software Increment Mask */
+
+#define PMU_SWINC_CNT4_Pos                    4U                                           /*!< PMU SWINC: Event Counter 4 Software Increment Position */
+#define PMU_SWINC_CNT4_Msk                   (1UL << PMU_SWINC_CNT4_Pos)                   /*!< PMU SWINC: Event Counter 4 Software Increment Mask */
+
+#define PMU_SWINC_CNT5_Pos                    5U                                           /*!< PMU SWINC: Event Counter 5 Software Increment Position */
+#define PMU_SWINC_CNT5_Msk                   (1UL << PMU_SWINC_CNT5_Pos)                   /*!< PMU SWINC: Event Counter 5 Software Increment Mask */
+
+#define PMU_SWINC_CNT6_Pos                    6U                                           /*!< PMU SWINC: Event Counter 6 Software Increment Position */
+#define PMU_SWINC_CNT6_Msk                   (1UL << PMU_SWINC_CNT6_Pos)                   /*!< PMU SWINC: Event Counter 6 Software Increment Mask */
+
+#define PMU_SWINC_CNT7_Pos                    7U                                           /*!< PMU SWINC: Event Counter 7 Software Increment Position */
+#define PMU_SWINC_CNT7_Msk                   (1UL << PMU_SWINC_CNT7_Pos)                   /*!< PMU SWINC: Event Counter 7 Software Increment Mask */
+
+#define PMU_SWINC_CNT8_Pos                    8U                                           /*!< PMU SWINC: Event Counter 8 Software Increment Position */
+#define PMU_SWINC_CNT8_Msk                   (1UL << PMU_SWINC_CNT8_Pos)                   /*!< PMU SWINC: Event Counter 8 Software Increment Mask */
+
+#define PMU_SWINC_CNT9_Pos                    9U                                           /*!< PMU SWINC: Event Counter 9 Software Increment Position */
+#define PMU_SWINC_CNT9_Msk                   (1UL << PMU_SWINC_CNT9_Pos)                   /*!< PMU SWINC: Event Counter 9 Software Increment Mask */
+
+#define PMU_SWINC_CNT10_Pos                   10U                                          /*!< PMU SWINC: Event Counter 10 Software Increment Position */
+#define PMU_SWINC_CNT10_Msk                  (1UL << PMU_SWINC_CNT10_Pos)                  /*!< PMU SWINC: Event Counter 10 Software Increment Mask */
+
+#define PMU_SWINC_CNT11_Pos                   11U                                          /*!< PMU SWINC: Event Counter 11 Software Increment Position */
+#define PMU_SWINC_CNT11_Msk                  (1UL << PMU_SWINC_CNT11_Pos)                  /*!< PMU SWINC: Event Counter 11 Software Increment Mask */
+
+#define PMU_SWINC_CNT12_Pos                   12U                                          /*!< PMU SWINC: Event Counter 12 Software Increment Position */
+#define PMU_SWINC_CNT12_Msk                  (1UL << PMU_SWINC_CNT12_Pos)                  /*!< PMU SWINC: Event Counter 12 Software Increment Mask */
+
+#define PMU_SWINC_CNT13_Pos                   13U                                          /*!< PMU SWINC: Event Counter 13 Software Increment Position */
+#define PMU_SWINC_CNT13_Msk                  (1UL << PMU_SWINC_CNT13_Pos)                  /*!< PMU SWINC: Event Counter 13 Software Increment Mask */
+
+#define PMU_SWINC_CNT14_Pos                   14U                                          /*!< PMU SWINC: Event Counter 14 Software Increment Position */
+#define PMU_SWINC_CNT14_Msk                  (1UL << PMU_SWINC_CNT14_Pos)                  /*!< PMU SWINC: Event Counter 14 Software Increment Mask */
+
+#define PMU_SWINC_CNT15_Pos                   15U                                          /*!< PMU SWINC: Event Counter 15 Software Increment Position */
+#define PMU_SWINC_CNT15_Msk                  (1UL << PMU_SWINC_CNT15_Pos)                  /*!< PMU SWINC: Event Counter 15 Software Increment Mask */
+
+#define PMU_SWINC_CNT16_Pos                   16U                                          /*!< PMU SWINC: Event Counter 16 Software Increment Position */
+#define PMU_SWINC_CNT16_Msk                  (1UL << PMU_SWINC_CNT16_Pos)                  /*!< PMU SWINC: Event Counter 16 Software Increment Mask */
+
+#define PMU_SWINC_CNT17_Pos                   17U                                          /*!< PMU SWINC: Event Counter 17 Software Increment Position */
+#define PMU_SWINC_CNT17_Msk                  (1UL << PMU_SWINC_CNT17_Pos)                  /*!< PMU SWINC: Event Counter 17 Software Increment Mask */
+
+#define PMU_SWINC_CNT18_Pos                   18U                                          /*!< PMU SWINC: Event Counter 18 Software Increment Position */
+#define PMU_SWINC_CNT18_Msk                  (1UL << PMU_SWINC_CNT18_Pos)                  /*!< PMU SWINC: Event Counter 18 Software Increment Mask */
+
+#define PMU_SWINC_CNT19_Pos                   19U                                          /*!< PMU SWINC: Event Counter 19 Software Increment Position */
+#define PMU_SWINC_CNT19_Msk                  (1UL << PMU_SWINC_CNT19_Pos)                  /*!< PMU SWINC: Event Counter 19 Software Increment Mask */
+
+#define PMU_SWINC_CNT20_Pos                   20U                                          /*!< PMU SWINC: Event Counter 20 Software Increment Position */
+#define PMU_SWINC_CNT20_Msk                  (1UL << PMU_SWINC_CNT20_Pos)                  /*!< PMU SWINC: Event Counter 20 Software Increment Mask */
+
+#define PMU_SWINC_CNT21_Pos                   21U                                          /*!< PMU SWINC: Event Counter 21 Software Increment Position */
+#define PMU_SWINC_CNT21_Msk                  (1UL << PMU_SWINC_CNT21_Pos)                  /*!< PMU SWINC: Event Counter 21 Software Increment Mask */
+
+#define PMU_SWINC_CNT22_Pos                   22U                                          /*!< PMU SWINC: Event Counter 22 Software Increment Position */
+#define PMU_SWINC_CNT22_Msk                  (1UL << PMU_SWINC_CNT22_Pos)                  /*!< PMU SWINC: Event Counter 22 Software Increment Mask */
+
+#define PMU_SWINC_CNT23_Pos                   23U                                          /*!< PMU SWINC: Event Counter 23 Software Increment Position */
+#define PMU_SWINC_CNT23_Msk                  (1UL << PMU_SWINC_CNT23_Pos)                  /*!< PMU SWINC: Event Counter 23 Software Increment Mask */
+
+#define PMU_SWINC_CNT24_Pos                   24U                                          /*!< PMU SWINC: Event Counter 24 Software Increment Position */
+#define PMU_SWINC_CNT24_Msk                  (1UL << PMU_SWINC_CNT24_Pos)                  /*!< PMU SWINC: Event Counter 24 Software Increment Mask */
+
+#define PMU_SWINC_CNT25_Pos                   25U                                          /*!< PMU SWINC: Event Counter 25 Software Increment Position */
+#define PMU_SWINC_CNT25_Msk                  (1UL << PMU_SWINC_CNT25_Pos)                  /*!< PMU SWINC: Event Counter 25 Software Increment Mask */
+
+#define PMU_SWINC_CNT26_Pos                   26U                                          /*!< PMU SWINC: Event Counter 26 Software Increment Position */
+#define PMU_SWINC_CNT26_Msk                  (1UL << PMU_SWINC_CNT26_Pos)                  /*!< PMU SWINC: Event Counter 26 Software Increment Mask */
+
+#define PMU_SWINC_CNT27_Pos                   27U                                          /*!< PMU SWINC: Event Counter 27 Software Increment Position */
+#define PMU_SWINC_CNT27_Msk                  (1UL << PMU_SWINC_CNT27_Pos)                  /*!< PMU SWINC: Event Counter 27 Software Increment Mask */
+
+#define PMU_SWINC_CNT28_Pos                   28U                                          /*!< PMU SWINC: Event Counter 28 Software Increment Position */
+#define PMU_SWINC_CNT28_Msk                  (1UL << PMU_SWINC_CNT28_Pos)                  /*!< PMU SWINC: Event Counter 28 Software Increment Mask */
+
+#define PMU_SWINC_CNT29_Pos                   29U                                          /*!< PMU SWINC: Event Counter 29 Software Increment Position */
+#define PMU_SWINC_CNT29_Msk                  (1UL << PMU_SWINC_CNT29_Pos)                  /*!< PMU SWINC: Event Counter 29 Software Increment Mask */
+
+#define PMU_SWINC_CNT30_Pos                   30U                                          /*!< PMU SWINC: Event Counter 30 Software Increment Position */
+#define PMU_SWINC_CNT30_Msk                  (1UL << PMU_SWINC_CNT30_Pos)                  /*!< PMU SWINC: Event Counter 30 Software Increment Mask */
+
+/** \brief PMU Control Register Definitions */
+
+#define PMU_CTRL_ENABLE_Pos                   0U                                           /*!< PMU CTRL: ENABLE Position */
+#define PMU_CTRL_ENABLE_Msk                  (1UL /*<< PMU_CTRL_ENABLE_Pos*/)              /*!< PMU CTRL: ENABLE Mask */
+
+#define PMU_CTRL_EVENTCNT_RESET_Pos           1U                                           /*!< PMU CTRL: Event Counter Reset Position */
+#define PMU_CTRL_EVENTCNT_RESET_Msk          (1UL << PMU_CTRL_EVENTCNT_RESET_Pos)          /*!< PMU CTRL: Event Counter Reset Mask */
+
+#define PMU_CTRL_CYCCNT_RESET_Pos             2U                                           /*!< PMU CTRL: Cycle Counter Reset Position */
+#define PMU_CTRL_CYCCNT_RESET_Msk            (1UL << PMU_CTRL_CYCCNT_RESET_Pos)            /*!< PMU CTRL: Cycle Counter Reset Mask */
+
+#define PMU_CTRL_CYCCNT_DISABLE_Pos           5U                                           /*!< PMU CTRL: Disable Cycle Counter Position */
+#define PMU_CTRL_CYCCNT_DISABLE_Msk          (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos)          /*!< PMU CTRL: Disable Cycle Counter Mask */
+
+#define PMU_CTRL_FRZ_ON_OV_Pos                9U                                           /*!< PMU CTRL: Freeze-on-overflow Position */
+#define PMU_CTRL_FRZ_ON_OV_Msk               (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos)         /*!< PMU CTRL: Freeze-on-overflow Mask */
+
+#define PMU_CTRL_TRACE_ON_OV_Pos              11U                                          /*!< PMU CTRL: Trace-on-overflow Position */
+#define PMU_CTRL_TRACE_ON_OV_Msk             (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos)       /*!< PMU CTRL: Trace-on-overflow Mask */
+
+/** \brief PMU Type Register Definitions */
+
+#define PMU_TYPE_NUM_CNTS_Pos                 0U                                           /*!< PMU TYPE: Number of Counters Position */
+#define PMU_TYPE_NUM_CNTS_Msk                (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/)         /*!< PMU TYPE: Number of Counters Mask */
+
+#define PMU_TYPE_SIZE_CNTS_Pos                8U                                           /*!< PMU TYPE: Size of Counters Position */
+#define PMU_TYPE_SIZE_CNTS_Msk               (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos)            /*!< PMU TYPE: Size of Counters Mask */
+
+#define PMU_TYPE_CYCCNT_PRESENT_Pos           14U                                          /*!< PMU TYPE: Cycle Counter Present Position */
+#define PMU_TYPE_CYCCNT_PRESENT_Msk          (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos)          /*!< PMU TYPE: Cycle Counter Present Mask */
+
+#define PMU_TYPE_FRZ_OV_SUPPORT_Pos           21U                                          /*!< PMU TYPE: Freeze-on-overflow Support Position */
+#define PMU_TYPE_FRZ_OV_SUPPORT_Msk          (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos)          /*!< PMU TYPE: Freeze-on-overflow Support Mask */
+
+#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos      23U                                          /*!< PMU TYPE: Trace-on-overflow Support Position */
+#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk     (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos)          /*!< PMU TYPE: Trace-on-overflow Support Mask */
+
+/** \brief PMU Authentication Status Register Definitions */
+
+#define PMU_AUTHSTATUS_NSID_Pos               0U                                           /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */
+#define PMU_AUTHSTATUS_NSID_Msk              (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/)        /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */
+
+#define PMU_AUTHSTATUS_NSNID_Pos              2U                                           /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */
+#define PMU_AUTHSTATUS_NSNID_Msk             (0x3UL << PMU_AUTHSTATUS_NSNID_Pos)           /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */
+
+#define PMU_AUTHSTATUS_SID_Pos                4U                                           /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */
+#define PMU_AUTHSTATUS_SID_Msk               (0x3UL << PMU_AUTHSTATUS_SID_Pos)             /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */
+
+#define PMU_AUTHSTATUS_SNID_Pos               6U                                           /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */
+#define PMU_AUTHSTATUS_SNID_Msk              (0x3UL << PMU_AUTHSTATUS_SNID_Pos)            /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */
+
+#define PMU_AUTHSTATUS_NSUID_Pos              16U                                          /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */
+#define PMU_AUTHSTATUS_NSUID_Msk             (0x3UL << PMU_AUTHSTATUS_NSUID_Pos)           /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */
+
+#define PMU_AUTHSTATUS_NSUNID_Pos             18U                                          /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */
+#define PMU_AUTHSTATUS_NSUNID_Msk            (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos)          /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */
+
+#define PMU_AUTHSTATUS_SUID_Pos               20U                                          /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */
+#define PMU_AUTHSTATUS_SUID_Msk              (0x3UL << PMU_AUTHSTATUS_SUID_Pos)            /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */
+
+#define PMU_AUTHSTATUS_SUNID_Pos              22U                                          /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */
+#define PMU_AUTHSTATUS_SUNID_Msk             (0x3UL << PMU_AUTHSTATUS_SUNID_Pos)           /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */
+
+
+/*@} end of group CMSIS_PMU */
+#endif
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
+  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
+  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
+  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
+        uint32_t RESERVED0[1];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_PXN_Pos                    4U                                            /*!< MPU RLAR: PXN Position */
+#define MPU_RLAR_PXN_Msk                   (1UL << MPU_RLAR_PXN_Pos)                      /*!< MPU RLAR: PXN Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (7UL << MPU_RLAR_AttrIndx_Pos)                 /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#else
+        uint32_t RESERVED0[3];
+#endif
+  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
+  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and VFP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+#define FPU_FPDSCR_FZ16_Pos                19U                                            /*!< FPDSCR: FZ16 bit Position */
+#define FPU_FPDSCR_FZ16_Msk                (1UL << FPU_FPDSCR_FZ16_Pos)                   /*!< FPDSCR: FZ16 bit Mask */
+
+#define FPU_FPDSCR_LTPSIZE_Pos             16U                                            /*!< FPDSCR: LTPSIZE bit Position */
+#define FPU_FPDSCR_LTPSIZE_Msk             (7UL << FPU_FPDSCR_LTPSIZE_Pos)                /*!< FPDSCR: LTPSIZE bit Mask */
+
+/* Media and VFP Feature Register 0 Definitions */
+#define FPU_MVFR0_FPRound_Pos              28U                                            /*!< MVFR0: FPRound bits Position */
+#define FPU_MVFR0_FPRound_Msk              (0xFUL << FPU_MVFR0_FPRound_Pos)               /*!< MVFR0: FPRound bits Mask */
+
+#define FPU_MVFR0_FPSqrt_Pos               20U                                            /*!< MVFR0: FPSqrt bits Position */
+#define FPU_MVFR0_FPSqrt_Msk               (0xFUL << FPU_MVFR0_FPSqrt_Pos)                 /*!< MVFR0: FPSqrt bits Mask */
+
+#define FPU_MVFR0_FPDivide_Pos             16U                                            /*!< MVFR0: FPDivide bits Position */
+#define FPU_MVFR0_FPDivide_Msk             (0xFUL << FPU_MVFR0_FPDivide_Pos)              /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FPDP_Pos                  8U                                            /*!< MVFR0: FPDP bits Position */
+#define FPU_MVFR0_FPDP_Msk                 (0xFUL << FPU_MVFR0_FPDP_Pos)                  /*!< MVFR0: FPDP bits Mask */
+
+#define FPU_MVFR0_FPSP_Pos                  4U                                            /*!< MVFR0: FPSP bits Position */
+#define FPU_MVFR0_FPSP_Msk                 (0xFUL << FPU_MVFR0_FPSP_Pos)                  /*!< MVFR0: FPSP bits Mask */
+
+#define FPU_MVFR0_SIMDReg_Pos               0U                                            /*!< MVFR0: SIMDReg bits Position */
+#define FPU_MVFR0_SIMDReg_Msk              (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/)           /*!< MVFR0: SIMDReg bits Mask */
+
+/* Media and VFP Feature Register 1 Definitions */
+#define FPU_MVFR1_FMAC_Pos                 28U                                            /*!< MVFR1: FMAC bits Position */
+#define FPU_MVFR1_FMAC_Msk                 (0xFUL << FPU_MVFR1_FMAC_Pos)                  /*!< MVFR1: FMAC bits Mask */
+
+#define FPU_MVFR1_FPHP_Pos                 24U                                            /*!< MVFR1: FPHP bits Position */
+#define FPU_MVFR1_FPHP_Msk                 (0xFUL << FPU_MVFR1_FPHP_Pos)                  /*!< MVFR1: FPHP bits Mask */
+
+#define FPU_MVFR1_FP16_Pos                 20U                                            /*!< MVFR1: FP16 bits Position */
+#define FPU_MVFR1_FP16_Msk                 (0xFUL << FPU_MVFR1_FP16_Pos)                  /*!< MVFR1: FP16 bits Mask */
+
+#define FPU_MVFR1_MVE_Pos                   8U                                            /*!< MVFR1: MVE bits Position */
+#define FPU_MVFR1_MVE_Msk                  (0xFUL << FPU_MVFR1_MVE_Pos)                   /*!< MVFR1: MVE bits Mask */
+
+#define FPU_MVFR1_FPDNaN_Pos                4U                                            /*!< MVFR1: FPDNaN bits Position */
+#define FPU_MVFR1_FPDNaN_Msk               (0xFUL << FPU_MVFR1_FPDNaN_Pos)                /*!< MVFR1: FPDNaN bits Mask */
+
+#define FPU_MVFR1_FPFtZ_Pos                 0U                                            /*!< MVFR1: FPFtZ bits Position */
+#define FPU_MVFR1_FPFtZ_Msk                (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/)             /*!< MVFR1: FPFtZ bits Mask */
+
+/* Media and VFP Feature Register 2 Definitions */
+#define FPU_MVFR2_FPMisc_Pos                4U                                            /*!< MVFR2: FPMisc bits Position */
+#define FPU_MVFR2_FPMisc_Msk               (0xFUL << FPU_MVFR2_FPMisc_Pos)                /*!< MVFR2: FPMisc bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  \deprecated Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+  __OM  uint32_t DSCEMCR;                /*!< Offset: 0x010 ( /W)  Debug Set Clear Exception and Monitor Control Register */
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_FPD_Pos          23U                                            /*!< \deprecated CoreDebug DHCSR: S_FPD Position */
+#define CoreDebug_DHCSR_S_FPD_Msk          (1UL << CoreDebug_DHCSR_S_FPD_Pos)             /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */
+
+#define CoreDebug_DHCSR_S_SUIDE_Pos        22U                                            /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */
+#define CoreDebug_DHCSR_S_SUIDE_Msk        (1UL << CoreDebug_DHCSR_S_SUIDE_Pos)           /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */
+
+#define CoreDebug_DHCSR_S_NSUIDE_Pos       21U                                            /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */
+#define CoreDebug_DHCSR_S_NSUIDE_Msk       (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos)          /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */
+
+#define CoreDebug_DHCSR_S_SDE_Pos          20U                                            /*!< \deprecated CoreDebug DHCSR: S_SDE Position */
+#define CoreDebug_DHCSR_S_SDE_Msk          (1UL << CoreDebug_DHCSR_S_SDE_Pos)             /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< \deprecated CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_PMOV_Pos          6U                                            /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */
+#define CoreDebug_DHCSR_C_PMOV_Msk         (1UL << CoreDebug_DHCSR_C_PMOV_Pos)            /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< \deprecated CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< \deprecated CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< \deprecated CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< \deprecated CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< \deprecated CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< \deprecated CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Set Clear Exception and Monitor Control Register Definitions */
+#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos  19U                                            /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */
+#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk  (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos)     /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */
+
+#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U                                            /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */
+#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos)    /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */
+
+#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos   3U                                            /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */
+#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk  (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos)     /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */
+
+#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos  1U                                            /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */
+#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos)    /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_UIDEN_Pos      10U                                            /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */
+#define CoreDebug_DAUTHCTRL_UIDEN_Msk      (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos)         /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos     9U                                            /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */
+#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk    (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos)       /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_FSDMA_Pos       8U                                            /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */
+#define CoreDebug_DAUTHCTRL_FSDMA_Msk      (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos)         /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< \deprecated CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< \deprecated CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DCB       Debug Control Block
+  \brief    Type definitions for the Debug Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Debug Control Block Registers (DCB).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+  __OM  uint32_t DSCEMCR;                /*!< Offset: 0x010 ( /W)  Debug Set Clear Exception and Monitor Control Register */
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} DCB_Type;
+
+/* DHCSR, Debug Halting Control and Status Register Definitions */
+#define DCB_DHCSR_DBGKEY_Pos               16U                                            /*!< DCB DHCSR: Debug key Position */
+#define DCB_DHCSR_DBGKEY_Msk               (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)             /*!< DCB DHCSR: Debug key Mask */
+
+#define DCB_DHCSR_S_RESTART_ST_Pos         26U                                            /*!< DCB DHCSR: Restart sticky status Position */
+#define DCB_DHCSR_S_RESTART_ST_Msk         (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)          /*!< DCB DHCSR: Restart sticky status Mask */
+
+#define DCB_DHCSR_S_RESET_ST_Pos           25U                                            /*!< DCB DHCSR: Reset sticky status Position */
+#define DCB_DHCSR_S_RESET_ST_Msk           (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)            /*!< DCB DHCSR: Reset sticky status Mask */
+
+#define DCB_DHCSR_S_RETIRE_ST_Pos          24U                                            /*!< DCB DHCSR: Retire sticky status Position */
+#define DCB_DHCSR_S_RETIRE_ST_Msk          (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)           /*!< DCB DHCSR: Retire sticky status Mask */
+
+#define DCB_DHCSR_S_FPD_Pos                23U                                            /*!< DCB DHCSR: Floating-point registers Debuggable Position */
+#define DCB_DHCSR_S_FPD_Msk                (0x1UL << DCB_DHCSR_S_FPD_Pos)                 /*!< DCB DHCSR: Floating-point registers Debuggable Mask */
+
+#define DCB_DHCSR_S_SUIDE_Pos              22U                                            /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */
+#define DCB_DHCSR_S_SUIDE_Msk              (0x1UL << DCB_DHCSR_S_SUIDE_Pos)               /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */
+
+#define DCB_DHCSR_S_NSUIDE_Pos             21U                                            /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */
+#define DCB_DHCSR_S_NSUIDE_Msk             (0x1UL << DCB_DHCSR_S_NSUIDE_Pos)              /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */
+
+#define DCB_DHCSR_S_SDE_Pos                20U                                            /*!< DCB DHCSR: Secure debug enabled Position */
+#define DCB_DHCSR_S_SDE_Msk                (0x1UL << DCB_DHCSR_S_SDE_Pos)                 /*!< DCB DHCSR: Secure debug enabled Mask */
+
+#define DCB_DHCSR_S_LOCKUP_Pos             19U                                            /*!< DCB DHCSR: Lockup status Position */
+#define DCB_DHCSR_S_LOCKUP_Msk             (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)              /*!< DCB DHCSR: Lockup status Mask */
+
+#define DCB_DHCSR_S_SLEEP_Pos              18U                                            /*!< DCB DHCSR: Sleeping status Position */
+#define DCB_DHCSR_S_SLEEP_Msk              (0x1UL << DCB_DHCSR_S_SLEEP_Pos)               /*!< DCB DHCSR: Sleeping status Mask */
+
+#define DCB_DHCSR_S_HALT_Pos               17U                                            /*!< DCB DHCSR: Halted status Position */
+#define DCB_DHCSR_S_HALT_Msk               (0x1UL << DCB_DHCSR_S_HALT_Pos)                /*!< DCB DHCSR: Halted status Mask */
+
+#define DCB_DHCSR_S_REGRDY_Pos             16U                                            /*!< DCB DHCSR: Register ready status Position */
+#define DCB_DHCSR_S_REGRDY_Msk             (0x1UL << DCB_DHCSR_S_REGRDY_Pos)              /*!< DCB DHCSR: Register ready status Mask */
+
+#define DCB_DHCSR_C_PMOV_Pos                6U                                            /*!< DCB DHCSR: Halt on PMU overflow control Position */
+#define DCB_DHCSR_C_PMOV_Msk               (0x1UL << DCB_DHCSR_C_PMOV_Pos)                /*!< DCB DHCSR: Halt on PMU overflow control Mask */
+
+#define DCB_DHCSR_C_SNAPSTALL_Pos           5U                                            /*!< DCB DHCSR: Snap stall control Position */
+#define DCB_DHCSR_C_SNAPSTALL_Msk          (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)           /*!< DCB DHCSR: Snap stall control Mask */
+
+#define DCB_DHCSR_C_MASKINTS_Pos            3U                                            /*!< DCB DHCSR: Mask interrupts control Position */
+#define DCB_DHCSR_C_MASKINTS_Msk           (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)            /*!< DCB DHCSR: Mask interrupts control Mask */
+
+#define DCB_DHCSR_C_STEP_Pos                2U                                            /*!< DCB DHCSR: Step control Position */
+#define DCB_DHCSR_C_STEP_Msk               (0x1UL << DCB_DHCSR_C_STEP_Pos)                /*!< DCB DHCSR: Step control Mask */
+
+#define DCB_DHCSR_C_HALT_Pos                1U                                            /*!< DCB DHCSR: Halt control Position */
+#define DCB_DHCSR_C_HALT_Msk               (0x1UL << DCB_DHCSR_C_HALT_Pos)                /*!< DCB DHCSR: Halt control Mask */
+
+#define DCB_DHCSR_C_DEBUGEN_Pos             0U                                            /*!< DCB DHCSR: Debug enable control Position */
+#define DCB_DHCSR_C_DEBUGEN_Msk            (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)         /*!< DCB DHCSR: Debug enable control Mask */
+
+/* DCRSR, Debug Core Register Select Register Definitions */
+#define DCB_DCRSR_REGWnR_Pos               16U                                            /*!< DCB DCRSR: Register write/not-read Position */
+#define DCB_DCRSR_REGWnR_Msk               (0x1UL << DCB_DCRSR_REGWnR_Pos)                /*!< DCB DCRSR: Register write/not-read Mask */
+
+#define DCB_DCRSR_REGSEL_Pos                0U                                            /*!< DCB DCRSR: Register selector Position */
+#define DCB_DCRSR_REGSEL_Msk               (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)           /*!< DCB DCRSR: Register selector Mask */
+
+/* DCRDR, Debug Core Register Data Register Definitions */
+#define DCB_DCRDR_DBGTMP_Pos                0U                                            /*!< DCB DCRDR: Data temporary buffer Position */
+#define DCB_DCRDR_DBGTMP_Msk               (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)     /*!< DCB DCRDR: Data temporary buffer Mask */
+
+/* DEMCR, Debug Exception and Monitor Control Register Definitions */
+#define DCB_DEMCR_TRCENA_Pos               24U                                            /*!< DCB DEMCR: Trace enable Position */
+#define DCB_DEMCR_TRCENA_Msk               (0x1UL << DCB_DEMCR_TRCENA_Pos)                /*!< DCB DEMCR: Trace enable Mask */
+
+#define DCB_DEMCR_MONPRKEY_Pos             23U                                            /*!< DCB DEMCR: Monitor pend req key Position */
+#define DCB_DEMCR_MONPRKEY_Msk             (0x1UL << DCB_DEMCR_MONPRKEY_Pos)              /*!< DCB DEMCR: Monitor pend req key Mask */
+
+#define DCB_DEMCR_UMON_EN_Pos              21U                                            /*!< DCB DEMCR: Unprivileged monitor enable Position */
+#define DCB_DEMCR_UMON_EN_Msk              (0x1UL << DCB_DEMCR_UMON_EN_Pos)               /*!< DCB DEMCR: Unprivileged monitor enable Mask */
+
+#define DCB_DEMCR_SDME_Pos                 20U                                            /*!< DCB DEMCR: Secure DebugMonitor enable Position */
+#define DCB_DEMCR_SDME_Msk                 (0x1UL << DCB_DEMCR_SDME_Pos)                  /*!< DCB DEMCR: Secure DebugMonitor enable Mask */
+
+#define DCB_DEMCR_MON_REQ_Pos              19U                                            /*!< DCB DEMCR: Monitor request Position */
+#define DCB_DEMCR_MON_REQ_Msk              (0x1UL << DCB_DEMCR_MON_REQ_Pos)               /*!< DCB DEMCR: Monitor request Mask */
+
+#define DCB_DEMCR_MON_STEP_Pos             18U                                            /*!< DCB DEMCR: Monitor step Position */
+#define DCB_DEMCR_MON_STEP_Msk             (0x1UL << DCB_DEMCR_MON_STEP_Pos)              /*!< DCB DEMCR: Monitor step Mask */
+
+#define DCB_DEMCR_MON_PEND_Pos             17U                                            /*!< DCB DEMCR: Monitor pend Position */
+#define DCB_DEMCR_MON_PEND_Msk             (0x1UL << DCB_DEMCR_MON_PEND_Pos)              /*!< DCB DEMCR: Monitor pend Mask */
+
+#define DCB_DEMCR_MON_EN_Pos               16U                                            /*!< DCB DEMCR: Monitor enable Position */
+#define DCB_DEMCR_MON_EN_Msk               (0x1UL << DCB_DEMCR_MON_EN_Pos)                /*!< DCB DEMCR: Monitor enable Mask */
+
+#define DCB_DEMCR_VC_SFERR_Pos             11U                                            /*!< DCB DEMCR: Vector Catch SecureFault Position */
+#define DCB_DEMCR_VC_SFERR_Msk             (0x1UL << DCB_DEMCR_VC_SFERR_Pos)              /*!< DCB DEMCR: Vector Catch SecureFault Mask */
+
+#define DCB_DEMCR_VC_HARDERR_Pos           10U                                            /*!< DCB DEMCR: Vector Catch HardFault errors Position */
+#define DCB_DEMCR_VC_HARDERR_Msk           (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)            /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
+
+#define DCB_DEMCR_VC_INTERR_Pos             9U                                            /*!< DCB DEMCR: Vector Catch interrupt errors Position */
+#define DCB_DEMCR_VC_INTERR_Msk            (0x1UL << DCB_DEMCR_VC_INTERR_Pos)             /*!< DCB DEMCR: Vector Catch interrupt errors Mask */
+
+#define DCB_DEMCR_VC_BUSERR_Pos             8U                                            /*!< DCB DEMCR: Vector Catch BusFault errors Position */
+#define DCB_DEMCR_VC_BUSERR_Msk            (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)             /*!< DCB DEMCR: Vector Catch BusFault errors Mask */
+
+#define DCB_DEMCR_VC_STATERR_Pos            7U                                            /*!< DCB DEMCR: Vector Catch state errors Position */
+#define DCB_DEMCR_VC_STATERR_Msk           (0x1UL << DCB_DEMCR_VC_STATERR_Pos)            /*!< DCB DEMCR: Vector Catch state errors Mask */
+
+#define DCB_DEMCR_VC_CHKERR_Pos             6U                                            /*!< DCB DEMCR: Vector Catch check errors Position */
+#define DCB_DEMCR_VC_CHKERR_Msk            (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)             /*!< DCB DEMCR: Vector Catch check errors Mask */
+
+#define DCB_DEMCR_VC_NOCPERR_Pos            5U                                            /*!< DCB DEMCR: Vector Catch NOCP errors Position */
+#define DCB_DEMCR_VC_NOCPERR_Msk           (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)            /*!< DCB DEMCR: Vector Catch NOCP errors Mask */
+
+#define DCB_DEMCR_VC_MMERR_Pos              4U                                            /*!< DCB DEMCR: Vector Catch MemManage errors Position */
+#define DCB_DEMCR_VC_MMERR_Msk             (0x1UL << DCB_DEMCR_VC_MMERR_Pos)              /*!< DCB DEMCR: Vector Catch MemManage errors Mask */
+
+#define DCB_DEMCR_VC_CORERESET_Pos          0U                                            /*!< DCB DEMCR: Vector Catch Core reset Position */
+#define DCB_DEMCR_VC_CORERESET_Msk         (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)      /*!< DCB DEMCR: Vector Catch Core reset Mask */
+
+/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */
+#define DCB_DSCEMCR_CLR_MON_REQ_Pos        19U                                            /*!< DCB DSCEMCR: Clear monitor request Position */
+#define DCB_DSCEMCR_CLR_MON_REQ_Msk        (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos)         /*!< DCB DSCEMCR: Clear monitor request Mask */
+
+#define DCB_DSCEMCR_CLR_MON_PEND_Pos       17U                                            /*!< DCB DSCEMCR: Clear monitor pend Position */
+#define DCB_DSCEMCR_CLR_MON_PEND_Msk       (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos)        /*!< DCB DSCEMCR: Clear monitor pend Mask */
+
+#define DCB_DSCEMCR_SET_MON_REQ_Pos         3U                                            /*!< DCB DSCEMCR: Set monitor request Position */
+#define DCB_DSCEMCR_SET_MON_REQ_Msk        (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos)         /*!< DCB DSCEMCR: Set monitor request Mask */
+
+#define DCB_DSCEMCR_SET_MON_PEND_Pos        1U                                            /*!< DCB DSCEMCR: Set monitor pend Position */
+#define DCB_DSCEMCR_SET_MON_PEND_Msk       (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos)        /*!< DCB DSCEMCR: Set monitor pend Mask */
+
+/* DAUTHCTRL, Debug Authentication Control Register Definitions */
+#define DCB_DAUTHCTRL_UIDEN_Pos            10U                                            /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */
+#define DCB_DAUTHCTRL_UIDEN_Msk            (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos)             /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */
+
+#define DCB_DAUTHCTRL_UIDAPEN_Pos           9U                                            /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */
+#define DCB_DAUTHCTRL_UIDAPEN_Msk          (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos)           /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */
+
+#define DCB_DAUTHCTRL_FSDMA_Pos             8U                                            /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */
+#define DCB_DAUTHCTRL_FSDMA_Msk            (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos)             /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */
+
+#define DCB_DAUTHCTRL_INTSPNIDEN_Pos        3U                                            /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPNIDEN_Msk       (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)        /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPNIDENSEL_Pos        2U                                            /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPNIDENSEL_Msk       (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)        /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */
+
+#define DCB_DAUTHCTRL_INTSPIDEN_Pos         1U                                            /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPIDEN_Msk        (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)         /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPIDENSEL_Pos         0U                                            /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPIDENSEL_Msk        (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)     /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */
+
+/* DSCSR, Debug Security Control and Status Register Definitions */
+#define DCB_DSCSR_CDSKEY_Pos               17U                                            /*!< DCB DSCSR: CDS write-enable key Position */
+#define DCB_DSCSR_CDSKEY_Msk               (0x1UL << DCB_DSCSR_CDSKEY_Pos)                /*!< DCB DSCSR: CDS write-enable key Mask */
+
+#define DCB_DSCSR_CDS_Pos                  16U                                            /*!< DCB DSCSR: Current domain Secure Position */
+#define DCB_DSCSR_CDS_Msk                  (0x1UL << DCB_DSCSR_CDS_Pos)                   /*!< DCB DSCSR: Current domain Secure Mask */
+
+#define DCB_DSCSR_SBRSEL_Pos                1U                                            /*!< DCB DSCSR: Secure banked register select Position */
+#define DCB_DSCSR_SBRSEL_Msk               (0x1UL << DCB_DSCSR_SBRSEL_Pos)                /*!< DCB DSCSR: Secure banked register select Mask */
+
+#define DCB_DSCSR_SBRSELEN_Pos              0U                                            /*!< DCB DSCSR: Secure banked register select enable Position */
+#define DCB_DSCSR_SBRSELEN_Msk             (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)          /*!< DCB DSCSR: Secure banked register select enable Mask */
+
+/*@} end of group CMSIS_DCB */
+
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DIB       Debug Identification Block
+  \brief    Type definitions for the Debug Identification Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Debug Identification Block Registers (DIB).
+ */
+typedef struct
+{
+  __OM  uint32_t DLAR;                   /*!< Offset: 0x000 ( /W)  SCS Software Lock Access Register */
+  __IM  uint32_t DLSR;                   /*!< Offset: 0x004 (R/ )  SCS Software Lock Status Register */
+  __IM  uint32_t DAUTHSTATUS;            /*!< Offset: 0x008 (R/ )  Debug Authentication Status Register */
+  __IM  uint32_t DDEVARCH;               /*!< Offset: 0x00C (R/ )  SCS Device Architecture Register */
+  __IM  uint32_t DDEVTYPE;               /*!< Offset: 0x010 (R/ )  SCS Device Type Register */
+} DIB_Type;
+
+/* DLAR, SCS Software Lock Access Register Definitions */
+#define DIB_DLAR_KEY_Pos                    0U                                            /*!< DIB DLAR: KEY Position */
+#define DIB_DLAR_KEY_Msk                   (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */)        /*!< DIB DLAR: KEY Mask */
+
+/* DLSR, SCS Software Lock Status Register Definitions */
+#define DIB_DLSR_nTT_Pos                    2U                                            /*!< DIB DLSR: Not thirty-two bit Position */
+#define DIB_DLSR_nTT_Msk                   (0x1UL << DIB_DLSR_nTT_Pos )                   /*!< DIB DLSR: Not thirty-two bit Mask */
+
+#define DIB_DLSR_SLK_Pos                    1U                                            /*!< DIB DLSR: Software Lock status Position */
+#define DIB_DLSR_SLK_Msk                   (0x1UL << DIB_DLSR_SLK_Pos )                   /*!< DIB DLSR: Software Lock status Mask */
+
+#define DIB_DLSR_SLI_Pos                    0U                                            /*!< DIB DLSR: Software Lock implemented Position */
+#define DIB_DLSR_SLI_Msk                   (0x1UL /*<< DIB_DLSR_SLI_Pos*/)                /*!< DIB DLSR: Software Lock implemented Mask */
+
+/* DAUTHSTATUS, Debug Authentication Status Register Definitions */
+#define DIB_DAUTHSTATUS_SUNID_Pos          22U                                            /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */
+#define DIB_DAUTHSTATUS_SUNID_Msk          (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos )          /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */
+
+#define DIB_DAUTHSTATUS_SUID_Pos           20U                                            /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */
+#define DIB_DAUTHSTATUS_SUID_Msk           (0x3UL << DIB_DAUTHSTATUS_SUID_Pos )           /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */
+
+#define DIB_DAUTHSTATUS_NSUNID_Pos         18U                                            /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */
+#define DIB_DAUTHSTATUS_NSUNID_Msk         (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos )         /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */
+
+#define DIB_DAUTHSTATUS_NSUID_Pos          16U                                            /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */
+#define DIB_DAUTHSTATUS_NSUID_Msk          (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos )          /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */
+
+#define DIB_DAUTHSTATUS_SNID_Pos            6U                                            /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_SNID_Msk           (0x3UL << DIB_DAUTHSTATUS_SNID_Pos )           /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_SID_Pos             4U                                            /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_SID_Msk            (0x3UL << DIB_DAUTHSTATUS_SID_Pos )            /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSNID_Pos           2U                                            /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSNID_Msk          (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos )          /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSID_Pos            0U                                            /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSID_Msk           (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/)        /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */
+
+/* DDEVARCH, SCS Device Architecture Register Definitions */
+#define DIB_DDEVARCH_ARCHITECT_Pos         21U                                            /*!< DIB DDEVARCH: Architect Position */
+#define DIB_DDEVARCH_ARCHITECT_Msk         (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos )       /*!< DIB DDEVARCH: Architect Mask */
+
+#define DIB_DDEVARCH_PRESENT_Pos           20U                                            /*!< DIB DDEVARCH: DEVARCH Present Position */
+#define DIB_DDEVARCH_PRESENT_Msk           (0x1FUL << DIB_DDEVARCH_PRESENT_Pos )          /*!< DIB DDEVARCH: DEVARCH Present Mask */
+
+#define DIB_DDEVARCH_REVISION_Pos          16U                                            /*!< DIB DDEVARCH: Revision Position */
+#define DIB_DDEVARCH_REVISION_Msk          (0xFUL << DIB_DDEVARCH_REVISION_Pos )          /*!< DIB DDEVARCH: Revision Mask */
+
+#define DIB_DDEVARCH_ARCHVER_Pos           12U                                            /*!< DIB DDEVARCH: Architecture Version Position */
+#define DIB_DDEVARCH_ARCHVER_Msk           (0xFUL << DIB_DDEVARCH_ARCHVER_Pos )           /*!< DIB DDEVARCH: Architecture Version Mask */
+
+#define DIB_DDEVARCH_ARCHPART_Pos           0U                                            /*!< DIB DDEVARCH: Architecture Part Position */
+#define DIB_DDEVARCH_ARCHPART_Msk          (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/)     /*!< DIB DDEVARCH: Architecture Part Mask */
+
+/* DDEVTYPE, SCS Device Type Register Definitions */
+#define DIB_DDEVTYPE_SUB_Pos                4U                                            /*!< DIB DDEVTYPE: Sub-type Position */
+#define DIB_DDEVTYPE_SUB_Msk               (0xFUL << DIB_DDEVTYPE_SUB_Pos )               /*!< DIB DDEVTYPE: Sub-type Mask */
+
+#define DIB_DDEVTYPE_MAJOR_Pos              0U                                            /*!< DIB DDEVTYPE: Major type Position */
+#define DIB_DDEVTYPE_MAJOR_Msk             (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/)          /*!< DIB DDEVTYPE: Major type Mask */
+
+
+/*@} end of group CMSIS_DIB */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define MEMSYSCTL_BASE      (0xE001E000UL)                             /*!< Memory System Control Base Address */
+  #define ERRBNK_BASE         (0xE001E100UL)                             /*!< Error Banking Base Address */
+  #define PWRMODCTL_BASE      (0xE001E300UL)                             /*!< Power Mode Control Base Address */
+  #define EWIC_BASE           (0xE001E400UL)                             /*!< External Wakeup Interrupt Controller Base Address */
+  #define PRCCFGINF_BASE      (0xE001E700UL)                             /*!< Processor Configuration Information Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< \deprecated Core Debug Base Address */
+  #define DCB_BASE            (0xE000EDF0UL)                             /*!< DCB Base Address */
+  #define DIB_BASE            (0xE000EFB0UL)                             /*!< DIB Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+  #define ICB                 ((ICB_Type       *)     SCS_BASE         ) /*!< System control Register not in SCB */
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define MEMSYSCTL           ((MemSysCtl_Type *)     MEMSYSCTL_BASE   ) /*!< Memory System Control configuration struct */
+  #define ERRBNK              ((ErrBnk_Type    *)     ERRBNK_BASE      ) /*!< Error Banking configuration struct */
+  #define PWRMODCTL           ((PwrModCtl_Type *)     PWRMODCTL_BASE   ) /*!< Power Mode Control configuration struct */
+  #define EWIC                ((EWIC_Type      *)     EWIC_BASE        ) /*!< EWIC configuration struct */
+  #define PRCCFGINF           ((PrcCfgInf_Type *)     PRCCFGINF_BASE   ) /*!< Processor Configuration Information configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< \deprecated Core Debug configuration struct */
+  #define DCB                 ((DCB_Type       *)     DCB_BASE         ) /*!< DCB configuration struct */
+  #define DIB                 ((DIB_Type       *)     DIB_BASE         ) /*!< DIB configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)
+    #define PMU_BASE          (0xE0003000UL)                             /*!< PMU Base Address */
+    #define PMU               ((PMU_Type       *)     PMU_BASE         ) /*!< PMU configuration struct */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
+  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< \deprecated Core Debug Base Address           (non-secure address space) */
+  #define DCB_BASE_NS         (0xE002EDF0UL)                             /*!< DCB Base Address                  (non-secure address space) */
+  #define DIB_BASE_NS         (0xE002EFB0UL)                             /*!< DIB Base Address                  (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define ICB_NS              ((ICB_Type       *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct   (non-secure address space) */
+  #define DCB_NS              ((DCB_Type       *)     DCB_BASE_NS      ) /*!< DCB configuration struct          (non-secure address space) */
+  #define DIB_NS              ((DIB_Type       *)     DIB_BASE_NS      ) /*!< DIB configuration struct          (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
+  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_register_aliases     Backwards Compatibility Aliases
+  \brief      Register alias definitions for backwards compatibility.
+  @{
+ */
+
+/*@} */
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
+#define EXC_RETURN_SPSEL           (0x00000004UL)     /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP           */
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
+#else
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
+#endif
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    __COMPILER_BARRIER();
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __COMPILER_BARRIER();
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+  __DSB();
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Priority Grouping (non-secure)
+  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB_NS->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)                      );              /* Insert write key and priority group */
+  SCB_NS->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping (non-secure)
+  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  PMU functions and events  #################################### */
+
+#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)
+
+#include "pmu_armv8.h"
+
+/**
+  \brief   Cortex-M85 PMU events
+  \note    Architectural PMU events can be found in pmu_armv8.h
+*/
+
+#define ARMCM85_PMU_ECC_ERR                          0xC000             /*!< One or more Error Correcting Code (ECC) errors detected */
+#define ARMCM85_PMU_ECC_ERR_MBIT                     0xC001             /*!< One or more multi-bit ECC errors detected */
+#define ARMCM85_PMU_ECC_ERR_DCACHE                   0xC010             /*!< One or more ECC errors in the data cache */
+#define ARMCM85_PMU_ECC_ERR_ICACHE                   0xC011             /*!< One or more ECC errors in the instruction cache */
+#define ARMCM85_PMU_ECC_ERR_MBIT_DCACHE              0xC012             /*!< One or more multi-bit ECC errors in the data cache */
+#define ARMCM85_PMU_ECC_ERR_MBIT_ICACHE              0xC013             /*!< One or more multi-bit ECC errors in the instruction cache */
+#define ARMCM85_PMU_ECC_ERR_DTCM                     0xC020             /*!< One or more ECC errors in the Data Tightly Coupled Memory (DTCM) */
+#define ARMCM85_PMU_ECC_ERR_ITCM                     0xC021             /*!< One or more ECC errors in the Instruction Tightly Coupled Memory (ITCM) */
+#define ARMCM85_PMU_ECC_ERR_MBIT_DTCM                0xC022             /*!< One or more multi-bit ECC errors in the DTCM */
+#define ARMCM85_PMU_ECC_ERR_MBIT_ITCM                0xC023             /*!< One or more multi-bit ECC errors in the ITCM */
+#define ARMCM85_PMU_PF_LINEFILL                      0xC100             /*!< The prefetcher starts a line-fill */
+#define ARMCM85_PMU_PF_CANCEL                        0xC101             /*!< The prefetcher stops prefetching */
+#define ARMCM85_PMU_PF_DROP_LINEFILL                 0xC102             /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */
+#define ARMCM85_PMU_NWAMODE_ENTER                    0xC200             /*!< No write-allocate mode entry */
+#define ARMCM85_PMU_NWAMODE                          0xC201             /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */
+#define ARMCM85_PMU_SAHB_ACCESS                      0xC300             /*!< Read or write access on the S-AHB interface to the TCM */
+#define ARMCM85_PMU_PAHB_ACCESS                      0xC301             /*!< Read or write access on the P-AHB write interface */
+#define ARMCM85_PMU_AXI_WRITE_ACCESS                 0xC302             /*!< Any beat access to M-AXI write interface */
+#define ARMCM85_PMU_AXI_READ_ACCESS                  0xC303             /*!< Any beat access to M-AXI read interface */
+#define ARMCM85_PMU_DOSTIMEOUT_DOUBLE                0xC400             /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */
+#define ARMCM85_PMU_DOSTIMEOUT_TRIPLE                0xC401             /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+/* ##########################  MVE functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_MveFunctions MVE Functions
+  \brief    Function that provides MVE type.
+  @{
+ */
+
+/**
+  \brief   get MVE type
+  \details returns the MVE type
+  \returns
+   - \b  0: No Vector Extension (MVE)
+   - \b  1: Integer Vector Extension (MVE-I)
+   - \b  2: Floating-point Vector Extension (MVE-F)
+ */
+__STATIC_INLINE uint32_t SCB_GetMVEType(void)
+{
+  const uint32_t mvfr1 = FPU->MVFR1;
+  if      ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos))
+  {
+    return 2U;
+  }
+  else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos))
+  {
+    return 1U;
+  }
+  else
+  {
+    return 0U;
+  }
+}
+
+
+/*@} end of CMSIS_Core_MveFunctions */
+
+
+/* ##########################  Cache functions  #################################### */
+
+#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \
+     (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)))
+#include "cachel1_armv7.h"
+#endif
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+/* ###################  PAC Key functions  ########################### */
+
+#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1))
+#include "pac_armv81.h"
+#endif
+
+
+/* ##################################    Debug Control function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_DCBFunctions Debug Control Functions
+  \brief    Functions that access the Debug Control Block.
+  @{
+ */
+
+
+/**
+  \brief   Set Debug Authentication Control Register
+  \details writes to Debug Authentication Control register.
+  \param [in]  value  value to be writen.
+ */
+__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
+{
+    __DSB();
+    __ISB();
+    DCB->DAUTHCTRL = value;
+    __DSB();
+    __ISB();
+}
+
+
+/**
+  \brief   Get Debug Authentication Control Register
+  \details Reads Debug Authentication Control register.
+  \return             Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
+{
+    return (DCB->DAUTHCTRL);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Debug Authentication Control Register (non-secure)
+  \details writes to non-secure Debug Authentication Control register when in secure state.
+  \param [in]  value  value to be writen
+ */
+__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
+{
+    __DSB();
+    __ISB();
+    DCB_NS->DAUTHCTRL = value;
+    __DSB();
+    __ISB();
+}
+
+
+/**
+  \brief   Get Debug Authentication Control Register (non-secure)
+  \details Reads non-secure Debug Authentication Control register when in secure state.
+  \return             Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
+{
+    return (DCB_NS->DAUTHCTRL);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ##################################    Debug Identification function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions
+  \brief    Functions that access the Debug Identification Block.
+  @{
+ */
+
+
+/**
+  \brief   Get Debug Authentication Status Register
+  \details Reads Debug Authentication Status register.
+  \return             Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
+{
+    return (DIB->DAUTHSTATUS);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Debug Authentication Status Register (non-secure)
+  \details Reads non-secure Debug Authentication Status register when in secure state.
+  \return             Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
+{
+    return (DIB_NS->DAUTHSTATUS);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM85_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

CMSIS/Core/Include/core_starmc1.h

@@ -0,0 +1,3592 @@
+/**************************************************************************//**
+ * @file     core_starmc1.h
+ * @brief    CMSIS ArmChina STAR-MC1 Core Peripheral Access Layer Header File
+ * @version  V1.0.2
+ * @date     07. April 2022
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. 
+ * Copyright (c) 2018-2022 Arm China. 
+ * All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header                   /* treat file as system include file */
+#elif defined ( __GNUC__ )
+  #pragma GCC diagnostic ignored "-Wpedantic"   /* disable pedantic warning due to unnamed structs/unions */
+#endif
+
+#ifndef __CORE_STAR_H_GENERIC
+#define __CORE_STAR_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup STAR-MC1
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/* Macro Define for STAR-MC1 */
+#define __STAR_MC                 (1U)                                       /*!< STAR-MC Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined (__TARGET_FPU_VFP)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined (__ARM_FP)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined (__ARMVFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined (__TI_VFP_SUPPORT__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined (__FPU_VFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_STAR_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_STAR_H_DEPENDANT
+#define __CORE_STAR_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __STAR_REV
+    #define __STAR_REV                0x0000U
+    #warning "__STAR_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DSP_PRESENT
+    #define __DSP_PRESENT             0U
+    #warning "__DSP_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ICACHE_PRESENT
+    #define __ICACHE_PRESENT          0U
+    #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DCACHE_PRESENT
+    #define __DCACHE_PRESENT          0U
+    #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DTCM_PRESENT
+    #define __DTCM_PRESENT            0U
+    #warning "__DTCM_PRESENT        not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group STAR-MC1 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for STAR-MC1 processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */
+    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */
+    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED6[580U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[5U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
+        uint32_t RESERVED_ADD1[21U];      
+  __IOM uint32_t SFSR;                   /*!< Offset: 0x0E4 (R/W)  Secure Fault Status Register */
+  __IOM uint32_t SFAR;                   /*!< Offset: 0x0E8 (R/W)  Secure Fault Address Register */
+        uint32_t RESERVED3[69U];
+  __OM  uint32_t STIR;                   /*!< Offset: F00-D00=0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+} SCB_Type;
+
+typedef struct
+{
+  __IOM uint32_t CACR;				       /*!< Offset: 0x0 (R/W)  L1 Cache Control Register */
+  __IOM uint32_t ITCMCR;				   /*!< Offset: 0x10 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+  __IOM uint32_t DTCMCR;				   /*!< Offset: 0x14 (R/W)  Data Tightly-Coupled Memory Control Registers */ 
+}EMSS_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_CFSR_MEMFAULTSR_Pos + 7U)                 /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_CFSR_MEMFAULTSR_Pos + 5U)                 /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_CFSR_MEMFAULTSR_Pos + 4U)                 /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_CFSR_MEMFAULTSR_Pos + 3U)                 /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_CFSR_MEMFAULTSR_Pos + 1U)                 /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_CFSR_MEMFAULTSR_Pos + 0U)                 /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+#define SCB_CLIDR_IC_Pos                   0U                                             /*!< SCB CLIDR: IC Position */
+#define SCB_CLIDR_IC_Msk                   (1UL << SCB_CLIDR_IC_Pos)                      /*!< SCB CLIDR: IC Mask */
+
+#define SCB_CLIDR_DC_Pos                   1U                                             /*!< SCB CLIDR: DC Position */
+#define SCB_CLIDR_DC_Msk                   (1UL << SCB_CLIDR_DC_Pos)                      /*!< SCB CLIDR: DC Mask */
+
+
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache line Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_LEVEL_Pos                1U                                             /*!< SCB DCISW: Level Position */
+#define SCB_DCISW_LEVEL_Msk                (7UL << SCB_DCISW_LEVEL_Pos)                   /*!< SCB DCISW: Level Mask */
+
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0xFFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean line by Set-way Register Definitions */
+#define SCB_DCCSW_LEVEL_Pos                1U                                             /*!< SCB DCCSW: Level Position */
+#define SCB_DCCSW_LEVEL_Msk                (7UL << SCB_DCCSW_LEVEL_Pos)                   /*!< SCB DCCSW: Level Mask */
+
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0xFFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_LEVEL_Pos               1U                                             /*!< SCB DCCISW: Level Position */
+#define SCB_DCCISW_LEVEL_Msk               (7UL << SCB_DCCISW_LEVEL_Pos)                  /*!< SCB DCCISW: Level Mask */
+
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0xFFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* ArmChina: Implementation Defined */
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_DCCLEAN_Pos                16U                                            /*!< SCB CACR: DCCLEAN Position */
+#define SCB_CACR_DCCLEAN_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: DCCLEAN Mask */
+
+#define SCB_CACR_ICACTIVE_Pos                13U                                            /*!< SCB CACR: ICACTIVE Position */
+#define SCB_CACR_ICACTIVE_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: ICACTIVE Mask */
+
+#define SCB_CACR_DCACTIVE_Pos                12U                                            /*!< SCB CACR: DCACTIVE Position */
+#define SCB_CACR_DCACTIVE_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: DCACTIVE Mask */
+
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[32U];
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
+        uint32_t RESERVED6[4U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+        uint32_t RESERVED32[934U];
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+        uint32_t RESERVED33[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t ITFTTD0;                /*!< Offset: 0xEEC (R/ )  Integration Test FIFO Test Data 0 Register */
+  __IOM uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/W)  Integration Test ATB Control Register 2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  Integration Test ATB Control Register 0 */
+  __IM  uint32_t ITFTTD1;                /*!< Offset: 0xEFC (R/ )  Integration Test FIFO Test Data 1 Register */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  Device Configuration Register */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos      16U                                         /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos       8U                                         /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos       0U                                          /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk      (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)      /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)      /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos      16U                                         /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos       8U                                         /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos       0U                                          /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk      (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)      /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)      /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
+  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
+  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
+  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
+        uint32_t RESERVED0[1];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#else
+        uint32_t RESERVED0[3];
+#endif
+  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
+  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and VFP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and VFP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and VFP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and VFP Feature Register 2 Definitions */
+#define FPU_MVFR2_FPMisc_Pos                4U                                            /*!< MVFR2: FPMisc bits Position */
+#define FPU_MVFR2_FPMisc_Msk               (0xFUL << FPU_MVFR2_FPMisc_Pos)                /*!< MVFR2: FPMisc bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup CMSIS_DCB       Debug Control Block
+  \brief    Type definitions for the Debug Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Debug Control Block Registers (DCB).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} DCB_Type;
+
+/* DHCSR, Debug Halting Control and Status Register Definitions */
+#define DCB_DHCSR_DBGKEY_Pos               16U                                            /*!< DCB DHCSR: Debug key Position */
+#define DCB_DHCSR_DBGKEY_Msk               (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)             /*!< DCB DHCSR: Debug key Mask */
+
+#define DCB_DHCSR_S_RESTART_ST_Pos         26U                                            /*!< DCB DHCSR: Restart sticky status Position */
+#define DCB_DHCSR_S_RESTART_ST_Msk         (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)          /*!< DCB DHCSR: Restart sticky status Mask */
+
+#define DCB_DHCSR_S_RESET_ST_Pos           25U                                            /*!< DCB DHCSR: Reset sticky status Position */
+#define DCB_DHCSR_S_RESET_ST_Msk           (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)            /*!< DCB DHCSR: Reset sticky status Mask */
+
+#define DCB_DHCSR_S_RETIRE_ST_Pos          24U                                            /*!< DCB DHCSR: Retire sticky status Position */
+#define DCB_DHCSR_S_RETIRE_ST_Msk          (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)           /*!< DCB DHCSR: Retire sticky status Mask */
+
+#define DCB_DHCSR_S_SDE_Pos                20U                                            /*!< DCB DHCSR: Secure debug enabled Position */
+#define DCB_DHCSR_S_SDE_Msk                (0x1UL << DCB_DHCSR_S_SDE_Pos)                 /*!< DCB DHCSR: Secure debug enabled Mask */
+
+#define DCB_DHCSR_S_LOCKUP_Pos             19U                                            /*!< DCB DHCSR: Lockup status Position */
+#define DCB_DHCSR_S_LOCKUP_Msk             (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)              /*!< DCB DHCSR: Lockup status Mask */
+
+#define DCB_DHCSR_S_SLEEP_Pos              18U                                            /*!< DCB DHCSR: Sleeping status Position */
+#define DCB_DHCSR_S_SLEEP_Msk              (0x1UL << DCB_DHCSR_S_SLEEP_Pos)               /*!< DCB DHCSR: Sleeping status Mask */
+
+#define DCB_DHCSR_S_HALT_Pos               17U                                            /*!< DCB DHCSR: Halted status Position */
+#define DCB_DHCSR_S_HALT_Msk               (0x1UL << DCB_DHCSR_S_HALT_Pos)                /*!< DCB DHCSR: Halted status Mask */
+
+#define DCB_DHCSR_S_REGRDY_Pos             16U                                            /*!< DCB DHCSR: Register ready status Position */
+#define DCB_DHCSR_S_REGRDY_Msk             (0x1UL << DCB_DHCSR_S_REGRDY_Pos)              /*!< DCB DHCSR: Register ready status Mask */
+
+#define DCB_DHCSR_C_SNAPSTALL_Pos           5U                                            /*!< DCB DHCSR: Snap stall control Position */
+#define DCB_DHCSR_C_SNAPSTALL_Msk          (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)           /*!< DCB DHCSR: Snap stall control Mask */
+
+#define DCB_DHCSR_C_MASKINTS_Pos            3U                                            /*!< DCB DHCSR: Mask interrupts control Position */
+#define DCB_DHCSR_C_MASKINTS_Msk           (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)            /*!< DCB DHCSR: Mask interrupts control Mask */
+
+#define DCB_DHCSR_C_STEP_Pos                2U                                            /*!< DCB DHCSR: Step control Position */
+#define DCB_DHCSR_C_STEP_Msk               (0x1UL << DCB_DHCSR_C_STEP_Pos)                /*!< DCB DHCSR: Step control Mask */
+
+#define DCB_DHCSR_C_HALT_Pos                1U                                            /*!< DCB DHCSR: Halt control Position */
+#define DCB_DHCSR_C_HALT_Msk               (0x1UL << DCB_DHCSR_C_HALT_Pos)                /*!< DCB DHCSR: Halt control Mask */
+
+#define DCB_DHCSR_C_DEBUGEN_Pos             0U                                            /*!< DCB DHCSR: Debug enable control Position */
+#define DCB_DHCSR_C_DEBUGEN_Msk            (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)         /*!< DCB DHCSR: Debug enable control Mask */
+
+/* DCRSR, Debug Core Register Select Register Definitions */
+#define DCB_DCRSR_REGWnR_Pos               16U                                            /*!< DCB DCRSR: Register write/not-read Position */
+#define DCB_DCRSR_REGWnR_Msk               (0x1UL << DCB_DCRSR_REGWnR_Pos)                /*!< DCB DCRSR: Register write/not-read Mask */
+
+#define DCB_DCRSR_REGSEL_Pos                0U                                            /*!< DCB DCRSR: Register selector Position */
+#define DCB_DCRSR_REGSEL_Msk               (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)           /*!< DCB DCRSR: Register selector Mask */
+
+/* DCRDR, Debug Core Register Data Register Definitions */
+#define DCB_DCRDR_DBGTMP_Pos                0U                                            /*!< DCB DCRDR: Data temporary buffer Position */
+#define DCB_DCRDR_DBGTMP_Msk               (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)     /*!< DCB DCRDR: Data temporary buffer Mask */
+
+/* DEMCR, Debug Exception and Monitor Control Register Definitions */
+#define DCB_DEMCR_TRCENA_Pos               24U                                            /*!< DCB DEMCR: Trace enable Position */
+#define DCB_DEMCR_TRCENA_Msk               (0x1UL << DCB_DEMCR_TRCENA_Pos)                /*!< DCB DEMCR: Trace enable Mask */
+
+#define DCB_DEMCR_MONPRKEY_Pos             23U                                            /*!< DCB DEMCR: Monitor pend req key Position */
+#define DCB_DEMCR_MONPRKEY_Msk             (0x1UL << DCB_DEMCR_MONPRKEY_Pos)              /*!< DCB DEMCR: Monitor pend req key Mask */
+
+#define DCB_DEMCR_UMON_EN_Pos              21U                                            /*!< DCB DEMCR: Unprivileged monitor enable Position */
+#define DCB_DEMCR_UMON_EN_Msk              (0x1UL << DCB_DEMCR_UMON_EN_Pos)               /*!< DCB DEMCR: Unprivileged monitor enable Mask */
+
+#define DCB_DEMCR_SDME_Pos                 20U                                            /*!< DCB DEMCR: Secure DebugMonitor enable Position */
+#define DCB_DEMCR_SDME_Msk                 (0x1UL << DCB_DEMCR_SDME_Pos)                  /*!< DCB DEMCR: Secure DebugMonitor enable Mask */
+
+#define DCB_DEMCR_MON_REQ_Pos              19U                                            /*!< DCB DEMCR: Monitor request Position */
+#define DCB_DEMCR_MON_REQ_Msk              (0x1UL << DCB_DEMCR_MON_REQ_Pos)               /*!< DCB DEMCR: Monitor request Mask */
+
+#define DCB_DEMCR_MON_STEP_Pos             18U                                            /*!< DCB DEMCR: Monitor step Position */
+#define DCB_DEMCR_MON_STEP_Msk             (0x1UL << DCB_DEMCR_MON_STEP_Pos)              /*!< DCB DEMCR: Monitor step Mask */
+
+#define DCB_DEMCR_MON_PEND_Pos             17U                                            /*!< DCB DEMCR: Monitor pend Position */
+#define DCB_DEMCR_MON_PEND_Msk             (0x1UL << DCB_DEMCR_MON_PEND_Pos)              /*!< DCB DEMCR: Monitor pend Mask */
+
+#define DCB_DEMCR_MON_EN_Pos               16U                                            /*!< DCB DEMCR: Monitor enable Position */
+#define DCB_DEMCR_MON_EN_Msk               (0x1UL << DCB_DEMCR_MON_EN_Pos)                /*!< DCB DEMCR: Monitor enable Mask */
+
+#define DCB_DEMCR_VC_SFERR_Pos             11U                                            /*!< DCB DEMCR: Vector Catch SecureFault Position */
+#define DCB_DEMCR_VC_SFERR_Msk             (0x1UL << DCB_DEMCR_VC_SFERR_Pos)              /*!< DCB DEMCR: Vector Catch SecureFault Mask */
+
+#define DCB_DEMCR_VC_HARDERR_Pos           10U                                            /*!< DCB DEMCR: Vector Catch HardFault errors Position */
+#define DCB_DEMCR_VC_HARDERR_Msk           (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)            /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
+
+#define DCB_DEMCR_VC_INTERR_Pos             9U                                            /*!< DCB DEMCR: Vector Catch interrupt errors Position */
+#define DCB_DEMCR_VC_INTERR_Msk            (0x1UL << DCB_DEMCR_VC_INTERR_Pos)             /*!< DCB DEMCR: Vector Catch interrupt errors Mask */
+
+#define DCB_DEMCR_VC_BUSERR_Pos             8U                                            /*!< DCB DEMCR: Vector Catch BusFault errors Position */
+#define DCB_DEMCR_VC_BUSERR_Msk            (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)             /*!< DCB DEMCR: Vector Catch BusFault errors Mask */
+
+#define DCB_DEMCR_VC_STATERR_Pos            7U                                            /*!< DCB DEMCR: Vector Catch state errors Position */
+#define DCB_DEMCR_VC_STATERR_Msk           (0x1UL << DCB_DEMCR_VC_STATERR_Pos)            /*!< DCB DEMCR: Vector Catch state errors Mask */
+
+#define DCB_DEMCR_VC_CHKERR_Pos             6U                                            /*!< DCB DEMCR: Vector Catch check errors Position */
+#define DCB_DEMCR_VC_CHKERR_Msk            (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)             /*!< DCB DEMCR: Vector Catch check errors Mask */
+
+#define DCB_DEMCR_VC_NOCPERR_Pos            5U                                            /*!< DCB DEMCR: Vector Catch NOCP errors Position */
+#define DCB_DEMCR_VC_NOCPERR_Msk           (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)            /*!< DCB DEMCR: Vector Catch NOCP errors Mask */
+
+#define DCB_DEMCR_VC_MMERR_Pos              4U                                            /*!< DCB DEMCR: Vector Catch MemManage errors Position */
+#define DCB_DEMCR_VC_MMERR_Msk             (0x1UL << DCB_DEMCR_VC_MMERR_Pos)              /*!< DCB DEMCR: Vector Catch MemManage errors Mask */
+
+#define DCB_DEMCR_VC_CORERESET_Pos          0U                                            /*!< DCB DEMCR: Vector Catch Core reset Position */
+#define DCB_DEMCR_VC_CORERESET_Msk         (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)      /*!< DCB DEMCR: Vector Catch Core reset Mask */
+
+/* DAUTHCTRL, Debug Authentication Control Register Definitions */
+#define DCB_DAUTHCTRL_INTSPNIDEN_Pos        3U                                            /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPNIDEN_Msk       (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)        /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPNIDENSEL_Pos        2U                                            /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPNIDENSEL_Msk       (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)        /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */
+
+#define DCB_DAUTHCTRL_INTSPIDEN_Pos         1U                                            /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPIDEN_Msk        (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)         /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPIDENSEL_Pos         0U                                            /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPIDENSEL_Msk        (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)     /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */
+
+/* DSCSR, Debug Security Control and Status Register Definitions */
+#define DCB_DSCSR_CDSKEY_Pos               17U                                            /*!< DCB DSCSR: CDS write-enable key Position */
+#define DCB_DSCSR_CDSKEY_Msk               (0x1UL << DCB_DSCSR_CDSKEY_Pos)                /*!< DCB DSCSR: CDS write-enable key Mask */
+
+#define DCB_DSCSR_CDS_Pos                  16U                                            /*!< DCB DSCSR: Current domain Secure Position */
+#define DCB_DSCSR_CDS_Msk                  (0x1UL << DCB_DSCSR_CDS_Pos)                   /*!< DCB DSCSR: Current domain Secure Mask */
+
+#define DCB_DSCSR_SBRSEL_Pos                1U                                            /*!< DCB DSCSR: Secure banked register select Position */
+#define DCB_DSCSR_SBRSEL_Msk               (0x1UL << DCB_DSCSR_SBRSEL_Pos)                /*!< DCB DSCSR: Secure banked register select Mask */
+
+#define DCB_DSCSR_SBRSELEN_Pos              0U                                            /*!< DCB DSCSR: Secure banked register select enable Position */
+#define DCB_DSCSR_SBRSELEN_Msk             (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)          /*!< DCB DSCSR: Secure banked register select enable Mask */
+
+/*@} end of group CMSIS_DCB */
+
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DIB       Debug Identification Block
+  \brief    Type definitions for the Debug Identification Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Debug Identification Block Registers (DIB).
+ */
+typedef struct
+{
+  __OM  uint32_t DLAR;                   /*!< Offset: 0x000 ( /W)  SCS Software Lock Access Register */
+  __IM  uint32_t DLSR;                   /*!< Offset: 0x004 (R/ )  SCS Software Lock Status Register */
+  __IM  uint32_t DAUTHSTATUS;            /*!< Offset: 0x008 (R/ )  Debug Authentication Status Register */
+  __IM  uint32_t DDEVARCH;               /*!< Offset: 0x00C (R/ )  SCS Device Architecture Register */
+  __IM  uint32_t DDEVTYPE;               /*!< Offset: 0x010 (R/ )  SCS Device Type Register */
+} DIB_Type;
+
+/* DLAR, SCS Software Lock Access Register Definitions */
+#define DIB_DLAR_KEY_Pos                    0U                                            /*!< DIB DLAR: KEY Position */
+#define DIB_DLAR_KEY_Msk                   (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */)        /*!< DIB DLAR: KEY Mask */
+
+/* DLSR, SCS Software Lock Status Register Definitions */
+#define DIB_DLSR_nTT_Pos                    2U                                            /*!< DIB DLSR: Not thirty-two bit Position */
+#define DIB_DLSR_nTT_Msk                   (0x1UL << DIB_DLSR_nTT_Pos )                   /*!< DIB DLSR: Not thirty-two bit Mask */
+
+#define DIB_DLSR_SLK_Pos                    1U                                            /*!< DIB DLSR: Software Lock status Position */
+#define DIB_DLSR_SLK_Msk                   (0x1UL << DIB_DLSR_SLK_Pos )                   /*!< DIB DLSR: Software Lock status Mask */
+
+#define DIB_DLSR_SLI_Pos                    0U                                            /*!< DIB DLSR: Software Lock implemented Position */
+#define DIB_DLSR_SLI_Msk                   (0x1UL /*<< DIB_DLSR_SLI_Pos*/)                /*!< DIB DLSR: Software Lock implemented Mask */
+
+/* DAUTHSTATUS, Debug Authentication Status Register Definitions */
+#define DIB_DAUTHSTATUS_SNID_Pos            6U                                            /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_SNID_Msk           (0x3UL << DIB_DAUTHSTATUS_SNID_Pos )           /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_SID_Pos             4U                                            /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_SID_Msk            (0x3UL << DIB_DAUTHSTATUS_SID_Pos )            /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSNID_Pos           2U                                            /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSNID_Msk          (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos )          /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSID_Pos            0U                                            /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSID_Msk           (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/)        /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */
+
+/* DDEVARCH, SCS Device Architecture Register Definitions */
+#define DIB_DDEVARCH_ARCHITECT_Pos         21U                                            /*!< DIB DDEVARCH: Architect Position */
+#define DIB_DDEVARCH_ARCHITECT_Msk         (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos )       /*!< DIB DDEVARCH: Architect Mask */
+
+#define DIB_DDEVARCH_PRESENT_Pos           20U                                            /*!< DIB DDEVARCH: DEVARCH Present Position */
+#define DIB_DDEVARCH_PRESENT_Msk           (0x1FUL << DIB_DDEVARCH_PRESENT_Pos )          /*!< DIB DDEVARCH: DEVARCH Present Mask */
+
+#define DIB_DDEVARCH_REVISION_Pos          16U                                            /*!< DIB DDEVARCH: Revision Position */
+#define DIB_DDEVARCH_REVISION_Msk          (0xFUL << DIB_DDEVARCH_REVISION_Pos )          /*!< DIB DDEVARCH: Revision Mask */
+
+#define DIB_DDEVARCH_ARCHVER_Pos           12U                                            /*!< DIB DDEVARCH: Architecture Version Position */
+#define DIB_DDEVARCH_ARCHVER_Msk           (0xFUL << DIB_DDEVARCH_ARCHVER_Pos )           /*!< DIB DDEVARCH: Architecture Version Mask */
+
+#define DIB_DDEVARCH_ARCHPART_Pos           0U                                            /*!< DIB DDEVARCH: Architecture Part Position */
+#define DIB_DDEVARCH_ARCHPART_Msk          (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/)     /*!< DIB DDEVARCH: Architecture Part Mask */
+
+/* DDEVTYPE, SCS Device Type Register Definitions */
+#define DIB_DDEVTYPE_SUB_Pos                4U                                            /*!< DIB DDEVTYPE: Sub-type Position */
+#define DIB_DDEVTYPE_SUB_Msk               (0xFUL << DIB_DDEVTYPE_SUB_Pos )               /*!< DIB DDEVTYPE: Sub-type Mask */
+
+#define DIB_DDEVTYPE_MAJOR_Pos              0U                                            /*!< DIB DDEVTYPE: Major type Position */
+#define DIB_DDEVTYPE_MAJOR_Msk             (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/)          /*!< DIB DDEVTYPE: Major type Mask */
+
+
+/*@} end of group CMSIS_DIB */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define DCB_BASE            (0xE000EDF0UL)                             /*!< DCB Base Address */
+  #define DIB_BASE            (0xE000EFB0UL)                             /*!< DIB Base Address */
+  #define EMSS_BASE           (0xE001E000UL)                             /*!<Enhanced Memory SubSystem Base Address */
+  
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define DCB                 ((DCB_Type       *)     DCB_BASE         ) /*!< DCB configuration struct */
+  #define DIB                 ((DIB_Type       *)     DIB_BASE         ) /*!< DIB configuration struct */
+  #define EMSS                ((EMSS_Type      *)     EMSS_BASE        ) /*!<Ehanced MSS Registers struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
+  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+
+  #define DCB_BASE_NS         (0xE002EDF0UL)                             /*!< DCB Base Address                  (non-secure address space) */
+  #define DIB_BASE_NS         (0xE002EFB0UL)                             /*!< DIB Base Address                  (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define DCB_NS              ((DCB_Type       *)     DCB_BASE_NS      ) /*!< DCB configuration struct          (non-secure address space) */
+  #define DIB_NS              ((DIB_Type       *)     DIB_BASE_NS      ) /*!< DIB configuration struct          (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
+  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+  #define SW_SystemReset              __SW_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */ 
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
+#define EXC_RETURN_SPSEL           (0x00000004UL)     /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP           */
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
+#else 
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
+#endif
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    __COMPILER_BARRIER();
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __COMPILER_BARRIER();
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+  __DSB();
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses including
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/**
+  \brief   Software Reset
+  \details Initiates a system reset request to reset the CPU.
+ */
+__NO_RETURN __STATIC_INLINE void __SW_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses including
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_BFHFNMINS_Msk) | /* Keep BFHFNMINS unchanged. Use this Reset function in case your case need to keep it */
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | /* Keep priority group unchanged */
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Priority Grouping (non-secure)
+  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB_NS->AIRCR;                                                /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
+  SCB_NS->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping (non-secure)
+  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+/* ##################################    Debug Control function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_DCBFunctions Debug Control Functions
+  \brief    Functions that access the Debug Control Block.
+  @{
+ */
+
+
+/**
+  \brief   Set Debug Authentication Control Register
+  \details writes to Debug Authentication Control register.
+  \param [in]  value  value to be writen.
+ */
+__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
+{
+    __DSB();
+    __ISB();
+    DCB->DAUTHCTRL = value;
+    __DSB();
+    __ISB();
+}
+
+
+/**
+  \brief   Get Debug Authentication Control Register
+  \details Reads Debug Authentication Control register.
+  \return             Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
+{
+    return (DCB->DAUTHCTRL);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Debug Authentication Control Register (non-secure)
+  \details writes to non-secure Debug Authentication Control register when in secure state.
+  \param [in]  value  value to be writen
+ */
+__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
+{
+    __DSB();
+    __ISB();
+    DCB_NS->DAUTHCTRL = value;
+    __DSB();
+    __ISB();
+}
+
+
+/**
+  \brief   Get Debug Authentication Control Register (non-secure)
+  \details Reads non-secure Debug Authentication Control register when in secure state.
+  \return             Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
+{
+    return (DCB_NS->DAUTHCTRL);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ##################################    Debug Identification function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions
+  \brief    Functions that access the Debug Identification Block.
+  @{
+ */
+
+
+/**
+  \brief   Get Debug Authentication Status Register
+  \details Reads Debug Authentication Status register.
+  \return             Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
+{
+    return (DIB->DAUTHSTATUS);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Debug Authentication Status Register (non-secure)
+  \details Reads non-secure Debug Authentication Status register when in secure state.
+  \return             Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
+{
+    return (DIB_NS->DAUTHSTATUS);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \
+     (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)))
+
+/* ##########################  Cache functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_CacheFunctions Cache Functions
+  \brief    Functions that configure Instruction and Data cache.
+  @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )
+
+#define __SCB_DCACHE_LINE_SIZE  32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
+#define __SCB_ICACHE_LINE_SIZE  32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
+
+/**
+  \brief   Enable I-Cache
+  \details Turns on I-Cache
+  */
+__STATIC_FORCEINLINE void SCB_EnableICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    if (SCB->CCR & SCB_CCR_IC_Msk) return;  /* return if ICache is already enabled */
+
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+    __DSB();
+    __ISB();
+    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Disable I-Cache
+  \details Turns off I-Cache
+  */
+__STATIC_FORCEINLINE void SCB_DisableICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  /* disable I-Cache */
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Invalidate I-Cache
+  \details Invalidates I-Cache
+  */
+__STATIC_FORCEINLINE void SCB_InvalidateICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   I-Cache Invalidate by address
+  \details Invalidates I-Cache for the given address.
+           I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
+           I-Cache memory blocks which are part of given address + given size are invalidated.
+  \param[in]   addr    address
+  \param[in]   isize   size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    if ( isize > 0 ) {
+       int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
+      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;
+
+      __DSB();
+
+      do {
+        SCB->ICIMVAU = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+        op_addr += __SCB_ICACHE_LINE_SIZE;
+        op_size -= __SCB_ICACHE_LINE_SIZE;
+      } while ( op_size > 0 );
+
+      __DSB();
+      __ISB();
+    }
+  #endif
+}
+
+
+/**
+  \brief   Enable D-Cache
+  \details Turns on D-Cache
+  */
+__STATIC_FORCEINLINE void SCB_EnableDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    if (SCB->CCR & SCB_CCR_DC_Msk) return;  /* return if DCache is already enabled */
+
+    SCB->CSSELR = 0U;                       /* select Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+    __DSB();
+
+    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Disable D-Cache
+  \details Turns off D-Cache
+  */
+__STATIC_FORCEINLINE void SCB_DisableDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U;                       /* select Level 1 data cache */
+    __DSB();
+
+    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  /* disable D-Cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean & invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Invalidate D-Cache
+  \details Invalidates D-Cache
+  */
+__STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U;                       /* select Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Clean D-Cache
+  \details Cleans D-Cache
+  */
+__STATIC_FORCEINLINE void SCB_CleanDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U;                       /* select Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
+                      ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Clean & Invalidate D-Cache
+  \details Cleans and Invalidates D-Cache
+  */
+__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U;                       /* select Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean & invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Invalidate by address
+  \details Invalidates D-Cache for the given address.
+           D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
+           D-Cache memory blocks which are part of given address + given size are invalidated.
+  \param[in]   addr    address
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    if ( dsize > 0 ) { 
+       int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+    
+      __DSB();
+
+      do {
+        SCB->DCIMVAC = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+        op_addr += __SCB_DCACHE_LINE_SIZE;
+        op_size -= __SCB_DCACHE_LINE_SIZE;
+      } while ( op_size > 0 );
+
+      __DSB();
+      __ISB();
+    }
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Clean by address
+  \details Cleans D-Cache for the given address
+           D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity.
+           D-Cache memory blocks which are part of given address + given size are cleaned.
+  \param[in]   addr    address
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    if ( dsize > 0 ) { 
+       int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+    
+      __DSB();
+
+      do {
+        SCB->DCCMVAC = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+        op_addr += __SCB_DCACHE_LINE_SIZE;
+        op_size -= __SCB_DCACHE_LINE_SIZE;
+      } while ( op_size > 0 );
+
+      __DSB();
+      __ISB();
+    }
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Clean and Invalidate by address
+  \details Cleans and invalidates D_Cache for the given address
+           D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity.
+           D-Cache memory blocks which are part of given address + given size are cleaned and invalidated.
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    if ( dsize > 0 ) { 
+       int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+    
+      __DSB();
+
+      do {
+        SCB->DCCIMVAC = op_addr;            /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+        op_addr +=          __SCB_DCACHE_LINE_SIZE;
+        op_size -=          __SCB_DCACHE_LINE_SIZE;
+      } while ( op_size > 0 );
+
+      __DSB();
+      __ISB();
+    }
+  #endif
+}
+
+/*@} end of CMSIS_Core_CacheFunctions */
+#endif
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_STAR_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

CMSIS/Core/Include/pac_armv81.h

@@ -0,0 +1,206 @@
+/******************************************************************************
+ * @file     pac_armv81.h
+ * @brief    CMSIS PAC key functions for Armv8.1-M PAC extension
+ * @version  V1.0.0
+ * @date     23. March 2022
+ ******************************************************************************/
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+
+#ifndef PAC_ARMV81_H
+#define PAC_ARMV81_H
+
+
+/* ###################  PAC Key functions  ########################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_PacKeyFunctions PAC Key functions
+  \brief    Functions that access the PAC keys.
+  @{
+ */
+
+#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1))
+
+/**
+  \brief   read the PAC key used for privileged mode
+  \details Reads the PAC key stored in the PAC_KEY_P registers.
+  \param [out]    pPacKey  128bit PAC key
+ */
+__STATIC_FORCEINLINE void __get_PAC_KEY_P (uint32_t* pPacKey) {
+  __ASM volatile (
+  "mrs   r1, pac_key_p_0\n"
+  "str   r1,[%0,#0]\n"
+  "mrs   r1, pac_key_p_1\n"
+  "str   r1,[%0,#4]\n"
+  "mrs   r1, pac_key_p_2\n"
+  "str   r1,[%0,#8]\n"
+  "mrs   r1, pac_key_p_3\n"
+  "str   r1,[%0,#12]\n"
+  : : "r" (pPacKey) : "memory", "r1"
+  );
+}
+
+/**
+  \brief   write the PAC key used for privileged mode
+  \details writes the given PAC key to the PAC_KEY_P registers.
+  \param [in]    pPacKey  128bit PAC key
+ */
+__STATIC_FORCEINLINE void __set_PAC_KEY_P (uint32_t* pPacKey) {
+  __ASM volatile (
+  "ldr   r1,[%0,#0]\n"
+  "msr   pac_key_p_0, r1\n"
+  "ldr   r1,[%0,#4]\n"
+  "msr   pac_key_p_1, r1\n"
+  "ldr   r1,[%0,#8]\n"
+  "msr   pac_key_p_2, r1\n"
+  "ldr   r1,[%0,#12]\n"
+  "msr   pac_key_p_3, r1\n"
+  : : "r" (pPacKey) : "memory", "r1"
+  );
+}
+
+/**
+  \brief   read the PAC key used for unprivileged mode
+  \details Reads the PAC key stored in the PAC_KEY_U registers.
+  \param [out]    pPacKey  128bit PAC key
+ */
+__STATIC_FORCEINLINE void __get_PAC_KEY_U (uint32_t* pPacKey) {
+  __ASM volatile (
+  "mrs   r1, pac_key_u_0\n"
+  "str   r1,[%0,#0]\n"
+  "mrs   r1, pac_key_u_1\n"
+  "str   r1,[%0,#4]\n"
+  "mrs   r1, pac_key_u_2\n"
+  "str   r1,[%0,#8]\n"
+  "mrs   r1, pac_key_u_3\n"
+  "str   r1,[%0,#12]\n"
+  : : "r" (pPacKey) : "memory", "r1"
+  );
+}
+
+/**
+  \brief   write the PAC key used for unprivileged mode
+  \details writes the given PAC key to the PAC_KEY_U registers.
+  \param [in]    pPacKey  128bit PAC key
+ */
+__STATIC_FORCEINLINE void __set_PAC_KEY_U (uint32_t* pPacKey) {
+  __ASM volatile (
+  "ldr   r1,[%0,#0]\n"
+  "msr   pac_key_u_0, r1\n"
+  "ldr   r1,[%0,#4]\n"
+  "msr   pac_key_u_1, r1\n"
+  "ldr   r1,[%0,#8]\n"
+  "msr   pac_key_u_2, r1\n"
+  "ldr   r1,[%0,#12]\n"
+  "msr   pac_key_u_3, r1\n"
+  : : "r" (pPacKey) : "memory", "r1"
+  );
+}
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+
+/**
+  \brief   read the PAC key used for privileged mode (non-secure)
+  \details Reads the PAC key stored in the non-secure PAC_KEY_P registers when in secure mode.
+  \param [out]    pPacKey  128bit PAC key
+ */
+__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_P_NS (uint32_t* pPacKey) {
+  __ASM volatile (
+  "mrs   r1, pac_key_p_0_ns\n"
+  "str   r1,[%0,#0]\n"
+  "mrs   r1, pac_key_p_1_ns\n"
+  "str   r1,[%0,#4]\n"
+  "mrs   r1, pac_key_p_2_ns\n"
+  "str   r1,[%0,#8]\n"
+  "mrs   r1, pac_key_p_3_ns\n"
+  "str   r1,[%0,#12]\n"
+  : : "r" (pPacKey) : "memory", "r1"
+  );
+}
+
+/**
+  \brief   write the PAC key used for privileged mode (non-secure)
+  \details writes the given PAC key to the non-secure PAC_KEY_P registers when in secure mode.
+  \param [in]    pPacKey  128bit PAC key
+ */
+__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_P_NS (uint32_t* pPacKey) {
+  __ASM volatile (
+  "ldr   r1,[%0,#0]\n"
+  "msr   pac_key_p_0_ns, r1\n"
+  "ldr   r1,[%0,#4]\n"
+  "msr   pac_key_p_1_ns, r1\n"
+  "ldr   r1,[%0,#8]\n"
+  "msr   pac_key_p_2_ns, r1\n"
+  "ldr   r1,[%0,#12]\n"
+  "msr   pac_key_p_3_ns, r1\n"
+  : : "r" (pPacKey) : "memory", "r1"
+  );
+}
+
+/**
+  \brief   read the PAC key used for unprivileged mode (non-secure)
+  \details Reads the PAC key stored in the non-secure PAC_KEY_U registers when in secure mode.
+  \param [out]    pPacKey  128bit PAC key
+ */
+__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_U_NS (uint32_t* pPacKey) {
+  __ASM volatile (
+  "mrs   r1, pac_key_u_0_ns\n"
+  "str   r1,[%0,#0]\n"
+  "mrs   r1, pac_key_u_1_ns\n"
+  "str   r1,[%0,#4]\n"
+  "mrs   r1, pac_key_u_2_ns\n"
+  "str   r1,[%0,#8]\n"
+  "mrs   r1, pac_key_u_3_ns\n"
+  "str   r1,[%0,#12]\n"
+  : : "r" (pPacKey) : "memory", "r1"
+  );
+}
+
+/**
+  \brief   write the PAC key used for unprivileged mode (non-secure)
+  \details writes the given PAC key to the non-secure PAC_KEY_U registers when in secure mode.
+  \param [in]    pPacKey  128bit PAC key
+ */
+__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_U_NS (uint32_t* pPacKey) {
+  __ASM volatile (
+  "ldr   r1,[%0,#0]\n"
+  "msr   pac_key_u_0_ns, r1\n"
+  "ldr   r1,[%0,#4]\n"
+  "msr   pac_key_u_1_ns, r1\n"
+  "ldr   r1,[%0,#8]\n"
+  "msr   pac_key_u_2_ns, r1\n"
+  "ldr   r1,[%0,#12]\n"
+  "msr   pac_key_u_3_ns, r1\n"
+  : : "r" (pPacKey) : "memory", "r1"
+  );
+}
+
+#endif /* (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) */
+
+#endif /* (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) */
+
+/*@} end of CMSIS_Core_PacKeyFunctions */
+
+
+#endif /* PAC_ARMV81_H */

CMSIS/CoreValidation/Tests/bootloader/config/core_m/rtebuild.sct

@@ -36,9 +36,9 @@
 #define __STACK_SIZE    0x00000400
 #define __HEAP_SIZE     0x00000C00
 
-/*--------------------- CMSE Venner Configuration ---------------------------
-; <h> CMSE Venner Configuration
-;   <o0>  CMSE Venner Size (in Bytes) <0x0-0xFFFFFFFF:32>
+/*--------------------- CMSE Veneer Configuration ---------------------------
+; <h> CMSE Veneer Configuration
+;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>
 ; </h>
  *----------------------------------------------------------------------------*/
 #define __CMSEVENEER_SIZE    0x200
@@ -115,7 +115,7 @@ LR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region
 }
 
 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Venners
+LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers
   ER_CMSE_VENEER __CV_BASE __CV_SIZE  {
    *(Veneer$$CMSE)
   }

CMSIS/CoreValidation/Tests/config/core_m/rtebuild.sct

@@ -36,9 +36,9 @@
 #define __STACK_SIZE    0x00000400
 #define __HEAP_SIZE     0x00000C00
 
-/*--------------------- CMSE Venner Configuration ---------------------------
-; <h> CMSE Venner Configuration
-;   <o0>  CMSE Venner Size (in Bytes) <0x0-0xFFFFFFFF:32>
+/*--------------------- CMSE Veneer Configuration ---------------------------
+; <h> CMSE Veneer Configuration
+;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>
 ; </h>
  *----------------------------------------------------------------------------*/
 #define __CMSEVENEER_SIZE    0x200
@@ -115,7 +115,7 @@ LR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region
 }
 
 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Venners
+LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers
   ER_CMSE_VENEER __CV_BASE __CV_SIZE  {
    *(Veneer$$CMSE)
   }

CMSIS/CoreValidation/Tests/config/core_m/rtebuild_ac5.sct

@@ -33,9 +33,9 @@
 #define __STACK_SIZE    0x00000400
 #define __HEAP_SIZE     0x00000C00
 
-/*--------------------- CMSE Venner Configuration ---------------------------
-; <h> CMSE Venner Configuration
-;   <o0>  CMSE Venner Size (in Bytes) <0x0-0xFFFFFFFF:32>
+/*--------------------- CMSE Veneer Configuration ---------------------------
+; <h> CMSE Veneer Configuration
+;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>
 ; </h>
  *----------------------------------------------------------------------------*/
 #define __CMSEVENEER_SIZE    0x200
@@ -112,7 +112,7 @@ LR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region
 }
 
 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Venners
+LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers
   ER_CMSE_VENEER __CV_BASE __CV_SIZE  {
    *(Veneer$$CMSE)
   }

CMSIS/CoreValidation/Tests/config/core_m/rtebuild_ns.sct

@@ -36,9 +36,9 @@
 #define __STACK_SIZE    0x00000400
 #define __HEAP_SIZE     0x00000C00
 
-/*--------------------- CMSE Venner Configuration ---------------------------
-; <h> CMSE Venner Configuration
-;   <o0>  CMSE Venner Size (in Bytes) <0x0-0xFFFFFFFF:32>
+/*--------------------- CMSE Veneer Configuration ---------------------------
+; <h> CMSE Veneer Configuration
+;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>
 ; </h>
  *----------------------------------------------------------------------------*/
 #define __CMSEVENEER_SIZE    0x200
@@ -115,7 +115,7 @@ LR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region
 }
 
 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Venners
+LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers
   ER_CMSE_VENEER __CV_BASE __CV_SIZE  {
    *(Veneer$$CMSE)
   }

CMSIS/CoreValidation/Tests/config/core_m/rtebuild_s.sct

@@ -36,9 +36,9 @@
 #define __STACK_SIZE    0x00000400
 #define __HEAP_SIZE     0x00000C00
 
-/*--------------------- CMSE Venner Configuration ---------------------------
-; <h> CMSE Venner Configuration
-;   <o0>  CMSE Venner Size (in Bytes) <0x0-0xFFFFFFFF:32>
+/*--------------------- CMSE Veneer Configuration ---------------------------
+; <h> CMSE Veneer Configuration
+;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>
 ; </h>
  *----------------------------------------------------------------------------*/
 #define __CMSEVENEER_SIZE    0x200
@@ -115,7 +115,7 @@ LR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region
 }
 
 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Venners
+LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers
   ER_CMSE_VENEER __CV_BASE __CV_SIZE  {
    *(Veneer$$CMSE)
   }

CMSIS/Core_A/Include/cmsis_gcc.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     cmsis_gcc.h
  * @brief    CMSIS compiler specific macros, functions, instructions
- * @version  V1.3.1
- * @date     05. May 2021
+ * @version  V1.3.2
+ * @date     24. March 2022
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
+ * Copyright (c) 2009-2022 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -459,23 +459,7 @@ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
 __STATIC_FORCEINLINE  uint32_t __RBIT(uint32_t value)
 {
   uint32_t result;
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
    __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) );
-#else
-  int32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
-
-  result = value;                      /* r will be reversed bits of v; first get LSB of v */
-  for (value >>= 1U; value; value >>= 1U)
-  {
-    result <<= 1U;
-    result |= value & 1U;
-    s--;
-  }
-  result <<= s;                        /* shift when v's highest bits are zero */
-#endif
   return result;
 }
 

CMSIS/DAP/Firmware/Config/DAP_config.h

@@ -30,9 +30,9 @@
 
 
 //**************************************************************************************************
-/** 
+/**
 \defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information
-\ingroup DAP_ConfigIO_gr 
+\ingroup DAP_ConfigIO_gr
 @{
 Provides definitions about the hardware and configuration of the Debug Unit.
 
@@ -59,7 +59,7 @@ This information includes:
 /// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
 /// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors
 /// require 2 processor cycles for a I/O Port Write operation.  If the Debug Unit uses
-/// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be 
+/// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
 /// required.
 #define IO_PORT_WRITE_CYCLES    2U              ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0.
 
@@ -263,13 +263,13 @@ __STATIC_INLINE uint8_t DAP_GetProductFirmwareVersionString (char *str) {
 
 
 //**************************************************************************************************
-/** 
+/**
 \defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access
-\ingroup DAP_ConfigIO_gr 
+\ingroup DAP_ConfigIO_gr
 @{
 
 Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode
-and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug 
+and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug
 interface of a device. The following I/O Pins are provided:
 
 JTAG I/O Pin                 | SWD I/O Pin          | CMSIS-DAP Hardware pin mode
@@ -277,19 +277,19 @@ JTAG I/O Pin                 | SWD I/O Pin          | CMSIS-DAP Hardware pin mod
 TCK: Test Clock              | SWCLK: Clock         | Output Push/Pull
 TMS: Test Mode Select        | SWDIO: Data I/O      | Output Push/Pull; Input (for receiving data)
 TDI: Test Data Input         |                      | Output Push/Pull
-TDO: Test Data Output        |                      | Input             
+TDO: Test Data Output        |                      | Input
 nTRST: Test Reset (optional) |                      | Output Open Drain with pull-up resistor
 nRESET: Device Reset         | nRESET: Device Reset | Output Open Drain with pull-up resistor
 
 
 DAP Hardware I/O Pin Access Functions
 -------------------------------------
-The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to 
-these I/O Pins. 
+The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to
+these I/O Pins.
 
 For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only.
-This functions are provided to achieve faster I/O that is possible with some advanced GPIO 
-peripherals that can independently write/read a single I/O pin without affecting any other pins 
+This functions are provided to achieve faster I/O that is possible with some advanced GPIO
+peripherals that can independently write/read a single I/O pin without affecting any other pins
 of the same I/O port. The following SWDIO I/O Pin functions are provided:
  - \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware.
  - \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware.
@@ -304,16 +304,16 @@ of the same I/O port. The following SWDIO I/O Pin functions are provided:
 Configures the DAP Hardware I/O pins for JTAG mode:
  - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level.
  - TDO to input mode.
-*/ 
+*/
 __STATIC_INLINE void PORT_JTAG_SETUP (void) {
   ;
 }
- 
+
 /** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
 Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
  - SWCLK, SWDIO, nRESET to output mode and set to default high level.
  - TDI, nTRST to HighZ mode (pins are unused in SWD mode).
-*/ 
+*/
 __STATIC_INLINE void PORT_SWD_SETUP (void) {
   ;
 }
@@ -393,7 +393,7 @@ Configure the SWDIO DAP hardware I/O pin to output mode. This function is
 called prior \ref PIN_SWDIO_OUT function calls.
 */
 __STATIC_FORCEINLINE void     PIN_SWDIO_OUT_ENABLE  (void) {
-  ; 
+  ;
 }
 
 /** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
@@ -447,7 +447,7 @@ __STATIC_FORCEINLINE uint32_t PIN_nTRST_IN   (void) {
            - 1: release JTAG TRST Test Reset.
 */
 __STATIC_FORCEINLINE void     PIN_nTRST_OUT  (uint32_t bit) {
-  ; 
+  ;
 }
 
 // nRESET Pin I/O------------------------------------------
@@ -472,7 +472,7 @@ __STATIC_FORCEINLINE void     PIN_nRESET_OUT (uint32_t bit) {
 
 
 //**************************************************************************************************
-/** 
+/**
 \defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs
 \ingroup DAP_ConfigIO_gr
 @{
@@ -502,13 +502,13 @@ __STATIC_INLINE void LED_RUNNING_OUT (uint32_t bit) {}
 
 
 //**************************************************************************************************
-/** 
+/**
 \defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp
 \ingroup DAP_ConfigIO_gr
 @{
 Access function for Test Domain Timer.
 
-The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By 
+The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By
 default, the DWT timer is used.  The frequency of this timer is configured with \ref TIMESTAMP_CLOCK.
 
 */
@@ -524,7 +524,7 @@ __STATIC_INLINE uint32_t TIMESTAMP_GET (void) {
 
 
 //**************************************************************************************************
-/** 
+/**
 \defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
 \ingroup DAP_ConfigIO_gr
 @{
@@ -533,7 +533,7 @@ CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_S
 */
 
 /** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized).
-This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the 
+This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the
 Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set:
  - I/O clock system enabled.
  - all I/O pins: input buffer enabled, output pins are set to HighZ mode.
@@ -546,7 +546,7 @@ __STATIC_INLINE void DAP_SETUP (void) {
 
 /** Reset Target Device with custom specific I/O pin or command sequence.
 This function allows the optional implementation of a device specific reset sequence.
-It is called when the command \ref DAP_ResetTarget and is for example required 
+It is called when the command \ref DAP_ResetTarget and is for example required
 when a device needs a time-critical unlock sequence that enables the debug port.
 \return 0 = no device specific reset sequence is implemented.\n
         1 = a device specific reset sequence is implemented.

CMSIS/DAP/Firmware/Examples/LPC-Link2/V2/CMSIS_DAP.uvguix → CMSIS/DAP/Firmware/Examples/LPC-Link2/CMSIS_DAP.uvguix

@@ -1864,7 +1864,7 @@
       <Size>100</Size>
       <ActiveTab>0</ActiveTab>
       <Doc>
-        <Name>.\Abstract.txt</Name>
+        <Name>.\README.md</Name>
         <ColumnNumber>0</ColumnNumber>
         <TopLine>1</TopLine>
         <CurrentLine>1</CurrentLine>

CMSIS/DAP/Firmware/Examples/LPC-Link2/V2/CMSIS_DAP.uvoptx → CMSIS/DAP/Firmware/Examples/LPC-Link2/CMSIS_DAP.uvoptx

@@ -432,8 +432,8 @@
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>.\Abstract.txt</PathWithFileName>
-      <FilenameWithoutPath>Abstract.txt</FilenameWithoutPath>
+      <PathWithFileName>.\README.md</PathWithFileName>
+      <FilenameWithoutPath>README.md</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
@@ -464,7 +464,7 @@
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\..\Source\DAP.c</PathWithFileName>
+      <PathWithFileName>..\..\Source\DAP.c</PathWithFileName>
       <FilenameWithoutPath>DAP.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
@@ -476,7 +476,7 @@
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\..\Source\JTAG_DP.c</PathWithFileName>
+      <PathWithFileName>..\..\Source\JTAG_DP.c</PathWithFileName>
       <FilenameWithoutPath>JTAG_DP.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
@@ -488,7 +488,7 @@
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\..\Source\SW_DP.c</PathWithFileName>
+      <PathWithFileName>..\..\Source\SW_DP.c</PathWithFileName>
       <FilenameWithoutPath>SW_DP.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
@@ -500,7 +500,7 @@
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\..\Source\SWO.c</PathWithFileName>
+      <PathWithFileName>..\..\Source\SWO.c</PathWithFileName>
       <FilenameWithoutPath>SWO.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
@@ -512,7 +512,7 @@
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\..\Source\UART.c</PathWithFileName>
+      <PathWithFileName>..\..\Source\UART.c</PathWithFileName>
       <FilenameWithoutPath>UART.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>

CMSIS/DAP/Firmware/Examples/LPC-Link2/V2/CMSIS_DAP.uvprojx → CMSIS/DAP/Firmware/Examples/LPC-Link2/CMSIS_DAP.uvprojx

@@ -339,7 +339,7 @@
               <MiscControls></MiscControls>
               <Define></Define>
               <Undefine></Undefine>
-              <IncludePath>.;..\..\..\Include</IncludePath>
+              <IncludePath>.;..\..\Include</IncludePath>
             </VariousControls>
           </Cads>
           <Aads>
@@ -465,9 +465,9 @@
           <GroupName>Documentation</GroupName>
           <Files>
             <File>
-              <FileName>Abstract.txt</FileName>
+              <FileName>README.md</FileName>
               <FileType>5</FileType>
-              <FilePath>.\Abstract.txt</FilePath>
+              <FilePath>.\README.md</FilePath>
             </File>
           </Files>
         </Group>
@@ -482,27 +482,27 @@
             <File>
               <FileName>DAP.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\Source\DAP.c</FilePath>
+              <FilePath>..\..\Source\DAP.c</FilePath>
             </File>
             <File>
               <FileName>JTAG_DP.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\Source\JTAG_DP.c</FilePath>
+              <FilePath>..\..\Source\JTAG_DP.c</FilePath>
             </File>
             <File>
               <FileName>SW_DP.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\Source\SW_DP.c</FilePath>
+              <FilePath>..\..\Source\SW_DP.c</FilePath>
             </File>
             <File>
               <FileName>SWO.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\Source\SWO.c</FilePath>
+              <FilePath>..\..\Source\SWO.c</FilePath>
             </File>
             <File>
               <FileName>UART.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\Source\UART.c</FilePath>
+              <FilePath>..\..\Source\UART.c</FilePath>
             </File>
           </Files>
         </Group>
@@ -853,7 +853,7 @@
               <MiscControls></MiscControls>
               <Define>TARGET_POWER_EN LPC_LINK2_ONBOARD</Define>
               <Undefine></Undefine>
-              <IncludePath>.;..\..\..\Include</IncludePath>
+              <IncludePath>.;..\..\Include</IncludePath>
             </VariousControls>
           </Cads>
           <Aads>
@@ -928,9 +928,9 @@
           <GroupName>Documentation</GroupName>
           <Files>
             <File>
-              <FileName>Abstract.txt</FileName>
+              <FileName>README.md</FileName>
               <FileType>5</FileType>
-              <FilePath>.\Abstract.txt</FilePath>
+              <FilePath>.\README.md</FilePath>
             </File>
           </Files>
         </Group>
@@ -945,27 +945,27 @@
             <File>
               <FileName>DAP.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\Source\DAP.c</FilePath>
+              <FilePath>..\..\Source\DAP.c</FilePath>
             </File>
             <File>
               <FileName>JTAG_DP.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\Source\JTAG_DP.c</FilePath>
+              <FilePath>..\..\Source\JTAG_DP.c</FilePath>
             </File>
             <File>
               <FileName>SW_DP.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\Source\SW_DP.c</FilePath>
+              <FilePath>..\..\Source\SW_DP.c</FilePath>
             </File>
             <File>
               <FileName>SWO.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\Source\SWO.c</FilePath>
+              <FilePath>..\..\Source\SWO.c</FilePath>
             </File>
             <File>
               <FileName>UART.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\Source\UART.c</FilePath>
+              <FilePath>..\..\Source\UART.c</FilePath>
             </File>
           </Files>
         </Group>

CMSIS/DAP/Firmware/Examples/LPC-Link2/V2/DAP_config.h → CMSIS/DAP/Firmware/Examples/LPC-Link2/DAP_config.h

@@ -30,9 +30,9 @@
 
 
 //**************************************************************************************************
-/** 
+/**
 \defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information
-\ingroup DAP_ConfigIO_gr 
+\ingroup DAP_ConfigIO_gr
 @{
 Provides definitions about the hardware and configuration of the Debug Unit.
 
@@ -64,7 +64,7 @@ This information includes:
 /// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
 /// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors
 /// require 2 processor cycles for a I/O Port Write operation.  If the Debug Unit uses
-/// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be 
+/// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
 /// required.
 #define IO_PORT_WRITE_CYCLES    2U              ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0.
 
@@ -339,13 +339,13 @@ __STATIC_INLINE uint8_t DAP_GetProductFirmwareVersionString (char *str) {
 
 
 //**************************************************************************************************
-/** 
+/**
 \defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access
-\ingroup DAP_ConfigIO_gr 
+\ingroup DAP_ConfigIO_gr
 @{
 
 Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode
-and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug 
+and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug
 interface of a device. The following I/O Pins are provided:
 
 JTAG I/O Pin                 | SWD I/O Pin          | CMSIS-DAP Hardware pin mode
@@ -353,19 +353,19 @@ JTAG I/O Pin                 | SWD I/O Pin          | CMSIS-DAP Hardware pin mod
 TCK: Test Clock              | SWCLK: Clock         | Output Push/Pull
 TMS: Test Mode Select        | SWDIO: Data I/O      | Output Push/Pull; Input (for receiving data)
 TDI: Test Data Input         |                      | Output Push/Pull
-TDO: Test Data Output        |                      | Input             
+TDO: Test Data Output        |                      | Input
 nTRST: Test Reset (optional) |                      | Output Open Drain with pull-up resistor
 nRESET: Device Reset         | nRESET: Device Reset | Output Open Drain with pull-up resistor
 
 
 DAP Hardware I/O Pin Access Functions
 -------------------------------------
-The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to 
-these I/O Pins. 
+The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to
+these I/O Pins.
 
 For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only.
-This functions are provided to achieve faster I/O that is possible with some advanced GPIO 
-peripherals that can independently write/read a single I/O pin without affecting any other pins 
+This functions are provided to achieve faster I/O that is possible with some advanced GPIO
+peripherals that can independently write/read a single I/O pin without affecting any other pins
 of the same I/O port. The following SWDIO I/O Pin functions are provided:
  - \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware.
  - \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware.
@@ -385,17 +385,17 @@ of the same I/O port. The following SWDIO I/O Pin functions are provided:
 Configures the DAP Hardware I/O pins for JTAG mode:
  - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level.
  - TDO to input mode.
-*/ 
+*/
 __STATIC_INLINE void PORT_JTAG_SETUP (void) {
   LPC_GPIO_PORT->MASK[PIN_SWDIO_TMS_PORT] = 0U;
   LPC_GPIO_PORT->MASK[PIN_TDI_PORT] = ~(1U << PIN_TDI_BIT);
 }
- 
+
 /** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
 Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
  - SWCLK, SWDIO, nRESET to output mode and set to default high level.
  - TDI, nTRST to HighZ mode (pins are unused in SWD mode).
-*/ 
+*/
 __STATIC_INLINE void PORT_SWD_SETUP (void) {
   LPC_GPIO_PORT->MASK[PIN_TDI_PORT] = 0U;
   LPC_GPIO_PORT->MASK[PIN_SWDIO_TMS_PORT] = ~(1U << PIN_SWDIO_TMS_BIT);
@@ -567,7 +567,7 @@ __STATIC_FORCEINLINE void     PIN_nRESET_OUT (uint32_t bit) {
 
 
 //**************************************************************************************************
-/** 
+/**
 \defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs
 \ingroup DAP_ConfigIO_gr
 @{
@@ -602,13 +602,13 @@ __STATIC_INLINE void LED_RUNNING_OUT (uint32_t bit) {
 
 
 //**************************************************************************************************
-/** 
+/**
 \defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp
 \ingroup DAP_ConfigIO_gr
 @{
 Access function for Test Domain Timer.
 
-The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By 
+The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By
 default, the DWT timer is used.  The frequency of this timer is configured with \ref TIMESTAMP_CLOCK.
 
 */
@@ -624,7 +624,7 @@ __STATIC_INLINE uint32_t TIMESTAMP_GET (void) {
 
 
 //**************************************************************************************************
-/** 
+/**
 \defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
 \ingroup DAP_ConfigIO_gr
 @{
@@ -633,7 +633,7 @@ CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_S
 */
 
 /** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized).
-This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the 
+This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the
 Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set:
  - I/O clock system enabled.
  - all I/O pins: input buffer enabled, output pins are set to HighZ mode.
@@ -694,7 +694,7 @@ __STATIC_INLINE void DAP_SETUP (void) {
 
 /** Reset Target Device with custom specific I/O pin or command sequence.
 This function allows the optional implementation of a device specific reset sequence.
-It is called when the command \ref DAP_ResetTarget and is for example required 
+It is called when the command \ref DAP_ResetTarget and is for example required
 when a device needs a time-critical unlock sequence that enables the debug port.
 \return 0 = no device specific reset sequence is implemented.\n
         1 = a device specific reset sequence is implemented.

CMSIS/DAP/Firmware/Examples/LPC-Link2/README.md

@@ -0,0 +1,8 @@
+CMSIS-DAP v2 firmware for NXP LPC-Link2 debug probe.
+
+CMSIS-DAP v2 uses USB bulk endpoints for the communication with the host PC and is therefore faster.
+Optionally, support for streaming SWO trace is provided via an additional USB endpoint.
+
+Following targets are available:
+ - LPC-Link2: stand-alone debug probe
+ - LPC-Link2 on-board: on-board debug probe (LPC55S69-EVK, MIMXRT1064-EVK, ...)

CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/Abstract.txt

@@ -1,4 +0,0 @@
-CMSIS-DAP V1 USB HID Firmware for NXP LPC-Link2 debug probe.
-
-CMSIS-DAP with V1 configuration uses USB HID interface to host PC and is 
-therefore compatible with previous versions of CMSIS-DAP.

CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/CMSIS_DAP.uvprojx

@@ -1,664 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
-
-  <SchemaVersion>2.1</SchemaVersion>
-
-  <Header>### uVision Project, (C) Keil Software</Header>
-
-  <Targets>
-    <Target>
-      <TargetName>LPC-Link2</TargetName>
-      <ToolsetNumber>0x4</ToolsetNumber>
-      <ToolsetName>ARM-ADS</ToolsetName>
-      <pCCUsed>6160000::V6.16::ARMCLANG</pCCUsed>
-      <uAC6>1</uAC6>
-      <TargetOption>
-        <TargetCommonOption>
-          <Device>LPC4370:Cortex-M4</Device>
-          <Vendor>NXP</Vendor>
-          <PackID>Keil.LPC4300_DFP.2.9.0</PackID>
-          <PackURL>http://www.keil.com/pack/</PackURL>
-          <Cpu>IRAM(0x10000000,0x20000) IRAM2(0x20000000,0x10000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
-          <FlashUtilSpec></FlashUtilSpec>
-          <StartupFile></StartupFile>
-          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD10000000 -FC1000)</FlashDriverDll>
-          <DeviceId>0</DeviceId>
-          <RegisterFile>$$Device:LPC4370$Device\Include\LPC43xx.h</RegisterFile>
-          <MemoryEnv></MemoryEnv>
-          <Cmp></Cmp>
-          <Asm></Asm>
-          <Linker></Linker>
-          <OHString></OHString>
-          <InfinionOptionDll></InfinionOptionDll>
-          <SLE66CMisc></SLE66CMisc>
-          <SLE66AMisc></SLE66AMisc>
-          <SLE66LinkerMisc></SLE66LinkerMisc>
-          <SFDFile>$$Device:LPC4370$SVD\LPC43xx.svd</SFDFile>
-          <bCustSvd>0</bCustSvd>
-          <UseEnv>0</UseEnv>
-          <BinPath></BinPath>
-          <IncludePath></IncludePath>
-          <LibPath></LibPath>
-          <RegisterFilePath></RegisterFilePath>
-          <DBRegisterFilePath></DBRegisterFilePath>
-          <TargetStatus>
-            <Error>0</Error>
-            <ExitCodeStop>0</ExitCodeStop>
-            <ButtonStop>0</ButtonStop>
-            <NotGenerated>0</NotGenerated>
-            <InvalidFlash>1</InvalidFlash>
-          </TargetStatus>
-          <OutputDirectory>.\Objects\</OutputDirectory>
-          <OutputName>CMSIS_DAP</OutputName>
-          <CreateExecutable>1</CreateExecutable>
-          <CreateLib>0</CreateLib>
-          <CreateHexFile>1</CreateHexFile>
-          <DebugInformation>1</DebugInformation>
-          <BrowseInformation>1</BrowseInformation>
-          <ListingPath>.\Listings\</ListingPath>
-          <HexFormatSelection>1</HexFormatSelection>
-          <Merge32K>0</Merge32K>
-          <CreateBatchFile>0</CreateBatchFile>
-          <BeforeCompile>
-            <RunUserProg1>0</RunUserProg1>
-            <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name></UserProg1Name>
-            <UserProg2Name></UserProg2Name>
-            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
-            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
-            <nStopU1X>0</nStopU1X>
-            <nStopU2X>0</nStopU2X>
-          </BeforeCompile>
-          <BeforeMake>
-            <RunUserProg1>0</RunUserProg1>
-            <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name></UserProg1Name>
-            <UserProg2Name></UserProg2Name>
-            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
-            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
-            <nStopB1X>0</nStopB1X>
-            <nStopB2X>0</nStopB2X>
-          </BeforeMake>
-          <AfterMake>
-            <RunUserProg1>1</RunUserProg1>
-            <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name>fromelf.exe --bin -o  "$L@L.bin" "#L"</UserProg1Name>
-            <UserProg2Name></UserProg2Name>
-            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
-            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
-            <nStopA1X>0</nStopA1X>
-            <nStopA2X>0</nStopA2X>
-          </AfterMake>
-          <SelectedForBatchBuild>0</SelectedForBatchBuild>
-          <SVCSIdString></SVCSIdString>
-        </TargetCommonOption>
-        <CommonProperty>
-          <UseCPPCompiler>0</UseCPPCompiler>
-          <RVCTCodeConst>0</RVCTCodeConst>
-          <RVCTZI>0</RVCTZI>
-          <RVCTOtherData>0</RVCTOtherData>
-          <ModuleSelection>0</ModuleSelection>
-          <IncludeInBuild>1</IncludeInBuild>
-          <AlwaysBuild>0</AlwaysBuild>
-          <GenerateAssemblyFile>0</GenerateAssemblyFile>
-          <AssembleAssemblyFile>0</AssembleAssemblyFile>
-          <PublicsOnly>0</PublicsOnly>
-          <StopOnExitCode>3</StopOnExitCode>
-          <CustomArgument></CustomArgument>
-          <IncludeLibraryModules></IncludeLibraryModules>
-          <ComprImg>1</ComprImg>
-        </CommonProperty>
-        <DllOption>
-          <SimDllName>SARMCM3.DLL</SimDllName>
-          <SimDllArguments>  -MPU</SimDllArguments>
-          <SimDlgDll>DCM.DLL</SimDlgDll>
-          <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
-          <TargetDllName>SARMCM3.DLL</TargetDllName>
-          <TargetDllArguments> -MPU</TargetDllArguments>
-          <TargetDlgDll>TCM.DLL</TargetDlgDll>
-          <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
-        </DllOption>
-        <DebugOption>
-          <OPTHX>
-            <HexSelection>1</HexSelection>
-            <HexRangeLowAddress>0</HexRangeLowAddress>
-            <HexRangeHighAddress>0</HexRangeHighAddress>
-            <HexOffset>0</HexOffset>
-            <Oh166RecLen>16</Oh166RecLen>
-          </OPTHX>
-        </DebugOption>
-        <Utilities>
-          <Flash1>
-            <UseTargetDll>1</UseTargetDll>
-            <UseExternalTool>0</UseExternalTool>
-            <RunIndependent>0</RunIndependent>
-            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
-            <Capability>1</Capability>
-            <DriverSelection>4096</DriverSelection>
-          </Flash1>
-          <bUseTDR>1</bUseTDR>
-          <Flash2>BIN\UL2CM3.DLL</Flash2>
-          <Flash3></Flash3>
-          <Flash4></Flash4>
-          <pFcarmOut></pFcarmOut>
-          <pFcarmGrp></pFcarmGrp>
-          <pFcArmRoot></pFcArmRoot>
-          <FcArmLst>0</FcArmLst>
-        </Utilities>
-        <TargetArmAds>
-          <ArmAdsMisc>
-            <GenerateListings>0</GenerateListings>
-            <asHll>1</asHll>
-            <asAsm>1</asAsm>
-            <asMacX>1</asMacX>
-            <asSyms>1</asSyms>
-            <asFals>1</asFals>
-            <asDbgD>1</asDbgD>
-            <asForm>1</asForm>
-            <ldLst>0</ldLst>
-            <ldmm>1</ldmm>
-            <ldXref>1</ldXref>
-            <BigEnd>0</BigEnd>
-            <AdsALst>1</AdsALst>
-            <AdsACrf>1</AdsACrf>
-            <AdsANop>0</AdsANop>
-            <AdsANot>0</AdsANot>
-            <AdsLLst>1</AdsLLst>
-            <AdsLmap>1</AdsLmap>
-            <AdsLcgr>1</AdsLcgr>
-            <AdsLsym>1</AdsLsym>
-            <AdsLszi>1</AdsLszi>
-            <AdsLtoi>1</AdsLtoi>
-            <AdsLsun>1</AdsLsun>
-            <AdsLven>1</AdsLven>
-            <AdsLsxf>1</AdsLsxf>
-            <RvctClst>0</RvctClst>
-            <GenPPlst>0</GenPPlst>
-            <AdsCpuType>"Cortex-M4"</AdsCpuType>
-            <RvctDeviceName></RvctDeviceName>
-            <mOS>1</mOS>
-            <uocRom>0</uocRom>
-            <uocRam>0</uocRam>
-            <hadIROM>0</hadIROM>
-            <hadIRAM>1</hadIRAM>
-            <hadXRAM>0</hadXRAM>
-            <uocXRam>0</uocXRam>
-            <RvdsVP>2</RvdsVP>
-            <RvdsMve>0</RvdsMve>
-            <RvdsCdeCp>0</RvdsCdeCp>
-            <hadIRAM2>1</hadIRAM2>
-            <hadIROM2>0</hadIROM2>
-            <StupSel>1</StupSel>
-            <useUlib>1</useUlib>
-            <EndSel>0</EndSel>
-            <uLtcg>0</uLtcg>
-            <nSecure>0</nSecure>
-            <RoSelD>0</RoSelD>
-            <RwSelD>4</RwSelD>
-            <CodeSel>0</CodeSel>
-            <OptFeed>0</OptFeed>
-            <NoZi1>0</NoZi1>
-            <NoZi2>0</NoZi2>
-            <NoZi3>0</NoZi3>
-            <NoZi4>0</NoZi4>
-            <NoZi5>0</NoZi5>
-            <Ro1Chk>1</Ro1Chk>
-            <Ro2Chk>0</Ro2Chk>
-            <Ro3Chk>0</Ro3Chk>
-            <Ir1Chk>0</Ir1Chk>
-            <Ir2Chk>0</Ir2Chk>
-            <Ra1Chk>0</Ra1Chk>
-            <Ra2Chk>0</Ra2Chk>
-            <Ra3Chk>0</Ra3Chk>
-            <Im1Chk>1</Im1Chk>
-            <Im2Chk>1</Im2Chk>
-            <OnChipMemories>
-              <Ocm1>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm1>
-              <Ocm2>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm2>
-              <Ocm3>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm3>
-              <Ocm4>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm4>
-              <Ocm5>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm5>
-              <Ocm6>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm6>
-              <IRAM>
-                <Type>0</Type>
-                <StartAddress>0x10000000</StartAddress>
-                <Size>0x20000</Size>
-              </IRAM>
-              <IROM>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </IROM>
-              <XRAM>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </XRAM>
-              <OCR_RVCT1>
-                <Type>1</Type>
-                <StartAddress>0x14000000</StartAddress>
-                <Size>0x400000</Size>
-              </OCR_RVCT1>
-              <OCR_RVCT2>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT2>
-              <OCR_RVCT3>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT3>
-              <OCR_RVCT4>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT4>
-              <OCR_RVCT5>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT5>
-              <OCR_RVCT6>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT6>
-              <OCR_RVCT7>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT7>
-              <OCR_RVCT8>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT8>
-              <OCR_RVCT9>
-                <Type>0</Type>
-                <StartAddress>0x10000000</StartAddress>
-                <Size>0x20000</Size>
-              </OCR_RVCT9>
-              <OCR_RVCT10>
-                <Type>0</Type>
-                <StartAddress>0x20000000</StartAddress>
-                <Size>0x10000</Size>
-              </OCR_RVCT10>
-            </OnChipMemories>
-            <RvctStartVector></RvctStartVector>
-          </ArmAdsMisc>
-          <Cads>
-            <interw>1</interw>
-            <Optim>4</Optim>
-            <oTime>0</oTime>
-            <SplitLS>0</SplitLS>
-            <OneElfS>0</OneElfS>
-            <Strict>0</Strict>
-            <EnumInt>0</EnumInt>
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-            <Ropi>0</Ropi>
-            <Rwpi>0</Rwpi>
-            <wLevel>3</wLevel>
-            <uThumb>0</uThumb>
-            <uSurpInc>0</uSurpInc>
-            <uC99>0</uC99>
-            <uGnu>0</uGnu>
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-            <v6LangP>3</v6LangP>
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-            <v6WtE>0</v6WtE>
-            <v6Rtti>0</v6Rtti>
-            <VariousControls>
-              <MiscControls></MiscControls>
-              <Define>DAP_FW_V1</Define>
-              <Undefine></Undefine>
-              <IncludePath>.;..\..\..\Include</IncludePath>
-            </VariousControls>
-          </Cads>
-          <Aads>
-            <interw>1</interw>
-            <Ropi>0</Ropi>
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-            <thumb>0</thumb>
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-            <SwStkChk>0</SwStkChk>
-            <NoWarn>0</NoWarn>
-            <uSurpInc>0</uSurpInc>
-            <useXO>0</useXO>
-            <ClangAsOpt>1</ClangAsOpt>
-            <VariousControls>
-              <MiscControls></MiscControls>
-              <Define></Define>
-              <Undefine></Undefine>
-              <IncludePath></IncludePath>
-            </VariousControls>
-          </Aads>
-          <LDads>
-            <umfTarg>1</umfTarg>
-            <Ropi>0</Ropi>
-            <Rwpi>0</Rwpi>
-            <noStLib>0</noStLib>
-            <RepFail>1</RepFail>
-            <useFile>0</useFile>
-            <TextAddressRange>0x00000000</TextAddressRange>
-            <DataAddressRange>0x10000000</DataAddressRange>
-            <pXoBase></pXoBase>
-            <ScatterFile></ScatterFile>
-            <IncludeLibs></IncludeLibs>
-            <IncludeLibsPath></IncludeLibsPath>
-            <Misc></Misc>
-            <LinkerInputFile></LinkerInputFile>
-            <DisabledWarnings></DisabledWarnings>
-          </LDads>
-        </TargetArmAds>
-      </TargetOption>
-      <Groups>
-        <Group>
-          <GroupName>Source</GroupName>
-          <Files>
-            <File>
-              <FileName>main.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>.\main.c</FilePath>
-            </File>
-            <File>
-              <FileName>USBD_User_HID_0.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>.\USBD_User_HID_0.c</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>Documentation</GroupName>
-          <Files>
-            <File>
-              <FileName>Abstract.txt</FileName>
-              <FileType>5</FileType>
-              <FilePath>.\Abstract.txt</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>CMSIS DAP</GroupName>
-          <Files>
-            <File>
-              <FileName>DAP_config.h</FileName>
-              <FileType>5</FileType>
-              <FilePath>.\DAP_config.h</FilePath>
-            </File>
-            <File>
-              <FileName>DAP.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Source\DAP.c</FilePath>
-            </File>
-            <File>
-              <FileName>JTAG_DP.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Source\JTAG_DP.c</FilePath>
-            </File>
-            <File>
-              <FileName>SW_DP.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Source\SW_DP.c</FilePath>
-            </File>
-            <File>
-              <FileName>SWO.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\Source\SWO.c</FilePath>
-              <FileOption>
-                <CommonProperty>
-                  <UseCPPCompiler>2</UseCPPCompiler>
-                  <RVCTCodeConst>0</RVCTCodeConst>
-                  <RVCTZI>0</RVCTZI>
-                  <RVCTOtherData>0</RVCTOtherData>
-                  <ModuleSelection>0</ModuleSelection>
-                  <IncludeInBuild>2</IncludeInBuild>
-                  <AlwaysBuild>2</AlwaysBuild>
-                  <GenerateAssemblyFile>2</GenerateAssemblyFile>
-                  <AssembleAssemblyFile>2</AssembleAssemblyFile>
-                  <PublicsOnly>2</PublicsOnly>
-                  <StopOnExitCode>11</StopOnExitCode>
-                  <CustomArgument></CustomArgument>
-                  <IncludeLibraryModules></IncludeLibraryModules>
-                  <ComprImg>1</ComprImg>
-                </CommonProperty>
-                <FileArmAds>
-                  <Cads>
-                    <interw>2</interw>
-                    <Optim>0</Optim>
-                    <oTime>2</oTime>
-                    <SplitLS>2</SplitLS>
-                    <OneElfS>2</OneElfS>
-                    <Strict>2</Strict>
-                    <EnumInt>2</EnumInt>
-                    <PlainCh>2</PlainCh>
-                    <Ropi>2</Ropi>
-                    <Rwpi>2</Rwpi>
-                    <wLevel>2</wLevel>
-                    <uThumb>2</uThumb>
-                    <uSurpInc>2</uSurpInc>
-                    <uC99>2</uC99>
-                    <uGnu>2</uGnu>
-                    <useXO>2</useXO>
-                    <v6Lang>0</v6Lang>
-                    <v6LangP>0</v6LangP>
-                    <vShortEn>2</vShortEn>
-                    <vShortWch>2</vShortWch>
-                    <v6Lto>2</v6Lto>
-                    <v6WtE>2</v6WtE>
-                    <v6Rtti>2</v6Rtti>
-                    <VariousControls>
-                      <MiscControls></MiscControls>
-                      <Define>USART_PORT=1</Define>
-                      <Undefine></Undefine>
-                      <IncludePath></IncludePath>
-                    </VariousControls>
-                  </Cads>
-                </FileArmAds>
-              </FileOption>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>::CMSIS</GroupName>
-        </Group>
-        <Group>
-          <GroupName>::CMSIS Driver</GroupName>
-        </Group>
-        <Group>
-          <GroupName>::Device</GroupName>
-        </Group>
-        <Group>
-          <GroupName>::USB</GroupName>
-        </Group>
-      </Groups>
-    </Target>
-  </Targets>
-
-  <RTE>
-    <apis>
-      <api Capiversion="2.01" Cclass="CMSIS Driver" Cgroup="USART" exclusive="0">
-        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.3.0"/>
-        <targetInfos>
-          <targetInfo name="LPC-Link2"/>
-        </targetInfos>
-      </api>
-      <api Capiversion="2.01" Cclass="CMSIS Driver" Cgroup="USB Device" exclusive="0">
-        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.3.0"/>
-        <targetInfos>
-          <targetInfo name="LPC-Link2"/>
-        </targetInfos>
-      </api>
-      <api Capiversion="2.1.2" Cclass="CMSIS" Cgroup="RTOS2" exclusive="1">
-        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.2.0"/>
-        <targetInfos>
-          <targetInfo name="LPC-Link2"/>
-        </targetInfos>
-      </api>
-    </apis>
-    <components>
-      <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.4.0" condition="ARMv6_7_8-M Device">
-        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0"/>
-        <targetInfos>
-          <targetInfo name="LPC-Link2"/>
-        </targetInfos>
-      </component>
-      <component Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cvendor="ARM" Cversion="5.5.2" condition="RTOS2 RTX5">
-        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.7.0"/>
-        <targetInfos>
-          <targetInfo name="LPC-Link2"/>
-        </targetInfos>
-      </component>
-      <component Cbundle="MDK-Pro" Cclass="USB" Cgroup="CORE" Cvariant="Release" Cvendor="Keil" Cversion="6.14.4" condition="USB Core">
-        <package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.12.1-dev21-emWin"/>
-        <targetInfos>
-          <targetInfo name="LPC-Link2"/>
-        </targetInfos>
-      </component>
-      <component Cbundle="MDK-Pro" Cclass="USB" Cgroup="Device" Cvendor="Keil" Cversion="6.14.4" condition="USB Core and Device Instance and Device Driver" maxInstances="4">
-        <package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.12.1-dev21-emWin"/>
-        <targetInfos>
-          <targetInfo name="LPC-Link2"/>
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-      </component>
-      <component Cbundle="MDK-Pro" Cclass="USB" Cgroup="Device" Csub="HID" Cvendor="Keil" Cversion="6.14.4" condition="USB Core and Device Instance and Device Driver" maxInstances="4">
-        <package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.12.1-dev21-emWin"/>
-        <targetInfos>
-          <targetInfo name="LPC-Link2"/>
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-      <component Capiversion="2.1" Cclass="CMSIS Driver" Cgroup="USART" Cvendor="Keil" Cversion="2.14" condition="LPC4300 CMSIS SCU GPDMA">
-        <package name="LPC4300_DFP" schemaVersion="1.4.9" url="http://www.keil.com/pack/" vendor="Keil" version="2.9.0"/>
-        <targetInfos>
-          <targetInfo name="LPC-Link2"/>
-        </targetInfos>
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-      <component Capiversion="2.1" Cclass="CMSIS Driver" Cgroup="USB Device" Csub="USB0" Cvendor="Keil" Cversion="2.12" condition="LPC4300 CMSIS SCU">
-        <package name="LPC4300_DFP" schemaVersion="1.4.9" url="http://www.keil.com/pack/" vendor="Keil" version="2.9.0"/>
-        <targetInfos>
-          <targetInfo name="LPC-Link2"/>
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-      <component Cclass="Device" Cgroup="GPDMA" Cvendor="Keil" Cversion="1.6" condition="LPC4300 CMSIS">
-        <package name="LPC4300_DFP" schemaVersion="1.4.9" url="http://www.keil.com/pack/" vendor="Keil" version="2.9.0"/>
-        <targetInfos>
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-      <component Cclass="Device" Cgroup="SCU" Cvendor="Keil" Cversion="1.1" condition="LPC4300 CMSIS">
-        <package name="LPC4300_DFP" schemaVersion="1.4.9" url="http://www.keil.com/pack/" vendor="Keil" version="2.9.0"/>
-        <targetInfos>
-          <targetInfo name="LPC-Link2"/>
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-      <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="LPC4300 CMSIS">
-        <package name="LPC4300_DFP" schemaVersion="1.4.9" url="http://www.keil.com/pack/" vendor="Keil" version="2.9.0"/>
-        <targetInfos>
-          <targetInfo name="LPC-Link2">
-            <c>
-              <Define>USE_SPIFI=1</Define>
-            </c>
-            <asm>
-              <Define>NO_CRP</Define>
-            </asm>
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-      </component>
-    </components>
-    <files>
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-      <file attr="config" category="source" condition="CM4 ARM Compiler" name="Device\Source\ARM\startup_LPC43xx.s" version="1.0.0">
-        <instance index="0">RTE\Device\LPC4370_Cortex-M4\startup_LPC43xx.s</instance>
-        <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="LPC4300 CMSIS"/>
-        <package name="LPC4300_DFP" schemaVersion="1.4.9" url="http://www.keil.com/pack/" vendor="Keil" version="2.9.0"/>
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-          <targetInfo name="LPC-Link2"/>
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-      </file>
-      <file attr="config" category="source" condition="CM4" name="Device\Source\system_LPC43xx.c" version="1.0.3">
-        <instance index="0">RTE\Device\LPC4370_Cortex-M4\system_LPC43xx.c</instance>
-        <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="LPC4300 CMSIS"/>
-        <package name="LPC4300_DFP" schemaVersion="1.4.9" url="http://www.keil.com/pack/" vendor="Keil" version="2.9.0"/>
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-      <file attr="config" category="source" name="USB\Config\USBD_Config.c" version="5.2.0">
-        <instance index="0">RTE\USB\USBD_Config_0.c</instance>
-        <component Cbundle="MDK-Pro" Cclass="USB" Cgroup="Device" Cvendor="Keil" Cversion="6.15.0" condition="USB Core and Device Instance and Device Driver" maxInstances="4"/>
-        <package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.13.0"/>
-        <targetInfos>
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-      <file attr="config" category="header" name="USB\Config\USBD_Config_HID.h" version="5.0.2">
-        <instance index="0">RTE\USB\USBD_Config_HID_0.h</instance>
-        <component Cbundle="MDK-Pro" Cclass="USB" Cgroup="Device" Csub="HID" Cvendor="Keil" Cversion="6.15.0" condition="USB Core and Device Instance and Device Driver" maxInstances="4"/>
-        <package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.13.0"/>
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-    </files>
-  </RTE>
-
-  <LayerInfo>
-    <Layers>
-      <Layer>
-        <LayName>CMSIS_DAP</LayName>
-        <LayPrjMark>1</LayPrjMark>
-      </Layer>
-    </Layers>
-  </LayerInfo>
-
-</Project>

CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/Objects/CMSIS_DAP.hex

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CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/RTE/Device/LPC4370_Cortex-M4/RTE_Device.h

@@ -1,2483 +0,0 @@
-/* -------------------------------------------------------------------------- 
- * Copyright (c) 2013-2016 Arm Limited (or its affiliates). All 
- * rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * $Date:        25. April 2016
- * $Revision:    V2.2.1
- *
- * Project:      RTE Device Configuration for NXP LPC43xx
- * -------------------------------------------------------------------------- */
-
-//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
-
-#ifndef __RTE_DEVICE_H
-#define __RTE_DEVICE_H
-
-
-// <e> USB0 Controller [Driver_USBD0 and Driver_USBH0]
-// <i> Configuration settings for Driver_USBD0 in component ::Drivers:USB Device
-// <i> Configuration settings for Driver_USBH0 in component ::Drivers:USB Host
-#define   RTE_USB_USB0                  1
-
-//   <h> Pin Configuration
-//     <o> USB0_PPWR (Host) <0=>Not used <1=>P1_7 <2=>P2_0 <3=>P2_3 <4=>P6_3
-//     <i> VBUS drive signal (towards external charge pump or power management unit).
-#define   RTE_USB0_PPWR_ID              0
-#if      (RTE_USB0_PPWR_ID == 0)
-  #define RTE_USB0_PPWR_PIN_EN          0
-#elif    (RTE_USB0_PPWR_ID == 1)
-  #define RTE_USB0_PPWR_PORT            1
-  #define RTE_USB0_PPWR_BIT             7
-  #define RTE_USB0_PPWR_FUNC            4
-#elif    (RTE_USB0_PPWR_ID == 2)
-  #define RTE_USB0_PPWR_PORT            2
-  #define RTE_USB0_PPWR_BIT             0
-  #define RTE_USB0_PPWR_FUNC            3
-#elif    (RTE_USB0_PPWR_ID == 3)
-  #define RTE_USB0_PPWR_PORT            2
-  #define RTE_USB0_PPWR_BIT             3
-  #define RTE_USB0_PPWR_FUNC            7
-#elif    (RTE_USB0_PPWR_ID == 4)
-  #define RTE_USB0_PPWR_PORT            6
-  #define RTE_USB0_PPWR_BIT             3
-  #define RTE_USB0_PPWR_FUNC            1
-#else
-  #error "Invalid RTE_USB0_PPWR Pin Configuration!"
-#endif
-#ifndef   RTE_USB0_PPWR_PIN_EN
-  #define RTE_USB0_PPWR_PIN_EN          1
-#endif
-//     <o> USB0_PWR_FAULT (Host) <0=>Not used <1=>P1_5 <2=>P2_1 <3=>P2_4 <4=>P6_6 <5=>P8_0
-//     <i> Port power fault signal indicating overcurrent condition.
-//     <i> This signal monitors over-current on the USB bus
-//        (external circuitry required to detect over-current condition).
-#define   RTE_USB0_PWR_FAULT_ID         0
-#if      (RTE_USB0_PWR_FAULT_ID == 0)
-  #define RTE_USB0_PWR_FAULT_PIN_EN     0
-#elif    (RTE_USB0_PWR_FAULT_ID == 1)
-  #define RTE_USB0_PWR_FAULT_PORT       1
-  #define RTE_USB0_PWR_FAULT_BIT        5
-  #define RTE_USB0_PWR_FAULT_FUNC       4
-#elif    (RTE_USB0_PWR_FAULT_ID == 2)
-  #define RTE_USB0_PWR_FAULT_PORT       2
-  #define RTE_USB0_PWR_FAULT_BIT        1
-  #define RTE_USB0_PWR_FAULT_FUNC       3
-#elif    (RTE_USB0_PWR_FAULT_ID == 3)
-  #define RTE_USB0_PWR_FAULT_PORT       2
-  #define RTE_USB0_PWR_FAULT_BIT        4
-  #define RTE_USB0_PWR_FAULT_FUNC       7
-#elif    (RTE_USB0_PWR_FAULT_ID == 4)
-  #define RTE_USB0_PWR_FAULT_PORT       6
-  #define RTE_USB0_PWR_FAULT_BIT        6
-  #define RTE_USB0_PWR_FAULT_FUNC       3
-#elif    (RTE_USB0_PWR_FAULT_ID == 5)
-  #define RTE_USB0_PWR_FAULT_PORT       8
-  #define RTE_USB0_PWR_FAULT_BIT        0
-  #define RTE_USB0_PWR_FAULT_FUNC       1
-#else
-  #error "Invalid RTE_USB0_PWR_FAULT Pin Configuration!"
-#endif
-#ifndef   RTE_USB0_PWR_FAULT_PIN_EN
-  #define RTE_USB0_PWR_FAULT_PIN_EN     1
-#endif
-//     <o> USB0_IND0 <0=>Not used <1=>P1_4 <2=>P2_5 <3=>P2_6 <4=>P6_8 <5=>P8_2
-//     <i> USB0 port indicator LED control output 0
-#define   RTE_USB0_IND0_ID              0
-#if      (RTE_USB0_IND0_ID == 0)
-  #define RTE_USB0_IND0_PIN_EN          0
-#elif    (RTE_USB0_IND0_ID == 1)
-  #define RTE_USB0_IND0_PORT            1
-  #define RTE_USB0_IND0_BIT             4
-  #define RTE_USB0_IND0_FUNC            4
-#elif    (RTE_USB0_IND0_ID == 2)
-  #define RTE_USB0_IND0_PORT            2
-  #define RTE_USB0_IND0_BIT             5
-  #define RTE_USB0_IND0_FUNC            7
-#elif    (RTE_USB0_IND0_ID == 3)
-  #define RTE_USB0_IND0_PORT            2
-  #define RTE_USB0_IND0_BIT             6
-  #define RTE_USB0_IND0_FUNC            3
-#elif    (RTE_USB0_IND0_ID == 4)
-  #define RTE_USB0_IND0_PORT            6
-  #define RTE_USB0_IND0_BIT             8
-  #define RTE_USB0_IND0_FUNC            3
-#elif    (RTE_USB0_IND0_ID == 5)
-  #define RTE_USB0_IND0_PORT            8
-  #define RTE_USB0_IND0_BIT             2
-  #define RTE_USB0_IND0_FUNC            1
-#else
-  #error "Invalid RTE_USB0_IND0 Pin Configuration!"
-#endif
-#ifndef   RTE_USB0_IND0_PIN_EN
-  #define RTE_USB0_IND0_PIN_EN          1
-#endif
-//     <o> USB0_IND1 <0=>Not used <1=>P1_3 <2=>P2_2 <3=>P6_7 <4=>P8_1
-//     <i> USB0 port indicator LED control output 1
-#define   RTE_USB0_IND1_ID              0
-#if      (RTE_USB0_IND1_ID == 0)
-  #define RTE_USB0_IND1_PIN_EN          0
-#elif    (RTE_USB0_IND1_ID == 1)
-  #define RTE_USB0_IND1_PORT            1
-  #define RTE_USB0_IND1_BIT             3
-  #define RTE_USB0_IND1_FUNC            4
-#elif    (RTE_USB0_IND1_ID == 2)
-  #define RTE_USB0_IND1_PORT            2
-  #define RTE_USB0_IND1_BIT             2
-  #define RTE_USB0_IND1_FUNC            3
-#elif    (RTE_USB0_IND1_ID == 3)
-  #define RTE_USB0_IND1_PORT            6
-  #define RTE_USB0_IND1_BIT             7
-  #define RTE_USB0_IND1_FUNC            3
-#elif    (RTE_USB0_IND1_ID == 4)
-  #define RTE_USB0_IND1_PORT            8
-  #define RTE_USB0_IND1_BIT             1
-  #define RTE_USB0_IND1_FUNC            1
-#else
-  #error "Invalid RTE_USB0_IND1 Pin Configuration!"
-#endif
-#ifndef   RTE_USB0_IND1_PIN_EN
-  #define RTE_USB0_IND1_PIN_EN          1
-#endif
-//   </h> Pin Configuration
-
-//   <h> Device [Driver_USBD0]
-//   <i> Configuration settings for Driver_USBD0 in component ::Drivers:USB Device
-//     <o.0> High-speed
-//     <i> Enable high-speed functionality
-#define   RTE_USB_USB0_HS_EN            1
-//   </h> Device [Driver_USBD0]
-// </e> USB0 Controller [Driver_USBD0 and Driver_USBH0]
-
-// <e> USB1 Controller [Driver_USBD1 and Driver_USBH1]
-// <i> Configuration settings for Driver_USBD1 in component ::Drivers:USB Device
-// <i> Configuration settings for Driver_USBH1 in component ::Drivers:USB Host
-#define   RTE_USB_USB1                  0
-
-//   <h> Pin Configuration
-//     <o> USB1_PPWR (Host) <0=>Not used <1=>P9_5
-//     <i> VBUS drive signal (towards external charge pump or power management unit).
-#define   RTE_USB1_PPWR_ID              1
-#if      (RTE_USB1_PPWR_ID == 0)
-  #define RTE_USB1_PPWR_PIN_EN          0
-#elif    (RTE_USB1_PPWR_ID == 1)
-  #define RTE_USB1_PPWR_PORT            9
-  #define RTE_USB1_PPWR_BIT             5
-  #define RTE_USB1_PPWR_FUNC            2
-#else
-  #error "Invalid RTE_USB1_PPWR Pin Configuration!"
-#endif
-#ifndef   RTE_USB1_PPWR_PIN_EN
-  #define RTE_USB1_PPWR_PIN_EN          1
-#endif
-//     <o> USB1_PWR_FAULT (Host) <0=>Not used <1=>P9_6
-//     <i> Port power fault signal indicating overcurrent condition.
-//     <i> This signal monitors over-current on the USB bus
-//        (external circuitry required to detect over-current condition).
-#define   RTE_USB1_PWR_FAULT_ID         1
-#if      (RTE_USB1_PWR_FAULT_ID == 0)
-  #define RTE_USB1_PWR_FAULT_PIN_EN     0
-#elif    (RTE_USB1_PWR_FAULT_ID == 1)
-  #define RTE_USB1_PWR_FAULT_PORT       9
-  #define RTE_USB1_PWR_FAULT_BIT        6
-  #define RTE_USB1_PWR_FAULT_FUNC       2
-#else
-  #error "Invalid RTE_USB1_PWR_FAULT Pin Configuration!"
-#endif
-#ifndef   RTE_USB1_PWR_FAULT_PIN_EN
-  #define RTE_USB1_PWR_FAULT_PIN_EN     1
-#endif
-//     <o> USB1_IND0 <0=>Not used <1=>P3_2 <2=>P9_4
-//     <i> USB1 port indicator LED control output 0
-#define   RTE_USB1_IND0_ID              1
-#if      (RTE_USB1_IND0_ID == 0)
-  #define RTE_USB1_IND0_PIN_EN          0
-#elif    (RTE_USB1_IND0_ID == 1)
-  #define RTE_USB1_IND0_PORT            3
-  #define RTE_USB1_IND0_BIT             2
-  #define RTE_USB1_IND0_FUNC            3
-#elif    (RTE_USB1_IND0_ID == 2)
-  #define RTE_USB1_IND0_PORT            9
-  #define RTE_USB1_IND0_BIT             4
-  #define RTE_USB1_IND0_FUNC            2
-#else
-  #error "Invalid RTE_USB1_IND0 Pin Configuration!"
-#endif
-#ifndef   RTE_USB1_IND0_PIN_EN
-  #define RTE_USB1_IND0_PIN_EN          1
-#endif
-//     <o> USB1_IND1 <0=>Not used <1=>P3_1 <2=>P9_3
-//     <i> USB1 port indicator LED control output 1
-#define   RTE_USB1_IND1_ID              1
-#if      (RTE_USB1_IND1_ID == 0)
-  #define RTE_USB1_IND1_PIN_EN          0
-#elif    (RTE_USB1_IND1_ID == 1)
-  #define RTE_USB1_IND1_PORT            3
-  #define RTE_USB1_IND1_BIT             1
-  #define RTE_USB1_IND1_FUNC            3
-#elif    (RTE_USB1_IND1_ID == 2)
-  #define RTE_USB1_IND1_PORT            9
-  #define RTE_USB1_IND1_BIT             3
-  #define RTE_USB1_IND1_FUNC            2
-#else
-  #error "Invalid RTE_USB1_IND1 Pin Configuration!"
-#endif
-#ifndef   RTE_USB1_IND1_PIN_EN
-  #define RTE_USB1_IND1_PIN_EN          1
-#endif
-
-//     <e> On-chip full-speed PHY
-#define   RTE_USB_USB1_FS_PHY_EN        1
-
-//       <o> USB1_VBUS (Device) <0=>Not used <1=>P2_5
-//       <i> Monitors the presence of USB1 bus power.
-#define   RTE_USB1_VBUS_ID              1
-#if      (RTE_USB1_VBUS_ID == 0)
-  #define RTE_USB1_VBUS_PIN_EN          0
-#elif    (RTE_USB1_VBUS_ID == 1)
-  #define RTE_USB1_VBUS_PORT            2
-  #define RTE_USB1_VBUS_BIT             5
-  #define RTE_USB1_VBUS_FUNC            2
-#else
-  #error "Invalid RTE_USB1_VBUS Pin Configuration!"
-#endif
-#ifndef   RTE_USB1_VBUS_PIN_EN
-  #define RTE_USB1_VBUS_PIN_EN          1
-#endif
-//     </e> On-chip full-speed PHY
-
-//     <e> External high-speed ULPI PHY (UTMI+ Low Pin Interface)
-#define   RTE_USB_USB1_HS_PHY_EN        0
-
-//       <o> USB1_ULPI_CLK <0=>P8_8 <1=>PC_0
-//       <i> USB1 ULPI link CLK signal.
-//       <i> 60 MHz clock generated by the PHY.
-#define   RTE_USB1_ULPI_CLK_ID          0
-#if      (RTE_USB1_ULPI_CLK_ID == 0)
-  #define RTE_USB1_ULPI_CLK_PORT        8
-  #define RTE_USB1_ULPI_CLK_BIT         8
-  #define RTE_USB1_ULPI_CLK_FUNC        1
-#elif    (RTE_USB1_ULPI_CLK_ID == 1)
-  #define RTE_USB1_ULPI_CLK_PORT        0xC
-  #define RTE_USB1_ULPI_CLK_BIT         0
-  #define RTE_USB1_ULPI_CLK_FUNC        1
-#else
-  #error "Invalid RTE_USB1_ULPI_CLK Pin Configuration!"
-#endif
-//       <o> USB1_ULPI_DIR <0=>PB_1 <1=>PC_11
-//       <i> USB1 ULPI link DIR signal.
-//       <i> Controls the ULPI data line direction.
-#define   RTE_USB1_ULPI_DIR_ID          0
-#if      (RTE_USB1_ULPI_DIR_ID == 0)
-  #define RTE_USB1_ULPI_DIR_PORT        0xB
-  #define RTE_USB1_ULPI_DIR_BIT         1
-  #define RTE_USB1_ULPI_DIR_FUNC        1
-#elif    (RTE_USB1_ULPI_DIR_ID == 1)
-  #define RTE_USB1_ULPI_DIR_PORT        0xC
-  #define RTE_USB1_ULPI_DIR_BIT         11
-  #define RTE_USB1_ULPI_DIR_FUNC        1
-#else
-  #error "Invalid RTE_USB1_ULPI_DIR Pin Configuration!"
-#endif
-//       <o> USB1_ULPI_STP <0=>P8_7 <1=>PC_10
-//       <i> USB1 ULPI link STP signal.
-//       <i> Asserted to end or interrupt transfers to the PHY.
-#define   RTE_USB1_ULPI_STP_ID          0
-#if      (RTE_USB1_ULPI_STP_ID == 0)
-  #define RTE_USB1_ULPI_STP_PORT        8
-  #define RTE_USB1_ULPI_STP_BIT         7
-  #define RTE_USB1_ULPI_STP_FUNC        1
-#elif    (RTE_USB1_ULPI_STP_ID == 1)
-  #define RTE_USB1_ULPI_STP_PORT        0xC
-  #define RTE_USB1_ULPI_STP_BIT         10
-  #define RTE_USB1_ULPI_STP_FUNC        1
-#else
-  #error "Invalid RTE_USB1_ULPI_STP Pin Configuration!"
-#endif
-//       <o> USB1_ULPI_NXT <0=>P8_6 <1=>PC_9
-//       <i> USB1 ULPI link NXT signal.
-//       <i> Data flow control signal from the PHY.
-#define   RTE_USB1_ULPI_NXT_ID          0
-#if      (RTE_USB1_ULPI_NXT_ID == 0)
-  #define RTE_USB1_ULPI_NXT_PORT        8
-  #define RTE_USB1_ULPI_NXT_BIT         6
-  #define RTE_USB1_ULPI_NXT_FUNC        1
-#elif    (RTE_USB1_ULPI_NXT_ID == 1)
-  #define RTE_USB1_ULPI_NXT_PORT        0xC
-  #define RTE_USB1_ULPI_NXT_BIT         9
-  #define RTE_USB1_ULPI_NXT_FUNC        1
-#else
-  #error "Invalid RTE_USB1_ULPI_NXT Pin Configuration!"
-#endif
-//       <o> USB1_ULPI_D0 <0=>P8_5 <1=>PC_8 <2=>PD_11
-//       <i> USB1 ULPI link bidirectional data line 0.
-#define   RTE_USB1_ULPI_D0_ID           0
-#if      (RTE_USB1_ULPI_D0_ID == 0)
-  #define RTE_USB1_ULPI_D0_PORT         8
-  #define RTE_USB1_ULPI_D0_BIT          5
-  #define RTE_USB1_ULPI_D0_FUNC         1
-#elif    (RTE_USB1_ULPI_D0_ID == 1)
-  #define RTE_USB1_ULPI_D0_PORT         0xC
-  #define RTE_USB1_ULPI_D0_BIT          8
-  #define RTE_USB1_ULPI_D0_FUNC         1
-#elif    (RTE_USB1_ULPI_D0_ID == 2)
-  #define RTE_USB1_ULPI_D0_PORT         0xD
-  #define RTE_USB1_ULPI_D0_BIT          11
-  #define RTE_USB1_ULPI_D0_FUNC         5
-#else
-  #error "Invalid RTE_USB1_ULPI_D0 Pin Configuration!"
-#endif
-//       <o> USB1_ULPI_D1 <0=>P8_4 <1=>PC_7
-//       <i> USB1 ULPI link bidirectional data line 1.
-#define   RTE_USB1_ULPI_D1_ID           0
-#if      (RTE_USB1_ULPI_D1_ID == 0)
-  #define RTE_USB1_ULPI_D1_PORT         8
-  #define RTE_USB1_ULPI_D1_BIT          4
-  #define RTE_USB1_ULPI_D1_FUNC         1
-#elif    (RTE_USB1_ULPI_D1_ID == 1)
-  #define RTE_USB1_ULPI_D1_PORT         0xC
-  #define RTE_USB1_ULPI_D1_BIT          7
-  #define RTE_USB1_ULPI_D1_FUNC         1
-#else
-  #error "Invalid RTE_USB1_ULPI_D1 Pin Configuration!"
-#endif
-//       <o> USB1_ULPI_D2 <0=>P8_3 <1=>PC_6
-//       <i> USB1 ULPI link bidirectional data line 2.
-#define   RTE_USB1_ULPI_D2_ID           0
-#if      (RTE_USB1_ULPI_D2_ID == 0)
-  #define RTE_USB1_ULPI_D2_PORT         8
-  #define RTE_USB1_ULPI_D2_BIT          3
-  #define RTE_USB1_ULPI_D2_FUNC         1
-#elif    (RTE_USB1_ULPI_D2_ID == 1)
-  #define RTE_USB1_ULPI_D2_PORT         0xC
-  #define RTE_USB1_ULPI_D2_BIT          6
-  #define RTE_USB1_ULPI_D2_FUNC         1
-#else
-  #error "Invalid RTE_USB1_ULPI_D2 Pin Configuration!"
-#endif
-//       <o> USB1_ULPI_D3 <0=>PB_6 <1=>PC_5
-//       <i> USB1 ULPI link bidirectional data line 3.
-#define   RTE_USB1_ULPI_D3_ID           0
-#if      (RTE_USB1_ULPI_D3_ID == 0)
-  #define RTE_USB1_ULPI_D3_PORT         0xB
-  #define RTE_USB1_ULPI_D3_BIT          6
-  #define RTE_USB1_ULPI_D3_FUNC         1
-#elif    (RTE_USB1_ULPI_D3_ID == 1)
-  #define RTE_USB1_ULPI_D3_PORT         0xC
-  #define RTE_USB1_ULPI_D3_BIT          5
-  #define RTE_USB1_ULPI_D3_FUNC         1
-#else
-  #error "Invalid RTE_USB1_ULPI_D3 Pin Configuration!"
-#endif
-//       <o> USB1_ULPI_D4 <0=>PB_5 <1=>PC_4
-//       <i> USB1 ULPI link bidirectional data line 4.
-#define   RTE_USB1_ULPI_D4_ID           0
-#if      (RTE_USB1_ULPI_D4_ID == 0)
-  #define RTE_USB1_ULPI_D4_PORT         0xB
-  #define RTE_USB1_ULPI_D4_BIT          5
-  #define RTE_USB1_ULPI_D4_FUNC         1
-#elif    (RTE_USB1_ULPI_D4_ID == 1)
-  #define RTE_USB1_ULPI_D4_PORT         0xC
-  #define RTE_USB1_ULPI_D4_BIT          4
-  #define RTE_USB1_ULPI_D4_FUNC         1
-#else
-  #error "Invalid RTE_USB1_ULPI_D4 Pin Configuration!"
-#endif
-//       <o> USB1_ULPI_D5 <0=>PB_4 <1=>PC_3
-//       <i> USB1 ULPI link bidirectional data line 5.
-#define   RTE_USB1_ULPI_D5_ID           0
-#if      (RTE_USB1_ULPI_D5_ID == 0)
-  #define RTE_USB1_ULPI_D5_PORT         0xB
-  #define RTE_USB1_ULPI_D5_BIT          4
-  #define RTE_USB1_ULPI_D5_FUNC         1
-#elif    (RTE_USB1_ULPI_D5_ID == 1)
-  #define RTE_USB1_ULPI_D5_PORT         0xC
-  #define RTE_USB1_ULPI_D5_BIT          3
-  #define RTE_USB1_ULPI_D5_FUNC         0
-#else
-  #error "Invalid RTE_USB1_ULPI_D5 Pin Configuration!"
-#endif
-//       <o> USB1_ULPI_D6 <0=>PB_3 <1=>PC_2
-//       <i> USB1 ULPI link bidirectional data line 6.
-#define   RTE_USB1_ULPI_D6_ID           0
-#if      (RTE_USB1_ULPI_D6_ID == 0)
-  #define RTE_USB1_ULPI_D6_PORT         0xB
-  #define RTE_USB1_ULPI_D6_BIT          3
-  #define RTE_USB1_ULPI_D6_FUNC         1
-#elif    (RTE_USB1_ULPI_D6_ID == 1)
-  #define RTE_USB1_ULPI_D6_PORT         0xC
-  #define RTE_USB1_ULPI_D6_BIT          2
-  #define RTE_USB1_ULPI_D6_FUNC         0
-#else
-  #error "Invalid RTE_USB1_ULPI_D6 Pin Configuration!"
-#endif
-//       <o> USB1_ULPI_D7 <0=>PB_2 <1=>PC_1
-//       <i> USB1 ULPI link bidirectional data line 7.
-#define   RTE_USB1_ULPI_D7_ID           0
-#if      (RTE_USB1_ULPI_D7_ID == 0)
-  #define RTE_USB1_ULPI_D7_PORT         0xB
-  #define RTE_USB1_ULPI_D7_BIT          2
-  #define RTE_USB1_ULPI_D7_FUNC         1
-#elif    (RTE_USB1_ULPI_D7_ID == 1)
-  #define RTE_USB1_ULPI_D7_PORT         0xC
-  #define RTE_USB1_ULPI_D7_BIT          1
-  #define RTE_USB1_ULPI_D7_FUNC         0
-#else
-  #error "Invalid RTE_USB1_ULPI_D7 Pin Configuration!"
-#endif
-//     </e> External high-speed ULPI PHY (UTMI+ Low Pin Interface)
-//   </h> Pin Configuration
-// </e> USB1 Controller [Driver_USBD1 and Driver_USBH1]
-
-// <e> ENET (Ethernet Interface) [Driver_ETH_MAC0]
-// <i> Configuration settings for Driver_ETH_MAC0 in component ::Drivers:Ethernet MAC
-#define   RTE_ENET                      0
-
-//   <e> MII (Media Independent Interface)
-#define   RTE_ENET_MII                  0
-
-//     <o> ENET_TXD0 Pin <0=>P1_18
-#define   RTE_ENET_MII_TXD0_PORT_ID     0
-#if      (RTE_ENET_MII_TXD0_PORT_ID == 0)
-  #define RTE_ENET_MII_TXD0_PORT        1
-  #define RTE_ENET_MII_TXD0_PIN         18
-  #define RTE_ENET_MII_TXD0_FUNC        3
-#else
-  #error "Invalid ENET_TXD0 Pin Configuration!"
-#endif
-//     <o> ENET_TXD1 Pin <0=>P1_20
-#define   RTE_ENET_MII_TXD1_PORT_ID     0
-#if      (RTE_ENET_MII_TXD1_PORT_ID == 0)
-  #define RTE_ENET_MII_TXD1_PORT        1
-  #define RTE_ENET_MII_TXD1_PIN         20
-  #define RTE_ENET_MII_TXD1_FUNC        3
-#else
-  #error "Invalid ENET_TXD1 Pin Configuration!"
-#endif
-//     <o> ENET_TXD2 Pin <0=>P9_4 <1=>PC_2
-#define   RTE_ENET_MII_TXD2_PORT_ID     0
-#if      (RTE_ENET_MII_TXD2_PORT_ID == 0)
-  #define RTE_ENET_MII_TXD2_PORT        9
-  #define RTE_ENET_MII_TXD2_PIN         4
-  #define RTE_ENET_MII_TXD2_FUNC        5
-#elif    (RTE_ENET_MII_TXD2_PORT_ID == 1)
-  #define RTE_ENET_MII_TXD2_PORT        0xC
-  #define RTE_ENET_MII_TXD2_PIN         2
-  #define RTE_ENET_MII_TXD2_FUNC        3
-#else
-  #error "Invalid ENET_TXD2 Pin Configuration!"
-#endif
-//     <o> ENET_TXD3 Pin <0=>P9_5 <1=>PC_3
-#define   RTE_ENET_MII_TXD3_PORT_ID     0
-#if      (RTE_ENET_MII_TXD3_PORT_ID == 0)
-  #define RTE_ENET_MII_TXD3_PORT        9
-  #define RTE_ENET_MII_TXD3_PIN         5
-  #define RTE_ENET_MII_TXD3_FUNC        5
-#elif    (RTE_ENET_MII_TXD3_PORT_ID == 1)
-  #define RTE_ENET_MII_TXD3_PORT        0xC
-  #define RTE_ENET_MII_TXD3_PIN         3
-  #define RTE_ENET_MII_TXD3_FUNC        3
-#else
-  #error "Invalid ENET_TXD3 Pin Configuration!"
-#endif
-//     <o> ENET_TX_EN Pin <0=>P0_1 <1=>PC_4
-#define   RTE_ENET_MII_TX_EN_PORT_ID    0
-#if      (RTE_ENET_MII_TX_EN_PORT_ID == 0)
-  #define RTE_ENET_MII_TX_EN_PORT       0
-  #define RTE_ENET_MII_TX_EN_PIN        1
-  #define RTE_ENET_MII_TX_EN_FUNC       6
-#elif    (RTE_ENET_MII_TX_EN_PORT_ID == 1)
-  #define RTE_ENET_MII_TX_EN_PORT       0xC
-  #define RTE_ENET_MII_TX_EN_PIN        4
-  #define RTE_ENET_MII_TX_EN_FUNC       3
-#else
-  #error "Invalid ENET_TX_EN Pin Configuration!"
-#endif
-//     <o> ENET_TX_CLK Pin <0=>P1_19 <1=>CLK0
-#define   RTE_ENET_MII_TX_CLK_PORT_ID   0
-#if      (RTE_ENET_MII_TX_CLK_PORT_ID == 0)
-  #define RTE_ENET_MII_TX_CLK_PORT      1
-  #define RTE_ENET_MII_TX_CLK_PIN       19
-  #define RTE_ENET_MII_TX_CLK_FUNC      0
-#elif    (RTE_ENET_MII_TX_CLK_PORT_ID == 1)
-  #define RTE_ENET_MII_TX_CLK_PORT      0x10
-  #define RTE_ENET_MII_TX_CLK_PIN       0
-  #define RTE_ENET_MII_TX_CLK_FUNC      7
-#else
-  #error "Invalid ENET_TX_CLK Pin Configuration!"
-#endif
-//     <o> ENET_TX_ER Pin <0=>Not used <1=>PC_5 <2=>PC_14
-//     <i> Optional signal, rarely used
-#define   RTE_ENET_MII_TX_ER_PORT_ID    0
-#if      (RTE_ENET_MII_TX_ER_PORT_ID == 0)
-  #define RTE_ENET_MII_TX_ER_PIN_EN     0
-#elif    (RTE_ENET_MII_TX_ER_PORT_ID == 1)
-  #define RTE_ENET_MII_TX_ER_PORT       0xC
-  #define RTE_ENET_MII_TX_ER_PIN        5
-  #define RTE_ENET_MII_TX_ER_FUNC       3
-#elif    (RTE_ENET_MII_TX_ER_PORT_ID == 2)
-  #define RTE_ENET_MII_TX_ER_PORT       0xC
-  #define RTE_ENET_MII_TX_ER_PIN        14
-  #define RTE_ENET_MII_TX_ER_FUNC       6
-#else
-  #error "Invalid ENET_TX_ER Pin Configuration!"
-#endif
-#ifndef   RTE_ENET_MII_TX_ER_PIN_EN
-  #define RTE_ENET_MII_TX_ER_PIN_EN     1
-#endif
-//     <o> ENET_RXD0 Pin <0=>P1_15
-#define   RTE_ENET_MII_RXD0_PORT_ID     0
-#if      (RTE_ENET_MII_RXD0_PORT_ID == 0)
-  #define RTE_ENET_MII_RXD0_PORT        1
-  #define RTE_ENET_MII_RXD0_PIN         15
-  #define RTE_ENET_MII_RXD0_FUNC        3
-#else
-  #error "Invalid ENET_RXD0 Pin Configuration!"
-#endif
-//     <o> ENET_RXD1 Pin <0=>P0_0
-#define   RTE_ENET_MII_RXD1_PORT_ID     0
-#if      (RTE_ENET_MII_RXD1_PORT_ID == 0)
-  #define RTE_ENET_MII_RXD1_PORT        0
-  #define RTE_ENET_MII_RXD1_PIN         0
-  #define RTE_ENET_MII_RXD1_FUNC        2
-#else
-  #error "Invalid ENET_RXD1 Pin Configuration!"
-#endif
-//     <o> ENET_RXD2 Pin <0=>P9_3 <1=>PC_6
-#define   RTE_ENET_MII_RXD2_PORT_ID     0
-#if      (RTE_ENET_MII_RXD2_PORT_ID == 0)
-  #define RTE_ENET_MII_RXD2_PORT        9
-  #define RTE_ENET_MII_RXD2_PIN         3
-  #define RTE_ENET_MII_RXD2_FUNC        5
-#elif    (RTE_ENET_MII_RXD2_PORT_ID == 1)
-  #define RTE_ENET_MII_RXD2_PORT        0xC
-  #define RTE_ENET_MII_RXD2_PIN         6
-  #define RTE_ENET_MII_RXD2_FUNC        3
-#else
-  #error "Invalid ENET_RXD2 Pin Configuration!"
-#endif
-//     <o> ENET_RXD3 Pin <0=>P9_2 <1=>PC_7
-#define   RTE_ENET_MII_RXD3_PORT_ID     0
-#if      (RTE_ENET_MII_RXD3_PORT_ID == 0)
-  #define RTE_ENET_MII_RXD3_PORT        9
-  #define RTE_ENET_MII_RXD3_PIN         2
-  #define RTE_ENET_MII_RXD3_FUNC        5
-#elif    (RTE_ENET_MII_RXD3_PORT_ID == 1)
-  #define RTE_ENET_MII_RXD3_PORT        0xC
-  #define RTE_ENET_MII_RXD3_PIN         7
-  #define RTE_ENET_MII_RXD3_FUNC        3
-#else
-  #error "Invalid ENET_RXD3 Pin Configuration!"
-#endif
-//     <o> ENET_RX_DV Pin <0=>P1_16 <1=>PC_8
-#define   RTE_ENET_MII_RX_DV_PORT_ID    0
-#if      (RTE_ENET_MII_RX_DV_PORT_ID == 0)
-  #define RTE_ENET_MII_RX_DV_PORT       1
-  #define RTE_ENET_MII_RX_DV_PIN        16
-  #define RTE_ENET_MII_RX_DV_FUNC       7
-#elif    (RTE_ENET_MII_RX_DV_PORT_ID == 1)
-  #define RTE_ENET_MII_RX_DV_PORT       0xC
-  #define RTE_ENET_MII_RX_DV_PIN        8
-  #define RTE_ENET_MII_RX_DV_FUNC       3
-#else
-  #error "Invalid ENET_RX_DV Pin Configuration!"
-#endif
-//     <o> ENET_RX_CLK Pin <0=>PC_0
-#define   RTE_ENET_MII_RX_CLK_PORT_ID   0
-#if      (RTE_ENET_MII_RX_CLK_PORT_ID == 0)
-  #define RTE_ENET_MII_RX_CLK_PORT      0xC
-  #define RTE_ENET_MII_RX_CLK_PIN       0
-  #define RTE_ENET_MII_RX_CLK_FUNC      3
-#else
-  #error "Invalid ENET_RX_CLK Pin Configuration!"
-#endif
-//     <o> ENET_RX_ER Pin <0=>P9_1 <1=>PC_9
-#define   RTE_ENET_MII_RX_ER_PORT_ID    0
-#if      (RTE_ENET_MII_RX_ER_PORT_ID == 0)
-  #define RTE_ENET_MII_RX_ER_PORT       9
-  #define RTE_ENET_MII_RX_ER_PIN        1
-  #define RTE_ENET_MII_RX_ER_FUNC       5
-#elif    (RTE_ENET_MII_RX_ER_PORT_ID == 1)
-  #define RTE_ENET_MII_RX_ER_PORT       0xC
-  #define RTE_ENET_MII_RX_ER_PIN        9
-  #define RTE_ENET_MII_RX_ER_FUNC       3
-#else
-  #error "Invalid ENET_RX_ER Pin Configuration!"
-#endif
-//     <o> ENET_COL Pin <0=>P0_1 <1=>P4_1 <2=>P9_6
-#define   RTE_ENET_MII_COL_PORT_ID      0
-#if      (RTE_ENET_MII_COL_PORT_ID == 0)
-  #define RTE_ENET_MII_COL_PORT         0
-  #define RTE_ENET_MII_COL_PIN          1
-  #define RTE_ENET_MII_COL_FUNC         2
-#elif    (RTE_ENET_MII_COL_PORT_ID == 1)
-  #define RTE_ENET_MII_COL_PORT         4
-  #define RTE_ENET_MII_COL_PIN          1
-  #define RTE_ENET_MII_COL_FUNC         7
-#elif    (RTE_ENET_MII_COL_PORT_ID == 2)
-  #define RTE_ENET_MII_COL_PORT         9
-  #define RTE_ENET_MII_COL_PIN          6
-  #define RTE_ENET_MII_COL_FUNC         5
-#else
-  #error "Invalid ENET_COL Pin Configuration!"
-#endif
-//     <o> ENET_CRS Pin <0=>P1_16 <1=>P9_0
-#define   RTE_ENET_MII_CRS_PORT_ID      0
-#if      (RTE_ENET_MII_CRS_PORT_ID == 0)
-  #define RTE_ENET_MII_CRS_PORT         1
-  #define RTE_ENET_MII_CRS_PIN          16
-  #define RTE_ENET_MII_CRS_FUNC         3
-#elif    (RTE_ENET_MII_CRS_PORT_ID == 1)
-  #define RTE_ENET_MII_CRS_PORT         9
-  #define RTE_ENET_MII_CRS_PIN          0
-  #define RTE_ENET_MII_CRS_FUNC         5
-#else
-  #error "Invalid ENET_CRS Pin Configuration!"
-#endif
-//   </e> MII (Media Independent Interface)
-
-//   <e> RMII (Reduced Media Independent Interface)
-#define   RTE_ENET_RMII                 0
-
-//     <o> ENET_TXD0 Pin <0=>P1_18
-#define   RTE_ENET_RMII_TXD0_PORT_ID    0
-#if      (RTE_ENET_RMII_TXD0_PORT_ID == 0)
-  #define RTE_ENET_RMII_TXD0_PORT       1
-  #define RTE_ENET_RMII_TXD0_PIN        18
-  #define RTE_ENET_RMII_TXD0_FUNC       3
-#else
-  #error "Invalid ENET_TXD0 Pin Configuration!"
-#endif
-//     <o> ENET_TXD1 Pin <0=>P1_20
-#define   RTE_ENET_RMII_TXD1_PORT_ID    0
-#if      (RTE_ENET_RMII_TXD1_PORT_ID == 0)
-  #define RTE_ENET_RMII_TXD1_PORT       1
-  #define RTE_ENET_RMII_TXD1_PIN        20
-  #define RTE_ENET_RMII_TXD1_FUNC       3
-#else
-  #error "Invalid ENET_TXD1 Pin Configuration!"
-#endif
-//     <o> ENET_TX_EN Pin <0=>P0_1 <1=>PC_4
-#define   RTE_ENET_RMII_TX_EN_PORT_ID   0
-#if      (RTE_ENET_RMII_TX_EN_PORT_ID == 0)
-  #define RTE_ENET_RMII_TX_EN_PORT      0
-  #define RTE_ENET_RMII_TX_EN_PIN       1
-  #define RTE_ENET_RMII_TX_EN_FUNC      6
-#elif    (RTE_ENET_RMII_TX_EN_PORT_ID == 1)
-  #define RTE_ENET_RMII_TX_EN_PORT      0xC
-  #define RTE_ENET_RMII_TX_EN_PIN       4
-  #define RTE_ENET_RMII_TX_EN_FUNC      3
-#else
-  #error "Invalid ENET_TX_EN Pin Configuration!"
-#endif
-//     <o> ENET_REF_CLK Pin <0=>P1_19 <1=>CLK0
-#define   RTE_ENET_RMII_REF_CLK_PORT_ID 0
-#if      (RTE_ENET_RMII_REF_CLK_PORT_ID == 0)
-  #define RTE_ENET_RMII_REF_CLK_PORT    1
-  #define RTE_ENET_RMII_REF_CLK_PIN     19
-  #define RTE_ENET_RMII_REF_CLK_FUNC    0
-#elif    (RTE_ENET_RMII_REF_CLK_PORT_ID == 1)
-  #define RTE_ENET_RMII_REF_CLK_PORT    0x10
-  #define RTE_ENET_RMII_REF_CLK_PIN     0
-  #define RTE_ENET_RMII_REF_CLK_FUNC    7
-#else
-  #error "Invalid ENET_REF_CLK Pin Configuration!"
-#endif
-//     <o> ENET_RXD0 Pin <0=>P1_15
-#define   RTE_ENET_RMII_RXD0_PORT_ID    0
-#if      (RTE_ENET_RMII_RXD0_PORT_ID == 0)
-  #define RTE_ENET_RMII_RXD0_PORT       1
-  #define RTE_ENET_RMII_RXD0_PIN        15
-  #define RTE_ENET_RMII_RXD0_FUNC       3
-#else
-  #error "Invalid ENET_RXD0 Pin Configuration!"
-#endif
-//     <o> ENET_RXD1 Pin <0=>P0_0
-#define   RTE_ENET_RMII_RXD1_PORT_ID    0
-#if      (RTE_ENET_RMII_RXD1_PORT_ID == 0)
-  #define RTE_ENET_RMII_RXD1_PORT       0
-  #define RTE_ENET_RMII_RXD1_PIN        0
-  #define RTE_ENET_RMII_RXD1_FUNC       2
-#else
-  #error "Invalid ENET_RXD1 Pin Configuration!"
-#endif
-//     <o> ENET_RX_DV Pin <0=>P1_16 <1=>PC_8
-#define   RTE_ENET_RMII_RX_DV_PORT_ID   0
-#if      (RTE_ENET_RMII_RX_DV_PORT_ID == 0)
-  #define RTE_ENET_RMII_RX_DV_PORT      1
-  #define RTE_ENET_RMII_RX_DV_PIN       16
-  #define RTE_ENET_RMII_RX_DV_FUNC      7
-#elif    (RTE_ENET_RMII_RX_DV_PORT_ID == 1)
-  #define RTE_ENET_RMII_RX_DV_PORT      0xC
-  #define RTE_ENET_RMII_RX_DV_PIN       8
-  #define RTE_ENET_RMII_RX_DV_FUNC      3
-#else
-  #error "Invalid ENET_RX_DV Pin Configuration!"
-#endif
-//   </e> RMII (Reduced Media Independent Interface)
-
-//   <h> MIIM (Management Data Interface)
-//     <o> ENET_MDIO Pin <0=>P1_17
-#define   RTE_ENET_MDI_MDIO_PORT_ID     0
-#if      (RTE_ENET_MDI_MDIO_PORT_ID == 0)
-  #define RTE_ENET_MDI_MDIO_PORT        1
-  #define RTE_ENET_MDI_MDIO_PIN         17
-  #define RTE_ENET_MDI_MDIO_FUNC        3
-#else
-  #error "Invalid ENET_MDIO Pin Configuration!"
-#endif
-//     <o> ENET_MDC Pin <0=>P2_0 <1=>P7_7 <2=>PC_1
-#define   RTE_ENET_MDI_MDC_PORT_ID      2
-#if      (RTE_ENET_MDI_MDC_PORT_ID == 0)
-  #define RTE_ENET_MDI_MDC_PORT         2
-  #define RTE_ENET_MDI_MDC_PIN          0
-  #define RTE_ENET_MDI_MDC_FUNC         7
-#elif    (RTE_ENET_MDI_MDC_PORT_ID == 1)
-  #define RTE_ENET_MDI_MDC_PORT         7
-  #define RTE_ENET_MDI_MDC_PIN          7
-  #define RTE_ENET_MDI_MDC_FUNC         6
-#elif    (RTE_ENET_MDI_MDC_PORT_ID == 2)
-  #define RTE_ENET_MDI_MDC_PORT         0xC
-  #define RTE_ENET_MDI_MDC_PIN          1
-  #define RTE_ENET_MDI_MDC_FUNC         3
-#else
-  #error "Invalid ENET_MDC Pin Configuration!"
-#endif
-//   </h> MIIM (Management Data Interface)
-// </e> ENET (Ethernet Interface) [Driver_ETH_MAC0]
-
-// <e> SD/MMC Interface [Driver_MCI0]
-// <i> Configuration settings for Driver_MCI0 in component ::Drivers:MCI
-#define RTE_SDMMC                       0
-
-//   <h> SD/MMC Peripheral Bus
-//     <o> SD_CLK Pin <0=>PC_0 <1=>CLK0 <2=>CLK2
-#define   RTE_SD_CLK_PORT_ID            0
-#if      (RTE_SD_CLK_PORT_ID == 0)
-  #define RTE_SD_CLK_PORT               0xC
-  #define RTE_SD_CLK_PIN                0
-  #define RTE_SD_CLK_FUNC               7
-#elif    (RTE_SD_CLK_PORT_ID == 1)
-  #define RTE_SD_CLK_PORT               0x10
-  #define RTE_SD_CLK_PIN                0
-  #define RTE_SD_CLK_FUNC               4
-#elif    (RTE_SD_CLK_PORT_ID == 2)
-  #define RTE_SD_CLK_PORT               0x10
-  #define RTE_SD_CLK_PIN                2
-  #define RTE_SD_CLK_FUNC               4
-#else
-  #error "Invalid SD_CLK Pin Configuration!"
-#endif
-//     <o> SD_CMD Pin <0=>P1_6 <1=>PC_10
-#define   RTE_SD_CMD_PORT_ID            0
-#if      (RTE_SD_CMD_PORT_ID == 0)
-  #define RTE_SD_CMD_PORT               1
-  #define RTE_SD_CMD_PIN                6
-  #define RTE_SD_CMD_FUNC               7
-#elif    (RTE_SD_CMD_PORT_ID == 1)
-  #define RTE_SD_CMD_PORT               0xC
-  #define RTE_SD_CMD_PIN                10
-  #define RTE_SD_CMD_FUNC               7
-#else
-  #error "Invalid SD_CMD Pin Configuration!"
-#endif
-//     <o> SD_DAT0 Pin <0=>P1_9 <1=>PC_4
-#define   RTE_SD_DAT0_PORT_ID           0
-#if      (RTE_SD_DAT0_PORT_ID == 0)
-  #define RTE_SD_DAT0_PORT              1
-  #define RTE_SD_DAT0_PIN               9
-  #define RTE_SD_DAT0_FUNC              7
-#elif    (RTE_SD_DAT0_PORT_ID == 1)
-  #define RTE_SD_DAT0_PORT              0xC
-  #define RTE_SD_DAT0_PIN               4
-  #define RTE_SD_DAT0_FUNC              7
-#else
-  #error "Invalid SD_DAT0 Pin Configuration!"
-#endif
-//     <e> SD_DAT[1 .. 3]
-#define   RTE_SDMMC_BUS_WIDTH_4         0
-//       <o> SD_DAT1 Pin <0=>P1_10 <1=>PC_5
-#define   RTE_SD_DAT1_PORT_ID           0
-#if      (RTE_SD_DAT1_PORT_ID == 0)
-  #define RTE_SD_DAT1_PORT              1
-  #define RTE_SD_DAT1_PIN               10
-  #define RTE_SD_DAT1_FUNC              7
-#elif    (RTE_SD_DAT1_PORT_ID == 1)
-  #define RTE_SD_DAT1_PORT              0xC
-  #define RTE_SD_DAT1_PIN               5
-  #define RTE_SD_DAT1_FUNC              7
-#else
-  #error "Invalid SD_DAT1 Pin Configuration!"
-#endif
-//       <o> SD_DAT2 Pin <0=>P1_11 <1=>PC_6
-#define   RTE_SD_DAT2_PORT_ID           0
-#if      (RTE_SD_DAT2_PORT_ID == 0)
-  #define RTE_SD_DAT2_PORT              1
-  #define RTE_SD_DAT2_PIN               11
-  #define RTE_SD_DAT2_FUNC              7
-#elif    (RTE_SD_DAT2_PORT_ID == 1)
-  #define RTE_SD_DAT2_PORT              0xC
-  #define RTE_SD_DAT2_PIN               6
-  #define RTE_SD_DAT2_FUNC              7
-#else
-  #error "Invalid SD_DAT2 Pin Configuration!"
-#endif
-//       <o> SD_DAT3 Pin <0=>P1_12 <1=>PC_7
-#define   RTE_SD_DAT3_PORT_ID           0
-#if      (RTE_SD_DAT3_PORT_ID == 0)
-  #define RTE_SD_DAT3_PORT              1
-  #define RTE_SD_DAT3_PIN               12
-  #define RTE_SD_DAT3_FUNC              7
-#elif    (RTE_SD_DAT3_PORT_ID == 1)
-  #define RTE_SD_DAT3_PORT              0xC
-  #define RTE_SD_DAT3_PIN               7
-  #define RTE_SD_DAT3_FUNC              7
-#else
-  #error "Invalid SD_DAT3 Pin Configuration!"
-#endif
-//     </e> SD_DAT[1 .. 3]
-//     <e> SD_DAT[4 .. 7]
-#define   RTE_SDMMC_BUS_WIDTH_8         0
-//       <o> SD_DAT4 Pin <0=>PC_11
-#define   RTE_SD_DAT4_PORT_ID           0
-#if      (RTE_SD_DAT4_PORT_ID == 0)
-  #define RTE_SD_DAT4_PORT              0xC
-  #define RTE_SD_DAT4_PIN               11
-  #define RTE_SD_DAT4_FUNC              7
-#else
-  #error "Invalid SD_DAT4 Pin Configuration!"
-#endif
-//       <o> SD_DAT5 Pin <0=>PC_12
-#define   RTE_SD_DAT5_PORT_ID           0
-#if      (RTE_SD_DAT5_PORT_ID == 0)
-  #define RTE_SD_DAT5_PORT              0xC
-  #define RTE_SD_DAT5_PIN               12
-  #define RTE_SD_DAT5_FUNC              7
-#else
-  #error "Invalid SD_DAT5 Pin Configuration!"
-#endif
-//       <o> SD_DAT6 Pin <0=>PC_13
-#define   RTE_SD_DAT6_PORT_ID           0
-#if      (RTE_SD_DAT6_PORT_ID == 0)
-  #define RTE_SD_DAT6_PORT              0xC
-  #define RTE_SD_DAT6_PIN               13
-  #define RTE_SD_DAT6_FUNC              7
-#else
-  #error "Invalid SD_DAT6 Pin Configuration!"
-#endif
-//       <o> SD_DAT7 Pin <0=>PC_14
-#define   RTE_SD_DAT7_PORT_ID           0
-#if      (RTE_SD_DAT7_PORT_ID == 0)
-  #define RTE_SD_DAT7_PORT              0xC
-  #define RTE_SD_DAT7_PIN               14
-  #define RTE_SD_DAT7_FUNC              7
-#else
-  #error "Invalid SD_DAT7 Pin Configuration!"
-#endif
-//     </e> SD_DAT[4 .. 7]
-//   </h> SD/MMC Peripheral Bus
-
-//   <o> SD_CD (Card Detect) Pin <0=>Not used <1=>P1_13 <2=>PC_8
-//   <i> Configure Pin if exists
-#define   RTE_SD_CD_PORT_ID             0
-#if      (RTE_SD_CD_PORT_ID == 0)
-  #define RTE_SD_CD_PIN_EN              0
-#elif    (RTE_SD_CD_PORT_ID == 1)
-  #define RTE_SD_CD_PORT                1
-  #define RTE_SD_CD_PIN                 13
-  #define RTE_SD_CD_FUNC                7
-#elif    (RTE_SD_CD_PORT_ID == 2)
-  #define RTE_SD_CD_PORT                0xC
-  #define RTE_SD_CD_PIN                 8
-  #define RTE_SD_CD_FUNC                7
-#else
-  #error "Invalid SD_CD Pin Configuration!"
-#endif
-#ifndef   RTE_SD_CD_PIN_EN
-  #define RTE_SD_CD_PIN_EN              1
-#endif
-//   <o> SD_WP (Write Protect) Pin <0=>Not used <1=>PD_15 <2=>PF_10
-//   <i> Configure Pin if exists
-#define   RTE_SD_WP_PORT_ID             0
-#if      (RTE_SD_WP_PORT_ID == 0)
-  #define RTE_SD_WP_PIN_EN              0
-#elif    (RTE_SD_WP_PORT_ID == 1)
-  #define RTE_SD_WP_PORT                0xD
-  #define RTE_SD_WP_PIN                 15
-  #define RTE_SD_WP_FUNC                5
-#elif    (RTE_SD_WP_PORT_ID == 2)
-  #define RTE_SD_WP_PORT                0xF
-  #define RTE_SD_WP_PIN                 10
-  #define RTE_SD_WP_FUNC                6
-#else
-  #error "Invalid SD_WP Pin Configuration!"
-#endif
-#ifndef   RTE_SD_WP_PIN_EN
-  #define RTE_SD_WP_PIN_EN              1
-#endif
-//   <o> SD_POW (Power) Pin <0=>Not used <1=>P1_5 <2=>PC_9 <3=>PD_1
-//   <i> Configure Pin if exists
-#define   RTE_SD_POW_PORT_ID            0
-#if      (RTE_SD_POW_PORT_ID == 0)
-  #define RTE_SD_POW_PIN_EN             0
-#elif    (RTE_SD_POW_PORT_ID == 1)
-  #define RTE_SD_POW_PORT               1
-  #define RTE_SD_POW_PIN                5
-  #define RTE_SD_POW_FUNC               7
-#elif    (RTE_SD_POW_PORT_ID == 2)
-  #define RTE_SD_POW_PORT               0xC
-  #define RTE_SD_POW_PIN                9
-  #define RTE_SD_POW_FUNC               7
-#elif    (RTE_SD_POW_PORT_ID == 3)
-  #define RTE_SD_POW_PORT               0xD
-  #define RTE_SD_POW_PIN                1
-  #define RTE_SD_POW_FUNC               5
-#else
-  #error "Invalid SD_POW Pin Configuration!"
-#endif
-#ifndef   RTE_SD_POW_PIN_EN
-  #define RTE_SD_POW_PIN_EN             1
-#endif
-//   <o> SD_RST (Card Reset for MMC4.4) Pin <0=>Not used <1=>P1_3 <2=>PC_2
-//   <i> Configure Pin if exists
-#define   RTE_SD_RST_PORT_ID            0
-#if      (RTE_SD_RST_PORT_ID == 0)
-  #define RTE_SD_RST_PIN_EN             0
-#elif    (RTE_SD_RST_PORT_ID == 1)
-  #define RTE_SD_RST_PORT               1
-  #define RTE_SD_RST_PIN                3
-  #define RTE_SD_RST_FUNC               7
-#elif    (RTE_SD_RST_PORT_ID == 2)
-  #define RTE_SD_RST_PORT               0xC
-  #define RTE_SD_RST_PIN                2
-  #define RTE_SD_RST_FUNC               7
-#else
-  #error "Invalid SD_RST Pin Configuration!"
-#endif
-#ifndef   RTE_SD_RST_PIN_EN
-  #define RTE_SD_RST_PIN_EN             1
-#endif
-// </e> SD/MMC Interface [Driver_MCI0]
-
-// <e> I2C0 (Inter-integrated Circuit Interface 0) [Driver_I2C0]
-// <i> Configuration settings for Driver_I2C0 in component ::Drivers:I2C
-// </e> I2C0 (Inter-integrated Circuit Interface 0) [Driver_I2C0]
-#define   RTE_I2C0                      0
-
-// <e> I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1]
-// <i> Configuration settings for Driver_I2C1 in component ::Drivers:I2C
-#define   RTE_I2C1                      0
-
-//   <o> I2C1_SCL Pin <0=>P2_4 <1=>PE_15
-#define   RTE_I2C1_SCL_PORT_ID          0
-#if      (RTE_I2C1_SCL_PORT_ID == 0)
-  #define RTE_I2C1_SCL_PORT             2
-  #define RTE_I2C1_SCL_PIN              4
-  #define RTE_I2C1_SCL_FUNC             1
-#elif    (RTE_I2C1_SCL_PORT_ID == 1)
-  #define RTE_I2C1_SCL_PORT             0xE
-  #define RTE_I2C1_SCL_PIN              15
-  #define RTE_I2C1_SCL_FUNC             2
-#else
-  #error "Invalid I2C1_SCL Pin Configuration!"
-#endif
-//   <o> I2C1_SDA Pin <0=>P2_3 <1=>PE_13
-#define   RTE_I2C1_SDA_PORT_ID          0
-#if      (RTE_I2C1_SDA_PORT_ID == 0)
-  #define RTE_I2C1_SDA_PORT             2
-  #define RTE_I2C1_SDA_PIN              3
-  #define RTE_I2C1_SDA_FUNC             1
-#elif    (RTE_I2C1_SDA_PORT_ID == 1)
-  #define RTE_I2C1_SDA_PORT             0xE
-  #define RTE_I2C1_SDA_PIN              13
-  #define RTE_I2C1_SDA_FUNC             2
-#else
-  #error "Invalid I2C1_SDA Pin Configuration!"
-#endif
-// </e> I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1]
-
-// <e> USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0]
-#define   RTE_USART0                    0
-
-//   <h> Pin Configuration
-//     <o> TX <0=>Not used <1=>P2_0 <2=>P6_4 <3=>P9_5 <4=>PF_10
-//     <i> USART0 Serial Output pin
-#define   RTE_USART0_TX_ID              0
-#if      (RTE_USART0_TX_ID == 0)
-  #define RTE_USART0_TX_PIN_EN          0
-#elif    (RTE_USART0_TX_ID == 1)
-  #define RTE_USART0_TX_PORT            2
-  #define RTE_USART0_TX_BIT             0
-  #define RTE_USART0_TX_FUNC            1
-#elif    (RTE_USART0_TX_ID == 2)
-  #define RTE_USART0_TX_PORT            6
-  #define RTE_USART0_TX_BIT             4
-  #define RTE_USART0_TX_FUNC            2
-#elif    (RTE_USART0_TX_ID == 3)
-  #define RTE_USART0_TX_PORT            9
-  #define RTE_USART0_TX_BIT             5
-  #define RTE_USART0_TX_FUNC            7
-#elif    (RTE_USART0_TX_ID == 4)
-  #define RTE_USART0_TX_PORT            0xF
-  #define RTE_USART0_TX_BIT             10
-  #define RTE_USART0_TX_FUNC            1
-#else
-  #error "Invalid USART0_TX Pin Configuration!"
-#endif
-#ifndef   RTE_USART0_TX_PIN_EN
-  #define RTE_USART0_TX_PIN_EN          1
-#endif
-//     <o> RX <0=>Not used <1=>P2_1 <2=>P6_5 <3=>P9_6 <4=>PF_11
-//     <i> USART0 Serial Input pin
-#define   RTE_USART0_RX_ID              0
-#if      (RTE_USART0_RX_ID == 0)
-  #define RTE_USART0_RX_PIN_EN          0
-#elif    (RTE_USART0_RX_ID == 1)
-  #define RTE_USART0_RX_PORT            2
-  #define RTE_USART0_RX_BIT             1
-  #define RTE_USART0_RX_FUNC            1
-#elif    (RTE_USART0_RX_ID == 2)
-  #define RTE_USART0_RX_PORT            6
-  #define RTE_USART0_RX_BIT             5
-  #define RTE_USART0_RX_FUNC            2
-#elif    (RTE_USART0_RX_ID == 3)
-  #define RTE_USART0_RX_PORT            9
-  #define RTE_USART0_RX_BIT             6
-  #define RTE_USART0_RX_FUNC            7
-#elif    (RTE_USART0_RX_ID == 4)
-  #define RTE_USART0_RX_PORT            0xF
-  #define RTE_USART0_RX_BIT             11
-  #define RTE_USART0_RX_FUNC            1
-#else
-  #error "Invalid USART0_RX Pin Configuration!"
-#endif
-#ifndef   RTE_USART0_RX_PIN_EN
-  #define RTE_USART0_RX_PIN_EN          1
-#endif
-//     <o> UCLK (Synchronous and SmartCard mode) <0=>Not used <1=>P2_2 <2=>P6_1 <3=>PF_8
-//     <i> USART0 Serial Clock input/output synchronous mode
-#define   RTE_USART0_UCLK_ID            0
-#if      (RTE_USART0_UCLK_ID == 0)
-  #define RTE_USART0_UCLK_PIN_EN        0
-#elif    (RTE_USART0_UCLK_ID == 1)
-  #define RTE_USART0_UCLK_PORT          2
-  #define RTE_USART0_UCLK_BIT           2
-  #define RTE_USART0_UCLK_FUNC          1
-#elif    (RTE_USART0_UCLK_ID == 2)
-  #define RTE_USART0_UCLK_PORT          6
-  #define RTE_USART0_UCLK_BIT           1
-  #define RTE_USART0_UCLK_FUNC          2
-#elif    (RTE_USART0_UCLK_ID == 3)
-  #define RTE_USART0_UCLK_PORT          0xF
-  #define RTE_USART0_UCLK_BIT           8
-  #define RTE_USART0_UCLK_FUNC          1
-#else
-  #error "Invalid USART0_UCLK Pin Configuration!"
-#endif
-#ifndef   RTE_USART0_UCLK_PIN_EN
-  #define RTE_USART0_UCLK_PIN_EN        1
-#endif
-//   </h> Pin Configuration
-
-//   <h> DMA
-//     <e> Tx
-//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
-//       <o2> Peripheral  <0=>1 (DMAMUXPER1)  <1=>11 (DMAMUXPER11)
-//     </e>
-#define   RTE_USART0_DMA_TX_EN          0
-#define   RTE_USART0_DMA_TX_CH          0
-#define   RTE_USART0_DMA_TX_PERI_ID     0
-#if      (RTE_USART0_DMA_TX_PERI_ID == 0)
-  #define RTE_USART0_DMA_TX_PERI        1
-  #define RTE_USART0_DMA_TX_PERI_SEL    1
-#elif    (RTE_USART0_DMA_TX_PERI_ID == 1)
-  #define RTE_USART0_DMA_TX_PERI        11
-  #define RTE_USART0_DMA_TX_PERI_SEL    2
-#endif
-//     <e> Rx
-//       <o1> Channel    <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
-//       <o2> Peripheral <0=>2 (DMAMUXPER2)  <1=>12 (DMAMUXPER12)
-//     </e>
-#define   RTE_USART0_DMA_RX_EN          0
-#define   RTE_USART0_DMA_RX_CH          1
-#define   RTE_USART0_DMA_RX_PERI_ID     0
-#if      (RTE_USART0_DMA_RX_PERI_ID == 0)
-  #define RTE_USART0_DMA_RX_PERI        2
-  #define RTE_USART0_DMA_RX_PERI_SEL    1
-#elif    (RTE_USART0_DMA_RX_PERI_ID == 1)
-  #define RTE_USART0_DMA_RX_PERI        12
-  #define RTE_USART0_DMA_RX_PERI_SEL    2
-#endif
-//   </h> DMA
-// </e> USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0]
-
-// <e> UART1 (Universal asynchronous receiver transmitter) [Driver_USART1]
-#define   RTE_UART1                     1
-
-//   <h> Pin Configuration
-//     <o> TX <0=>Not used <1=>P1_13 <2=>P3_4 <3=>P5_6 <4=>PC_13 <5=>PE_11
-//     <i> UART0 Serial Output pin
-#define   RTE_UART1_TX_ID               0
-#if      (RTE_UART1_TX_ID == 0)
-  #define RTE_UART1_TX_PIN_EN           0
-#elif    (RTE_UART1_TX_ID == 1)
-  #define RTE_UART1_TX_PORT             1
-  #define RTE_UART1_TX_BIT              13
-  #define RTE_UART1_TX_FUNC             1
-#elif    (RTE_UART1_TX_ID == 2)
-  #define RTE_UART1_TX_PORT             3
-  #define RTE_UART1_TX_BIT              4
-  #define RTE_UART1_TX_FUNC             4
-#elif    (RTE_UART1_TX_ID == 3)
-  #define RTE_UART1_TX_PORT             5
-  #define RTE_UART1_TX_BIT              6
-  #define RTE_UART1_TX_FUNC             4
-#elif    (RTE_UART1_TX_ID == 4)
-  #define RTE_UART1_TX_PORT             0xC
-  #define RTE_UART1_TX_BIT              13
-  #define RTE_UART1_TX_FUNC             2
-#elif    (RTE_UART1_TX_ID == 5)
-  #define RTE_UART1_TX_PORT             0xE
-  #define RTE_UART1_TX_BIT              11
-  #define RTE_UART1_TX_FUNC             2
-#else
-  #error "Invalid UART1_TX Pin Configuration!"
-#endif
-#ifndef   RTE_UART1_TX_PIN_EN
-  #define RTE_UART1_TX_PIN_EN           1
-#endif
-//   <o> RX <0=>Not used <1=>P1_14 <2=>P3_5 <3=>P5_7 <4=>PC_14 <5=>PE_12
-//   <i> UART1 Serial Input pin
-#define   RTE_UART1_RX_ID               1
-#if      (RTE_UART1_RX_ID == 0)
-  #define RTE_UART1_RX_PIN_EN           0
-#elif    (RTE_UART1_RX_ID == 1)
-  #define RTE_UART1_RX_PORT             1
-  #define RTE_UART1_RX_BIT              14
-  #define RTE_UART1_RX_FUNC             1
-#elif    (RTE_UART1_RX_ID == 2)
-  #define RTE_UART1_RX_PORT             3
-  #define RTE_UART1_RX_BIT              5
-  #define RTE_UART1_RX_FUNC             4
-#elif    (RTE_UART1_RX_ID == 3)
-  #define RTE_UART1_RX_PORT             5
-  #define RTE_UART1_RX_BIT              7
-  #define RTE_UART1_RX_FUNC             4
-#elif    (RTE_UART1_RX_ID == 4)
-  #define RTE_UART1_RX_PORT             0xC
-  #define RTE_UART1_RX_BIT              14
-  #define RTE_UART1_RX_FUNC             2
-#elif    (RTE_UART1_RX_ID == 5)
-  #define RTE_UART1_RX_PORT             0xE
-  #define RTE_UART1_RX_BIT              12
-  #define RTE_UART1_RX_FUNC             2
-#else
-  #error "Invalid UART1_RX Pin Configuration!"
-#endif
-#ifndef   RTE_UART1_RX_PIN_EN
-  #define RTE_UART1_RX_PIN_EN           1
-#endif
-
-//     <h> Modem Lines
-//       <o> CTS <0=>Not used <1=>P1_11 <2=>P5_4 <3=>PC_2 <4=>PE_7
-#define   RTE_UART1_CTS_ID              0
-#if      (RTE_UART1_CTS_ID == 0)
-  #define RTE_UART1_CTS_PIN_EN          0
-#elif    (RTE_UART1_CTS_ID == 1)
-  #define RTE_UART1_CTS_PORT            1
-  #define RTE_UART1_CTS_BIT             11
-  #define RTE_UART1_CTS_FUNC            1
-#elif    (RTE_UART1_CTS_ID == 2)
-  #define RTE_UART1_CTS_PORT            5
-  #define RTE_UART1_CTS_BIT             4
-  #define RTE_UART1_CTS_FUNC            4
-#elif    (RTE_UART1_CTS_ID == 3)
-  #define RTE_UART1_CTS_PORT            0xC
-  #define RTE_UART1_CTS_BIT             2
-  #define RTE_UART1_CTS_FUNC            2
-#elif    (RTE_UART1_CTS_ID == 4)
-  #define RTE_UART1_CTS_PORT            0xE
-  #define RTE_UART1_CTS_BIT             7
-  #define RTE_UART1_CTS_FUNC            2
-#else
-  #error "Invalid UART1_CTS Pin Configuration!"
-#endif
-#ifndef   RTE_UART1_CTS_PIN_EN
-  #define RTE_UART1_CTS_PIN_EN          1
-#endif
-//       <o> RTS <0=>Not used <1=>P1_9  <2=>P5_2 <3=>PC_3 <4=>PE_5
-#define   RTE_UART1_RTS_ID              0
-#if      (RTE_UART1_RTS_ID == 0)
-  #define RTE_UART1_RTS_PIN_EN          0
-#elif    (RTE_UART1_RTS_ID == 1)
-  #define RTE_UART1_RTS_PORT            1
-  #define RTE_UART1_RTS_BIT             9
-  #define RTE_UART1_RTS_FUNC            1
-#elif    (RTE_UART1_RTS_ID == 2)
-  #define RTE_UART1_RTS_PORT            5
-  #define RTE_UART1_RTS_BIT             2
-  #define RTE_UART1_RTS_FUNC            4
-#elif    (RTE_UART1_RTS_ID == 3)
-  #define RTE_UART1_RTS_PORT            0xC
-  #define RTE_UART1_RTS_BIT             3
-  #define RTE_UART1_RTS_FUNC            2
-#elif    (RTE_UART1_RTS_ID == 4)
-  #define RTE_UART1_RTS_PORT            0xE
-  #define RTE_UART1_RTS_BIT             5
-  #define RTE_UART1_RTS_FUNC            2
-#else
-  #error "Invalid UART1_RTS Pin Configuration!"
-#endif
-#ifndef   RTE_UART1_RTS_PIN_EN
-  #define RTE_UART1_RTS_PIN_EN          1
-#endif
-//       <o> DCD <0=>Not used <1=>P1_12 <2=>P5_5 <3=>PC_11 <4=>PE_9
-#define   RTE_UART1_DCD_ID              0
-#if      (RTE_UART1_DCD_ID == 0)
-  #define RTE_UART1_DCD_PIN_EN          0
-#elif    (RTE_UART1_DCD_ID == 1)
-  #define RTE_UART1_DCD_PORT            1
-  #define RTE_UART1_DCD_BIT             12
-  #define RTE_UART1_DCD_FUNC            1
-#elif    (RTE_UART1_DCD_ID == 2)
-  #define RTE_UART1_DCD_PORT            5
-  #define RTE_UART1_DCD_BIT             5
-  #define RTE_UART1_DCD_FUNC            4
-#elif    (RTE_UART1_DCD_ID == 3)
-  #define RTE_UART1_DCD_PORT            0xC
-  #define RTE_UART1_DCD_BIT             11
-  #define RTE_UART1_DCD_FUNC            2
-#elif    (RTE_UART1_DCD_ID == 4)
-  #define RTE_UART1_DCD_PORT            0xE
-  #define RTE_UART1_DCD_BIT             9
-  #define RTE_UART1_DCD_FUNC            2
-#else
-  #error "Invalid UART1_DCD Pin Configuration!"
-#endif
-#ifndef   RTE_UART1_DCD_PIN_EN
-  #define RTE_UART1_DCD_PIN_EN          1
-#endif
-//       <o> DSR <0=>Not used <1=>P1_7 <2=>P5_0 <3=>PC_10 <4=>PE_8
-#define   RTE_UART1_DSR_ID              0
-#if      (RTE_UART1_DSR_ID == 0)
-  #define RTE_UART1_DSR_PIN_EN          0
-#elif    (RTE_UART1_DSR_ID == 1)
-  #define RTE_UART1_DSR_PORT            1
-  #define RTE_UART1_DSR_BIT             7
-  #define RTE_UART1_DSR_FUNC            1
-#elif    (RTE_UART1_DSR_ID == 2)
-  #define RTE_UART1_DSR_PORT            5
-  #define RTE_UART1_DSR_BIT             0
-  #define RTE_UART1_DSR_FUNC            4
-#elif    (RTE_UART1_DSR_ID == 3)
-  #define RTE_UART1_DSR_PORT            0xC
-  #define RTE_UART1_DSR_BIT             10
-  #define RTE_UART1_DSR_FUNC            2
-#elif    (RTE_UART1_DSR_ID == 4)
-  #define RTE_UART1_DSR_PORT            0xE
-  #define RTE_UART1_DSR_BIT             8
-  #define RTE_UART1_DSR_FUNC            2
-#else
-  #error "Invalid UART1_DSR Pin Configuration!"
-#endif
-#ifndef   RTE_UART1_DSR_PIN_EN
-  #define RTE_UART1_DSR_PIN_EN          1
-#endif
-//       <o> DTR <0=>Not used <1=>P1_8  <2=>P5_1 <3=>PC_12 <4=>PE_10
-#define   RTE_UART1_DTR_ID              0
-#if      (RTE_UART1_DTR_ID == 0)
-  #define RTE_UART1_DTR_PIN_EN          0
-#elif    (RTE_UART1_DTR_ID == 1)
-  #define RTE_UART1_DTR_PORT            1
-  #define RTE_UART1_DTR_BIT             8
-  #define RTE_UART1_DTR_FUNC            1
-#elif    (RTE_UART1_DTR_ID == 2)
-  #define RTE_UART1_DTR_PORT            5
-  #define RTE_UART1_DTR_BIT             1
-  #define RTE_UART1_DTR_FUNC            4
-#elif    (RTE_UART1_DTR_ID == 3)
-  #define RTE_UART1_DTR_PORT            0xC
-  #define RTE_UART1_DTR_BIT             12
-  #define RTE_UART1_DTR_FUNC            2
-#elif    (RTE_UART1_DTR_ID == 4)
-  #define RTE_UART1_DTR_PORT            0xE
-  #define RTE_UART1_DTR_BIT             10
-  #define RTE_UART1_DTR_FUNC            2
-#else
-  #error "Invalid UART1_DTR Pin Configuration!"
-#endif
-#ifndef   RTE_UART1_DTR_PIN_EN
-  #define RTE_UART1_DTR_PIN_EN          1
-#endif
-//       <o> RI <0=>Not used <1=>P1_10 <2=>P5_3 <3=>PC_1 <4=>PE_6
-#define   RTE_UART1_RI_ID               0
-#if      (RTE_UART1_RI_ID == 0)
-  #define RTE_UART1_RI_PIN_EN           0
-#elif    (RTE_UART1_RI_ID == 1)
-  #define RTE_UART1_RI_PORT             1
-  #define RTE_UART1_RI_BIT              10
-  #define RTE_UART1_RI_FUNC             1
-#elif    (RTE_UART1_RI_ID == 2)
-  #define RTE_UART1_RI_PORT             5
-  #define RTE_UART1_RI_BIT              3
-  #define RTE_UART1_RI_FUNC             4
-#elif    (RTE_UART1_RI_ID == 3)
-  #define RTE_UART1_RI_PORT             0xC
-  #define RTE_UART1_RI_BIT              1
-  #define RTE_UART1_RI_FUNC             2
-#elif    (RTE_UART1_RI_ID == 4)
-  #define RTE_UART1_RI_PORT             0xE
-  #define RTE_UART1_RI_BIT              6
-  #define RTE_UART1_RI_FUNC             2
-#else
-  #error "Invalid UART1_RI Pin Configuration!"
-#endif
-#ifndef   RTE_UART1_RI_PIN_EN
-  #define RTE_UART1_RI_PIN_EN           1
-#endif
-//     </h> Modem Lines
-//   </h> Pin Configuration
-
-//   <h> DMA
-//     <e> Tx
-//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
-//       <o2> Peripheral  <0=>3 (DMAMUXPER3)
-//     </e>
-#define   RTE_UART1_DMA_TX_EN           0
-#define   RTE_UART1_DMA_TX_CH           0
-#define   RTE_UART1_DMA_TX_PERI_ID      0
-#if      (RTE_UART1_DMA_TX_PERI_ID == 0)
-  #define RTE_UART1_DMA_TX_PERI         3
-  #define RTE_UART1_DMA_TX_PERI_SEL     1
-#endif
-//     <e> Rx
-//       <o1> Channel    <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
-//       <o2> Peripheral <0=>4 (DMAMUXPER4)
-//     </e>
-#define   RTE_UART1_DMA_RX_EN           0
-#define   RTE_UART1_DMA_RX_CH           1
-#define   RTE_UART1_DMA_RX_PERI_ID      0
-#if      (RTE_UART1_DMA_RX_PERI_ID == 0)
-  #define RTE_UART1_DMA_RX_PERI         4
-  #define RTE_UART1_DMA_RX_PERI_SEL     1
-#endif
-//   </h> DMA
-// </e> UART1 (Universal asynchronous receiver transmitter) [Driver_USART1]
-
-// <e> USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2]
-#define   RTE_USART2                    0
-
-//   <h> Pin Configuration
-//     <o> TX <0=>Not used <1=>P1_15 <2=>P2_10 <3=>P7_1 <4=>PA_1
-//     <i> USART2 Serial Output pin
-#define   RTE_USART2_TX_ID              0
-#if      (RTE_USART2_TX_ID == 0)
-  #define RTE_USART2_TX_PIN_EN          0
-#elif    (RTE_USART2_TX_ID == 1)
-  #define RTE_USART2_TX_PORT            1
-  #define RTE_USART2_TX_BIT             15
-  #define RTE_USART2_TX_FUNC            1
-#elif    (RTE_USART2_TX_ID == 2)
-  #define RTE_USART2_TX_PORT            2
-  #define RTE_USART2_TX_BIT             10
-  #define RTE_USART2_TX_FUNC            2
-#elif    (RTE_USART2_TX_ID == 3)
-  #define RTE_USART2_TX_PORT            7
-  #define RTE_USART2_TX_BIT             1
-  #define RTE_USART2_TX_FUNC            6
-#elif    (RTE_USART2_TX_ID == 4)
-  #define RTE_USART2_TX_PORT            0xA
-  #define RTE_USART2_TX_BIT             1
-  #define RTE_USART2_TX_FUNC            3
-#else
-  #error "Invalid USART2_TX Pin Configuration!"
-#endif
-#ifndef   RTE_USART2_TX_PIN_EN
-  #define RTE_USART2_TX_PIN_EN          1
-#endif
-//     <o> RX <0=>Not used <1=>P1_16 <2=>P2_11 <3=>P7_2 <4=>PA_2
-//     <i> USART2 Serial Input pin
-#define   RTE_USART2_RX_ID              0
-#if      (RTE_USART2_RX_ID == 0)
-  #define RTE_USART2_RX_PIN_EN          0
-#elif    (RTE_USART2_RX_ID == 1)
-  #define RTE_USART2_RX_PORT            1
-  #define RTE_USART2_RX_BIT             16
-  #define RTE_USART2_RX_FUNC            1
-#elif    (RTE_USART2_RX_ID == 2)
-  #define RTE_USART2_RX_PORT            2
-  #define RTE_USART2_RX_BIT             11
-  #define RTE_USART2_RX_FUNC            2
-#elif    (RTE_USART2_RX_ID == 3)
-  #define RTE_USART2_RX_PORT            7
-  #define RTE_USART2_RX_BIT             2
-  #define RTE_USART2_RX_FUNC            6
-#elif    (RTE_USART2_RX_ID == 4)
-  #define RTE_USART2_RX_PORT            0xA
-  #define RTE_USART2_RX_BIT             2
-  #define RTE_USART2_RX_FUNC            3
-#else
-  #error "Invalid USART2_RX Pin Configuration!"
-#endif
-#ifndef   RTE_USART2_RX_PIN_EN
-  #define RTE_USART2_RX_PIN_EN          1
-#endif
-//       <o> UCLK (Synchronous and SmartCard mode) <0=>Not used <1=>P1_17 <2=>P2_12
-//       <i> USART2 Serial Clock input/output synchronous mode
-#define   RTE_USART2_UCLK_ID            0
-#if      (RTE_USART2_UCLK_ID == 0)
-  #define RTE_USART2_UCLK_PIN_EN        0
-#elif    (RTE_USART2_UCLK_ID == 1)
-  #define RTE_USART2_UCLK_PORT          1
-  #define RTE_USART2_UCLK_BIT           17
-  #define RTE_USART2_UCLK_FUNC          1
-#elif    (RTE_USART2_UCLK_ID == 2)
-  #define RTE_USART2_UCLK_PORT          2
-  #define RTE_USART2_UCLK_BIT           12
-  #define RTE_USART2_UCLK_FUNC          7
-#else
-  #error "Invalid USART2_UCLK Pin Configuration!"
-#endif
-#ifndef   RTE_USART2_UCLK_PIN_EN
-  #define RTE_USART2_UCLK_PIN_EN        1
-#endif
-//   </h> Pin Configuration
-
-//   <h> DMA
-//     <e> Tx
-//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
-//       <o2> Peripheral  <0=>5 (DMAMUXPER5)
-//     </e>
-#define   RTE_USART2_DMA_TX_EN          0
-#define   RTE_USART2_DMA_TX_CH          0
-#define   RTE_USART2_DMA_TX_PERI_ID     0
-#if      (RTE_USART2_DMA_TX_PERI_ID == 0)
-  #define RTE_USART2_DMA_TX_PERI        5
-  #define RTE_USART2_DMA_TX_PERI_SEL    1
-#endif
-//     <e> Rx
-//       <o1> Channel    <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
-//       <o2> Peripheral <0=>6 (DMAMUXPER6)
-//     </e>
-#define   RTE_USART2_DMA_RX_EN          0
-#define   RTE_USART2_DMA_RX_CH          1
-#define   RTE_USART2_DMA_RX_PERI_ID     0
-#if      (RTE_USART2_DMA_RX_PERI_ID == 0)
-  #define RTE_USART2_DMA_RX_PERI        6
-  #define RTE_USART2_DMA_RX_PERI_SEL    1
-#endif
-//   </h> DMA
-// </e> USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2]
-
-// <e> USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3]
-#define   RTE_USART3                    0
-
-//   <h> Pin Configuration
-//     <o> TX <0=>Not used <1=>P2_3 <2=>P4_1 <3=>P9_3 <4=>PF_2
-//     <i> USART3 Serial Output pin
-#define   RTE_USART3_TX_ID              0
-#if      (RTE_USART3_TX_ID == 0)
-  #define RTE_USART3_TX_PIN_EN          0
-#elif    (RTE_USART3_TX_ID == 1)
-  #define RTE_USART3_TX_PORT            2
-  #define RTE_USART3_TX_BIT             3
-  #define RTE_USART3_TX_FUNC            2
-#elif    (RTE_USART3_TX_ID == 2)
-  #define RTE_USART3_TX_PORT            4
-  #define RTE_USART3_TX_BIT             1
-  #define RTE_USART3_TX_FUNC            6
-#elif    (RTE_USART3_TX_ID == 3)
-  #define RTE_USART3_TX_PORT            9
-  #define RTE_USART3_TX_BIT             3
-  #define RTE_USART3_TX_FUNC            7
-#elif    (RTE_USART3_TX_ID == 4)
-  #define RTE_USART3_TX_PORT            0xF
-  #define RTE_USART3_TX_BIT             2
-  #define RTE_USART3_TX_FUNC            1
-#else
-  #error "Invalid USART3_TX Pin Configuration!"
-#endif
-#ifndef   RTE_USART3_TX_PIN_EN
-  #define RTE_USART3_TX_PIN_EN          1
-#endif
-//     <o> RX <0=>Not used <1=>P2_4 <2=>P4_2 <3=>P9_4 <4=>PF_3
-//     <i> USART3 Serial Input pin
-#define   RTE_USART3_RX_ID              0
-#if      (RTE_USART3_RX_ID == 0)
-  #define RTE_USART3_RX_PIN_EN          0
-#elif    (RTE_USART3_RX_ID == 1)
-  #define RTE_USART3_RX_PORT            2
-  #define RTE_USART3_RX_BIT             4
-  #define RTE_USART3_RX_FUNC            2
-#elif    (RTE_USART3_RX_ID == 2)
-  #define RTE_USART3_RX_PORT            4
-  #define RTE_USART3_RX_BIT             2
-  #define RTE_USART3_RX_FUNC            6
-#elif    (RTE_USART3_RX_ID == 3)
-  #define RTE_USART3_RX_PORT            9
-  #define RTE_USART3_RX_BIT             4
-  #define RTE_USART3_RX_FUNC            7
-#elif    (RTE_USART3_RX_ID == 4)
-  #define RTE_USART3_RX_PORT            0xF
-  #define RTE_USART3_RX_BIT             3
-  #define RTE_USART3_RX_FUNC            1
-#else
-  #error "Invalid USART3_RX Pin Configuration!"
-#endif
-#ifndef   RTE_USART3_RX_PIN_EN
-  #define RTE_USART3_RX_PIN_EN          1
-#endif
-//     <o> UCLK (Synchronous and SmartCard mode) <0=>Not used <1=>P2_7 <2=>P4_0 <3=>PF_5
-//     <i> USART3 Serial Clock input/output synchronous mode
-#define   RTE_USART3_UCLK_ID            0
-#if      (RTE_USART3_UCLK_ID == 0)
-  #define RTE_USART3_UCLK_PIN_EN        0
-#elif    (RTE_USART3_UCLK_ID == 1)
-  #define RTE_USART3_UCLK_PORT          2
-  #define RTE_USART3_UCLK_BIT           7
-  #define RTE_USART3_UCLK_FUNC          2
-#elif    (RTE_USART3_UCLK_ID == 2)
-  #define RTE_USART3_UCLK_PORT          4
-  #define RTE_USART3_UCLK_BIT           0
-  #define RTE_USART3_UCLK_FUNC          6
-#elif    (RTE_USART3_UCLK_ID == 3)
-  #define RTE_USART3_UCLK_PORT          0xF
-  #define RTE_USART3_UCLK_BIT           5
-  #define RTE_USART3_UCLK_FUNC          1
-#else
-  #error "Invalid USART3_UCLK Pin Configuration!"
-#endif
-#ifndef   RTE_USART3_UCLK_PIN_EN
-  #define RTE_USART3_UCLK_PIN_EN        1
-#endif
-//   </h> Pin Configuration
-
-//   <h> DMA
-//     <e> Tx
-//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
-//       <o2> Peripheral  <0=>7 (DMAMUXPER7)  <1=>14 (DMAMUXPER14)
-//     </e>
-#define   RTE_USART3_DMA_TX_EN          0
-#define   RTE_USART3_DMA_TX_CH          0
-#define   RTE_USART3_DMA_TX_PERI_ID     0
-#if      (RTE_USART3_DMA_TX_PERI_ID == 0)
-  #define RTE_USART3_DMA_TX_PERI        7
-  #define RTE_USART3_DMA_TX_PERI_SEL    1
-#elif    (RTE_USART3_DMA_TX_PERI_ID == 1)
-  #define RTE_USART3_DMA_TX_PERI        14
-  #define RTE_USART3_DMA_TX_PERI_SEL    3
-#endif
-//     <e> Rx
-//       <o1> Channel    <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
-//       <o2> Peripheral <0=>8 (DMAMUXPER8)  <1=>13 (DMAMUXPER13)
-//     </e>
-#define   RTE_USART3_DMA_RX_EN          0
-#define   RTE_USART3_DMA_RX_CH          1
-#define   RTE_USART3_DMA_RX_PERI_ID     0
-#if      (RTE_USART3_DMA_RX_PERI_ID == 0)
-  #define RTE_USART3_DMA_RX_PERI        8
-  #define RTE_USART3_DMA_RX_PERI_SEL    1
-#elif    (RTE_USART3_DMA_RX_PERI_ID == 1)
-  #define RTE_USART3_DMA_RX_PERI        13
-  #define RTE_USART3_DMA_RX_PERI_SEL    3
-#endif
-//   </h> DMA
-// </e> USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3]
-
-// <e> SSP0 (Synchronous Serial Port 0) [Driver_SPI0]
-// <i> Configuration settings for Driver_SPI0 in component ::Drivers:SPI
-#define   RTE_SSP0                      0
-
-//   <h> Pin Configuration
-//     <o> SSP0_SSEL <0=>Not used <1=>P1_0 <2=>P3_6 <3=>P3_8 <4=>P9_0 <5=>PF_1
-//     <i> Slave Select for SSP0
-#define   RTE_SSP0_SSEL_PIN_SEL         1
-#if      (RTE_SSP0_SSEL_PIN_SEL == 0)
-#define   RTE_SSP0_SSEL_PIN_EN          0
-#elif    (RTE_SSP0_SSEL_PIN_SEL == 1)
-  #define RTE_SSP0_SSEL_PORT            1
-  #define RTE_SSP0_SSEL_BIT             0
-  #define RTE_SSP0_SSEL_FUNC            5
-  #define RTE_SSP0_SSEL_GPIO_FUNC       0
-  #define RTE_SSP0_SSEL_GPIO_PORT       0
-  #define RTE_SSP0_SSEL_GPIO_BIT        4
-#elif    (RTE_SSP0_SSEL_PIN_SEL == 2)
-  #define RTE_SSP0_SSEL_PORT            3
-  #define RTE_SSP0_SSEL_BIT             6
-  #define RTE_SSP0_SSEL_FUNC            2
-  #define RTE_SSP0_SSEL_GPIO_FUNC       0
-  #define RTE_SSP0_SSEL_GPIO_PORT       0
-  #define RTE_SSP0_SSEL_GPIO_BIT        6
-#elif    (RTE_SSP0_SSEL_PIN_SEL == 3)
-  #define RTE_SSP0_SSEL_PORT            3
-  #define RTE_SSP0_SSEL_BIT             8
-  #define RTE_SSP0_SSEL_FUNC            5
-  #define RTE_SSP0_SSEL_GPIO_FUNC       4
-  #define RTE_SSP0_SSEL_GPIO_PORT       5
-  #define RTE_SSP0_SSEL_GPIO_BIT        11
-#elif    (RTE_SSP0_SSEL_PIN_SEL == 4)
-  #define RTE_SSP0_SSEL_PORT            9
-  #define RTE_SSP0_SSEL_BIT             0
-  #define RTE_SSP0_SSEL_FUNC            7
-  #define RTE_SSP0_SSEL_GPIO_FUNC       0
-  #define RTE_SSP0_SSEL_GPIO_PORT       4
-  #define RTE_SSP0_SSEL_GPIO_BIT        12
-#elif    (RTE_SSP0_SSEL_PIN_SEL == 5)
-  #define RTE_SSP0_SSEL_PORT            0xF
-  #define RTE_SSP0_SSEL_BIT             1
-  #define RTE_SSP0_SSEL_FUNC            2
-  #define RTE_SSP0_SSEL_GPIO_FUNC       4
-  #define RTE_SSP0_SSEL_GPIO_PORT       7
-  #define RTE_SSP0_SSEL_GPIO_BIT        16
-#else
-  #error "Invalid SSP0 SSP0_SSEL Pin Configuration!"
-#endif
-#ifndef   RTE_SSP0_SSEL_PIN_EN
-#define   RTE_SSP0_SSEL_PIN_EN          1
-#endif
-//     <o> SSP0_SCK <0=>P3_0 <1=>P3_3 <2=>PF_0
-//     <i> Serial clock for SSP0
-#define   RTE_SSP0_SCK_PIN_SEL          0
-#if      (RTE_SSP0_SCK_PIN_SEL == 0)
-  #define RTE_SSP0_SCK_PORT             3
-  #define RTE_SSP0_SCK_BIT              0
-  #define RTE_SSP0_SCK_FUNC             4
-#elif    (RTE_SSP0_SCK_PIN_SEL == 1)
-  #define RTE_SSP0_SCK_PORT             3
-  #define RTE_SSP0_SCK_BIT              3
-  #define RTE_SSP0_SCK_FUNC             2
-#elif    (RTE_SSP0_SCK_PIN_SEL == 2)
-  #define RTE_SSP0_SCK_PORT             0xF
-  #define RTE_SSP0_SCK_BIT              0
-  #define RTE_SSP0_SCK_FUNC             0
-#else
-  #error "Invalid SSP0 SSP0_SCK Pin Configuration!"
-#endif
-//     <o> SSP0_MISO <0=>Not used <1=>P1_1 <2=>P3_6 <3=>P3_7 <4=>P9_1 <5=>PF_2
-//     <i> Master In Slave Out for SSP0
-#define   RTE_SSP0_MISO_PIN_SEL         0
-#if      (RTE_SSP0_MISO_PIN_SEL == 0)
-  #define RTE_SSP0_MISO_PIN_EN          0
-#elif    (RTE_SSP0_MISO_PIN_SEL == 1)
-  #define RTE_SSP0_MISO_PORT            1
-  #define RTE_SSP0_MISO_BIT             1
-  #define RTE_SSP0_MISO_FUNC            5
-#elif    (RTE_SSP0_MISO_PIN_SEL == 2)
-  #define RTE_SSP0_MISO_PORT            3
-  #define RTE_SSP0_MISO_BIT             6
-  #define RTE_SSP0_MISO_FUNC            5
-#elif    (RTE_SSP0_MISO_PIN_SEL == 3)
-  #define RTE_SSP0_MISO_PORT            3
-  #define RTE_SSP0_MISO_BIT             7
-  #define RTE_SSP0_MISO_FUNC            2
-#elif    (RTE_SSP0_MISO_PIN_SEL == 4)
-  #define RTE_SSP0_MISO_PORT            9
-  #define RTE_SSP0_MISO_BIT             1
-  #define RTE_SSP0_MISO_FUNC            7
-#elif    (RTE_SSP0_MISO_PIN_SEL == 5)
-  #define RTE_SSP0_MISO_PORT            0xF
-  #define RTE_SSP0_MISO_BIT             2
-  #define RTE_SSP0_MISO_FUNC            2
-#else
-  #error "Invalid SSP0 SSP0_MISO Pin Configuration!"
-#endif
-#ifndef   RTE_SSP0_MISO_PIN_EN
-  #define RTE_SSP0_MISO_PIN_EN          1
-#endif
-//     <o> SSP0_MOSI <0=>Not used <1=>P1_2 <2=>P3_7 <3=>P3_8 <4=>P9_2 <5=>PF_3
-//     <i> Master Out Slave In for SSP0
-#define   RTE_SSP0_MOSI_PIN_SEL         0
-#if      (RTE_SSP0_MOSI_PIN_SEL == 0)
-  #define RTE_SSP0_MOSI_PIN_EN          0
-#elif    (RTE_SSP0_MOSI_PIN_SEL == 1)
-  #define RTE_SSP0_MOSI_PORT            1
-  #define RTE_SSP0_MOSI_BIT             2
-  #define RTE_SSP0_MOSI_FUNC            5
-#elif    (RTE_SSP0_MOSI_PIN_SEL == 2)
-  #define RTE_SSP0_MOSI_PORT            3
-  #define RTE_SSP0_MOSI_BIT             7
-  #define RTE_SSP0_MOSI_FUNC            5
-#elif    (RTE_SSP0_MOSI_PIN_SEL == 3)
-  #define RTE_SSP0_MOSI_PORT            3
-  #define RTE_SSP0_MOSI_BIT             8
-  #define RTE_SSP0_MOSI_FUNC            2
-#elif    (RTE_SSP0_MOSI_PIN_SEL == 4)
-  #define RTE_SSP0_MOSI_PORT            9
-  #define RTE_SSP0_MOSI_BIT             2
-  #define RTE_SSP0_MOSI_FUNC            7
-#elif    (RTE_SSP0_MOSI_PIN_SEL == 5)
-  #define RTE_SSP0_MOSI_PORT            0xF
-  #define RTE_SSP0_MOSI_BIT             3
-  #define RTE_SSP0_MOSI_FUNC            2
-#else
-  #error "Invalid SSP0 SSP0_MOSI Pin Configuration!"
-#endif
-#ifndef   RTE_SSP0_MOSI_PIN_EN
-  #define RTE_SSP0_MOSI_PIN_EN          1
-#endif
-//   </h> Pin Configuration
-
-//   <h> DMA
-//     <e> Tx
-//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
-//       <o2> Peripheral  <0=>10 (DMAMUXPER10)
-//     </e>
-#define   RTE_SSP0_DMA_TX_EN            0
-#define   RTE_SSP0_DMA_TX_CH            0
-#define   RTE_SSP0_DMA_TX_PERI_ID       0
-#if      (RTE_SSP0_DMA_TX_PERI_ID == 0)
-  #define RTE_SSP0_DMA_TX_PERI          10
-  #define RTE_SSP0_DMA_TX_PERI_SEL      0
-#endif
-//     <e> Rx
-//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
-//       <o2> Peripheral  <0=>9 (DMAMUXPER9)
-//     </e>
-#define   RTE_SSP0_DMA_RX_EN            0
-#define   RTE_SSP0_DMA_RX_CH            1
-#define   RTE_SSP0_DMA_RX_PERI_ID       0
-#if      (RTE_SSP0_DMA_RX_PERI_ID == 0)
-  #define RTE_SSP0_DMA_RX_PERI          9
-  #define RTE_SSP0_DMA_RX_PERI_SEL      0
-#endif
-//   </h> DMA
-// </e> SSP0 (Synchronous Serial Port 0) [Driver_SPI0]
-
-// <e> SSP1 (Synchronous Serial Port 1) [Driver_SPI1]
-// <i> Configuration settings for Driver_SPI1 in component ::Drivers:SPI
-#define   RTE_SSP1                      0
-
-//   <h> Pin Configuration
-//     <o> SSP1_SSEL <0=>Not used <1=>P1_5 <2=>P1_20 <3=>PF_5
-//     <i> Slave Select for SSP1
-#define   RTE_SSP1_SSEL_PIN_SEL         1
-#if      (RTE_SSP1_SSEL_PIN_SEL == 0)
-  #define RTE_SSP1_SSEL_PIN_EN          0
-#elif    (RTE_SSP1_SSEL_PIN_SEL == 1)
-  #define RTE_SSP1_SSEL_PORT            1
-  #define RTE_SSP1_SSEL_BIT             5
-  #define RTE_SSP1_SSEL_FUNC            5
-  #define RTE_SSP1_SSEL_GPIO_FUNC       0
-  #define RTE_SSP1_SSEL_GPIO_PORT       1
-  #define RTE_SSP1_SSEL_GPIO_BIT        8
-#elif    (RTE_SSP1_SSEL_PIN_SEL == 2)
-  #define RTE_SSP1_SSEL_PORT            1
-  #define RTE_SSP1_SSEL_BIT             20
-  #define RTE_SSP1_SSEL_FUNC            1
-  #define RTE_SSP1_SSEL_GPIO_FUNC       0
-  #define RTE_SSP1_SSEL_GPIO_PORT       0
-  #define RTE_SSP1_SSEL_GPIO_BIT        15
-#elif    (RTE_SSP1_SSEL_PIN_SEL == 3)
-  #define RTE_SSP1_SSEL_PORT            0xF
-  #define RTE_SSP1_SSEL_BIT             5
-  #define RTE_SSP1_SSEL_FUNC            2
-  #define RTE_SSP1_SSEL_GPIO_FUNC       4
-  #define RTE_SSP1_SSEL_GPIO_PORT       7
-  #define RTE_SSP1_SSEL_GPIO_BIT        19
-#else
-  #error "Invalid SSP1 SSP1_SSEL Pin Configuration!"
-#endif
-#ifndef   RTE_SSP1_SSEL_PIN_EN
-#define   RTE_SSP1_SSEL_PIN_EN          1
-#endif
-//     <o> SSP1_SCK <0=>P1_19 <1=>PF_4 <2=>CLK0
-//     <i> Serial clock for SSP1
-#define   RTE_SSP1_SCK_PIN_SEL          0
-#if      (RTE_SSP1_SCK_PIN_SEL == 0)
-  #define RTE_SSP1_SCK_PORT             1
-  #define RTE_SSP1_SCK_BIT              19
-  #define RTE_SSP1_SCK_FUNC             1
-#elif    (RTE_SSP1_SCK_PIN_SEL == 1)
-  #define RTE_SSP1_SCK_PORT             0xF
-  #define RTE_SSP1_SCK_BIT              4
-  #define RTE_SSP1_SCK_FUNC             0
-#elif    (RTE_SSP1_SCK_PIN_SEL == 2)
-  #define RTE_SSP1_SCK_PORT             0x10
-  #define RTE_SSP1_SCK_BIT              0
-  #define RTE_SSP1_SCK_FUNC             6
-#else
-  #error "Invalid SSP1 SSP1_SCK Pin Configuration!"
-#endif
-//     <o> SSP1_MISO <0=>Not used <1=>P0_0 <2=>P1_3 <3=>PF_6
-//     <i> Master In Slave Out for SSP1
-#define   RTE_SSP1_MISO_PIN_SEL         0
-#if      (RTE_SSP1_MISO_PIN_SEL == 0)
-  #define RTE_SSP1_MISO_PIN_EN          0
-#elif    (RTE_SSP1_MISO_PIN_SEL == 1)
-  #define RTE_SSP1_MISO_PORT            0
-  #define RTE_SSP1_MISO_BIT             0
-  #define RTE_SSP1_MISO_FUNC            1
-#elif    (RTE_SSP1_MISO_PIN_SEL == 2)
-  #define RTE_SSP1_MISO_PORT            1
-  #define RTE_SSP1_MISO_BIT             3
-  #define RTE_SSP1_MISO_FUNC            5
-#elif    (RTE_SSP1_MISO_PIN_SEL == 3)
-  #define RTE_SSP1_MISO_PORT            0xF
-  #define RTE_SSP1_MISO_BIT             6
-  #define RTE_SSP1_MISO_FUNC            2
-#else
-  #error "Invalid SSP1 SSP1_MISO Pin Configuration!"
-#endif
-#ifndef   RTE_SSP1_MISO_PIN_EN
-  #define RTE_SSP1_MISO_PIN_EN          1
-#endif
-//     <o> SSP1_MOSI <0=>Not used <1=>P0_1 <2=>P1_4 <3=>PF_7
-//     <i> Master Out Slave In for SSP1
-#define   RTE_SSP1_MOSI_PIN_SEL         0
-#if      (RTE_SSP1_MOSI_PIN_SEL == 0)
-  #define RTE_SSP1_MOSI_PIN_EN          0
-#elif    (RTE_SSP1_MOSI_PIN_SEL == 1)
-  #define RTE_SSP1_MOSI_PORT            0
-  #define RTE_SSP1_MOSI_BIT             1
-  #define RTE_SSP1_MOSI_FUNC            1
-#elif    (RTE_SSP1_MOSI_PIN_SEL == 2)
-  #define RTE_SSP1_MOSI_PORT            1
-  #define RTE_SSP1_MOSI_BIT             4
-  #define RTE_SSP1_MOSI_FUNC            5
-#elif    (RTE_SSP1_MOSI_PIN_SEL == 3)
-  #define RTE_SSP1_MOSI_PORT            0xF
-  #define RTE_SSP1_MOSI_BIT             7
-  #define RTE_SSP1_MOSI_FUNC            2
-#else
-  #error "Invalid SSP1 SSP1_MOSI Pin Configuration!"
-#endif
-#ifndef   RTE_SSP1_MOSI_PIN_EN
-  #define RTE_SSP1_MOSI_PIN_EN          1
-#endif
-//   </h> Pin Configuration
-
-//   <h> DMA
-//     <e> Tx
-//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
-//       <o2> Peripheral  <0=>3 (DMAMUXPER3) <1=>5 (DMAMUXPER5) <2=>12 (DMAMUXPER12) <3=>14 (DMAMUXPER14)
-//     </e>
-#define   RTE_SSP1_DMA_TX_EN            0
-#define   RTE_SSP1_DMA_TX_CH            0
-#define   RTE_SSP1_DMA_TX_PERI_ID       0
-#if      (RTE_SSP1_DMA_TX_PERI_ID == 0)
-  #define RTE_SSP1_DMA_TX_PERI          3
-  #define RTE_SSP1_DMA_TX_PERI_SEL      3
-#elif    (RTE_SSP1_DMA_TX_PERI_ID == 1)
-  #define RTE_SSP1_DMA_TX_PERI          5
-  #define RTE_SSP1_DMA_TX_PERI_SEL      2
-#elif    (RTE_SSP1_DMA_TX_PERI_ID == 2)
-  #define RTE_SSP1_DMA_TX_PERI          12
-  #define RTE_SSP1_DMA_TX_PERI_SEL      0
-#elif    (RTE_SSP1_DMA_TX_PERI_ID == 3)
-  #define RTE_SSP1_DMA_TX_PERI          14
-  #define RTE_SSP1_DMA_TX_PERI_SEL      2
-#endif
-//     <e> Rx
-//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
-//       <o2> Peripheral  <0=>4 (DMAMUXPER4) <1=>6 (DMAMUXPER6) <2=>11 (DMAMUXPER11) <3=>13 (DMAMUXPER13)
-//     </e>
-#define   RTE_SSP1_DMA_RX_EN            0
-#define   RTE_SSP1_DMA_RX_CH            1
-#define   RTE_SSP1_DMA_RX_PERI_ID       0
-#if      (RTE_SSP1_DMA_RX_PERI_ID == 0)
-  #define RTE_SSP1_DMA_RX_PERI          4
-  #define RTE_SSP1_DMA_RX_PERI_SEL      3
-#elif    (RTE_SSP1_DMA_RX_PERI_ID == 1)
-  #define RTE_SSP1_DMA_RX_PERI          6
-  #define RTE_SSP1_DMA_RX_PERI_SEL      2
-#elif    (RTE_SSP1_DMA_RX_PERI_ID == 2)
-  #define RTE_SSP1_DMA_RX_PERI          11
-  #define RTE_SSP1_DMA_RX_PERI_SEL      0
-#elif    (RTE_SSP1_DMA_RX_PERI_ID == 3)
-  #define RTE_SSP1_DMA_RX_PERI          13
-  #define RTE_SSP1_DMA_RX_PERI_SEL      2
-#endif
-//   </h> DMA
-// </e> SSP1 (Synchronous Serial Port 1) [Driver_SPI1]
-
-// <e> SPI (Serial Peripheral Interface) [Driver_SPI2]
-// <i> Configuration settings for Driver_SPI2 in component ::Drivers:SPI
-#define   RTE_SPI                       0
-
-//   <h> Pin Configuration
-//     <o> SPI_SSEL <0=>Not used <1=>P3_8
-//     <i> Slave Select for SPI
-#define   RTE_SPI_SSEL_PIN_SEL          0
-#if      (RTE_SPI_SSEL_PIN_SEL == 0)
-#define   RTE_SPI_SSEL_PIN_EN           0
-#elif    (RTE_SPI_SSEL_PIN_SEL == 1)
-  #define RTE_SPI_SSEL_PORT             3
-  #define RTE_SPI_SSEL_BIT              8
-  #define RTE_SPI_SSEL_FUNC             1
-  #define RTE_SPI_SSEL_GPIO_FUNC        4
-  #define RTE_SPI_SSEL_GPIO_PORT        5
-  #define RTE_SPI_SSEL_GPIO_BIT         11
-#else
-  #error "Invalid SPI SPI_SSEL Pin Configuration!"
-#endif
-#ifndef   RTE_SPI_SSEL_PIN_EN
-#define   RTE_SPI_SSEL_PIN_EN           1
-#endif
-//     <o> SPI_SCK <0=>P3_3
-//     <i> Serial clock for SPI
-#define   RTE_SPI_SCK_PIN_SEL           0
-#if      (RTE_SPI_SCK_PIN_SEL == 0)
-  #define RTE_SPI_SCK_PORT              3
-  #define RTE_SPI_SCK_BIT               3
-  #define RTE_SPI_SCK_FUNC              1
-#else
-  #error "Invalid SPI SPI_SCK Pin Configuration!"
-#endif
-//     <o> SPI_MISO <0=>Not used <1=>P3_6
-//     <i> Master In Slave Out for SPI
-#define   RTE_SPI_MISO_PIN_SEL          0
-#if      (RTE_SPI_MISO_PIN_SEL == 0)
-  #define RTE_SPI_MISO_PIN_EN           0
-#elif    (RTE_SPI_MISO_PIN_SEL == 1)
-  #define RTE_SPI_MISO_PORT             3
-  #define RTE_SPI_MISO_BIT              6
-  #define RTE_SPI_MISO_FUNC             1
-#else
-  #error "Invalid SPI SPI_MISO Pin Configuration!"
-#endif
-#ifndef   RTE_SPI_MISO_PIN_EN
-  #define RTE_SPI_MISO_PIN_EN           1
-#endif
-//     <o> SPI_MOSI <0=>Not used <1=>P3_7
-//     <i> Master Out Slave In for SPI
-#define   RTE_SPI_MOSI_PIN_SEL          0
-#if      (RTE_SPI_MOSI_PIN_SEL == 0)
-  #define RTE_SPI_MOSI_PIN_EN           0
-#elif    (RTE_SPI_MOSI_PIN_SEL == 1)
-  #define RTE_SPI_MOSI_PORT             3
-  #define RTE_SPI_MOSI_BIT              7
-  #define RTE_SPI_MOSI_FUNC             1
-#else
-  #error "Invalid SPI SPI_MOSI Pin Configuration!"
-#endif
-#ifndef   RTE_SPI_MOSI_PIN_EN
-  #define RTE_SPI_MOSI_PIN_EN           1
-#endif
-//   </h> Pin Configuration
-// </e> SPI (Serial Peripheral Interface) [Driver_SPI2]
-
-// <e> I2S0 (Integrated Interchip Sound 0) [Driver_SAI0]
-// <i> Configuration settings for Driver_SAI0 in component ::Drivers:SAI
-#define   RTE_I2S0                      0
-
-//   <h> Pin Configuration
-//     <o> I2S0_RX_SCK <0=>Not used <1=>P3_0 <2=>P6_0 <3=>PF_4
-//     <i> Receive clock for I2S0
-#define   RTE_I2S0_RX_SCK_PIN_SEL       2
-#if      (RTE_I2S0_RX_SCK_PIN_SEL == 0)
-#define   RTE_I2S0_RX_SCK_PIN_EN        0
-#elif    (RTE_I2S0_RX_SCK_PIN_SEL == 1)
-  #define RTE_I2S0_RX_SCK_PORT          3
-  #define RTE_I2S0_RX_SCK_BIT           0
-  #define RTE_I2S0_RX_SCK_FUNC          0
-#elif    (RTE_I2S0_RX_SCK_PIN_SEL == 2)
-  #define RTE_I2S0_RX_SCK_PORT          6
-  #define RTE_I2S0_RX_SCK_BIT           0
-  #define RTE_I2S0_RX_SCK_FUNC          4
-#elif    (RTE_I2S0_RX_SCK_PIN_SEL == 3)
-  #define RTE_I2S0_RX_SCK_PORT          0xF
-  #define RTE_I2S0_RX_SCK_BIT           4
-  #define RTE_I2S0_RX_SCK_FUNC          7
-#else
-  #error "Invalid I2S0 I2S0_RX_SCK Pin Configuration!"
-#endif
-#ifndef   RTE_I2S0_RX_SCK_PIN_EN
-#define   RTE_I2S0_RX_SCK_PIN_EN        1
-#endif
-//     <o> I2S0_RX_WS <0=>Not used <1=>P3_1 <2=>P6_1
-//     <i> Receive word select for I2S0
-#define   RTE_I2S0_RX_WS_PIN_SEL        2
-#if      (RTE_I2S0_RX_WS_PIN_SEL == 0)
-#define   RTE_I2S0_RX_WS_PIN_EN         0
-#elif    (RTE_I2S0_RX_WS_PIN_SEL == 1)
-  #define RTE_I2S0_RX_WS_PORT           3
-  #define RTE_I2S0_RX_WS_BIT            1
-  #define RTE_I2S0_RX_WS_FUNC           1
-#elif    (RTE_I2S0_RX_WS_PIN_SEL == 2)
-  #define RTE_I2S0_RX_WS_PORT           6
-  #define RTE_I2S0_RX_WS_BIT            1
-  #define RTE_I2S0_RX_WS_FUNC           3
-#else
-  #error "Invalid I2S0 I2S0_RX_WS Pin Configuration!"
-#endif
-#ifndef   RTE_I2S0_RX_WS_PIN_EN
-#define   RTE_I2S0_RX_WS_PIN_EN         1
-#endif
-//     <o> I2S0_RX_SDA <0=>Not used <1=>P3_2 <2=>P6_2
-//     <i> Receive master clock for I2S0
-#define   RTE_I2S0_RX_SDA_PIN_SEL       2
-#if      (RTE_I2S0_RX_SDA_PIN_SEL == 0)
-#define   RTE_I2S0_RX_SDA_PIN_EN        0
-#elif    (RTE_I2S0_RX_SDA_PIN_SEL == 1)
-  #define RTE_I2S0_RX_SDA_PORT          3
-  #define RTE_I2S0_RX_SDA_BIT           2
-  #define RTE_I2S0_RX_SDA_FUNC          1
-#elif    (RTE_I2S0_RX_SDA_PIN_SEL == 2)
-  #define RTE_I2S0_RX_SDA_PORT          6
-  #define RTE_I2S0_RX_SDA_BIT           2
-  #define RTE_I2S0_RX_SDA_FUNC          3
-#else
-  #error "Invalid I2S0 I2S0_RX_SDA Pin Configuration!"
-#endif
-#ifndef   RTE_I2S0_RX_SDA_PIN_EN
-#define   RTE_I2S0_RX_SDA_PIN_EN       1
-#endif
-//     <o> I2S0_RX_MCLK <0=>Not used <1=>P1_19 <2=>P3_0 <3=>P6_0
-//     <i> Receive master clock for I2S0
-#define   RTE_I2S0_RX_MCLK_PIN_SEL      0
-#if      (RTE_I2S0_RX_MCLK_PIN_SEL == 0)
-#define   RTE_I2S0_RX_MCLK_PIN_EN       0
-#elif    (RTE_I2S0_RX_MCLK_PIN_SEL == 1)
-  #define RTE_I2S0_RX_MCLK_PORT         1
-  #define RTE_I2S0_RX_MCLK_BIT          19
-  #define RTE_I2S0_RX_MCLK_FUNC         6
-#elif    (RTE_I2S0_RX_MCLK_PIN_SEL == 2)
-  #define RTE_I2S0_RX_MCLK_PORT         3
-  #define RTE_I2S0_RX_MCLK_BIT          0
-  #define RTE_I2S0_RX_MCLK_FUNC         1
-#elif    (RTE_I2S0_RX_MCLK_PIN_SEL == 3)
-  #define RTE_I2S0_RX_MCLK_PORT         6
-  #define RTE_I2S0_RX_MCLK_BIT          0
-  #define RTE_I2S0_RX_MCLK_FUNC         1
-#else
-  #error "Invalid I2S0 I2S0_RX_MCLK Pin Configuration!"
-#endif
-#ifndef   RTE_I2S0_RX_MCLK_PIN_EN
-#define   RTE_I2S0_RX_MCLK_PIN_EN       1
-#endif
-//     <o> I2S0_TX_SCK <0=>Not used <1=>P3_0 <2=>P4_7
-//     <i> Transmit clock for I2S0
-#define   RTE_I2S0_TX_SCK_PIN_SEL       1
-#if      (RTE_I2S0_TX_SCK_PIN_SEL == 0)
-#define   RTE_I2S0_TX_SCK_PIN_EN        0
-#elif    (RTE_I2S0_TX_SCK_PIN_SEL == 1)
-  #define RTE_I2S0_TX_SCK_PORT          3
-  #define RTE_I2S0_TX_SCK_BIT           0
-  #define RTE_I2S0_TX_SCK_FUNC          2
-#elif    (RTE_I2S0_TX_SCK_PIN_SEL == 2)
-  #define RTE_I2S0_TX_SCK_PORT          4
-  #define RTE_I2S0_TX_SCK_BIT           7
-  #define RTE_I2S0_TX_SCK_FUNC          7
-#else
-  #error "Invalid I2S0 I2S0_TX_SCK Pin Configuration!"
-#endif
-#ifndef   RTE_I2S0_TX_SCK_PIN_EN
-#define   RTE_I2S0_TX_SCK_PIN_EN        1
-#endif
-//     <o> I2S0_TX_WS <0=>Not used <1=>P0_0 <2=>P3_1 <3=>P3_4 <4=>P7_1 <5=>P9_1 <6=>PC_13
-//     <i> Transmit word select for I2S0
-#define   RTE_I2S0_TX_WS_PIN_SEL        4
-#if      (RTE_I2S0_TX_WS_PIN_SEL == 0)
-#define   RTE_I2S0_TX_WS_PIN_EN         0
-#elif    (RTE_I2S0_TX_WS_PIN_SEL == 1)
-  #define RTE_I2S0_TX_WS_PORT           0
-  #define RTE_I2S0_TX_WS_BIT            0
-  #define RTE_I2S0_TX_WS_FUNC           6
-#elif    (RTE_I2S0_TX_WS_PIN_SEL == 2)
-  #define RTE_I2S0_TX_WS_PORT           3
-  #define RTE_I2S0_TX_WS_BIT            1
-  #define RTE_I2S0_TX_WS_FUNC           0
-#elif    (RTE_I2S0_TX_WS_PIN_SEL == 3)
-  #define RTE_I2S0_TX_WS_PORT           3
-  #define RTE_I2S0_TX_WS_BIT            4
-  #define RTE_I2S0_TX_WS_FUNC           5
-#elif    (RTE_I2S0_TX_WS_PIN_SEL == 4)
-  #define RTE_I2S0_TX_WS_PORT           7
-  #define RTE_I2S0_TX_WS_BIT            1
-  #define RTE_I2S0_TX_WS_FUNC           2
-#elif    (RTE_I2S0_TX_WS_PIN_SEL == 5)
-  #define RTE_I2S0_TX_WS_PORT           9
-  #define RTE_I2S0_TX_WS_BIT            1
-  #define RTE_I2S0_TX_WS_FUNC           4
-#elif    (RTE_I2S0_TX_WS_PIN_SEL == 6)
-  #define RTE_I2S0_TX_WS_PORT           0xC
-  #define RTE_I2S0_TX_WS_BIT            13
-  #define RTE_I2S0_TX_WS_FUNC           6
-#else
-  #error "Invalid I2S0 I2S0_TX_WS Pin Configuration!"
-#endif
-#ifndef   RTE_I2S0_TX_WS_PIN_EN
-#define   RTE_I2S0_TX_WS_PIN_EN         1
-#endif
-//     <o> I2S0_TX_SDA <0=>Not used <1=>P3_2 <2=>P3_5 <3=>P7_2 <4=>P9_2  <5=>PC_12
-//     <i> Transmit data for I2S0
-#define   RTE_I2S0_TX_SDA_PIN_SEL       3
-#if      (RTE_I2S0_TX_SDA_PIN_SEL == 0)
-#define   RTE_I2S0_TX_SDA_PIN_EN        0
-#elif    (RTE_I2S0_TX_SDA_PIN_SEL == 1)
-  #define RTE_I2S0_TX_SDA_PORT          3
-  #define RTE_I2S0_TX_SDA_BIT           2
-  #define RTE_I2S0_TX_SDA_FUNC          0
-#elif    (RTE_I2S0_TX_SDA_PIN_SEL == 2)
-  #define RTE_I2S0_TX_SDA_PORT          3
-  #define RTE_I2S0_TX_SDA_BIT           5
-  #define RTE_I2S0_TX_SDA_FUNC          5
-#elif    (RTE_I2S0_TX_SDA_PIN_SEL == 3)
-  #define RTE_I2S0_TX_SDA_PORT          7
-  #define RTE_I2S0_TX_SDA_BIT           2
-  #define RTE_I2S0_TX_SDA_FUNC          2
-#elif    (RTE_I2S0_TX_SDA_PIN_SEL == 4)
-  #define RTE_I2S0_TX_SDA_PORT          9
-  #define RTE_I2S0_TX_SDA_BIT           2
-  #define RTE_I2S0_TX_SDA_FUNC          4
-#elif    (RTE_I2S0_TX_SDA_PIN_SEL == 5)
-  #define RTE_I2S0_TX_SDA_PORT          0xC
-  #define RTE_I2S0_TX_SDA_BIT           12
-  #define RTE_I2S0_TX_SDA_FUNC          6
-#else
-  #error "Invalid I2S0 I2S0_TX_SDA Pin Configuration!"
-#endif
-#ifndef   RTE_I2S0_TX_SDA_PIN_EN
-#define   RTE_I2S0_TX_SDA_PIN_EN        1
-#endif
-//     <o> I2S0_TX_MCLK <0=>Not used <1=>P3_0 <2=>P3_3 <3=>PF_4 <4=>CLK2
-//     <i> Transmit master clock for I2S0
-#define   RTE_I2S0_TX_MCLK_PIN_SEL      2
-#if      (RTE_I2S0_TX_MCLK_PIN_SEL == 0)
-#define   RTE_I2S0_TX_MCLK_PIN_EN       0
-#elif    (RTE_I2S0_TX_MCLK_PIN_SEL == 1)
-  #define RTE_I2S0_TX_MCLK_PORT         3
-  #define RTE_I2S0_TX_MCLK_BIT          0
-  #define RTE_I2S0_TX_MCLK_FUNC         3
-#elif    (RTE_I2S0_TX_MCLK_PIN_SEL == 2)
-  #define RTE_I2S0_TX_MCLK_PORT         3
-  #define RTE_I2S0_TX_MCLK_BIT          3
-  #define RTE_I2S0_TX_MCLK_FUNC         6
-#elif    (RTE_I2S0_TX_MCLK_PIN_SEL == 3)
-  #define RTE_I2S0_TX_MCLK_PORT         0xf
-  #define RTE_I2S0_TX_MCLK_BIT          4
-  #define RTE_I2S0_TX_MCLK_FUNC         6
-#elif    (RTE_I2S0_TX_MCLK_PIN_SEL == 4)
-  #define RTE_I2S0_TX_MCLK_PORT         0x10
-  #define RTE_I2S0_TX_MCLK_BIT          2
-  #define RTE_I2S0_TX_MCLK_FUNC         6
-#else
-  #error "Invalid I2S0 I2S0_TX_MCLK Pin Configuration!"
-#endif
-#ifndef   RTE_I2S0_TX_MCLK_PIN_EN
-#define   RTE_I2S0_TX_MCLK_PIN_EN       1
-#endif
-//   </h> Pin Configuration
-
-//   <h> DMA
-//     <e> Tx
-//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
-//       <o2> Peripheral  <0=>9 (DMAMUXPER9)
-//     </e>
-#define   RTE_I2S0_DMA_TX_EN            0
-#define   RTE_I2S0_DMA_TX_CH            0
-#define   RTE_I2S0_DMA_TX_PERI_ID       0
-#if      (RTE_I2S0_DMA_TX_PERI_ID == 0)
-  #define RTE_I2S0_DMA_TX_PERI          9
-  #define RTE_I2S0_DMA_TX_PERI_SEL      1
-#endif
-//     <e> Rx
-//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
-//       <o2> Peripheral  <0=>10 (DMAMUXPER10)
-//     </e>
-#define   RTE_I2S0_DMA_RX_EN            0
-#define   RTE_I2S0_DMA_RX_CH            1
-#define   RTE_I2S0_DMA_RX_PERI_ID       0
-#if      (RTE_I2S0_DMA_RX_PERI_ID == 0)
-  #define RTE_I2S0_DMA_RX_PERI          10
-  #define RTE_I2S0_DMA_RX_PERI_SEL      1
-#endif
-//   </h> DMA
-// </e> I2S0 (Integrated Interchip Sound 0) [Driver_SAI0]
-
-// <e> I2S1 (Integrated Interchip Sound 1) [Driver_SAI1]
-// <i> Configuration settings for Driver_I2S1 in component ::Drivers:SAI
-#define   RTE_I2S1                      0
-
-//   <h> Pin Configuration
-//     <o> I2S1_RX_SCK <0=>Not used <1=>CLK2 <2=>CLK3
-//     <i> Receive clock for I2S1
-#define   RTE_I2S1_RX_SCK_PIN_SEL       0
-#if      (RTE_I2S1_RX_SCK_PIN_SEL == 0)
-#define   RTE_I2S1_RX_SCK_PIN_EN        0
-#elif    (RTE_I2S1_RX_SCK_PIN_SEL == 1)
-  #define RTE_I2S1_RX_SCK_PORT          0x10
-  #define RTE_I2S1_RX_SCK_BIT           2
-  #define RTE_I2S1_RX_SCK_FUNC          7
-#elif    (RTE_I2S1_RX_SCK_PIN_SEL == 2)
-  #define RTE_I2S1_RX_SCK_PORT          0x10
-  #define RTE_I2S1_RX_SCK_BIT           3
-  #define RTE_I2S1_RX_SCK_FUNC          7
-#else
-  #error "Invalid I2S1 I2S1_RX_SCK Pin Configuration!"
-#endif
-#ifndef   RTE_I2S1_RX_SCK_PIN_EN
-#define   RTE_I2S1_RX_SCK_PIN_EN        1
-#endif
-//     <o> I2S1_RX_WS <0=>Not used <1=>P3_5
-//     <i> Receive word select for I2S1
-#define   RTE_I2S1_RX_WS_PIN_SEL        0
-#if      (RTE_I2S1_RX_WS_PIN_SEL == 0)
-#define   RTE_I2S1_RX_WS_PIN_EN         0
-#elif    (RTE_I2S1_RX_WS_PIN_SEL == 1)
-  #define RTE_I2S1_RX_WS_PORT           3
-  #define RTE_I2S1_RX_WS_BIT            5
-  #define RTE_I2S1_RX_WS_FUNC           6
-#else
-  #error "Invalid I2S1 I2S1_RX_WS Pin Configuration!"
-#endif
-#ifndef   RTE_I2S1_RX_WS_PIN_EN
-#define   RTE_I2S1_RX_WS_PIN_EN         1
-#endif
-//     <o> I2S1_RX_SDA <0=>Not used <1=>P3_4
-//     <i> Receive master clock for I2S1
-#define   RTE_I2S1_RX_SDA_PIN_SEL       0
-#if      (RTE_I2S1_RX_SDA_PIN_SEL == 0)
-#define   RTE_I2S1_RX_SDA_PIN_EN        0
-#elif    (RTE_I2S1_RX_SDA_PIN_SEL == 1)
-  #define RTE_I2S1_RX_SDA_PORT          3
-  #define RTE_I2S1_RX_SDA_BIT           4
-  #define RTE_I2S1_RX_SDA_FUNC          6
-#else
-  #error "Invalid I2S1 I2S1_RX_SDA Pin Configuration!"
-#endif
-#ifndef   RTE_I2S1_RX_SDA_PIN_EN
-#define   RTE_I2S1_RX_SDA_PIN_EN       1
-#endif
-//     <o> I2S1_RX_MCLK <0=>Not used <1=>PA_0
-//     <i> Receive master clock for I2S1
-#define   RTE_I2S1_RX_MCLK_PIN_SEL      0
-#if      (RTE_I2S1_RX_MCLK_PIN_SEL == 0)
-#define   RTE_I2S1_RX_MCLK_PIN_EN       0
-#elif    (RTE_I2S1_RX_MCLK_PIN_SEL == 1)
-  #define RTE_I2S1_RX_MCLK_PORT         0x0A
-  #define RTE_I2S1_RX_MCLK_BIT          0
-  #define RTE_I2S1_RX_MCLK_FUNC         5
-#else
-  #error "Invalid I2S1 I2S1_RX_MCLK Pin Configuration!"
-#endif
-#ifndef   RTE_I2S1_RX_MCLK_PIN_EN
-#define   RTE_I2S1_RX_MCLK_PIN_EN       1
-#endif
-//     <o> I2S1_TX_SCK <0=>Not used <1=>P1_19 <2=>P3_3 <3=>P4_7
-//     <i> Transmit clock for I2S1
-#define   RTE_I2S1_TX_SCK_PIN_SEL       0
-#if      (RTE_I2S1_TX_SCK_PIN_SEL == 0)
-#define   RTE_I2S1_TX_SCK_PIN_EN        0
-#elif    (RTE_I2S1_TX_SCK_PIN_SEL == 1)
-  #define RTE_I2S1_TX_SCK_PORT          1
-  #define RTE_I2S1_TX_SCK_BIT           19
-  #define RTE_I2S1_TX_SCK_FUNC          7
-#elif    (RTE_I2S1_TX_SCK_PIN_SEL == 2)
-  #define RTE_I2S1_TX_SCK_PORT          3
-  #define RTE_I2S1_TX_SCK_BIT           3
-  #define RTE_I2S1_TX_SCK_FUNC          7
-#elif    (RTE_I2S1_TX_SCK_PIN_SEL == 3)
-  #define RTE_I2S1_TX_SCK_PORT          4
-  #define RTE_I2S1_TX_SCK_BIT           7
-  #define RTE_I2S1_TX_SCK_FUNC          6
-#else
-  #error "Invalid I2S1 I2S1_TX_SCK Pin Configuration!"
-#endif
-#ifndef   RTE_I2S1_TX_SCK_PIN_EN
-#define   RTE_I2S1_TX_SCK_PIN_EN        1
-#endif
-//     <o> I2S1_TX_WS <0=>Not used <1=>P0_0 <2=>PF_7
-//     <i> Transmit word select for I2S1
-#define   RTE_I2S1_TX_WS_PIN_SEL        0
-#if      (RTE_I2S1_TX_WS_PIN_SEL == 0)
-#define   RTE_I2S1_TX_WS_PIN_EN         0
-#elif    (RTE_I2S1_TX_WS_PIN_SEL == 1)
-  #define RTE_I2S1_TX_WS_PORT           0
-  #define RTE_I2S1_TX_WS_BIT            0
-  #define RTE_I2S1_TX_WS_FUNC           7
-#elif    (RTE_I2S1_TX_WS_PIN_SEL == 2)
-  #define RTE_I2S1_TX_WS_PORT           0x0F
-  #define RTE_I2S1_TX_WS_BIT            7
-  #define RTE_I2S1_TX_WS_FUNC           7
-#else
-  #error "Invalid I2S1 I2S1_TX_WS Pin Configuration!"
-#endif
-#ifndef   RTE_I2S1_TX_WS_PIN_EN
-#define   RTE_I2S1_TX_WS_PIN_EN         1
-#endif
-//     <o> I2S1_TX_SDA <0=>Not used <1=>P0_1 <2=>PF_6
-//     <i> Transmit data for I2S
-#define   RTE_I2S1_TX_SDA_PIN_SEL       0
-#if      (RTE_I2S1_TX_SDA_PIN_SEL == 0)
-#define   RTE_I2S1_TX_SDA_PIN_EN        0
-#elif    (RTE_I2S1_TX_SDA_PIN_SEL == 1)
-  #define RTE_I2S1_TX_SDA_PORT          0
-  #define RTE_I2S1_TX_SDA_BIT           1
-  #define RTE_I2S1_TX_SDA_FUNC          7
-#elif    (RTE_I2S1_TX_SDA_PIN_SEL == 2)
-  #define RTE_I2S1_TX_SDA_PORT          0x0F
-  #define RTE_I2S1_TX_SDA_BIT           6
-  #define RTE_I2S1_TX_SDA_FUNC          7
-#else
-  #error "Invalid I2S1 I2S1_TX_SDA Pin Configuration!"
-#endif
-#ifndef   RTE_I2S1_TX_SDA_PIN_EN
-#define   RTE_I2S1_TX_SDA_PIN_EN        1
-#endif
-//     <o> I2S1_TX_MCLK <0=>Not used <1=>P8_8 <2=>PF_0 <3=>CLK1
-//     <i> Transmit master clock for I2S1
-#define   RTE_I2S1_TX_MCLK_PIN_SEL      0
-#if      (RTE_I2S1_TX_MCLK_PIN_SEL == 0)
-#define   RTE_I2S1_TX_MCLK_PIN_EN       0
-#elif    (RTE_I2S1_TX_MCLK_PIN_SEL == 1)
-  #define RTE_I2S1_TX_MCLK_PORT         8
-  #define RTE_I2S1_TX_MCLK_BIT          8
-  #define RTE_I2S1_TX_MCLK_FUNC         7
-#elif    (RTE_I2S1_TX_MCLK_PIN_SEL == 2)
-  #define RTE_I2S1_TX_MCLK_PORT         0x0F
-  #define RTE_I2S1_TX_MCLK_BIT          0
-  #define RTE_I2S1_TX_MCLK_FUNC         7
-#elif    (RTE_I2S1_TX_MCLK_PIN_SEL == 3)
-  #define RTE_I2S1_TX_MCLK_PORT         0x10
-  #define RTE_I2S1_TX_MCLK_BIT          1
-  #define RTE_I2S1_TX_MCLK_FUNC         7
-#else
-  #error "Invalid I2S1 I2S1_TX_MCLK Pin Configuration!"
-#endif
-#ifndef   RTE_I2S1_TX_MCLK_PIN_EN
-#define   RTE_I2S1_TX_MCLK_PIN_EN       1
-#endif
-//   </h> Pin Configuration
-
-//   <h> DMA
-//     <e> Tx
-//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
-//       <o2> Peripheral  <0=>3 (DMAMUXPER3)
-//     </e>
-#define   RTE_I2S1_DMA_TX_EN            0
-#define   RTE_I2S1_DMA_TX_CH            0
-#define   RTE_I2S1_DMA_TX_PERI_ID       0
-#if      (RTE_I2S1_DMA_TX_PERI_ID == 0)
-  #define RTE_I2S1_DMA_TX_PERI          3
-  #define RTE_I2S1_DMA_TX_PERI_SEL      2
-#endif
-//     <e> Rx
-//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
-//       <o2> Peripheral  <0=>4 (DMAMUXPER4)
-//     </e>
-#define   RTE_I2S1_DMA_RX_EN            0
-#define   RTE_I2S1_DMA_RX_CH            1
-#define   RTE_I2S1_DMA_RX_PERI_ID       0
-#if      (RTE_I2S1_DMA_RX_PERI_ID == 0)
-  #define RTE_I2S1_DMA_RX_PERI          4
-  #define RTE_I2S1_DMA_RX_PERI_SEL      2
-#endif
-//   </h> DMA
-// </e> I2S1 (Integrated Interchip Sound 1) [Driver_SAI1]
-
-// <e> CAN0 Controller [Driver_CAN0]
-// <i> Configuration settings for Driver_CAN0 in component ::Drivers:CAN
-#define   RTE_CAN_CAN0                  0
-
-//   <h> Pin Configuration
-//     <o> CAN0_RD <0=>Not used <1=>P3_1 <2=>PE_2
-//     <i> CAN0 receiver input.
-#define   RTE_CAN0_RD_ID                0
-#if      (RTE_CAN0_RD_ID == 0)
-  #define RTE_CAN0_RD_PIN_EN            0
-#elif    (RTE_CAN0_RD_ID == 1)
-  #define RTE_CAN0_RD_PORT              3
-  #define RTE_CAN0_RD_BIT               1
-  #define RTE_CAN0_RD_FUNC              2
-#elif    (RTE_CAN0_RD_ID == 2)
-  #define RTE_CAN0_RD_PORT              0xE
-  #define RTE_CAN0_RD_BIT               2
-  #define RTE_CAN0_RD_FUNC              1
-#else
-  #error "Invalid RTE_CAN0_RD Pin Configuration!"
-#endif
-#ifndef   RTE_CAN0_RD_PIN_EN
-  #define RTE_CAN0_RD_PIN_EN            1
-#endif
-//     <o> CAN0_TD <0=>Not used <1=>P3_2 <2=>PE_3
-//     <i> CAN0 transmitter output.
-#define   RTE_CAN0_TD_ID                0
-#if      (RTE_CAN0_TD_ID == 0)
-  #define RTE_CAN0_TD_PIN_EN            0
-#elif    (RTE_CAN0_TD_ID == 1)
-  #define RTE_CAN0_TD_PORT              3
-  #define RTE_CAN0_TD_BIT               2
-  #define RTE_CAN0_TD_FUNC              2
-#elif    (RTE_CAN0_TD_ID == 2)
-  #define RTE_CAN0_TD_PORT              0xE
-  #define RTE_CAN0_TD_BIT               3
-  #define RTE_CAN0_TD_FUNC              1
-#else
-  #error "Invalid RTE_CAN0_TD Pin Configuration!"
-#endif
-#ifndef   RTE_CAN0_TD_PIN_EN
-  #define RTE_CAN0_TD_PIN_EN            1
-#endif
-//   </h> Pin Configuration
-// </e> CAN0 Controller [Driver_CAN0]
-
-// <e> CAN1 Controller [Driver_CAN1]
-// <i> Configuration settings for Driver_CAN1 in component ::Drivers:CAN
-#define   RTE_CAN_CAN1                  0
-
-//   <h> Pin Configuration
-//     <o> CAN1_RD <0=>Not used <1=>P1_18 <2=>P4_9 <3=>PE_1
-//     <i> CAN1 receiver input.
-#define   RTE_CAN1_RD_ID                0
-#if      (RTE_CAN1_RD_ID == 0)
-  #define RTE_CAN1_RD_PIN_EN            0
-#elif    (RTE_CAN1_RD_ID == 1)
-  #define RTE_CAN1_RD_PORT              1
-  #define RTE_CAN1_RD_BIT               18
-  #define RTE_CAN1_RD_FUNC              5
-#elif    (RTE_CAN1_RD_ID == 2)
-  #define RTE_CAN1_RD_PORT              4
-  #define RTE_CAN1_RD_BIT               9
-  #define RTE_CAN1_RD_FUNC              6
-#elif    (RTE_CAN1_RD_ID == 3)
-  #define RTE_CAN1_RD_PORT              0xE
-  #define RTE_CAN1_RD_BIT               1
-  #define RTE_CAN1_RD_FUNC              5
-#else
-  #error "Invalid RTE_CAN1_RD Pin Configuration!"
-#endif
-#ifndef   RTE_CAN1_RD_PIN_EN
-  #define RTE_CAN1_RD_PIN_EN            1
-#endif
-//     <o> CAN1_TD <0=>Not used <1=>P1_17 <2=>P4_8 <3=>PE_0
-//     <i> CAN1 transmitter output.
-#define   RTE_CAN1_TD_ID                0
-#if      (RTE_CAN1_TD_ID == 0)
-  #define RTE_CAN1_TD_PIN_EN            0
-#elif    (RTE_CAN1_TD_ID == 1)
-  #define RTE_CAN1_TD_PORT              1
-  #define RTE_CAN1_TD_BIT               17
-  #define RTE_CAN1_TD_FUNC              5
-#elif    (RTE_CAN1_TD_ID == 2)
-  #define RTE_CAN1_TD_PORT              4
-  #define RTE_CAN1_TD_BIT               8
-  #define RTE_CAN1_TD_FUNC              6
-#elif    (RTE_CAN1_TD_ID == 3)
-  #define RTE_CAN1_TD_PORT              0xE
-  #define RTE_CAN1_TD_BIT               0
-  #define RTE_CAN1_TD_FUNC              5
-#else
-  #error "Invalid RTE_CAN1_TD Pin Configuration!"
-#endif
-#ifndef   RTE_CAN1_TD_PIN_EN
-  #define RTE_CAN1_TD_PIN_EN            1
-#endif
-//   </h> Pin Configuration
-// </e> CAN1 Controller [Driver_CAN1]
-
-
-#endif  /* __RTE_DEVICE_H */

CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/RTE/USB/USBD_Config_HID_0.h

@@ -1,167 +0,0 @@
-/*------------------------------------------------------------------------------
- * MDK Middleware - Component ::USB:Device
- * Copyright (c) 2004-2020 Arm Limited (or its affiliates). All rights reserved.
- *------------------------------------------------------------------------------
- * Name:    USBD_Config_HID_0.h
- * Purpose: USB Device Human Interface Device class (HID) Configuration
- * Rev.:    V5.0.2
- *----------------------------------------------------------------------------*/
-
-//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
-
-// <h>USB Device: Human Interface Device class (HID) 0
-//   <o>Assign Device Class to USB Device # <0-3>
-//   <i>Select USB Device that is used for this Device Class instance
-#define USBD_HID0_DEV                             0
-
-//   <h>Interrupt Endpoint Settings
-//   <i>By default, the settings match the first USB Class instance in a USB Device.
-//   <i>Endpoint conflicts are flagged by compile-time error messages.
-//
-//     <h>Interrupt IN Endpoint Settings
-//       <o.0..3>Interrupt IN Endpoint Number
-//                 <1=>1   <2=>2   <3=>3   <4=>4   <5=>5   <6=>6   <7=>7
-//         <8=>8   <9=>9   <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
-#define USBD_HID0_EP_INT_IN                       1
-
-//       <h>Endpoint Settings
-//         <i>Parameters are used to create Endpoint Descriptors
-//         <i>and for memory allocation in the USB component.
-//
-//         <h>Full/Low-speed (High-speed disabled)
-//         <i>Parameters apply when High-speed is disabled in USBD_Config_n.c
-//           <o.0..6>Maximum Endpoint Packet Size (in bytes) <0-64>
-//           <i>Specifies the physical packet size used for information exchange.
-//           <i>Maximum value is 64.
-#define USBD_HID0_EP_INT_IN_WMAXPACKETSIZE        64
-
-//           <o.0..7>Endpoint polling Interval (in ms) <1-255>
-//           <i>Specifies the frequency of requests initiated by USB Host for getting data.
-#define USBD_HID0_EP_INT_IN_BINTERVAL             1
-
-//         </h>
-
-//         <h>High-speed
-//         <i>Parameters apply when High-speed is enabled in USBD_Config_n.c
-//
-//           <o.0..10>Maximum Endpoint Packet Size (in bytes) <0-1024>
-//           <i>Specifies the physical packet size used for information exchange.
-//           <i>Maximum value is 1024.
-//           <o.11..12>Additional transactions per microframe
-//           <i>Additional transactions improve communication performance.
-//             <0=>None <1=>1 additional <2=>2 additional
-#define USBD_HID0_EP_INT_IN_HS_WMAXPACKETSIZE     64
-
-//           <o.0..4>Endpoint polling Interval (in 125 us intervals)
-//           <i>Specifies the frequency of requests initiated by USB Host for getting data.
-//             <1=>    1 <2=>    2 <3=>     4 <4=>     8
-//             <5=>   16 <6=>   32 <7=>    64 <8=>   128
-//             <9=>  256 <10=> 512 <11=> 1024 <12=> 2048
-//             <13=>4096 <14=>8192 <15=>16384 <16=>32768
-#define USBD_HID0_EP_INT_IN_HS_BINTERVAL          1
-
-//         </h>
-//       </h>
-//     </h>
-
-//     <h>Interrupt OUT Endpoint Settings
-//       <o.0..3>Interrupt OUT Endpoint Number
-//         <i>When OUT Endpoint is set to "Not used" the USB Host uses
-//         <i>the Control Endpoint 0 for Out Reports.
-//         <0=>Not used
-//                 <1=>1   <2=>2   <3=>3   <4=>4   <5=>5   <6=>6   <7=>7
-//         <8=>8   <9=>9   <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
-#define USBD_HID0_EP_INT_OUT                      1
-
-//       <h>Endpoint Settings
-//         <i>Parameters are used to create USB Descriptors, HID Device Descriptor
-//         <i>and for memory allocation in the USB component.
-//
-//         <h>Full/Low-speed (High-speed disabled)
-//         <i>Parameters apply when High-speed is disabled in USBD_Config_n.c
-//           <o.0..6>Maximum Endpoint Packet Size (in bytes) <0-64>
-//           <i>Specifies the physical packet size used for information exchange.
-//           <i>Maximum value is 64.
-#define USBD_HID0_EP_INT_OUT_WMAXPACKETSIZE       64
-
-//           <o.0..7>Endpoint polling Interval (in ms) <1-255>
-//           <i>Specifies the frequency of requests sent by USB Host for setting data.
-#define USBD_HID0_EP_INT_OUT_BINTERVAL            1
-
-//         </h>
-
-//         <h>High-speed
-//         <i>Parameters apply when High-speed is enabled in USBD_Config_n.c
-//
-//           <o.0..10>Maximum Endpoint Packet Size (in bytes) <0-1024>
-//           <i>Specifies the physical packet size used for information exchange.
-//           <i>Maximum value is 1024.
-//           <o.11..12>Additional transactions per microframe
-//           <i>Additional transactions improve communication performance.
-//             <0=>None <1=>1 additional <2=>2 additional
-#define USBD_HID0_EP_INT_OUT_HS_WMAXPACKETSIZE    64
-
-//           <o.0..4>Endpoint polling Interval (in 125 us intervals)
-//           <i>Specifies the frequency of requests sent by USB Host for setting data.
-//             <1=>    1 <2=>    2 <3=>     4 <4=>     8
-//             <5=>   16 <6=>   32 <7=>    64 <8=>   128
-//             <9=>  256 <10=> 512 <11=> 1024 <12=> 2048
-//             <13=>4096 <14=>8192 <15=>16384 <16=>32768
-#define USBD_HID0_EP_INT_OUT_HS_BINTERVAL         1
-
-//         </h>
-//       </h>
-//     </h>
-//   </h>
-
-//   <h>Human Interface Device Class Settings
-//   <i>Parameters are used to create USB Descriptors, USB HID Report Descriptor
-//   <i>and for memory allocation in the USB component.
-//
-//     <s.126>HID Interface String
-#define USBD_HID0_STR_DESC                        L"LPC-Link2 CMSIS-DAP"
-
-//     <o.0..4>Number of Input Reports <1-32>
-//     <i>Configures max 'rid' value for USBD_HID0_GetReport and USBD_HID_GetReportTrigger
-#define USBD_HID0_IN_REPORT_NUM                   1
-
-//     <o.0..4>Number of Output Reports <1-32>
-//     <i>Configures max 'rid' value for USBD_HID0_SetReport
-#define USBD_HID0_OUT_REPORT_NUM                  1
-
-//     <o.0..15>Maximum Input Report Size (in bytes) <1-65535>
-//     <i>Allocates memory and configures 'len' value for USBD_HID0_GetReport
-//     <i>and USBD_HID_GetReportTrigger
-#define USBD_HID0_IN_REPORT_MAX_SZ                1024
-
-//     <o.0..15>Maximum Output Report Size (in bytes) <1-65535>
-//     <i>Allocates memory and configures 'len' value for USBD_HID0_SetReport
-//     <i>when rtype=HID_REPORT_OUTPUT.
-#define USBD_HID0_OUT_REPORT_MAX_SZ               1024
-
-//     <o.0..15>Maximum Feature Report Size (in bytes) <1-65535>
-//     <i>Allocates memory and configures 'len' value for USBD_HID0_SetReport
-//     <i>when rtype=HID_REPORT_FEATURE
-#define USBD_HID0_FEAT_REPORT_MAX_SZ              1
-
-//     <e.0>Use User Provided HID Report Descriptor
-//     <i>User needs to provide HID Report Descriptor in array
-//     <i>const uint8_t usbd_hid0_report_descriptor[]
-#define USBD_HID0_USER_REPORT_DESCRIPTOR          0
-
-//       <o>User Provided HID Report Descriptor Size (in bytes) <1-65535>
-#define USBD_HID0_USER_REPORT_DESCRIPTOR_SIZE     33
-
-//     </e>
-//   </h>
-
-//   <h>OS Resources Settings
-//   <i>These settings are used to optimize usage of OS resources.
-//     <o>Human Interface Device Class Thread Stack Size <64-65536>
-#define USBD_HID0_THREAD_STACK_SIZE               512
-
-//        Human Interface Device Class Thread Priority
-#define USBD_HID0_THREAD_PRIORITY                 osPriorityAboveNormal
-
-//   </h>
-// </h>

CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/USBD_User_HID_0.c

@@ -1,246 +0,0 @@
-/*------------------------------------------------------------------------------
- * MDK Middleware - Component ::USB:Device
- * Copyright (c) 2004-2017 ARM Germany GmbH. All rights reserved.
- *------------------------------------------------------------------------------
- * Name:    USBD_User_HID_0.c
- * Purpose: USB Device Human Interface Device class (HID) User module
- * Rev.:    V6.2.3
- *----------------------------------------------------------------------------*/
-/**
- * \addtogroup usbd_hidFunctions
- *
- * USBD_User_HID_0.c implements the application specific functionality of the
- * HID class and is used to receive and send data reports to the USB Host.
- *
- * The implementation must match the configuration file USBD_Config_HID_0.h.
- * The following values in USBD_Config_HID_0.h affect the user code:
- *
- *  - 'Endpoint polling Interval' specifies the frequency of requests
- *    initiated by USB Host for \ref USBD_HIDn_GetReport.
- *
- *  - 'Number of Output Reports' configures the values for \em rid of
- *    \ref USBD_HIDn_SetReport.
- *
- *  - 'Number of Input Reports' configures the values for \em rid of
- *    \ref USBD_HIDn_GetReport and \ref USBD_HID_GetReportTrigger.
- *
- *  - 'Maximum Input Report Size' specifies the maximum value for:
- *       - return of \ref USBD_HIDn_GetReport
- *       - len of \ref USBD_HID_GetReportTrigger.
- *
- *  - 'Maximum Output Report Size' specifies the maximum value for \em len
- *    in \ref USBD_HIDn_SetReport for rtype=HID_REPORT_OUTPUT
- *
- *  - 'Maximum Feature Report Size' specifies the maximum value for \em len
- *    in \ref USBD_HIDn_SetReport for rtype=HID_REPORT_FEATURE
- *
- */
-
-
-//! [code_USBD_User_HID]
-
-#include <stdint.h>
-#include <string.h>
-#include "cmsis_os2.h"
-#define   osObjectsExternal
-#include "osObjects.h"
-#include "rl_usb.h"
-#include "RTE\USB\USBD_Config_HID_0.h"
-#include "DAP_config.h"
-#include "DAP.h"
-
-
-#if (USBD_HID0_OUT_REPORT_MAX_SZ != DAP_PACKET_SIZE)
-#error "USB HID0 Output Report Size must match DAP Packet Size"
-#endif
-#if (USBD_HID0_IN_REPORT_MAX_SZ != DAP_PACKET_SIZE)
-#error "USB HID Input Report Size must match DAP Packet Size"
-#endif
-
-static volatile uint16_t USB_RequestIndexI;     // Request  Index In
-static volatile uint16_t USB_RequestIndexO;     // Request  Index Out
-static volatile uint16_t USB_RequestCountI;     // Request  Count In
-static volatile uint16_t USB_RequestCountO;     // Request  Count Out
-
-static volatile uint16_t USB_ResponseIndexI;    // Response Index In
-static volatile uint16_t USB_ResponseIndexO;    // Response Index Out
-static volatile uint16_t USB_ResponseCountI;    // Response Count In
-static volatile uint16_t USB_ResponseCountO;    // Response Count Out
-static volatile uint8_t  USB_ResponseIdle;      // Response Idle  Flag
-
-static uint8_t  USB_Request [DAP_PACKET_COUNT][DAP_PACKET_SIZE];  // Request  Buffer
-static uint8_t  USB_Response[DAP_PACKET_COUNT][DAP_PACKET_SIZE];  // Response Buffer
-
-
-// Called during USBD_Initialize to initialize the USB HID class instance.
-void USBD_HID0_Initialize (void) {
-  // Initialize variables
-  USB_RequestIndexI  = 0U;
-  USB_RequestIndexO  = 0U;
-  USB_RequestCountI  = 0U;
-  USB_RequestCountO  = 0U;
-  USB_ResponseIndexI = 0U;
-  USB_ResponseIndexO = 0U;
-  USB_ResponseCountI = 0U;
-  USB_ResponseCountO = 0U;
-  USB_ResponseIdle   = 1U;
-}
-
-
-// Called during USBD_Uninitialize to de-initialize the USB HID class instance.
-void USBD_HID0_Uninitialize (void) {
-}
-
-
-// \brief Prepare HID Report data to send.
-// \param[in]   rtype   report type:
-//                - HID_REPORT_INPUT           = input report requested
-//                - HID_REPORT_FEATURE         = feature report requested
-// \param[in]   req     request type:
-//                - USBD_HID_REQ_EP_CTRL       = control endpoint request
-//                - USBD_HID_REQ_PERIOD_UPDATE = idle period expiration request
-//                - USBD_HID_REQ_EP_INT        = previously sent report on interrupt endpoint request
-// \param[in]   rid     report ID (0 if only one report exists).
-// \param[out]  buf     buffer containing report data to send.
-// \return              number of report data bytes prepared to send or invalid report requested.
-//              - value >= 0: number of report data bytes prepared to send
-//              - value = -1: invalid report requested
-int32_t USBD_HID0_GetReport (uint8_t rtype, uint8_t req, uint8_t rid, uint8_t *buf) {
-  (void)rid;
-
-  switch (rtype) {
-    case HID_REPORT_INPUT:
-      switch (req) {
-        case USBD_HID_REQ_EP_CTRL:        // Explicit USB Host request via Control OUT Endpoint
-        case USBD_HID_REQ_PERIOD_UPDATE:  // Periodic USB Host request via Interrupt OUT Endpoint
-          break;
-        case USBD_HID_REQ_EP_INT:         // Called after USBD_HID_GetReportTrigger to signal data obtained.
-          if (USB_ResponseCountI != USB_ResponseCountO) {
-            // Load data from response buffer to be sent back
-            memcpy(buf, USB_Response[USB_ResponseIndexO], DAP_PACKET_SIZE);
-            USB_ResponseIndexO++;
-            if (USB_ResponseIndexO == DAP_PACKET_COUNT) {
-              USB_ResponseIndexO = 0U;
-            }
-            USB_ResponseCountO++;
-            return ((int32_t)DAP_PACKET_SIZE);
-          } else {
-            USB_ResponseIdle = 1U;
-          }
-          break;
-      }
-      break;
-    case HID_REPORT_FEATURE:
-      break;
-  }
-  return (0);
-}
-
-
-// \brief Process received HID Report data.
-// \param[in]   rtype   report type:
-//                - HID_REPORT_OUTPUT    = output report received
-//                - HID_REPORT_FEATURE   = feature report received
-// \param[in]   req     request type:
-//                - USBD_HID_REQ_EP_CTRL = report received on control endpoint
-//                - USBD_HID_REQ_EP_INT  = report received on interrupt endpoint
-// \param[in]   rid     report ID (0 if only one report exists).
-// \param[in]   buf     buffer that receives report data.
-// \param[in]   len     length of received report data.
-// \return      true    received report data processed.
-// \return      false   received report data not processed or request not supported.
-bool USBD_HID0_SetReport (uint8_t rtype, uint8_t req, uint8_t rid, const uint8_t *buf, int32_t len) {
-  (void)req;
-  (void)rid;
-
-  switch (rtype) {
-    case HID_REPORT_OUTPUT:
-      if (len == 0) {
-        break;
-      }
-      if (buf[0] == ID_DAP_TransferAbort) {
-        DAP_TransferAbort = 1U;
-        break;
-      }
-      if ((uint16_t)(USB_RequestCountI - USB_RequestCountO) == DAP_PACKET_COUNT) {
-        osThreadFlagsSet(DAP_ThreadId, 0x80U);
-        break;  // Discard packet when buffer is full
-      }
-      // Store received data into request buffer
-      memcpy(USB_Request[USB_RequestIndexI], buf, (uint32_t)len);
-      USB_RequestIndexI++;
-      if (USB_RequestIndexI == DAP_PACKET_COUNT) {
-        USB_RequestIndexI = 0U;
-      }
-      USB_RequestCountI++;
-      osThreadFlagsSet(DAP_ThreadId, 0x01U);
-      break;
-    case HID_REPORT_FEATURE:
-      break;
-  }
-  return true;
-}
-
-
-// DAP Thread.
-__NO_RETURN void DAP_Thread (void *argument) {
-  uint32_t flags;
-  uint32_t n;
-  (void)   argument;
-
-  for (;;) {
-    osThreadFlagsWait(0x81U, osFlagsWaitAny, osWaitForever);
-
-    // Process pending requests
-    while (USB_RequestCountI != USB_RequestCountO) {
-
-      // Handle Queue Commands
-      n = USB_RequestIndexO;
-      while (USB_Request[n][0] == ID_DAP_QueueCommands) {
-        USB_Request[n][0] = ID_DAP_ExecuteCommands;
-        n++;
-        if (n == DAP_PACKET_COUNT) {
-          n = 0U;
-        }
-        if (n == USB_RequestIndexI) {
-          flags = osThreadFlagsWait(0x81U, osFlagsWaitAny, osWaitForever);
-          if (flags & 0x80U) {
-            break;
-          }
-        }
-      }
-
-      // Execute DAP Command (process request and prepare response)
-      DAP_ExecuteCommand(USB_Request[USB_RequestIndexO], USB_Response[USB_ResponseIndexI]);
-
-      // Update Request Index and Count
-      USB_RequestIndexO++;
-      if (USB_RequestIndexO == DAP_PACKET_COUNT) {
-        USB_RequestIndexO = 0U;
-      }
-      USB_RequestCountO++;
-
-      // Update Response Index and Count
-      USB_ResponseIndexI++;
-      if (USB_ResponseIndexI == DAP_PACKET_COUNT) {
-        USB_ResponseIndexI = 0U;
-      }
-      USB_ResponseCountI++;
-
-      if (USB_ResponseIdle) {
-        if (USB_ResponseCountI != USB_ResponseCountO) {
-          // Load data from response buffer to be sent back
-          n = USB_ResponseIndexO++;
-          if (USB_ResponseIndexO == DAP_PACKET_COUNT) {
-            USB_ResponseIndexO = 0U;
-          }
-          USB_ResponseCountO++;
-          USB_ResponseIdle = 0U;
-          USBD_HID_GetReportTrigger(0U, 0U, USB_Response[n], DAP_PACKET_SIZE);
-        }
-      }
-    }
-  }
-}
-
-//! [code_USBD_User_HID]

CMSIS/DAP/Firmware/Examples/LPC-Link2/V2/Abstract.txt

@@ -1,8 +0,0 @@
-CMSIS-DAP V2 USB WinUSB Firmware for NXP LPC-Link2 debug probe.
-
-Following targets are available:
- - LPC-Link2: stand-alone debug probe
- - LPC-Link2 on-board: on-board debug probe (LPC55S69-EVK, MIMXRT1064-EVK, ...)
-
-CMSIS-DAP with default V2 configuration uses WinUSB interface to host PC and is therefore faster. 
-Optionally support for streaming SWO trace is provided via an additional USB endpoint.

CMSIS/DAP/Firmware/Examples/LPC-Link2/V2/DebugConfig/LPC-Link2_LPC4370_Cortex-M4.dbgconf

@@ -1,43 +0,0 @@
-// <<< Use Configuration Wizard in Context Menu >>>
-
-// <h> Debug Setup
-
-// <o> Release M0 On Connect
-//   <0=> No
-//   <1=> Yes
-// <i> Debugger releases the M0 Application processor from reset when connecting to it.
-ReleaseM0OnConnect = 1;
-
-// <o> Release M0 Sub-System On Connect
-//   <0=> No
-//   <1=> Yes
-// <i> Debugger releases the M0 Sub-System from reset when connecting to it (LPC437x only).
-ReleaseM0SubOnConnect = 1;
-
-// <o> Vector Reset
-//   <0=> Processor Only
-//   <1=> Processor and Peripherals
-// <i> Select if to additionally reset peripherals (LCD, USB0, USB1, DMA, SDIO, ETHERNET) after a Vector Reset
-VecResetWithPeriph = 1;
-
-// </h>
-
-// <h> TPIU Pin Routing (TRACECLK fixed on PF_4)
-// <i> Configure the TPIU pin routing as used on your target platform.
-// <o.1> TRACEDATA0
-//   <0=> Pin PF_5
-//   <1=> Pin P7_4
-// <o.2> TRACEDATA1
-//   <0=> Pin PF_6
-//   <1=> Pin P7_5
-// <o.3> TRACEDATA2
-//   <0=> Pin PF_7
-//   <1=> Pin P7_6
-// <o.4> TRACEDATA3
-//   <0=> Pin PF_8
-//   <1=> Pin P7_7
-RoutingTPIU = 0x00000000;
-
-// </h>
-
-// <<< end of configuration section >>>

CMSIS/DAP/Firmware/Examples/LPC-Link2/V2/RTE/Device/LPC4370_Cortex-M4/startup_LPC43xx.s

@@ -1,333 +0,0 @@
-;/**************************************************************************//**
-; * @file     LPC43xx.s
-; * @brief    CMSIS Cortex-M4 Core Device Startup File for
-; *           NXP LPC43xxDevice Series
-; * @version  V1.00
-; * @date     03. September 2013
-; *
-; * @note
-; * Copyright (C) 2009-2013 ARM Limited. All rights reserved.
-; *
-; * @par
-; * ARM Limited (ARM) is supplying this software for use with Cortex-M
-; * processor based microcontrollers.  This file can be freely distributed
-; * within development tools that are supporting such ARM based processors.
-; *
-; * @par
-; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-; *
-; * <<< Use Configuration Wizard in Context Menu >>>   
-; ******************************************************************************/
-
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-; Vector Table Mapped to Address 0 at Reset
-
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-
-Sign_Value      EQU     0x5A5A5A5A
-
-__Vectors       DCD     __initial_sp                            ;  0  Top of Stack
-                DCD     Reset_Handler                           ;  1  Reset Handler
-                DCD     NMI_Handler                             ;  2  NMI Handler
-                DCD     HardFault_Handler                       ;  3  Hard Fault Handler
-                DCD     MemManage_Handler                       ;  4  MPU Fault Handler
-                DCD     BusFault_Handler                        ;  5  Bus Fault Handler
-                DCD     UsageFault_Handler                      ;  6  Usage Fault Handler
-                DCD     Sign_Value                              ;  7  Reserved
-                DCD     0                                       ;  8  Reserved
-                DCD     0                                       ;  9  Reserved
-                DCD     0                                       ; 10  Reserved
-                DCD     SVC_Handler                             ; 11  SVCall Handler
-                DCD     DebugMon_Handler                        ; 12  Debug Monitor Handler
-                DCD     0                                       ; 13  Reserved
-                DCD     PendSV_Handler                          ; 14  PendSV Handler
-                DCD     SysTick_Handler                         ; 15  SysTick Handler
-
-                ; External LPC43xx/M4 Interrupts
-                DCD     DAC_IRQHandler                          ;  0  DAC interrupt
-                DCD     M0APP_IRQHandler                        ;  1  Cortex-M0APP; Latched TXEV; for M4-M0APP communication
-                DCD     DMA_IRQHandler                          ;  2  DMA interrupt
-                DCD     0                                       ;  3  Reserved
-                DCD     FLASHEEPROM_IRQHandler                  ;  4  flash bank A, flash bank B, EEPROM ORed interrupt
-                DCD     ETHERNET_IRQHandler                     ;  5  Ethernet interrupt
-                DCD     SDIO_IRQHandler                         ;  6  SD/MMC interrupt
-                DCD     LCD_IRQHandler                          ;  7  LCD interrupt
-                DCD     USB0_IRQHandler                         ;  8  OTG interrupt
-                DCD     USB1_IRQHandler                         ;  9  USB1 interrupt
-                DCD     SCT_IRQHandler                          ; 10  SCT combined interrupt
-                DCD     RITIMER_IRQHandler                      ; 11  RI Timer interrupt
-                DCD     TIMER0_IRQHandler                       ; 12  Timer 0 interrupt
-                DCD     TIMER1_IRQHandler                       ; 13  Timer 1 interrupt
-                DCD     TIMER2_IRQHandler                       ; 14  Timer 2 interrupt
-                DCD     TIMER3_IRQHandler                       ; 15  Timer 3 interrupt
-                DCD     MCPWM_IRQHandler                        ; 16  Motor control PWM interrupt
-                DCD     ADC0_IRQHandler                         ; 17  ADC0 interrupt
-                DCD     I2C0_IRQHandler                         ; 18  I2C0 interrupt
-                DCD     I2C1_IRQHandler                         ; 19  I2C1 interrupt
-                DCD     SPI_IRQHandler                          ; 20  SPI interrupt
-                DCD     ADC1_IRQHandler                         ; 21  ADC1 interrupt
-                DCD     SSP0_IRQHandler                         ; 22  SSP0 interrupt
-                DCD     SSP1_IRQHandler                         ; 23  SSP1 interrupt
-                DCD     USART0_IRQHandler                       ; 24  USART0 interrupt
-                DCD     UART1_IRQHandler                        ; 25  Combined UART1, Modem interrupt
-                DCD     USART2_IRQHandler                       ; 26  USART2 interrupt
-                DCD     USART3_IRQHandler                       ; 27  Combined USART3, IrDA interrupt
-                DCD     I2S0_IRQHandler                         ; 28  I2S0 interrupt
-                DCD     I2S1_IRQHandler                         ; 29  I2S1 interrupt
-                DCD     SPIFI_IRQHandler                        ; 30  SPISI interrupt
-                DCD     SGPIO_IRQHandler                        ; 31  SGPIO interrupt
-                DCD     PIN_INT0_IRQHandler                     ; 32  GPIO pin interrupt 0
-                DCD     PIN_INT1_IRQHandler                     ; 33  GPIO pin interrupt 1
-                DCD     PIN_INT2_IRQHandler                     ; 34  GPIO pin interrupt 2
-                DCD     PIN_INT3_IRQHandler                     ; 35  GPIO pin interrupt 3
-                DCD     PIN_INT4_IRQHandler                     ; 36  GPIO pin interrupt 4
-                DCD     PIN_INT5_IRQHandler                     ; 37  GPIO pin interrupt 5
-                DCD     PIN_INT6_IRQHandler                     ; 38  GPIO pin interrupt 6
-                DCD     PIN_INT7_IRQHandler                     ; 39  GPIO pin interrupt 7
-                DCD     GINT0_IRQHandler                        ; 40  GPIO global interrupt 0
-                DCD     GINT1_IRQHandler                        ; 41  GPIO global interrupt 1
-                DCD     EVENTROUTER_IRQHandler                  ; 42  Event router interrupt
-                DCD     C_CAN1_IRQHandler                       ; 43  C_CAN1 interrupt
-                DCD     0                                       ; 44  Reserved
-                DCD     ADCHS_IRQHandler                        ; 45  ADCHS combined interrupt
-                DCD     ATIMER_IRQHandler                       ; 46  Alarm timer interrupt
-                DCD     RTC_IRQHandler                          ; 47  RTC interrupt
-                DCD     0                                       ; 48  Reserved
-                DCD     WWDT_IRQHandler                         ; 49  WWDT interrupt
-                DCD     M0SUB_IRQHandler                        ; 50  TXEV instruction from the M0 subsystem core interrupt
-                DCD     C_CAN0_IRQHandler                       ; 51  C_CAN0 interrupt
-                DCD     QEI_IRQHandler                          ; 52  QEI interrupt
-
-
-;CRP address at offset 0x2FC relative to the BOOT Bank address
-                IF      :LNOT::DEF:NO_CRP
-                SPACE   (0x2FC - (. - __Vectors))
-;                EXPORT  CRP_Key
-CRP_Key         DCD     0xFFFFFFFF
-;                       0xFFFFFFFF => CRP Disabled
-;                       0x12345678 => CRP Level 1
-;                       0x87654321 => CRP Level 2
-;                       0x43218765 => CRP Level 3 (ARE YOU SURE?)
-;                       0x4E697370 => NO ISP      (ARE YOU SURE?)
-                ENDIF
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset Handler
-
-Reset_Handler   PROC
-                EXPORT  Reset_Handler           [WEAK]
-                IMPORT  SystemInit
-                IMPORT  __main
-                LDR     R0, =SystemInit
-                BLX     R0
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                         [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler                   [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler                   [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler                    [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler                  [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                         [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler                    [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler                      [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler                     [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-                EXPORT  DAC_IRQHandler                      [WEAK]
-                EXPORT  M0APP_IRQHandler                    [WEAK]
-                EXPORT  DMA_IRQHandler                      [WEAK]
-                EXPORT  FLASHEEPROM_IRQHandler              [WEAK]
-                EXPORT  ETHERNET_IRQHandler                 [WEAK]
-                EXPORT  SDIO_IRQHandler                     [WEAK]
-                EXPORT  LCD_IRQHandler                      [WEAK]
-                EXPORT  USB0_IRQHandler                     [WEAK]
-                EXPORT  USB1_IRQHandler                     [WEAK]
-                EXPORT  SCT_IRQHandler                      [WEAK]
-                EXPORT  RITIMER_IRQHandler                  [WEAK]
-                EXPORT  TIMER0_IRQHandler                   [WEAK]
-                EXPORT  TIMER1_IRQHandler                   [WEAK]
-                EXPORT  TIMER2_IRQHandler                   [WEAK]
-                EXPORT  TIMER3_IRQHandler                   [WEAK]
-                EXPORT  MCPWM_IRQHandler                    [WEAK]
-                EXPORT  ADC0_IRQHandler                     [WEAK]
-                EXPORT  I2C0_IRQHandler                     [WEAK]
-                EXPORT  I2C1_IRQHandler                     [WEAK]
-                EXPORT  SPI_IRQHandler                      [WEAK]
-                EXPORT  ADC1_IRQHandler                     [WEAK]
-                EXPORT  SSP0_IRQHandler                     [WEAK]
-                EXPORT  SSP1_IRQHandler                     [WEAK]
-                EXPORT  USART0_IRQHandler                   [WEAK]
-                EXPORT  UART1_IRQHandler                    [WEAK]
-                EXPORT  USART2_IRQHandler                   [WEAK]
-                EXPORT  USART3_IRQHandler                   [WEAK]
-                EXPORT  I2S0_IRQHandler                     [WEAK]
-                EXPORT  I2S1_IRQHandler                     [WEAK]
-                EXPORT  SPIFI_IRQHandler                    [WEAK]
-                EXPORT  SGPIO_IRQHandler                    [WEAK]
-                EXPORT  PIN_INT0_IRQHandler                 [WEAK]
-                EXPORT  PIN_INT1_IRQHandler                 [WEAK]
-                EXPORT  PIN_INT2_IRQHandler                 [WEAK]
-                EXPORT  PIN_INT3_IRQHandler                 [WEAK]
-                EXPORT  PIN_INT4_IRQHandler                 [WEAK]
-                EXPORT  PIN_INT5_IRQHandler                 [WEAK]
-                EXPORT  PIN_INT6_IRQHandler                 [WEAK]
-                EXPORT  PIN_INT7_IRQHandler                 [WEAK]
-                EXPORT  GINT0_IRQHandler                    [WEAK]
-                EXPORT  GINT1_IRQHandler                    [WEAK]
-                EXPORT  EVENTROUTER_IRQHandler              [WEAK]
-                EXPORT  C_CAN1_IRQHandler                   [WEAK]
-                EXPORT  ADCHS_IRQHandler                    [WEAK]
-                EXPORT  ATIMER_IRQHandler                   [WEAK]
-                EXPORT  RTC_IRQHandler                      [WEAK]
-                EXPORT  WWDT_IRQHandler                     [WEAK]
-                EXPORT  M0SUB_IRQHandler                    [WEAK]
-                EXPORT  C_CAN0_IRQHandler                   [WEAK]
-                EXPORT  QEI_IRQHandler                      [WEAK]
-
-DAC_IRQHandler
-M0APP_IRQHandler
-DMA_IRQHandler
-FLASHEEPROM_IRQHandler
-ETHERNET_IRQHandler
-SDIO_IRQHandler
-LCD_IRQHandler
-USB0_IRQHandler
-USB1_IRQHandler
-SCT_IRQHandler
-RITIMER_IRQHandler
-TIMER0_IRQHandler
-TIMER1_IRQHandler
-TIMER2_IRQHandler
-TIMER3_IRQHandler
-MCPWM_IRQHandler
-ADC0_IRQHandler
-I2C0_IRQHandler
-I2C1_IRQHandler
-SPI_IRQHandler
-ADC1_IRQHandler
-SSP0_IRQHandler
-SSP1_IRQHandler
-USART0_IRQHandler
-UART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-I2S0_IRQHandler
-I2S1_IRQHandler
-SPIFI_IRQHandler
-SGPIO_IRQHandler
-PIN_INT0_IRQHandler
-PIN_INT1_IRQHandler
-PIN_INT2_IRQHandler
-PIN_INT3_IRQHandler
-PIN_INT4_IRQHandler
-PIN_INT5_IRQHandler
-PIN_INT6_IRQHandler
-PIN_INT7_IRQHandler
-GINT0_IRQHandler
-GINT1_IRQHandler
-EVENTROUTER_IRQHandler
-C_CAN1_IRQHandler
-ADCHS_IRQHandler
-ATIMER_IRQHandler
-RTC_IRQHandler
-WWDT_IRQHandler
-M0SUB_IRQHandler
-C_CAN0_IRQHandler
-QEI_IRQHandler
-
-                B       .
-                ENDP
-
-                ALIGN
-
-; User Initial Stack & Heap
-
-                IF      :DEF:__MICROLIB
-
-                EXPORT  __initial_sp
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-
-                ELSE
-
-                IMPORT  __use_two_region_memory
-                EXPORT  __user_initial_stackheap
-__user_initial_stackheap
-
-                LDR     R0, =  Heap_Mem
-                LDR     R1, =(Stack_Mem + Stack_Size)
-                LDR     R2, = (Heap_Mem +  Heap_Size)
-                LDR     R3, = Stack_Mem
-                BX      LR
-
-                ALIGN
-
-                ENDIF
-
-
-                END

CMSIS/DAP/Firmware/Examples/LPC-Link2/V2/RTE/Device/LPC4370_Cortex-M4/system_LPC43xx.c

@@ -1,938 +0,0 @@
-/* -----------------------------------------------------------------------------
- * Copyright (c) 2013 - 2017 ARM Ltd.
- *
- * This software is provided 'as-is', without any express or implied warranty.
- * In no event will the authors be held liable for any damages arising from
- * the use of this software. Permission is granted to anyone to use this
- * software for any purpose, including commercial applications, and to alter
- * it and redistribute it freely, subject to the following restrictions:
- *
- * 1. The origin of this software must not be misrepresented; you must not
- *    claim that you wrote the original software. If you use this software in
- *    a product, an acknowledgment in the product documentation would be
- *    appreciated but is not required.
- *
- * 2. Altered source versions must be plainly marked as such, and must not be
- *    misrepresented as being the original software.
- *
- * 3. This notice may not be removed or altered from any source distribution.
- *
- * $Date:        10. September 2018
- * $Revision:    V1.0.3
- *
- * Project:      NXP LPC43xx System initialization
- * -------------------------------------------------------------------------- */
-
-#include "LPC43xx.h"
-
-/*----------------------------------------------------------------------------
-  This file configures the clocks as follows:
- -----------------------------------------------------------------------------
- Clock Unit  |  Output clock  |  Source clock  |          Note
- -----------------------------------------------------------------------------
-   PLL0USB   |    480 MHz     |      XTAL      | External crystal @ 12 MHz
- -----------------------------------------------------------------------------
-    PLL1     |    180 MHz     |      XTAL      | External crystal @ 12 MHz
- -----------------------------------------------------------------------------
-    CPU      |    180 MHz     |      PLL1      | CPU Clock ==  BASE_M4_CLK
- -----------------------------------------------------------------------------
-   IDIV A    |     60 MHz     |      PLL1      | To the USB1 peripheral
- -----------------------------------------------------------------------------
-   IDIV B    |     25 MHz     |   ENET_TX_CLK  | ENET_TX_CLK @ 50MHz
- -----------------------------------------------------------------------------
-   IDIV C    |     12 MHz     |      IRC       | Internal oscillator @ 12 MHz
- -----------------------------------------------------------------------------
-   IDIV D    |     12 MHz     |      IRC       | Internal oscillator @ 12 MHz
- -----------------------------------------------------------------------------
-   IDIV E    |    5.3 MHz     |      PLL1      | To the LCD controller
- -----------------------------------------------------------------------------*/
-
-
-/*----------------------------------------------------------------------------
-  Clock source selection definitions (do not change)
- *----------------------------------------------------------------------------*/
-#define CLK_SRC_32KHZ       0x00
-#define CLK_SRC_IRC         0x01
-#define CLK_SRC_ENET_RX     0x02
-#define CLK_SRC_ENET_TX     0x03
-#define CLK_SRC_GP_CLKIN    0x04
-#define CLK_SRC_XTAL        0x06
-#define CLK_SRC_PLL0U       0x07
-#define CLK_SRC_PLL0A       0x08
-#define CLK_SRC_PLL1        0x09
-#define CLK_SRC_IDIVA       0x0C
-#define CLK_SRC_IDIVB       0x0D
-#define CLK_SRC_IDIVC       0x0E
-#define CLK_SRC_IDIVD       0x0F
-#define CLK_SRC_IDIVE       0x10
-
-
-/*----------------------------------------------------------------------------
-  Define external input frequency values
- *----------------------------------------------------------------------------*/
-#define CLK_32KHZ            32768UL    /* 32 kHz oscillator frequency        */
-#define CLK_IRC           12000000UL    /* Internal oscillator frequency      */
-#define CLK_ENET_RX       50000000UL    /* Ethernet Rx frequency              */
-#define CLK_ENET_TX       50000000UL    /* Ethernet Tx frequency              */
-#define CLK_GP_CLKIN      12000000UL    /* General purpose clock input freq.  */
-#define CLK_XTAL          12000000UL    /* Crystal oscilator frequency        */
-
-
-/*----------------------------------------------------------------------------
-  Define clock sources
- *----------------------------------------------------------------------------*/
-#define PLL1_CLK_SEL      CLK_SRC_XTAL    /* PLL1 input clock: XTAL           */
-#define PLL0USB_CLK_SEL   CLK_SRC_XTAL    /* PLL0USB input clock: XTAL        */
-#define IDIVA_CLK_SEL     CLK_SRC_PLL1    /* IDIVA input clock: PLL1          */
-#define IDIVB_CLK_SEL     CLK_SRC_ENET_TX /* IDIVB input clock: ENET TX       */
-#define IDIVC_CLK_SEL     CLK_SRC_IRC     /* IDIVC input clock: IRC           */
-#define IDIVD_CLK_SEL     CLK_SRC_IRC     /* IDIVD input clock: IRC           */
-#define IDIVE_CLK_SEL     CLK_SRC_PLL1    /* IDIVD input clock: PLL1          */
-
-
-/*----------------------------------------------------------------------------
-  Configure integer divider values
- *----------------------------------------------------------------------------*/
-#define IDIVA_IDIV        2             /* Divide input clock by 3            */
-#define IDIVB_IDIV        1             /* Divide input clock by 2            */
-#define IDIVC_IDIV        0             /* Divide input clock by 1            */
-#define IDIVD_IDIV        0             /* Divide input clock by 1            */
-#define IDIVE_IDIV       33             /* Divide input clock by 34           */
-
-
-/*----------------------------------------------------------------------------
-  Define CPU clock input
- *----------------------------------------------------------------------------*/
-#define CPU_CLK_SEL       CLK_SRC_PLL1  /* Default CPU clock source is PLL1   */
-
-
-/*----------------------------------------------------------------------------
-  Configure external memory controller options
- *----------------------------------------------------------------------------*/
-#define USE_EXT_STAT_MEM_CS0 1          /* Use ext. static  memory with CS0   */
-#define USE_EXT_DYN_MEM_CS0  1          /* Use ext. dynamic memory with CS0   */
-
-
-/*----------------------------------------------------------------------------
- * Configure PLL1
- *----------------------------------------------------------------------------
- * Integer mode:
- *    - PLL1_DIRECT = 0 (Post divider enabled)
- *    - PLL1_FBSEL  = 1 (Feedback divider runs from PLL output)
- *    - Output frequency:
- *                        FCLKOUT = (FCLKIN / N) * M
- *                        FCCO    = FCLKOUT * 2 * P
- *
- * Non-integer:
- *    - PLL1_DIRECT = 0 (Post divider enabled)
- *    - PLL1_FBSEL  = 0 (Feedback divider runs from CCO clock)
- *    - Output frequency:
- *                        FCLKOUT = (FCLKIN / N) * M / (2 * P)
- *                        FCCO    = FCLKOUT * 2 * P
- *
- * Direct mode:
- *    - PLL1_DIRECT = 1         (Post divider disabled)
- *    - PLL1_FBSEL  = dont care (Feedback divider runs from CCO clock)
- *    - Output frequency:
- *                        FCLKOUT = (FCLKIN / N) * M
- *                        FCCO    = FCLKOUT
- *
- *----------------------------------------------------------------------------
- * PLL1 requirements:
- * | Frequency |  Minimum  |  Maximum  |               Note                   |
- * |  FCLKIN   |    1MHz   |   25MHz   |   Clock source is external crystal   |
- * |  FCLKIN   |    1MHz   |   50MHz   |                                      |
- * |   FCCO    |  156MHz   |  320MHz   |                                      |
- * |  FCLKOUT  | 9.75MHz   |  320MHz   |                                      |
- *----------------------------------------------------------------------------
- * Configuration examples:
- * | Fclkout |  Fcco  |  N  |  M  |  P  | DIRECT | FBSEL | BYPASS |
- * |  36MHz | 288MHz |  1  |  24 |  4  |   0    |   0   |    0   |
- * |  72MHz | 288MHz |  1  |  24 |  2  |   0    |   0   |    0   |
- * | 100MHz | 200MHz |  3  |  50 |  1  |   0    |   0   |    0   |
- * | 120MHz | 240MHz |  1  |  20 |  1  |   0    |   0   |    0   |
- * | 160MHz | 160MHz |  3  |  40 |  x  |   1    |   0   |    0   |
- * | 180MHz | 180MHz |  1  |  15 |  x  |   1    |   0   |    0   |
- * | 204MHz | 204MHz |  1  |  17 |  x  |   1    |   0   |    0   |
- *----------------------------------------------------------------------------
- * Relations beetwen PLL dividers and definitions:
- * N = PLL1_NSEL + 1,     M = PLL1_MSEL + 1,     P = 2 ^ PLL1_PSEL
- *----------------------------------------------------------------------------*/
-
-/* PLL1 output clock: 180MHz, Fcco: 180MHz, N = 1, M = 15, P = x              */
-#define PLL1_NSEL   0           /* Range [0 -   3]: Pre-divider ratio N       */
-#define PLL1_MSEL  14           /* Range [0 - 255]: Feedback-divider ratio M  */
-#define PLL1_PSEL   0           /* Range [0 -   3]: Post-divider ratio P      */
-
-#define PLL1_BYPASS 0           /* 0: Use PLL, 1: PLL is bypassed             */
-#define PLL1_DIRECT 1           /* 0: Use PSEL, 1: Don't use PSEL             */
-#define PLL1_FBSEL  0           /* 0: FCCO is used as PLL feedback            */
-                                /* 1: FCLKOUT is used as PLL feedback         */
-
-/*----------------------------------------------------------------------------
- * Configure Flash Accelerator
- *----------------------------------------------------------------------------
- * Flash acces time:
- * |  CPU clock   | FLASHTIM |
- * | up to  21MHz |    0     |
- * | up to  43MHz |    1     |
- * | up to  64MHz |    2     |
- * | up to  86MHz |    3     |
- * | up to 107MHz |    4     |
- * | up to 129MHz |    5     |
- * | up to 150MHz |    6     |
- * | up to 172MHz |    7     |
- * | up to 193MHz |    8     |
- * | up to 204MHz |    9     |
- *----------------------------------------------------------------------------*/
-#define FLASHCFG_FLASHTIM   9
-
-
-/*----------------------------------------------------------------------------
- * Configure PLL0USB
- *----------------------------------------------------------------------------
- *
- *   Normal operating mode without post-divider and without pre-divider
- *    - PLL0USB_DIRECTI = 1
- *    - PLL0USB_DIRECTO = 1
- *    - PLL0USB_BYPASS  = 0
- *    - Output frequency:
- *                        FOUT = FIN * 2 * M
- *                        FCCO = FOUT
- *
- *   Normal operating mode with post-divider and without pre-divider
- *    - PLL0USB_DIRECTI = 1
- *    - PLL0USB_DIRECTO = 0
- *    - PLL0USB_BYPASS  = 0
- *    - Output frequency:
- *                        FOUT = FIN * (M / P)
- *                        FCCO = FOUT * 2 * P
- *
- *   Normal operating mode without post-divider and with pre-divider
- *    - PLL0USB_DIRECTI = 0
- *    - PLL0USB_DIRECTO = 1
- *    - PLL0USB_BYPASS  = 0
- *    - Output frequency:
- *                        FOUT = FIN * 2 * M / N
- *                        FCCO = FOUT
- *
- *   Normal operating mode with post-divider and with pre-divider
- *    - PLL0USB_DIRECTI = 0
- *    - PLL0USB_DIRECTO = 0
- *    - PLL0USB_BYPASS  = 0
- *    - Output frequency:
- *                        FOUT = FIN * M / (P * N)
- *                        FCCO = FOUT * 2 * P
- *----------------------------------------------------------------------------
- * PLL0 requirements:
- * | Frequency |  Minimum  |  Maximum  |               Note                   |
- * |  FCLKIN   |   14kHz   |   25MHz   |   Clock source is external crystal   |
- * |  FCLKIN   |   14kHz   |  150MHz   |                                      |
- * |   FCCO    |  275MHz   |  550MHz   |                                      |
- * |  FCLKOUT  |  4.3MHz   |  550MHz   |                                      |
- *----------------------------------------------------------------------------
- * Configuration examples:
- * | Fclkout |  Fcco  |  N  |  M  |  P  | DIRECTI | DIRECTO | BYPASS |
- * | 120MHz | 480MHz |  x  |  20 |  2  |    1    |    0    |    0   |
- * | 480MHz | 480MHz |  1  |  20 |  1  |    1    |    1    |    0   |
- *----------------------------------------------------------------------------*/
-
-/* PLL0USB output clock: 480MHz, Fcco: 480MHz, N = 1, M = 20, P = 1           */
-#define PLL0USB_N       1       /* Range [1 -  256]: Pre-divider              */
-#define PLL0USB_M      20       /* Range [1 - 2^15]: Feedback-divider         */
-#define PLL0USB_P       1       /* Range [1 -   32]: Post-divider             */
-
-#define PLL0USB_DIRECTI 1       /* 0: Use N_DIV, 1: Don't use N_DIV           */
-#define PLL0USB_DIRECTO 1       /* 0: Use P_DIV, 1: Don't use P_DIV           */
-#define PLL0USB_BYPASS  0       /* 0: Use PLL, 1: PLL is bypassed             */
-
-
-/*----------------------------------------------------------------------------
-  End of configuration
- *----------------------------------------------------------------------------*/
-
-/* PLL0 Setting Check */
-#if (PLL0USB_BYPASS == 0)
- #if (PLL0USB_CLK_SEL == CLK_SRC_XTAL)
-  #define PLL0USB_CLKIN CLK_XTAL
- #else
-  #define PLL0USB_CLKIN CLK_IRC
- #endif
-
- #if   ((PLL0USB_DIRECTI == 1) && (PLL0USB_DIRECTO == 1)) /* Mode 1a          */
-  #define PLL0USB_FOUT (PLL0USB_CLKIN * 2 * PLL0USB_M)
-  #define PLL0USB_FCCO (PLL0USB_FOUT)
- #elif ((PLL0USB_DIRECTI == 1) && (PLL0USB_DIRECTO == 0)) /* Mode 1b          */
-  #define PLL0USB_FOUT (PLL0USB_CLKIN * PLL0USB_M / PLL0USB_P)
-  #define PLL0USB_FCCO (PLL0USB_FOUT * 2 * PLL0USB_P)
- #elif ((PLL0USB_DIRECTI == 0) && (PLL0USB_DIRECTO == 1)) /* Mode 1c          */
-  #define PLL0USB_FOUT (PLL0USB_CLKIN * 2 * PLL0USB_M / PLL0USB_N)
-  #define PLL0USB_FCCO (PLL0USB_FOUT)
- #else                                                    /* Mode 1d          */
-  #define PLL0USB_FOUT (PLL0USB_CLKIN * PLL0USB_M / (PLL0USB_P * PLL0USB_N))
-  #define PLL0USB_FCCO (PLL0USB_FOUT * 2 * PLL0USB_P)
- #endif
-
- #if (PLL0USB_FCCO < 275000000UL || PLL0USB_FCCO > 550000000UL)
-  #error "PLL0USB Fcco frequency out of range! (275MHz >= Fcco <= 550MHz)"
- #endif
- #if (PLL0USB_FOUT < 4300000UL || PLL0USB_FOUT > 550000000UL)
-  #error "PLL0USB output frequency out of range! (4.3MHz >= Fclkout <= 550MHz)"
- #endif
-#endif
-
-/* PLL1 Setting Check */
-#if (PLL1_BYPASS == 0)
- #if (PLL1_CLK_SEL == CLK_SRC_XTAL)
-  #define PLL1_CLKIN CLK_XTAL
- #else
-  #define PLL1_CLKIN CLK_IRC
- #endif
-
- #if   (PLL1_DIRECT == 1)               /* Direct Mode                        */
-  #define PLL1_FCCO ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
-  #define PLL1_FOUT ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
- #elif (PLL1_FBSEL  == 1)               /* Integer Mode                       */
-  #define PLL1_FCCO ((2 * (1 << PLL1_PSEL)) * (PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
-  #define PLL1_FOUT ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
- #else                                  /* Noninteger Mode                    */
-  #define PLL1_FCCO ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
-  #define PLL1_FOUT (PLL1_FCCO / (2 * (1 << PLL1_PSEL)))
- #endif
- #if (PLL1_FCCO < 156000000UL || PLL1_FCCO > 320000000UL)
-  #error "PLL1 Fcco frequency out of range! (156MHz >= Fcco <= 320MHz)"
- #endif
- #if (PLL1_FOUT < 9750000UL || PLL1_FOUT > 204000000UL)
-  #error "PLL1 output frequency out of range! (9.75MHz >= Fclkout <= 204MHz)"
- #endif
-#endif
-
-
-/*----------------------------------------------------------------------------
-  System Core Clock variable
- *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = 180000000U; /* System Clock Frequency (Core Clock) */
-
-
-/******************************************************************************
- * SetClock
- ******************************************************************************/
-void SetClock (void) {
-  uint32_t x, i;
-  uint32_t selp, seli;
-
-
-  /* Set flash accelerator configuration for bank A and B to reset value      */
-  LPC_CREG->FLASHCFGA |= (0xF << 12);
-  LPC_CREG->FLASHCFGB |= (0xF << 12);
-
-  /* Set flash wait states to maximum                                         */
-  LPC_EMC->STATICWAITRD0  = 0x1F;
-
-  /* Switch BASE_M4_CLOCK to IRC                                              */
-  LPC_CGU->BASE_M4_CLK = (0x01        << 11) |  /* Autoblock En               */
-                         (CLK_SRC_IRC << 24) ;  /* Set clock source           */
-
-  /* Configure input to crystal oscilator                                     */
-  LPC_CGU->XTAL_OSC_CTRL = (0 << 0) |   /* Enable oscillator-pad              */
-                           (0 << 1) |   /* Operation with crystal connected   */
-                           (0 << 2) ;   /* Low-frequency mode                 */
-
-  /* Wait ~250us @ 12MHz */
-  for (i = 1500; i; i--);
-
-#if (USE_SPIFI)
-/* configure SPIFI clk to IRC via IDIVA (later IDIVA is configured to PLL1/3) */
-  LPC_CGU->IDIVA_CTRL     = (0              <<  0) |  /* Disable Power-down   */
-                            (0              <<  2) |  /* IDIV                 */
-                            (1              << 11) |  /* Autoblock En         */
-                            (CLK_SRC_IRC    << 24) ;  /* Clock source         */
-
-  LPC_CGU->BASE_SPIFI_CLK = (0              <<  0) |  /* Disable Power-down   */
-                            (0              <<  2) |  /* IDIV                 */
-                            (1              << 11) |  /* Autoblock En         */
-                            (CLK_SRC_IDIVA  << 24) ;  /* Clock source         */
-#endif
-
-/*----------------------------------------------------------------------------
-  PLL1 Setup
- *----------------------------------------------------------------------------*/
-  /* Power down PLL                                                           */
-  LPC_CGU->PLL1_CTRL |= 1;
-
-#if ((PLL1_FOUT > 110000000UL) && (CPU_CLK_SEL == CLK_SRC_PLL1))
-  /* To run at full speed, CPU must first run at an intermediate speed        */
-  LPC_CGU->PLL1_CTRL = (0            << 0) | /* PLL1 Enabled                  */
-                       (PLL1_BYPASS  << 1) | /* CCO out sent to post-dividers */
-                       (PLL1_FBSEL   << 6) | /* PLL output used as feedback   */
-                       (0            << 7) | /* Direct on/off                 */
-                       (PLL1_PSEL    << 8) | /* PSEL                          */
-                       (0            << 11)| /* Autoblock Disabled            */
-                       (PLL1_NSEL    << 12)| /* NSEL                          */
-                       (PLL1_MSEL    << 16)| /* MSEL                          */
-                       (PLL1_CLK_SEL << 24); /* Clock source                  */
-  /* Wait for lock                                                            */
-  while (!(LPC_CGU->PLL1_STAT & 1));
-
-  /* CPU base clock is in the mid frequency range before final clock set      */
-  LPC_CGU->BASE_M4_CLK     = (0x01 << 11) |  /* Autoblock En                  */
-                             (0x09 << 24) ;  /* Clock source: PLL1            */
-
-  /* Max. BASE_M4_CLK frequency here is 102MHz, wait at least 20us */
-  for (i = 1050; i; i--);                    /* Wait minimum 2100 cycles      */
-#endif
-  /* Configure PLL1                                                           */
-  LPC_CGU->PLL1_CTRL = (0            << 0) | /* PLL1 Enabled                  */
-                       (PLL1_BYPASS  << 1) | /* CCO out sent to post-dividers */
-                       (PLL1_FBSEL   << 6) | /* PLL output used as feedback   */
-                       (PLL1_DIRECT  << 7) | /* Direct on/off                 */
-                       (PLL1_PSEL    << 8) | /* PSEL                          */
-                       (1            << 11)| /* Autoblock En                  */
-                       (PLL1_NSEL    << 12)| /* NSEL                          */
-                       (PLL1_MSEL    << 16)| /* MSEL                          */
-                       (PLL1_CLK_SEL << 24); /* Clock source                  */
-
-  /* Wait for lock                                                            */
-  while (!(LPC_CGU->PLL1_STAT & 1));
-
-  /* Set CPU base clock source                                                */
-  LPC_CGU->BASE_M4_CLK = (0x01        << 11) |  /* Autoblock En               */
-                         (CPU_CLK_SEL << 24) ;  /* Set clock source           */
-
-  /* Set flash accelerator configuration for internal flash bank A and B      */
-  LPC_CREG->FLASHCFGA = (LPC_CREG->FLASHCFGA & (~0x0000F000)) | (FLASHCFG_FLASHTIM << 12);
-  LPC_CREG->FLASHCFGB = (LPC_CREG->FLASHCFGB & (~0x0000F000)) | (FLASHCFG_FLASHTIM << 12);
-
-/*----------------------------------------------------------------------------
-  PLL0USB Setup
- *----------------------------------------------------------------------------*/
-
-  /* Power down PLL0USB                                                       */
-  LPC_CGU->PLL0USB_CTRL  |= 1;
-
-  /* M divider                                                                */
-  x = 0x00004000;
-  switch (PLL0USB_M) {
-    case 0:  x = 0xFFFFFFFF;
-      break;
-    case 1:  x = 0x00018003;
-      break;
-    case 2:  x = 0x00010003;
-      break;
-    default:
-      for (i = PLL0USB_M; i <= 0x8000; i++) {
-        x = (((x ^ (x >> 1)) & 1) << 14) | ((x >> 1) & 0x3FFF);
-      }
-  }
-
-  if (PLL0USB_M < 60) selp = (PLL0USB_M >> 1) + 1;
-  else        selp = 31;
-
-  if      (PLL0USB_M > 16384) seli = 1;
-  else if (PLL0USB_M >  8192) seli = 2;
-  else if (PLL0USB_M >  2048) seli = 4;
-  else if (PLL0USB_M >=  501) seli = 8;
-  else if (PLL0USB_M >=   60) seli = 4 * (1024 / (PLL0USB_M + 9));
-  else                        seli = (PLL0USB_M & 0x3C) + 4;
-  LPC_CGU->PLL0USB_MDIV   =  (selp   << 17) |
-                             (seli   << 22) |
-                             (x      <<  0);
-
-  /* N divider                                                                */
-  x = 0x80;
-  switch (PLL0USB_N) {
-    case 0:  x = 0xFFFFFFFF;
-      break;
-    case 1:  x = 0x00000302;
-      break;
-    case 2:  x = 0x00000202;
-      break;
-    default:
-      for (i = PLL0USB_N; i <= 0x0100; i++) {
-        x =(((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F);
-      }
-  }
-  LPC_CGU->PLL0USB_NP_DIV = (x << 12);
-
-  /* P divider                                                                */
-  x = 0x10;
-  switch (PLL0USB_P) {
-    case 0:  x = 0xFFFFFFFF;
-      break;
-    case 1:  x = 0x00000062;
-      break;
-    case 2:  x = 0x00000042;
-      break;
-    default:
-      for (i = PLL0USB_P; i <= 0x200; i++) {
-        x = (((x ^ (x >> 2)) & 1) << 4) | ((x >> 1) &0x0F);
-      }
-  }
-  LPC_CGU->PLL0USB_NP_DIV |= x;
-
-  LPC_CGU->PLL0USB_CTRL  = (PLL0USB_CLK_SEL   << 24) | /* Clock source sel    */
-                           (1                 << 11) | /* Autoblock En        */
-                           (1                 << 4 ) | /* PLL0USB clock en    */
-                           (PLL0USB_DIRECTO   << 3 ) | /* Direct output       */
-                           (PLL0USB_DIRECTI   << 2 ) | /* Direct input        */
-                           (PLL0USB_BYPASS    << 1 ) | /* PLL bypass          */
-                           (0                 << 0 ) ; /* PLL0USB Enabled     */
-  while (!(LPC_CGU->PLL0USB_STAT & 1));
-
-
-/*----------------------------------------------------------------------------
-  Integer divider Setup
- *----------------------------------------------------------------------------*/
-
-  /* Configure integer dividers                                               */
-  LPC_CGU->IDIVA_CTRL = (0              <<  0) |  /* Disable Power-down       */
-                        (IDIVA_IDIV     <<  2) |  /* IDIV                     */
-                        (1              << 11) |  /* Autoblock En             */
-                        (IDIVA_CLK_SEL  << 24) ;  /* Clock source             */
-
-  LPC_CGU->IDIVB_CTRL = (0              <<  0) |  /* Disable Power-down       */
-                        (IDIVB_IDIV     <<  2) |  /* IDIV                     */
-                        (1              << 11) |  /* Autoblock En             */
-                        (IDIVB_CLK_SEL  << 24) ;  /* Clock source             */
-
-  LPC_CGU->IDIVC_CTRL = (0              <<  0) |  /* Disable Power-down       */
-                        (IDIVC_IDIV     <<  2) |  /* IDIV                     */
-                        (1              << 11) |  /* Autoblock En             */
-                        (IDIVC_CLK_SEL  << 24) ;  /* Clock source             */
-
-  LPC_CGU->IDIVD_CTRL = (0              <<  0) |  /* Disable Power-down       */
-                        (IDIVD_IDIV     <<  2) |  /* IDIV                     */
-                        (1              << 11) |  /* Autoblock En             */
-                        (IDIVD_CLK_SEL  << 24) ;  /* Clock source             */
-
-  LPC_CGU->IDIVE_CTRL = (0              <<  0) |  /* Disable Power-down       */
-                        (IDIVE_IDIV     <<  2) |  /* IDIV                     */
-                        (1              << 11) |  /* Autoblock En             */
-                        (IDIVE_CLK_SEL  << 24) ;  /* Clock source             */
-}
-
-
-/*----------------------------------------------------------------------------
-  Approximate delay function (must be used after SystemCoreClockUpdate() call)
- *----------------------------------------------------------------------------*/
-#define CPU_NANOSEC(x) (((uint64_t)(x) * SystemCoreClock)/1000000000)
-
-static void WaitUs (uint32_t us) {
-  uint32_t cyc = us * CPU_NANOSEC(1000)/4;
-  while(cyc--);
-}
-
-
-/*----------------------------------------------------------------------------
-  External Memory Controller Definitions
- *----------------------------------------------------------------------------*/
-#define SDRAM_ADDR_BASE 0x28000000      /* SDRAM base address                 */
-/* Write Mode register macro                                                  */
-#define WR_MODE(x) (*((volatile uint32_t *)(SDRAM_ADDR_BASE | (x))))
-
-/* Pin Settings: Glith filter DIS, Input buffer EN, Fast Slew Rate, No Pullup */
-#define EMC_PIN_SET ((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4))
-#define EMC_NANOSEC(ns, freq, div) (((uint64_t)(ns) * ((freq)/((div)+1)))/1000000000)
-
-#define EMC_CLK_DLY_TIM_2  (0x7777)     /* 3.5 ns delay for the EMC clock out */
-#define EMC_CLK_DLY_TIM_0  (0x0000)     /* No delay for the EMC clock out     */
-
-typedef void (*emcdivby2) (volatile uint32_t *creg6, volatile uint32_t *emcdiv, uint32_t cfg);
-
-const uint16_t emcdivby2_opc[] =  {
-  0x6803,        /*      LDR  R3,[R0,#0]      ; Load CREG6          */
-  0xF443,0x3380, /*      ORR  R3,R3,#0x10000  ; Set Divided by 2    */
-  0x6003,        /*      STR  R3,[R0,#0]      ; Store CREG6         */
-  0x600A,        /*      STR  R2,[R1,#0]      ; EMCDIV_CFG = cfg    */
-  0x684B,        /* loop LDR  R3,[R1,#4]      ; Load EMCDIV_STAT    */
-  0x07DB,        /*      LSLS R3,R3,#31       ; Check EMCDIV_STAT.0 */
-  0xD0FC,        /*      BEQ  loop            ; Jump if 0           */
-  0x4770,        /*      BX   LR              ; Exit                */
-  0,
-};
-
-#define        emcdivby2_szw ((sizeof(emcdivby2_opc)+3)/4)
-#define        emcdivby2_ram 0x10000000
-
-/*----------------------------------------------------------------------------
-  Initialize external memory controller
- *----------------------------------------------------------------------------*/
-
-void SystemInit_ExtMemCtl (void) {
-  uint32_t emcdivby2_buf[emcdivby2_szw];
-  uint32_t div, n;
-
-  /* Select and enable EMC branch clock */
-  LPC_CCU1->CLK_M4_EMC_CFG = (1 << 2) | (1 << 1) | 1;
-  while (!(LPC_CCU1->CLK_M4_EMC_STAT & 1));
-
-  /* Set EMC clock output delay */
-  if (SystemCoreClock < 80000000UL) {
-    LPC_SCU->EMCDELAYCLK = EMC_CLK_DLY_TIM_0; /* No EMC clock out delay       */
-  }
-  else {
-    LPC_SCU->EMCDELAYCLK = EMC_CLK_DLY_TIM_2; /* 2.0 ns EMC clock out delay   */
-  }
-
-  /* Configure EMC port pins */
-  LPC_SCU->SFSP1_0  = EMC_PIN_SET | 2;  /* P1_0:  A5                          */
-  LPC_SCU->SFSP1_1  = EMC_PIN_SET | 2;  /* P1_1:  A6                          */
-  LPC_SCU->SFSP1_2  = EMC_PIN_SET | 2;  /* P1_2:  A7                          */
-  LPC_SCU->SFSP1_3  = EMC_PIN_SET | 3;  /* P1_3:  OE                          */
-  LPC_SCU->SFSP1_4  = EMC_PIN_SET | 3;  /* P1_4:  BLS0                        */
-  LPC_SCU->SFSP1_5  = EMC_PIN_SET | 3;  /* P1_5:  CS0                         */
-  LPC_SCU->SFSP1_6  = EMC_PIN_SET | 3;  /* P1_6:  WE                          */
-  LPC_SCU->SFSP1_7  = EMC_PIN_SET | 3;  /* P1_7:  D0                          */
-  LPC_SCU->SFSP1_8  = EMC_PIN_SET | 3;  /* P1_8:  D1                          */
-  LPC_SCU->SFSP1_9  = EMC_PIN_SET | 3;  /* P1_9:  D2                          */
-  LPC_SCU->SFSP1_10 = EMC_PIN_SET | 3;  /* P1_10: D3                          */
-  LPC_SCU->SFSP1_11 = EMC_PIN_SET | 3;  /* P1_11: D4                          */
-  LPC_SCU->SFSP1_12 = EMC_PIN_SET | 3;  /* P1_12: D5                          */
-  LPC_SCU->SFSP1_13 = EMC_PIN_SET | 3;  /* P1_13: D6                          */
-  LPC_SCU->SFSP1_14 = EMC_PIN_SET | 3;  /* P1_14: D7                          */
-
-  LPC_SCU->SFSP2_0  = EMC_PIN_SET | 2;  /* P2_0:  A13                         */
-  LPC_SCU->SFSP2_1  = EMC_PIN_SET | 2;  /* P2_1:  A12                         */
-  LPC_SCU->SFSP2_2  = EMC_PIN_SET | 2;  /* P2_2:  A11                         */
-  LPC_SCU->SFSP2_6  = EMC_PIN_SET | 2;  /* P2_6:  A10                         */
-  LPC_SCU->SFSP2_7  = EMC_PIN_SET | 3;  /* P2_7:  A9                          */
-  LPC_SCU->SFSP2_8  = EMC_PIN_SET | 3;  /* P2_8:  A8                          */
-  LPC_SCU->SFSP2_9  = EMC_PIN_SET | 3;  /* P2_9:  A0                          */
-  LPC_SCU->SFSP2_10 = EMC_PIN_SET | 3;  /* P2_10: A1                          */
-  LPC_SCU->SFSP2_11 = EMC_PIN_SET | 3;  /* P2_11: A2                          */
-  LPC_SCU->SFSP2_12 = EMC_PIN_SET | 3;  /* P2_12: A3                          */
-  LPC_SCU->SFSP2_13 = EMC_PIN_SET | 3;  /* P2_13: A4                          */
-
-  LPC_SCU->SFSP5_0  = EMC_PIN_SET | 2;  /* P5_0:  D12                         */
-  LPC_SCU->SFSP5_1  = EMC_PIN_SET | 2;  /* P5_1:  D13                         */
-  LPC_SCU->SFSP5_2  = EMC_PIN_SET | 2;  /* P5_2:  D14                         */
-  LPC_SCU->SFSP5_3  = EMC_PIN_SET | 2;  /* P5_3:  D15                         */
-  LPC_SCU->SFSP5_4  = EMC_PIN_SET | 2;  /* P5_4:  D8                          */
-  LPC_SCU->SFSP5_5  = EMC_PIN_SET | 2;  /* P5_5:  D9                          */
-  LPC_SCU->SFSP5_6  = EMC_PIN_SET | 2;  /* P5_6:  D10                         */
-  LPC_SCU->SFSP5_7  = EMC_PIN_SET | 2;  /* P5_7:  D11                         */
-
-  LPC_SCU->SFSP6_1  = EMC_PIN_SET | 1;  /* P6_1:  DYCS1                       */
-  LPC_SCU->SFSP6_2  = EMC_PIN_SET | 1;  /* P6_3:  CKEOUT1                     */
-  LPC_SCU->SFSP6_3  = EMC_PIN_SET | 3;  /* P6_3:  CS1                         */
-  LPC_SCU->SFSP6_4  = EMC_PIN_SET | 3;  /* P6_4:  CAS                         */
-  LPC_SCU->SFSP6_5  = EMC_PIN_SET | 3;  /* P6_5:  RAS                         */
-  LPC_SCU->SFSP6_6  = EMC_PIN_SET | 1;  /* P6_6:  BLS1                        */
-  LPC_SCU->SFSP6_7  = EMC_PIN_SET | 1;  /* P6_7:  A15                         */
-  LPC_SCU->SFSP6_8  = EMC_PIN_SET | 1;  /* P6_8:  A14                         */
-  LPC_SCU->SFSP6_9  = EMC_PIN_SET | 3;  /* P6_9:  DYCS0                       */
-  LPC_SCU->SFSP6_10 = EMC_PIN_SET | 3;  /* P6_10: DQMOUT1                     */
-  LPC_SCU->SFSP6_11 = EMC_PIN_SET | 3;  /* P6_11: CKEOUT0                     */
-  LPC_SCU->SFSP6_12 = EMC_PIN_SET | 3;  /* P6_12: DQMOUT0                     */
-
-  LPC_SCU->SFSPA_4  = EMC_PIN_SET | 3;  /* PA_4:  A23                         */
-
-  LPC_SCU->SFSPD_0  = EMC_PIN_SET | 2;  /* PD_0:  DQMOUT2                     */
-  LPC_SCU->SFSPD_1  = EMC_PIN_SET | 2;  /* PD_1:  CKEOUT2                     */
-  LPC_SCU->SFSPD_2  = EMC_PIN_SET | 2;  /* PD_2:  D16                         */
-  LPC_SCU->SFSPD_3  = EMC_PIN_SET | 2;  /* PD_3:  D17                         */
-  LPC_SCU->SFSPD_4  = EMC_PIN_SET | 2;  /* PD_4:  D18                         */
-  LPC_SCU->SFSPD_5  = EMC_PIN_SET | 2;  /* PD_5:  D19                         */
-  LPC_SCU->SFSPD_6  = EMC_PIN_SET | 2;  /* PD_6:  D20                         */
-  LPC_SCU->SFSPD_7  = EMC_PIN_SET | 2;  /* PD_7:  D21                         */
-  LPC_SCU->SFSPD_8  = EMC_PIN_SET | 2;  /* PD_8:  D22                         */
-  LPC_SCU->SFSPD_9  = EMC_PIN_SET | 2;  /* PD_9:  D23                         */
-  LPC_SCU->SFSPD_10 = EMC_PIN_SET | 2;  /* PD_10: BLS3                        */
-  LPC_SCU->SFSPD_11 = EMC_PIN_SET | 2;  /* PD_11: CS3                         */
-  LPC_SCU->SFSPD_12 = EMC_PIN_SET | 2;  /* PD_12: CS2                         */
-  LPC_SCU->SFSPD_13 = EMC_PIN_SET | 2;  /* PD_13: BLS2                        */
-  LPC_SCU->SFSPD_14 = EMC_PIN_SET | 2;  /* PD_14: DYCS2                       */
-  LPC_SCU->SFSPD_15 = EMC_PIN_SET | 2;  /* PD_15: A17                         */
-  LPC_SCU->SFSPD_16 = EMC_PIN_SET | 2;  /* PD_16: A16                         */
-
-  LPC_SCU->SFSPE_0  = EMC_PIN_SET | 3;  /* PE_0:  A18                         */
-  LPC_SCU->SFSPE_1  = EMC_PIN_SET | 3;  /* PE_1:  A19                         */
-  LPC_SCU->SFSPE_2  = EMC_PIN_SET | 3;  /* PE_2:  A20                         */
-  LPC_SCU->SFSPE_3  = EMC_PIN_SET | 3;  /* PE_3:  A21                         */
-  LPC_SCU->SFSPE_4  = EMC_PIN_SET | 3;  /* PE_4:  A22                         */
-  LPC_SCU->SFSPE_5  = EMC_PIN_SET | 3;  /* PE_5:  D24                         */
-  LPC_SCU->SFSPE_6  = EMC_PIN_SET | 3;  /* PE_6:  D25                         */
-  LPC_SCU->SFSPE_7  = EMC_PIN_SET | 3;  /* PE_7:  D26                         */
-  LPC_SCU->SFSPE_8  = EMC_PIN_SET | 3;  /* PE_8:  D27                         */
-  LPC_SCU->SFSPE_9  = EMC_PIN_SET | 3;  /* PE_9:  D28                         */
-  LPC_SCU->SFSPE_10 = EMC_PIN_SET | 3;  /* PE_10: D29                         */
-  LPC_SCU->SFSPE_11 = EMC_PIN_SET | 3;  /* PE_11: D30                         */
-  LPC_SCU->SFSPE_12 = EMC_PIN_SET | 3;  /* PE_12: D31                         */
-  LPC_SCU->SFSPE_13 = EMC_PIN_SET | 3;  /* PE_13: DQMOUT3                     */
-  LPC_SCU->SFSPE_14 = EMC_PIN_SET | 3;  /* PE_14: DYCS3                       */
-  LPC_SCU->SFSPE_15 = EMC_PIN_SET | 3;  /* PE_15: CKEOUT3                     */
-
-  LPC_EMC->CONTROL  = 0x00000001;       /* EMC Enable                         */
-  LPC_EMC->CONFIG   = 0x00000000;       /* Little-endian, Clock Ratio 1:1     */
-
-  div = 0;
-  if (SystemCoreClock > 120000000UL) {
-    /* Use EMC clock divider and EMC clock output delay */
-    div = 1;
-    /* Following code must be executed in RAM to ensure stable operation      */
-    /* LPC_CCU1->CLK_M4_EMCDIV_CFG = (1 << 5) | (1 << 2) | (1 << 1) | 1;      */
-    /* LPC_CREG->CREG6 |= (1 << 16);       // EMC_CLK_DIV divided by 2        */
-    /* while (!(LPC_CCU1->CLK_M4_EMCDIV_STAT & 1));                           */
-
-    /* This code configures EMC clock divider and is executed in RAM          */
-    for (n = 0; n < emcdivby2_szw; n++) {
-      emcdivby2_buf[n] =  *((uint32_t *)emcdivby2_ram + n);
-      *((uint32_t *)emcdivby2_ram + n) = *((uint32_t *)emcdivby2_opc + n);
-    }
-    __ISB();
-    ((emcdivby2 )(emcdivby2_ram+1))(&LPC_CREG->CREG6, &LPC_CCU1->CLK_M4_EMCDIV_CFG, (1 << 5) | (1 << 2) | (1 << 1) | 1);
-    for (n = 0; n < emcdivby2_szw; n++) {
-      *((uint32_t *)emcdivby2_ram + n) = emcdivby2_buf[n];
-    }
-  }
-
-  /* Configure EMC clock-out pins                                             */
-  LPC_SCU->SFSCLK_0 = EMC_PIN_SET | 0;  /* CLK0                               */
-  LPC_SCU->SFSCLK_1 = EMC_PIN_SET | 0;  /* CLK1                               */
-  LPC_SCU->SFSCLK_2 = EMC_PIN_SET | 0;  /* CLK2                               */
-  LPC_SCU->SFSCLK_3 = EMC_PIN_SET | 0;  /* CLK3                               */
-
-  /* Static memory configuration (chip select 0)                              */
-#if (USE_EXT_STAT_MEM_CS0)
-  LPC_EMC->STATICCONFIG0  = (1 <<  7) | /* Byte lane state: use WE signal     */
-                            (2 <<  0) | /* Memory width 32-bit                */
-                            (1 <<  3);  /* Async page mode enable             */
-
-  LPC_EMC->STATICWAITOEN0 = (0 <<  0) ; /* Wait output enable: No delay       */
-
-  LPC_EMC->STATICWAITPAGE0 = 2;
-
-  /* Set Static Memory Read Delay for 90ns External NOR Flash                 */
-  LPC_EMC->STATICWAITRD0  = 1 + EMC_NANOSEC(90, SystemCoreClock, div);
-  LPC_EMC->STATICCONFIG0 |= (1 << 19) ; /* Enable buffer                      */
-#endif
-
-  /* Dynamic memory configuration (chip select 0)                             */
-#if (USE_EXT_DYN_MEM_CS0)
-
-  /* Set Address mapping: 128Mb(4Mx32), 4 banks, row len = 12, column len = 8 */
-  LPC_EMC->DYNAMICCONFIG0    = (1 << 14) |  /* AM[14]   = 1                   */
-                               (0 << 12) |  /* AM[12]   = 0                   */
-                               (2 <<  9) |  /* AM[11:9] = 2                   */
-                               (2 <<  7) ;  /* AM[8:7]  = 2                   */
-
-  LPC_EMC->DYNAMICRASCAS0    = 0x00000303;  /* Latency: RAS 3, CAS 3 CCLK cyc.*/
-  LPC_EMC->DYNAMICREADCONFIG = 0x00000001;  /* Command delayed by 1/2 CCLK    */
-
-  LPC_EMC->DYNAMICRP         = EMC_NANOSEC (20, SystemCoreClock, div);
-  LPC_EMC->DYNAMICRAS        = EMC_NANOSEC (42, SystemCoreClock, div);
-  LPC_EMC->DYNAMICSREX       = EMC_NANOSEC (63, SystemCoreClock, div);
-  LPC_EMC->DYNAMICAPR        = EMC_NANOSEC (70, SystemCoreClock, div);
-  LPC_EMC->DYNAMICDAL        = EMC_NANOSEC (70, SystemCoreClock, div);
-  LPC_EMC->DYNAMICWR         = EMC_NANOSEC (30, SystemCoreClock, div);
-  LPC_EMC->DYNAMICRC         = EMC_NANOSEC (63, SystemCoreClock, div);
-  LPC_EMC->DYNAMICRFC        = EMC_NANOSEC (63, SystemCoreClock, div);
-  LPC_EMC->DYNAMICXSR        = EMC_NANOSEC (63, SystemCoreClock, div);
-  LPC_EMC->DYNAMICRRD        = EMC_NANOSEC (14, SystemCoreClock, div);
-  LPC_EMC->DYNAMICMRD        = EMC_NANOSEC (30, SystemCoreClock, div);
-
-  WaitUs (100);
-  LPC_EMC->DYNAMICCONTROL    = 0x00000183;  /* Issue NOP command              */
-  WaitUs (10);
-  LPC_EMC->DYNAMICCONTROL    = 0x00000103;  /* Issue PALL command             */
-  WaitUs (1);
-  LPC_EMC->DYNAMICCONTROL    = 0x00000183;  /* Issue NOP command              */
-  WaitUs (1);
-  LPC_EMC->DYNAMICREFRESH    = EMC_NANOSEC(  200, SystemCoreClock, div) / 16 + 1;
-  WaitUs (10);
-  LPC_EMC->DYNAMICREFRESH    = EMC_NANOSEC(15625, SystemCoreClock, div) / 16 + 1;
-  WaitUs (10);
-  LPC_EMC->DYNAMICCONTROL    = 0x00000083;  /* Issue MODE command             */
-
-  /* Mode register: Burst Length: 4, Burst Type: Sequential, CAS Latency: 3   */
-  WR_MODE(((3 << 4) | 2) << 12);
-
-  WaitUs (10);
-  LPC_EMC->DYNAMICCONTROL    = 0x00000002;  /* Issue NORMAL command           */
-  LPC_EMC->DYNAMICCONFIG0   |= (1 << 19);   /* Enable buffer                  */
-#endif
-}
-
-
-/*----------------------------------------------------------------------------
-  Measure frequency using frequency monitor
- *----------------------------------------------------------------------------*/
-uint32_t MeasureFreq (uint32_t clk_sel) {
-  uint32_t fcnt, rcnt, fout;
-
-  /* Set register values */
-  LPC_CGU->FREQ_MON &= ~(1 << 23);                /* Stop frequency counters  */
-  LPC_CGU->FREQ_MON  = (clk_sel << 24) | 511;     /* RCNT == 511              */
-  LPC_CGU->FREQ_MON |= (1 << 23);                 /* Start RCNT and FCNT      */
-  while (LPC_CGU->FREQ_MON & (1 << 23)) {
-    fcnt = (LPC_CGU->FREQ_MON >> 9) & 0x3FFF;
-    rcnt = (LPC_CGU->FREQ_MON     ) & 0x01FF;
-    if (fcnt == 0 && rcnt == 0) {
-      return (0);                                 /* No input clock present   */
-    }
-  }
-  fcnt = (LPC_CGU->FREQ_MON >> 9) & 0x3FFF;
-  fout = fcnt * (12000000U/511U);                 /* FCNT * (IRC_CLK / RCNT)  */
-
-  return (fout);
-}
-
-
-/*----------------------------------------------------------------------------
-  Get PLL1 (divider and multiplier) parameters
- *----------------------------------------------------------------------------*/
-static __inline uint32_t GetPLL1Param (void) {
-  uint32_t ctrl;
-  uint32_t p;
-  uint32_t div, mul;
-
-  ctrl = LPC_CGU->PLL1_CTRL;
-  div = ((ctrl >> 12) & 0x03) + 1;
-  mul = ((ctrl >> 16) & 0xFF) + 1;
-  p = 1 << ((ctrl >>  8) & 0x03);
-
-  if (ctrl & (1 << 1)) {
-    /* Bypass = 1, PLL1 input clock sent to post-dividers */
-    if (ctrl & (1 << 7)) {
-      div *= (2*p);
-    }
-  }
-  else {
-    /* Direct and integer mode */
-    if (((ctrl & (1 << 7)) == 0) && ((ctrl & (1 << 6)) == 0)) {
-      /* Non-integer mode */
-      div *= (2*p);
-    }
-  }
-  return ((div << 8) | (mul));
-}
-
-
-/*----------------------------------------------------------------------------
-  Get input clock source for specified clock generation block
- *----------------------------------------------------------------------------*/
-int32_t GetClkSel (uint32_t clk_src) {
-  uint32_t reg;
-  int32_t clk_sel = -1;
-
-  switch (clk_src) {
-    case CLK_SRC_IRC:
-    case CLK_SRC_ENET_RX:
-    case CLK_SRC_ENET_TX:
-    case CLK_SRC_GP_CLKIN:
-      return (clk_src);
-
-    case CLK_SRC_32KHZ:
-      return ((LPC_CREG->CREG0 & 0x0A) != 0x02) ? (-1) : (CLK_SRC_32KHZ);
-    case CLK_SRC_XTAL:
-     return  (LPC_CGU->XTAL_OSC_CTRL & 1)       ? (-1) : (CLK_SRC_XTAL);
-
-    case CLK_SRC_PLL0U: reg = LPC_CGU->PLL0USB_CTRL;    break;
-    case CLK_SRC_PLL0A: reg = LPC_CGU->PLL0AUDIO_CTRL;  break;
-    case CLK_SRC_PLL1:  reg = (LPC_CGU->PLL1_STAT & 1) ? (LPC_CGU->PLL1_CTRL) : (0); break;
-
-    case CLK_SRC_IDIVA: reg = LPC_CGU->IDIVA_CTRL;      break;
-    case CLK_SRC_IDIVB: reg = LPC_CGU->IDIVB_CTRL;      break;
-    case CLK_SRC_IDIVC: reg = LPC_CGU->IDIVC_CTRL;      break;
-    case CLK_SRC_IDIVD: reg = LPC_CGU->IDIVD_CTRL;      break;
-    case CLK_SRC_IDIVE: reg = LPC_CGU->IDIVE_CTRL;      break;
-
-    default:
-      return (clk_sel);
-  }
-  if (!(reg & 1)) {
-    clk_sel = (reg >> 24) & 0x1F;
-  }
-  return (clk_sel);
-}
-
-
-/*----------------------------------------------------------------------------
-  Get clock frequency for specified clock source
- *----------------------------------------------------------------------------*/
-uint32_t GetClockFreq (uint32_t clk_src) {
-  uint32_t tmp;
-  uint32_t mul        =  1;
-  uint32_t div        =  1;
-  uint32_t main_freq  =  0;
-  int32_t  clk_sel    = clk_src;
-
-  do {
-    switch (clk_sel) {
-      case CLK_SRC_32KHZ:    main_freq = CLK_32KHZ;     break;
-      case CLK_SRC_IRC:      main_freq = CLK_IRC;       break;
-      case CLK_SRC_ENET_RX:  main_freq = CLK_ENET_RX;   break;
-      case CLK_SRC_ENET_TX:  main_freq = CLK_ENET_TX;   break;
-      case CLK_SRC_GP_CLKIN: main_freq = CLK_GP_CLKIN;  break;
-      case CLK_SRC_XTAL:     main_freq = CLK_XTAL;      break;
-
-      case CLK_SRC_IDIVA: div *= ((LPC_CGU->IDIVA_CTRL >> 2) & 0x03) + 1; break;
-      case CLK_SRC_IDIVB: div *= ((LPC_CGU->IDIVB_CTRL >> 2) & 0x0F) + 1; break;
-      case CLK_SRC_IDIVC: div *= ((LPC_CGU->IDIVC_CTRL >> 2) & 0x0F) + 1; break;
-      case CLK_SRC_IDIVD: div *= ((LPC_CGU->IDIVD_CTRL >> 2) & 0x0F) + 1; break;
-      case CLK_SRC_IDIVE: div *= ((LPC_CGU->IDIVE_CTRL >> 2) & 0xFF) + 1; break;
-
-      case CLK_SRC_PLL0U: /* Not implemented */  break;
-      case CLK_SRC_PLL0A: /* Not implemented */  break;
-
-      case CLK_SRC_PLL1:
-        tmp = GetPLL1Param ();
-        mul *= (tmp     ) & 0xFF;       /* PLL input clock multiplier         */
-        div *= (tmp >> 8) & 0xFF;       /* PLL input clock divider            */
-        break;
-
-      default:
-        return (0);                     /* Clock not running or not supported */
-    }
-    if (main_freq == 0) {
-      clk_sel = GetClkSel (clk_sel);
-    }
-  }
-  while (main_freq == 0);
-
-  return ((main_freq * mul) / div);
-}
-
-
-/*----------------------------------------------------------------------------
-  System Core Clock update
- *----------------------------------------------------------------------------*/
-void SystemCoreClockUpdate (void) {
-  /* Check BASE_M4_CLK connection */
-  uint32_t base_src = (LPC_CGU->BASE_M4_CLK >> 24) & 0x1F;
-
-  /* Update core clock frequency */
-  SystemCoreClock = GetClockFreq (base_src);
-}
-
-
-extern uint32_t __Vectors;                         /* see startup_LPC43xx.s   */
-
-/*----------------------------------------------------------------------------
-  Initialize the system
- *----------------------------------------------------------------------------*/
-void SystemInit (void) {
-
-  #if (__FPU_USED == 1)
-    SCB->CPACR |= ((3UL << 10*2) |                 /* set CP10 Full Access */
-                   (3UL << 11*2)  );               /* set CP11 Full Access */
-  #endif
-
-  /* Stop CM0 core */
-  LPC_RGU->RESET_CTRL1 = (1 << 24);
-
-  /* Disable SysTick timer                                                    */
-  SysTick->CTRL &= ~(SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk);
-
-  /* Set vector table pointer */
-  SCB->VTOR = ((uint32_t)(&__Vectors)) & 0xFFF00000UL;
-
-  /* Configure PLL0 and PLL1, connect CPU clock to selected clock source */
-  SetClock();
-
-  /* Update SystemCoreClock variable */
-  SystemCoreClockUpdate();
-
-  /* Configure External Memory Controller */
-//SystemInit_ExtMemCtl ();
-}

CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/CMSIS_DAP.uvoptx → CMSIS/DAP/Firmware/Examples/MCU-LINK/CMSIS_DAP.uvoptx

@@ -22,7 +22,7 @@
   </DaveTm>
 
   <Target>
-    <TargetName>LPC-Link2</TargetName>
+    <TargetName>MCU-LINK</TargetName>
     <ToolsetNumber>0x4</ToolsetNumber>
     <ToolsetName>ARM-ADS</ToolsetName>
     <TargetOption>
@@ -103,7 +103,7 @@
         <bEvRecOn>1</bEvRecOn>
         <bSchkAxf>0</bSchkAxf>
         <bTchkAxf>0</bTchkAxf>
-        <nTsel>0</nTsel>
+        <nTsel>15</nTsel>
         <sDll></sDll>
         <sDllPa></sDllPa>
         <sDlgDll></sDlgDll>
@@ -114,28 +114,73 @@
         <tDlgDll></tDlgDll>
         <tDlgPa></tDlgPa>
         <tIfile></tIfile>
-        <pMon>BIN\UL2CM3.DLL</pMon>
+        <pMon>BIN\CMSIS_AGDI_V8M.DLL</pMon>
       </DebugOpt>
       <TargetDriverDllRegistry>
         <SetRegEntry>
           <Number>0</Number>
-          <Key>UL2CM3</Key>
-          <Name>-UV0018BME -O206 -S8 -C0 -P00 -N00("") -D00(00000000) -L00(0) -TO65554 -TC180000000 -TT180000000 -TP21 -TDS802F -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD10000000 -FC10000 -FN1 -FF0LPC18xx43xx_S25FL032 -FS014000000 -FL0400000</Name>
+          <Key>CMSIS_AGDI_V8M</Key>
+          <Name>-X"ULINKplus CMSIS-DAP" -UL68410450A -O206 -S9 -C0 -P00000000 -N00("") -D00(00000000) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN2 -FF0LPC55XX_640.FLM -FS00 -FL098000 -FP0($$Device:LPC55S69JBD64$arm\LPC55XX_640.FLM) -FF1LPC55XX_S_640.FLM -FS110000000 -FL198000 -FP1($$Device:LPC55S69JBD64$arm\LPC55XX_S_640.FLM)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>EVENTREC_CNF</Key>
+          <Name>-l0 -a1 -s0 -f0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ULPL2CM3</Key>
+          <Name>-UL68410450A -O718 -S9 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN2 -FF0LPC55XX_640.FLM -FS00 -FL098000 -FP0($$Device:LPC55S69JBD64$arm\LPC55XX_640.FLM) -FF1LPC55XX_S_640.FLM -FS110000000 -FL198000 -FP1($$Device:LPC55S69JBD64$arm\LPC55XX_S_640.FLM)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMRTXEVENTFLAGS</Key>
+          <Name>-L70 -Z18 -C0 -M0 -T1</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(6010=75,104,552,700,0)(6018=-1,-1,-1,-1,0)(6019=-1,-1,-1,-1,0)(6008=-1,-1,-1,-1,0)(6009=-1,-1,-1,-1,0)(6014=-1,-1,-1,-1,0)(6015=-1,-1,-1,-1,0)(6003=-1,-1,-1,-1,0)(6000=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2V8M</Key>
+          <Name>-UAny -O206 -S9 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN2 -FF0LPC55XX_640.FLM -FS00 -FL098000 -FP0($$Device:LPC55S69JBD64$arm\LPC55XX_640.FLM) -FF1LPC55XX_S_640.FLM -FS110000000 -FL198000 -FP1($$Device:LPC55S69JBD64$arm\LPC55XX_S_640.FLM)</Name>
         </SetRegEntry>
       </TargetDriverDllRegistry>
       <Breakpoint/>
+      <ScvdPack>
+        <Filename>C:\Keil_v5\ARM\PACK\Keil\MDK-Middleware\7.13.0\USB\USB.scvd</Filename>
+        <Type>Keil.MDK-Middleware.7.13.0</Type>
+        <SubType>1</SubType>
+      </ScvdPack>
+      <ScvdPack>
+        <Filename>C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.8.0\CMSIS\RTOS2\RTX\RTX5.scvd</Filename>
+        <Type>ARM.CMSIS.5.8.0</Type>
+        <SubType>1</SubType>
+      </ScvdPack>
       <Tracepoint>
         <THDelay>0</THDelay>
       </Tracepoint>
       <DebugFlag>
         <trace>0</trace>
         <periodic>1</periodic>
-        <aLwin>0</aLwin>
+        <aLwin>1</aLwin>
         <aCover>0</aCover>
         <aSer1>0</aSer1>
         <aSer2>0</aSer2>
         <aPa>0</aPa>
-        <viewmode>0</viewmode>
+        <viewmode>1</viewmode>
         <vrSel>0</vrSel>
         <aSym>0</aSym>
         <aTbox>0</aTbox>
@@ -148,7 +193,7 @@
         <aPa1>0</aPa1>
         <AscS4>0</AscS4>
         <aSer4>0</aSer4>
-        <StkLoc>0</StkLoc>
+        <StkLoc>1</StkLoc>
         <TrcWin>0</TrcWin>
         <newCpu>0</newCpu>
         <uProt>0</uProt>
@@ -168,10 +213,10 @@
       <pMultCmdsp></pMultCmdsp>
       <DebugDescription>
         <Enable>1</Enable>
-        <EnableFlashSeq>0</EnableFlashSeq>
+        <EnableFlashSeq>1</EnableFlashSeq>
         <EnableLog>0</EnableLog>
-        <Protocol>1</Protocol>
-        <DbgClock>10000000</DbgClock>
+        <Protocol>2</Protocol>
+        <DbgClock>5000000</DbgClock>
       </DebugDescription>
     </TargetOption>
   </Target>
@@ -201,8 +246,56 @@
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>.\USBD_User_HID_0.c</PathWithFileName>
-      <FilenameWithoutPath>USBD_User_HID_0.c</FilenameWithoutPath>
+      <PathWithFileName>.\ser_num.c</PathWithFileName>
+      <FilenameWithoutPath>ser_num.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>3</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\USBD_User_CustomClass_0.c</PathWithFileName>
+      <FilenameWithoutPath>USBD_User_CustomClass_0.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>4</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\USBD_User_CDC_ACM_UART_0.c</PathWithFileName>
+      <FilenameWithoutPath>USBD_User_CDC_ACM_UART_0.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>5</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\USBD1_LPC55xxx.c</PathWithFileName>
+      <FilenameWithoutPath>USBD1_LPC55xxx.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>6</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\fsl_usart.c</PathWithFileName>
+      <FilenameWithoutPath>fsl_usart.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
@@ -216,27 +309,71 @@
     <RteFlg>0</RteFlg>
     <File>
       <GroupNumber>2</GroupNumber>
-      <FileNumber>3</FileNumber>
+      <FileNumber>7</FileNumber>
       <FileType>5</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>.\Abstract.txt</PathWithFileName>
-      <FilenameWithoutPath>Abstract.txt</FilenameWithoutPath>
+      <PathWithFileName>.\README.md</PathWithFileName>
+      <FilenameWithoutPath>README.md</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
   </Group>
 
   <Group>
-    <GroupName>CMSIS DAP</GroupName>
+    <GroupName>Board</GroupName>
     <tvExp>1</tvExp>
     <tvExpOptDlg>0</tvExpOptDlg>
     <cbSel>0</cbSel>
     <RteFlg>0</RteFlg>
     <File>
       <GroupNumber>3</GroupNumber>
-      <FileNumber>4</FileNumber>
+      <FileNumber>8</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\board\clock_config.c</PathWithFileName>
+      <FilenameWithoutPath>clock_config.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>9</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\board\peripherals.c</PathWithFileName>
+      <FilenameWithoutPath>peripherals.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>10</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\board\pin_mux.c</PathWithFileName>
+      <FilenameWithoutPath>pin_mux.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>CMSIS DAP</GroupName>
+    <tvExp>1</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>4</GroupNumber>
+      <FileNumber>11</FileNumber>
       <FileType>5</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -247,53 +384,65 @@
       <bShared>0</bShared>
     </File>
     <File>
-      <GroupNumber>3</GroupNumber>
-      <FileNumber>5</FileNumber>
+      <GroupNumber>4</GroupNumber>
+      <FileNumber>12</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\..\Source\DAP.c</PathWithFileName>
+      <PathWithFileName>..\..\Source\DAP.c</PathWithFileName>
       <FilenameWithoutPath>DAP.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
-      <GroupNumber>3</GroupNumber>
-      <FileNumber>6</FileNumber>
+      <GroupNumber>4</GroupNumber>
+      <FileNumber>13</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\..\Source\JTAG_DP.c</PathWithFileName>
+      <PathWithFileName>..\..\Source\JTAG_DP.c</PathWithFileName>
       <FilenameWithoutPath>JTAG_DP.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
-      <GroupNumber>3</GroupNumber>
-      <FileNumber>7</FileNumber>
+      <GroupNumber>4</GroupNumber>
+      <FileNumber>14</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\..\Source\SW_DP.c</PathWithFileName>
+      <PathWithFileName>..\..\Source\SW_DP.c</PathWithFileName>
       <FilenameWithoutPath>SW_DP.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
-      <GroupNumber>3</GroupNumber>
-      <FileNumber>8</FileNumber>
+      <GroupNumber>4</GroupNumber>
+      <FileNumber>15</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\..\Source\SWO.c</PathWithFileName>
+      <PathWithFileName>..\..\Source\SWO.c</PathWithFileName>
       <FilenameWithoutPath>SWO.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
+    <File>
+      <GroupNumber>4</GroupNumber>
+      <FileNumber>16</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\Source\UART.c</PathWithFileName>
+      <FilenameWithoutPath>UART.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
   </Group>
 
   <Group>
@@ -314,7 +463,7 @@
 
   <Group>
     <GroupName>::Device</GroupName>
-    <tvExp>1</tvExp>
+    <tvExp>0</tvExp>
     <tvExpOptDlg>0</tvExpOptDlg>
     <cbSel>0</cbSel>
     <RteFlg>1</RteFlg>

CMSIS/DAP/Firmware/Examples/MCU-LINK/CMSIS_DAP.uvprojx

@@ -0,0 +1,955 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>MCU-LINK</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>6160000::V6.16::ARMCLANG</pCCUsed>
+      <uAC6>1</uAC6>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>LPC55S69JBD64:cm33_core0</Device>
+          <Vendor>NXP</Vendor>
+          <PackID>NXP.LPC55S69_DFP.13.1.0</PackID>
+          <PackURL>https://mcuxpresso.nxp.com/cmsis_pack/repo/</PackURL>
+          <Cpu>IRAM(0x20000000,0x040000) IRAM2(0x20040000,0x4000) IROM(0x00000000,0x098000) XRAM(0x04000000,0x8000) XRAM2(0x40100000,0x4000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP TZ CLOCK(12000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN2 -FF0LPC55XX_640 -FS00 -FL098000 -FF1LPC55XX_S_640 -FS110000000 -FL198000 -FP0($$Device:LPC55S69JBD64$arm\LPC55XX_640.FLM) -FP1($$Device:LPC55S69JBD64$arm\LPC55XX_S_640.FLM))</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:LPC55S69JBD64$fsl_device_registers.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:LPC55S69JBD64$LPC55S69_cm33_core0.xml</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\Objects\</OutputDirectory>
+          <OutputName>CMSIS_DAP</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>1</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\Listings\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName></SimDllName>
+          <SimDllArguments></SimDllArguments>
+          <SimDlgDll></SimDlgDll>
+          <SimDlgDllArguments></SimDlgDllArguments>
+          <TargetDllName>SARMV8M.DLL</TargetDllName>
+          <TargetDllArguments> -MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM33</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4102</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2V8M.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M33"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>1</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>1</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>2</RvdsVP>
+            <RvdsMve>0</RvdsMve>
+            <RvdsCdeCp>0</RvdsCdeCp>
+            <hadIRAM2>1</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>2</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>4</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>1</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x40000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x98000</Size>
+              </IROM>
+              <XRAM>
+                <Type>1</Type>
+                <StartAddress>0x4000000</StartAddress>
+                <Size>0x8000</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x98000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x4000000</StartAddress>
+                <Size>0x8000</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x40100000</StartAddress>
+                <Size>0x4000</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x40000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x20040000</StartAddress>
+                <Size>0x4000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>4</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>3</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <uGnu>0</uGnu>
+            <useXO>0</useXO>
+            <v6Lang>3</v6Lang>
+            <v6LangP>3</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>.;.\board;..\..\Include</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <ClangAsOpt>1</ClangAsOpt>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x10000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile>.\RTE\Device\LPC55S69JBD64_cm33_core0\LPC55S69_cm33_core0_flash.scf</ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc>--diag_suppress=L6314</Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Source</GroupName>
+          <Files>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\main.c</FilePath>
+            </File>
+            <File>
+              <FileName>ser_num.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\ser_num.c</FilePath>
+            </File>
+            <File>
+              <FileName>USBD_User_CustomClass_0.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\USBD_User_CustomClass_0.c</FilePath>
+            </File>
+            <File>
+              <FileName>USBD_User_CDC_ACM_UART_0.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\USBD_User_CDC_ACM_UART_0.c</FilePath>
+            </File>
+            <File>
+              <FileName>USBD1_LPC55xxx.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\USBD1_LPC55xxx.c</FilePath>
+            </File>
+            <File>
+              <FileName>fsl_usart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\fsl_usart.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Documentation</GroupName>
+          <Files>
+            <File>
+              <FileName>README.md</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\README.md</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Board</GroupName>
+          <Files>
+            <File>
+              <FileName>clock_config.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\board\clock_config.c</FilePath>
+            </File>
+            <File>
+              <FileName>peripherals.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\board\peripherals.c</FilePath>
+            </File>
+            <File>
+              <FileName>pin_mux.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\board\pin_mux.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>CMSIS DAP</GroupName>
+          <Files>
+            <File>
+              <FileName>DAP_config.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\DAP_config.h</FilePath>
+            </File>
+            <File>
+              <FileName>DAP.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\Source\DAP.c</FilePath>
+            </File>
+            <File>
+              <FileName>JTAG_DP.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\Source\JTAG_DP.c</FilePath>
+            </File>
+            <File>
+              <FileName>SW_DP.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\Source\SW_DP.c</FilePath>
+            </File>
+            <File>
+              <FileName>SWO.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\Source\SWO.c</FilePath>
+            </File>
+            <File>
+              <FileName>UART.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\Source\UART.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::CMSIS</GroupName>
+        </Group>
+        <Group>
+          <GroupName>::CMSIS Driver</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>1</IncludeInBuild>
+              <AlwaysBuild>2</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+              <ComprImg>1</ComprImg>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <uSurpInc>2</uSurpInc>
+                <uC99>2</uC99>
+                <uGnu>2</uGnu>
+                <useXO>2</useXO>
+                <v6Lang>0</v6Lang>
+                <v6LangP>0</v6LangP>
+                <vShortEn>2</vShortEn>
+                <vShortWch>2</vShortWch>
+                <v6Lto>2</v6Lto>
+                <v6WtE>2</v6WtE>
+                <v6Rtti>2</v6Rtti>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <uSurpInc>2</uSurpInc>
+                <useXO>2</useXO>
+                <ClangAsOpt>0</ClangAsOpt>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+        </Group>
+        <Group>
+          <GroupName>::Device</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>1</IncludeInBuild>
+              <AlwaysBuild>2</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+              <ComprImg>1</ComprImg>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <uSurpInc>2</uSurpInc>
+                <uC99>2</uC99>
+                <uGnu>2</uGnu>
+                <useXO>2</useXO>
+                <v6Lang>0</v6Lang>
+                <v6LangP>0</v6LangP>
+                <vShortEn>2</vShortEn>
+                <vShortWch>2</vShortWch>
+                <v6Lto>2</v6Lto>
+                <v6WtE>2</v6WtE>
+                <v6Rtti>2</v6Rtti>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <uSurpInc>2</uSurpInc>
+                <useXO>2</useXO>
+                <ClangAsOpt>0</ClangAsOpt>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+        </Group>
+        <Group>
+          <GroupName>::USB</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <packages>
+      <filter>
+        <targetInfos/>
+      </filter>
+      <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.8.0">
+        <targetInfos>
+          <targetInfo name="MCU-LINK"/>
+        </targetInfos>
+      </package>
+      <package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.13.0">
+        <targetInfos>
+          <targetInfo name="MCU-LINK"/>
+        </targetInfos>
+      </package>
+      <package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0">
+        <targetInfos>
+          <targetInfo name="MCU-LINK" versionMatchMode="fixed"/>
+        </targetInfos>
+      </package>
+    </packages>
+    <apis>
+      <api Capiversion="2.01" Cclass="CMSIS Driver" Cgroup="USART" exclusive="0">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.3.0"/>
+        <targetInfos>
+          <targetInfo name="MCU-LINK"/>
+        </targetInfos>
+      </api>
+      <api Capiversion="2.01" Cclass="CMSIS Driver" Cgroup="USB Device" exclusive="0">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.3.0"/>
+        <targetInfos>
+          <targetInfo name="MCU-LINK"/>
+        </targetInfos>
+      </api>
+      <api Capiversion="2.1.2" Cclass="CMSIS" Cgroup="RTOS2" exclusive="1">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.2.0"/>
+        <targetInfos>
+          <targetInfo name="MCU-LINK"/>
+        </targetInfos>
+      </api>
+    </apis>
+    <components>
+      <component Capiversion="2.4.0" Cclass="CMSIS Driver" Cgroup="USART" Csub="Custom" Cvendor="ARM" Cversion="1.0.0" custom="1">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.8.0"/>
+        <targetInfos>
+          <targetInfo name="MCU-LINK"/>
+        </targetInfos>
+      </component>
+      <component Capiversion="2.3.0" Cclass="CMSIS Driver" Cgroup="USB Device" Csub="Custom" Cvendor="ARM" Cversion="1.0.0" custom="1">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.8.0"/>
+        <targetInfos>
+          <targetInfo name="MCU-LINK"/>
+        </targetInfos>
+      </component>
+      <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.5.0" condition="ARMv6_7_8-M Device">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.8.0"/>
+        <targetInfos>
+          <targetInfo name="MCU-LINK"/>
+        </targetInfos>
+      </component>
+      <component Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cvendor="ARM" Cversion="5.5.3" condition="RTOS2 RTX5">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.8.0"/>
+        <targetInfos>
+          <targetInfo name="MCU-LINK"/>
+        </targetInfos>
+      </component>
+      <component Cbundle="MDK-Plus" Cclass="USB" Cgroup="CORE" Cvariant="Release" Cvendor="Keil" Cversion="6.15.0" condition="USB Core">
+        <package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.13.0"/>
+        <targetInfos>
+          <targetInfo name="MCU-LINK"/>
+        </targetInfos>
+      </component>
+      <component Cbundle="MDK-Plus" Cclass="USB" Cgroup="Device" Cvendor="Keil" Cversion="6.15.0" condition="USB Core and Device Instance and Device Driver" maxInstances="4">
+        <package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.13.0"/>
+        <targetInfos>
+          <targetInfo name="MCU-LINK"/>
+        </targetInfos>
+      </component>
+      <component Cbundle="MDK-Plus" Cclass="USB" Cgroup="Device" Csub="CDC" Cvendor="Keil" Cversion="6.15.0" condition="USB Core and Device Instance and Device Driver" maxInstances="8">
+        <package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.13.0"/>
+        <targetInfos>
+          <targetInfo name="MCU-LINK"/>
+        </targetInfos>
+      </component>
+      <component Cbundle="MDK-Plus" Cclass="USB" Cgroup="Device" Csub="Custom Class" Cvendor="Keil" Cversion="6.15.0" condition="USB Core and Device Instance and Device Driver" maxInstances="4">
+        <package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.13.0"/>
+        <targetInfos>
+          <targetInfo name="MCU-LINK"/>
+        </targetInfos>
+      </component>
+      <component Capiversion="2.3.0" Cclass="CMSIS Driver" Cgroup="USART" Csub="flexcomm_usart_cmsis" Cvendor="NXP" Cversion="2.2.0" condition="device.LPC55S69_AND_CMSIS_Driver_Include.USART_AND_RTE_Device_AND_driver.flexcomm_usart_dma">
+        <package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
+        <targetInfos>
+          <targetInfo name="MCU-LINK"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="CMSIS" Csub="LPC55S69_system" Cvendor="NXP" Cversion="1.0.0" condition="device.LPC55S69_AND_device.LPC55S69_CMSIS">
+        <package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
+        <targetInfos>
+          <targetInfo name="MCU-LINK"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="SDK Drivers" Csub="clock" Cvendor="NXP" Cversion="2.3.3" condition="device.LPC55S69_AND__driver.power_OR_driver.power_s__AND_driver.common">
+        <package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
+        <targetInfos>
+          <targetInfo name="MCU-LINK"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="SDK Drivers" Csub="common" Cvendor="NXP" Cversion="2.3.0" condition="device.LPC55S69_AND_device.LPC55S69_CMSIS_AND_driver.clock_AND_driver.reset">
+        <package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
+        <targetInfos>
+          <targetInfo name="MCU-LINK"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="SDK Drivers" Csub="dma" Cvendor="NXP" Cversion="2.4.2" condition="device.LPC55S69_AND_driver.common">
+        <package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
+        <targetInfos>
+          <targetInfo name="MCU-LINK"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="SDK Drivers" Csub="flexcomm" Cvendor="NXP" Cversion="2.0.2" condition="device.LPC55S69_AND_driver.common">
+        <package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
+        <targetInfos>
+          <targetInfo name="MCU-LINK"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="SDK Drivers" Csub="gpio" Cvendor="NXP" Cversion="2.1.7" condition="device.LPC55S69_AND_driver.common">
+        <package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
+        <targetInfos>
+          <targetInfo name="MCU-LINK"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="SDK Drivers" Csub="iap1" Cvendor="NXP" Cversion="2.1.3" condition="device.LPC55S69_AND_driver.common">
+        <package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
+        <targetInfos>
+          <targetInfo name="MCU-LINK"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="SDK Drivers" Csub="iocon" Cvendor="NXP" Cversion="2.2.0" condition="device.LPC55S69_AND_driver.common">
+        <package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
+        <targetInfos>
+          <targetInfo name="MCU-LINK"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="SDK Drivers" Csub="lists" Cvendor="NXP" Cversion="1.0.0" condition="device.LPC55S69_AND_driver.common">
+        <package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
+        <targetInfos>
+          <targetInfo name="MCU-LINK"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="SDK Drivers" Csub="power" Cvendor="NXP" Cversion="2.0.0" condition="device.LPC55S69_AND_driver.common">
+        <package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
+        <targetInfos>
+          <targetInfo name="MCU-LINK"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="SDK Drivers" Csub="reset" Cvendor="NXP" Cversion="2.0.1" condition="device.LPC55S69_AND_driver.common">
+        <package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
+        <targetInfos>
+          <targetInfo name="MCU-LINK"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="SDK Drivers" Csub="usart" Cvendor="NXP" Cversion="2.6.0" condition="device.LPC55S69_AND_driver.flexcomm">
+        <package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
+        <targetInfos>
+          <targetInfo excluded="1" name="MCU-LINK" versionMatchMode=""/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="SDK Drivers" Csub="usart_adapter" Cvendor="NXP" Cversion="1.0.0" condition="device.LPC55S69_AND_driver.common_AND_driver.flexcomm_AND_driver.flexcomm_usart">
+        <package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
+        <targetInfos>
+          <targetInfo name="MCU-LINK"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="SDK Drivers" Csub="usart_dma" Cvendor="NXP" Cversion="2.6.0" condition="device.LPC55S69_AND_driver.flexcomm_AND_driver.flexcomm_usart_AND_driver.lpc_dma">
+        <package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
+        <targetInfos>
+          <targetInfo name="MCU-LINK"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="SDK Project Template" Csub="RTE_Device" Cvendor="NXP" Cversion="1.0.0" condition="device.LPC55S69_AND_driver.lpc_dma">
+        <package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
+        <targetInfos>
+          <targetInfo name="MCU-LINK"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="SDK Utilities" Csub="assert" Cvendor="NXP" Cversion="1.0.0" condition="device.LPC55S69_AND_utility.debug_console">
+        <package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
+        <targetInfos>
+          <targetInfo name="MCU-LINK"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="SDK Utilities" Csub="debug_console" Cvendor="NXP" Cversion="1.0.0" condition="device.LPC55S69_AND_component.serial_manager_AND_driver.common">
+        <package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
+        <targetInfos>
+          <targetInfo name="MCU-LINK"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="SDK Utilities" Csub="serial_manager" Cvendor="NXP" Cversion="1.0.1" condition="device.LPC55S69_AND__component.serial_manager_swo_OR_component.serial_manager_uart_OR_component.serial_manager_virtual__AND_component.lists_AND_driver.common">
+        <package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
+        <targetInfos>
+          <targetInfo name="MCU-LINK"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="SDK Utilities" Csub="serial_manager_uart" Cvendor="NXP" Cversion="1.0.0" condition="device.LPC55S69_AND_component.serial_manager_AND_component.usart_adapter_AND_driver.flexcomm_usart">
+        <package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
+        <targetInfos>
+          <targetInfo name="MCU-LINK"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="Startup" Cvendor="NXP" Cversion="1.1.0" condition="device.LPC55S69_AND_CMSIS_Include_core_cm_AND__armclang_OR_iar__AND_device.LPC55S69_system">
+        <package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
+        <targetInfos>
+          <targetInfo name="MCU-LINK"/>
+        </targetInfos>
+      </component>
+    </components>
+    <files>
+      <file attr="config" category="source" name="CMSIS\RTOS2\RTX\Config\RTX_Config.c" version="5.1.1">
+        <instance index="0">RTE\CMSIS\RTX_Config.c</instance>
+        <component Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cvendor="ARM" Cversion="5.5.3" condition="RTOS2 RTX5"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.8.0"/>
+        <targetInfos>
+          <targetInfo name="MCU-LINK"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="header" name="CMSIS\RTOS2\RTX\Config\RTX_Config.h" version="5.5.2">
+        <instance index="0">RTE\CMSIS\RTX_Config.h</instance>
+        <component Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cvendor="ARM" Cversion="5.5.3" condition="RTOS2 RTX5"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.8.0"/>
+        <targetInfos>
+          <targetInfo name="MCU-LINK"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="linkerScript" condition="core_id.cm33_core0_AND_core_type.cm33_AND_mdk" name="arm\LPC55S69_cm33_core0_flash.scf" version="1.1.0">
+        <instance index="0">RTE\Device\LPC55S69JBD64_cm33_core0\LPC55S69_cm33_core0_flash.scf</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="NXP" Cversion="1.1.0" condition="device.LPC55S69_AND_CMSIS_Include_core_cm_AND__armclang_OR_iar__AND_device.LPC55S69_system"/>
+        <package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
+        <targetInfos>
+          <targetInfo name="MCU-LINK"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="linkerScript" condition="core_id.cm33_core0_AND_core_type.cm33_AND_mdk" name="arm\LPC55S69_cm33_core0_flash_ns.scf" version="1.1.0">
+        <instance index="0">RTE\Device\LPC55S69JBD64_cm33_core0\LPC55S69_cm33_core0_flash_ns.scf</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="NXP" Cversion="1.1.0" condition="device.LPC55S69_AND_CMSIS_Include_core_cm_AND__armclang_OR_iar__AND_device.LPC55S69_system"/>
+        <package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
+        <targetInfos>
+          <targetInfo name="MCU-LINK"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="linkerScript" condition="core_id.cm33_core0_AND_core_type.cm33_AND_mdk" name="arm\LPC55S69_cm33_core0_flash_s.scf" version="1.1.0">
+        <instance index="0">RTE\Device\LPC55S69JBD64_cm33_core0\LPC55S69_cm33_core0_flash_s.scf</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="NXP" Cversion="1.1.0" condition="device.LPC55S69_AND_CMSIS_Include_core_cm_AND__armclang_OR_iar__AND_device.LPC55S69_system"/>
+        <package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
+        <targetInfos>
+          <targetInfo name="MCU-LINK"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="linkerScript" condition="core_id.cm33_core0_AND_core_type.cm33_AND_mdk" name="arm\LPC55S69_cm33_core0_ram.scf" version="1.1.0">
+        <instance index="0">RTE\Device\LPC55S69JBD64_cm33_core0\LPC55S69_cm33_core0_ram.scf</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="NXP" Cversion="1.1.0" condition="device.LPC55S69_AND_CMSIS_Include_core_cm_AND__armclang_OR_iar__AND_device.LPC55S69_system"/>
+        <package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
+        <targetInfos>
+          <targetInfo name="MCU-LINK"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="header" name="template\RTE_Device.h" version="1.0.0">
+        <instance index="0">RTE\Device\LPC55S69JBD64_cm33_core0\RTE_Device.h</instance>
+        <component Cclass="Device" Cgroup="SDK Project Template" Csub="RTE_Device" Cvendor="NXP" Cversion="1.0.0" condition="device.LPC55S69_AND_driver.lpc_dma"/>
+        <package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
+        <targetInfos>
+          <targetInfo name="MCU-LINK"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="sourceAsm" condition="core_id.cm33_core0_AND_core_type.cm33_AND_mdk" name="arm\startup_LPC55S69_cm33_core0.S" version="1.1.0">
+        <instance index="0">RTE\Device\LPC55S69JBD64_cm33_core0\startup_LPC55S69_cm33_core0.S</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="NXP" Cversion="1.1.0" condition="device.LPC55S69_AND_CMSIS_Include_core_cm_AND__armclang_OR_iar__AND_device.LPC55S69_system"/>
+        <package name="LPC55S69_DFP" schemaVersion="1.4" url="https://mcuxpresso.nxp.com/cmsis_pack/repo/" vendor="NXP" version="13.1.0"/>
+        <targetInfos>
+          <targetInfo name="MCU-LINK"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="source" name="USB\Config\USBD_Config.c" version="5.2.0">
+        <instance index="0">RTE\USB\USBD_Config_0.c</instance>
+        <component Cbundle="MDK-Plus" Cclass="USB" Cgroup="Device" Cvendor="Keil" Cversion="6.15.0" condition="USB Core and Device Instance and Device Driver" maxInstances="4"/>
+        <package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.13.0"/>
+        <targetInfos>
+          <targetInfo name="MCU-LINK"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="header" name="USB\Config\USBD_Config_CDC.h" version="5.2.0">
+        <instance index="0">RTE\USB\USBD_Config_CDC_0.h</instance>
+        <component Cbundle="MDK-Plus" Cclass="USB" Cgroup="Device" Csub="CDC" Cvendor="Keil" Cversion="6.15.0" condition="USB Core and Device Instance and Device Driver" maxInstances="8"/>
+        <package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.13.0"/>
+        <targetInfos>
+          <targetInfo name="MCU-LINK"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="header" name="USB\Config\USBD_Config_CustomClass.h" version="5.2.0">
+        <instance index="0">RTE\USB\USBD_Config_CustomClass_0.h</instance>
+        <component Cbundle="MDK-Plus" Cclass="USB" Cgroup="Device" Csub="Custom Class" Cvendor="Keil" Cversion="6.15.0" condition="USB Core and Device Instance and Device Driver" maxInstances="4"/>
+        <package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.13.0"/>
+        <targetInfos>
+          <targetInfo name="MCU-LINK"/>
+        </targetInfos>
+      </file>
+    </files>
+  </RTE>
+
+  <LayerInfo>
+    <Layers>
+      <Layer>
+        <LayName>CMSIS_DAP</LayName>
+        <LayPrjMark>1</LayPrjMark>
+      </Layer>
+    </Layers>
+  </LayerInfo>
+
+</Project>

CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/DAP_config.h → CMSIS/DAP/Firmware/Examples/MCU-LINK/DAP_config.h

@@ -17,11 +17,11 @@
  *
  * ----------------------------------------------------------------------
  *
- * $Date:        16. June 2021
+ * $Date:        15. September 2021
  * $Revision:    V2.1.0
  *
- * Project:      CMSIS-DAP Examples LPC-Link2
- * Title:        DAP_config.h CMSIS-DAP Configuration File for LPC-Link2
+ * Project:      CMSIS-DAP Examples MCU-LINK
+ * Title:        DAP_config.h CMSIS-DAP Configuration File for MCU-LINK
  *
  *---------------------------------------------------------------------------*/
 
@@ -30,9 +30,9 @@
 
 
 //**************************************************************************************************
-/** 
+/**
 \defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information
-\ingroup DAP_ConfigIO_gr 
+\ingroup DAP_ConfigIO_gr
 @{
 Provides definitions about the hardware and configuration of the Debug Unit.
 
@@ -51,15 +51,20 @@ This information includes:
 #include "device.h"                             // Debug Unit Cortex-M Processor Header File
 #endif
 
+#include "pin_mux.h"
+#include "fsl_gpio.h"
+
+#include "ser_num.h"
+
 /// Processor Clock of the Cortex-M MCU used in the Debug Unit.
 /// This value is used to calculate the SWD/JTAG clock speed.
-#define CPU_CLOCK               180000000U      ///< Specifies the CPU Clock in Hz.
+#define CPU_CLOCK               150000000U      ///< Specifies the CPU Clock in Hz.
 
 /// Number of processor cycles for I/O Port write operations.
 /// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
 /// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors
 /// require 2 processor cycles for a I/O Port Write operation.  If the Debug Unit uses
-/// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be 
+/// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
 /// required.
 #define IO_PORT_WRITE_CYCLES    2U              ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0.
 
@@ -88,23 +93,23 @@ This information includes:
 /// This configuration settings is used to optimize the communication performance with the
 /// debugger and depends on the USB peripheral. Typical vales are 64 for Full-speed USB HID or WinUSB,
 /// 1024 for High-speed USB HID and 512 for High-speed USB WinUSB.
-#define DAP_PACKET_SIZE         1024U           ///< Specifies Packet Size in bytes.
+#define DAP_PACKET_SIZE         512U            ///< Specifies Packet Size in bytes.
 
 /// Maximum Package Buffers for Command and Response data.
 /// This configuration settings is used to optimize the communication performance with the
 /// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
 /// setting can be reduced (valid range is 1 .. 255).
-#define DAP_PACKET_COUNT        4U              ///< Specifies number of packets buffered.
+#define DAP_PACKET_COUNT        8U              ///< Specifies number of packets buffered.
 
 /// Indicate that UART Serial Wire Output (SWO) trace is available.
 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
 #define SWO_UART                1               ///< SWO UART:  1 = available, 0 = not available.
 
 /// USART Driver instance number for the UART SWO.
-#define SWO_UART_DRIVER         1               ///< USART Driver instance number (Driver_USART#).
+#define SWO_UART_DRIVER         3               ///< USART Driver instance number (Driver_USART#).
 
 /// Maximum SWO UART Baudrate.
-#define SWO_UART_MAX_BAUDRATE   10000000U       ///< SWO UART Maximum Baudrate in Hz.
+#define SWO_UART_MAX_BAUDRATE   9000000U        ///< SWO UART Maximum Baudrate in Hz.
 
 /// Indicate that Manchester Serial Wire Output (SWO) trace is available.
 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
@@ -114,14 +119,14 @@ This information includes:
 #define SWO_BUFFER_SIZE         8192U           ///< SWO Trace Buffer Size in bytes (must be 2^n).
 
 /// SWO Streaming Trace.
-#define SWO_STREAM              0               ///< SWO Streaming Trace: 1 = available, 0 = not available.
+#define SWO_STREAM              1               ///< SWO Streaming Trace: 1 = available, 0 = not available.
 
 /// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET.
-#define TIMESTAMP_CLOCK         180000000U      ///< Timestamp clock in Hz (0 = timestamps not supported).
+#define TIMESTAMP_CLOCK         150000000U      ///< Timestamp clock in Hz (0 = timestamps not supported).
 
 /// Indicate that UART Communication Port is available.
 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
-#define DAP_UART                0               ///< DAP UART:  1 = available, 0 = not available.
+#define DAP_UART                1               ///< DAP UART:  1 = available, 0 = not available.
 
 /// USART Driver instance number for the UART Communication Port.
 #define DAP_UART_DRIVER         0               ///< USART Driver instance number (Driver_USART#).
@@ -134,7 +139,7 @@ This information includes:
 
 /// Indicate that UART Communication via USB COM Port is available.
 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
-#define DAP_UART_USB_COM_PORT   0               ///< USB COM Port:  1 = available, 0 = not available.
+#define DAP_UART_USB_COM_PORT   1               ///< USB COM Port:  1 = available, 0 = not available.
 
 /// Debug Unit is connected to fixed Target Device.
 /// The Debug Unit may be part of an evaluation board and always connected to a fixed
@@ -178,8 +183,16 @@ __STATIC_INLINE uint8_t DAP_GetProductString (char *str) {
 \return String length (including terminating NULL character) or 0 (no string).
 */
 __STATIC_INLINE uint8_t DAP_GetSerNumString (char *str) {
-  (void)str;
-  return (0U);
+  uint8_t len = 0U;
+  char *ser_num;
+
+  ser_num = GetSerialNum();
+  if (ser_num != NULL) {
+    strcpy(str, ser_num);
+    len = (uint8_t)(strlen(ser_num) + 1U);
+  }
+
+  return (len);
 }
 
 /** Get Target Device Vendor string.
@@ -261,70 +274,19 @@ __STATIC_INLINE uint8_t DAP_GetProductFirmwareVersionString (char *str) {
 
 ///@}
 
-
-// LPC43xx peripheral register bit masks (used by macros)
-#define CCU_CLK_CFG_RUN         (1U << 0)
-#define CCU_CLK_CFG_AUTO        (1U << 1)
-#define CCU_CLK_STAT_RUN        (1U << 0)
-#define SCU_SFS_EPD             (1U << 3)
-#define SCU_SFS_EPUN            (1U << 4)
-#define SCU_SFS_EHS             (1U << 5)
-#define SCU_SFS_EZI             (1U << 6)
-#define SCU_SFS_ZIF             (1U << 7)
-
-
 // Debug Port I/O Pins
-
-// SWCLK/TCK Pin                P1_17: GPIO0[12]
-#define PIN_SWCLK_TCK_PORT      0
-#define PIN_SWCLK_TCK_BIT       12
-
-// SWDIO/TMS Pin                P1_6:  GPIO1[9]
-#define PIN_SWDIO_TMS_PORT      1
-#define PIN_SWDIO_TMS_BIT       9
-
-// SWDIO Output Enable Pin      P1_5:  GPIO1[8]
-#define PIN_SWDIO_OE_PORT       1
-#define PIN_SWDIO_OE_BIT        8
-
-// TDI Pin                      P1_18: GPIO0[13]
-#define PIN_TDI_PORT            0
-#define PIN_TDI_BIT             13
-
-// TDO Pin                      P1_14: GPIO1[7]
-#define PIN_TDO_PORT            1
-#define PIN_TDO_BIT             7
-
-// nTRST Pin                    Not available
-#define PIN_nTRST_PORT
-#define PIN_nTRST_BIT
-
-// nRESET Pin                   P2_5:  GPIO5[5]
-#define PIN_nRESET_PORT         5
-#define PIN_nRESET_BIT          5
-
-// nRESET Output Enable Pin     P2_6:  GPIO5[6]
-#define PIN_nRESET_OE_PORT      5
-#define PIN_nRESET_OE_BIT       6
-
-
-// Debug Unit LEDs
-
-// Connected LED                P1_1: GPIO0[8]
-#define LED_CONNECTED_PORT      0
-#define LED_CONNECTED_BIT       8
-
-// Target Running LED           Not available
-
+//SWO/TDO
+#define PIN_SWO_TDO_PORT  (0U)
+#define PIN_SWO_TDO_PIN   (3U)
 
 //**************************************************************************************************
-/** 
+/**
 \defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access
-\ingroup DAP_ConfigIO_gr 
+\ingroup DAP_ConfigIO_gr
 @{
 
 Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode
-and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug 
+and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug
 interface of a device. The following I/O Pins are provided:
 
 JTAG I/O Pin                 | SWD I/O Pin          | CMSIS-DAP Hardware pin mode
@@ -332,19 +294,19 @@ JTAG I/O Pin                 | SWD I/O Pin          | CMSIS-DAP Hardware pin mod
 TCK: Test Clock              | SWCLK: Clock         | Output Push/Pull
 TMS: Test Mode Select        | SWDIO: Data I/O      | Output Push/Pull; Input (for receiving data)
 TDI: Test Data Input         |                      | Output Push/Pull
-TDO: Test Data Output        |                      | Input             
+TDO: Test Data Output        |                      | Input
 nTRST: Test Reset (optional) |                      | Output Open Drain with pull-up resistor
 nRESET: Device Reset         | nRESET: Device Reset | Output Open Drain with pull-up resistor
 
 
 DAP Hardware I/O Pin Access Functions
 -------------------------------------
-The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to 
-these I/O Pins. 
+The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to
+these I/O Pins.
 
 For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only.
-This functions are provided to achieve faster I/O that is possible with some advanced GPIO 
-peripherals that can independently write/read a single I/O pin without affecting any other pins 
+This functions are provided to achieve faster I/O that is possible with some advanced GPIO
+peripherals that can independently write/read a single I/O pin without affecting any other pins
 of the same I/O port. The following SWDIO I/O Pin functions are provided:
  - \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware.
  - \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware.
@@ -355,29 +317,58 @@ of the same I/O port. The following SWDIO I/O Pin functions are provided:
 
 // Configure DAP I/O pins ------------------------------
 
-//   LPC-Link2 HW uses buffers for debug port pins. Therefore it is not
-//   possible to disable outputs SWCLK/TCK, TDI and they are left active.
-//   Only SWDIO/TMS output can be disabled but it is also left active.
-//   nRESET is configured for open drain mode.
-
 /** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET.
 Configures the DAP Hardware I/O pins for JTAG mode:
  - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level.
  - TDO to input mode.
-*/ 
+*/
 __STATIC_INLINE void PORT_JTAG_SETUP (void) {
-  LPC_GPIO_PORT->MASK[PIN_SWDIO_TMS_PORT] = 0U;
-  LPC_GPIO_PORT->MASK[PIN_TDI_PORT] = ~(1U << PIN_TDI_BIT);
+
+  // TCK
+  DBGIF_TCK_SWCLK_GPIO->SET[DBGIF_TCK_SWCLK_PORT]    = (1U << DBGIF_TCK_SWCLK_PIN);
+  DBGIF_TCK_SWCLK_GPIO->DIRSET[DBGIF_TCK_SWCLK_PORT] = (1U << DBGIF_TCK_SWCLK_PIN);
+
+  // TDI
+  DBGIF_TDI_GPIO->SET[DBGIF_TDI_PORT]    = (1U << DBGIF_TDI_PIN);
+  DBGIF_TDI_GPIO->DIRSET[DBGIF_TDI_PORT] = (1U << DBGIF_TDI_PIN);
+
+  // TMS
+  DBGIF_TMS_SWDIO_GPIO->SET[DBGIF_TMS_SWDIO_PORT]           = (1U << DBGIF_TMS_SWDIO_PIN);
+  DBGIF_TMS_SWDIO_GPIO->DIRSET[DBGIF_TMS_SWDIO_PORT]        = (1U << DBGIF_TMS_SWDIO_PIN);
+  DBGIF_TMS_SWDIO_TXEN_GPIO->SET[DBGIF_TMS_SWDIO_TXEN_PORT] = (1U << DBGIF_TMS_SWDIO_TXEN_PIN);
+
+  // nRESET
+  DBGIF_RESET_GPIO->SET[DBGIF_RESET_PORT]           = (1U << DBGIF_RESET_PIN);
+  DBGIF_RESET_GPIO->DIRSET[DBGIF_RESET_PORT]        = (1U << DBGIF_RESET_PIN);
+  DBGIF_RESET_TXEN_GPIO->SET[DBGIF_RESET_TXEN_PORT] = (1U << DBGIF_RESET_TXEN_PIN);
+
+  // TDO
+  GPIO->DIRCLR[PIN_SWO_TDO_PORT] = (1U << PIN_SWO_TDO_PIN);
 }
- 
+
 /** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
 Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
  - SWCLK, SWDIO, nRESET to output mode and set to default high level.
  - TDI, nTRST to HighZ mode (pins are unused in SWD mode).
-*/ 
+*/
 __STATIC_INLINE void PORT_SWD_SETUP (void) {
-  LPC_GPIO_PORT->MASK[PIN_TDI_PORT] = 0U;
-  LPC_GPIO_PORT->MASK[PIN_SWDIO_TMS_PORT] = ~(1U << PIN_SWDIO_TMS_BIT);
+
+  // SWCLK
+  DBGIF_TCK_SWCLK_GPIO->SET[DBGIF_TCK_SWCLK_PORT]    = (1U << DBGIF_TCK_SWCLK_PIN);
+  DBGIF_TCK_SWCLK_GPIO->DIRSET[DBGIF_TCK_SWCLK_PORT] = (1U << DBGIF_TCK_SWCLK_PIN);
+
+  // SWDIO
+  DBGIF_TMS_SWDIO_GPIO->SET[DBGIF_TMS_SWDIO_PORT]           = (1U << DBGIF_TMS_SWDIO_PIN);
+  DBGIF_TMS_SWDIO_GPIO->DIRSET[DBGIF_TMS_SWDIO_PORT]        = (1U << DBGIF_TMS_SWDIO_PIN);
+  DBGIF_TMS_SWDIO_TXEN_GPIO->SET[DBGIF_TMS_SWDIO_TXEN_PORT] = (1U << DBGIF_TMS_SWDIO_TXEN_PIN);
+
+  // nRESET
+  DBGIF_RESET_GPIO->SET[DBGIF_RESET_PORT]           = (1U << DBGIF_RESET_PIN);
+  DBGIF_RESET_GPIO->DIRSET[DBGIF_RESET_PORT]        = (1U << DBGIF_RESET_PIN);
+  DBGIF_RESET_TXEN_GPIO->SET[DBGIF_RESET_TXEN_PORT] = (1U << DBGIF_RESET_TXEN_PIN);
+ 
+  // TDI
+  DBGIF_TDI_GPIO->DIRCLR[DBGIF_TDI_PORT] = (1U << DBGIF_TDI_PIN);
 }
 
 /** Disable JTAG/SWD I/O Pins.
@@ -385,12 +376,23 @@ Disables the DAP Hardware I/O pins which configures:
  - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
 */
 __STATIC_INLINE void PORT_OFF (void) {
-  LPC_GPIO_PORT->SET[PIN_SWCLK_TCK_PORT]  =  (1U << PIN_SWCLK_TCK_BIT);
-  LPC_GPIO_PORT->SET[PIN_SWDIO_TMS_PORT]  =  (1U << PIN_SWDIO_TMS_BIT);
-  LPC_GPIO_PORT->SET[PIN_SWDIO_OE_PORT]   =  (1U << PIN_SWDIO_OE_BIT);
-  LPC_GPIO_PORT->SET[PIN_TDI_PORT]        =  (1U << PIN_TDI_BIT);
-  LPC_GPIO_PORT->DIR[PIN_nRESET_PORT]    &= ~(1U << PIN_nRESET_BIT);
-  LPC_GPIO_PORT->CLR[PIN_nRESET_OE_PORT]  =  (1U << PIN_nRESET_OE_BIT);
+
+  // TCK/SWCLK
+  DBGIF_TCK_SWCLK_GPIO->DIRCLR[DBGIF_TCK_SWCLK_PORT] = (1U << DBGIF_TCK_SWCLK_PIN);
+
+  // TMS/SWDIO
+  DBGIF_TMS_SWDIO_TXEN_GPIO->CLR[DBGIF_TMS_SWDIO_TXEN_PORT] = (1U << DBGIF_TMS_SWDIO_TXEN_PIN);
+  DBGIF_TMS_SWDIO_GPIO->DIRCLR[DBGIF_TMS_SWDIO_PORT]        = (1U << DBGIF_TMS_SWDIO_PIN);
+
+  // nRESET
+  DBGIF_RESET_TXEN_GPIO->CLR[DBGIF_RESET_TXEN_PORT] = (1U << DBGIF_RESET_TXEN_PIN);
+  DBGIF_RESET_GPIO->DIRCLR[DBGIF_RESET_PORT]        = (1U << DBGIF_RESET_PIN);
+  
+  // TDI
+  DBGIF_TDI_GPIO->DIRCLR[DBGIF_TDI_PORT] = (1U << DBGIF_TDI_PIN);
+  
+  // TDO
+  GPIO->DIRCLR[PIN_SWO_TDO_PORT] = (1U << PIN_SWO_TDO_PIN);
 }
 
 
@@ -400,21 +402,21 @@ __STATIC_INLINE void PORT_OFF (void) {
 \return Current status of the SWCLK/TCK DAP hardware I/O pin.
 */
 __STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN  (void) {
-  return ((LPC_GPIO_PORT->PIN[PIN_SWCLK_TCK_PORT] >> PIN_SWCLK_TCK_BIT) & 1U);
+  return ((DBGIF_TCK_SWCLK_GPIO->PIN[DBGIF_TCK_SWCLK_PORT] >> DBGIF_TCK_SWCLK_PIN) & 1U);
 }
 
 /** SWCLK/TCK I/O pin: Set Output to High.
 Set the SWCLK/TCK DAP hardware I/O pin to high level.
 */
 __STATIC_FORCEINLINE void     PIN_SWCLK_TCK_SET (void) {
-  LPC_GPIO_PORT->SET[PIN_SWCLK_TCK_PORT] = 1U << PIN_SWCLK_TCK_BIT;
+  DBGIF_TCK_SWCLK_GPIO->SET[DBGIF_TCK_SWCLK_PORT] = (1U << DBGIF_TCK_SWCLK_PIN);
 }
 
 /** SWCLK/TCK I/O pin: Set Output to Low.
 Set the SWCLK/TCK DAP hardware I/O pin to low level.
 */
 __STATIC_FORCEINLINE void     PIN_SWCLK_TCK_CLR (void) {
-  LPC_GPIO_PORT->CLR[PIN_SWCLK_TCK_PORT] = 1U << PIN_SWCLK_TCK_BIT;
+  DBGIF_TCK_SWCLK_GPIO->CLR[DBGIF_TCK_SWCLK_PORT] = (1U << DBGIF_TCK_SWCLK_PIN);
 }
 
 
@@ -424,35 +426,35 @@ __STATIC_FORCEINLINE void     PIN_SWCLK_TCK_CLR (void) {
 \return Current status of the SWDIO/TMS DAP hardware I/O pin.
 */
 __STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN  (void) {
-  return ((LPC_GPIO_PORT->PIN[PIN_SWDIO_TMS_PORT] >> PIN_SWDIO_TMS_BIT) & 1U);
+  return ((DBGIF_TMS_SWDIO_GPIO->PIN[DBGIF_TMS_SWDIO_PORT] >> DBGIF_TMS_SWDIO_PIN) & 1U);
 }
 
 /** SWDIO/TMS I/O pin: Set Output to High.
 Set the SWDIO/TMS DAP hardware I/O pin to high level.
 */
 __STATIC_FORCEINLINE void     PIN_SWDIO_TMS_SET (void) {
-  LPC_GPIO_PORT->SET[PIN_SWDIO_TMS_PORT] = 1U << PIN_SWDIO_TMS_BIT;
+  DBGIF_TMS_SWDIO_GPIO->SET[DBGIF_TMS_SWDIO_PORT] = (1U << DBGIF_TMS_SWDIO_PIN);
 }
 
 /** SWDIO/TMS I/O pin: Set Output to Low.
 Set the SWDIO/TMS DAP hardware I/O pin to low level.
 */
 __STATIC_FORCEINLINE void     PIN_SWDIO_TMS_CLR (void) {
-  LPC_GPIO_PORT->CLR[PIN_SWDIO_TMS_PORT] = 1U << PIN_SWDIO_TMS_BIT;
+  DBGIF_TMS_SWDIO_GPIO->CLR[DBGIF_TMS_SWDIO_PORT] = (1U << DBGIF_TMS_SWDIO_PIN);
 }
 
 /** SWDIO I/O pin: Get Input (used in SWD mode only).
 \return Current status of the SWDIO DAP hardware I/O pin.
 */
 __STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN      (void) {
-  return (LPC_GPIO_PORT->MPIN[PIN_SWDIO_TMS_PORT] >> PIN_SWDIO_TMS_BIT);
+  return (DBGIF_TMS_SWDIO_GPIO->B[DBGIF_TMS_SWDIO_PORT][DBGIF_TMS_SWDIO_PIN]);
 }
 
 /** SWDIO I/O pin: Set Output (used in SWD mode only).
 \param bit Output value for the SWDIO DAP hardware I/O pin.
 */
 __STATIC_FORCEINLINE void     PIN_SWDIO_OUT     (uint32_t bit) {
-  LPC_GPIO_PORT->MPIN[PIN_SWDIO_TMS_PORT] = bit << PIN_SWDIO_TMS_BIT;
+  DBGIF_TMS_SWDIO_GPIO->B[DBGIF_TMS_SWDIO_PORT][DBGIF_TMS_SWDIO_PIN] = bit;
 }
 
 /** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
@@ -460,7 +462,8 @@ Configure the SWDIO DAP hardware I/O pin to output mode. This function is
 called prior \ref PIN_SWDIO_OUT function calls.
 */
 __STATIC_FORCEINLINE void     PIN_SWDIO_OUT_ENABLE  (void) {
-  LPC_GPIO_PORT->SET[PIN_SWDIO_OE_PORT] = 1U << PIN_SWDIO_OE_BIT;
+  DBGIF_TMS_SWDIO_GPIO->DIRSET[DBGIF_TMS_SWDIO_PORT]        = (1U << DBGIF_TMS_SWDIO_PIN);
+  DBGIF_TMS_SWDIO_TXEN_GPIO->SET[DBGIF_TMS_SWDIO_TXEN_PORT] = (1U << DBGIF_TMS_SWDIO_TXEN_PIN);
 }
 
 /** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
@@ -468,7 +471,8 @@ Configure the SWDIO DAP hardware I/O pin to input mode. This function is
 called prior \ref PIN_SWDIO_IN function calls.
 */
 __STATIC_FORCEINLINE void     PIN_SWDIO_OUT_DISABLE (void) {
-  LPC_GPIO_PORT->CLR[PIN_SWDIO_OE_PORT] = 1U << PIN_SWDIO_OE_BIT;
+  DBGIF_TMS_SWDIO_TXEN_GPIO->CLR[DBGIF_TMS_SWDIO_TXEN_PORT] = (1U << DBGIF_TMS_SWDIO_TXEN_PIN);
+  DBGIF_TMS_SWDIO_GPIO->DIRCLR[DBGIF_TMS_SWDIO_PORT]        = (1U << DBGIF_TMS_SWDIO_PIN);
 }
 
 
@@ -478,14 +482,14 @@ __STATIC_FORCEINLINE void     PIN_SWDIO_OUT_DISABLE (void) {
 \return Current status of the TDI DAP hardware I/O pin.
 */
 __STATIC_FORCEINLINE uint32_t PIN_TDI_IN  (void) {
-  return ((LPC_GPIO_PORT->PIN [PIN_TDI_PORT] >> PIN_TDI_BIT) & 1U);
+  return (DBGIF_TDI_GPIO->B[DBGIF_TDI_PORT][DBGIF_TDI_PIN]);
 }
 
 /** TDI I/O pin: Set Output.
 \param bit Output value for the TDI DAP hardware I/O pin.
 */
 __STATIC_FORCEINLINE void     PIN_TDI_OUT (uint32_t bit) {
-  LPC_GPIO_PORT->MPIN[PIN_TDI_PORT] = bit << PIN_TDI_BIT;
+  DBGIF_TDI_GPIO->B[DBGIF_TDI_PORT][DBGIF_TDI_PIN] = bit;
 }
 
 
@@ -495,7 +499,8 @@ __STATIC_FORCEINLINE void     PIN_TDI_OUT (uint32_t bit) {
 \return Current status of the TDO DAP hardware I/O pin.
 */
 __STATIC_FORCEINLINE uint32_t PIN_TDO_IN  (void) {
-  return ((LPC_GPIO_PORT->PIN[PIN_TDO_PORT] >> PIN_TDO_BIT) & 1U);
+  return (GPIO->B[PIN_SWO_TDO_PORT][PIN_SWO_TDO_PIN]);
+
 }
 
 
@@ -524,7 +529,7 @@ __STATIC_FORCEINLINE void     PIN_nTRST_OUT  (uint32_t bit) {
 \return Current status of the nRESET DAP hardware I/O pin.
 */
 __STATIC_FORCEINLINE uint32_t PIN_nRESET_IN  (void) {
-  return ((LPC_GPIO_PORT->PIN[PIN_nRESET_PORT] >> PIN_nRESET_BIT) & 1U);
+  return ((DBGIF_RESET_GPIO->PIN[DBGIF_RESET_PORT] >> DBGIF_RESET_PIN) & 1U);
 }
 
 /** nRESET I/O pin: Set Output.
@@ -534,11 +539,13 @@ __STATIC_FORCEINLINE uint32_t PIN_nRESET_IN  (void) {
 */
 __STATIC_FORCEINLINE void     PIN_nRESET_OUT (uint32_t bit) {
   if (bit) {
-    LPC_GPIO_PORT->DIR[PIN_nRESET_PORT]    &= ~(1U << PIN_nRESET_BIT);
-    LPC_GPIO_PORT->CLR[PIN_nRESET_OE_PORT]  =  (1U << PIN_nRESET_OE_BIT);
+    DBGIF_RESET_GPIO->SET[DBGIF_RESET_PORT]           = (1U << DBGIF_RESET_PIN);
+    DBGIF_RESET_TXEN_GPIO->CLR[DBGIF_RESET_TXEN_PORT] = (1U << DBGIF_RESET_TXEN_PIN);
+    DBGIF_RESET_GPIO->DIRCLR[DBGIF_RESET_PORT]        = (1U << DBGIF_RESET_PIN);
   } else {
-    LPC_GPIO_PORT->SET[PIN_nRESET_OE_PORT]  =  (1U << PIN_nRESET_OE_BIT);
-    LPC_GPIO_PORT->DIR[PIN_nRESET_PORT]    |=  (1U << PIN_nRESET_BIT);
+    DBGIF_RESET_GPIO->CLR[DBGIF_RESET_PORT]           = (1U << DBGIF_RESET_PIN);
+    DBGIF_RESET_GPIO->DIRSET[DBGIF_RESET_PORT]        = (1U << DBGIF_RESET_PIN);
+    DBGIF_RESET_TXEN_GPIO->SET[DBGIF_RESET_TXEN_PORT] = (1U << DBGIF_RESET_TXEN_PIN);
   }
 }
 
@@ -564,7 +571,11 @@ It is recommended to provide the following LEDs for status indication:
            - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
 */
 __STATIC_INLINE void LED_CONNECTED_OUT (uint32_t bit) {
-  LPC_GPIO_PORT->B[32*LED_CONNECTED_PORT + LED_CONNECTED_BIT] = (uint8_t)bit;
+  if (bit) {
+    LED1_GPIO->CLR[LED1_PORT] = (1U << LED1_PIN);
+  } else {
+    LED1_GPIO->SET[LED1_PORT] = (1U << LED1_PIN);
+  }
 }
 
 /** Debug Unit: Set status Target Running LED.
@@ -581,13 +592,13 @@ __STATIC_INLINE void LED_RUNNING_OUT (uint32_t bit) {
 
 
 //**************************************************************************************************
-/** 
+/**
 \defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp
 \ingroup DAP_ConfigIO_gr
 @{
 Access function for Test Domain Timer.
 
-The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By 
+The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By
 default, the DWT timer is used.  The frequency of this timer is configured with \ref TIMESTAMP_CLOCK.
 
 */
@@ -603,7 +614,7 @@ __STATIC_INLINE uint32_t TIMESTAMP_GET (void) {
 
 
 //**************************************************************************************************
-/** 
+/**
 \defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
 \ingroup DAP_ConfigIO_gr
 @{
@@ -612,7 +623,7 @@ CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_S
 */
 
 /** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized).
-This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the 
+This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the
 Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set:
  - I/O clock system enabled.
  - all I/O pins: input buffer enabled, output pins are set to HighZ mode.
@@ -620,60 +631,12 @@ Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled an
  - LED output pins are enabled and LEDs are turned off.
 */
 __STATIC_INLINE void DAP_SETUP (void) {
-
-  /* Enable clock and init GPIO outputs */
-  LPC_CCU1->CLK_M4_GPIO_CFG = CCU_CLK_CFG_AUTO | CCU_CLK_CFG_RUN;
-  while (!(LPC_CCU1->CLK_M4_GPIO_STAT & CCU_CLK_STAT_RUN));
-
-  /* Configure I/O pins: function number, input buffer enabled,  */
-  /*                     no pull-up/down except nRESET (pull-up) */
-  LPC_SCU->SFSP1_17 = 0U | SCU_SFS_EPUN|SCU_SFS_EZI;  /* SWCLK/TCK: GPIO0[12] */
-  LPC_SCU->SFSP1_6  = 0U | SCU_SFS_EPUN|SCU_SFS_EZI;  /* SWDIO/TMS: GPIO1[9]  */
-  LPC_SCU->SFSP1_5  = 0U | SCU_SFS_EPUN|SCU_SFS_EZI;  /* SWDIO_OE:  GPIO1[8]  */
-  LPC_SCU->SFSP1_18 = 0U | SCU_SFS_EPUN|SCU_SFS_EZI;  /* TDI:       GPIO0[13] */
-  LPC_SCU->SFSP1_14 = 0U | SCU_SFS_EPUN|SCU_SFS_EZI;  /* TDO:       GPIO1[7]  */
-  LPC_SCU->SFSP2_5  = 4U |              SCU_SFS_EZI;  /* nRESET:    GPIO5[5]  */
-  LPC_SCU->SFSP2_6  = 4U | SCU_SFS_EPUN|SCU_SFS_EZI;  /* nRESET_OE: GPIO5[6]  */
-  LPC_SCU->SFSP1_1  = 0U | SCU_SFS_EPUN|SCU_SFS_EZI;  /* LED:       GPIO0[8]  */
-#ifdef TARGET_POWER_EN
-  LPC_SCU->SFSP3_1  = 4U | SCU_SFS_EPUN|SCU_SFS_EZI;  /* Target Power enable P3_1 GPIO5[8] */
-#endif
-
-  /* Configure: SWCLK/TCK, SWDIO/TMS, SWDIO_OE, TDI as outputs (high level)   */
-  /*            TDO as input                                                  */
-  /*            nRESET as input with output latch set to low level            */
-  /*            nRESET_OE as output (low level)                               */
-  LPC_GPIO_PORT->SET[PIN_SWCLK_TCK_PORT]  =  (1U << PIN_SWCLK_TCK_BIT);
-  LPC_GPIO_PORT->SET[PIN_SWDIO_TMS_PORT]  =  (1U << PIN_SWDIO_TMS_BIT);
-  LPC_GPIO_PORT->SET[PIN_SWDIO_OE_PORT]   =  (1U << PIN_SWDIO_OE_BIT);
-  LPC_GPIO_PORT->SET[PIN_TDI_PORT]        =  (1U << PIN_TDI_BIT);
-  LPC_GPIO_PORT->CLR[PIN_nRESET_PORT]     =  (1U << PIN_nRESET_BIT);
-  LPC_GPIO_PORT->CLR[PIN_nRESET_OE_PORT]  =  (1U << PIN_nRESET_OE_BIT);
-  LPC_GPIO_PORT->DIR[PIN_SWCLK_TCK_PORT] |=  (1U << PIN_SWCLK_TCK_BIT);
-  LPC_GPIO_PORT->DIR[PIN_SWDIO_TMS_PORT] |=  (1U << PIN_SWDIO_TMS_BIT);
-  LPC_GPIO_PORT->DIR[PIN_SWDIO_OE_PORT]  |=  (1U << PIN_SWDIO_OE_BIT);
-  LPC_GPIO_PORT->DIR[PIN_TDI_PORT]       |=  (1U << PIN_TDI_BIT);
-  LPC_GPIO_PORT->DIR[PIN_TDO_PORT]       &= ~(1U << PIN_TDO_BIT);
-  LPC_GPIO_PORT->DIR[PIN_nRESET_PORT]    &= ~(1U << PIN_nRESET_BIT);
-  LPC_GPIO_PORT->DIR[PIN_nRESET_OE_PORT] |=  (1U << PIN_nRESET_OE_BIT);
-
-#ifdef TARGET_POWER_EN
-  /* Target Power enable as output (turned on)  */
-  LPC_GPIO_PORT->SET[5]  = (1U << 8);
-  LPC_GPIO_PORT->DIR[5] |= (1U << 8);
-#endif
-
-  /* Configure: LED as output (turned off) */
-  LPC_GPIO_PORT->CLR[LED_CONNECTED_PORT]  =  (1U << LED_CONNECTED_BIT);
-  LPC_GPIO_PORT->DIR[LED_CONNECTED_PORT] |=  (1U << LED_CONNECTED_BIT);
-
-  /* Configure Peripheral Interrupt Priorities */
-  NVIC_SetPriority(USB0_IRQn, 1U);
+  BOARD_InitBootPins();
 }
 
 /** Reset Target Device with custom specific I/O pin or command sequence.
 This function allows the optional implementation of a device specific reset sequence.
-It is called when the command \ref DAP_ResetTarget and is for example required 
+It is called when the command \ref DAP_ResetTarget and is for example required
 when a device needs a time-critical unlock sequence that enables the debug port.
 \return 0 = no device specific reset sequence is implemented.\n
         1 = a device specific reset sequence is implemented.

CMSIS/DAP/Firmware/Examples/MCU-LINK/DebugConfig/MCU-Link_LPC55S69JBD64_cm33_core0.dbgconf

@@ -0,0 +1,18 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <o0> SWO pin
+// <i> The SWO (Serial Wire Output) pin optionally provides data from the ITM
+// <i> for an external debug tool to evaluate.
+//      <0=> PIO0_10
+//      <1=> PIO0_8
+SWO_Pin = 0;
+// 
+
+// <h>Debug Configuration
+//   <o.0>    StopAfterBootloader       <i> Stop after Bootloader
+// </h>
+Dbg_CR = 0x00000001;
+//
+
+
+// <<< end of configuration section >>>

CMSIS/DAP/Firmware/Examples/MCU-LINK/MCU-Link.mex

@@ -0,0 +1,743 @@
+<?xml version="1.0" encoding= "UTF-8" ?>
+<configuration name="MCU-LINK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_1.9 http://mcuxpresso.nxp.com/XSD/mex_configuration_1.9.xsd" uuid="ec487fd8-754b-47b3-bbcd-ee484cc22247" version="1.9" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_1.9" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+   <common>
+      <processor>LPC55S69</processor>
+      <package>LPC55S69JBD64</package>
+      <mcu_data>ksdk2_0</mcu_data>
+      <cores selected="cm33_core0">
+         <core name="Cortex-M33 (Core #0)" id="cm33_core0" description=""/>
+         <core name="Cortex-M33 (Core #1)" id="cm33_core1" description=""/>
+      </cores>
+      <description></description>
+   </common>
+   <preferences>
+      <validate_boot_init_only>true</validate_boot_init_only>
+      <generate_extended_information>false</generate_extended_information>
+      <generate_code_modified_registers_only>false</generate_code_modified_registers_only>
+   </preferences>
+   <tools>
+      <pins name="Pins" version="9.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/pin_mux.c" update_enabled="true"/>
+            <file path="board/pin_mux.h" update_enabled="true"/>
+         </generated_project_files>
+         <pins_profile>
+            <processor_version>9.0.3</processor_version>
+            <pin_labels>
+               <pin_label pin_num="36" pin_signal="PIO0_0/FC3_SCK/CTIMER0_MAT0/SCT_GPI0/SD1_CARD_INT_N/SECURE_GPIO0_0/ACMP0_A" label="_DBGIF_TCK_SWCLK" identifier="DBGIF_TCK_SWCLK"/>
+               <pin_label pin_num="2" pin_signal="PIO0_1/FC3_CTS_SDA_SSEL0/CT_INP0/SCT_GPI1/SD1_CLK/CMP0_OUT/SECURE_GPIO0_1" label="_DBGIF_TDI" identifier="DBGIF_TDI"/>
+               <pin_label pin_num="52" pin_signal="PIO0_2/FC3_TXD_SCL_MISO_WS/CT_INP1/SCT0_OUT0/SCT_GPI2/SECURE_GPIO0_2" label="_DBGIF_TMS_SWDIO" identifier="DBGIF_TMS_SWDIO"/>
+               <pin_label pin_num="44" pin_signal="PIO0_28/FC0_SCK/SD1_CMD/CT_INP11/SCT0_OUT7/USB0_OVERCURRENTN/PLU_OUT1/SECURE_GPIO0_28" label="_DBGIF_TMS_SWDIO_TXEN" identifier="DBGIF_TMS_SWDIO_TXEN"/>
+               <pin_label pin_num="58" pin_signal="PIO0_19/FC4_RTS_SCL_SSEL1/UTICK_CAP0/CTIMER0_MAT2/SCT0_OUT2/FC7_TXD_SCL_MISO_WS/PLU_IN4/SECURE_GPIO0_19" label="_DBGIF_RESET" identifier="DBG_IF_RESET;DBGIF_RESET"/>
+               <pin_label pin_num="46" pin_signal="PIO0_13/FC1_CTS_SDA_SSEL0/UTICK_CAP0/CT_INP0/SCT_GPI0/FC1_RXD_SDA_MOSI_DATA/PLU_IN0/SECURE_GPIO0_13" label="_DBGIF_RESET_TXEN" identifier="DBG_IF_RESET_TXEN;DBGIF_RESET_TXEN"/>
+               <pin_label pin_num="53" pin_signal="PIO0_3/FC3_RXD_SDA_MOSI_DATA/CTIMER0_MAT1/SCT0_OUT1/SCT_GPI3/SECURE_GPIO0_3" label="_DBGIF_TDO_SWO" identifier="DBG_IF_TDO_SWO;DBGIF_TDO_SWO"/>
+               <pin_label pin_num="45" pin_signal="PIO0_24/FC0_RXD_SDA_MOSI_DATA/SD0_D0/CT_INP8/SCT_GPI0/SECURE_GPIO0_24" label="_FC0_TARGET_RXD" identifier="FC0_TARGET_RXD"/>
+               <pin_label pin_num="51" pin_signal="PIO0_25/FC0_TXD_SCL_MISO_WS/SD0_D1/CT_INP9/SCT_GPI1/SECURE_GPIO0_25" label="_FC0_TARGET_TXD" identifier="FC0_TARGET_TXD"/>
+               <pin_label pin_num="56" pin_signal="PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5" label="_LED1" identifier="LED1"/>
+            </pin_labels>
+         </pins_profile>
+         <functions_list>
+            <function name="MCU_LINK_InitPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <prefix></prefix>
+                  <coreID>cm33_core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="FLEXCOMM3" description="Peripheral FLEXCOMM3 is not initialized" problem_level="1" source="Pins:MCU_LINK_InitPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="Peripheral" resourceId="FLEXCOMM0" description="Peripheral FLEXCOMM0 is not initialized" problem_level="1" source="Pins:MCU_LINK_InitPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="Peripheral" resourceId="USBHSH" description="Peripheral USBHSH is not initialized" problem_level="1" source="Pins:MCU_LINK_InitPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:MCU_LINK_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core1">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.lpc_gpio" description="Pins initialization requires the LPC_GPIO Driver in the project." problem_level="2" source="Pins:MCU_LINK_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core1">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="GPIO" signal="PIO0, 0" pin_num="36" pin_signal="PIO0_0/FC3_SCK/CTIMER0_MAT0/SCT_GPI0/SD1_CARD_INT_N/SECURE_GPIO0_0/ACMP0_A">
+                     <pin_features>
+                        <pin_feature name="direction" value="INPUT"/>
+                        <pin_feature name="slew_rate" value="fast"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO" signal="PIO0, 1" pin_num="2" pin_signal="PIO0_1/FC3_CTS_SDA_SSEL0/CT_INP0/SCT_GPI1/SD1_CLK/CMP0_OUT/SECURE_GPIO0_1">
+                     <pin_features>
+                        <pin_feature name="direction" value="INPUT"/>
+                        <pin_feature name="slew_rate" value="fast"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO" signal="PIO0, 2" pin_num="52" pin_signal="PIO0_2/FC3_TXD_SCL_MISO_WS/CT_INP1/SCT0_OUT0/SCT_GPI2/SECURE_GPIO0_2">
+                     <pin_features>
+                        <pin_feature name="direction" value="INPUT"/>
+                        <pin_feature name="mode" value="inactive"/>
+                        <pin_feature name="slew_rate" value="fast"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO" signal="PIO0, 28" pin_num="44" pin_signal="PIO0_28/FC0_SCK/SD1_CMD/CT_INP11/SCT0_OUT7/USB0_OVERCURRENTN/PLU_OUT1/SECURE_GPIO0_28">
+                     <pin_features>
+                        <pin_feature name="direction" value="OUTPUT"/>
+                        <pin_feature name="gpio_init_state" value="false"/>
+                        <pin_feature name="slew_rate" value="fast"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO" signal="PIO0, 19" pin_num="58" pin_signal="PIO0_19/FC4_RTS_SCL_SSEL1/UTICK_CAP0/CTIMER0_MAT2/SCT0_OUT2/FC7_TXD_SCL_MISO_WS/PLU_IN4/SECURE_GPIO0_19">
+                     <pin_features>
+                        <pin_feature name="identifier" value="DBGIF_RESET"/>
+                        <pin_feature name="direction" value="INPUT"/>
+                        <pin_feature name="slew_rate" value="fast"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO" signal="PIO0, 13" pin_num="46" pin_signal="PIO0_13/FC1_CTS_SDA_SSEL0/UTICK_CAP0/CT_INP0/SCT_GPI0/FC1_RXD_SDA_MOSI_DATA/PLU_IN0/SECURE_GPIO0_13">
+                     <pin_features>
+                        <pin_feature name="identifier" value="DBGIF_RESET_TXEN"/>
+                        <pin_feature name="direction" value="OUTPUT"/>
+                        <pin_feature name="gpio_init_state" value="false"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="FLEXCOMM3" signal="RXD_SDA_MOSI_DATA" pin_num="53" pin_signal="PIO0_3/FC3_RXD_SDA_MOSI_DATA/CTIMER0_MAT1/SCT0_OUT1/SCT_GPI3/SECURE_GPIO0_3">
+                     <pin_features>
+                        <pin_feature name="identifier" value="DBGIF_TDO_SWO"/>
+                        <pin_feature name="slew_rate" value="fast"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="FLEXCOMM0" signal="RXD_SDA_MOSI_DATA" pin_num="45" pin_signal="PIO0_24/FC0_RXD_SDA_MOSI_DATA/SD0_D0/CT_INP8/SCT_GPI0/SECURE_GPIO0_24">
+                     <pin_features>
+                        <pin_feature name="slew_rate" value="fast"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="FLEXCOMM0" signal="TXD_SCL_MISO_WS" pin_num="51" pin_signal="PIO0_25/FC0_TXD_SCL_MISO_WS/SD0_D1/CT_INP9/SCT_GPI1/SECURE_GPIO0_25">
+                     <pin_features>
+                        <pin_feature name="slew_rate" value="fast"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="USBHSH" signal="USB_DP" pin_num="23" pin_signal="USB1_DP"/>
+                  <pin peripheral="USBHSH" signal="USB_DM" pin_num="24" pin_signal="USB1_DM"/>
+                  <pin peripheral="USBHSH" signal="USB_VBUS" pin_num="25" pin_signal="USB1_VBUS"/>
+                  <pin peripheral="USBHSH" signal="USB_VSS" pin_num="22" pin_signal="USB1_VSS22"/>
+                  <pin peripheral="USBHSH" signal="USB_VSS" pin_num="26" pin_signal="USB1_VSS26"/>
+                  <pin peripheral="USBHSH" signal="USB_PORTPWRN" pin_num="41" pin_signal="PIO1_2/CTIMER0_MAT3/SCT_GPI6/HS_SPI_SCK/USB1_PORTPWRN/PLU_OUT5"/>
+                  <pin peripheral="GPIO" signal="PIO0, 5" pin_num="56" pin_signal="PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5">
+                     <pin_features>
+                        <pin_feature name="direction" value="OUTPUT"/>
+                        <pin_feature name="gpio_init_state" value="true"/>
+                        <pin_feature name="mode" value="pullUp"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+         </functions_list>
+      </pins>
+      <clocks name="Clocks" version="7.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/clock_config.c" update_enabled="true"/>
+            <file path="board/clock_config.h" update_enabled="true"/>
+         </generated_project_files>
+         <clocks_profile>
+            <processor_version>9.0.3</processor_version>
+         </clocks_profile>
+         <clock_configurations>
+            <clock_configuration name="BOARD_BootClockRUN">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="&apos;XTALIN&apos; (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="SYSCON.XTALIN" description="&apos;XTALIN&apos; (Pins tool id: SYSCON.XTALIN, Clocks tool id: SYSCON.XTALIN) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="&apos;XTALOUT&apos; (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="SYSCON.XTALOUT" description="&apos;XTALOUT&apos; (Pins tool id: SYSCON.XTALOUT, Clocks tool id: SYSCON.XTALOUT) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core1">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core1">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.power" description="Clocks initialization requires the POWER Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core1">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="cm33_core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <clock_sources>
+                  <clock_source id="ANACTRL.fro_hf.outFreq" value="96 MHz" locked="false" enabled="false"/>
+                  <clock_source id="SYSCON.XTAL32M.outFreq" value="16 MHz" locked="false" enabled="true"/>
+               </clock_sources>
+               <clock_outputs>
+                  <clock_output id="FXCOM0_clock.outFreq" value="48 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FXCOM3_clock.outFreq" value="48 MHz" locked="false" accuracy=""/>
+                  <clock_output id="System_clock.outFreq" value="150 MHz" locked="true" accuracy="0.001"/>
+                  <clock_output id="USB1_PHY_clock.outFreq" value="16 MHz" locked="false" accuracy=""/>
+               </clock_outputs>
+               <clock_settings>
+                  <setting id="PLL0_Mode" value="Normal" locked="false"/>
+                  <setting id="ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG" value="Enable" locked="false"/>
+                  <setting id="ENABLE_CLKIN_ENA" value="Enabled" locked="false"/>
+                  <setting id="ENABLE_PLL_USB_OUT" value="Enabled" locked="false"/>
+                  <setting id="ENABLE_SYSTEM_CLK_OUT" value="Enabled" locked="false"/>
+                  <setting id="SYSCON.FCCLKSEL0.sel" value="SYSCON.FROHFDIV" locked="false"/>
+                  <setting id="SYSCON.FCCLKSEL3.sel" value="SYSCON.FROHFDIV" locked="false"/>
+                  <setting id="SYSCON.FRGCTRL3_DIV.scale" value="256" locked="true"/>
+                  <setting id="SYSCON.FROHFDIV.scale" value="2" locked="true"/>
+                  <setting id="SYSCON.MAINCLKSELB.sel" value="SYSCON.PLL0_BYPASS" locked="false"/>
+                  <setting id="SYSCON.PLL0CLKSEL.sel" value="SYSCON.CLK_IN_EN" locked="false"/>
+                  <setting id="SYSCON.PLL0M_MULT.scale" value="150" locked="true"/>
+                  <setting id="SYSCON.PLL0N_DIV.scale" value="8" locked="true"/>
+                  <setting id="SYSCON.PLL0_PDEC.scale" value="2" locked="false"/>
+               </clock_settings>
+               <called_from_default_init>true</called_from_default_init>
+            </clock_configuration>
+         </clock_configurations>
+      </clocks>
+      <dcdx name="DCDx" version="2.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <dcdx_profile>
+            <processor_version>0.0.0</processor_version>
+         </dcdx_profile>
+         <dcdx_configurations/>
+      </dcdx>
+      <periphs name="Peripherals" version="9.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/peripherals.c" update_enabled="true"/>
+            <file path="board/peripherals.h" update_enabled="true"/>
+         </generated_project_files>
+         <peripherals_profile>
+            <processor_version>9.0.3</processor_version>
+         </peripherals_profile>
+         <functional_groups>
+            <functional_group name="BOARD_InitPeripherals" uuid="85f4cd0c-3b58-4e23-a413-239f6952f139" called_from_default_init="true" id_prefix="" core="cm33_core0">
+               <description></description>
+               <options/>
+               <dependencies/>
+               <instances>
+                  <instance name="NVIC" uuid="96d19cd9-5329-408b-ab68-cd8a2e493850" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
+                     <config_set name="nvic">
+                        <array name="interrupt_table"/>
+                        <array name="interrupts"/>
+                     </config_set>
+                  </instance>
+                  <instance name="FLEXCOMM3" uuid="878079cb-696c-4271-a7b1-8f9fbc96ca99" type="flexcomm_usart_cmsis" type_id="flexcomm_usart_cmsis_adab49614496eb4b6311b98863269f48" mode="interrupt" peripheral="FLEXCOMM3" enabled="false" comment="" custom_name_enabled="false" editing_lock="false">
+                     <config_set name="general" quick_selection="default">
+                        <struct name="main_config">
+                           <setting name="operationMode" value="ARM_USART_MODE_ASYNCHRONOUS"/>
+                           <setting name="clockSource" value="FXCOMFunctionClock"/>
+                           <setting name="clockSourceFreq" value="BOARD_BootClockRUN"/>
+                           <setting name="power_state" value="ARM_POWER_FULL"/>
+                           <setting name="baudRate_Bps" value="500000"/>
+                           <setting name="dataBits" value="ARM_USART_DATA_BITS_8"/>
+                           <setting name="parityBit" value="ARM_USART_PARITY_NONE"/>
+                           <setting name="stopBit" value="ARM_USART_STOP_BITS_1"/>
+                           <setting name="enableRX" value="false"/>
+                           <setting name="enableTX" value="false"/>
+                           <setting name="signalEventFunctionId" value="USART_SignalEvent"/>
+                           <setting name="enableGetFreqFnCustomName" value="false"/>
+                           <setting name="getFreqFunctionCustomID" value="USART_GetFreq"/>
+                           <setting name="enableInitPinsFnCustomName" value="false"/>
+                           <setting name="initPinFunctionCustomID" value="USART_InitPins"/>
+                           <setting name="enableDeinitPinsFnCustomName" value="false"/>
+                           <setting name="deinitPinFunctionCustomID" value="USART_DeinitPins"/>
+                        </struct>
+                     </config_set>
+                     <config_set name="fsl_cmsis_uart">
+                        <struct name="interrupt">
+                           <setting name="IRQn" value="FLEXCOMM3_IRQn"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="FLEXCOMM0" uuid="700bce49-bf21-46fe-8618-062c52fe30f6" type="flexcomm_usart_cmsis" type_id="flexcomm_usart_cmsis_adab49614496eb4b6311b98863269f48" mode="interrupt" peripheral="FLEXCOMM0" enabled="false" comment="" custom_name_enabled="false" editing_lock="false">
+                     <config_set name="general" quick_selection="default">
+                        <struct name="main_config">
+                           <setting name="operationMode" value="ARM_USART_MODE_ASYNCHRONOUS"/>
+                           <setting name="clockSource" value="FXCOMFunctionClock"/>
+                           <setting name="clockSourceFreq" value="BOARD_BootClockRUN"/>
+                           <setting name="power_state" value="ARM_POWER_FULL"/>
+                           <setting name="baudRate_Bps" value="500000"/>
+                           <setting name="dataBits" value="ARM_USART_DATA_BITS_8"/>
+                           <setting name="parityBit" value="ARM_USART_PARITY_NONE"/>
+                           <setting name="stopBit" value="ARM_USART_STOP_BITS_1"/>
+                           <setting name="enableRX" value="false"/>
+                           <setting name="enableTX" value="false"/>
+                           <setting name="signalEventFunctionId" value="USART_SignalEvent"/>
+                           <setting name="enableGetFreqFnCustomName" value="false"/>
+                           <setting name="getFreqFunctionCustomID" value="USART_GetFreq"/>
+                           <setting name="enableInitPinsFnCustomName" value="false"/>
+                           <setting name="initPinFunctionCustomID" value="USART_InitPins"/>
+                           <setting name="enableDeinitPinsFnCustomName" value="false"/>
+                           <setting name="deinitPinFunctionCustomID" value="USART_DeinitPins"/>
+                        </struct>
+                     </config_set>
+                     <config_set name="fsl_cmsis_uart">
+                        <struct name="interrupt">
+                           <setting name="IRQn" value="FLEXCOMM0_IRQn"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="USBHSH" uuid="953a3f80-8155-4308-af14-b0c8598e9b55" type="usb" type_id="usb_49b3e4c7d25fbcd298641994d1b911e9" mode="host" peripheral="USBHSH" enabled="false" comment="" custom_name_enabled="false" editing_lock="false">
+                     <config_set name="hostSettings" quick_selection="QS_HOST_DEFAULT">
+                        <setting name="max_power" value="500"/>
+                        <setting name="hub_support" value="true"/>
+                        <array name="interfaces"/>
+                     </config_set>
+                  </instance>
+                  <instance name="DMA0" uuid="883b2846-ab3c-4241-941c-366bc6b8da44" type="lpc_dma" type_id="lpc_dma_c13ca997a68f2ca6c666916ba13db7d7" mode="basic" peripheral="DMA0" enabled="false" comment="" custom_name_enabled="false" editing_lock="false">
+                     <config_set name="fsl_dma">
+                        <array name="dma_table"/>
+                        <array name="dma_channels">
+                           <struct name="0">
+                              <setting name="apiMode" value="trans"/>
+                              <struct name="dma_channel">
+                                 <setting name="channel_prefix_id" value="CH0"/>
+                                 <setting name="DMA_source" value="kDma0RequestFlexcomm3Rx"/>
+                                 <setting name="init_channel_priority" value="true"/>
+                                 <setting name="dma_priority" value="kDMA_ChannelPriority0"/>
+                                 <setting name="enable_custom_name" value="false"/>
+                              </struct>
+                              <setting name="peripheral_request" value="true"/>
+                              <setting name="init_trigger_config" value="false"/>
+                              <struct name="trigger_config">
+                                 <setting name="type" value="kDMA_NoTrigger"/>
+                                 <setting name="burst" value="kDMA_SingleTransfer"/>
+                                 <setting name="wrap" value="kDMA_NoWrap"/>
+                              </struct>
+                              <struct name="trans_config">
+                                 <setting name="init_callback" value="false"/>
+                                 <setting name="callback_function" value=""/>
+                                 <setting name="callback_user_data" value=""/>
+                              </struct>
+                              <array name="tcd_config"/>
+                              <setting name="allocateTCD" value="noncache"/>
+                              <setting name="initTCD" value="noTCDInit"/>
+                           </struct>
+                        </array>
+                        <struct name="dma_interrupt_trans">
+                           <setting name="IRQn" value="DMA0_IRQn"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+               </instances>
+            </functional_group>
+         </functional_groups>
+         <components>
+            <component name="system" uuid="9cbd66be-7ac1-4104-b28d-2bebba2e4e11" type_id="system_54b53072540eeeb8f8e9343e71f28176">
+               <config_set_global name="global_system_definitions">
+                  <setting name="user_definitions" value=""/>
+                  <setting name="user_includes" value=""/>
+               </config_set_global>
+            </component>
+            <component name="msg" uuid="617d74e2-0b6d-4083-802c-350abaf71755" type_id="msg_6e2baaf3b97dbeef01c0043275f9a0e7">
+               <config_set_global name="global_messages"/>
+            </component>
+            <component name="generic_uart" uuid="7f9addee-5c8c-4ce3-8089-19751347aba2" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6">
+               <config_set_global name="global_uart"/>
+            </component>
+            <component name="generic_can" uuid="1282bde3-0821-45b7-8df8-cde69f421f03" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80">
+               <config_set_global name="global_can"/>
+            </component>
+         </components>
+      </periphs>
+      <tee name="TEE" version="2.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <tee_profile>
+            <processor_version>0.0.0</processor_version>
+         </tee_profile>
+         <ahb>
+            <relative_region start="0" size="655360" security="ns_user" memory="PROGRAM_FLASH"/>
+            <relative_region start="0" size="131072" security="ns_user" memory="BootROM"/>
+            <relative_region start="0" size="32768" security="ns_user" memory="SRAMX"/>
+            <relative_region start="0" size="65536" security="ns_user" memory="SRAM0"/>
+            <relative_region start="0" size="65536" security="ns_user" memory="SRAM1"/>
+            <relative_region start="0" size="65536" security="ns_user" memory="SRAM2"/>
+            <relative_region start="0" size="65536" security="ns_user" memory="SRAM3"/>
+            <relative_region start="0" size="16384" security="ns_user" memory="SRAM4"/>
+            <relative_region start="0" size="16384" security="ns_user" memory="USB_RAM"/>
+            <masters>
+               <master id="HASH" security="ns_user"/>
+               <master id="MCM33C" security="ns_user"/>
+               <master id="MCM33S" security="ns_user"/>
+               <master id="PQ" security="ns_user"/>
+               <master id="SDIO" security="ns_user"/>
+               <master id="SDMA0" security="ns_user"/>
+               <master id="SDMA1" security="ns_user"/>
+               <master id="USBFSD" security="ns_user"/>
+               <master id="USBFSH" security="ns_user"/>
+            </masters>
+            <peripherals>
+               <peripheral id="ADC0" security="ns_user"/>
+               <peripheral id="AHB_SECURE_CTRL" security="ns_user"/>
+               <peripheral id="ANACTRL" security="ns_user"/>
+               <peripheral id="CASPER" security="ns_user"/>
+               <peripheral id="CRC_ENGINE" security="ns_user"/>
+               <peripheral id="CTIMER0" security="ns_user"/>
+               <peripheral id="CTIMER1" security="ns_user"/>
+               <peripheral id="CTIMER2" security="ns_user"/>
+               <peripheral id="CTIMER3" security="ns_user"/>
+               <peripheral id="CTIMER4" security="ns_user"/>
+               <peripheral id="DBGMAILBOX" security="ns_user"/>
+               <peripheral id="DMA0" security="ns_user"/>
+               <peripheral id="DMA1" security="ns_user"/>
+               <peripheral id="FLASH" security="ns_user"/>
+               <peripheral id="FLEXCOMM0" security="ns_user"/>
+               <peripheral id="FLEXCOMM1" security="ns_user"/>
+               <peripheral id="FLEXCOMM2" security="ns_user"/>
+               <peripheral id="FLEXCOMM3" security="ns_user"/>
+               <peripheral id="FLEXCOMM4" security="ns_user"/>
+               <peripheral id="FLEXCOMM5" security="ns_user"/>
+               <peripheral id="FLEXCOMM6" security="ns_user"/>
+               <peripheral id="FLEXCOMM7" security="ns_user"/>
+               <peripheral id="GINT0" security="ns_user"/>
+               <peripheral id="GINT1" security="ns_user"/>
+               <peripheral id="GPIO" security="ns_user"/>
+               <peripheral id="HASHCRYPT" security="ns_user"/>
+               <peripheral id="INPUTMUX" security="ns_user"/>
+               <peripheral id="IOCON" security="ns_user"/>
+               <peripheral id="MAILBOX" security="ns_user"/>
+               <peripheral id="MRT0" security="ns_user"/>
+               <peripheral id="OSTIMER" security="ns_user"/>
+               <peripheral id="PINT" security="ns_user"/>
+               <peripheral id="PLU" security="ns_user"/>
+               <peripheral id="PMC" security="ns_user"/>
+               <peripheral id="POWERQUAD" security="ns_user"/>
+               <peripheral id="PRINCE" security="ns_user"/>
+               <peripheral id="PUF" security="ns_user"/>
+               <peripheral id="RNG" security="ns_user"/>
+               <peripheral id="RTC" security="ns_user"/>
+               <peripheral id="SCT0" security="ns_user"/>
+               <peripheral id="SDIF" security="ns_user"/>
+               <peripheral id="SECGPIO" security="ns_user"/>
+               <peripheral id="SECPINT" security="ns_user"/>
+               <peripheral id="SPI8" security="ns_user"/>
+               <peripheral id="SYSCON" security="ns_user"/>
+               <peripheral id="SYSCTL" security="ns_user"/>
+               <peripheral id="USB0" security="ns_user"/>
+               <peripheral id="USBFSH" security="ns_user"/>
+               <peripheral id="USBHSD" security="ns_user"/>
+               <peripheral id="USBHSH" security="ns_user"/>
+               <peripheral id="USBPHY" security="ns_user"/>
+               <peripheral id="UTICK0" security="ns_user"/>
+               <peripheral id="WWDT" security="ns_user"/>
+            </peripherals>
+            <interrupts>
+               <masking>
+                  <interrupt id="acmp_capt_irq" masked="Non-masked"/>
+                  <interrupt id="adc_irq" masked="Non-masked"/>
+                  <interrupt id="casper_irq" masked="Non-masked"/>
+                  <interrupt id="ctimer0_irq" masked="Non-masked"/>
+                  <interrupt id="ctimer1_irq" masked="Non-masked"/>
+                  <interrupt id="ctimer2_irq" masked="Non-masked"/>
+                  <interrupt id="ctimer3_irq" masked="Non-masked"/>
+                  <interrupt id="ctimer4_irq" masked="Non-masked"/>
+                  <interrupt id="flexcomm0_irq" masked="Non-masked"/>
+                  <interrupt id="flexcomm1_irq" masked="Non-masked"/>
+                  <interrupt id="flexcomm2_irq" masked="Non-masked"/>
+                  <interrupt id="flexcomm3_irq" masked="Non-masked"/>
+                  <interrupt id="flexcomm4_irq" masked="Non-masked"/>
+                  <interrupt id="flexcomm5_irq" masked="Non-masked"/>
+                  <interrupt id="flexcomm6_irq" masked="Non-masked"/>
+                  <interrupt id="flexcomm7_irq" masked="Non-masked"/>
+                  <interrupt id="global_irq0" masked="Non-masked"/>
+                  <interrupt id="global_irq1" masked="Non-masked"/>
+                  <interrupt id="lspi_hs_irq" masked="Non-masked"/>
+                  <interrupt id="mailbox_irq" masked="Non-masked"/>
+                  <interrupt id="mrt_irq" masked="Non-masked"/>
+                  <interrupt id="os_event_irq" masked="Non-masked"/>
+                  <interrupt id="pin_int4" masked="Non-masked"/>
+                  <interrupt id="pin_int5" masked="Non-masked"/>
+                  <interrupt id="pin_int6" masked="Non-masked"/>
+                  <interrupt id="pin_int7" masked="Non-masked"/>
+                  <interrupt id="pin_irq0" masked="Non-masked"/>
+                  <interrupt id="pin_irq1" masked="Non-masked"/>
+                  <interrupt id="pin_irq2" masked="Non-masked"/>
+                  <interrupt id="pin_irq3" masked="Non-masked"/>
+                  <interrupt id="plu_irq" masked="Non-masked"/>
+                  <interrupt id="pq_irq" masked="Non-masked"/>
+                  <interrupt id="qddkey_irq" masked="Non-masked"/>
+                  <interrupt id="rtc_irq" masked="Non-masked"/>
+                  <interrupt id="sct_irq" masked="Non-masked"/>
+                  <interrupt id="sdio_irq" masked="Non-masked"/>
+                  <interrupt id="sdma0_irq" masked="Non-masked"/>
+                  <interrupt id="sdma1_irq" masked="Non-masked"/>
+                  <interrupt id="sec_hypervisor_call_irq" masked="Non-masked"/>
+                  <interrupt id="sec_int0" masked="Non-masked"/>
+                  <interrupt id="sec_int1" masked="Non-masked"/>
+                  <interrupt id="sec_vio_irq" masked="Non-masked"/>
+                  <interrupt id="sha_irq" masked="Non-masked"/>
+                  <interrupt id="sys_irq" masked="Non-masked"/>
+                  <interrupt id="usb0_irq" masked="Non-masked"/>
+                  <interrupt id="usb0_needclk_irq" masked="Non-masked"/>
+                  <interrupt id="usb1_irq" masked="Non-masked"/>
+                  <interrupt id="usb1_needclk_irq" masked="Non-masked"/>
+                  <interrupt id="usb1_utmi_irq" masked="Non-masked"/>
+                  <interrupt id="utick_irq" masked="Non-masked"/>
+               </masking>
+               <security>
+                  <interrupt id="acmp_capt_irq" secure="Secure"/>
+                  <interrupt id="adc_irq" secure="Secure"/>
+                  <interrupt id="casper_irq" secure="Secure"/>
+                  <interrupt id="ctimer0_irq" secure="Secure"/>
+                  <interrupt id="ctimer1_irq" secure="Secure"/>
+                  <interrupt id="ctimer2_irq" secure="Secure"/>
+                  <interrupt id="ctimer3_irq" secure="Secure"/>
+                  <interrupt id="ctimer4_irq" secure="Secure"/>
+                  <interrupt id="flexcomm0_irq" secure="Secure"/>
+                  <interrupt id="flexcomm1_irq" secure="Secure"/>
+                  <interrupt id="flexcomm2_irq" secure="Secure"/>
+                  <interrupt id="flexcomm3_irq" secure="Secure"/>
+                  <interrupt id="flexcomm4_irq" secure="Secure"/>
+                  <interrupt id="flexcomm5_irq" secure="Secure"/>
+                  <interrupt id="flexcomm6_irq" secure="Secure"/>
+                  <interrupt id="flexcomm7_irq" secure="Secure"/>
+                  <interrupt id="global_irq0" secure="Secure"/>
+                  <interrupt id="global_irq1" secure="Secure"/>
+                  <interrupt id="lspi_hs_irq" secure="Secure"/>
+                  <interrupt id="mailbox_irq" secure="Secure"/>
+                  <interrupt id="mrt_irq" secure="Secure"/>
+                  <interrupt id="os_event_irq" secure="Secure"/>
+                  <interrupt id="pin_int4" secure="Secure"/>
+                  <interrupt id="pin_int5" secure="Secure"/>
+                  <interrupt id="pin_int6" secure="Secure"/>
+                  <interrupt id="pin_int7" secure="Secure"/>
+                  <interrupt id="pin_irq0" secure="Secure"/>
+                  <interrupt id="pin_irq1" secure="Secure"/>
+                  <interrupt id="pin_irq2" secure="Secure"/>
+                  <interrupt id="pin_irq3" secure="Secure"/>
+                  <interrupt id="plu_irq" secure="Secure"/>
+                  <interrupt id="pq_irq" secure="Secure"/>
+                  <interrupt id="qddkey_irq" secure="Secure"/>
+                  <interrupt id="rtc_irq" secure="Secure"/>
+                  <interrupt id="sct_irq" secure="Secure"/>
+                  <interrupt id="sdio_irq" secure="Secure"/>
+                  <interrupt id="sdma0_irq" secure="Secure"/>
+                  <interrupt id="sdma1_irq" secure="Secure"/>
+                  <interrupt id="sec_hypervisor_call_irq" secure="Secure"/>
+                  <interrupt id="sec_int0" secure="Secure"/>
+                  <interrupt id="sec_int1" secure="Secure"/>
+                  <interrupt id="sec_vio_irq" secure="Secure"/>
+                  <interrupt id="sha_irq" secure="Secure"/>
+                  <interrupt id="sys_irq" secure="Secure"/>
+                  <interrupt id="usb0_irq" secure="Secure"/>
+                  <interrupt id="usb0_needclk_irq" secure="Secure"/>
+                  <interrupt id="usb1_irq" secure="Secure"/>
+                  <interrupt id="usb1_needclk_irq" secure="Secure"/>
+                  <interrupt id="usb1_utmi_irq" secure="Secure"/>
+                  <interrupt id="utick_irq" secure="Secure"/>
+               </security>
+            </interrupts>
+            <pins_masks>
+               <port id="pio0">
+                  <pin_mask id="0" masked="Non-masked"/>
+                  <pin_mask id="1" masked="Non-masked"/>
+                  <pin_mask id="10" masked="Non-masked"/>
+                  <pin_mask id="11" masked="Non-masked"/>
+                  <pin_mask id="12" masked="Non-masked"/>
+                  <pin_mask id="13" masked="Non-masked"/>
+                  <pin_mask id="14" masked="Non-masked"/>
+                  <pin_mask id="15" masked="Non-masked"/>
+                  <pin_mask id="16" masked="Non-masked"/>
+                  <pin_mask id="17" masked="Non-masked"/>
+                  <pin_mask id="18" masked="Non-masked"/>
+                  <pin_mask id="19" masked="Non-masked"/>
+                  <pin_mask id="2" masked="Non-masked"/>
+                  <pin_mask id="20" masked="Non-masked"/>
+                  <pin_mask id="21" masked="Non-masked"/>
+                  <pin_mask id="22" masked="Non-masked"/>
+                  <pin_mask id="23" masked="Non-masked"/>
+                  <pin_mask id="24" masked="Non-masked"/>
+                  <pin_mask id="25" masked="Non-masked"/>
+                  <pin_mask id="26" masked="Non-masked"/>
+                  <pin_mask id="27" masked="Non-masked"/>
+                  <pin_mask id="28" masked="Non-masked"/>
+                  <pin_mask id="29" masked="Non-masked"/>
+                  <pin_mask id="3" masked="Non-masked"/>
+                  <pin_mask id="30" masked="Non-masked"/>
+                  <pin_mask id="31" masked="Non-masked"/>
+                  <pin_mask id="4" masked="Non-masked"/>
+                  <pin_mask id="5" masked="Non-masked"/>
+                  <pin_mask id="6" masked="Non-masked"/>
+                  <pin_mask id="7" masked="Non-masked"/>
+                  <pin_mask id="8" masked="Non-masked"/>
+                  <pin_mask id="9" masked="Non-masked"/>
+               </port>
+               <port id="pio1">
+                  <pin_mask id="0" masked="Non-masked"/>
+                  <pin_mask id="1" masked="Non-masked"/>
+                  <pin_mask id="10" masked="Non-masked"/>
+                  <pin_mask id="11" masked="Non-masked"/>
+                  <pin_mask id="12" masked="Non-masked"/>
+                  <pin_mask id="13" masked="Non-masked"/>
+                  <pin_mask id="14" masked="Non-masked"/>
+                  <pin_mask id="15" masked="Non-masked"/>
+                  <pin_mask id="16" masked="Non-masked"/>
+                  <pin_mask id="17" masked="Non-masked"/>
+                  <pin_mask id="18" masked="Non-masked"/>
+                  <pin_mask id="19" masked="Non-masked"/>
+                  <pin_mask id="2" masked="Non-masked"/>
+                  <pin_mask id="20" masked="Non-masked"/>
+                  <pin_mask id="21" masked="Non-masked"/>
+                  <pin_mask id="22" masked="Non-masked"/>
+                  <pin_mask id="23" masked="Non-masked"/>
+                  <pin_mask id="24" masked="Non-masked"/>
+                  <pin_mask id="25" masked="Non-masked"/>
+                  <pin_mask id="26" masked="Non-masked"/>
+                  <pin_mask id="27" masked="Non-masked"/>
+                  <pin_mask id="28" masked="Non-masked"/>
+                  <pin_mask id="29" masked="Non-masked"/>
+                  <pin_mask id="3" masked="Non-masked"/>
+                  <pin_mask id="30" masked="Non-masked"/>
+                  <pin_mask id="31" masked="Non-masked"/>
+                  <pin_mask id="4" masked="Non-masked"/>
+                  <pin_mask id="5" masked="Non-masked"/>
+                  <pin_mask id="6" masked="Non-masked"/>
+                  <pin_mask id="7" masked="Non-masked"/>
+                  <pin_mask id="8" masked="Non-masked"/>
+                  <pin_mask id="9" masked="Non-masked"/>
+               </port>
+            </pins_masks>
+         </ahb>
+         <sau enabled="true" all_non_secure="false" generate_code_for_disabled_regions="false">
+            <region start="0" size="268435456" security="ns" enabled="true" index="0"/>
+            <region start="536870912" size="3489660928" security="ns" enabled="true" index="1"/>
+            <region start="0" size="32" security="ns" enabled="false" index="2"/>
+            <region start="0" size="32" security="ns" enabled="false" index="3"/>
+            <region start="0" size="32" security="ns" enabled="false" index="4"/>
+            <region start="0" size="32" security="ns" enabled="false" index="5"/>
+            <region start="0" size="32" security="ns" enabled="false" index="6"/>
+            <region start="0" size="32" security="ns" enabled="false" index="7"/>
+         </sau>
+         <global_options>
+            <option id="AIRCR_PRIS" value="no"/>
+            <option id="AIRCR_BFHFNMINS" value="no"/>
+            <option id="AIRCR_SYSRESETREQS" value="no"/>
+            <option id="SCR_SLEEPDEEPS" value="no"/>
+            <option id="SHCSR_SECUREFAULTENA" value="no"/>
+            <option id="NSACR_CP0" value="yes"/>
+            <option id="NSACR_CP1" value="yes"/>
+            <option id="NSACR_CP2" value="no"/>
+            <option id="NSACR_CP3" value="no"/>
+            <option id="NSACR_CP4" value="no"/>
+            <option id="NSACR_CP5" value="no"/>
+            <option id="NSACR_CP6" value="no"/>
+            <option id="NSACR_CP7" value="no"/>
+            <option id="NSACR_CP10" value="yes"/>
+            <option id="NSACR_CP11" value="yes"/>
+            <option id="CPPWR_SU0" value="no"/>
+            <option id="CPPWR_SUS0" value="no"/>
+            <option id="CPPWR_SU1" value="no"/>
+            <option id="CPPWR_SUS1" value="no"/>
+            <option id="CPPWR_SU2" value="no"/>
+            <option id="CPPWR_SUS2" value="no"/>
+            <option id="CPPWR_SU3" value="no"/>
+            <option id="CPPWR_SUS3" value="no"/>
+            <option id="CPPWR_SU4" value="no"/>
+            <option id="CPPWR_SUS4" value="no"/>
+            <option id="CPPWR_SU5" value="no"/>
+            <option id="CPPWR_SUS5" value="no"/>
+            <option id="CPPWR_SU6" value="no"/>
+            <option id="CPPWR_SUS6" value="no"/>
+            <option id="CPPWR_SU7" value="no"/>
+            <option id="CPPWR_SUS7" value="no"/>
+            <option id="CPPWR_SU10" value="no"/>
+            <option id="CPPWR_SUS10" value="no"/>
+            <option id="CPPWR_SU11" value="no"/>
+            <option id="CPPWR_SUS11" value="no"/>
+            <option id="SEC_GPIO_MASK0_LOCK" value="no"/>
+            <option id="SEC_GPIO_MASK1_LOCK" value="no"/>
+            <option id="SEC_CPU1_INT_MASK0_LOCK" value="no"/>
+            <option id="SEC_CPU1_INT_MASK1_LOCK" value="no"/>
+            <option id="MASTER_SEC_LEVEL_LOCK" value="no"/>
+            <option id="CPU0_LOCK_NS_VTOR" value="no"/>
+            <option id="CPU0_LOCK_NS_MPU" value="no"/>
+            <option id="CPU0_LOCK_S_VTAIRCR" value="no"/>
+            <option id="CPU0_LOCK_S_MPU" value="no"/>
+            <option id="CPU0_LOCK_SAU" value="no"/>
+            <option id="CPU0_LOCK_REG_LOCK" value="no"/>
+            <option id="CPU1_LOCK_NS_VTOR" value="no"/>
+            <option id="CPU1_LOCK_NS_MPU" value="no"/>
+            <option id="CPU1_LOCK_REG_LOCK" value="no"/>
+            <option id="AHB_MISC_CTRL_REG_ENABLE_SECURE_CHECKING" value="yes"/>
+            <option id="AHB_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK" value="no"/>
+            <option id="AHB_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK" value="no"/>
+            <option id="AHB_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT" value="no"/>
+            <option id="AHB_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE" value="no"/>
+            <option id="AHB_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE" value="no"/>
+            <option id="AHB_MISC_CTRL_REG_IDAU_ALL_NS" value="no"/>
+            <option id="AHB_MISC_CTRL_REG_WRITE_LOCK" value="yes"/>
+         </global_options>
+         <user_memory_regions/>
+         <mpus>
+            <mpu enabled="false" priv_default_map="false" handler_enabled="false" id="s" generate_code_for_disabled_regions="false">
+               <attributes>
+                  <group index="0" id="Code" memory_type="normal" device="nGnRE"/>
+                  <group index="1" id="RAM" memory_type="normal" device="nGnRE"/>
+                  <group index="2" id="Peripheral" memory_type="device" device="nGnRE"/>
+               </attributes>
+               <regions/>
+            </mpu>
+            <mpu enabled="false" priv_default_map="false" handler_enabled="false" id="ns" generate_code_for_disabled_regions="false">
+               <attributes>
+                  <group index="0" id="Code" memory_type="normal" device="nGnRE"/>
+                  <group index="1" id="RAM" memory_type="normal" device="nGnRE"/>
+                  <group index="2" id="Peripheral" memory_type="device" device="nGnRE"/>
+               </attributes>
+               <regions/>
+            </mpu>
+         </mpus>
+      </tee>
+   </tools>
+</configuration>

CMSIS/DAP/Firmware/Examples/MCU-LINK/Objects/CMSIS_DAP.hex

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CMSIS/DAP/Firmware/Examples/MCU-LINK/README.md

@@ -0,0 +1,13 @@
+CMSIS-DAP v2 firmware for NXP MCU-LINK debug probe.
+
+CMSIS-DAP v2 uses USB bulk endpoints for the communication with the host PC and is therefore faster.
+Optionally, support for streaming SWO trace is provided via an additional USB endpoint.
+
+Instructions for programing CMSIS_DAP firmware on MCU-LINK:
+- download and install MCU-LINK_installer from https://www.nxp.com/design/microcontrollers-developer-resources/mcu-link-debug-probe:MCU-LINK
+- disconnect MCU-LINK from USB (J1), set "firmware update" jumper (J3), connect MCU-LINK to USB (J1)
+- open a Command Window
+- navigate to the MCU-LINK_installer installation (default C:\nxp\MCU-LINK_installer\) and go to the scripts sub-directory
+- copy pre-built firmware hex file ..\CMSIS\DAP\Firmware\Examples\MCU-LINK\Objects\CMSIS_DAP.hex to scripts directory
+- run the command: programm_CMSIS.cmd CMSIS_DAP.hex
+- follow the instructions in command window

CMSIS/DAP/Firmware/Examples/LPC-Link2/V2/RTE/CMSIS/RTX_Config.c → CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/CMSIS/RTX_Config.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2021 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,7 +17,7 @@
  *
  * -----------------------------------------------------------------------------
  *
- * $Revision:   V5.1.0
+ * $Revision:   V5.1.1
  *
  * Project:     CMSIS-RTOS RTX
  * Title:       RTX Configuration
@@ -40,7 +40,7 @@ __WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) {
   (void)object_id;
 
   switch (code) {
-    case osRtxErrorStackUnderflow:
+    case osRtxErrorStackOverflow:
       // Stack overflow detected for thread (thread_id=object_id)
       break;
     case osRtxErrorISRQueueOverflow:
@@ -56,6 +56,7 @@ __WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) {
       // Standard C/C++ library mutex initialization failed
       break;
     default:
+      // Reserved
       break;
   }
   for (;;) {}

CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/RTE/CMSIS/RTX_Config.h → CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/CMSIS/RTX_Config.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2020 Arm Limited. All rights reserved.
+ * Copyright (c) 2013-2021 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,7 +17,7 @@
  *
  * -----------------------------------------------------------------------------
  *
- * $Revision:   V5.5.1
+ * $Revision:   V5.5.2
  *
  * Project:     CMSIS-RTOS RTX
  * Title:       RTX Configuration definitions
@@ -69,14 +69,14 @@
  
 //   </e>
  
-//   <o>ISR FIFO Queue 
+//   <o>ISR FIFO Queue
 //      <4=>  4 entries    <8=>   8 entries   <12=>  12 entries   <16=>  16 entries
 //     <24=> 24 entries   <32=>  32 entries   <48=>  48 entries   <64=>  64 entries
 //     <96=> 96 entries  <128=> 128 entries  <196=> 196 entries  <256=> 256 entries
 //   <i> RTOS Functions called from ISR store requests to this buffer.
 //   <i> Default: 16 entries
 #ifndef OS_ISR_FIFO_QUEUE
-#define OS_ISR_FIFO_QUEUE           16
+#define OS_ISR_FIFO_QUEUE           32
 #endif
  
 //   <q>Object Memory usage counters
@@ -143,10 +143,10 @@
 #endif
  
 //   <q>Stack overrun checking
-//   <i> Enables stack overrun check at thread switch.
+//   <i> Enables stack overrun check at thread switch (requires RTX source variant).
 //   <i> Enabling this option increases slightly the execution time of a thread switch.
 #ifndef OS_STACK_CHECK
-#define OS_STACK_CHECK              1
+#define OS_STACK_CHECK              0
 #endif
  
 //   <q>Stack usage watermark
@@ -156,8 +156,8 @@
 #define OS_STACK_WATERMARK          0
 #endif
  
-//   <o>Processor mode for Thread execution 
-//     <0=> Unprivileged mode 
+//   <o>Processor mode for Thread execution
+//     <0=> Unprivileged mode
 //     <1=> Privileged mode
 //   <i> Default: Privileged mode
 #ifndef OS_PRIVILEGE_MODE
@@ -367,125 +367,125 @@
 //     <i> Recording levels for RTX components.
 //     <i> Only applicable if events for the respective component are generated.
  
-//       <h>Memory Management
+//       <e.7>Memory Management
 //       <i> Recording level for Memory Management events.
 //         <o.0>Error events
 //         <o.1>API function call events
 //         <o.2>Operation events
 //         <o.3>Detailed operation events
-//       </h>
-#ifndef OS_EVR_MEMORY_LEVEL 
-#define OS_EVR_MEMORY_LEVEL         0x01U
+//       </e>
+#ifndef OS_EVR_MEMORY_LEVEL
+#define OS_EVR_MEMORY_LEVEL         0x81U
 #endif
  
-//       <h>Kernel
+//       <e.7>Kernel
 //       <i> Recording level for Kernel events.
 //         <o.0>Error events
 //         <o.1>API function call events
 //         <o.2>Operation events
 //         <o.3>Detailed operation events
-//       </h>
-#ifndef OS_EVR_KERNEL_LEVEL 
-#define OS_EVR_KERNEL_LEVEL         0x01U
+//       </e>
+#ifndef OS_EVR_KERNEL_LEVEL
+#define OS_EVR_KERNEL_LEVEL         0x81U
 #endif
  
-//       <h>Thread
+//       <e.7>Thread
 //       <i> Recording level for Thread events.
 //         <o.0>Error events
 //         <o.1>API function call events
 //         <o.2>Operation events
 //         <o.3>Detailed operation events
-//       </h>
-#ifndef OS_EVR_THREAD_LEVEL 
-#define OS_EVR_THREAD_LEVEL         0x05U
+//       </e>
+#ifndef OS_EVR_THREAD_LEVEL
+#define OS_EVR_THREAD_LEVEL         0x85U
 #endif
  
-//       <h>Generic Wait
+//       <e.7>Generic Wait
 //       <i> Recording level for Generic Wait events.
 //         <o.0>Error events
 //         <o.1>API function call events
 //         <o.2>Operation events
 //         <o.3>Detailed operation events
-//       </h>
-#ifndef OS_EVR_WAIT_LEVEL 
-#define OS_EVR_WAIT_LEVEL           0x01U
+//       </e>
+#ifndef OS_EVR_WAIT_LEVEL
+#define OS_EVR_WAIT_LEVEL           0x81U
 #endif
  
-//       <h>Thread Flags
+//       <e.7>Thread Flags
 //       <i> Recording level for Thread Flags events.
 //         <o.0>Error events
 //         <o.1>API function call events
 //         <o.2>Operation events
 //         <o.3>Detailed operation events
-//       </h>
-#ifndef OS_EVR_THFLAGS_LEVEL 
-#define OS_EVR_THFLAGS_LEVEL        0x01U
+//       </e>
+#ifndef OS_EVR_THFLAGS_LEVEL
+#define OS_EVR_THFLAGS_LEVEL        0x81U
 #endif
  
-//       <h>Event Flags
+//       <e.7>Event Flags
 //       <i> Recording level for Event Flags events.
 //         <o.0>Error events
 //         <o.1>API function call events
 //         <o.2>Operation events
 //         <o.3>Detailed operation events
-//       </h>
-#ifndef OS_EVR_EVFLAGS_LEVEL 
-#define OS_EVR_EVFLAGS_LEVEL        0x01U
+//       </e>
+#ifndef OS_EVR_EVFLAGS_LEVEL
+#define OS_EVR_EVFLAGS_LEVEL        0x81U
 #endif
  
-//       <h>Timer
+//       <e.7>Timer
 //       <i> Recording level for Timer events.
 //         <o.0>Error events
 //         <o.1>API function call events
 //         <o.2>Operation events
 //         <o.3>Detailed operation events
-//       </h>
-#ifndef OS_EVR_TIMER_LEVEL 
-#define OS_EVR_TIMER_LEVEL          0x01U
+//       </e>
+#ifndef OS_EVR_TIMER_LEVEL
+#define OS_EVR_TIMER_LEVEL          0x81U
 #endif
  
-//       <h>Mutex
+//       <e.7>Mutex
 //       <i> Recording level for Mutex events.
 //         <o.0>Error events
 //         <o.1>API function call events
 //         <o.2>Operation events
 //         <o.3>Detailed operation events
-//       </h>
-#ifndef OS_EVR_MUTEX_LEVEL 
-#define OS_EVR_MUTEX_LEVEL          0x01U
+//       </e>
+#ifndef OS_EVR_MUTEX_LEVEL
+#define OS_EVR_MUTEX_LEVEL          0x81U
 #endif
  
-//       <h>Semaphore
+//       <e.7>Semaphore
 //       <i> Recording level for Semaphore events.
 //         <o.0>Error events
 //         <o.1>API function call events
 //         <o.2>Operation events
 //         <o.3>Detailed operation events
-//       </h>
-#ifndef OS_EVR_SEMAPHORE_LEVEL 
-#define OS_EVR_SEMAPHORE_LEVEL      0x01U
+//       </e>
+#ifndef OS_EVR_SEMAPHORE_LEVEL
+#define OS_EVR_SEMAPHORE_LEVEL      0x81U
 #endif
  
-//       <h>Memory Pool
+//       <e.7>Memory Pool
 //       <i> Recording level for Memory Pool events.
 //         <o.0>Error events
 //         <o.1>API function call events
 //         <o.2>Operation events
 //         <o.3>Detailed operation events
-//       </h>
-#ifndef OS_EVR_MEMPOOL_LEVEL 
-#define OS_EVR_MEMPOOL_LEVEL        0x01U
+//       </e>
+#ifndef OS_EVR_MEMPOOL_LEVEL
+#define OS_EVR_MEMPOOL_LEVEL        0x81U
 #endif
  
-//       <h>Message Queue
+//       <e.7>Message Queue
 //       <i> Recording level for Message Queue events.
 //         <o.0>Error events
 //         <o.1>API function call events
 //         <o.2>Operation events
 //         <o.3>Detailed operation events
-//       </h>
-#ifndef OS_EVR_MSGQUEUE_LEVEL 
-#define OS_EVR_MSGQUEUE_LEVEL       0x01U
+//       </e>
+#ifndef OS_EVR_MSGQUEUE_LEVEL
+#define OS_EVR_MSGQUEUE_LEVEL       0x81U
 #endif
  
 //     </h>

CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/Device/LPC55S69JBD64_cm33_core0/LPC55S69_cm33_core0_flash.scf

@@ -0,0 +1,105 @@
+#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c
+/*
+** ###################################################################
+**     Processors:          LPC55S69JBD100_cm33_core0
+**                          LPC55S69JBD64_cm33_core0
+**                          LPC55S69JEV98_cm33_core0
+**
+**     Compiler:            Keil ARM C/C++ Compiler
+**     Reference manual:    LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3  16 May 2019
+**     Version:             rev. 1.1, 2019-05-16
+**     Build:               b200722
+**
+**     Abstract:
+**         Linker file for the Keil ARM C/C++ Compiler
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2020 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+** ###################################################################
+*/
+
+
+/* USB BDT size */
+#define usb_bdt_size                   0x0
+/* Sizes */
+#if (defined(__stack_size__))
+  #define Stack_Size                   __stack_size__
+#else
+  #define Stack_Size                   0x0400
+#endif
+
+#if (defined(__heap_size__))
+  #define Heap_Size                    __heap_size__
+#else
+  #define Heap_Size                    0x0400
+#endif
+
+#define  m_interrupts_start            0x00000000
+#define  m_interrupts_size             0x00000200
+
+#define  m_text_start                  0x00000200
+#define  m_text_size                   0x00071E00
+
+#define  m_core1_image_start           0x00072000
+#define  m_core1_image_size            0x00026000
+
+#if (defined(__use_shmem__))
+  #define  m_data_start                0x20000000
+  #define  m_data_size                 0x00031800
+  #define  m_rpmsg_sh_mem_start        0x20031800
+  #define  m_rpmsg_sh_mem_size         0x00001800
+#else
+  #define  m_data_start                0x20000000
+  #define  m_data_size                 0x00033000
+#endif
+
+#define  m_usb_sram_start              0x40100000
+#define  m_usb_sram_size               0x00004000
+
+
+LR_m_text m_interrupts_start m_interrupts_size+m_text_size {   ; load region size_region
+
+  VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
+    * (.isr_vector,+FIRST)
+  }
+
+  ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
+    * (InRoot$$Sections)
+    .ANY (+RO)
+  }
+
+#if (defined(__use_shmem__))
+  RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG
+    * (rpmsg_sh_mem_section)
+  }
+#endif
+
+  RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
+    .ANY (+RW +ZI)
+  }
+  ARM_LIB_HEAP +0 EMPTY Heap_Size {    ; Heap region growing up
+  }
+  ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
+  }
+
+  RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
+    * (*m_usb_bdt)
+  }
+
+  RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
+    * (*m_usb_global)
+  }
+}
+
+LR_CORE1_IMAGE m_core1_image_start {
+  CORE1_REGION m_core1_image_start m_core1_image_size {
+    * (.core1_code)
+  }
+}

CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/Device/LPC55S69JBD64_cm33_core0/LPC55S69_cm33_core0_flash_ns.scf

@@ -0,0 +1,107 @@
+#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c
+/*
+** ###################################################################
+**     Processors:          LPC55S69JBD100_cm33_core0
+**                          LPC55S69JBD64_cm33_core0
+**                          LPC55S69JEV98_cm33_core0
+**
+**     Compiler:            Keil ARM C/C++ Compiler
+**     Reference manual:    LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3  16 May 2019
+**     Version:             rev. 1.1, 2019-05-16
+**     Build:               b190923
+**
+**     Abstract:
+**         Linker file for the Keil ARM C/C++ Compiler
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2019 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+** ###################################################################
+*/
+
+
+/* USB BDT size */
+#define usb_bdt_size                   0x0
+/* Sizes */
+#if (defined(__stack_size__))
+  #define Stack_Size                   __stack_size__
+#else
+  #define Stack_Size                   0x0400
+#endif
+
+#if (defined(__heap_size__))
+  #define Heap_Size                    __heap_size__
+#else
+  #define Heap_Size                    0x0400
+#endif
+
+/* The first 64kB of FLASH is used as secure memory. The rest of FLASH memory is non-secure memory. */
+#define  m_interrupts_start            0x00010000
+#define  m_interrupts_size             0x00000200
+
+#define  m_text_start                  0x00010200
+#define  m_text_size                   0x00061E00
+
+#define  m_core1_image_start           0x00072000
+#define  m_core1_image_size            0x00026000
+
+/* The first 32kB of data RAM is used as secure memory. The rest of data RAM memory is non-secure memory. */
+#if (defined(__use_shmem__))
+  #define  m_data_start                0x20008000
+  #define  m_data_size                 0x00029000
+  #define  m_rpmsg_sh_mem_start        0x20031800
+  #define  m_rpmsg_sh_mem_size         0x00001800
+#else
+  #define  m_data_start                0x20008000
+  #define  m_data_size                 0x0002B000
+#endif
+
+#define  m_usb_sram_start              0x40100000
+#define  m_usb_sram_size               0x00004000
+
+
+LR_m_text m_interrupts_start m_interrupts_size+m_text_size {   ; load region size_region
+
+  VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
+    * (.isr_vector,+FIRST)
+  }
+
+  ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
+    * (InRoot$$Sections)
+    .ANY (+RO)
+  }
+
+#if (defined(__use_shmem__))
+  RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG
+    * (rpmsg_sh_mem_section)
+  }
+#endif
+
+  RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
+    .ANY (+RW +ZI)
+  }
+  ARM_LIB_HEAP +0 EMPTY Heap_Size {    ; Heap region growing up
+  }
+  ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
+  }
+
+  RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
+    * (*m_usb_bdt)
+  }
+
+  RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
+    * (*m_usb_global)
+  }
+}
+
+LR_CORE1_IMAGE m_core1_image_start {
+  CORE1_REGION m_core1_image_start m_core1_image_size {
+    * (.core1_code)
+  }
+}

CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/Device/LPC55S69JBD64_cm33_core0/LPC55S69_cm33_core0_flash_s.scf

@@ -0,0 +1,116 @@
+#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c
+/*
+** ###################################################################
+**     Processors:          LPC55S69JBD100_cm33_core0
+**                          LPC55S69JBD64_cm33_core0
+**                          LPC55S69JEV98_cm33_core0
+**
+**     Compiler:            Keil ARM C/C++ Compiler
+**     Reference manual:    LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3  16 May 2019
+**     Version:             rev. 1.1, 2019-05-16
+**     Build:               b190923
+**
+**     Abstract:
+**         Linker file for the Keil ARM C/C++ Compiler
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2019 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+** ###################################################################
+*/
+
+
+/* USB BDT size */
+#define usb_bdt_size                   0x0
+/* Sizes */
+#if (defined(__stack_size__))
+  #define Stack_Size                   __stack_size__
+#else
+  #define Stack_Size                   0x0400
+#endif
+
+#if (defined(__heap_size__))
+  #define Heap_Size                    __heap_size__
+#else
+  #define Heap_Size                    0x0400
+#endif
+
+/* Only the first 64kB of flash is used as secure memory. */
+#define  m_interrupts_start            0x10000000
+#define  m_interrupts_size             0x00000200
+
+#define  m_text_start                  0x10000200
+#define  m_text_size                   0x0000FC00
+
+#define  m_core1_image_start           0x10072000
+#define  m_core1_image_size            0x00026000
+
+/* Only first 32kB of data RAM is used as secure memory. */
+#if (defined(__use_shmem__))
+  #define  m_data_start                0x30000000
+  #define  m_data_size                 0x00008000
+  #define  m_rpmsg_sh_mem_start        0x30031800
+  #define  m_rpmsg_sh_mem_size         0x00001800
+#else
+  #define  m_data_start                0x30000000
+  #define  m_data_size                 0x00008000
+#endif
+
+/* 512B - memory for veneer table (NSC - secure, non-secure callable memory) */
+#define  m_veneer_table_start          0x1000FE00
+#define  m_veneer_table_size           0x200
+
+
+#define  m_usb_sram_start              0x50100000
+#define  m_usb_sram_size               0x00004000
+
+
+LR_m_text m_interrupts_start m_interrupts_size+m_text_size+m_veneer_table_size {   ; load region size_region
+
+  VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
+    * (.isr_vector,+FIRST)
+  }
+
+  ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
+    * (InRoot$$Sections)
+    .ANY (+RO)
+  }
+
+#if (defined(__use_shmem__))
+  RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG
+    * (rpmsg_sh_mem_section)
+  }
+#endif
+
+  RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
+    .ANY (+RW +ZI)
+  }
+  ARM_LIB_HEAP +0 EMPTY Heap_Size {    ; Heap region growing up
+  }
+  ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
+  }
+
+  ER_m_veneer_table m_veneer_table_start FIXED m_veneer_table_size {; veneer table
+    *(Veneer$$CMSE)
+  }
+
+  RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
+    * (*m_usb_bdt)
+  }
+
+  RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
+    * (*m_usb_global)
+  }
+}
+
+LR_CORE1_IMAGE m_core1_image_start {
+  CORE1_REGION m_core1_image_start m_core1_image_size {
+    * (.core1_code)
+  }
+}

CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/Device/LPC55S69JBD64_cm33_core0/LPC55S69_cm33_core0_ram.scf

@@ -0,0 +1,105 @@
+#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c
+/*
+** ###################################################################
+**     Processors:          LPC55S69JBD100_cm33_core0
+**                          LPC55S69JBD64_cm33_core0
+**                          LPC55S69JEV98_cm33_core0
+**
+**     Compiler:            Keil ARM C/C++ Compiler
+**     Reference manual:    LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3  16 May 2019
+**     Version:             rev. 1.1, 2019-05-16
+**     Build:               b200722
+**
+**     Abstract:
+**         Linker file for the Keil ARM C/C++ Compiler
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2020 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+** ###################################################################
+*/
+
+
+/* USB BDT size */
+#define usb_bdt_size                   0x0
+/* Sizes */
+#if (defined(__stack_size__))
+  #define Stack_Size                   __stack_size__
+#else
+  #define Stack_Size                   0x0400
+#endif
+
+#if (defined(__heap_size__))
+  #define Heap_Size                    __heap_size__
+#else
+  #define Heap_Size                    0x0400
+#endif
+
+#define  m_interrupts_start            0x04000000
+#define  m_interrupts_size             0x00000200
+
+#define  m_text_start                  0x04000200
+#define  m_text_size                   0x00007E00
+
+#define  m_core1_image_start           0x20033000
+#define  m_core1_image_size            0x0000C800
+
+#if (defined(__use_shmem__))
+  #define  m_data_start                0x20000000
+  #define  m_data_size                 0x00031800
+  #define  m_rpmsg_sh_mem_start        0x20031800
+  #define  m_rpmsg_sh_mem_size         0x00001800
+#else
+  #define  m_data_start                0x20000000
+  #define  m_data_size                 0x00033000
+#endif
+
+#define  m_usb_sram_start              0x40100000
+#define  m_usb_sram_size               0x00004000
+
+
+LR_m_text m_interrupts_start m_interrupts_size+m_text_size {   ; load region size_region
+
+  VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
+    * (.isr_vector,+FIRST)
+  }
+
+  ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
+    * (InRoot$$Sections)
+    .ANY (+RO)
+  }
+
+#if (defined(__use_shmem__))
+  RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG
+    * (rpmsg_sh_mem_section)
+  }
+#endif
+
+  RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
+    .ANY (+RW +ZI)
+  }
+  ARM_LIB_HEAP +0 EMPTY Heap_Size {    ; Heap region growing up
+  }
+  ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
+  }
+
+  RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
+    * (*m_usb_bdt)
+  }
+
+  RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
+    * (*m_usb_global)
+  }
+}
+
+LR_CORE1_IMAGE m_core1_image_start {
+  CORE1_REGION m_core1_image_start m_core1_image_size {
+    * (.core1_code)
+  }
+}

CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/Device/LPC55S69JBD64_cm33_core0/RTE_Device.h

@@ -0,0 +1,215 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _RTE_DEVICE_H
+#define _RTE_DEVICE_H
+
+#include "pin_mux.h"
+
+/* UART Select, UART0-UART7. */
+/* User needs to provide the implementation of USARTX_GetFreq/USARTX_InitPins/USARTX_DeinitPins for the enabled USART
+ * instance. */
+#define RTE_USART0        1
+#define RTE_USART0_DMA_EN 1
+#define RTE_USART1        0
+#define RTE_USART1_DMA_EN 0
+#define RTE_USART2        0
+#define RTE_USART2_DMA_EN 0
+#define RTE_USART3        1
+#define RTE_USART3_DMA_EN 1
+#define RTE_USART4        0
+#define RTE_USART4_DMA_EN 0
+#define RTE_USART5        0
+#define RTE_USART5_DMA_EN 0
+#define RTE_USART6        0
+#define RTE_USART6_DMA_EN 0
+#define RTE_USART7        0
+#define RTE_USART7_DMA_EN 0
+
+/* USART configuration. */
+#define USART_RX_BUFFER_LEN     64
+#define USART0_RX_BUFFER_ENABLE 1
+#define USART1_RX_BUFFER_ENABLE 0
+#define USART2_RX_BUFFER_ENABLE 0
+#define USART3_RX_BUFFER_ENABLE 1
+#define USART4_RX_BUFFER_ENABLE 0
+#define USART5_RX_BUFFER_ENABLE 0
+#define USART6_RX_BUFFER_ENABLE 0
+#define USART7_RX_BUFFER_ENABLE 0
+
+#define RTE_USART0_DMA_TX_CH       5
+#define RTE_USART0_DMA_TX_DMA_BASE DMA0
+#define RTE_USART0_DMA_RX_CH       4
+#define RTE_USART0_DMA_RX_DMA_BASE DMA0
+
+#define RTE_USART1_DMA_TX_CH       7
+#define RTE_USART1_DMA_TX_DMA_BASE DMA0
+#define RTE_USART1_DMA_RX_CH       6
+#define RTE_USART1_DMA_RX_DMA_BASE DMA0
+
+#define RTE_USART2_DMA_TX_CH       8
+#define RTE_USART2_DMA_TX_DMA_BASE DMA0
+#define RTE_USART2_DMA_RX_CH       9
+#define RTE_USART2_DMA_RX_DMA_BASE DMA0
+
+#define RTE_USART3_DMA_TX_CH       9
+#define RTE_USART3_DMA_TX_DMA_BASE DMA0
+#define RTE_USART3_DMA_RX_CH       8
+#define RTE_USART3_DMA_RX_DMA_BASE DMA0
+
+#define RTE_USART4_DMA_TX_CH       13
+#define RTE_USART4_DMA_TX_DMA_BASE DMA0
+#define RTE_USART4_DMA_RX_CH       12
+#define RTE_USART4_DMA_RX_DMA_BASE DMA0
+
+#define RTE_USART5_DMA_TX_CH       15
+#define RTE_USART5_DMA_TX_DMA_BASE DMA0
+#define RTE_USART5_DMA_RX_CH       14
+#define RTE_USART5_DMA_RX_DMA_BASE DMA0
+
+#define RTE_USART6_DMA_TX_CH       17
+#define RTE_USART6_DMA_TX_DMA_BASE DMA0
+#define RTE_USART6_DMA_RX_CH       16
+#define RTE_USART6_DMA_RX_DMA_BASE DMA0
+
+#define RTE_USART7_DMA_TX_CH       19
+#define RTE_USART7_DMA_TX_DMA_BASE DMA0
+#define RTE_USART7_DMA_RX_CH       18
+#define RTE_USART7_DMA_RX_DMA_BASE DMA0
+
+/* I2C Select, I2C0 -I2C7*/
+/* User needs to provide the implementation of I2CX_GetFreq/I2CX_InitPins/I2CX_DeinitPins for the enabled I2C instance.
+ */
+#define RTE_I2C0        0
+#define RTE_I2C0_DMA_EN 0
+#define RTE_I2C1        0
+#define RTE_I2C1_DMA_EN 0
+#define RTE_I2C2        0
+#define RTE_I2C2_DMA_EN 0
+#define RTE_I2C3        0
+#define RTE_I2C3_DMA_EN 0
+#define RTE_I2C4        0
+#define RTE_I2C4_DMA_EN 0
+#define RTE_I2C5        0
+#define RTE_I2C5_DMA_EN 0
+#define RTE_I2C6        0
+#define RTE_I2C6_DMA_EN 0
+#define RTE_I2C7        0
+#define RTE_I2C7_DMA_EN 0
+
+/*I2C configuration*/
+#define RTE_I2C0_Master_DMA_BASE DMA0
+#define RTE_I2C0_Master_DMA_CH   1
+
+#define RTE_I2C1_Master_DMA_BASE DMA0
+#define RTE_I2C1_Master_DMA_CH   3
+
+#define RTE_I2C2_Master_DMA_BASE DMA0
+#define RTE_I2C2_Master_DMA_CH   5
+
+#define RTE_I2C3_Master_DMA_BASE DMA0
+#define RTE_I2C3_Master_DMA_CH   7
+
+#define RTE_I2C4_Master_DMA_BASE DMA0
+#define RTE_I2C4_Master_DMA_CH   9
+
+#define RTE_I2C5_Master_DMA_BASE DMA0
+#define RTE_I2C5_Master_DMA_CH   11
+
+#define RTE_I2C6_Master_DMA_BASE DMA0
+#define RTE_I2C6_Master_DMA_CH   13
+
+#define RTE_I2C7_Master_DMA_BASE DMA0
+#define RTE_I2C7_Master_DMA_CH   15
+
+/* SPI select, SPI0 - SPI7.*/
+/* User needs to provide the implementation of SPIX_GetFreq/SPIX_InitPins/SPIX_DeinitPins for the enabled SPI instance.
+ */
+#define RTE_SPI0        0
+#define RTE_SPI0_DMA_EN 0
+#define RTE_SPI1        0
+#define RTE_SPI1_DMA_EN 0
+#define RTE_SPI2        0
+#define RTE_SPI2_DMA_EN 0
+#define RTE_SPI3        0
+#define RTE_SPI3_DMA_EN 0
+#define RTE_SPI4        0
+#define RTE_SPI4_DMA_EN 0
+#define RTE_SPI5        0
+#define RTE_SPI5_DMA_EN 0
+#define RTE_SPI6        0
+#define RTE_SPI6_DMA_EN 0
+#define RTE_SPI7        0
+#define RTE_SPI7_DMA_EN 0
+
+/* SPI configuration. */
+#define RTE_SPI0_SSEL_NUM        kSPI_Ssel0
+#define RTE_SPI0_PIN_INIT        SPI0_InitPins
+#define RTE_SPI0_PIN_DEINIT      SPI0_DeinitPins
+#define RTE_SPI0_DMA_TX_CH       1
+#define RTE_SPI0_DMA_TX_DMA_BASE DMA0
+#define RTE_SPI0_DMA_RX_CH       0
+#define RTE_SPI0_DMA_RX_DMA_BASE DMA0
+
+#define RTE_SPI1_SSEL_NUM        kSPI_Ssel0
+#define RTE_SPI1_PIN_INIT        SPI1_InitPins
+#define RTE_SPI1_PIN_DEINIT      SPI1_DeinitPins
+#define RTE_SPI1_DMA_TX_CH       3
+#define RTE_SPI1_DMA_TX_DMA_BASE DMA0
+#define RTE_SPI1_DMA_RX_CH       2
+#define RTE_SPI1_DMA_RX_DMA_BASE DMA0
+
+#define RTE_SPI2_SSEL_NUM        kSPI_Ssel0
+#define RTE_SPI2_PIN_INIT        SPI2_InitPins
+#define RTE_SPI2_PIN_DEINIT      SPI2_DeinitPins
+#define RTE_SPI2_DMA_TX_CH       5
+#define RTE_SPI2_DMA_TX_DMA_BASE DMA0
+#define RTE_SPI2_DMA_RX_CH       4
+#define RTE_SPI2_DMA_RX_DMA_BASE DMA0
+
+#define RTE_SPI3_SSEL_NUM        kSPI_Ssel0
+#define RTE_SPI3_PIN_INIT        SPI3_InitPins
+#define RTE_SPI3_PIN_DEINIT      SPI3_DeinitPins
+#define RTE_SPI3_DMA_TX_CH       7
+#define RTE_SPI3_DMA_TX_DMA_BASE DMA0
+#define RTE_SPI3_DMA_RX_CH       6
+#define RTE_SPI3_DMA_RX_DMA_BASE DMA0
+
+#define RTE_SPI4_SSEL_NUM        kSPI_Ssel0
+#define RTE_SPI4_PIN_INIT        SPI4_InitPins
+#define RTE_SPI4_PIN_DEINIT      SPI4_DeinitPins
+#define RTE_SPI4_DMA_TX_CH       9
+#define RTE_SPI4_DMA_TX_DMA_BASE DMA0
+#define RTE_SPI4_DMA_RX_CH       8
+#define RTE_SPI4_DMA_RX_DMA_BASE DMA0
+
+#define RTE_SPI5_SSEL_NUM        kSPI_Ssel0
+#define RTE_SPI5_PIN_INIT        SPI5_InitPins
+#define RTE_SPI5_PIN_DEINIT      SPI5_DeinitPins
+#define RTE_SPI5_DMA_TX_CH       11
+#define RTE_SPI5_DMA_TX_DMA_BASE DMA0
+#define RTE_SPI5_DMA_RX_CH       10
+#define RTE_SPI5_DMA_RX_DMA_BASE DMA0
+
+#define RTE_SPI6_SSEL_NUM        kSPI_Ssel0
+#define RTE_SPI6_PIN_INIT        SPI6_InitPins
+#define RTE_SPI6_PIN_DEINIT      SPI6_DeinitPins
+#define RTE_SPI6_DMA_TX_CH       13
+#define RTE_SPI6_DMA_TX_DMA_BASE DMA0
+#define RTE_SPI6_DMA_RX_CH       12
+#define RTE_SPI6_DMA_RX_DMA_BASE DMA0
+
+#define RTE_SPI7_SSEL_NUM        kSPI_Ssel0
+#define RTE_SPI7_PIN_INIT        SPI7_InitPins
+#define RTE_SPI7_PIN_DEINIT      SPI7_DeinitPins
+#define RTE_SPI7_DMA_TX_CH       15
+#define RTE_SPI7_DMA_TX_DMA_BASE DMA0
+#define RTE_SPI7_DMA_RX_CH       14
+#define RTE_SPI7_DMA_RX_DMA_BASE DMA0
+
+#endif /* _RTE_DEVICE_H */

CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/Device/LPC55S69JBD64_cm33_core0/startup_LPC55S69_cm33_core0.S

@@ -0,0 +1,801 @@
+/* ---------------------------------------------------------------------------------------
+ * @file:    startup_LPC55S69_cm33_core0.s
+ * @purpose: CMSIS Cortex-M33 Core Device Startup File for the LPC55S69_cm33_core0
+ * @version: 1.1
+ * @date:    2019-5-16
+ * ---------------------------------------------------------------------------------------*/
+/*
+ * Copyright 1997-2016 Freescale Semiconductor, Inc.
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/*****************************************************************************/
+/* Version: GCC for ARM Embedded Processors                                  */
+/*****************************************************************************/
+
+    .syntax unified
+    .arch armv8-m.main
+    .eabi_attribute Tag_ABI_align_preserved, 1 /*8-byte alignment */
+
+    .section .isr_vector, "a"
+    .align 2
+    .globl __Vectors
+
+__Vectors:
+    .long    Image$$ARM_LIB_STACK$$ZI$$Limit                /* Top of Stack */
+    .long    Reset_Handler                                   /* Reset Handler */
+    .long    NMI_Handler                                     /* NMI Handler*/
+    .long    HardFault_Handler                               /* Hard Fault Handler*/
+    .long    MemManage_Handler                               /* MPU Fault Handler*/
+    .long    BusFault_Handler                                /* Bus Fault Handler*/
+    .long    UsageFault_Handler                              /* Usage Fault Handler*/
+    .long    SecureFault_Handler                             /* Secure Fault Handler*/
+    .long    0                                               /* Reserved*/
+    .long    0                                               /* Reserved*/
+    .long    0                                               /* Reserved*/
+    .long    SVC_Handler                                     /* SVCall Handler*/
+    .long    DebugMon_Handler                                /* Debug Monitor Handler*/
+    .long    0                                               /* Reserved*/
+    .long    PendSV_Handler                                  /* PendSV Handler*/
+    .long    SysTick_Handler                                 /* SysTick Handler*/
+
+                                                            /* External Interrupts*/
+    .long    WDT_BOD_IRQHandler                              /* Windowed watchdog timer, Brownout detect, Flash interrupt */
+    .long    DMA0_IRQHandler                              /* DMA0 controller */
+    .long    GINT0_IRQHandler                              /* GPIO group 0 */
+    .long    GINT1_IRQHandler                              /* GPIO group 1 */
+    .long    PIN_INT0_IRQHandler                              /* Pin interrupt 0 or pattern match engine slice 0 */
+    .long    PIN_INT1_IRQHandler                              /* Pin interrupt 1or pattern match engine slice 1 */
+    .long    PIN_INT2_IRQHandler                              /* Pin interrupt 2 or pattern match engine slice 2 */
+    .long    PIN_INT3_IRQHandler                              /* Pin interrupt 3 or pattern match engine slice 3 */
+    .long    UTICK0_IRQHandler                              /* Micro-tick Timer */
+    .long    MRT0_IRQHandler                              /* Multi-rate timer */
+    .long    CTIMER0_IRQHandler                              /* Standard counter/timer CTIMER0 */
+    .long    CTIMER1_IRQHandler                              /* Standard counter/timer CTIMER1 */
+    .long    SCT0_IRQHandler                              /* SCTimer/PWM */
+    .long    CTIMER3_IRQHandler                              /* Standard counter/timer CTIMER3 */
+    .long    FLEXCOMM0_IRQHandler                              /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    .long    FLEXCOMM1_IRQHandler                              /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    .long    FLEXCOMM2_IRQHandler                              /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    .long    FLEXCOMM3_IRQHandler                              /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    .long    FLEXCOMM4_IRQHandler                              /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    .long    FLEXCOMM5_IRQHandler                              /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    .long    FLEXCOMM6_IRQHandler                              /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    .long    FLEXCOMM7_IRQHandler                              /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    .long    ADC0_IRQHandler                              /* ADC0  */
+    .long    Reserved39_IRQHandler                              /* Reserved interrupt */
+    .long    ACMP_IRQHandler                              /* ACMP  interrupts */
+    .long    Reserved41_IRQHandler                              /* Reserved interrupt */
+    .long    Reserved42_IRQHandler                              /* Reserved interrupt */
+    .long    USB0_NEEDCLK_IRQHandler                              /* USB Activity Wake-up Interrupt */
+    .long    USB0_IRQHandler                              /* USB device */
+    .long    RTC_IRQHandler                              /* RTC alarm and wake-up interrupts */
+    .long    Reserved46_IRQHandler                              /* Reserved interrupt */
+    .long    MAILBOX_IRQHandler                              /* WAKEUP,Mailbox interrupt (present on selected devices) */
+    .long    PIN_INT4_IRQHandler                              /* Pin interrupt 4 or pattern match engine slice 4 int */
+    .long    PIN_INT5_IRQHandler                              /* Pin interrupt 5 or pattern match engine slice 5 int */
+    .long    PIN_INT6_IRQHandler                              /* Pin interrupt 6 or pattern match engine slice 6 int */
+    .long    PIN_INT7_IRQHandler                              /* Pin interrupt 7 or pattern match engine slice 7 int */
+    .long    CTIMER2_IRQHandler                              /* Standard counter/timer CTIMER2 */
+    .long    CTIMER4_IRQHandler                              /* Standard counter/timer CTIMER4 */
+    .long    OS_EVENT_IRQHandler                              /* OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */
+    .long    Reserved55_IRQHandler                              /* Reserved interrupt */
+    .long    Reserved56_IRQHandler                              /* Reserved interrupt */
+    .long    Reserved57_IRQHandler                              /* Reserved interrupt */
+    .long    SDIO_IRQHandler                              /* SD/MMC  */
+    .long    Reserved59_IRQHandler                              /* Reserved interrupt */
+    .long    Reserved60_IRQHandler                              /* Reserved interrupt */
+    .long    Reserved61_IRQHandler                              /* Reserved interrupt */
+    .long    USB1_PHY_IRQHandler                              /* USB1_PHY */
+    .long    USB1_IRQHandler                              /* USB1 interrupt */
+    .long    USB1_NEEDCLK_IRQHandler                              /* USB1 activity */
+    .long    SEC_HYPERVISOR_CALL_IRQHandler                              /* SEC_HYPERVISOR_CALL interrupt */
+    .long    SEC_GPIO_INT0_IRQ0_IRQHandler                              /* SEC_GPIO_INT0_IRQ0 interrupt */
+    .long    SEC_GPIO_INT0_IRQ1_IRQHandler                              /* SEC_GPIO_INT0_IRQ1 interrupt */
+    .long    PLU_IRQHandler                              /* PLU interrupt */
+    .long    SEC_VIO_IRQHandler                              /* SEC_VIO interrupt */
+    .long    HASHCRYPT_IRQHandler                              /* HASHCRYPT interrupt */
+    .long    CASER_IRQHandler                              /* CASPER interrupt */
+    .long    PUF_IRQHandler                              /* PUF interrupt */
+    .long    PQ_IRQHandler                              /* PQ interrupt */
+    .long    DMA1_IRQHandler                              /* DMA1 interrupt */
+    .long    FLEXCOMM8_IRQHandler                              /* Flexcomm Interface 8 (SPI, , FLEXCOMM) */
+    .size    __Vectors, . - __Vectors
+
+    .text
+    .thumb
+
+/* Reset Handler */
+    .thumb_func
+    .align 2
+    .weak    Reset_Handler
+    .type    Reset_Handler, %function
+
+Reset_Handler:
+    cpsid   i               /* Mask interrupts */
+    .equ    VTOR, 0xE000ED08
+    ldr     r0, =VTOR
+    ldr     r1, =__Vectors
+    str     r1, [r0]
+    ldr     r2, [r1]
+    msr     msp, r2
+    ldr     R0, =Image$$ARM_LIB_STACK$$ZI$$Base
+    msr     msplim, R0
+    ldr     r0,=SystemInit
+    blx     r0
+    cpsie   i               /* Unmask interrupts */
+    ldr     r0,=__main
+    bx      r0
+
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+
+    .align  1
+    .thumb_func
+    .weak DefaultISR
+    .type DefaultISR, %function
+DefaultISR:
+    b DefaultISR
+    .size DefaultISR, . - DefaultISR
+
+    .align 1
+    .thumb_func
+    .weak NMI_Handler
+    .type NMI_Handler, %function
+NMI_Handler:
+    ldr   r0,=NMI_Handler
+    bx    r0
+    .size NMI_Handler, . - NMI_Handler
+
+    .align 1
+    .thumb_func
+    .weak HardFault_Handler
+    .type HardFault_Handler, %function
+HardFault_Handler:
+    ldr   r0,=HardFault_Handler
+    bx    r0
+    .size HardFault_Handler, . - HardFault_Handler
+
+    .align 1
+    .thumb_func
+    .weak SVC_Handler
+    .type SVC_Handler, %function
+SVC_Handler:
+    ldr   r0,=SVC_Handler
+    bx    r0
+    .size SVC_Handler, . - SVC_Handler
+
+    .align 1
+    .thumb_func
+    .weak PendSV_Handler
+    .type PendSV_Handler, %function
+PendSV_Handler:
+    ldr   r0,=PendSV_Handler
+    bx    r0
+    .size PendSV_Handler, . - PendSV_Handler
+
+    .align 1
+    .thumb_func
+    .weak SysTick_Handler
+    .type SysTick_Handler, %function
+SysTick_Handler:
+    ldr   r0,=SysTick_Handler
+    bx    r0
+    .size SysTick_Handler, . - SysTick_Handler
+    .align 1
+    .thumb_func
+    .weak WDT_BOD_IRQHandler
+    .type WDT_BOD_IRQHandler, %function
+WDT_BOD_IRQHandler:
+    ldr   r0,=WDT_BOD_DriverIRQHandler
+    bx    r0
+    .size WDT_BOD_IRQHandler, . - WDT_BOD_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMA0_IRQHandler
+    .type DMA0_IRQHandler, %function
+DMA0_IRQHandler:
+    ldr   r0,=DMA0_DriverIRQHandler
+    bx    r0
+    .size DMA0_IRQHandler, . - DMA0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak GINT0_IRQHandler
+    .type GINT0_IRQHandler, %function
+GINT0_IRQHandler:
+    ldr   r0,=GINT0_DriverIRQHandler
+    bx    r0
+    .size GINT0_IRQHandler, . - GINT0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak GINT1_IRQHandler
+    .type GINT1_IRQHandler, %function
+GINT1_IRQHandler:
+    ldr   r0,=GINT1_DriverIRQHandler
+    bx    r0
+    .size GINT1_IRQHandler, . - GINT1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT0_IRQHandler
+    .type PIN_INT0_IRQHandler, %function
+PIN_INT0_IRQHandler:
+    ldr   r0,=PIN_INT0_DriverIRQHandler
+    bx    r0
+    .size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT1_IRQHandler
+    .type PIN_INT1_IRQHandler, %function
+PIN_INT1_IRQHandler:
+    ldr   r0,=PIN_INT1_DriverIRQHandler
+    bx    r0
+    .size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT2_IRQHandler
+    .type PIN_INT2_IRQHandler, %function
+PIN_INT2_IRQHandler:
+    ldr   r0,=PIN_INT2_DriverIRQHandler
+    bx    r0
+    .size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT3_IRQHandler
+    .type PIN_INT3_IRQHandler, %function
+PIN_INT3_IRQHandler:
+    ldr   r0,=PIN_INT3_DriverIRQHandler
+    bx    r0
+    .size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak UTICK0_IRQHandler
+    .type UTICK0_IRQHandler, %function
+UTICK0_IRQHandler:
+    ldr   r0,=UTICK0_DriverIRQHandler
+    bx    r0
+    .size UTICK0_IRQHandler, . - UTICK0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak MRT0_IRQHandler
+    .type MRT0_IRQHandler, %function
+MRT0_IRQHandler:
+    ldr   r0,=MRT0_DriverIRQHandler
+    bx    r0
+    .size MRT0_IRQHandler, . - MRT0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak CTIMER0_IRQHandler
+    .type CTIMER0_IRQHandler, %function
+CTIMER0_IRQHandler:
+    ldr   r0,=CTIMER0_DriverIRQHandler
+    bx    r0
+    .size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak CTIMER1_IRQHandler
+    .type CTIMER1_IRQHandler, %function
+CTIMER1_IRQHandler:
+    ldr   r0,=CTIMER1_DriverIRQHandler
+    bx    r0
+    .size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak SCT0_IRQHandler
+    .type SCT0_IRQHandler, %function
+SCT0_IRQHandler:
+    ldr   r0,=SCT0_DriverIRQHandler
+    bx    r0
+    .size SCT0_IRQHandler, . - SCT0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak CTIMER3_IRQHandler
+    .type CTIMER3_IRQHandler, %function
+CTIMER3_IRQHandler:
+    ldr   r0,=CTIMER3_DriverIRQHandler
+    bx    r0
+    .size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM0_IRQHandler
+    .type FLEXCOMM0_IRQHandler, %function
+FLEXCOMM0_IRQHandler:
+    ldr   r0,=FLEXCOMM0_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM0_IRQHandler, . - FLEXCOMM0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM1_IRQHandler
+    .type FLEXCOMM1_IRQHandler, %function
+FLEXCOMM1_IRQHandler:
+    ldr   r0,=FLEXCOMM1_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM1_IRQHandler, . - FLEXCOMM1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM2_IRQHandler
+    .type FLEXCOMM2_IRQHandler, %function
+FLEXCOMM2_IRQHandler:
+    ldr   r0,=FLEXCOMM2_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM2_IRQHandler, . - FLEXCOMM2_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM3_IRQHandler
+    .type FLEXCOMM3_IRQHandler, %function
+FLEXCOMM3_IRQHandler:
+    ldr   r0,=FLEXCOMM3_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM3_IRQHandler, . - FLEXCOMM3_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM4_IRQHandler
+    .type FLEXCOMM4_IRQHandler, %function
+FLEXCOMM4_IRQHandler:
+    ldr   r0,=FLEXCOMM4_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM4_IRQHandler, . - FLEXCOMM4_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM5_IRQHandler
+    .type FLEXCOMM5_IRQHandler, %function
+FLEXCOMM5_IRQHandler:
+    ldr   r0,=FLEXCOMM5_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM5_IRQHandler, . - FLEXCOMM5_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM6_IRQHandler
+    .type FLEXCOMM6_IRQHandler, %function
+FLEXCOMM6_IRQHandler:
+    ldr   r0,=FLEXCOMM6_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM6_IRQHandler, . - FLEXCOMM6_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM7_IRQHandler
+    .type FLEXCOMM7_IRQHandler, %function
+FLEXCOMM7_IRQHandler:
+    ldr   r0,=FLEXCOMM7_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM7_IRQHandler, . - FLEXCOMM7_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak ADC0_IRQHandler
+    .type ADC0_IRQHandler, %function
+ADC0_IRQHandler:
+    ldr   r0,=ADC0_DriverIRQHandler
+    bx    r0
+    .size ADC0_IRQHandler, . - ADC0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak Reserved39_IRQHandler
+    .type Reserved39_IRQHandler, %function
+Reserved39_IRQHandler:
+    ldr   r0,=Reserved39_DriverIRQHandler
+    bx    r0
+    .size Reserved39_IRQHandler, . - Reserved39_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak ACMP_IRQHandler
+    .type ACMP_IRQHandler, %function
+ACMP_IRQHandler:
+    ldr   r0,=ACMP_DriverIRQHandler
+    bx    r0
+    .size ACMP_IRQHandler, . - ACMP_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak Reserved41_IRQHandler
+    .type Reserved41_IRQHandler, %function
+Reserved41_IRQHandler:
+    ldr   r0,=Reserved41_DriverIRQHandler
+    bx    r0
+    .size Reserved41_IRQHandler, . - Reserved41_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak Reserved42_IRQHandler
+    .type Reserved42_IRQHandler, %function
+Reserved42_IRQHandler:
+    ldr   r0,=Reserved42_DriverIRQHandler
+    bx    r0
+    .size Reserved42_IRQHandler, . - Reserved42_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak USB0_NEEDCLK_IRQHandler
+    .type USB0_NEEDCLK_IRQHandler, %function
+USB0_NEEDCLK_IRQHandler:
+    ldr   r0,=USB0_NEEDCLK_DriverIRQHandler
+    bx    r0
+    .size USB0_NEEDCLK_IRQHandler, . - USB0_NEEDCLK_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak USB0_IRQHandler
+    .type USB0_IRQHandler, %function
+USB0_IRQHandler:
+    ldr   r0,=USB0_DriverIRQHandler
+    bx    r0
+    .size USB0_IRQHandler, . - USB0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak RTC_IRQHandler
+    .type RTC_IRQHandler, %function
+RTC_IRQHandler:
+    ldr   r0,=RTC_DriverIRQHandler
+    bx    r0
+    .size RTC_IRQHandler, . - RTC_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak Reserved46_IRQHandler
+    .type Reserved46_IRQHandler, %function
+Reserved46_IRQHandler:
+    ldr   r0,=Reserved46_DriverIRQHandler
+    bx    r0
+    .size Reserved46_IRQHandler, . - Reserved46_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak MAILBOX_IRQHandler
+    .type MAILBOX_IRQHandler, %function
+MAILBOX_IRQHandler:
+    ldr   r0,=MAILBOX_DriverIRQHandler
+    bx    r0
+    .size MAILBOX_IRQHandler, . - MAILBOX_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT4_IRQHandler
+    .type PIN_INT4_IRQHandler, %function
+PIN_INT4_IRQHandler:
+    ldr   r0,=PIN_INT4_DriverIRQHandler
+    bx    r0
+    .size PIN_INT4_IRQHandler, . - PIN_INT4_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT5_IRQHandler
+    .type PIN_INT5_IRQHandler, %function
+PIN_INT5_IRQHandler:
+    ldr   r0,=PIN_INT5_DriverIRQHandler
+    bx    r0
+    .size PIN_INT5_IRQHandler, . - PIN_INT5_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT6_IRQHandler
+    .type PIN_INT6_IRQHandler, %function
+PIN_INT6_IRQHandler:
+    ldr   r0,=PIN_INT6_DriverIRQHandler
+    bx    r0
+    .size PIN_INT6_IRQHandler, . - PIN_INT6_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PIN_INT7_IRQHandler
+    .type PIN_INT7_IRQHandler, %function
+PIN_INT7_IRQHandler:
+    ldr   r0,=PIN_INT7_DriverIRQHandler
+    bx    r0
+    .size PIN_INT7_IRQHandler, . - PIN_INT7_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak CTIMER2_IRQHandler
+    .type CTIMER2_IRQHandler, %function
+CTIMER2_IRQHandler:
+    ldr   r0,=CTIMER2_DriverIRQHandler
+    bx    r0
+    .size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak CTIMER4_IRQHandler
+    .type CTIMER4_IRQHandler, %function
+CTIMER4_IRQHandler:
+    ldr   r0,=CTIMER4_DriverIRQHandler
+    bx    r0
+    .size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak OS_EVENT_IRQHandler
+    .type OS_EVENT_IRQHandler, %function
+OS_EVENT_IRQHandler:
+    ldr   r0,=OS_EVENT_DriverIRQHandler
+    bx    r0
+    .size OS_EVENT_IRQHandler, . - OS_EVENT_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak Reserved55_IRQHandler
+    .type Reserved55_IRQHandler, %function
+Reserved55_IRQHandler:
+    ldr   r0,=Reserved55_DriverIRQHandler
+    bx    r0
+    .size Reserved55_IRQHandler, . - Reserved55_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak Reserved56_IRQHandler
+    .type Reserved56_IRQHandler, %function
+Reserved56_IRQHandler:
+    ldr   r0,=Reserved56_DriverIRQHandler
+    bx    r0
+    .size Reserved56_IRQHandler, . - Reserved56_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak Reserved57_IRQHandler
+    .type Reserved57_IRQHandler, %function
+Reserved57_IRQHandler:
+    ldr   r0,=Reserved57_DriverIRQHandler
+    bx    r0
+    .size Reserved57_IRQHandler, . - Reserved57_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak SDIO_IRQHandler
+    .type SDIO_IRQHandler, %function
+SDIO_IRQHandler:
+    ldr   r0,=SDIO_DriverIRQHandler
+    bx    r0
+    .size SDIO_IRQHandler, . - SDIO_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak Reserved59_IRQHandler
+    .type Reserved59_IRQHandler, %function
+Reserved59_IRQHandler:
+    ldr   r0,=Reserved59_DriverIRQHandler
+    bx    r0
+    .size Reserved59_IRQHandler, . - Reserved59_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak Reserved60_IRQHandler
+    .type Reserved60_IRQHandler, %function
+Reserved60_IRQHandler:
+    ldr   r0,=Reserved60_DriverIRQHandler
+    bx    r0
+    .size Reserved60_IRQHandler, . - Reserved60_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak Reserved61_IRQHandler
+    .type Reserved61_IRQHandler, %function
+Reserved61_IRQHandler:
+    ldr   r0,=Reserved61_DriverIRQHandler
+    bx    r0
+    .size Reserved61_IRQHandler, . - Reserved61_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak USB1_PHY_IRQHandler
+    .type USB1_PHY_IRQHandler, %function
+USB1_PHY_IRQHandler:
+    ldr   r0,=USB1_PHY_DriverIRQHandler
+    bx    r0
+    .size USB1_PHY_IRQHandler, . - USB1_PHY_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak USB1_IRQHandler
+    .type USB1_IRQHandler, %function
+USB1_IRQHandler:
+    ldr   r0,=USB1_DriverIRQHandler
+    bx    r0
+    .size USB1_IRQHandler, . - USB1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak USB1_NEEDCLK_IRQHandler
+    .type USB1_NEEDCLK_IRQHandler, %function
+USB1_NEEDCLK_IRQHandler:
+    ldr   r0,=USB1_NEEDCLK_DriverIRQHandler
+    bx    r0
+    .size USB1_NEEDCLK_IRQHandler, . - USB1_NEEDCLK_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak SEC_HYPERVISOR_CALL_IRQHandler
+    .type SEC_HYPERVISOR_CALL_IRQHandler, %function
+SEC_HYPERVISOR_CALL_IRQHandler:
+    ldr   r0,=SEC_HYPERVISOR_CALL_DriverIRQHandler
+    bx    r0
+    .size SEC_HYPERVISOR_CALL_IRQHandler, . - SEC_HYPERVISOR_CALL_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak SEC_GPIO_INT0_IRQ0_IRQHandler
+    .type SEC_GPIO_INT0_IRQ0_IRQHandler, %function
+SEC_GPIO_INT0_IRQ0_IRQHandler:
+    ldr   r0,=SEC_GPIO_INT0_IRQ0_DriverIRQHandler
+    bx    r0
+    .size SEC_GPIO_INT0_IRQ0_IRQHandler, . - SEC_GPIO_INT0_IRQ0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak SEC_GPIO_INT0_IRQ1_IRQHandler
+    .type SEC_GPIO_INT0_IRQ1_IRQHandler, %function
+SEC_GPIO_INT0_IRQ1_IRQHandler:
+    ldr   r0,=SEC_GPIO_INT0_IRQ1_DriverIRQHandler
+    bx    r0
+    .size SEC_GPIO_INT0_IRQ1_IRQHandler, . - SEC_GPIO_INT0_IRQ1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PLU_IRQHandler
+    .type PLU_IRQHandler, %function
+PLU_IRQHandler:
+    ldr   r0,=PLU_DriverIRQHandler
+    bx    r0
+    .size PLU_IRQHandler, . - PLU_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak SEC_VIO_IRQHandler
+    .type SEC_VIO_IRQHandler, %function
+SEC_VIO_IRQHandler:
+    ldr   r0,=SEC_VIO_DriverIRQHandler
+    bx    r0
+    .size SEC_VIO_IRQHandler, . - SEC_VIO_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak HASHCRYPT_IRQHandler
+    .type HASHCRYPT_IRQHandler, %function
+HASHCRYPT_IRQHandler:
+    ldr   r0,=HASHCRYPT_DriverIRQHandler
+    bx    r0
+    .size HASHCRYPT_IRQHandler, . - HASHCRYPT_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak CASER_IRQHandler
+    .type CASER_IRQHandler, %function
+CASER_IRQHandler:
+    ldr   r0,=CASER_DriverIRQHandler
+    bx    r0
+    .size CASER_IRQHandler, . - CASER_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PUF_IRQHandler
+    .type PUF_IRQHandler, %function
+PUF_IRQHandler:
+    ldr   r0,=PUF_DriverIRQHandler
+    bx    r0
+    .size PUF_IRQHandler, . - PUF_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak PQ_IRQHandler
+    .type PQ_IRQHandler, %function
+PQ_IRQHandler:
+    ldr   r0,=PQ_DriverIRQHandler
+    bx    r0
+    .size PQ_IRQHandler, . - PQ_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMA1_IRQHandler
+    .type DMA1_IRQHandler, %function
+DMA1_IRQHandler:
+    ldr   r0,=DMA1_DriverIRQHandler
+    bx    r0
+    .size DMA1_IRQHandler, . - DMA1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak FLEXCOMM8_IRQHandler
+    .type FLEXCOMM8_IRQHandler, %function
+FLEXCOMM8_IRQHandler:
+    ldr   r0,=FLEXCOMM8_DriverIRQHandler
+    bx    r0
+    .size FLEXCOMM8_IRQHandler, . - FLEXCOMM8_IRQHandler
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro def_irq_handler  handler_name
+    .weak \handler_name
+    .set  \handler_name, DefaultISR
+    .endm
+/* Exception Handlers */
+    def_irq_handler    MemManage_Handler
+    def_irq_handler    BusFault_Handler
+    def_irq_handler    UsageFault_Handler
+    def_irq_handler    SecureFault_Handler
+    def_irq_handler    DebugMon_Handler
+    def_irq_handler    WDT_BOD_DriverIRQHandler              /* Windowed watchdog timer, Brownout detect, Flash interrupt */
+    def_irq_handler    DMA0_DriverIRQHandler              /* DMA0 controller */
+    def_irq_handler    GINT0_DriverIRQHandler              /* GPIO group 0 */
+    def_irq_handler    GINT1_DriverIRQHandler              /* GPIO group 1 */
+    def_irq_handler    PIN_INT0_DriverIRQHandler              /* Pin interrupt 0 or pattern match engine slice 0 */
+    def_irq_handler    PIN_INT1_DriverIRQHandler              /* Pin interrupt 1or pattern match engine slice 1 */
+    def_irq_handler    PIN_INT2_DriverIRQHandler              /* Pin interrupt 2 or pattern match engine slice 2 */
+    def_irq_handler    PIN_INT3_DriverIRQHandler              /* Pin interrupt 3 or pattern match engine slice 3 */
+    def_irq_handler    UTICK0_DriverIRQHandler              /* Micro-tick Timer */
+    def_irq_handler    MRT0_DriverIRQHandler              /* Multi-rate timer */
+    def_irq_handler    CTIMER0_DriverIRQHandler              /* Standard counter/timer CTIMER0 */
+    def_irq_handler    CTIMER1_DriverIRQHandler              /* Standard counter/timer CTIMER1 */
+    def_irq_handler    SCT0_DriverIRQHandler              /* SCTimer/PWM */
+    def_irq_handler    CTIMER3_DriverIRQHandler              /* Standard counter/timer CTIMER3 */
+    def_irq_handler    FLEXCOMM0_DriverIRQHandler              /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    def_irq_handler    FLEXCOMM1_DriverIRQHandler              /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    def_irq_handler    FLEXCOMM2_DriverIRQHandler              /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    def_irq_handler    FLEXCOMM3_DriverIRQHandler              /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    def_irq_handler    FLEXCOMM4_DriverIRQHandler              /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    def_irq_handler    FLEXCOMM5_DriverIRQHandler              /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    def_irq_handler    FLEXCOMM6_DriverIRQHandler              /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    def_irq_handler    FLEXCOMM7_DriverIRQHandler              /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */
+    def_irq_handler    ADC0_DriverIRQHandler              /* ADC0  */
+    def_irq_handler    Reserved39_DriverIRQHandler              /* Reserved interrupt */
+    def_irq_handler    ACMP_DriverIRQHandler              /* ACMP  interrupts */
+    def_irq_handler    Reserved41_DriverIRQHandler              /* Reserved interrupt */
+    def_irq_handler    Reserved42_DriverIRQHandler              /* Reserved interrupt */
+    def_irq_handler    USB0_NEEDCLK_DriverIRQHandler              /* USB Activity Wake-up Interrupt */
+    def_irq_handler    USB0_DriverIRQHandler              /* USB device */
+    def_irq_handler    RTC_DriverIRQHandler              /* RTC alarm and wake-up interrupts */
+    def_irq_handler    Reserved46_DriverIRQHandler              /* Reserved interrupt */
+    def_irq_handler    MAILBOX_DriverIRQHandler              /* WAKEUP,Mailbox interrupt (present on selected devices) */
+    def_irq_handler    PIN_INT4_DriverIRQHandler              /* Pin interrupt 4 or pattern match engine slice 4 int */
+    def_irq_handler    PIN_INT5_DriverIRQHandler              /* Pin interrupt 5 or pattern match engine slice 5 int */
+    def_irq_handler    PIN_INT6_DriverIRQHandler              /* Pin interrupt 6 or pattern match engine slice 6 int */
+    def_irq_handler    PIN_INT7_DriverIRQHandler              /* Pin interrupt 7 or pattern match engine slice 7 int */
+    def_irq_handler    CTIMER2_DriverIRQHandler              /* Standard counter/timer CTIMER2 */
+    def_irq_handler    CTIMER4_DriverIRQHandler              /* Standard counter/timer CTIMER4 */
+    def_irq_handler    OS_EVENT_DriverIRQHandler              /* OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */
+    def_irq_handler    Reserved55_DriverIRQHandler              /* Reserved interrupt */
+    def_irq_handler    Reserved56_DriverIRQHandler              /* Reserved interrupt */
+    def_irq_handler    Reserved57_DriverIRQHandler              /* Reserved interrupt */
+    def_irq_handler    SDIO_DriverIRQHandler              /* SD/MMC  */
+    def_irq_handler    Reserved59_DriverIRQHandler              /* Reserved interrupt */
+    def_irq_handler    Reserved60_DriverIRQHandler              /* Reserved interrupt */
+    def_irq_handler    Reserved61_DriverIRQHandler              /* Reserved interrupt */
+    def_irq_handler    USB1_PHY_DriverIRQHandler              /* USB1_PHY */
+    def_irq_handler    USB1_DriverIRQHandler              /* USB1 interrupt */
+    def_irq_handler    USB1_NEEDCLK_DriverIRQHandler              /* USB1 activity */
+    def_irq_handler    SEC_HYPERVISOR_CALL_DriverIRQHandler              /* SEC_HYPERVISOR_CALL interrupt */
+    def_irq_handler    SEC_GPIO_INT0_IRQ0_DriverIRQHandler              /* SEC_GPIO_INT0_IRQ0 interrupt */
+    def_irq_handler    SEC_GPIO_INT0_IRQ1_DriverIRQHandler              /* SEC_GPIO_INT0_IRQ1 interrupt */
+    def_irq_handler    PLU_DriverIRQHandler              /* PLU interrupt */
+    def_irq_handler    SEC_VIO_DriverIRQHandler              /* SEC_VIO interrupt */
+    def_irq_handler    HASHCRYPT_DriverIRQHandler              /* HASHCRYPT interrupt */
+    def_irq_handler    CASER_DriverIRQHandler              /* CASPER interrupt */
+    def_irq_handler    PUF_DriverIRQHandler              /* PUF interrupt */
+    def_irq_handler    PQ_DriverIRQHandler              /* PQ interrupt */
+    def_irq_handler    DMA1_DriverIRQHandler              /* DMA1 interrupt */
+    def_irq_handler    FLEXCOMM8_DriverIRQHandler              /* Flexcomm Interface 8 (SPI, , FLEXCOMM) */
+
+    .end

CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/RTE/USB/USBD_Config_0.c → CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/USB/USBD_Config_0.c

@@ -19,7 +19,7 @@
 // <h>USB Device 0
 //   <o>Connect to hardware via Driver_USBD# <0-255>
 //   <i>Select driver control block for hardware interface.
-#define USBD0_PORT                      0
+#define USBD0_PORT                      1
 
 //   <o.0>High-speed
 //   <i>Enable High-speed functionality (if device supports it).
@@ -38,7 +38,7 @@
 
 //     <o.0..15>Product ID <0x0000-0xFFFF>
 //     <i>Product ID assigned by manufacturer (idProduct).
-#define USBD0_DEV_DESC_IDPRODUCT        0xF001
+#define USBD0_DEV_DESC_IDPRODUCT        0xF00B
 
 //     <o.0..15>Device Release Number <0x0000-0xFFFF>
 //     <i>Device Release Number in binary-coded decimal (bcdDevice)
@@ -75,7 +75,7 @@
 
 //     <s.126>Product String
 //     <i>String Descriptor describing Product.
-#define USBD0_STR_DESC_PROD             L"LPC-Link2 CMSIS-DAP"
+#define USBD0_STR_DESC_PROD             L"MCU-LINK"
 
 //     <e.0>Serial Number String
 //     <i>Enable Serial Number String.
@@ -98,7 +98,7 @@
 //   <i>These settings are used to create the Microsoft OS Descriptors.
 //     <e.0>OS String
 //     <i>Enable creation of Microsoft OS String and Extended Compat ID OS Feature Descriptors.
-#define USBD0_OS_DESC_EN                0
+#define USBD0_OS_DESC_EN                1
 
 //       <o.0..7>Vendor Code <0x01-0xFF>
 //       <i>Specifies Vendor Code used to retrieve OS Feature Descriptors.
@@ -115,7 +115,7 @@
 //   <h>OS Resources Settings
 //   <i>These settings are used to optimize usage of OS resources.
 //     <o>Core Thread Stack Size <64-65536>
-#define USBD0_CORE_THREAD_STACK_SIZE    512
+#define USBD0_CORE_THREAD_STACK_SIZE    1024
 
 //        Core Thread Priority
 #define USBD0_CORE_THREAD_PRIORITY      osPriorityAboveNormal

CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/USB/USBD_Config_CDC_0.h

@@ -0,0 +1,364 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::USB:Device
+ * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    USBD_Config_CDC_0.h
+ * Purpose: USB Device Communication Device Class (CDC) Configuration
+ * Rev.:    V5.2.0
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h>USB Device: Communication Device Class (CDC) 0
+//   <o>Assign Device Class to USB Device # <0-3>
+//   <i>Select USB Device that is used for this Device Class instance
+#define USBD_CDC0_DEV                    0
+
+//   <o>Communication Class Subclass
+//   <i>Specifies the model used by the CDC class.
+//     <2=>Abstract Control Model (ACM)
+//     <13=>Network Control Model (NCM)
+#define USBD_CDC0_SUBCLASS               2
+
+//   <o>Communication Class Protocol
+//   <i>Specifies the protocol used by the CDC class.
+//     <0=>No protocol (Virtual COM)
+//     <255=>Vendor-specific (RNDIS)
+#define USBD_CDC0_PROTOCOL               0
+
+//   <h>Interrupt Endpoint Settings
+//   <i>By default, the settings match the first USB Class instance in a USB Device.
+//   <i>Endpoint conflicts are flagged by compile-time error messages.
+
+//     <o.0..3>Interrupt IN Endpoint Number
+//               <1=>1   <2=>2   <3=>3   <4=>4   <5=>5   <6=>6   <7=>7
+//       <8=>8   <9=>9   <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
+#define USBD_CDC0_EP_INT_IN              3
+
+
+//     <h>Endpoint Settings
+//       <i>Parameters are used to create Endpoint Descriptors
+//       <i>and for memory allocation in the USB component.
+
+//       <h>Full/Low-speed (High-speed disabled)
+//       <i>Parameters apply when High-speed is disabled in USBD_Config_n.c
+//         <o.0..6>Maximum Endpoint Packet Size (in bytes) <0-64>
+//         <i>Specifies the physical packet size used for information exchange.
+//         <i>Maximum value is 64.
+#define USBD_CDC0_WMAXPACKETSIZE         16
+
+//         <o.0..7>Endpoint polling Interval (in ms) <1-255>
+//         <i>Specifies the frequency of requests initiated by USB Host for
+//         <i>getting the notification.
+#define USBD_CDC0_BINTERVAL              2
+
+//       </h>
+
+//       <h>High-speed
+//       <i>Parameters apply when High-speed is enabled in USBD_Config_n.c
+//
+//         <o.0..10>Maximum Endpoint Packet Size (in bytes) <0-1024>
+//         <i>Specifies the physical packet size used for information exchange.
+//         <i>Maximum value is 1024.
+//         <o.11..12>Additional transactions per microframe
+//         <i>Additional transactions improve communication performance.
+//           <0=>None <1=>1 additional <2=>2 additional
+#define USBD_CDC0_HS_WMAXPACKETSIZE      16
+
+//         <o.0..4>Endpoint polling Interval (in 125 us intervals)
+//         <i>Specifies the frequency of requests initiated by USB Host for
+//         <i>getting the notification.
+//           <1=>    1 <2=>    2 <3=>     4 <4=>     8
+//           <5=>   16 <6=>   32 <7=>    64 <8=>   128
+//           <9=>  256 <10=> 512 <11=> 1024 <12=> 2048
+//           <13=>4096 <14=>8192 <15=>16384 <16=>32768
+#define USBD_CDC0_HS_BINTERVAL           2
+
+//       </h>
+//     </h>
+//   </h>
+
+
+//   <h>Bulk Endpoint Settings
+//   <i>By default, the settings match the first USB Class instance in a USB Device.
+//   <i>Endpoint conflicts are flagged by compile-time error messages.
+
+//     <o.0..3>Bulk IN Endpoint Number
+//               <1=>1   <2=>2   <3=>3   <4=>4   <5=>5   <6=>6   <7=>7
+//       <8=>8   <9=>9   <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
+#define USBD_CDC0_EP_BULK_IN             4
+
+//     <o.0..3>Bulk OUT Endpoint Number
+//               <1=>1   <2=>2   <3=>3   <4=>4   <5=>5   <6=>6   <7=>7
+//       <8=>8   <9=>9   <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
+#define USBD_CDC0_EP_BULK_OUT            4
+
+
+//     <h>Endpoint Settings
+//       <i>Parameters are used to create USB Descriptors and for memory
+//       <i>allocation in the USB component.
+//
+//       <h>Full/Low-speed (High-speed disabled)
+//       <i>Parameters apply when High-speed is disabled in USBD_Config_n.c
+//         <o.0..6>Maximum Endpoint Packet Size (in bytes) <8=>8 <16=>16 <32=>32 <64=>64
+//         <i>Specifies the physical packet size used for information exchange.
+//         <i>Maximum value is 64.
+#define USBD_CDC0_WMAXPACKETSIZE1        64
+
+//       </h>
+
+//       <h>High-speed
+//       <i>Parameters apply when High-speed is enabled in USBD_Config_n.c
+//
+//         <o.0..9>Maximum Endpoint Packet Size (in bytes) <512=>512
+//         <i>Specifies the physical packet size used for information exchange.
+//         <i>Only available value is 512.
+#define USBD_CDC0_HS_WMAXPACKETSIZE1     512
+
+//         <o.0..7>Maximum NAK Rate <0-255>
+//         <i>Specifies the interval in which Bulk Endpoint can NAK.
+//         <i>Value of 0 indicates that Bulk Endpoint never NAKs.
+#define USBD_CDC0_HS_BINTERVAL1          0
+
+//       </h>
+//     </h>
+//   </h>
+
+//   <h>Communication Device Class Settings
+//   <i>Parameters are used to create USB Descriptors and for memory allocation
+//   <i>in the USB component.
+//
+//     <s.126>Communication Class Interface String
+#define USBD_CDC0_CIF_STR_DESC           L"USB_CDC0_0"
+
+//     <s.126>Data Class Interface String
+#define USBD_CDC0_DIF_STR_DESC           L"USB_CDC0_1"
+
+//     <h>Abstract Control Model Settings
+
+//       <h>Call Management Capabilities
+//       <i>Specifies which call management functionality is supported.
+//         <o.1>Call Management channel
+//           <0=>Communication Class Interface only
+//           <1=>Communication and Data Class Interface
+//         <o.0>Device Call Management handling
+//           <0=>None
+//           <1=>All
+//       </h>
+#define USBD_CDC0_ACM_CM_BM_CAPABILITIES 0x03
+
+//       <h>Abstract Control Management Capabilities
+//       <i>Specifies which abstract control management functionality is supported.
+//         <o.3>D3 bit
+//           <i>Enabled = Supports the notification Network_Connection
+//         <o.2>D2 bit
+//           <i>Enabled = Supports the request Send_Break
+//         <o.1>D1 bit
+//           <i>Enabled = Supports the following requests: Set_Line_Coding, Get_Line_Coding,
+//           <i> Set_Control_Line_State, and notification Serial_State
+//         <o.0>D0 bit
+//           <i>Enabled = Supports the following requests: Set_Comm_Feature, Clear_Comm_Feature and Get_Comm_Feature
+//       </h>
+#define USBD_CDC0_ACM_ACM_BM_CAPABILITIES 0x06
+
+//       <o>Maximum Communication Device Send Buffer Size
+//       <i>Specifies size of buffer used for sending of data to USB Host.
+//         <8=>      8 Bytes <16=>    16 Bytes <32=>    32 Bytes <64=>      64 Bytes
+//         <128=>  128 Bytes <256=>  256 Bytes <512=>  512 Bytes <1024=>  1024 Bytes
+//         <2048=>2048 Bytes <4096=>4096 Bytes <8192=>8192 Bytes <16384=>16384 Bytes
+#define USBD_CDC0_ACM_SEND_BUF_SIZE      1024
+
+//       <o>Maximum Communication Device Receive Buffer Size
+//       <i>Specifies size of buffer used for receiving of data from USB Host.
+//       <i>Minimum size must be twice as large as Maximum Packet Size for Bulk OUT Endpoint.
+//       <i>Suggested size is three or more times larger then Maximum Packet Size for Bulk OUT Endpoint.
+//         <8=>      8 Bytes <16=>    16 Bytes <32=>    32 Bytes <64=>      64 Bytes
+//         <128=>  128 Bytes <256=>  256 Bytes <512=>  512 Bytes <1024=>  1024 Bytes
+//         <2048=>2048 Bytes <4096=>4096 Bytes <8192=>8192 Bytes <16384=>16384 Bytes
+#define USBD_CDC0_ACM_RECEIVE_BUF_SIZE   2048
+
+//     </h>
+
+//     <h>Network Control Model Settings
+
+//       <s.12>MAC Address String
+//       <i>Specifies 48-bit Ethernet MAC address.
+#define USBD_CDC0_NCM_MAC_ADDRESS        L"1E306CA2455E"
+
+//       <h>Ethernet Statistics
+//       <i>Specifies Ethernet statistic functions supported.
+//         <o.0>XMIT_OK
+//         <i>Frames transmitted without errors
+//         <o.1>RVC_OK
+//         <i>Frames received without errors
+//         <o.2>XMIT_ERROR
+//         <i>Frames not transmitted, or transmitted with errors
+//         <o.3>RCV_ERROR
+//         <i>Frames received with errors that are not delivered to the USB host.
+//         <o.4>RCV_NO_BUFFER
+//         <i>Frame missed, no buffers
+//         <o.5>DIRECTED_BYTES_XMIT
+//         <i>Directed bytes transmitted without errors
+//         <o.6>DIRECTED_FRAMES_XMIT
+//         <i>Directed frames transmitted without errors
+//         <o.7>MULTICAST_BYTES_XMIT
+//         <i>Multicast bytes transmitted without errors
+//         <o.8>MULTICAST_FRAMES_XMIT
+//         <i>Multicast frames transmitted without errors
+//         <o.9>BROADCAST_BYTES_XMIT
+//         <i>Broadcast bytes transmitted without errors
+//         <o.10>BROADCAST_FRAMES_XMIT
+//         <i>Broadcast frames transmitted without errors
+//         <o.11>DIRECTED_BYTES_RCV
+//         <i>Directed bytes received without errors
+//         <o.12>DIRECTED_FRAMES_RCV
+//         <i>Directed frames received without errors
+//         <o.13>MULTICAST_BYTES_RCV
+//         <i>Multicast bytes received without errors
+//         <o.14>MULTICAST_FRAMES_RCV
+//         <i>Multicast frames received without errors
+//         <o.15>BROADCAST_BYTES_RCV
+//         <i>Broadcast bytes received without errors
+//         <o.16>BROADCAST_FRAMES_RCV
+//         <i>Broadcast frames received without errors
+//         <o.17>RCV_CRC_ERROR
+//         <i>Frames received with circular redundancy check (CRC) or frame check sequence (FCS) error
+//         <o.18>TRANSMIT_QUEUE_LENGTH
+//         <i>Length of transmit queue
+//         <o.19>RCV_ERROR_ALIGNMENT
+//         <i>Frames received with alignment error
+//         <o.20>XMIT_ONE_COLLISION
+//         <i>Frames transmitted with one collision
+//         <o.21>XMIT_MORE_COLLISIONS
+//         <i>Frames transmitted with more than one collision
+//         <o.22>XMIT_DEFERRED
+//         <i>Frames transmitted after deferral
+//         <o.23>XMIT_MAX_COLLISIONS
+//         <i>Frames not transmitted due to collisions
+//         <o.24>RCV_OVERRUN
+//         <i>Frames not received due to overrun
+//         <o.25>XMIT_UNDERRUN
+//         <i>Frames not transmitted due to underrun
+//         <o.26>XMIT_HEARTBEAT_FAILURE
+//         <i>Frames transmitted with heartbeat failure
+//         <o.27>XMIT_TIMES_CRS_LOST
+//         <i>Times carrier sense signal lost during transmission
+//         <o.28>XMIT_LATE_COLLISIONS
+//         <i>Late collisions detected
+//       </h>
+#define USBD_CDC0_NCM_BM_ETHERNET_STATISTICS     0x00000003
+
+//       <o>Maximum Segment Size
+//       <i>Specifies maximum segment size that Ethernet device is capable of supporting.
+//       <i>Typically 1514 bytes.
+#define USBD_CDC0_NCM_W_MAX_SEGMENT_SIZE         1514
+
+//       <o.15>Multicast Filtering <0=>Perfect (no hashing) <1=>Imperfect (hashing)
+//       <i>Specifies multicast filtering type.
+//       <o.0..14>Number of Multicast Filters
+//       <i>Specifies number of multicast filters that can be configured by the USB Host.
+#define USBD_CDC0_NCM_W_NUMBER_MC_FILTERS        1
+
+//       <o.0..7>Number of Power Filters
+//       <i>Specifies number of pattern filters that are available for causing wake-up of the USB Host.
+#define USBD_CDC0_NCM_B_NUMBER_POWER_FILTERS     0
+
+//       <h>Network Capabilities
+//       <i>Specifies which functions are supported.
+//         <o.4>SetCrcMode/GetCrcMode
+//         <o.3>SetMaxDatagramSize/GetMaxDatagramSize
+//         <o.1>SetNetAddress/GetNetAddress
+//         <o.0>SetEthernetPacketFilter
+//       </h>
+#define USBD_CDC0_NCM_BM_NETWORK_CAPABILITIES    0x1B
+
+//       <h>NTB Parameters
+//       <i>Specifies NTB parameters reported by GetNtbParameters function.
+
+//         <h>NTB Formats Supported (bmNtbFormatsSupported)
+//         <i>Specifies NTB formats supported.
+//           <o.0>16-bit NTB (always supported)
+//           <o.1>32-bit NTB
+//         </h>
+#define USBD_CDC0_NCM_BM_NTB_FORMATS_SUPPORTED   0x0001
+
+//         <h>IN Data Pipe
+//
+//           <o>Maximum NTB Size (dwNtbInMaxSize)
+//           <i>Specifies maximum IN NTB size in bytes.
+#define USBD_CDC0_NCM_DW_NTB_IN_MAX_SIZE         4096
+
+//           <o.0..15>NTB Datagram Payload Alignment Divisor (wNdpInDivisor)
+//           <i>Specifies divisor used for IN NTB Datagram payload alignment.
+#define USBD_CDC0_NCM_W_NDP_IN_DIVISOR           4
+
+//           <o.0..15>NTB Datagram Payload Alignment Remainder (wNdpInPayloadRemainder)
+//           <i>Specifies remainder used to align input datagram payload within the NTB.
+//           <i>(Payload Offset) % (wNdpInDivisor) = wNdpInPayloadRemainder
+#define USBD_CDC0_NCM_W_NDP_IN_PAYLOAD_REMINDER  0
+
+//           <o.0..15>NDP Alignment Modulus in NTB (wNdpInAlignment)
+//           <i>Specifies NDP alignment modulus for NTBs on the IN pipe.
+//           <i>Shall be power of 2, and shall be at least 4.
+#define USBD_CDC0_NCM_W_NDP_IN_ALIGNMENT         4
+
+//         </h>
+
+//         <h>OUT Data Pipe
+//
+//           <o>Maximum NTB Size (dwNtbOutMaxSize)
+//           <i>Specifies maximum OUT NTB size in bytes.
+#define USBD_CDC0_NCM_DW_NTB_OUT_MAX_SIZE        4096
+
+//           <o.0..15>NTB Datagram Payload Alignment Divisor (wNdpOutDivisor)
+//           <i>Specifies divisor used for OUT NTB Datagram payload alignment.
+#define USBD_CDC0_NCM_W_NDP_OUT_DIVISOR          4
+
+//           <o.0..15>NTB Datagram Payload Alignment Remainder (wNdpOutPayloadRemainder)
+//           <i>Specifies remainder used to align output datagram payload within the NTB.
+//           <i>(Payload Offset) % (wNdpOutDivisor) = wNdpOutPayloadRemainder
+#define USBD_CDC0_NCM_W_NDP_OUT_PAYLOAD_REMINDER 0
+
+//           <o.0..15>NDP Alignment Modulus in NTB (wNdpOutAlignment)
+//           <i>Specifies NDP alignment modulus for NTBs on the IN pipe.
+//           <i>Shall be power of 2, and shall be at least 4.
+#define USBD_CDC0_NCM_W_NDP_OUT_ALIGNMENT        4
+
+//         </h>
+
+//       </h>
+
+//       <o.0>Raw Data Access API
+//       <i>Enables or disables Raw Data Access API.
+#define USBD_CDC0_NCM_RAW_ENABLE         0
+
+//       <o>IN NTB Data Buffering <1=>Single Buffer <2=>Double Buffer
+//       <i>Specifies buffering used for sending data to USB Host.
+//       <i>Not used when RAW Data Access API is enabled.
+#define USBD_CDC0_NCM_NTB_IN_BUF_CNT     1
+
+//       <o>OUT NTB Data Buffering <1=>Single Buffer <2=>Double Buffer
+//       <i>Specifies buffering used for receiving data from USB Host.
+//       <i>Not used when RAW Data Access API is enabled.
+#define USBD_CDC0_NCM_NTB_OUT_BUF_CNT    1
+
+//     </h>
+
+//   </h>
+
+//   <h>OS Resources Settings
+//   <i>These settings are used to optimize usage of OS resources.
+//     <o>Communication Device Class Interrupt Endpoint Thread Stack Size <64-65536>
+#define USBD_CDC0_INT_THREAD_STACK_SIZE  512
+
+//        Communication Device Class Interrupt Endpoint Thread Priority
+#define USBD_CDC0_INT_THREAD_PRIORITY    osPriorityAboveNormal
+
+//     <o>Communication Device Class Bulk Endpoints Thread Stack Size <64-65536>
+#define USBD_CDC0_BULK_THREAD_STACK_SIZE 512
+
+//        Communication Device Class Bulk Endpoints Thread Priority
+#define USBD_CDC0_BULK_THREAD_PRIORITY   osPriorityAboveNormal
+
+//   </h>
+// </h>

CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/USB/USBD_Config_CustomClass_0.h

@@ -0,0 +1,3771 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::USB:Device
+ * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    USBD_Config_CustomClass_0.h
+ * Purpose: USB Device Custom Class Configuration
+ * Rev.:    V5.2.0
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h>USB Device: Custom Class 0
+// <i>Custom Class can be used to make support for Standard or Vendor-Specific Class
+//   <o>Assign Device Class to USB Device # <0-3>
+//   <i>Select USB Device that is used for this Device Class instance
+#define USBD_CUSTOM_CLASS0_DEV                                     0
+
+//   <e0.0>Interface Association
+//   <i>Used for grouping of multiple interfaces to a single class.
+#define USBD_CUSTOM_CLASS0_IAD_EN                                  0
+
+//       <o.0..7>Class Code
+//         <i>Class Codes are defined by USB-IF. For more information refer to
+//         <i>http://www.usb.org/developers/defined_class.
+//         <0x00=>0x00: Indicate a Null Class Code triple
+//         <0x01=>0x01: Audio
+//         <0x02=>0x02: Communications and CDC Control
+//         <0x03=>0x03: HID (Human Interface Device)
+//         <0x05=>0x05: Physical
+//         <0x06=>0x06: Image
+//         <0x07=>0x07: Printer
+//         <0x08=>0x08: Mass Storage
+//         <0x0A=>0x0A: CDC-Data
+//         <0x0B=>0x0B: Smart Card
+//         <0x0D=>0x0D: Content Security
+//         <0x0E=>0x0E: Video
+//         <0x0F=>0x0F: Personal Healthcare
+//         <0x10=>0x10: Audio/Video Devices
+//         <0xDC=>0xDC: Diagnostic Device
+//         <0xE0=>0xE0: Wireless Controller
+//         <0xEF=>0xEF: Miscellaneous
+//         <0xFE=>0xFE: Application Specific
+//         <0xFF=>0xFF: Vendor Specific
+#define USBD_CUSTOM_CLASS0_IAD_CLASS                               0xFF
+
+//       <o.0..7>Subclass Code <0x00-0xFF>
+//       <i>The possible values depend on the Class Code:
+//       <i>Class Code 0x00: Subclass Code must be 0
+//       <i>Class Code 0x01 .. 0xFE: Subclass Code is defined by USB-IF
+//       <i>Class Code 0xFF: Subclass Code can be 0x00 .. 0xFF
+#define USBD_CUSTOM_CLASS0_IAD_SUBCLASS                            0x00
+
+//       <o.0..7>Protocol Code <0x00-0xFF>
+//       <i>The Protocol Code value defines the protocol used on this interface:
+//       <i>Protocol Code 0x00: class-specific protocol not used
+//       <i>Protocol Code 0x01 .. 0xFE: class-specific protocol used
+//       <i>Protocol Code 0xFF: vendor-specific protocol used
+#define USBD_CUSTOM_CLASS0_IAD_PROTOCOL                            0x00
+
+//   </e>
+
+
+//   <e>Interface
+#define USBD_CUSTOM_CLASS0_IF0_EN                                  1
+
+//     <h>Interface Settings
+//     <i>The Interface Settings are used to create the Interface Descriptor.
+//     <i>Refer to USB - USB Concepts - USB Descriptor in the MDK Components
+//     <i>User's Guide for more information about the Interface Descriptor.
+
+//       <o>Interface Number <0-255>
+//       <i>Defines the value for bInterfaceNumber
+//       <i>Each USB Device Interface has a sequential Interface Number starting with 0.
+//       <i>Several Interfaces may have the same Interface Number; in this case the value
+//       <i>of Alternate Setting is used to differ between the Interfaces. For a
+//       <i>composite device the Interface Numbers of the custom classes must be contiguous.
+#define USBD_CUSTOM_CLASS0_IF0_NUM                                 0
+
+//       <o>Alternate Setting <0=>0 <1=>1 <2=>2 <3=>3
+//       <i>Defines the value for bAlternateSetting
+//       <i>A sequential number starting with 0 to identify the Interface Descriptors
+//       <i>that share the same value for Interface Number.
+#define USBD_CUSTOM_CLASS0_IF0_ALT                                 0
+
+//       <o.0..7>Class Code
+//         <i>Class Codes are defined by USB-IF. For more information refer to
+//         <i>http://www.usb.org/developers/defined_class.
+//         <0x00=>0x00: Indicate a Null Class Code triple
+//         <0x01=>0x01: Audio
+//         <0x02=>0x02: Communications and CDC Control
+//         <0x03=>0x03: HID (Human Interface Device)
+//         <0x05=>0x05: Physical
+//         <0x06=>0x06: Image
+//         <0x07=>0x07: Printer
+//         <0x08=>0x08: Mass Storage
+//         <0x0A=>0x0A: CDC-Data
+//         <0x0B=>0x0B: Smart Card
+//         <0x0D=>0x0D: Content Security
+//         <0x0E=>0x0E: Video
+//         <0x0F=>0x0F: Personal Healthcare
+//         <0x10=>0x10: Audio/Video Devices
+//         <0xDC=>0xDC: Diagnostic Device
+//         <0xE0=>0xE0: Wireless Controller
+//         <0xEF=>0xEF: Miscellaneous
+//         <0xFE=>0xFE: Application Specific
+//         <0xFF=>0xFF: Vendor Specific
+#define USBD_CUSTOM_CLASS0_IF0_CLASS                               0xFF
+
+//       <o.0..7>Subclass Code <0x00-0xFF>
+//       <i>The possible values depend on the Class Code:
+//       <i>Class Code 0x00: Subclass Code must be 0
+//       <i>Class Code 0x01 .. 0xFE: Subclass Code is defined by USB-IF
+//       <i>Class Code 0xFF: Subclass Code can be 0x00 .. 0xFF
+#define USBD_CUSTOM_CLASS0_IF0_SUBCLASS                            0x00
+
+//       <o.0..7>Protocol Code <0x00-0xFF>
+//       <i>The Protocol Code value defines the protocol used on this interface:
+//       <i>Protocol Code 0x00: class-specific protocol not used
+//       <i>Protocol Code 0x01 .. 0xFE: class-specific protocol used
+//       <i>Protocol Code 0xFF: vendor-specific protocol used
+#define USBD_CUSTOM_CLASS0_IF0_PROTOCOL                            0x00
+
+//     </h>
+
+//     <h>Endpoint Settings
+//     <i>Following settings are used to create the Endpoint Descriptors.
+//     <i>Refer to USB - USB Concepts - USB Descriptor in the MDK Components
+//     <i>User's Guide for more information about Endpoint Descriptors.
+
+//       <e>Endpoint
+//       <i>Enable Endpoint for this interface.
+#define USBD_CUSTOM_CLASS0_IF0_EP0_EN                              1
+
+//         <o.0..1>Type
+//           <i>Select Endpoint Type.
+//           <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
+//           <i>If required, for Isochronous Endpoint, Synchronization and Usage Type 
+//           <i>can be set by manually editing define value of BMATTRIBUTES.
+//           <2=>Bulk
+//           <3=>Interrupt
+//           <1=>Isochronous
+#define USBD_CUSTOM_CLASS0_IF0_EP0_BMATTRIBUTES                    0x02
+
+//         <o.0..3>Number
+//           <i>Select Endpoint Number.
+//           <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
+//                   <1=>1   <2=>2   <3=>3   <4=>4   <5=>5   <6=>6   <7=>7
+//           <8=>8   <9=>9   <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
+//         <o.7>Direction
+//           <i>Select Endpoint Direction.
+//           <i>Endpoint Descriptor: bEndpointAddress field bit 7.
+//           <0=>OUT
+//           <1=>IN
+#define USBD_CUSTOM_CLASS0_IF0_EP0_BENDPOINTADDRESS                0x01
+
+//         <h>Speed Settings
+//           <i>Settings that are different depending on device operating speed.
+//
+//           <h>Full/Low-speed
+//             <i>Parameters apply when device operates in Full/Low-speed.
+//
+//             <o.0..9>Maximum Packet Size <0-1023>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
+//               <i>For Interrupt Endpoint set value to 1 .. 64.
+//               <i>For Isochronous Endpoint set value to 1 .. 1023.
+#define USBD_CUSTOM_CLASS0_IF0_EP0_FS_WMAXPACKETSIZE               64
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in ms).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>Setting is not used for Bulk Endpoint (set value to 0).
+//               <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF0_EP0_FS_BINTERVAL                    0
+
+//           </h>
+
+//           <h>High-speed
+//             <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
+//             <i>(n is the index of device on which this interface will be used) and when
+//             <i>device operates in High-speed.
+//
+//             <o.0..10>Maximum Packet Size <0-1024>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 512.
+//               <i>For Interrupt Endpoint set value to 1 .. 1024.
+//               <i>For Isochronous Endpoint set value to 1 .. 1024.
+//             <o.11..12>Additional Transactions per Microframe
+//               <i>Specifies additional transactions per microframe to improve communication performance.
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
+//               <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
+//               <i>Value: None = 1 transaction per microframe
+//               <i>Value: 1 additional = 2 transaction per microframe
+//               <i>Value: 2 additional = 3 transaction per microframe
+//                 <0=>None
+//                 <1=>1 additional
+//                 <2=>2 additional
+#define USBD_CUSTOM_CLASS0_IF0_EP0_HS_WMAXPACKETSIZE               512
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
+//               <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF0_EP0_HS_BINTERVAL                    0
+
+//           </h>
+//         </h>
+//       </e>
+
+//       <e>Endpoint
+//       <i>Enable Endpoint for this interface.
+#define USBD_CUSTOM_CLASS0_IF0_EP1_EN                              1
+
+//         <o.0..1>Type
+//           <i>Select Endpoint Type.
+//           <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
+//           <i>If required, for Isochronous Endpoint, Synchronization and Usage Type 
+//           <i>can be set by manually editing define value of BMATTRIBUTES.
+//           <2=>Bulk
+//           <3=>Interrupt
+//           <1=>Isochronous
+#define USBD_CUSTOM_CLASS0_IF0_EP1_BMATTRIBUTES                    0x02
+
+//         <o.0..3>Number
+//           <i>Select Endpoint Number.
+//           <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
+//                   <1=>1   <2=>2   <3=>3   <4=>4   <5=>5   <6=>6   <7=>7
+//           <8=>8   <9=>9   <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
+//         <o.7>Direction
+//           <i>Select Endpoint Direction.
+//           <i>Endpoint Descriptor: bEndpointAddress field bit 7.
+//           <0=>OUT
+//           <1=>IN
+#define USBD_CUSTOM_CLASS0_IF0_EP1_BENDPOINTADDRESS                0x81
+
+//         <h>Speed Settings
+//           <i>Settings that are different depending on device operating speed.
+//
+//           <h>Full/Low-speed
+//             <i>Parameters apply when device operates in Full/Low-speed.
+//
+//             <o.0..9>Maximum Packet Size <0-1023>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
+//               <i>For Interrupt Endpoint set value to 1 .. 64.
+//               <i>For Isochronous Endpoint set value to 1 .. 1023.
+#define USBD_CUSTOM_CLASS0_IF0_EP1_FS_WMAXPACKETSIZE               64
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in ms).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>Setting is not used for Bulk Endpoint (set value to 0).
+//               <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF0_EP1_FS_BINTERVAL                    0
+
+//           </h>
+
+//           <h>High-speed
+//             <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
+//             <i>(n is the index of device on which this interface will be used) and when
+//             <i>device operates in High-speed.
+//
+//             <o.0..10>Maximum Packet Size <0-1024>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 512.
+//               <i>For Interrupt Endpoint set value to 1 .. 1024.
+//               <i>For Isochronous Endpoint set value to 1 .. 1024.
+//             <o.11..12>Additional Transactions per Microframe
+//               <i>Specifies additional transactions per microframe to improve communication performance.
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
+//               <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
+//               <i>Value: None = 1 transaction per microframe
+//               <i>Value: 1 additional = 2 transaction per microframe
+//               <i>Value: 2 additional = 3 transaction per microframe
+//                 <0=>None
+//                 <1=>1 additional
+//                 <2=>2 additional
+#define USBD_CUSTOM_CLASS0_IF0_EP1_HS_WMAXPACKETSIZE               512
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
+//               <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF0_EP1_HS_BINTERVAL                    0
+
+//           </h>
+//         </h>
+//       </e>
+
+//       <e>Endpoint
+//       <i>Enable Endpoint for this interface.
+#define USBD_CUSTOM_CLASS0_IF0_EP2_EN                              1
+
+//         <o.0..1>Type
+//           <i>Select Endpoint Type.
+//           <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
+//           <i>If required, for Isochronous Endpoint, Synchronization and Usage Type 
+//           <i>can be set by manually editing define value of BMATTRIBUTES.
+//           <2=>Bulk
+//           <3=>Interrupt
+//           <1=>Isochronous
+#define USBD_CUSTOM_CLASS0_IF0_EP2_BMATTRIBUTES                    0x02
+
+//         <o.0..3>Number
+//           <i>Select Endpoint Number.
+//           <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
+//                   <1=>1   <2=>2   <3=>3   <4=>4   <5=>5   <6=>6   <7=>7
+//           <8=>8   <9=>9   <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
+//         <o.7>Direction
+//           <i>Select Endpoint Direction.
+//           <i>Endpoint Descriptor: bEndpointAddress field bit 7.
+//           <0=>OUT
+//           <1=>IN
+#define USBD_CUSTOM_CLASS0_IF0_EP2_BENDPOINTADDRESS                0x82
+
+//         <h>Speed Settings
+//           <i>Settings that are different depending on device operating speed.
+//
+//           <h>Full/Low-speed
+//             <i>Parameters apply when device operates in Full/Low-speed.
+//
+//             <o.0..9>Maximum Packet Size <0-1023>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
+//               <i>For Interrupt Endpoint set value to 1 .. 64.
+//               <i>For Isochronous Endpoint set value to 1 .. 1023.
+#define USBD_CUSTOM_CLASS0_IF0_EP2_FS_WMAXPACKETSIZE               64
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in ms).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>Setting is not used for Bulk Endpoint (set value to 0).
+//               <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF0_EP2_FS_BINTERVAL                    0
+
+//           </h>
+
+//           <h>High-speed
+//             <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
+//             <i>(n is the index of device on which this interface will be used) and when
+//             <i>device operates in High-speed.
+//
+//             <o.0..10>Maximum Packet Size <0-1024>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 512.
+//               <i>For Interrupt Endpoint set value to 1 .. 1024.
+//               <i>For Isochronous Endpoint set value to 1 .. 1024.
+//             <o.11..12>Additional Transactions per Microframe
+//               <i>Specifies additional transactions per microframe to improve communication performance.
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
+//               <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
+//               <i>Value: None = 1 transaction per microframe
+//               <i>Value: 1 additional = 2 transaction per microframe
+//               <i>Value: 2 additional = 3 transaction per microframe
+//                 <0=>None
+//                 <1=>1 additional
+//                 <2=>2 additional
+#define USBD_CUSTOM_CLASS0_IF0_EP2_HS_WMAXPACKETSIZE               512
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
+//               <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF0_EP2_HS_BINTERVAL                    0
+
+//           </h>
+//         </h>
+//       </e>
+
+//       <e>Endpoint
+//       <i>Enable Endpoint for this interface.
+#define USBD_CUSTOM_CLASS0_IF0_EP3_EN                              0
+
+//         <o.0..1>Type
+//           <i>Select Endpoint Type.
+//           <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
+//           <i>If required, for Isochronous Endpoint, Synchronization and Usage Type 
+//           <i>can be set by manually editing define value of BMATTRIBUTES.
+//           <2=>Bulk
+//           <3=>Interrupt
+//           <1=>Isochronous
+#define USBD_CUSTOM_CLASS0_IF0_EP3_BMATTRIBUTES                    0x03
+
+//         <o.0..3>Number
+//           <i>Select Endpoint Number.
+//           <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
+//                   <1=>1   <2=>2   <3=>3   <4=>4   <5=>5   <6=>6   <7=>7
+//           <8=>8   <9=>9   <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
+//         <o.7>Direction
+//           <i>Select Endpoint Direction.
+//           <i>Endpoint Descriptor: bEndpointAddress field bit 7.
+//           <0=>OUT
+//           <1=>IN
+#define USBD_CUSTOM_CLASS0_IF0_EP3_BENDPOINTADDRESS                0x82
+
+//         <h>Speed Settings
+//           <i>Settings that are different depending on device operating speed.
+//
+//           <h>Full/Low-speed
+//             <i>Parameters apply when device operates in Full/Low-speed.
+//
+//             <o.0..9>Maximum Packet Size <0-1023>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
+//               <i>For Interrupt Endpoint set value to 1 .. 64.
+//               <i>For Isochronous Endpoint set value to 1 .. 1023.
+#define USBD_CUSTOM_CLASS0_IF0_EP3_FS_WMAXPACKETSIZE               64
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in ms).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>Setting is not used for Bulk Endpoint (set value to 0).
+//               <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF0_EP3_FS_BINTERVAL                    1
+
+//           </h>
+
+//           <h>High-speed
+//             <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
+//             <i>(n is the index of device on which this interface will be used) and when
+//             <i>device operates in High-speed.
+//
+//             <o.0..10>Maximum Packet Size <0-1024>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 512.
+//               <i>For Interrupt Endpoint set value to 1 .. 1024.
+//               <i>For Isochronous Endpoint set value to 1 .. 1024.
+//             <o.11..12>Additional Transactions per Microframe
+//               <i>Specifies additional transactions per microframe to improve communication performance.
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
+//               <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
+//               <i>Value: None = 1 transaction per microframe
+//               <i>Value: 1 additional = 2 transaction per microframe
+//               <i>Value: 2 additional = 3 transaction per microframe
+//                 <0=>None
+//                 <1=>1 additional
+//                 <2=>2 additional
+#define USBD_CUSTOM_CLASS0_IF0_EP3_HS_WMAXPACKETSIZE               1024
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
+//               <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF0_EP3_HS_BINTERVAL                    1
+
+//           </h>
+//         </h>
+//       </e>
+
+//       <e>Endpoint
+//       <i>Enable Endpoint for this interface.
+#define USBD_CUSTOM_CLASS0_IF0_EP4_EN                              0
+
+//         <o.0..1>Type
+//           <i>Select Endpoint Type.
+//           <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
+//           <i>If required, for Isochronous Endpoint, Synchronization and Usage Type 
+//           <i>can be set by manually editing define value of BMATTRIBUTES.
+//           <2=>Bulk
+//           <3=>Interrupt
+//           <1=>Isochronous
+#define USBD_CUSTOM_CLASS0_IF0_EP4_BMATTRIBUTES                    0x01
+
+//         <o.0..3>Number
+//           <i>Select Endpoint Number.
+//           <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
+//                   <1=>1   <2=>2   <3=>3   <4=>4   <5=>5   <6=>6   <7=>7
+//           <8=>8   <9=>9   <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
+//         <o.7>Direction
+//           <i>Select Endpoint Direction.
+//           <i>Endpoint Descriptor: bEndpointAddress field bit 7.
+//           <0=>OUT
+//           <1=>IN
+#define USBD_CUSTOM_CLASS0_IF0_EP4_BENDPOINTADDRESS                0x03
+
+//         <h>Speed Settings
+//           <i>Settings that are different depending on device operating speed.
+//
+//           <h>Full/Low-speed
+//             <i>Parameters apply when device operates in Full/Low-speed.
+//
+//             <o.0..9>Maximum Packet Size <0-1023>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
+//               <i>For Interrupt Endpoint set value to 1 .. 64.
+//               <i>For Isochronous Endpoint set value to 1 .. 1023.
+#define USBD_CUSTOM_CLASS0_IF0_EP4_FS_WMAXPACKETSIZE               1023
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in ms).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>Setting is not used for Bulk Endpoint (set value to 0).
+//               <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF0_EP4_FS_BINTERVAL                    1
+
+//           </h>
+
+//           <h>High-speed
+//             <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
+//             <i>(n is the index of device on which this interface will be used) and when
+//             <i>device operates in High-speed.
+//
+//             <o.0..10>Maximum Packet Size <0-1024>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 512.
+//               <i>For Interrupt Endpoint set value to 1 .. 1024.
+//               <i>For Isochronous Endpoint set value to 1 .. 1024.
+//             <o.11..12>Additional Transactions per Microframe
+//               <i>Specifies additional transactions per microframe to improve communication performance.
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
+//               <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
+//               <i>Value: None = 1 transaction per microframe
+//               <i>Value: 1 additional = 2 transaction per microframe
+//               <i>Value: 2 additional = 3 transaction per microframe
+//                 <0=>None
+//                 <1=>1 additional
+//                 <2=>2 additional
+#define USBD_CUSTOM_CLASS0_IF0_EP4_HS_WMAXPACKETSIZE               1024
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
+//               <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF0_EP4_HS_BINTERVAL                    1
+
+//           </h>
+//         </h>
+//       </e>
+
+//       <e>Endpoint
+//       <i>Enable Endpoint for this interface.
+#define USBD_CUSTOM_CLASS0_IF0_EP5_EN                              0
+
+//         <o.0..1>Type
+//           <i>Select Endpoint Type.
+//           <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
+//           <i>If required, for Isochronous Endpoint, Synchronization and Usage Type 
+//           <i>can be set by manually editing define value of BMATTRIBUTES.
+//           <2=>Bulk
+//           <3=>Interrupt
+//           <1=>Isochronous
+#define USBD_CUSTOM_CLASS0_IF0_EP5_BMATTRIBUTES                    0x01
+
+//         <o.0..3>Number
+//           <i>Select Endpoint Number.
+//           <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
+//                   <1=>1   <2=>2   <3=>3   <4=>4   <5=>5   <6=>6   <7=>7
+//           <8=>8   <9=>9   <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
+//         <o.7>Direction
+//           <i>Select Endpoint Direction.
+//           <i>Endpoint Descriptor: bEndpointAddress field bit 7.
+//           <0=>OUT
+//           <1=>IN
+#define USBD_CUSTOM_CLASS0_IF0_EP5_BENDPOINTADDRESS                0x83
+
+//         <h>Speed Settings
+//           <i>Settings that are different depending on device operating speed.
+//
+//           <h>Full/Low-speed
+//             <i>Parameters apply when device operates in Full/Low-speed.
+//
+//             <o.0..9>Maximum Packet Size <0-1023>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
+//               <i>For Interrupt Endpoint set value to 1 .. 64.
+//               <i>For Isochronous Endpoint set value to 1 .. 1023.
+#define USBD_CUSTOM_CLASS0_IF0_EP5_FS_WMAXPACKETSIZE               1023
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in ms).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>Setting is not used for Bulk Endpoint (set value to 0).
+//               <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF0_EP5_FS_BINTERVAL                    1
+
+//           </h>
+
+//           <h>High-speed
+//             <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
+//             <i>(n is the index of device on which this interface will be used) and when
+//             <i>device operates in High-speed.
+//
+//             <o.0..10>Maximum Packet Size <0-1024>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 512.
+//               <i>For Interrupt Endpoint set value to 1 .. 1024.
+//               <i>For Isochronous Endpoint set value to 1 .. 1024.
+//             <o.11..12>Additional Transactions per Microframe
+//               <i>Specifies additional transactions per microframe to improve communication performance.
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
+//               <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
+//               <i>Value: None = 1 transaction per microframe
+//               <i>Value: 1 additional = 2 transaction per microframe
+//               <i>Value: 2 additional = 3 transaction per microframe
+//                 <0=>None
+//                 <1=>1 additional
+//                 <2=>2 additional
+#define USBD_CUSTOM_CLASS0_IF0_EP5_HS_WMAXPACKETSIZE               1024
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
+//               <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF0_EP5_HS_BINTERVAL                    1
+
+//           </h>
+//         </h>
+//       </e>
+
+//       <e>Endpoint
+//       <i>Enable Endpoint for this interface.
+#define USBD_CUSTOM_CLASS0_IF0_EP6_EN                              0
+
+//         <o.0..1>Type
+//           <i>Select Endpoint Type.
+//           <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
+//           <i>If required, for Isochronous Endpoint, Synchronization and Usage Type 
+//           <i>can be set by manually editing define value of BMATTRIBUTES.
+//           <2=>Bulk
+//           <3=>Interrupt
+//           <1=>Isochronous
+#define USBD_CUSTOM_CLASS0_IF0_EP6_BMATTRIBUTES                    0x02
+
+//         <o.0..3>Number
+//           <i>Select Endpoint Number.
+//           <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
+//                   <1=>1   <2=>2   <3=>3   <4=>4   <5=>5   <6=>6   <7=>7
+//           <8=>8   <9=>9   <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
+//         <o.7>Direction
+//           <i>Select Endpoint Direction.
+//           <i>Endpoint Descriptor: bEndpointAddress field bit 7.
+//           <0=>OUT
+//           <1=>IN
+#define USBD_CUSTOM_CLASS0_IF0_EP6_BENDPOINTADDRESS                0x04
+
+//         <h>Speed Settings
+//           <i>Settings that are different depending on device operating speed.
+//
+//           <h>Full/Low-speed
+//             <i>Parameters apply when device operates in Full/Low-speed.
+//
+//             <o.0..9>Maximum Packet Size <0-1023>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
+//               <i>For Interrupt Endpoint set value to 1 .. 64.
+//               <i>For Isochronous Endpoint set value to 1 .. 1023.
+#define USBD_CUSTOM_CLASS0_IF0_EP6_FS_WMAXPACKETSIZE               64
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in ms).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>Setting is not used for Bulk Endpoint (set value to 0).
+//               <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF0_EP6_FS_BINTERVAL                    0
+
+//           </h>
+
+//           <h>High-speed
+//             <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
+//             <i>(n is the index of device on which this interface will be used) and when
+//             <i>device operates in High-speed.
+//
+//             <o.0..10>Maximum Packet Size <0-1024>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 512.
+//               <i>For Interrupt Endpoint set value to 1 .. 1024.
+//               <i>For Isochronous Endpoint set value to 1 .. 1024.
+//             <o.11..12>Additional Transactions per Microframe
+//               <i>Specifies additional transactions per microframe to improve communication performance.
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
+//               <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
+//               <i>Value: None = 1 transaction per microframe
+//               <i>Value: 1 additional = 2 transaction per microframe
+//               <i>Value: 2 additional = 3 transaction per microframe
+//                 <0=>None
+//                 <1=>1 additional
+//                 <2=>2 additional
+#define USBD_CUSTOM_CLASS0_IF0_EP6_HS_WMAXPACKETSIZE               512
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
+//               <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF0_EP6_HS_BINTERVAL                    0
+
+//           </h>
+//         </h>
+//       </e>
+
+//       <e>Endpoint
+//       <i>Enable Endpoint for this interface.
+#define USBD_CUSTOM_CLASS0_IF0_EP7_EN                              0
+
+//         <o.0..1>Type
+//           <i>Select Endpoint Type.
+//           <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
+//           <i>If required, for Isochronous Endpoint, Synchronization and Usage Type 
+//           <i>can be set by manually editing define value of BMATTRIBUTES.
+//           <2=>Bulk
+//           <3=>Interrupt
+//           <1=>Isochronous
+#define USBD_CUSTOM_CLASS0_IF0_EP7_BMATTRIBUTES                    0x02
+
+//         <o.0..3>Number
+//           <i>Select Endpoint Number.
+//           <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
+//                   <1=>1   <2=>2   <3=>3   <4=>4   <5=>5   <6=>6   <7=>7
+//           <8=>8   <9=>9   <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
+//         <o.7>Direction
+//           <i>Select Endpoint Direction.
+//           <i>Endpoint Descriptor: bEndpointAddress field bit 7.
+//           <0=>OUT
+//           <1=>IN
+#define USBD_CUSTOM_CLASS0_IF0_EP7_BENDPOINTADDRESS                0x84
+
+//         <h>Speed Settings
+//           <i>Settings that are different depending on device operating speed.
+//
+//           <h>Full/Low-speed
+//             <i>Parameters apply when device operates in Full/Low-speed.
+//
+//             <o.0..9>Maximum Packet Size <0-1023>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
+//               <i>For Interrupt Endpoint set value to 1 .. 64.
+//               <i>For Isochronous Endpoint set value to 1 .. 1023.
+#define USBD_CUSTOM_CLASS0_IF0_EP7_FS_WMAXPACKETSIZE               64
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in ms).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>Setting is not used for Bulk Endpoint (set value to 0).
+//               <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF0_EP7_FS_BINTERVAL                    0
+
+//           </h>
+
+//           <h>High-speed
+//             <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
+//             <i>(n is the index of device on which this interface will be used) and when
+//             <i>device operates in High-speed.
+//
+//             <o.0..10>Maximum Packet Size <0-1024>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 512.
+//               <i>For Interrupt Endpoint set value to 1 .. 1024.
+//               <i>For Isochronous Endpoint set value to 1 .. 1024.
+//             <o.11..12>Additional Transactions per Microframe
+//               <i>Specifies additional transactions per microframe to improve communication performance.
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
+//               <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
+//               <i>Value: None = 1 transaction per microframe
+//               <i>Value: 1 additional = 2 transaction per microframe
+//               <i>Value: 2 additional = 3 transaction per microframe
+//                 <0=>None
+//                 <1=>1 additional
+//                 <2=>2 additional
+#define USBD_CUSTOM_CLASS0_IF0_EP7_HS_WMAXPACKETSIZE               512
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
+//               <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF0_EP7_HS_BINTERVAL                    0
+
+//           </h>
+//         </h>
+//       </e>
+//     </h>
+
+//     <h>String Settings
+//     <i>Following settings are used to create String Descriptor(s)
+
+//       <e.0>Interface String Enable
+//       <i>Enable Interface String.
+//       <i>If disabled Interface String will not be assigned to USB Device Custom Class Interface 0.
+#define USBD_CUSTOM_CLASS0_IF0_STR_EN                              1
+
+//         <s.126>Interface String
+#define USBD_CUSTOM_CLASS0_IF0_STR                                 L"MCU-LINK CMSIS-DAP"
+
+//       </e>
+//     </h>
+
+//     <h>Microsoft OS Descriptor Settings
+//     <i>Following settings are used to create Extended Compat ID OS Feature Descriptor
+
+//       <e.0>Extended Compat ID OS Feature Descriptor Function Section
+//       <i>Enable creation of function section in Extended Compat ID OS Feature Descriptor for this interface.
+#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_COMPAT_ID_EN                 1
+
+//         <s.7>compatibleID
+//         <i>compatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface.
+#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_COMPAT_ID                    "WINUSB"
+
+//         <s.7>subCompatibleID
+//         <i>subCompatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface.
+#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_SUBCOMPAT_ID                 ""
+
+//       </e>
+
+//       <h>Extended Properties OS Feature Descriptor
+//         <e.0>Custom Property Section 0
+//         <i>Enable creation of custom property 0 section in Extended Properties OS Feature Descriptor.
+#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP0_EN                     1
+
+//           <o>Data Type
+//           <i>Specifies the dwPropertyDataType field of custom property 0 section in Extended Properties OS Feature Descriptor.
+//           <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
+//             <1=>Unicode String (REG_SZ)
+//             <2=>Unicode String with environment variables (REG_EXPAND_SZ)
+//             <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
+//             <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
+//             <6=>Unicode String with symbolic link (REG_LINK)
+#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP0_DATA_TYP               1
+
+//           <s.512>Name
+#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP0_NAME                   L"DeviceInterfaceGUID"
+
+//           <h>Data
+//             <s.1024>Unicode String
+//             <i>Property Data in case Data Type is selected as Unicode String.
+#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP0_DATA_STR               L"{CDB3B5AD-293B-4663-AA36-1AAE46463776}"
+
+//             <o>32-bit Integer
+//             <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
+#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP0_DATA_INT               0
+
+//           </h>
+//         </e>
+
+//         <e.0>Custom Property Section 1
+//         <i>Enable creation of custom property 1 section in Extended Properties OS Feature Descriptor.
+#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP1_EN                     0
+
+//           <o>Data Type
+//           <i>Specifies the dwPropertyDataType field of custom property 1 section in Extended Properties OS Feature Descriptor.
+//           <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
+//             <1=>Unicode String (REG_SZ)
+//             <2=>Unicode String with environment variables (REG_EXPAND_SZ)
+//             <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
+//             <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
+//             <6=>Unicode String with symbolic link (REG_LINK)
+#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP1_DATA_TYP               1
+
+//           <s.512>Name
+#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP1_NAME                   L""
+
+//           <h>Data
+//             <s.1024>Unicode String
+//             <i>Property Data in case Data Type is selected as Unicode String.
+#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP1_DATA_STR               L""
+
+//             <o>32-bit Integer
+//             <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
+#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP1_DATA_INT               0
+
+//           </h>
+//         </e>
+
+//         <e.0>Custom Property Section 2
+//         <i>Enable creation of custom property 2 section in Extended Properties OS Feature Descriptor.
+#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP2_EN                     0
+
+//           <o>Data Type
+//           <i>Specifies the dwPropertyDataType field of custom property 2 section in Extended Properties OS Feature Descriptor.
+//           <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
+//             <1=>Unicode String (REG_SZ)
+//             <2=>Unicode String with environment variables (REG_EXPAND_SZ)
+//             <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
+//             <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
+//             <6=>Unicode String with symbolic link (REG_LINK)
+#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP2_DATA_TYP               1
+
+//           <s.512>Name
+#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP2_NAME                   L""
+
+//           <h>Data
+//             <s.1024>Unicode String
+//             <i>Property Data in case Data Type is selected as Unicode String.
+#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP2_DATA_STR               L""
+
+//             <o>32-bit Integer
+//             <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
+#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP2_DATA_INT               0
+
+//           </h>
+//         </e>
+
+//         <e.0>Custom Property Section 3
+//         <i>Enable creation of custom property 3 section in Extended Properties OS Feature Descriptor.
+#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP3_EN                     0
+
+//           <o>Data Type
+//           <i>Specifies the dwPropertyDataType field of custom property 3 section in Extended Properties OS Feature Descriptor.
+//           <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
+//             <1=>Unicode String (REG_SZ)
+//             <2=>Unicode String with environment variables (REG_EXPAND_SZ)
+//             <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
+//             <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
+//             <6=>Unicode String with symbolic link (REG_LINK)
+#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP3_DATA_TYP               1
+
+//           <s.512>Name
+#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP3_NAME                   L""
+
+//           <h>Data
+//             <s.1024>Unicode String
+//             <i>Property Data in case Data Type is selected as Unicode String.
+#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP3_DATA_STR               L""
+
+//             <o>32-bit Integer
+//             <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
+#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP3_DATA_INT               0
+
+//           </h>
+//         </e>
+//       </h>
+//     </h>
+//   </e>
+
+
+//   <e>Interface
+#define USBD_CUSTOM_CLASS0_IF1_EN                                  0
+
+//     <h>Interface Settings
+//     <i>The Interface Settings are used to create the Interface Descriptor.
+//     <i>Refer to USB - USB Concepts - USB Descriptor in the MDK Components
+//     <i>User's Guide for more information about the Interface Descriptor.
+
+//       <o>Interface Number <0-255>
+//       <i>Defines the value for bInterfaceNumber
+//       <i>Each USB Device Interface has a sequential Interface Number starting with 0.
+//       <i>Several Interfaces may have the same Interface Number; in this case the value
+//       <i>of Alternate Setting is used to differ between the Interfaces. For a
+//       <i>composite device the Interface Numbers of the custom classes must be contiguous.
+#define USBD_CUSTOM_CLASS0_IF1_NUM                                 1
+
+//       <o>Alternate Setting <0=>0 <1=>1 <2=>2 <3=>3
+//       <i>Defines the value for bAlternateSetting
+//       <i>A sequential number starting with 0 to identify the Interface Descriptors
+//       <i>that share the same value for Interface Number.
+#define USBD_CUSTOM_CLASS0_IF1_ALT                                 0
+
+//       <o.0..7>Class Code
+//         <i>Class Codes are defined by USB-IF. For more information refer to
+//         <i>http://www.usb.org/developers/defined_class.
+//         <0x00=>0x00: Indicate a Null Class Code triple
+//         <0x01=>0x01: Audio
+//         <0x02=>0x02: Communications and CDC Control
+//         <0x03=>0x03: HID (Human Interface Device)
+//         <0x05=>0x05: Physical
+//         <0x06=>0x06: Image
+//         <0x07=>0x07: Printer
+//         <0x08=>0x08: Mass Storage
+//         <0x0A=>0x0A: CDC-Data
+//         <0x0B=>0x0B: Smart Card
+//         <0x0D=>0x0D: Content Security
+//         <0x0E=>0x0E: Video
+//         <0x0F=>0x0F: Personal Healthcare
+//         <0x10=>0x10: Audio/Video Devices
+//         <0xDC=>0xDC: Diagnostic Device
+//         <0xE0=>0xE0: Wireless Controller
+//         <0xEF=>0xEF: Miscellaneous
+//         <0xFE=>0xFE: Application Specific
+//         <0xFF=>0xFF: Vendor Specific
+#define USBD_CUSTOM_CLASS0_IF1_CLASS                               0xFF
+
+//       <o.0..7>Subclass Code <0x00-0xFF>
+//       <i>The possible values depend on the Class Code:
+//       <i>Class Code 0x00: Subclass Code must be 0
+//       <i>Class Code 0x01 .. 0xFE: Subclass Code is defined by USB-IF
+//       <i>Class Code 0xFF: Subclass Code can be 0x00 .. 0xFF
+#define USBD_CUSTOM_CLASS0_IF1_SUBCLASS                            0x00
+
+//       <o.0..7>Protocol Code <0x00-0xFF>
+//       <i>The Protocol Code value defines the protocol used on this interface:
+//       <i>Protocol Code 0x00: class-specific protocol not used
+//       <i>Protocol Code 0x01 .. 0xFE: class-specific protocol used
+//       <i>Protocol Code 0xFF: vendor-specific protocol used
+#define USBD_CUSTOM_CLASS0_IF1_PROTOCOL                            0x00
+
+//     </h>
+
+//     <h>Endpoint Settings
+//     <i>Following settings are used to create the Endpoint Descriptors.
+//     <i>Refer to USB - USB Concepts - USB Descriptor in the MDK Components
+//     <i>User's Guide for more information about Endpoint Descriptors.
+
+//       <e>Endpoint
+//       <i>Enable Endpoint for this interface.
+#define USBD_CUSTOM_CLASS0_IF1_EP0_EN                              0
+
+//         <o.0..1>Type
+//           <i>Select Endpoint Type.
+//           <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
+//           <i>If required, for Isochronous Endpoint, Synchronization and Usage Type 
+//           <i>can be set by manually editing define value of BMATTRIBUTES.
+//           <2=>Bulk
+//           <3=>Interrupt
+//           <1=>Isochronous
+#define USBD_CUSTOM_CLASS0_IF1_EP0_BMATTRIBUTES                    0x02
+
+//         <o.0..3>Number
+//           <i>Select Endpoint Number.
+//           <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
+//                   <1=>1   <2=>2   <3=>3   <4=>4   <5=>5   <6=>6   <7=>7
+//           <8=>8   <9=>9   <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
+//         <o.7>Direction
+//           <i>Select Endpoint Direction.
+//           <i>Endpoint Descriptor: bEndpointAddress field bit 7.
+//           <0=>OUT
+//           <1=>IN
+#define USBD_CUSTOM_CLASS0_IF1_EP0_BENDPOINTADDRESS                0x01
+
+//         <h>Speed Settings
+//           <i>Settings that are different depending on device operating speed.
+//
+//           <h>Full/Low-speed
+//             <i>Parameters apply when device operates in Full/Low-speed.
+//
+//             <o.0..9>Maximum Packet Size <0-1023>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
+//               <i>For Interrupt Endpoint set value to 1 .. 64.
+//               <i>For Isochronous Endpoint set value to 1 .. 1023.
+#define USBD_CUSTOM_CLASS0_IF1_EP0_FS_WMAXPACKETSIZE               64
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in ms).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>Setting is not used for Bulk Endpoint (set value to 0).
+//               <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF1_EP0_FS_BINTERVAL                    0
+
+//           </h>
+
+//           <h>High-speed
+//             <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
+//             <i>(n is the index of device on which this interface will be used) and when
+//             <i>device operates in High-speed.
+//
+//             <o.0..10>Maximum Packet Size <0-1024>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 512.
+//               <i>For Interrupt Endpoint set value to 1 .. 1024.
+//               <i>For Isochronous Endpoint set value to 1 .. 1024.
+//             <o.11..12>Additional Transactions per Microframe
+//               <i>Specifies additional transactions per microframe to improve communication performance.
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
+//               <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
+//               <i>Value: None = 1 transaction per microframe
+//               <i>Value: 1 additional = 2 transaction per microframe
+//               <i>Value: 2 additional = 3 transaction per microframe
+//                 <0=>None
+//                 <1=>1 additional
+//                 <2=>2 additional
+#define USBD_CUSTOM_CLASS0_IF1_EP0_HS_WMAXPACKETSIZE               512
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
+//               <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF1_EP0_HS_BINTERVAL                    0
+
+//           </h>
+//         </h>
+//       </e>
+
+//       <e>Endpoint
+//       <i>Enable Endpoint for this interface.
+#define USBD_CUSTOM_CLASS0_IF1_EP1_EN                              0
+
+//         <o.0..1>Type
+//           <i>Select Endpoint Type.
+//           <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
+//           <i>If required, for Isochronous Endpoint, Synchronization and Usage Type 
+//           <i>can be set by manually editing define value of BMATTRIBUTES.
+//           <2=>Bulk
+//           <3=>Interrupt
+//           <1=>Isochronous
+#define USBD_CUSTOM_CLASS0_IF1_EP1_BMATTRIBUTES                    0x02
+
+//         <o.0..3>Number
+//           <i>Select Endpoint Number.
+//           <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
+//                   <1=>1   <2=>2   <3=>3   <4=>4   <5=>5   <6=>6   <7=>7
+//           <8=>8   <9=>9   <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
+//         <o.7>Direction
+//           <i>Select Endpoint Direction.
+//           <i>Endpoint Descriptor: bEndpointAddress field bit 7.
+//           <0=>OUT
+//           <1=>IN
+#define USBD_CUSTOM_CLASS0_IF1_EP1_BENDPOINTADDRESS                0x81
+
+//         <h>Speed Settings
+//           <i>Settings that are different depending on device operating speed.
+//
+//           <h>Full/Low-speed
+//             <i>Parameters apply when device operates in Full/Low-speed.
+//
+//             <o.0..9>Maximum Packet Size <0-1023>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
+//               <i>For Interrupt Endpoint set value to 1 .. 64.
+//               <i>For Isochronous Endpoint set value to 1 .. 1023.
+#define USBD_CUSTOM_CLASS0_IF1_EP1_FS_WMAXPACKETSIZE               64
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in ms).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>Setting is not used for Bulk Endpoint (set value to 0).
+//               <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF1_EP1_FS_BINTERVAL                    0
+
+//           </h>
+
+//           <h>High-speed
+//             <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
+//             <i>(n is the index of device on which this interface will be used) and when
+//             <i>device operates in High-speed.
+//
+//             <o.0..10>Maximum Packet Size <0-1024>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 512.
+//               <i>For Interrupt Endpoint set value to 1 .. 1024.
+//               <i>For Isochronous Endpoint set value to 1 .. 1024.
+//             <o.11..12>Additional Transactions per Microframe
+//               <i>Specifies additional transactions per microframe to improve communication performance.
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
+//               <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
+//               <i>Value: None = 1 transaction per microframe
+//               <i>Value: 1 additional = 2 transaction per microframe
+//               <i>Value: 2 additional = 3 transaction per microframe
+//                 <0=>None
+//                 <1=>1 additional
+//                 <2=>2 additional
+#define USBD_CUSTOM_CLASS0_IF1_EP1_HS_WMAXPACKETSIZE               512
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
+//               <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF1_EP1_HS_BINTERVAL                    0
+
+//           </h>
+//         </h>
+//       </e>
+
+//       <e>Endpoint
+//       <i>Enable Endpoint for this interface.
+#define USBD_CUSTOM_CLASS0_IF1_EP2_EN                              0
+
+//         <o.0..1>Type
+//           <i>Select Endpoint Type.
+//           <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
+//           <i>If required, for Isochronous Endpoint, Synchronization and Usage Type 
+//           <i>can be set by manually editing define value of BMATTRIBUTES.
+//           <2=>Bulk
+//           <3=>Interrupt
+//           <1=>Isochronous
+#define USBD_CUSTOM_CLASS0_IF1_EP2_BMATTRIBUTES                    0x03
+
+//         <o.0..3>Number
+//           <i>Select Endpoint Number.
+//           <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
+//                   <1=>1   <2=>2   <3=>3   <4=>4   <5=>5   <6=>6   <7=>7
+//           <8=>8   <9=>9   <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
+//         <o.7>Direction
+//           <i>Select Endpoint Direction.
+//           <i>Endpoint Descriptor: bEndpointAddress field bit 7.
+//           <0=>OUT
+//           <1=>IN
+#define USBD_CUSTOM_CLASS0_IF1_EP2_BENDPOINTADDRESS                0x02
+
+//         <h>Speed Settings
+//           <i>Settings that are different depending on device operating speed.
+//
+//           <h>Full/Low-speed
+//             <i>Parameters apply when device operates in Full/Low-speed.
+//
+//             <o.0..9>Maximum Packet Size <0-1023>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
+//               <i>For Interrupt Endpoint set value to 1 .. 64.
+//               <i>For Isochronous Endpoint set value to 1 .. 1023.
+#define USBD_CUSTOM_CLASS0_IF1_EP2_FS_WMAXPACKETSIZE               64
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in ms).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>Setting is not used for Bulk Endpoint (set value to 0).
+//               <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF1_EP2_FS_BINTERVAL                    1
+
+//           </h>
+
+//           <h>High-speed
+//             <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
+//             <i>(n is the index of device on which this interface will be used) and when
+//             <i>device operates in High-speed.
+//
+//             <o.0..10>Maximum Packet Size <0-1024>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 512.
+//               <i>For Interrupt Endpoint set value to 1 .. 1024.
+//               <i>For Isochronous Endpoint set value to 1 .. 1024.
+//             <o.11..12>Additional Transactions per Microframe
+//               <i>Specifies additional transactions per microframe to improve communication performance.
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
+//               <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
+//               <i>Value: None = 1 transaction per microframe
+//               <i>Value: 1 additional = 2 transaction per microframe
+//               <i>Value: 2 additional = 3 transaction per microframe
+//                 <0=>None
+//                 <1=>1 additional
+//                 <2=>2 additional
+#define USBD_CUSTOM_CLASS0_IF1_EP2_HS_WMAXPACKETSIZE               1024
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
+//               <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF1_EP2_HS_BINTERVAL                    1
+
+//           </h>
+//         </h>
+//       </e>
+
+//       <e>Endpoint
+//       <i>Enable Endpoint for this interface.
+#define USBD_CUSTOM_CLASS0_IF1_EP3_EN                              0
+
+//         <o.0..1>Type
+//           <i>Select Endpoint Type.
+//           <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
+//           <i>If required, for Isochronous Endpoint, Synchronization and Usage Type 
+//           <i>can be set by manually editing define value of BMATTRIBUTES.
+//           <2=>Bulk
+//           <3=>Interrupt
+//           <1=>Isochronous
+#define USBD_CUSTOM_CLASS0_IF1_EP3_BMATTRIBUTES                    0x03
+
+//         <o.0..3>Number
+//           <i>Select Endpoint Number.
+//           <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
+//                   <1=>1   <2=>2   <3=>3   <4=>4   <5=>5   <6=>6   <7=>7
+//           <8=>8   <9=>9   <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
+//         <o.7>Direction
+//           <i>Select Endpoint Direction.
+//           <i>Endpoint Descriptor: bEndpointAddress field bit 7.
+//           <0=>OUT
+//           <1=>IN
+#define USBD_CUSTOM_CLASS0_IF1_EP3_BENDPOINTADDRESS                0x82
+
+//         <h>Speed Settings
+//           <i>Settings that are different depending on device operating speed.
+//
+//           <h>Full/Low-speed
+//             <i>Parameters apply when device operates in Full/Low-speed.
+//
+//             <o.0..9>Maximum Packet Size <0-1023>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
+//               <i>For Interrupt Endpoint set value to 1 .. 64.
+//               <i>For Isochronous Endpoint set value to 1 .. 1023.
+#define USBD_CUSTOM_CLASS0_IF1_EP3_FS_WMAXPACKETSIZE               64
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in ms).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>Setting is not used for Bulk Endpoint (set value to 0).
+//               <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF1_EP3_FS_BINTERVAL                    1
+
+//           </h>
+
+//           <h>High-speed
+//             <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
+//             <i>(n is the index of device on which this interface will be used) and when
+//             <i>device operates in High-speed.
+//
+//             <o.0..10>Maximum Packet Size <0-1024>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 512.
+//               <i>For Interrupt Endpoint set value to 1 .. 1024.
+//               <i>For Isochronous Endpoint set value to 1 .. 1024.
+//             <o.11..12>Additional Transactions per Microframe
+//               <i>Specifies additional transactions per microframe to improve communication performance.
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
+//               <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
+//               <i>Value: None = 1 transaction per microframe
+//               <i>Value: 1 additional = 2 transaction per microframe
+//               <i>Value: 2 additional = 3 transaction per microframe
+//                 <0=>None
+//                 <1=>1 additional
+//                 <2=>2 additional
+#define USBD_CUSTOM_CLASS0_IF1_EP3_HS_WMAXPACKETSIZE               1024
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
+//               <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF1_EP3_HS_BINTERVAL                    1
+
+//           </h>
+//         </h>
+//       </e>
+
+//       <e>Endpoint
+//       <i>Enable Endpoint for this interface.
+#define USBD_CUSTOM_CLASS0_IF1_EP4_EN                              0
+
+//         <o.0..1>Type
+//           <i>Select Endpoint Type.
+//           <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
+//           <i>If required, for Isochronous Endpoint, Synchronization and Usage Type 
+//           <i>can be set by manually editing define value of BMATTRIBUTES.
+//           <2=>Bulk
+//           <3=>Interrupt
+//           <1=>Isochronous
+#define USBD_CUSTOM_CLASS0_IF1_EP4_BMATTRIBUTES                    0x01
+
+//         <o.0..3>Number
+//           <i>Select Endpoint Number.
+//           <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
+//                   <1=>1   <2=>2   <3=>3   <4=>4   <5=>5   <6=>6   <7=>7
+//           <8=>8   <9=>9   <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
+//         <o.7>Direction
+//           <i>Select Endpoint Direction.
+//           <i>Endpoint Descriptor: bEndpointAddress field bit 7.
+//           <0=>OUT
+//           <1=>IN
+#define USBD_CUSTOM_CLASS0_IF1_EP4_BENDPOINTADDRESS                0x03
+
+//         <h>Speed Settings
+//           <i>Settings that are different depending on device operating speed.
+//
+//           <h>Full/Low-speed
+//             <i>Parameters apply when device operates in Full/Low-speed.
+//
+//             <o.0..9>Maximum Packet Size <0-1023>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
+//               <i>For Interrupt Endpoint set value to 1 .. 64.
+//               <i>For Isochronous Endpoint set value to 1 .. 1023.
+#define USBD_CUSTOM_CLASS0_IF1_EP4_FS_WMAXPACKETSIZE               1023
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in ms).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>Setting is not used for Bulk Endpoint (set value to 0).
+//               <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF1_EP4_FS_BINTERVAL                    1
+
+//           </h>
+
+//           <h>High-speed
+//             <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
+//             <i>(n is the index of device on which this interface will be used) and when
+//             <i>device operates in High-speed.
+//
+//             <o.0..10>Maximum Packet Size <0-1024>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 512.
+//               <i>For Interrupt Endpoint set value to 1 .. 1024.
+//               <i>For Isochronous Endpoint set value to 1 .. 1024.
+//             <o.11..12>Additional Transactions per Microframe
+//               <i>Specifies additional transactions per microframe to improve communication performance.
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
+//               <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
+//               <i>Value: None = 1 transaction per microframe
+//               <i>Value: 1 additional = 2 transaction per microframe
+//               <i>Value: 2 additional = 3 transaction per microframe
+//                 <0=>None
+//                 <1=>1 additional
+//                 <2=>2 additional
+#define USBD_CUSTOM_CLASS0_IF1_EP4_HS_WMAXPACKETSIZE               1024
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
+//               <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF1_EP4_HS_BINTERVAL                    1
+
+//           </h>
+//         </h>
+//       </e>
+
+//       <e>Endpoint
+//       <i>Enable Endpoint for this interface.
+#define USBD_CUSTOM_CLASS0_IF1_EP5_EN                              0
+
+//         <o.0..1>Type
+//           <i>Select Endpoint Type.
+//           <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
+//           <i>If required, for Isochronous Endpoint, Synchronization and Usage Type 
+//           <i>can be set by manually editing define value of BMATTRIBUTES.
+//           <2=>Bulk
+//           <3=>Interrupt
+//           <1=>Isochronous
+#define USBD_CUSTOM_CLASS0_IF1_EP5_BMATTRIBUTES                    0x01
+
+//         <o.0..3>Number
+//           <i>Select Endpoint Number.
+//           <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
+//                   <1=>1   <2=>2   <3=>3   <4=>4   <5=>5   <6=>6   <7=>7
+//           <8=>8   <9=>9   <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
+//         <o.7>Direction
+//           <i>Select Endpoint Direction.
+//           <i>Endpoint Descriptor: bEndpointAddress field bit 7.
+//           <0=>OUT
+//           <1=>IN
+#define USBD_CUSTOM_CLASS0_IF1_EP5_BENDPOINTADDRESS                0x83
+
+//         <h>Speed Settings
+//           <i>Settings that are different depending on device operating speed.
+//
+//           <h>Full/Low-speed
+//             <i>Parameters apply when device operates in Full/Low-speed.
+//
+//             <o.0..9>Maximum Packet Size <0-1023>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
+//               <i>For Interrupt Endpoint set value to 1 .. 64.
+//               <i>For Isochronous Endpoint set value to 1 .. 1023.
+#define USBD_CUSTOM_CLASS0_IF1_EP5_FS_WMAXPACKETSIZE               1023
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in ms).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>Setting is not used for Bulk Endpoint (set value to 0).
+//               <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF1_EP5_FS_BINTERVAL                    1
+
+//           </h>
+
+//           <h>High-speed
+//             <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
+//             <i>(n is the index of device on which this interface will be used) and when
+//             <i>device operates in High-speed.
+//
+//             <o.0..10>Maximum Packet Size <0-1024>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 512.
+//               <i>For Interrupt Endpoint set value to 1 .. 1024.
+//               <i>For Isochronous Endpoint set value to 1 .. 1024.
+//             <o.11..12>Additional Transactions per Microframe
+//               <i>Specifies additional transactions per microframe to improve communication performance.
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
+//               <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
+//               <i>Value: None = 1 transaction per microframe
+//               <i>Value: 1 additional = 2 transaction per microframe
+//               <i>Value: 2 additional = 3 transaction per microframe
+//                 <0=>None
+//                 <1=>1 additional
+//                 <2=>2 additional
+#define USBD_CUSTOM_CLASS0_IF1_EP5_HS_WMAXPACKETSIZE               1024
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
+//               <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF1_EP5_HS_BINTERVAL                    1
+
+//           </h>
+//         </h>
+//       </e>
+
+//       <e>Endpoint
+//       <i>Enable Endpoint for this interface.
+#define USBD_CUSTOM_CLASS0_IF1_EP6_EN                              0
+
+//         <o.0..1>Type
+//           <i>Select Endpoint Type.
+//           <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
+//           <i>If required, for Isochronous Endpoint, Synchronization and Usage Type 
+//           <i>can be set by manually editing define value of BMATTRIBUTES.
+//           <2=>Bulk
+//           <3=>Interrupt
+//           <1=>Isochronous
+#define USBD_CUSTOM_CLASS0_IF1_EP6_BMATTRIBUTES                    0x02
+
+//         <o.0..3>Number
+//           <i>Select Endpoint Number.
+//           <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
+//                   <1=>1   <2=>2   <3=>3   <4=>4   <5=>5   <6=>6   <7=>7
+//           <8=>8   <9=>9   <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
+//         <o.7>Direction
+//           <i>Select Endpoint Direction.
+//           <i>Endpoint Descriptor: bEndpointAddress field bit 7.
+//           <0=>OUT
+//           <1=>IN
+#define USBD_CUSTOM_CLASS0_IF1_EP6_BENDPOINTADDRESS                0x04
+
+//         <h>Speed Settings
+//           <i>Settings that are different depending on device operating speed.
+//
+//           <h>Full/Low-speed
+//             <i>Parameters apply when device operates in Full/Low-speed.
+//
+//             <o.0..9>Maximum Packet Size <0-1023>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
+//               <i>For Interrupt Endpoint set value to 1 .. 64.
+//               <i>For Isochronous Endpoint set value to 1 .. 1023.
+#define USBD_CUSTOM_CLASS0_IF1_EP6_FS_WMAXPACKETSIZE               64
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in ms).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>Setting is not used for Bulk Endpoint (set value to 0).
+//               <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF1_EP6_FS_BINTERVAL                    0
+
+//           </h>
+
+//           <h>High-speed
+//             <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
+//             <i>(n is the index of device on which this interface will be used) and when
+//             <i>device operates in High-speed.
+//
+//             <o.0..10>Maximum Packet Size <0-1024>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 512.
+//               <i>For Interrupt Endpoint set value to 1 .. 1024.
+//               <i>For Isochronous Endpoint set value to 1 .. 1024.
+//             <o.11..12>Additional Transactions per Microframe
+//               <i>Specifies additional transactions per microframe to improve communication performance.
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
+//               <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
+//               <i>Value: None = 1 transaction per microframe
+//               <i>Value: 1 additional = 2 transaction per microframe
+//               <i>Value: 2 additional = 3 transaction per microframe
+//                 <0=>None
+//                 <1=>1 additional
+//                 <2=>2 additional
+#define USBD_CUSTOM_CLASS0_IF1_EP6_HS_WMAXPACKETSIZE               512
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
+//               <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF1_EP6_HS_BINTERVAL                    0
+
+//           </h>
+//         </h>
+//       </e>
+
+//       <e>Endpoint
+//       <i>Enable Endpoint for this interface.
+#define USBD_CUSTOM_CLASS0_IF1_EP7_EN                              0
+
+//         <o.0..1>Type
+//           <i>Select Endpoint Type.
+//           <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
+//           <i>If required, for Isochronous Endpoint, Synchronization and Usage Type 
+//           <i>can be set by manually editing define value of BMATTRIBUTES.
+//           <2=>Bulk
+//           <3=>Interrupt
+//           <1=>Isochronous
+#define USBD_CUSTOM_CLASS0_IF1_EP7_BMATTRIBUTES                    0x02
+
+//         <o.0..3>Number
+//           <i>Select Endpoint Number.
+//           <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
+//                   <1=>1   <2=>2   <3=>3   <4=>4   <5=>5   <6=>6   <7=>7
+//           <8=>8   <9=>9   <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
+//         <o.7>Direction
+//           <i>Select Endpoint Direction.
+//           <i>Endpoint Descriptor: bEndpointAddress field bit 7.
+//           <0=>OUT
+//           <1=>IN
+#define USBD_CUSTOM_CLASS0_IF1_EP7_BENDPOINTADDRESS                0x84
+
+//         <h>Speed Settings
+//           <i>Settings that are different depending on device operating speed.
+//
+//           <h>Full/Low-speed
+//             <i>Parameters apply when device operates in Full/Low-speed.
+//
+//             <o.0..9>Maximum Packet Size <0-1023>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
+//               <i>For Interrupt Endpoint set value to 1 .. 64.
+//               <i>For Isochronous Endpoint set value to 1 .. 1023.
+#define USBD_CUSTOM_CLASS0_IF1_EP7_FS_WMAXPACKETSIZE               64
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in ms).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>Setting is not used for Bulk Endpoint (set value to 0).
+//               <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF1_EP7_FS_BINTERVAL                    0
+
+//           </h>
+
+//           <h>High-speed
+//             <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
+//             <i>(n is the index of device on which this interface will be used) and when
+//             <i>device operates in High-speed.
+//
+//             <o.0..10>Maximum Packet Size <0-1024>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 512.
+//               <i>For Interrupt Endpoint set value to 1 .. 1024.
+//               <i>For Isochronous Endpoint set value to 1 .. 1024.
+//             <o.11..12>Additional Transactions per Microframe
+//               <i>Specifies additional transactions per microframe to improve communication performance.
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
+//               <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
+//               <i>Value: None = 1 transaction per microframe
+//               <i>Value: 1 additional = 2 transaction per microframe
+//               <i>Value: 2 additional = 3 transaction per microframe
+//                 <0=>None
+//                 <1=>1 additional
+//                 <2=>2 additional
+#define USBD_CUSTOM_CLASS0_IF1_EP7_HS_WMAXPACKETSIZE               512
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
+//               <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF1_EP7_HS_BINTERVAL                    0
+
+//           </h>
+//         </h>
+//       </e>
+//     </h>
+
+//     <h>String Settings
+//     <i>Following settings are used to create String Descriptor(s)
+
+//       <e.0>Interface String Enable
+//       <i>Enable Interface String.
+//       <i>If disabled Interface String will not be assigned to USB Device Custom Class Interface 1.
+#define USBD_CUSTOM_CLASS0_IF1_STR_EN                              0
+
+//         <s.126>Interface String
+#define USBD_CUSTOM_CLASS0_IF1_STR                                 L"USB_CUSTOM_CLASS0_IF1"
+
+//       </e>
+//     </h>
+
+//     <h>Microsoft OS Descriptor Settings
+//     <i>Following settings are used to create Extended Compat ID OS Feature Descriptor
+
+//       <e.0>Extended Compat ID OS Feature Descriptor Function Section
+//       <i>Enable creation of function section in Extended Compat ID OS Feature Descriptor for this interface.
+#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_COMPAT_ID_EN                 0
+
+//         <s.7>compatibleID
+//         <i>compatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface.
+#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_COMPAT_ID                    "WINUSB"
+
+//         <s.7>subCompatibleID
+//         <i>subCompatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface.
+#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_SUBCOMPAT_ID                 ""
+
+//       </e>
+
+//       <h>Extended Properties OS Feature Descriptor
+//         <e.0>Custom Property Section 0
+//         <i>Enable creation of custom property 0 section in Extended Properties OS Feature Descriptor.
+#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP0_EN                     0
+
+//           <o>Data Type
+//           <i>Specifies the dwPropertyDataType field of custom property 0 section in Extended Properties OS Feature Descriptor.
+//           <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
+//             <1=>Unicode String (REG_SZ)
+//             <2=>Unicode String with environment variables (REG_EXPAND_SZ)
+//             <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
+//             <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
+//             <6=>Unicode String with symbolic link (REG_LINK)
+#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP0_DATA_TYP               1
+
+//           <s.512>Name
+#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP0_NAME                   L"DeviceInterfaceGUID"
+
+//           <h>Data
+//             <s.1024>Unicode String
+//             <i>Property Data in case Data Type is selected as Unicode String.
+#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP0_DATA_STR               L"{7D9ADCFC-E570-4B38-BF4E-8F81F68964E0}"
+
+//             <o>32-bit Integer
+//             <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
+#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP0_DATA_INT               0
+
+//           </h>
+//         </e>
+
+//         <e.0>Custom Property Section 1
+//         <i>Enable creation of custom property 1 section in Extended Properties OS Feature Descriptor.
+#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP1_EN                     0
+
+//           <o>Data Type
+//           <i>Specifies the dwPropertyDataType field of custom property 1 section in Extended Properties OS Feature Descriptor.
+//           <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
+//             <1=>Unicode String (REG_SZ)
+//             <2=>Unicode String with environment variables (REG_EXPAND_SZ)
+//             <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
+//             <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
+//             <6=>Unicode String with symbolic link (REG_LINK)
+#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP1_DATA_TYP               1
+
+//           <s.512>Name
+#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP1_NAME                   L""
+
+//           <h>Data
+//             <s.1024>Unicode String
+//             <i>Property Data in case Data Type is selected as Unicode String.
+#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP1_DATA_STR               L""
+
+//             <o>32-bit Integer
+//             <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
+#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP1_DATA_INT               0
+
+//           </h>
+//         </e>
+
+//         <e.0>Custom Property Section 2
+//         <i>Enable creation of custom property 2 section in Extended Properties OS Feature Descriptor.
+#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP2_EN                     0
+
+//           <o>Data Type
+//           <i>Specifies the dwPropertyDataType field of custom property 2 section in Extended Properties OS Feature Descriptor.
+//           <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
+//             <1=>Unicode String (REG_SZ)
+//             <2=>Unicode String with environment variables (REG_EXPAND_SZ)
+//             <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
+//             <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
+//             <6=>Unicode String with symbolic link (REG_LINK)
+#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP2_DATA_TYP               1
+
+//           <s.512>Name
+#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP2_NAME                   L""
+
+//           <h>Data
+//             <s.1024>Unicode String
+//             <i>Property Data in case Data Type is selected as Unicode String.
+#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP2_DATA_STR               L""
+
+//             <o>32-bit Integer
+//             <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
+#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP2_DATA_INT               0
+
+//           </h>
+//         </e>
+
+//         <e.0>Custom Property Section 3
+//         <i>Enable creation of custom property 3 section in Extended Properties OS Feature Descriptor.
+#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP3_EN                     0
+
+//           <o>Data Type
+//           <i>Specifies the dwPropertyDataType field of custom property 3 section in Extended Properties OS Feature Descriptor.
+//           <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
+//             <1=>Unicode String (REG_SZ)
+//             <2=>Unicode String with environment variables (REG_EXPAND_SZ)
+//             <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
+//             <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
+//             <6=>Unicode String with symbolic link (REG_LINK)
+#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP3_DATA_TYP               1
+
+//           <s.512>Name
+#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP3_NAME                   L""
+
+//           <h>Data
+//             <s.1024>Unicode String
+//             <i>Property Data in case Data Type is selected as Unicode String.
+#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP3_DATA_STR               L""
+
+//             <o>32-bit Integer
+//             <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
+#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP3_DATA_INT               0
+
+//           </h>
+//         </e>
+//       </h>
+//     </h>
+//   </e>
+
+
+//   <e>Interface
+#define USBD_CUSTOM_CLASS0_IF2_EN                                  0
+
+//     <h>Interface Settings
+//     <i>The Interface Settings are used to create the Interface Descriptor.
+//     <i>Refer to USB - USB Concepts - USB Descriptor in the MDK Components
+//     <i>User's Guide for more information about the Interface Descriptor.
+
+//       <o>Interface Number <0-255>
+//       <i>Defines the value for bInterfaceNumber
+//       <i>Each USB Device Interface has a sequential Interface Number starting with 0.
+//       <i>Several Interfaces may have the same Interface Number; in this case the value
+//       <i>of Alternate Setting is used to differ between the Interfaces. For a
+//       <i>composite device the Interface Numbers of the custom classes must be contiguous.
+#define USBD_CUSTOM_CLASS0_IF2_NUM                                 2
+
+//       <o>Alternate Setting <0=>0 <1=>1 <2=>2 <3=>3
+//       <i>Defines the value for bAlternateSetting
+//       <i>A sequential number starting with 0 to identify the Interface Descriptors
+//       <i>that share the same value for Interface Number.
+#define USBD_CUSTOM_CLASS0_IF2_ALT                                 0
+
+//       <o.0..7>Class Code
+//         <i>Class Codes are defined by USB-IF. For more information refer to
+//         <i>http://www.usb.org/developers/defined_class.
+//         <0x00=>0x00: Indicate a Null Class Code triple
+//         <0x01=>0x01: Audio
+//         <0x02=>0x02: Communications and CDC Control
+//         <0x03=>0x03: HID (Human Interface Device)
+//         <0x05=>0x05: Physical
+//         <0x06=>0x06: Image
+//         <0x07=>0x07: Printer
+//         <0x08=>0x08: Mass Storage
+//         <0x0A=>0x0A: CDC-Data
+//         <0x0B=>0x0B: Smart Card
+//         <0x0D=>0x0D: Content Security
+//         <0x0E=>0x0E: Video
+//         <0x0F=>0x0F: Personal Healthcare
+//         <0x10=>0x10: Audio/Video Devices
+//         <0xDC=>0xDC: Diagnostic Device
+//         <0xE0=>0xE0: Wireless Controller
+//         <0xEF=>0xEF: Miscellaneous
+//         <0xFE=>0xFE: Application Specific
+//         <0xFF=>0xFF: Vendor Specific
+#define USBD_CUSTOM_CLASS0_IF2_CLASS                               0xFF
+
+//       <o.0..7>Subclass Code <0x00-0xFF>
+//       <i>The possible values depend on the Class Code:
+//       <i>Class Code 0x00: Subclass Code must be 0
+//       <i>Class Code 0x01 .. 0xFE: Subclass Code is defined by USB-IF
+//       <i>Class Code 0xFF: Subclass Code can be 0x00 .. 0xFF
+#define USBD_CUSTOM_CLASS0_IF2_SUBCLASS                            0x00
+
+//       <o.0..7>Protocol Code <0x00-0xFF>
+//       <i>The Protocol Code value defines the protocol used on this interface:
+//       <i>Protocol Code 0x00: class-specific protocol not used
+//       <i>Protocol Code 0x01 .. 0xFE: class-specific protocol used
+//       <i>Protocol Code 0xFF: vendor-specific protocol used
+#define USBD_CUSTOM_CLASS0_IF2_PROTOCOL                            0x00
+
+//     </h>
+
+//     <h>Endpoint Settings
+//     <i>Following settings are used to create the Endpoint Descriptors.
+//     <i>Refer to USB - USB Concepts - USB Descriptor in the MDK Components
+//     <i>User's Guide for more information about Endpoint Descriptors.
+
+//       <e>Endpoint
+//       <i>Enable Endpoint for this interface.
+#define USBD_CUSTOM_CLASS0_IF2_EP0_EN                              0
+
+//         <o.0..1>Type
+//           <i>Select Endpoint Type.
+//           <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
+//           <i>If required, for Isochronous Endpoint, Synchronization and Usage Type 
+//           <i>can be set by manually editing define value of BMATTRIBUTES.
+//           <2=>Bulk
+//           <3=>Interrupt
+//           <1=>Isochronous
+#define USBD_CUSTOM_CLASS0_IF2_EP0_BMATTRIBUTES                    0x02
+
+//         <o.0..3>Number
+//           <i>Select Endpoint Number.
+//           <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
+//                   <1=>1   <2=>2   <3=>3   <4=>4   <5=>5   <6=>6   <7=>7
+//           <8=>8   <9=>9   <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
+//         <o.7>Direction
+//           <i>Select Endpoint Direction.
+//           <i>Endpoint Descriptor: bEndpointAddress field bit 7.
+//           <0=>OUT
+//           <1=>IN
+#define USBD_CUSTOM_CLASS0_IF2_EP0_BENDPOINTADDRESS                0x01
+
+//         <h>Speed Settings
+//           <i>Settings that are different depending on device operating speed.
+//
+//           <h>Full/Low-speed
+//             <i>Parameters apply when device operates in Full/Low-speed.
+//
+//             <o.0..9>Maximum Packet Size <0-1023>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
+//               <i>For Interrupt Endpoint set value to 1 .. 64.
+//               <i>For Isochronous Endpoint set value to 1 .. 1023.
+#define USBD_CUSTOM_CLASS0_IF2_EP0_FS_WMAXPACKETSIZE               64
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in ms).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>Setting is not used for Bulk Endpoint (set value to 0).
+//               <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF2_EP0_FS_BINTERVAL                    0
+
+//           </h>
+
+//           <h>High-speed
+//             <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
+//             <i>(n is the index of device on which this interface will be used) and when
+//             <i>device operates in High-speed.
+//
+//             <o.0..10>Maximum Packet Size <0-1024>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 512.
+//               <i>For Interrupt Endpoint set value to 1 .. 1024.
+//               <i>For Isochronous Endpoint set value to 1 .. 1024.
+//             <o.11..12>Additional Transactions per Microframe
+//               <i>Specifies additional transactions per microframe to improve communication performance.
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
+//               <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
+//               <i>Value: None = 1 transaction per microframe
+//               <i>Value: 1 additional = 2 transaction per microframe
+//               <i>Value: 2 additional = 3 transaction per microframe
+//                 <0=>None
+//                 <1=>1 additional
+//                 <2=>2 additional
+#define USBD_CUSTOM_CLASS0_IF2_EP0_HS_WMAXPACKETSIZE               512
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
+//               <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF2_EP0_HS_BINTERVAL                    0
+
+//           </h>
+//         </h>
+//       </e>
+
+//       <e>Endpoint
+//       <i>Enable Endpoint for this interface.
+#define USBD_CUSTOM_CLASS0_IF2_EP1_EN                              0
+
+//         <o.0..1>Type
+//           <i>Select Endpoint Type.
+//           <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
+//           <i>If required, for Isochronous Endpoint, Synchronization and Usage Type 
+//           <i>can be set by manually editing define value of BMATTRIBUTES.
+//           <2=>Bulk
+//           <3=>Interrupt
+//           <1=>Isochronous
+#define USBD_CUSTOM_CLASS0_IF2_EP1_BMATTRIBUTES                    0x02
+
+//         <o.0..3>Number
+//           <i>Select Endpoint Number.
+//           <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
+//                   <1=>1   <2=>2   <3=>3   <4=>4   <5=>5   <6=>6   <7=>7
+//           <8=>8   <9=>9   <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
+//         <o.7>Direction
+//           <i>Select Endpoint Direction.
+//           <i>Endpoint Descriptor: bEndpointAddress field bit 7.
+//           <0=>OUT
+//           <1=>IN
+#define USBD_CUSTOM_CLASS0_IF2_EP1_BENDPOINTADDRESS                0x81
+
+//         <h>Speed Settings
+//           <i>Settings that are different depending on device operating speed.
+//
+//           <h>Full/Low-speed
+//             <i>Parameters apply when device operates in Full/Low-speed.
+//
+//             <o.0..9>Maximum Packet Size <0-1023>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
+//               <i>For Interrupt Endpoint set value to 1 .. 64.
+//               <i>For Isochronous Endpoint set value to 1 .. 1023.
+#define USBD_CUSTOM_CLASS0_IF2_EP1_FS_WMAXPACKETSIZE               64
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in ms).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>Setting is not used for Bulk Endpoint (set value to 0).
+//               <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF2_EP1_FS_BINTERVAL                    0
+
+//           </h>
+
+//           <h>High-speed
+//             <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
+//             <i>(n is the index of device on which this interface will be used) and when
+//             <i>device operates in High-speed.
+//
+//             <o.0..10>Maximum Packet Size <0-1024>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 512.
+//               <i>For Interrupt Endpoint set value to 1 .. 1024.
+//               <i>For Isochronous Endpoint set value to 1 .. 1024.
+//             <o.11..12>Additional Transactions per Microframe
+//               <i>Specifies additional transactions per microframe to improve communication performance.
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
+//               <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
+//               <i>Value: None = 1 transaction per microframe
+//               <i>Value: 1 additional = 2 transaction per microframe
+//               <i>Value: 2 additional = 3 transaction per microframe
+//                 <0=>None
+//                 <1=>1 additional
+//                 <2=>2 additional
+#define USBD_CUSTOM_CLASS0_IF2_EP1_HS_WMAXPACKETSIZE               512
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
+//               <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF2_EP1_HS_BINTERVAL                    0
+
+//           </h>
+//         </h>
+//       </e>
+
+//       <e>Endpoint
+//       <i>Enable Endpoint for this interface.
+#define USBD_CUSTOM_CLASS0_IF2_EP2_EN                              0
+
+//         <o.0..1>Type
+//           <i>Select Endpoint Type.
+//           <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
+//           <i>If required, for Isochronous Endpoint, Synchronization and Usage Type 
+//           <i>can be set by manually editing define value of BMATTRIBUTES.
+//           <2=>Bulk
+//           <3=>Interrupt
+//           <1=>Isochronous
+#define USBD_CUSTOM_CLASS0_IF2_EP2_BMATTRIBUTES                    0x03
+
+//         <o.0..3>Number
+//           <i>Select Endpoint Number.
+//           <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
+//                   <1=>1   <2=>2   <3=>3   <4=>4   <5=>5   <6=>6   <7=>7
+//           <8=>8   <9=>9   <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
+//         <o.7>Direction
+//           <i>Select Endpoint Direction.
+//           <i>Endpoint Descriptor: bEndpointAddress field bit 7.
+//           <0=>OUT
+//           <1=>IN
+#define USBD_CUSTOM_CLASS0_IF2_EP2_BENDPOINTADDRESS                0x02
+
+//         <h>Speed Settings
+//           <i>Settings that are different depending on device operating speed.
+//
+//           <h>Full/Low-speed
+//             <i>Parameters apply when device operates in Full/Low-speed.
+//
+//             <o.0..9>Maximum Packet Size <0-1023>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
+//               <i>For Interrupt Endpoint set value to 1 .. 64.
+//               <i>For Isochronous Endpoint set value to 1 .. 1023.
+#define USBD_CUSTOM_CLASS0_IF2_EP2_FS_WMAXPACKETSIZE               64
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in ms).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>Setting is not used for Bulk Endpoint (set value to 0).
+//               <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF2_EP2_FS_BINTERVAL                    1
+
+//           </h>
+
+//           <h>High-speed
+//             <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
+//             <i>(n is the index of device on which this interface will be used) and when
+//             <i>device operates in High-speed.
+//
+//             <o.0..10>Maximum Packet Size <0-1024>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 512.
+//               <i>For Interrupt Endpoint set value to 1 .. 1024.
+//               <i>For Isochronous Endpoint set value to 1 .. 1024.
+//             <o.11..12>Additional Transactions per Microframe
+//               <i>Specifies additional transactions per microframe to improve communication performance.
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
+//               <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
+//               <i>Value: None = 1 transaction per microframe
+//               <i>Value: 1 additional = 2 transaction per microframe
+//               <i>Value: 2 additional = 3 transaction per microframe
+//                 <0=>None
+//                 <1=>1 additional
+//                 <2=>2 additional
+#define USBD_CUSTOM_CLASS0_IF2_EP2_HS_WMAXPACKETSIZE               1024
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
+//               <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF2_EP2_HS_BINTERVAL                    1
+
+//           </h>
+//         </h>
+//       </e>
+
+//       <e>Endpoint
+//       <i>Enable Endpoint for this interface.
+#define USBD_CUSTOM_CLASS0_IF2_EP3_EN                              0
+
+//         <o.0..1>Type
+//           <i>Select Endpoint Type.
+//           <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
+//           <i>If required, for Isochronous Endpoint, Synchronization and Usage Type 
+//           <i>can be set by manually editing define value of BMATTRIBUTES.
+//           <2=>Bulk
+//           <3=>Interrupt
+//           <1=>Isochronous
+#define USBD_CUSTOM_CLASS0_IF2_EP3_BMATTRIBUTES                    0x03
+
+//         <o.0..3>Number
+//           <i>Select Endpoint Number.
+//           <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
+//                   <1=>1   <2=>2   <3=>3   <4=>4   <5=>5   <6=>6   <7=>7
+//           <8=>8   <9=>9   <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
+//         <o.7>Direction
+//           <i>Select Endpoint Direction.
+//           <i>Endpoint Descriptor: bEndpointAddress field bit 7.
+//           <0=>OUT
+//           <1=>IN
+#define USBD_CUSTOM_CLASS0_IF2_EP3_BENDPOINTADDRESS                0x82
+
+//         <h>Speed Settings
+//           <i>Settings that are different depending on device operating speed.
+//
+//           <h>Full/Low-speed
+//             <i>Parameters apply when device operates in Full/Low-speed.
+//
+//             <o.0..9>Maximum Packet Size <0-1023>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
+//               <i>For Interrupt Endpoint set value to 1 .. 64.
+//               <i>For Isochronous Endpoint set value to 1 .. 1023.
+#define USBD_CUSTOM_CLASS0_IF2_EP3_FS_WMAXPACKETSIZE               64
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in ms).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>Setting is not used for Bulk Endpoint (set value to 0).
+//               <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF2_EP3_FS_BINTERVAL                    1
+
+//           </h>
+
+//           <h>High-speed
+//             <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
+//             <i>(n is the index of device on which this interface will be used) and when
+//             <i>device operates in High-speed.
+//
+//             <o.0..10>Maximum Packet Size <0-1024>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 512.
+//               <i>For Interrupt Endpoint set value to 1 .. 1024.
+//               <i>For Isochronous Endpoint set value to 1 .. 1024.
+//             <o.11..12>Additional Transactions per Microframe
+//               <i>Specifies additional transactions per microframe to improve communication performance.
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
+//               <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
+//               <i>Value: None = 1 transaction per microframe
+//               <i>Value: 1 additional = 2 transaction per microframe
+//               <i>Value: 2 additional = 3 transaction per microframe
+//                 <0=>None
+//                 <1=>1 additional
+//                 <2=>2 additional
+#define USBD_CUSTOM_CLASS0_IF2_EP3_HS_WMAXPACKETSIZE               1024
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
+//               <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF2_EP3_HS_BINTERVAL                    1
+
+//           </h>
+//         </h>
+//       </e>
+
+//       <e>Endpoint
+//       <i>Enable Endpoint for this interface.
+#define USBD_CUSTOM_CLASS0_IF2_EP4_EN                              0
+
+//         <o.0..1>Type
+//           <i>Select Endpoint Type.
+//           <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
+//           <i>If required, for Isochronous Endpoint, Synchronization and Usage Type 
+//           <i>can be set by manually editing define value of BMATTRIBUTES.
+//           <2=>Bulk
+//           <3=>Interrupt
+//           <1=>Isochronous
+#define USBD_CUSTOM_CLASS0_IF2_EP4_BMATTRIBUTES                    0x01
+
+//         <o.0..3>Number
+//           <i>Select Endpoint Number.
+//           <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
+//                   <1=>1   <2=>2   <3=>3   <4=>4   <5=>5   <6=>6   <7=>7
+//           <8=>8   <9=>9   <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
+//         <o.7>Direction
+//           <i>Select Endpoint Direction.
+//           <i>Endpoint Descriptor: bEndpointAddress field bit 7.
+//           <0=>OUT
+//           <1=>IN
+#define USBD_CUSTOM_CLASS0_IF2_EP4_BENDPOINTADDRESS                0x03
+
+//         <h>Speed Settings
+//           <i>Settings that are different depending on device operating speed.
+//
+//           <h>Full/Low-speed
+//             <i>Parameters apply when device operates in Full/Low-speed.
+//
+//             <o.0..9>Maximum Packet Size <0-1023>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
+//               <i>For Interrupt Endpoint set value to 1 .. 64.
+//               <i>For Isochronous Endpoint set value to 1 .. 1023.
+#define USBD_CUSTOM_CLASS0_IF2_EP4_FS_WMAXPACKETSIZE               1023
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in ms).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>Setting is not used for Bulk Endpoint (set value to 0).
+//               <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF2_EP4_FS_BINTERVAL                    1
+
+//           </h>
+
+//           <h>High-speed
+//             <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
+//             <i>(n is the index of device on which this interface will be used) and when
+//             <i>device operates in High-speed.
+//
+//             <o.0..10>Maximum Packet Size <0-1024>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 512.
+//               <i>For Interrupt Endpoint set value to 1 .. 1024.
+//               <i>For Isochronous Endpoint set value to 1 .. 1024.
+//             <o.11..12>Additional Transactions per Microframe
+//               <i>Specifies additional transactions per microframe to improve communication performance.
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
+//               <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
+//               <i>Value: None = 1 transaction per microframe
+//               <i>Value: 1 additional = 2 transaction per microframe
+//               <i>Value: 2 additional = 3 transaction per microframe
+//                 <0=>None
+//                 <1=>1 additional
+//                 <2=>2 additional
+#define USBD_CUSTOM_CLASS0_IF2_EP4_HS_WMAXPACKETSIZE               1024
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
+//               <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF2_EP4_HS_BINTERVAL                    1
+
+//           </h>
+//         </h>
+//       </e>
+
+//       <e>Endpoint
+//       <i>Enable Endpoint for this interface.
+#define USBD_CUSTOM_CLASS0_IF2_EP5_EN                              0
+
+//         <o.0..1>Type
+//           <i>Select Endpoint Type.
+//           <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
+//           <i>If required, for Isochronous Endpoint, Synchronization and Usage Type 
+//           <i>can be set by manually editing define value of BMATTRIBUTES.
+//           <2=>Bulk
+//           <3=>Interrupt
+//           <1=>Isochronous
+#define USBD_CUSTOM_CLASS0_IF2_EP5_BMATTRIBUTES                    0x01
+
+//         <o.0..3>Number
+//           <i>Select Endpoint Number.
+//           <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
+//                   <1=>1   <2=>2   <3=>3   <4=>4   <5=>5   <6=>6   <7=>7
+//           <8=>8   <9=>9   <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
+//         <o.7>Direction
+//           <i>Select Endpoint Direction.
+//           <i>Endpoint Descriptor: bEndpointAddress field bit 7.
+//           <0=>OUT
+//           <1=>IN
+#define USBD_CUSTOM_CLASS0_IF2_EP5_BENDPOINTADDRESS                0x83
+
+//         <h>Speed Settings
+//           <i>Settings that are different depending on device operating speed.
+//
+//           <h>Full/Low-speed
+//             <i>Parameters apply when device operates in Full/Low-speed.
+//
+//             <o.0..9>Maximum Packet Size <0-1023>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
+//               <i>For Interrupt Endpoint set value to 1 .. 64.
+//               <i>For Isochronous Endpoint set value to 1 .. 1023.
+#define USBD_CUSTOM_CLASS0_IF2_EP5_FS_WMAXPACKETSIZE               1023
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in ms).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>Setting is not used for Bulk Endpoint (set value to 0).
+//               <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF2_EP5_FS_BINTERVAL                    1
+
+//           </h>
+
+//           <h>High-speed
+//             <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
+//             <i>(n is the index of device on which this interface will be used) and when
+//             <i>device operates in High-speed.
+//
+//             <o.0..10>Maximum Packet Size <0-1024>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 512.
+//               <i>For Interrupt Endpoint set value to 1 .. 1024.
+//               <i>For Isochronous Endpoint set value to 1 .. 1024.
+//             <o.11..12>Additional Transactions per Microframe
+//               <i>Specifies additional transactions per microframe to improve communication performance.
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
+//               <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
+//               <i>Value: None = 1 transaction per microframe
+//               <i>Value: 1 additional = 2 transaction per microframe
+//               <i>Value: 2 additional = 3 transaction per microframe
+//                 <0=>None
+//                 <1=>1 additional
+//                 <2=>2 additional
+#define USBD_CUSTOM_CLASS0_IF2_EP5_HS_WMAXPACKETSIZE               1024
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
+//               <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF2_EP5_HS_BINTERVAL                    1
+
+//           </h>
+//         </h>
+//       </e>
+
+//       <e>Endpoint
+//       <i>Enable Endpoint for this interface.
+#define USBD_CUSTOM_CLASS0_IF2_EP6_EN                              0
+
+//         <o.0..1>Type
+//           <i>Select Endpoint Type.
+//           <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
+//           <i>If required, for Isochronous Endpoint, Synchronization and Usage Type 
+//           <i>can be set by manually editing define value of BMATTRIBUTES.
+//           <2=>Bulk
+//           <3=>Interrupt
+//           <1=>Isochronous
+#define USBD_CUSTOM_CLASS0_IF2_EP6_BMATTRIBUTES                    0x02
+
+//         <o.0..3>Number
+//           <i>Select Endpoint Number.
+//           <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
+//                   <1=>1   <2=>2   <3=>3   <4=>4   <5=>5   <6=>6   <7=>7
+//           <8=>8   <9=>9   <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
+//         <o.7>Direction
+//           <i>Select Endpoint Direction.
+//           <i>Endpoint Descriptor: bEndpointAddress field bit 7.
+//           <0=>OUT
+//           <1=>IN
+#define USBD_CUSTOM_CLASS0_IF2_EP6_BENDPOINTADDRESS                0x04
+
+//         <h>Speed Settings
+//           <i>Settings that are different depending on device operating speed.
+//
+//           <h>Full/Low-speed
+//             <i>Parameters apply when device operates in Full/Low-speed.
+//
+//             <o.0..9>Maximum Packet Size <0-1023>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
+//               <i>For Interrupt Endpoint set value to 1 .. 64.
+//               <i>For Isochronous Endpoint set value to 1 .. 1023.
+#define USBD_CUSTOM_CLASS0_IF2_EP6_FS_WMAXPACKETSIZE               64
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in ms).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>Setting is not used for Bulk Endpoint (set value to 0).
+//               <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF2_EP6_FS_BINTERVAL                    0
+
+//           </h>
+
+//           <h>High-speed
+//             <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
+//             <i>(n is the index of device on which this interface will be used) and when
+//             <i>device operates in High-speed.
+//
+//             <o.0..10>Maximum Packet Size <0-1024>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 512.
+//               <i>For Interrupt Endpoint set value to 1 .. 1024.
+//               <i>For Isochronous Endpoint set value to 1 .. 1024.
+//             <o.11..12>Additional Transactions per Microframe
+//               <i>Specifies additional transactions per microframe to improve communication performance.
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
+//               <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
+//               <i>Value: None = 1 transaction per microframe
+//               <i>Value: 1 additional = 2 transaction per microframe
+//               <i>Value: 2 additional = 3 transaction per microframe
+//                 <0=>None
+//                 <1=>1 additional
+//                 <2=>2 additional
+#define USBD_CUSTOM_CLASS0_IF2_EP6_HS_WMAXPACKETSIZE               512
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
+//               <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF2_EP6_HS_BINTERVAL                    0
+
+//           </h>
+//         </h>
+//       </e>
+
+//       <e>Endpoint
+//       <i>Enable Endpoint for this interface.
+#define USBD_CUSTOM_CLASS0_IF2_EP7_EN                              0
+
+//         <o.0..1>Type
+//           <i>Select Endpoint Type.
+//           <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
+//           <i>If required, for Isochronous Endpoint, Synchronization and Usage Type 
+//           <i>can be set by manually editing define value of BMATTRIBUTES.
+//           <2=>Bulk
+//           <3=>Interrupt
+//           <1=>Isochronous
+#define USBD_CUSTOM_CLASS0_IF2_EP7_BMATTRIBUTES                    0x02
+
+//         <o.0..3>Number
+//           <i>Select Endpoint Number.
+//           <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
+//                   <1=>1   <2=>2   <3=>3   <4=>4   <5=>5   <6=>6   <7=>7
+//           <8=>8   <9=>9   <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
+//         <o.7>Direction
+//           <i>Select Endpoint Direction.
+//           <i>Endpoint Descriptor: bEndpointAddress field bit 7.
+//           <0=>OUT
+//           <1=>IN
+#define USBD_CUSTOM_CLASS0_IF2_EP7_BENDPOINTADDRESS                0x84
+
+//         <h>Speed Settings
+//           <i>Settings that are different depending on device operating speed.
+//
+//           <h>Full/Low-speed
+//             <i>Parameters apply when device operates in Full/Low-speed.
+//
+//             <o.0..9>Maximum Packet Size <0-1023>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
+//               <i>For Interrupt Endpoint set value to 1 .. 64.
+//               <i>For Isochronous Endpoint set value to 1 .. 1023.
+#define USBD_CUSTOM_CLASS0_IF2_EP7_FS_WMAXPACKETSIZE               64
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in ms).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>Setting is not used for Bulk Endpoint (set value to 0).
+//               <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF2_EP7_FS_BINTERVAL                    0
+
+//           </h>
+
+//           <h>High-speed
+//             <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
+//             <i>(n is the index of device on which this interface will be used) and when
+//             <i>device operates in High-speed.
+//
+//             <o.0..10>Maximum Packet Size <0-1024>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 512.
+//               <i>For Interrupt Endpoint set value to 1 .. 1024.
+//               <i>For Isochronous Endpoint set value to 1 .. 1024.
+//             <o.11..12>Additional Transactions per Microframe
+//               <i>Specifies additional transactions per microframe to improve communication performance.
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
+//               <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
+//               <i>Value: None = 1 transaction per microframe
+//               <i>Value: 1 additional = 2 transaction per microframe
+//               <i>Value: 2 additional = 3 transaction per microframe
+//                 <0=>None
+//                 <1=>1 additional
+//                 <2=>2 additional
+#define USBD_CUSTOM_CLASS0_IF2_EP7_HS_WMAXPACKETSIZE               512
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
+//               <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF2_EP7_HS_BINTERVAL                    0
+
+//           </h>
+//         </h>
+//       </e>
+//     </h>
+
+//     <h>String Settings
+//     <i>Following settings are used to create String Descriptor(s)
+
+//       <e.0>Interface String Enable
+//       <i>Enable Interface String.
+//       <i>If disabled Interface String will not be assigned to USB Device Custom Class Interface 2.
+#define USBD_CUSTOM_CLASS0_IF2_STR_EN                              0
+
+//         <s.126>Interface String
+#define USBD_CUSTOM_CLASS0_IF2_STR                                 L"USB_CUSTOM_CLASS0_IF2"
+
+//       </e>
+//     </h>
+
+//     <h>Microsoft OS Descriptor Settings
+//     <i>Following settings are used to create Extended Compat ID OS Feature Descriptor
+
+//       <e.0>Extended Compat ID OS Feature Descriptor Function Section
+//       <i>Enable creation of function section in Extended Compat ID OS Feature Descriptor for this interface.
+#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_COMPAT_ID_EN                 0
+
+//         <s.7>compatibleID
+//         <i>compatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface.
+#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_COMPAT_ID                    "WINUSB"
+
+//         <s.7>subCompatibleID
+//         <i>subCompatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface.
+#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_SUBCOMPAT_ID                 ""
+
+//       </e>
+
+//       <h>Extended Properties OS Feature Descriptor
+//         <e.0>Custom Property Section 0
+//         <i>Enable creation of custom property 0 section in Extended Properties OS Feature Descriptor.
+#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP0_EN                     0
+
+//           <o>Data Type
+//           <i>Specifies the dwPropertyDataType field of custom property 0 section in Extended Properties OS Feature Descriptor.
+//           <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
+//             <1=>Unicode String (REG_SZ)
+//             <2=>Unicode String with environment variables (REG_EXPAND_SZ)
+//             <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
+//             <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
+//             <6=>Unicode String with symbolic link (REG_LINK)
+#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP0_DATA_TYP               1
+
+//           <s.512>Name
+#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP0_NAME                   L"DeviceInterfaceGUID"
+
+//           <h>Data
+//             <s.1024>Unicode String
+//             <i>Property Data in case Data Type is selected as Unicode String.
+#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP0_DATA_STR               L"{7D9ADCFC-E570-4B38-BF4E-8F81F68964E0}"
+
+//             <o>32-bit Integer
+//             <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
+#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP0_DATA_INT               0
+
+//           </h>
+//         </e>
+
+//         <e.0>Custom Property Section 1
+//         <i>Enable creation of custom property 1 section in Extended Properties OS Feature Descriptor.
+#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP1_EN                     0
+
+//           <o>Data Type
+//           <i>Specifies the dwPropertyDataType field of custom property 1 section in Extended Properties OS Feature Descriptor.
+//           <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
+//             <1=>Unicode String (REG_SZ)
+//             <2=>Unicode String with environment variables (REG_EXPAND_SZ)
+//             <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
+//             <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
+//             <6=>Unicode String with symbolic link (REG_LINK)
+#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP1_DATA_TYP               1
+
+//           <s.512>Name
+#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP1_NAME                   L""
+
+//           <h>Data
+//             <s.1024>Unicode String
+//             <i>Property Data in case Data Type is selected as Unicode String.
+#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP1_DATA_STR               L""
+
+//             <o>32-bit Integer
+//             <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
+#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP1_DATA_INT               0
+
+//           </h>
+//         </e>
+
+//         <e.0>Custom Property Section 2
+//         <i>Enable creation of custom property 2 section in Extended Properties OS Feature Descriptor.
+#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP2_EN                     0
+
+//           <o>Data Type
+//           <i>Specifies the dwPropertyDataType field of custom property 2 section in Extended Properties OS Feature Descriptor.
+//           <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
+//             <1=>Unicode String (REG_SZ)
+//             <2=>Unicode String with environment variables (REG_EXPAND_SZ)
+//             <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
+//             <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
+//             <6=>Unicode String with symbolic link (REG_LINK)
+#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP2_DATA_TYP               1
+
+//           <s.512>Name
+#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP2_NAME                   L""
+
+//           <h>Data
+//             <s.1024>Unicode String
+//             <i>Property Data in case Data Type is selected as Unicode String.
+#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP2_DATA_STR               L""
+
+//             <o>32-bit Integer
+//             <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
+#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP2_DATA_INT               0
+
+//           </h>
+//         </e>
+
+//         <e.0>Custom Property Section 3
+//         <i>Enable creation of custom property 3 section in Extended Properties OS Feature Descriptor.
+#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP3_EN                     0
+
+//           <o>Data Type
+//           <i>Specifies the dwPropertyDataType field of custom property 3 section in Extended Properties OS Feature Descriptor.
+//           <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
+//             <1=>Unicode String (REG_SZ)
+//             <2=>Unicode String with environment variables (REG_EXPAND_SZ)
+//             <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
+//             <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
+//             <6=>Unicode String with symbolic link (REG_LINK)
+#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP3_DATA_TYP               1
+
+//           <s.512>Name
+#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP3_NAME                   L""
+
+//           <h>Data
+//             <s.1024>Unicode String
+//             <i>Property Data in case Data Type is selected as Unicode String.
+#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP3_DATA_STR               L""
+
+//             <o>32-bit Integer
+//             <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
+#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP3_DATA_INT               0
+
+//           </h>
+//         </e>
+//       </h>
+//     </h>
+//   </e>
+
+
+//   <e>Interface
+#define USBD_CUSTOM_CLASS0_IF3_EN                                  0
+
+//     <h>Interface Settings
+//     <i>The Interface Settings are used to create the Interface Descriptor.
+//     <i>Refer to USB - USB Concepts - USB Descriptor in the MDK Components
+//     <i>User's Guide for more information about the Interface Descriptor.
+
+//       <o>Interface Number <0-255>
+//       <i>Defines the value for bInterfaceNumber
+//       <i>Each USB Device Interface has a sequential Interface Number starting with 0.
+//       <i>Several Interfaces may have the same Interface Number; in this case the value
+//       <i>of Alternate Setting is used to differ between the Interfaces. For a
+//       <i>composite device the Interface Numbers of the custom classes must be contiguous.
+#define USBD_CUSTOM_CLASS0_IF3_NUM                                 3
+
+//       <o>Alternate Setting <0=>0 <1=>1 <2=>2 <3=>3
+//       <i>Defines the value for bAlternateSetting
+//       <i>A sequential number starting with 0 to identify the Interface Descriptors
+//       <i>that share the same value for Interface Number.
+#define USBD_CUSTOM_CLASS0_IF3_ALT                                 0
+
+//       <o.0..7>Class Code
+//         <i>Class Codes are defined by USB-IF. For more information refer to
+//         <i>http://www.usb.org/developers/defined_class.
+//         <0x00=>0x00: Indicate a Null Class Code triple
+//         <0x01=>0x01: Audio
+//         <0x02=>0x02: Communications and CDC Control
+//         <0x03=>0x03: HID (Human Interface Device)
+//         <0x05=>0x05: Physical
+//         <0x06=>0x06: Image
+//         <0x07=>0x07: Printer
+//         <0x08=>0x08: Mass Storage
+//         <0x0A=>0x0A: CDC-Data
+//         <0x0B=>0x0B: Smart Card
+//         <0x0D=>0x0D: Content Security
+//         <0x0E=>0x0E: Video
+//         <0x0F=>0x0F: Personal Healthcare
+//         <0x10=>0x10: Audio/Video Devices
+//         <0xDC=>0xDC: Diagnostic Device
+//         <0xE0=>0xE0: Wireless Controller
+//         <0xEF=>0xEF: Miscellaneous
+//         <0xFE=>0xFE: Application Specific
+//         <0xFF=>0xFF: Vendor Specific
+#define USBD_CUSTOM_CLASS0_IF3_CLASS                               0xFF
+
+//       <o.0..7>Subclass Code <0x00-0xFF>
+//       <i>The possible values depend on the Class Code:
+//       <i>Class Code 0x00: Subclass Code must be 0
+//       <i>Class Code 0x01 .. 0xFE: Subclass Code is defined by USB-IF
+//       <i>Class Code 0xFF: Subclass Code can be 0x00 .. 0xFF
+#define USBD_CUSTOM_CLASS0_IF3_SUBCLASS                            0x00
+
+//       <o.0..7>Protocol Code <0x00-0xFF>
+//       <i>The Protocol Code value defines the protocol used on this interface:
+//       <i>Protocol Code 0x00: class-specific protocol not used
+//       <i>Protocol Code 0x01 .. 0xFE: class-specific protocol used
+//       <i>Protocol Code 0xFF: vendor-specific protocol used
+#define USBD_CUSTOM_CLASS0_IF3_PROTOCOL                            0x00
+
+//     </h>
+
+//     <h>Endpoint Settings
+//     <i>Following settings are used to create the Endpoint Descriptors.
+//     <i>Refer to USB - USB Concepts - USB Descriptor in the MDK Components
+//     <i>User's Guide for more information about Endpoint Descriptors.
+
+//       <e>Endpoint
+//       <i>Enable Endpoint for this interface.
+#define USBD_CUSTOM_CLASS0_IF3_EP0_EN                              0
+
+//         <o.0..1>Type
+//           <i>Select Endpoint Type.
+//           <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
+//           <i>If required, for Isochronous Endpoint, Synchronization and Usage Type 
+//           <i>can be set by manually editing define value of BMATTRIBUTES.
+//           <2=>Bulk
+//           <3=>Interrupt
+//           <1=>Isochronous
+#define USBD_CUSTOM_CLASS0_IF3_EP0_BMATTRIBUTES                    0x02
+
+//         <o.0..3>Number
+//           <i>Select Endpoint Number.
+//           <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
+//                   <1=>1   <2=>2   <3=>3   <4=>4   <5=>5   <6=>6   <7=>7
+//           <8=>8   <9=>9   <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
+//         <o.7>Direction
+//           <i>Select Endpoint Direction.
+//           <i>Endpoint Descriptor: bEndpointAddress field bit 7.
+//           <0=>OUT
+//           <1=>IN
+#define USBD_CUSTOM_CLASS0_IF3_EP0_BENDPOINTADDRESS                0x01
+
+//         <h>Speed Settings
+//           <i>Settings that are different depending on device operating speed.
+//
+//           <h>Full/Low-speed
+//             <i>Parameters apply when device operates in Full/Low-speed.
+//
+//             <o.0..9>Maximum Packet Size <0-1023>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
+//               <i>For Interrupt Endpoint set value to 1 .. 64.
+//               <i>For Isochronous Endpoint set value to 1 .. 1023.
+#define USBD_CUSTOM_CLASS0_IF3_EP0_FS_WMAXPACKETSIZE               64
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in ms).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>Setting is not used for Bulk Endpoint (set value to 0).
+//               <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF3_EP0_FS_BINTERVAL                    0
+
+//           </h>
+
+//           <h>High-speed
+//             <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
+//             <i>(n is the index of device on which this interface will be used) and when
+//             <i>device operates in High-speed.
+//
+//             <o.0..10>Maximum Packet Size <0-1024>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 512.
+//               <i>For Interrupt Endpoint set value to 1 .. 1024.
+//               <i>For Isochronous Endpoint set value to 1 .. 1024.
+//             <o.11..12>Additional Transactions per Microframe
+//               <i>Specifies additional transactions per microframe to improve communication performance.
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
+//               <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
+//               <i>Value: None = 1 transaction per microframe
+//               <i>Value: 1 additional = 2 transaction per microframe
+//               <i>Value: 2 additional = 3 transaction per microframe
+//                 <0=>None
+//                 <1=>1 additional
+//                 <2=>2 additional
+#define USBD_CUSTOM_CLASS0_IF3_EP0_HS_WMAXPACKETSIZE               512
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
+//               <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF3_EP0_HS_BINTERVAL                    0
+
+//           </h>
+//         </h>
+//       </e>
+
+//       <e>Endpoint
+//       <i>Enable Endpoint for this interface.
+#define USBD_CUSTOM_CLASS0_IF3_EP1_EN                              0
+
+//         <o.0..1>Type
+//           <i>Select Endpoint Type.
+//           <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
+//           <i>If required, for Isochronous Endpoint, Synchronization and Usage Type 
+//           <i>can be set by manually editing define value of BMATTRIBUTES.
+//           <2=>Bulk
+//           <3=>Interrupt
+//           <1=>Isochronous
+#define USBD_CUSTOM_CLASS0_IF3_EP1_BMATTRIBUTES                    0x02
+
+//         <o.0..3>Number
+//           <i>Select Endpoint Number.
+//           <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
+//                   <1=>1   <2=>2   <3=>3   <4=>4   <5=>5   <6=>6   <7=>7
+//           <8=>8   <9=>9   <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
+//         <o.7>Direction
+//           <i>Select Endpoint Direction.
+//           <i>Endpoint Descriptor: bEndpointAddress field bit 7.
+//           <0=>OUT
+//           <1=>IN
+#define USBD_CUSTOM_CLASS0_IF3_EP1_BENDPOINTADDRESS                0x81
+
+//         <h>Speed Settings
+//           <i>Settings that are different depending on device operating speed.
+//
+//           <h>Full/Low-speed
+//             <i>Parameters apply when device operates in Full/Low-speed.
+//
+//             <o.0..9>Maximum Packet Size <0-1023>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
+//               <i>For Interrupt Endpoint set value to 1 .. 64.
+//               <i>For Isochronous Endpoint set value to 1 .. 1023.
+#define USBD_CUSTOM_CLASS0_IF3_EP1_FS_WMAXPACKETSIZE               64
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in ms).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>Setting is not used for Bulk Endpoint (set value to 0).
+//               <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF3_EP1_FS_BINTERVAL                    0
+
+//           </h>
+
+//           <h>High-speed
+//             <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
+//             <i>(n is the index of device on which this interface will be used) and when
+//             <i>device operates in High-speed.
+//
+//             <o.0..10>Maximum Packet Size <0-1024>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 512.
+//               <i>For Interrupt Endpoint set value to 1 .. 1024.
+//               <i>For Isochronous Endpoint set value to 1 .. 1024.
+//             <o.11..12>Additional Transactions per Microframe
+//               <i>Specifies additional transactions per microframe to improve communication performance.
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
+//               <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
+//               <i>Value: None = 1 transaction per microframe
+//               <i>Value: 1 additional = 2 transaction per microframe
+//               <i>Value: 2 additional = 3 transaction per microframe
+//                 <0=>None
+//                 <1=>1 additional
+//                 <2=>2 additional
+#define USBD_CUSTOM_CLASS0_IF3_EP1_HS_WMAXPACKETSIZE               512
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
+//               <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF3_EP1_HS_BINTERVAL                    0
+
+//           </h>
+//         </h>
+//       </e>
+
+//       <e>Endpoint
+//       <i>Enable Endpoint for this interface.
+#define USBD_CUSTOM_CLASS0_IF3_EP2_EN                              0
+
+//         <o.0..1>Type
+//           <i>Select Endpoint Type.
+//           <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
+//           <i>If required, for Isochronous Endpoint, Synchronization and Usage Type 
+//           <i>can be set by manually editing define value of BMATTRIBUTES.
+//           <2=>Bulk
+//           <3=>Interrupt
+//           <1=>Isochronous
+#define USBD_CUSTOM_CLASS0_IF3_EP2_BMATTRIBUTES                    0x03
+
+//         <o.0..3>Number
+//           <i>Select Endpoint Number.
+//           <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
+//                   <1=>1   <2=>2   <3=>3   <4=>4   <5=>5   <6=>6   <7=>7
+//           <8=>8   <9=>9   <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
+//         <o.7>Direction
+//           <i>Select Endpoint Direction.
+//           <i>Endpoint Descriptor: bEndpointAddress field bit 7.
+//           <0=>OUT
+//           <1=>IN
+#define USBD_CUSTOM_CLASS0_IF3_EP2_BENDPOINTADDRESS                0x02
+
+//         <h>Speed Settings
+//           <i>Settings that are different depending on device operating speed.
+//
+//           <h>Full/Low-speed
+//             <i>Parameters apply when device operates in Full/Low-speed.
+//
+//             <o.0..9>Maximum Packet Size <0-1023>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
+//               <i>For Interrupt Endpoint set value to 1 .. 64.
+//               <i>For Isochronous Endpoint set value to 1 .. 1023.
+#define USBD_CUSTOM_CLASS0_IF3_EP2_FS_WMAXPACKETSIZE               64
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in ms).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>Setting is not used for Bulk Endpoint (set value to 0).
+//               <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF3_EP2_FS_BINTERVAL                    1
+
+//           </h>
+
+//           <h>High-speed
+//             <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
+//             <i>(n is the index of device on which this interface will be used) and when
+//             <i>device operates in High-speed.
+//
+//             <o.0..10>Maximum Packet Size <0-1024>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 512.
+//               <i>For Interrupt Endpoint set value to 1 .. 1024.
+//               <i>For Isochronous Endpoint set value to 1 .. 1024.
+//             <o.11..12>Additional Transactions per Microframe
+//               <i>Specifies additional transactions per microframe to improve communication performance.
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
+//               <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
+//               <i>Value: None = 1 transaction per microframe
+//               <i>Value: 1 additional = 2 transaction per microframe
+//               <i>Value: 2 additional = 3 transaction per microframe
+//                 <0=>None
+//                 <1=>1 additional
+//                 <2=>2 additional
+#define USBD_CUSTOM_CLASS0_IF3_EP2_HS_WMAXPACKETSIZE               1024
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
+//               <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF3_EP2_HS_BINTERVAL                    1
+
+//           </h>
+//         </h>
+//       </e>
+
+//       <e>Endpoint
+//       <i>Enable Endpoint for this interface.
+#define USBD_CUSTOM_CLASS0_IF3_EP3_EN                              0
+
+//         <o.0..1>Type
+//           <i>Select Endpoint Type.
+//           <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
+//           <i>If required, for Isochronous Endpoint, Synchronization and Usage Type 
+//           <i>can be set by manually editing define value of BMATTRIBUTES.
+//           <2=>Bulk
+//           <3=>Interrupt
+//           <1=>Isochronous
+#define USBD_CUSTOM_CLASS0_IF3_EP3_BMATTRIBUTES                    0x03
+
+//         <o.0..3>Number
+//           <i>Select Endpoint Number.
+//           <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
+//                   <1=>1   <2=>2   <3=>3   <4=>4   <5=>5   <6=>6   <7=>7
+//           <8=>8   <9=>9   <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
+//         <o.7>Direction
+//           <i>Select Endpoint Direction.
+//           <i>Endpoint Descriptor: bEndpointAddress field bit 7.
+//           <0=>OUT
+//           <1=>IN
+#define USBD_CUSTOM_CLASS0_IF3_EP3_BENDPOINTADDRESS                0x82
+
+//         <h>Speed Settings
+//           <i>Settings that are different depending on device operating speed.
+//
+//           <h>Full/Low-speed
+//             <i>Parameters apply when device operates in Full/Low-speed.
+//
+//             <o.0..9>Maximum Packet Size <0-1023>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
+//               <i>For Interrupt Endpoint set value to 1 .. 64.
+//               <i>For Isochronous Endpoint set value to 1 .. 1023.
+#define USBD_CUSTOM_CLASS0_IF3_EP3_FS_WMAXPACKETSIZE               64
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in ms).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>Setting is not used for Bulk Endpoint (set value to 0).
+//               <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF3_EP3_FS_BINTERVAL                    1
+
+//           </h>
+
+//           <h>High-speed
+//             <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
+//             <i>(n is the index of device on which this interface will be used) and when
+//             <i>device operates in High-speed.
+//
+//             <o.0..10>Maximum Packet Size <0-1024>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 512.
+//               <i>For Interrupt Endpoint set value to 1 .. 1024.
+//               <i>For Isochronous Endpoint set value to 1 .. 1024.
+//             <o.11..12>Additional Transactions per Microframe
+//               <i>Specifies additional transactions per microframe to improve communication performance.
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
+//               <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
+//               <i>Value: None = 1 transaction per microframe
+//               <i>Value: 1 additional = 2 transaction per microframe
+//               <i>Value: 2 additional = 3 transaction per microframe
+//                 <0=>None
+//                 <1=>1 additional
+//                 <2=>2 additional
+#define USBD_CUSTOM_CLASS0_IF3_EP3_HS_WMAXPACKETSIZE               1024
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
+//               <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF3_EP3_HS_BINTERVAL                    1
+
+//           </h>
+//         </h>
+//       </e>
+
+//       <e>Endpoint
+//       <i>Enable Endpoint for this interface.
+#define USBD_CUSTOM_CLASS0_IF3_EP4_EN                              0
+
+//         <o.0..1>Type
+//           <i>Select Endpoint Type.
+//           <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
+//           <i>If required, for Isochronous Endpoint, Synchronization and Usage Type 
+//           <i>can be set by manually editing define value of BMATTRIBUTES.
+//           <2=>Bulk
+//           <3=>Interrupt
+//           <1=>Isochronous
+#define USBD_CUSTOM_CLASS0_IF3_EP4_BMATTRIBUTES                    0x01
+
+//         <o.0..3>Number
+//           <i>Select Endpoint Number.
+//           <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
+//                   <1=>1   <2=>2   <3=>3   <4=>4   <5=>5   <6=>6   <7=>7
+//           <8=>8   <9=>9   <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
+//         <o.7>Direction
+//           <i>Select Endpoint Direction.
+//           <i>Endpoint Descriptor: bEndpointAddress field bit 7.
+//           <0=>OUT
+//           <1=>IN
+#define USBD_CUSTOM_CLASS0_IF3_EP4_BENDPOINTADDRESS                0x03
+
+//         <h>Speed Settings
+//           <i>Settings that are different depending on device operating speed.
+//
+//           <h>Full/Low-speed
+//             <i>Parameters apply when device operates in Full/Low-speed.
+//
+//             <o.0..9>Maximum Packet Size <0-1023>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
+//               <i>For Interrupt Endpoint set value to 1 .. 64.
+//               <i>For Isochronous Endpoint set value to 1 .. 1023.
+#define USBD_CUSTOM_CLASS0_IF3_EP4_FS_WMAXPACKETSIZE               1023
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in ms).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>Setting is not used for Bulk Endpoint (set value to 0).
+//               <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF3_EP4_FS_BINTERVAL                    1
+
+//           </h>
+
+//           <h>High-speed
+//             <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
+//             <i>(n is the index of device on which this interface will be used) and when
+//             <i>device operates in High-speed.
+//
+//             <o.0..10>Maximum Packet Size <0-1024>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 512.
+//               <i>For Interrupt Endpoint set value to 1 .. 1024.
+//               <i>For Isochronous Endpoint set value to 1 .. 1024.
+//             <o.11..12>Additional Transactions per Microframe
+//               <i>Specifies additional transactions per microframe to improve communication performance.
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
+//               <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
+//               <i>Value: None = 1 transaction per microframe
+//               <i>Value: 1 additional = 2 transaction per microframe
+//               <i>Value: 2 additional = 3 transaction per microframe
+//                 <0=>None
+//                 <1=>1 additional
+//                 <2=>2 additional
+#define USBD_CUSTOM_CLASS0_IF3_EP4_HS_WMAXPACKETSIZE               1024
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
+//               <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF3_EP4_HS_BINTERVAL                    1
+
+//           </h>
+//         </h>
+//       </e>
+
+//       <e>Endpoint
+//       <i>Enable Endpoint for this interface.
+#define USBD_CUSTOM_CLASS0_IF3_EP5_EN                              0
+
+//         <o.0..1>Type
+//           <i>Select Endpoint Type.
+//           <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
+//           <i>If required, for Isochronous Endpoint, Synchronization and Usage Type 
+//           <i>can be set by manually editing define value of BMATTRIBUTES.
+//           <2=>Bulk
+//           <3=>Interrupt
+//           <1=>Isochronous
+#define USBD_CUSTOM_CLASS0_IF3_EP5_BMATTRIBUTES                    0x01
+
+//         <o.0..3>Number
+//           <i>Select Endpoint Number.
+//           <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
+//                   <1=>1   <2=>2   <3=>3   <4=>4   <5=>5   <6=>6   <7=>7
+//           <8=>8   <9=>9   <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
+//         <o.7>Direction
+//           <i>Select Endpoint Direction.
+//           <i>Endpoint Descriptor: bEndpointAddress field bit 7.
+//           <0=>OUT
+//           <1=>IN
+#define USBD_CUSTOM_CLASS0_IF3_EP5_BENDPOINTADDRESS                0x83
+
+//         <h>Speed Settings
+//           <i>Settings that are different depending on device operating speed.
+//
+//           <h>Full/Low-speed
+//             <i>Parameters apply when device operates in Full/Low-speed.
+//
+//             <o.0..9>Maximum Packet Size <0-1023>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
+//               <i>For Interrupt Endpoint set value to 1 .. 64.
+//               <i>For Isochronous Endpoint set value to 1 .. 1023.
+#define USBD_CUSTOM_CLASS0_IF3_EP5_FS_WMAXPACKETSIZE               1023
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in ms).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>Setting is not used for Bulk Endpoint (set value to 0).
+//               <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF3_EP5_FS_BINTERVAL                    1
+
+//           </h>
+
+//           <h>High-speed
+//             <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
+//             <i>(n is the index of device on which this interface will be used) and when
+//             <i>device operates in High-speed.
+//
+//             <o.0..10>Maximum Packet Size <0-1024>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 512.
+//               <i>For Interrupt Endpoint set value to 1 .. 1024.
+//               <i>For Isochronous Endpoint set value to 1 .. 1024.
+//             <o.11..12>Additional Transactions per Microframe
+//               <i>Specifies additional transactions per microframe to improve communication performance.
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
+//               <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
+//               <i>Value: None = 1 transaction per microframe
+//               <i>Value: 1 additional = 2 transaction per microframe
+//               <i>Value: 2 additional = 3 transaction per microframe
+//                 <0=>None
+//                 <1=>1 additional
+//                 <2=>2 additional
+#define USBD_CUSTOM_CLASS0_IF3_EP5_HS_WMAXPACKETSIZE               1024
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
+//               <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF3_EP5_HS_BINTERVAL                    1
+
+//           </h>
+//         </h>
+//       </e>
+
+//       <e>Endpoint
+//       <i>Enable Endpoint for this interface.
+#define USBD_CUSTOM_CLASS0_IF3_EP6_EN                              0
+
+//         <o.0..1>Type
+//           <i>Select Endpoint Type.
+//           <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
+//           <i>If required, for Isochronous Endpoint, Synchronization and Usage Type 
+//           <i>can be set by manually editing define value of BMATTRIBUTES.
+//           <2=>Bulk
+//           <3=>Interrupt
+//           <1=>Isochronous
+#define USBD_CUSTOM_CLASS0_IF3_EP6_BMATTRIBUTES                    0x02
+
+//         <o.0..3>Number
+//           <i>Select Endpoint Number.
+//           <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
+//                   <1=>1   <2=>2   <3=>3   <4=>4   <5=>5   <6=>6   <7=>7
+//           <8=>8   <9=>9   <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
+//         <o.7>Direction
+//           <i>Select Endpoint Direction.
+//           <i>Endpoint Descriptor: bEndpointAddress field bit 7.
+//           <0=>OUT
+//           <1=>IN
+#define USBD_CUSTOM_CLASS0_IF3_EP6_BENDPOINTADDRESS                0x04
+
+//         <h>Speed Settings
+//           <i>Settings that are different depending on device operating speed.
+//
+//           <h>Full/Low-speed
+//             <i>Parameters apply when device operates in Full/Low-speed.
+//
+//             <o.0..9>Maximum Packet Size <0-1023>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
+//               <i>For Interrupt Endpoint set value to 1 .. 64.
+//               <i>For Isochronous Endpoint set value to 1 .. 1023.
+#define USBD_CUSTOM_CLASS0_IF3_EP6_FS_WMAXPACKETSIZE               64
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in ms).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>Setting is not used for Bulk Endpoint (set value to 0).
+//               <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF3_EP6_FS_BINTERVAL                    0
+
+//           </h>
+
+//           <h>High-speed
+//             <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
+//             <i>(n is the index of device on which this interface will be used) and when
+//             <i>device operates in High-speed.
+//
+//             <o.0..10>Maximum Packet Size <0-1024>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 512.
+//               <i>For Interrupt Endpoint set value to 1 .. 1024.
+//               <i>For Isochronous Endpoint set value to 1 .. 1024.
+//             <o.11..12>Additional Transactions per Microframe
+//               <i>Specifies additional transactions per microframe to improve communication performance.
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
+//               <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
+//               <i>Value: None = 1 transaction per microframe
+//               <i>Value: 1 additional = 2 transaction per microframe
+//               <i>Value: 2 additional = 3 transaction per microframe
+//                 <0=>None
+//                 <1=>1 additional
+//                 <2=>2 additional
+#define USBD_CUSTOM_CLASS0_IF3_EP6_HS_WMAXPACKETSIZE               512
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
+//               <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF3_EP6_HS_BINTERVAL                    0
+
+//           </h>
+//         </h>
+//       </e>
+
+//       <e>Endpoint
+//       <i>Enable Endpoint for this interface.
+#define USBD_CUSTOM_CLASS0_IF3_EP7_EN                              0
+
+//         <o.0..1>Type
+//           <i>Select Endpoint Type.
+//           <i>Endpoint Descriptor: bmAttributes field bits 0 .. 1.
+//           <i>If required, for Isochronous Endpoint, Synchronization and Usage Type 
+//           <i>can be set by manually editing define value of BMATTRIBUTES.
+//           <2=>Bulk
+//           <3=>Interrupt
+//           <1=>Isochronous
+#define USBD_CUSTOM_CLASS0_IF3_EP7_BMATTRIBUTES                    0x02
+
+//         <o.0..3>Number
+//           <i>Select Endpoint Number.
+//           <i>Endpoint Descriptor: bEndpointAddress field bits 0 .. 3.
+//                   <1=>1   <2=>2   <3=>3   <4=>4   <5=>5   <6=>6   <7=>7
+//           <8=>8   <9=>9   <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
+//         <o.7>Direction
+//           <i>Select Endpoint Direction.
+//           <i>Endpoint Descriptor: bEndpointAddress field bit 7.
+//           <0=>OUT
+//           <1=>IN
+#define USBD_CUSTOM_CLASS0_IF3_EP7_BENDPOINTADDRESS                0x84
+
+//         <h>Speed Settings
+//           <i>Settings that are different depending on device operating speed.
+//
+//           <h>Full/Low-speed
+//             <i>Parameters apply when device operates in Full/Low-speed.
+//
+//             <o.0..9>Maximum Packet Size <0-1023>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 8, 16, 32 or 64.
+//               <i>For Interrupt Endpoint set value to 1 .. 64.
+//               <i>For Isochronous Endpoint set value to 1 .. 1023.
+#define USBD_CUSTOM_CLASS0_IF3_EP7_FS_WMAXPACKETSIZE               64
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in ms).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>Setting is not used for Bulk Endpoint (set value to 0).
+//               <i>For Interrupt Endpoint set value to 1 .. 255 (polling interval).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF3_EP7_FS_BINTERVAL                    0
+
+//           </h>
+
+//           <h>High-speed
+//             <i>Parameters apply when High-speed is enabled in corresponding USBD_Config_n.c
+//             <i>(n is the index of device on which this interface will be used) and when
+//             <i>device operates in High-speed.
+//
+//             <o.0..10>Maximum Packet Size <0-1024>
+//               <i>Specifies the physical packet size used for information exchange (in bytes).
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10.
+//               <i>For Bulk Endpoint set value to 512.
+//               <i>For Interrupt Endpoint set value to 1 .. 1024.
+//               <i>For Isochronous Endpoint set value to 1 .. 1024.
+//             <o.11..12>Additional Transactions per Microframe
+//               <i>Specifies additional transactions per microframe to improve communication performance.
+//               <i>Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12.
+//               <i>Relevant only if Endpoint Type is Isochronous or Interrupt.
+//               <i>Value: None = 1 transaction per microframe
+//               <i>Value: 1 additional = 2 transaction per microframe
+//               <i>Value: 2 additional = 3 transaction per microframe
+//                 <0=>None
+//                 <1=>1 additional
+//                 <2=>2 additional
+#define USBD_CUSTOM_CLASS0_IF3_EP7_HS_WMAXPACKETSIZE               512
+
+//             <o.0..7>Endpoint Polling Interval <0-255>
+//               <i>Specifies the frequency of requests initiated by USB Host (in 125 us units).
+//               <i>Endpoint Descriptor: bInterval field.
+//               <i>For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255.
+//               <i>For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+//               <i>For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)).
+#define USBD_CUSTOM_CLASS0_IF3_EP7_HS_BINTERVAL                    0
+
+//           </h>
+//         </h>
+//       </e>
+//     </h>
+
+//     <h>String Settings
+//     <i>Following settings are used to create String Descriptor(s)
+
+//       <e.0>Interface String Enable
+//       <i>Enable Interface String.
+//       <i>If disabled Interface String will not be assigned to USB Device Custom Class Interface 3.
+#define USBD_CUSTOM_CLASS0_IF3_STR_EN                              0
+
+//         <s.126>Interface String
+#define USBD_CUSTOM_CLASS0_IF3_STR                                 L"USB_CUSTOM_CLASS0_IF3"
+
+//       </e>
+//     </h>
+
+//     <h>Microsoft OS Descriptor Settings
+//     <i>Following settings are used to create Extended Compat ID OS Feature Descriptor
+
+//       <e.0>Extended Compat ID OS Feature Descriptor Function Section
+//       <i>Enable creation of function section in Extended Compat ID OS Feature Descriptor for this interface.
+#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_COMPAT_ID_EN                 0
+
+//         <s.7>compatibleID
+//         <i>compatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface.
+#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_COMPAT_ID                    "WINUSB"
+
+//         <s.7>subCompatibleID
+//         <i>subCompatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface.
+#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_SUBCOMPAT_ID                 ""
+
+//       </e>
+
+//       <h>Extended Properties OS Feature Descriptor
+//         <e.0>Custom Property Section 0
+//         <i>Enable creation of custom property 0 section in Extended Properties OS Feature Descriptor.
+#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP0_EN                     0
+
+//           <o>Data Type
+//           <i>Specifies the dwPropertyDataType field of custom property 0 section in Extended Properties OS Feature Descriptor.
+//           <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
+//             <1=>Unicode String (REG_SZ)
+//             <2=>Unicode String with environment variables (REG_EXPAND_SZ)
+//             <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
+//             <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
+//             <6=>Unicode String with symbolic link (REG_LINK)
+#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP0_DATA_TYP               1
+
+//           <s.512>Name
+#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP0_NAME                   L"DeviceInterfaceGUID"
+
+//           <h>Data
+//             <s.1024>Unicode String
+//             <i>Property Data in case Data Type is selected as Unicode String.
+#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP0_DATA_STR               L"{7D9ADCFC-E570-4B38-BF4E-8F81F68964E0}"
+
+//             <o>32-bit Integer
+//             <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
+#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP0_DATA_INT               0
+
+//           </h>
+//         </e>
+
+//         <e.0>Custom Property Section 1
+//         <i>Enable creation of custom property 1 section in Extended Properties OS Feature Descriptor.
+#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP1_EN                     0
+
+//           <o>Data Type
+//           <i>Specifies the dwPropertyDataType field of custom property 1 section in Extended Properties OS Feature Descriptor.
+//           <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
+//             <1=>Unicode String (REG_SZ)
+//             <2=>Unicode String with environment variables (REG_EXPAND_SZ)
+//             <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
+//             <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
+//             <6=>Unicode String with symbolic link (REG_LINK)
+#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP1_DATA_TYP               1
+
+//           <s.512>Name
+#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP1_NAME                   L""
+
+//           <h>Data
+//             <s.1024>Unicode String
+//             <i>Property Data in case Data Type is selected as Unicode String.
+#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP1_DATA_STR               L""
+
+//             <o>32-bit Integer
+//             <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
+#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP1_DATA_INT               0
+
+//           </h>
+//         </e>
+
+//         <e.0>Custom Property Section 2
+//         <i>Enable creation of custom property 2 section in Extended Properties OS Feature Descriptor.
+#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP2_EN                     0
+
+//           <o>Data Type
+//           <i>Specifies the dwPropertyDataType field of custom property 2 section in Extended Properties OS Feature Descriptor.
+//           <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
+//             <1=>Unicode String (REG_SZ)
+//             <2=>Unicode String with environment variables (REG_EXPAND_SZ)
+//             <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
+//             <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
+//             <6=>Unicode String with symbolic link (REG_LINK)
+#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP2_DATA_TYP               1
+
+//           <s.512>Name
+#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP2_NAME                   L""
+
+//           <h>Data
+//             <s.1024>Unicode String
+//             <i>Property Data in case Data Type is selected as Unicode String.
+#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP2_DATA_STR               L""
+
+//             <o>32-bit Integer
+//             <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
+#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP2_DATA_INT               0
+
+//           </h>
+//         </e>
+
+//         <e.0>Custom Property Section 3
+//         <i>Enable creation of custom property 3 section in Extended Properties OS Feature Descriptor.
+#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP3_EN                     0
+
+//           <o>Data Type
+//           <i>Specifies the dwPropertyDataType field of custom property 3 section in Extended Properties OS Feature Descriptor.
+//           <i>Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported.
+//             <1=>Unicode String (REG_SZ)
+//             <2=>Unicode String with environment variables (REG_EXPAND_SZ)
+//             <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN)
+//             <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN)
+//             <6=>Unicode String with symbolic link (REG_LINK)
+#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP3_DATA_TYP               1
+
+//           <s.512>Name
+#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP3_NAME                   L""
+
+//           <h>Data
+//             <s.1024>Unicode String
+//             <i>Property Data in case Data Type is selected as Unicode String.
+#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP3_DATA_STR               L""
+
+//             <o>32-bit Integer
+//             <i>Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer.
+#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP3_DATA_INT               0
+
+//           </h>
+//         </e>
+//       </h>
+//     </h>
+//   </e>
+
+
+//   <h>OS Resources Settings
+//   <i>These settings are used to optimize usage of OS resources.
+//     <o>Endpoint 1 Thread Stack Size <64-65536>
+//     <i>This setting is used if Endpoint 1 is enabled.
+#define USBD_CUSTOM_CLASS0_EP1_THREAD_STACK_SIZE                   512
+
+//        Endpoint 1 Thread Priority
+#define USBD_CUSTOM_CLASS0_EP1_THREAD_PRIORITY                     osPriorityAboveNormal
+
+//     <o>Endpoint 2 Thread Stack Size <64-65536>
+//     <i>This setting is used if Endpoint 2 is enabled.
+#define USBD_CUSTOM_CLASS0_EP2_THREAD_STACK_SIZE                   512
+
+//        Endpoint 2 Thread Priority
+#define USBD_CUSTOM_CLASS0_EP2_THREAD_PRIORITY                     osPriorityAboveNormal
+
+//     <o>Endpoint 3 Thread Stack Size <64-65536>
+//     <i>This setting is used if Endpoint 3 is enabled.
+#define USBD_CUSTOM_CLASS0_EP3_THREAD_STACK_SIZE                   512
+
+//        Endpoint 3 Thread Priority
+#define USBD_CUSTOM_CLASS0_EP3_THREAD_PRIORITY                     osPriorityAboveNormal
+
+//     <o>Endpoint 4 Thread Stack Size <64-65536>
+//     <i>This setting is used if Endpoint 4 is enabled.
+#define USBD_CUSTOM_CLASS0_EP4_THREAD_STACK_SIZE                   512
+
+//        Endpoint 4 Thread Priority
+#define USBD_CUSTOM_CLASS0_EP4_THREAD_PRIORITY                     osPriorityAboveNormal
+
+//     <o>Endpoint 5 Thread Stack Size <64-65536>
+//     <i>This setting is used if Endpoint 5 is enabled.
+#define USBD_CUSTOM_CLASS0_EP5_THREAD_STACK_SIZE                   512
+
+//        Endpoint 5 Thread Priority
+#define USBD_CUSTOM_CLASS0_EP5_THREAD_PRIORITY                     osPriorityAboveNormal
+
+//     <o>Endpoint 6 Thread Stack Size <64-65536>
+//     <i>This setting is used if Endpoint 6 is enabled.
+#define USBD_CUSTOM_CLASS0_EP6_THREAD_STACK_SIZE                   512
+
+//        Endpoint 6 Thread Priority
+#define USBD_CUSTOM_CLASS0_EP6_THREAD_PRIORITY                     osPriorityAboveNormal
+
+//     <o>Endpoint 7 Thread Stack Size <64-65536>
+//     <i>This setting is used if Endpoint 7 is enabled.
+#define USBD_CUSTOM_CLASS0_EP7_THREAD_STACK_SIZE                   512
+
+//        Endpoint 7 Thread Priority
+#define USBD_CUSTOM_CLASS0_EP7_THREAD_PRIORITY                     osPriorityAboveNormal
+
+//     <o>Endpoint 8 Thread Stack Size <64-65536>
+//     <i>This setting is used if Endpoint 8 is enabled.
+#define USBD_CUSTOM_CLASS0_EP8_THREAD_STACK_SIZE                   512
+
+//        Endpoint 8 Thread Priority
+#define USBD_CUSTOM_CLASS0_EP8_THREAD_PRIORITY                     osPriorityAboveNormal
+
+//     <o>Endpoint 9 Thread Stack Size <64-65536>
+//     <i>This setting is used if Endpoint 9 is enabled.
+#define USBD_CUSTOM_CLASS0_EP9_THREAD_STACK_SIZE                   512
+
+//        Endpoint 9 Thread Priority
+#define USBD_CUSTOM_CLASS0_EP9_THREAD_PRIORITY                     osPriorityAboveNormal
+
+//     <o>Endpoint 10 Thread Stack Size <64-65536>
+//     <i>This setting is used if Endpoint 10 is enabled.
+#define USBD_CUSTOM_CLASS0_EP10_THREAD_STACK_SIZE                  512
+
+//        Endpoint 10 Thread Priority
+#define USBD_CUSTOM_CLASS0_EP10_THREAD_PRIORITY                    osPriorityAboveNormal
+
+//     <o>Endpoint 11 Thread Stack Size <64-65536>
+//     <i>This setting is used if Endpoint 11 is enabled.
+#define USBD_CUSTOM_CLASS0_EP11_THREAD_STACK_SIZE                  512
+
+//        Endpoint 11 Thread Priority
+#define USBD_CUSTOM_CLASS0_EP11_THREAD_PRIORITY                    osPriorityAboveNormal
+
+//     <o>Endpoint 12 Thread Stack Size <64-65536>
+//     <i>This setting is used if Endpoint 12 is enabled.
+#define USBD_CUSTOM_CLASS0_EP12_THREAD_STACK_SIZE                  512
+
+//        Endpoint 12 Thread Priority
+#define USBD_CUSTOM_CLASS0_EP12_THREAD_PRIORITY                    osPriorityAboveNormal
+
+//     <o>Endpoint 13 Thread Stack Size <64-65536>
+//     <i>This setting is used if Endpoint 13 is enabled.
+#define USBD_CUSTOM_CLASS0_EP13_THREAD_STACK_SIZE                  512
+
+//        Endpoint 13 Thread Priority
+#define USBD_CUSTOM_CLASS0_EP13_THREAD_PRIORITY                    osPriorityAboveNormal
+
+//     <o>Endpoint 14 Thread Stack Size <64-65536>
+//     <i>This setting is used if Endpoint 14 is enabled.
+#define USBD_CUSTOM_CLASS0_EP14_THREAD_STACK_SIZE                  512
+
+//        Endpoint 14 Thread Priority
+#define USBD_CUSTOM_CLASS0_EP14_THREAD_PRIORITY                    osPriorityAboveNormal
+
+//     <o>Endpoint 15 Thread Stack Size <64-65536>
+//     <i>This setting is used if Endpoint 15 is enabled.
+#define USBD_CUSTOM_CLASS0_EP15_THREAD_STACK_SIZE                  512
+
+//        Endpoint 15 Thread Priority
+#define USBD_CUSTOM_CLASS0_EP15_THREAD_PRIORITY                    osPriorityAboveNormal
+
+//   </h>
+// </h>

CMSIS/DAP/Firmware/Examples/MCU-LINK/USBD1_LPC55xxx.c

@@ -0,0 +1,984 @@
+/* -----------------------------------------------------------------------------
+ * Copyright (c) 2021 ARM Ltd.
+ *
+ * This software is provided 'as-is', without any express or implied warranty.
+ * In no event will the authors be held liable for any damages arising from
+ * the use of this software. Permission is granted to anyone to use this
+ * software for any purpose, including commercial applications, and to alter
+ * it and redistribute it freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software in
+ *    a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ *
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ *
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *
+ * $Date:        28. June 2021
+ * $Revision:    V1.0
+ *
+ * Driver:       Driver_USBD1
+ * Project:      USB1 High-Speed Device Driver for NXP LPC55xxx
+ * --------------------------------------------------------------------------
+ * Use the following configuration settings in the middleware component
+ * to connect to this driver.
+ *
+ *   Configuration Setting                  Value
+ *   ---------------------                  -----
+ *   Connect to hardware via Driver_USBD# = 1
+ * --------------------------------------------------------------------------
+ * Defines used for driver configuration (at compile time):
+ *
+ *   USBD1_MAX_ENDPOINT_NUM: defines maximum number of IN/OUT Endpoint pairs 
+ *                           that driver will support with Control Endpoint 0
+ *                           not included, this value impacts driver memory
+ *                           requirements
+ *     - default value: 5
+ *     - maximum value: 5
+ *
+ *   USBD1_OUT_EP0_BUF_SZ:   defines Out Endpoint0 buffer size (in Bytes)
+ *   USBD1_IN_EP0_BUF_SZ:    defines In  Endpoint0 buffer size (in Bytes)
+ *   USBD1_OUT_EP1_BUF_SZ:   defines Out Endpoint1 buffer size (in Bytes)
+ *   USBD1_IN_EP1_BUF_SZ:    defines In  Endpoint1 buffer size (in Bytes)
+ *   USBD1_OUT_EP2_BUF_SZ:   defines Out Endpoint2 buffer size (in Bytes)
+ *   USBD1_IN_EP2_BUF_SZ:    defines In  Endpoint2 buffer size (in Bytes)
+ *   USBD1_OUT_EP3_BUF_SZ:   defines Out Endpoint3 buffer size (in Bytes)
+ *   USBD1_IN_EP3_BUF_SZ:    defines In  Endpoint3 buffer size (in Bytes)
+ *   USBD1_OUT_EP4_BUF_SZ:   defines Out Endpoint4 buffer size (in Bytes)
+ *   USBD1_IN_EP4_BUF_SZ:    defines In  Endpoint4 buffer size (in Bytes)
+ *   USBD1_OUT_EP5_BUF_SZ:   defines Out Endpoint5 buffer size (in Bytes)
+ *   USBD1_IN_EP5_BUF_SZ:    defines In  Endpoint5 buffer size (in Bytes)
+ * -------------------------------------------------------------------------- */
+
+/* History:
+ *  Version 1.0
+ *    Initial release
+ */
+
+#include <stdint.h>
+#include <string.h>
+
+#include "Driver_USBD.h"
+
+#include "RTE_Device.h"
+#include "RTE_Components.h"
+
+#include "fsl_common.h"
+#include "fsl_power.h"
+#include "fsl_clock.h"
+#include "fsl_reset.h"
+
+#include "USB_LPC55xxx.h"
+
+// Endpoint buffer must be 64Byte aligned
+#define ALIGN_64(n)                    (n == 0U ? (0U) : (64U * (((n - 1U) / 64U) + 1U)))
+
+#ifndef USBD1_MAX_ENDPOINT_NUM
+#define USBD1_MAX_ENDPOINT_NUM         (5U)
+#endif
+#if    (USBD1_MAX_ENDPOINT_NUM > 5)
+#error  Too many Endpoints, maximum IN/OUT Endpoint pairs that this driver supports is 5 !!!
+#endif
+
+// Endpoint Bufer size definitions
+#ifndef USBD1_OUT_EP0_BUF_SZ
+#define USBD1_OUT_EP0_BUF_SZ           (64U)
+#endif
+#ifndef USBD1_IN_EP0_BUF_SZ
+#define USBD1_IN_EP0_BUF_SZ            (64U)
+#endif
+#define USBD1_OUT_EP0_BUF_SZ_64        (ALIGN_64(USBD1_OUT_EP0_BUF_SZ))
+#define USBD1_IN_EP0_BUF_SZ_64         (ALIGN_64(USBD1_IN_EP0_BUF_SZ))
+
+#if (USBD1_MAX_ENDPOINT_NUM > 0)
+#ifndef USBD1_OUT_EP1_BUF_SZ
+#define USBD1_OUT_EP1_BUF_SZ           (1024U)
+#endif
+#ifndef USBD1_IN_EP1_BUF_SZ
+#define USBD1_IN_EP1_BUF_SZ            (1024U)
+#endif                     
+#else
+#define USBD1_OUT_EP1_BUF_SZ           (0U)
+#define USBD1_IN_EP1_BUF_SZ            (0U)
+#endif
+#define USBD1_OUT_EP1_BUF_SZ_64        (ALIGN_64(USBD1_OUT_EP1_BUF_SZ))
+#define USBD1_IN_EP1_BUF_SZ_64         (ALIGN_64(USBD1_IN_EP1_BUF_SZ))
+
+#if (USBD1_MAX_ENDPOINT_NUM > 1)
+#ifndef USBD1_OUT_EP2_BUF_SZ
+#define USBD1_OUT_EP2_BUF_SZ           (1024U)
+#endif
+#ifndef USBD1_IN_EP2_BUF_SZ
+#define USBD1_IN_EP2_BUF_SZ            (1024U)
+#endif
+#else
+#define USBD1_OUT_EP2_BUF_SZ           (0U)
+#define USBD1_IN_EP2_BUF_SZ            (0U)
+#endif
+#define USBD1_OUT_EP2_BUF_SZ_64        (ALIGN_64(USBD1_OUT_EP2_BUF_SZ))
+#define USBD1_IN_EP2_BUF_SZ_64         (ALIGN_64(USBD1_IN_EP2_BUF_SZ))
+
+#if (USBD1_MAX_ENDPOINT_NUM > 2)
+#ifndef USBD1_OUT_EP3_BUF_SZ
+#define USBD1_OUT_EP3_BUF_SZ           (1024U)
+#endif
+#ifndef USBD1_IN_EP3_BUF_SZ
+#define USBD1_IN_EP3_BUF_SZ            (1024U)
+#endif
+#else
+#define USBD1_OUT_EP3_BUF_SZ           (0U)
+#define USBD1_IN_EP3_BUF_SZ            (0U)
+#endif
+#define USBD1_OUT_EP3_BUF_SZ_64        (ALIGN_64(USBD1_OUT_EP3_BUF_SZ))
+#define USBD1_IN_EP3_BUF_SZ_64         (ALIGN_64(USBD1_IN_EP3_BUF_SZ))
+
+#if (USBD1_MAX_ENDPOINT_NUM > 3)
+#ifndef USBD1_OUT_EP4_BUF_SZ
+#define USBD1_OUT_EP4_BUF_SZ           (1024U)
+#endif
+#ifndef USBD1_IN_EP4_BUF_SZ
+#define USBD1_IN_EP4_BUF_SZ            (1024U)
+#endif
+#else
+#define USBD1_OUT_EP4_BUF_SZ           (0U)
+#define USBD1_IN_EP4_BUF_SZ            (0U)
+#endif
+#define USBD1_OUT_EP4_BUF_SZ_64        (ALIGN_64(USBD1_OUT_EP4_BUF_SZ))
+#define USBD1_IN_EP4_BUF_SZ_64         (ALIGN_64(USBD1_IN_EP4_BUF_SZ))
+
+#if (USBD1_MAX_ENDPOINT_NUM > 4)
+#ifndef USBD1_OUT_EP5_BUF_SZ
+#define USBD1_OUT_EP5_BUF_SZ           (1024U)
+#endif
+#ifndef USBD1_IN_EP5_BUF_SZ
+#define USBD1_IN_EP5_BUF_SZ            (1024U)
+#endif
+#else
+#define USBD1_OUT_EP5_BUF_SZ           (0U)
+#define USBD1_IN_EP5_BUF_SZ            (0U)
+#endif
+#define USBD1_OUT_EP5_BUF_SZ_64        (ALIGN_64(USBD1_OUT_EP5_BUF_SZ))
+#define USBD1_IN_EP5_BUF_SZ_64         (ALIGN_64(USBD1_IN_EP5_BUF_SZ))
+
+#define USBD1_OUT_EP0_BUF_OFFSET       (0U)
+#define USBD1_IN_EP0_BUF_OFFSET        (USBD1_OUT_EP0_BUF_SZ_64)
+#define USBD1_OUT_EP1_BUF_OFFSET       (USBD1_IN_EP0_BUF_OFFSET  + USBD1_IN_EP0_BUF_SZ_64)
+#define USBD1_IN_EP1_BUF_OFFSET        (USBD1_OUT_EP1_BUF_OFFSET + USBD1_OUT_EP1_BUF_SZ_64)
+#define USBD1_OUT_EP2_BUF_OFFSET       (USBD1_IN_EP1_BUF_OFFSET  + USBD1_IN_EP1_BUF_SZ_64)
+#define USBD1_IN_EP2_BUF_OFFSET        (USBD1_OUT_EP2_BUF_OFFSET + USBD1_OUT_EP2_BUF_SZ_64)
+#define USBD1_OUT_EP3_BUF_OFFSET       (USBD1_IN_EP2_BUF_OFFSET  + USBD1_IN_EP2_BUF_SZ_64)
+#define USBD1_IN_EP3_BUF_OFFSET        (USBD1_OUT_EP3_BUF_OFFSET + USBD1_OUT_EP3_BUF_SZ_64)
+#define USBD1_OUT_EP4_BUF_OFFSET       (USBD1_IN_EP3_BUF_OFFSET  + USBD1_IN_EP3_BUF_SZ_64)
+#define USBD1_IN_EP4_BUF_OFFSET        (USBD1_OUT_EP4_BUF_OFFSET + USBD1_OUT_EP4_BUF_SZ_64)
+#define USBD1_OUT_EP5_BUF_OFFSET       (USBD1_IN_EP4_BUF_OFFSET  + USBD1_IN_EP4_BUF_SZ_64)
+#define USBD1_IN_EP5_BUF_OFFSET        (USBD1_OUT_EP5_BUF_OFFSET + USBD1_OUT_EP5_BUF_SZ_64)
+
+#define USBD_EP_BUFFER_SZ              (USBD1_OUT_EP0_BUF_SZ_64 + USBD1_IN_EP0_BUF_SZ_64 + \
+                                        USBD1_OUT_EP1_BUF_SZ_64 + USBD1_IN_EP1_BUF_SZ_64 + \
+                                        USBD1_OUT_EP2_BUF_SZ_64 + USBD1_IN_EP2_BUF_SZ_64 + \
+                                        USBD1_OUT_EP3_BUF_SZ_64 + USBD1_IN_EP3_BUF_SZ_64 + \
+                                        USBD1_OUT_EP4_BUF_SZ_64 + USBD1_IN_EP4_BUF_SZ_64 + \
+                                        USBD1_OUT_EP5_BUF_SZ_64 + USBD1_IN_EP5_BUF_SZ_64 )
+
+#if (USBD_EP_BUFFER_SZ > 0x3C00U)
+  #error "Endpoint buffers do not fit into RAMx!"
+#endif
+
+#define EP_NUM(ep_addr)   (ep_addr & ARM_USB_ENDPOINT_NUMBER_MASK)
+#define EP_IDX(ep_addr)  ((ep_addr & 0x80U) ? ((EP_NUM(ep_addr)) * 2U + 1U)  : (ep_addr * 2U))
+#define CMD_IDX(ep_addr) ((ep_addr & 0x80U) ? ((EP_NUM(ep_addr)) * 4U + 2U)  : (ep_addr * 4U))
+
+// Resource allocation
+static uint8_t           ep_buf[USBD_EP_BUFFER_SZ]                __attribute__((section(".bss.ARM.__at_0x40100000")));
+static EP_CMD            ep_cmd[(USBD1_MAX_ENDPOINT_NUM + 1) * 4] __attribute__((section(".bss.ARM.__at_0x40103C00")));
+static EP_TRANSFER       ep_transfer[(USBD1_MAX_ENDPOINT_NUM + 1) * 2];
+
+// Global variables
+static ARM_USBD_STATE    usbd_state;
+static uint8_t           usbd_flags;
+
+static uint8_t           setup_packet[8];     // Setup packet data
+static volatile uint8_t  setup_received;      // Setup packet received
+
+static ARM_USBD_SignalDeviceEvent_t   SignalDeviceEvent;
+static ARM_USBD_SignalEndpointEvent_t SignalEndpointEvent;
+
+static const EP endpoint[] = {
+  // Endpoint 0
+  { &(ep_cmd[0]),  &(ep_buf[USBD1_OUT_EP0_BUF_OFFSET]), &(ep_transfer[0]), USBD1_OUT_EP0_BUF_OFFSET, },
+  { &(ep_cmd[2]),  &(ep_buf[USBD1_IN_EP0_BUF_OFFSET]),  &(ep_transfer[1]), USBD1_IN_EP0_BUF_OFFSET,  },
+
+#if (USBD1_MAX_ENDPOINT_NUM > 0U)
+  // Endpoint 1
+  { &(ep_cmd[4]),  &(ep_buf[USBD1_OUT_EP1_BUF_OFFSET]), &(ep_transfer[2]), USBD1_OUT_EP1_BUF_OFFSET, },
+  { &(ep_cmd[6]),  &(ep_buf[USBD1_IN_EP1_BUF_OFFSET]),  &(ep_transfer[3]), USBD1_IN_EP1_BUF_OFFSET,  },
+#endif
+
+#if (USBD1_MAX_ENDPOINT_NUM > 1U)
+  // Endpoint 2
+  { &(ep_cmd[8]),  &(ep_buf[USBD1_OUT_EP2_BUF_OFFSET]), &(ep_transfer[4]), USBD1_OUT_EP2_BUF_OFFSET, },
+  { &(ep_cmd[10]), &(ep_buf[USBD1_IN_EP2_BUF_OFFSET]),  &(ep_transfer[5]), USBD1_IN_EP2_BUF_OFFSET,  },
+#endif
+
+#if (USBD1_MAX_ENDPOINT_NUM > 2U)
+  // Endpoint 3
+  { &(ep_cmd[12]), &(ep_buf[USBD1_OUT_EP3_BUF_OFFSET]), &(ep_transfer[6]), USBD1_OUT_EP3_BUF_OFFSET, },
+  { &(ep_cmd[14]), &(ep_buf[USBD1_IN_EP3_BUF_OFFSET]),  &(ep_transfer[7]), USBD1_IN_EP3_BUF_OFFSET,  },
+#endif
+
+#if (USBD1_MAX_ENDPOINT_NUM > 3U)
+  // Endpoint 4
+  { &(ep_cmd[16]), &(ep_buf[USBD1_OUT_EP4_BUF_OFFSET]), &(ep_transfer[8]), USBD1_OUT_EP4_BUF_OFFSET, },
+  { &(ep_cmd[18]), &(ep_buf[USBD1_IN_EP4_BUF_OFFSET]),  &(ep_transfer[9]), USBD1_IN_EP4_BUF_OFFSET,  },
+#endif
+#if (USBD1_MAX_ENDPOINT_NUM > 4U)
+  // Endpoint 5
+  { &(ep_cmd[16]), &(ep_buf[USBD1_OUT_EP5_BUF_OFFSET]), &(ep_transfer[8]), USBD1_OUT_EP5_BUF_OFFSET, },
+  { &(ep_cmd[18]), &(ep_buf[USBD1_IN_EP5_BUF_OFFSET]),  &(ep_transfer[9]), USBD1_IN_EP5_BUF_OFFSET,  },
+#endif
+};
+
+
+// USBD Driver *****************************************************************
+
+#define ARM_USBD_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0)
+
+// Driver Version
+static const ARM_DRIVER_VERSION usbd_driver_version = { ARM_USBD_API_VERSION, ARM_USBD_DRV_VERSION };
+
+// Driver Capabilities
+static const ARM_USBD_CAPABILITIES usbd_driver_capabilities = {
+#if (USBD_VBUS_DETECT == 1)
+  1U,   // VBUS Detection
+  1U,   // Event VBUS On
+  1U,   // Event VBUS Off
+#else
+  0U,   // VBUS Detection
+  0U,   // Event VBUS On
+  0U    // Event VBUS Off
+#endif
+};
+
+/**
+  \fn          void USBD_Reset (void)
+  \brief       Reset USB Endpoint settings and variables.
+*/
+static void USBD_Reset (void) {
+  // Clear USB Endpoint command/status list
+  memset((void *)ep_cmd, 0, sizeof(ep_cmd));
+
+  memset((void *)&usbd_state, 0, sizeof(usbd_state));
+}
+
+// USBD Driver functions
+
+/**
+  \fn          ARM_DRIVER_VERSION USBD_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+*/
+static ARM_DRIVER_VERSION USBD_GetVersion (void) { return usbd_driver_version; }
+
+/**
+  \fn          ARM_USBD_CAPABILITIES USBD_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_USBD_CAPABILITIES
+*/
+static ARM_USBD_CAPABILITIES USBD_GetCapabilities (void) { return usbd_driver_capabilities; }
+
+/**
+  \fn          int32_t USBD_Initialize (ARM_USBD_SignalDeviceEvent_t   cb_device_event,
+                                        ARM_USBD_SignalEndpointEvent_t cb_endpoint_event)
+  \brief       Initialize USB Device Interface.
+  \param[in]   cb_device_event    Pointer to \ref ARM_USBD_SignalDeviceEvent
+  \param[in]   cb_endpoint_event  Pointer to \ref ARM_USBD_SignalEndpointEvent
+  \return      \ref execution_status
+*/
+static int32_t USBD_Initialize (ARM_USBD_SignalDeviceEvent_t   cb_device_event,
+                                ARM_USBD_SignalEndpointEvent_t cb_endpoint_event) {
+
+  if ((usbd_flags & USBD_DRIVER_FLAG_INITIALIZED) != 0U) { return ARM_DRIVER_OK; }
+
+  SignalDeviceEvent   = cb_device_event;
+  SignalEndpointEvent = cb_endpoint_event;
+
+  usbd_flags =  USBD_DRIVER_FLAG_INITIALIZED;
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t USBD_Uninitialize (void)
+  \brief       De-initialize USB Device Interface.
+  \return      \ref execution_status
+*/
+static int32_t USBD_Uninitialize (void) {
+
+  usbd_flags &= ~USBD_DRIVER_FLAG_INITIALIZED;
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t USBD_PowerControl (ARM_POWER_STATE state)
+  \brief       Control USB Device Interface Power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+*/
+static int32_t USBD_PowerControl (ARM_POWER_STATE state) {
+
+  switch (state) {
+    case ARM_POWER_OFF:
+      NVIC_DisableIRQ      (USB1_IRQn);                 // Disable interrupt
+      NVIC_ClearPendingIRQ (USB1_IRQn);                 // Clear pending interrupt
+
+      usbd_flags &= ~USBD_DRIVER_FLAG_POWERED;          // Clear powered flag
+
+      RESET_PeripheralReset(kUSB1D_RST_SHIFT_RSTn);     // Reset USB1 Device controller
+      RESET_PeripheralReset(kUSB1_RST_SHIFT_RSTn);      // Reset USB1 PHY
+      RESET_PeripheralReset(kUSB1RAM_RST_SHIFT_RSTn);   // Reset USB1 RAM controller
+
+      // Disable USB IP clock
+      SYSCON->AHBCLKCTRLSET[2] &= ~SYSCON_AHBCLKCTRL2_USB1_RAM(1);
+      SYSCON->AHBCLKCTRLSET[2] &= ~SYSCON_AHBCLKCTRL2_USB1_DEV(1);
+      SYSCON->AHBCLKCTRLSET[2] &= ~SYSCON_AHBCLKCTRL2_USB1_PHY(1);
+
+      // Clear USB Endpoint command/status list
+      memset((void *)ep_cmd, 0, sizeof(ep_cmd));
+
+      // Clear Endpoint transfer structure
+      memset((void *)ep_transfer, 0, sizeof(ep_transfer));
+      break;
+
+    case ARM_POWER_FULL:
+      if ((usbd_flags & USBD_DRIVER_FLAG_INITIALIZED) == 0U) { return ARM_DRIVER_ERROR; }
+      if ((usbd_flags & USBD_DRIVER_FLAG_POWERED)     != 0U) { return ARM_DRIVER_OK; }
+
+      // Enable USB IP clock
+      CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_UsbPhySrcExt, 16000000U);
+      CLOCK_EnableUsbhs0DeviceClock(kCLOCK_UsbSrcUnused, 0U);
+
+      // Enable device operation (through USB1 Host PORTMODE register)
+      CLOCK_EnableClock(kCLOCK_Usbh1);
+      USBHSH->PORTMODE  = USBHSH_PORTMODE_SW_PDCOM_MASK;
+      USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK;
+      CLOCK_DisableClock(kCLOCK_Usbh1);
+
+      // Setup PHY
+      USBPHY->PWD = 0U;
+      USBPHY->CTRL_SET = USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK;
+      USBPHY->CTRL_SET = USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK;
+
+      // Clear USB RAM
+      memset((void *)FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS, 0, FSL_FEATURE_USBHSD_USB_RAM);
+
+      // Reset variables and endpoint settings
+      USBD_Reset ();
+
+      // Set Endpoint list start address
+      USBHSD->EPLISTSTART = (uint32_t)ep_cmd;
+
+      // Set USB Data buffer start address
+      USBHSD->DATABUFSTART = (uint32_t)ep_buf;
+
+      // Enable device status interrupt
+      USBHSD->INTEN = USB_INTSTAT_DEV_INT_MASK;
+
+      usbd_flags |=  USBD_DRIVER_FLAG_POWERED;
+
+      // Enable USB interrupt
+      NVIC_EnableIRQ (USB1_IRQn);
+      break;
+
+    default:
+      return ARM_DRIVER_ERROR_UNSUPPORTED;
+  }
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t USBD_DeviceConnect (void)
+  \brief       Connect USB Device.
+  \return      \ref execution_status
+*/
+static int32_t USBD_DeviceConnect (void) {
+
+  if ((usbd_flags & USBD_DRIVER_FLAG_POWERED) == 0U) { return ARM_DRIVER_ERROR; }
+
+  // Attach Device
+  USBHSD->DEVCMDSTAT |= USB_DEVCMDSTAT_DCON_MASK;
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t USBD_DeviceDisconnect (void)
+  \brief       Disconnect USB Device.
+  \return      \ref execution_status
+*/
+static int32_t USBD_DeviceDisconnect (void) {
+
+  if ((usbd_flags & USBD_DRIVER_FLAG_POWERED) == 0U) { return ARM_DRIVER_ERROR; }
+
+  // Detach Device
+  USBHSD->DEVCMDSTAT &= ~USB_DEVCMDSTAT_DCON_MASK;
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          ARM_USBD_STATE USBD_DeviceGetState (void)
+  \brief       Get current USB Device State.
+  \return      Device State \ref ARM_USBD_STATE
+*/
+static ARM_USBD_STATE USBD_DeviceGetState (void) {
+  ARM_USBD_STATE dev_state = { 0U, 0U, 0U };
+
+  if ((usbd_flags & USBD_DRIVER_FLAG_POWERED) == 0U) { return dev_state; }
+
+
+  return usbd_state;
+}
+
+/**
+  \fn          int32_t USBD_DeviceRemoteWakeup (void)
+  \brief       Trigger USB Remote Wakeup.
+  \return      \ref execution_status
+*/
+static int32_t USBD_DeviceRemoteWakeup (void) {
+
+  if ((usbd_flags & USBD_DRIVER_FLAG_POWERED) == 0U) { return ARM_DRIVER_ERROR; }
+
+  // Force remote wakeup
+  USBHSD->DEVCMDSTAT &= ~USB_DEVCMDSTAT_DSUS_MASK;
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t USBD_DeviceSetAddress (uint8_t dev_addr)
+  \brief       Set USB Device Address.
+  \param[in]   dev_addr  Device Address
+  \return      \ref execution_status
+*/
+static int32_t USBD_DeviceSetAddress (uint8_t dev_addr) {
+
+  if ((usbd_flags & USBD_DRIVER_FLAG_POWERED) == 0U) { return ARM_DRIVER_ERROR; }
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t USBD_ReadSetupPacket (uint8_t *setup)
+  \brief       Read setup packet received over Control Endpoint.
+  \param[out]  setup  Pointer to buffer for setup packet
+  \return      \ref execution_status
+*/
+static int32_t USBD_ReadSetupPacket (uint8_t *setup) {
+  if ((usbd_flags & USBD_DRIVER_FLAG_POWERED) == 0U) { return ARM_DRIVER_ERROR; }
+  if (setup_received                          == 0U) { return ARM_DRIVER_ERROR; }
+
+  setup_received = 0U;
+  memcpy(setup, setup_packet, 8);
+
+  if (setup_received != 0U) {           // If new setup packet was received while this was being read
+    return ARM_DRIVER_ERROR;
+  }
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t USBD_EndpointConfigure (uint8_t  ep_addr,
+                                               uint8_t  ep_type,
+                                               uint16_t ep_max_packet_size)
+  \brief       Configure USB Endpoint.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \param[in]   ep_type  Endpoint Type (ARM_USB_ENDPOINT_xxx)
+  \param[in]   ep_max_packet_size Endpoint Maximum Packet Size
+  \return      \ref execution_status
+*/
+static int32_t USBD_EndpointConfigure (uint8_t  ep_addr,
+                                       uint8_t  ep_type,
+                                       uint16_t ep_max_packet_size) {
+  uint8_t ep_num, ep_idx;
+  EP const * ep;
+  volatile uint32_t DBG1 = 0;
+  volatile uint32_t DBG2 = 0;
+  volatile uint32_t DBG3 = 0;
+  volatile uint32_t DBG4 = 0;
+  volatile uint32_t DBG5 = ep_addr;
+  volatile uint32_t DBG6 = ep_type;
+  volatile uint32_t DBG7 = ep_max_packet_size;
+
+  ep_num = EP_NUM(ep_addr);
+  ep_idx = EP_IDX(ep_addr);
+  ep     = &endpoint[ep_idx];
+
+  if (ep_num > USBD1_MAX_ENDPOINT_NUM) {
+    DBG1++;
+    return ARM_DRIVER_ERROR;
+  }
+  if ((usbd_flags & USBD_DRIVER_FLAG_POWERED) == 0U) {
+    DBG2++;
+    return ARM_DRIVER_ERROR;
+  }
+
+  if (ep->cmd->active == 1U) {
+    // Endpoint is "owned" by hardware
+    DBG3++;
+    return ARM_DRIVER_ERROR_BUSY;
+  }
+
+  if (ep_max_packet_size > ((ep+1)->buf_offset - ep->buf_offset)) {
+    // Configured Endpoint buffer size is too small
+    DBG4++;
+    return ARM_DRIVER_ERROR;
+  }
+
+  // Clear Endpoint command/status
+  memset((void *)ep->cmd, 0, sizeof(EP_CMD) * 2U);
+
+  // Clear Endpoint transfer structure
+  memset((void *)ep->transfer, 0, sizeof(EP_TRANSFER));
+
+  ep_transfer[ep_idx].max_packet_sz = ep_max_packet_size & ARM_USB_ENDPOINT_MAX_PACKET_SIZE_MASK;
+
+  ep->cmd->buff_addr_offset = ep->buf_offset >> 6;
+
+  if (ep_num != 0U) {
+    ep->cmd->ep_disabled  = 1U;
+
+    // Reset data toggle
+    ep->cmd->ep_type_periodic = 0U;
+    ep->cmd->toggle_value     = 0U;
+    ep->cmd->toggle_reset     = 1U;
+
+    switch (ep_type) {
+      case ARM_USB_ENDPOINT_CONTROL:
+        break;
+      case ARM_USB_ENDPOINT_ISOCHRONOUS:
+        ep->cmd->toggle_value     = 0U;
+        ep->cmd->ep_type_periodic = 1U;
+        break;
+      case ARM_USB_ENDPOINT_BULK:
+        ep->cmd->toggle_value     = 0U;
+        ep->cmd->ep_type_periodic = 0U;
+        break;
+      case ARM_USB_ENDPOINT_INTERRUPT:
+        ep->cmd->toggle_value     = 1U;
+        ep->cmd->ep_type_periodic = 1U;
+        break;
+      default:                            // Unknown endpoint type
+        return ARM_DRIVER_ERROR;
+    }
+    ep->cmd->ep_disabled  = 0U;
+
+    /* Double-buffering not configured/used */
+    ep->cmd[1].buff_addr_offset = ep->buf_offset >> 6;
+    ep->cmd[1].ep_disabled = 1U;
+  }
+
+  // Clear Endpoint Interrupt
+  USBHSD->INTSTAT = USB_INT_EP(ep_idx);
+
+  // Enable endpoint interrupt
+  USBHSD->INTEN  |= USB_INT_EP(ep_idx);
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t USBD_EndpointUnconfigure (uint8_t ep_addr)
+  \brief       Unconfigure USB Endpoint.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \return      \ref execution_status
+*/
+static int32_t USBD_EndpointUnconfigure (uint8_t ep_addr) {
+  uint8_t ep_num, ep_idx;
+  EP const * ep;
+
+  ep_num = EP_NUM(ep_addr);
+  ep_idx = EP_IDX(ep_addr);
+  ep     = &endpoint[ep_idx];
+
+  if (ep_num > USBD1_MAX_ENDPOINT_NUM)               { return ARM_DRIVER_ERROR; }
+  if ((usbd_flags & USBD_DRIVER_FLAG_POWERED) == 0U) { return ARM_DRIVER_ERROR; }
+
+  if (ep->cmd->active == 1U) {
+    // Endpoint is "owned" by hardware
+    return ARM_DRIVER_ERROR_BUSY;
+  }
+
+  // Disable endpoint interrupt
+  USBHSD->INTEN &= ~USB_INT_EP(ep_idx);
+
+  if (ep->cmd->active) {
+    USBHSD->EPSKIP |= (1U << ep_idx);
+    while (USBHSD->EPSKIP & (1U << ep_idx));
+  }
+
+  // Clear Endpoint command/status
+  memset((void *)ep->cmd, 0, sizeof(EP_CMD) * 2U);
+
+  ep->cmd->ep_disabled = 1U;
+
+  // Clear Endpoint Interrupt
+  USBHSD->INTSTAT = USB_INT_EP(ep_idx);
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t USBD_EndpointStall (uint8_t ep_addr, bool stall)
+  \brief       Set/Clear Stall for USB Endpoint.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \param[in]   stall  Operation
+                - \b false Clear
+                - \b true Set
+  \return      \ref execution_status
+*/
+static int32_t USBD_EndpointStall (uint8_t ep_addr, bool stall) {
+  uint8_t ep_num;
+  EP const * ep;
+
+  ep_num = EP_NUM(ep_addr);
+  ep     = &endpoint[EP_IDX(ep_addr)];
+
+  if (ep_num > USBD1_MAX_ENDPOINT_NUM)               { return ARM_DRIVER_ERROR; }
+  if ((usbd_flags & USBD_DRIVER_FLAG_POWERED) == 0U) { return ARM_DRIVER_ERROR; }
+
+  if (ep->cmd->active == 1U) {
+    // Endpoint is "owned" by hardware
+    return ARM_DRIVER_ERROR_BUSY;
+  }
+
+  if (stall != 0U) {
+    // Set Endpoint stall
+    ep->cmd->stall = 1U;
+  } else {
+    ep->cmd->toggle_value     = 0U;
+    ep->cmd->toggle_reset     = 1U;
+
+    // Clear Stall
+    ep->cmd->stall = 0U;
+  }
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t USBD_EndpointTransfer (uint8_t ep_addr, uint8_t *data, uint32_t num)
+  \brief       Read data from or Write data to USB Endpoint.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \param[out]  data Pointer to buffer for data to read or with data to write
+  \param[in]   num  Number of data bytes to transfer
+  \return      \ref execution_status
+*/
+static int32_t USBD_EndpointTransfer (uint8_t ep_addr, uint8_t *data, uint32_t num) {
+  uint8_t      ep_num, ep_idx;
+  EP const * ep;
+
+  ep_num = EP_NUM(ep_addr);
+  ep_idx = EP_IDX(ep_addr);
+  ep     = &endpoint[ep_idx];
+
+  if (ep_num > USBD1_MAX_ENDPOINT_NUM)               { return ARM_DRIVER_ERROR; }
+  if ((usbd_flags & USBD_DRIVER_FLAG_POWERED) == 0U)  { return ARM_DRIVER_ERROR; }
+
+  if (ep->cmd->active == 1U) {
+    // Endpoint is "owned" by hardware
+    return ARM_DRIVER_ERROR_BUSY;
+  }
+
+  ep->transfer->num = num;
+  ep->transfer->buf = data;
+  ep->transfer->num_transferred_total = 0U;
+  if (num > ep->transfer->max_packet_sz) { num = ep->transfer->max_packet_sz; }
+
+  if (ep_addr & ARM_USB_ENDPOINT_DIRECTION_MASK) {
+    // Copy data into IN Endpoint buffer
+    memcpy (ep->buf, ep->transfer->buf, num);
+  }
+
+  ep->cmd->buff_addr_offset = ep->buf_offset >> 6;
+
+  ep->transfer->num_transferring = num;
+
+  // Set number of bytes to send/receive
+  ep->cmd->NBytes = num;
+
+  // Activate endpoint
+  ep->cmd->active |= 1U;
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          uint32_t USBD_EndpointTransferGetResult (uint8_t ep_addr)
+  \brief       Get result of USB Endpoint transfer.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \return      number of successfully transferred data bytes
+*/
+static uint32_t USBD_EndpointTransferGetResult (uint8_t ep_addr) {
+
+  if (EP_NUM(ep_addr) > USBD1_MAX_ENDPOINT_NUM) { return 0U; }
+
+  return (ep_transfer[EP_IDX(ep_addr)].num_transferred_total);
+}
+
+/**
+  \fn          int32_t USBD_EndpointTransferAbort (uint8_t ep_addr)
+  \brief       Abort current USB Endpoint transfer.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \return      \ref execution_status
+*/
+static int32_t USBD_EndpointTransferAbort (uint8_t ep_addr) {
+  uint8_t      ep_num, ep_idx;
+  EP const * ep;
+
+  ep_num = EP_NUM(ep_addr);
+  ep_idx = EP_IDX(ep_addr);
+  ep     = &endpoint[ep_idx];
+
+  if (ep_num > USBD1_MAX_ENDPOINT_NUM)               { return ARM_DRIVER_ERROR; }
+  if ((usbd_flags & USBD_DRIVER_FLAG_POWERED) == 0U) { return ARM_DRIVER_ERROR; }
+
+  // Disable endpoint interrupt
+  USBHSD->INTEN  &= ~USB_INT_EP(ep_idx);
+
+  if (ep->cmd->active == 1U) {
+    USBHSD->EPSKIP |= (1U << EP_IDX(ep_addr));
+    while (USBHSD->EPSKIP & (1U << EP_IDX(ep_addr)));
+    ep->cmd->active = 0U;
+  }
+
+  // Clear transfer info
+  ep->transfer->num                   = 0U;
+  ep->transfer->num_transferred_total = 0U;
+  ep->transfer->num_transferring      = 0U;
+
+  // Clear Endpoint Interrupt
+  USBHSD->INTSTAT = USB_INT_EP(ep_idx);
+
+  // Enable endpoint interrupt
+  USBHSD->INTEN  |= USB_INT_EP(ep_idx);
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          uint16_t USBD_GetFrameNumber (void)
+  \brief       Get current USB Frame Number.
+  \return      Frame Number
+*/
+static uint16_t USBD_GetFrameNumber (void) {
+
+  if ((usbd_flags & USBD_DRIVER_FLAG_POWERED) == 0U) { return 0; }
+
+  return ((USBHSD->INFO & USB_INFO_FRAME_NR_MASK) >> USB_INFO_FRAME_NR_SHIFT);
+}
+
+/**
+  \fn          void USB1_IRQHandler (void)
+  \brief       USB1 Device Interrupt Routine (IRQ).
+*/
+void USB1_IRQHandler (void) {
+  uint32_t num, ep_idx, intstat, cmdstat, dev_evt = 0U;
+  uint16_t val;
+  EP const * ep;
+
+  intstat = USBHSD->INTSTAT & USBHSD->INTEN;
+  cmdstat = USBHSD->DEVCMDSTAT;
+
+  // Clear interrupt flags
+  USBHSD->INTSTAT = intstat;
+
+  // Device Status interrupt
+  if (intstat & USB_INTSTAT_DEV_INT_MASK) {
+
+    // Reset
+    if (cmdstat & USB_DEVCMDSTAT_DRES_C_MASK) {
+      USBD_Reset ();
+      usbd_state.active = 1U;
+      usbd_state.speed  = ARM_USB_SPEED_FULL;
+      USBHSD->DEVCMDSTAT |= USB_DEVCMDSTAT_DRES_C_MASK | USB_DEVCMDSTAT_DEV_EN_MASK;
+      SignalDeviceEvent(ARM_USBD_EVENT_RESET);
+
+      if (((USBHSD->DEVCMDSTAT & USBHSD_DEVCMDSTAT_Speed_MASK) >> USBHSD_DEVCMDSTAT_Speed_SHIFT) == 2U) {
+        SignalDeviceEvent(ARM_USBD_EVENT_HIGH_SPEED);
+      }
+    }
+
+    // Suspend
+    if (cmdstat & USB_DEVCMDSTAT_DSUS_MASK) {
+      usbd_state.active = 0U;
+      USBHSD->DEVCMDSTAT |= USB_DEVCMDSTAT_DSUS_MASK;
+      SignalDeviceEvent(ARM_USBD_EVENT_SUSPEND);
+    }
+
+#if (USBD_VBUS_DETECT == 1)
+    // Disconnect
+    if (cmdstat & USB_DEVCMDSTAT_DCON_C) {
+      usbd_state.active = 0U;
+      usbd_state.vbus   = 0U;
+      LPC_USB->DEVCMDSTAT |= USB_DEVCMDSTAT_DCON_C;
+      SignalDeviceEvent(ARM_USBD_EVENT_VBUS_OFF);
+    }
+
+    // VBUS De-bounced
+    if (cmdstat & USB_DEVCMDSTAT_VBUS_DEBOUNCED) {
+      usbd_state.vbus   = 1U;
+      SignalDeviceEvent(ARM_USBD_EVENT_VBUS_ON);
+    }
+#endif
+  }
+
+  // Endpoint interrupt
+  if (intstat & USB_INT_EP_MSK) {
+    for (ep_idx = 0; ep_idx <= USBD1_MAX_ENDPOINT_NUM * 2U; ep_idx += 2U) {
+
+      if (intstat & (USB_INT_EP(ep_idx))) {
+
+        // Clear Interrupt status
+        USBHSD->INTSTAT = (1 << ep_idx);
+        // Setup Packet
+        if ((ep_idx == 0U) && ((cmdstat & USB_DEVCMDSTAT_SETUP_MASK) != 0U)) {
+          ep_cmd[0].stall = 0U;
+          ep_cmd[1].stall = 0U;
+          ep_cmd[2].stall = 0U;
+          ep_cmd[3].stall = 0U;
+
+          USBHSD->DEVCMDSTAT |= USB_DEVCMDSTAT_SETUP_MASK;
+          memcpy(setup_packet, ep_buf, 8);
+
+          // Analyze Setup packet for SetAddress
+          val = setup_packet[0] | (setup_packet[1] << 8);
+          if (val == 0x0500U) {
+            val = (setup_packet[2] | (setup_packet[3] << 8)) & USB_DEVCMDSTAT_DEV_ADDR_MASK;
+            // Set device address
+            USBHSD->DEVCMDSTAT = (USBHSD->DEVCMDSTAT & ~USB_DEVCMDSTAT_DEV_ADDR_MASK) |
+                                   USB_DEVCMDSTAT_DEV_ADDR(val) | USB_DEVCMDSTAT_DEV_EN_MASK;
+          }
+
+          setup_received = 1U;
+          if (SignalEndpointEvent != NULL) {
+            SignalEndpointEvent(0U, ARM_USBD_EVENT_SETUP);
+          }
+        } else {
+        // OUT Packet
+          ep = &endpoint[ep_idx];
+
+          num = ep->transfer->num_transferring - ep->cmd->NBytes;
+
+          // Copy EP data
+          memcpy (ep->transfer->buf, ep->buf, num);
+
+          ep->transfer->buf                   += num;
+          ep->transfer->num_transferred_total += num;
+
+          // Check if all OUT data received:
+          //  - data terminated with ZLP or short packet or
+          //  - all required data received
+          if ((ep->transfer->num_transferred_total == ep->transfer->num) || 
+              (num == 0U) || (num != ep->transfer->max_packet_sz)) {
+
+            if (SignalEndpointEvent != NULL) {
+              SignalEndpointEvent(ep_idx / 2U, ARM_USBD_EVENT_OUT);
+            }
+          } else {
+            // Remaining data to transfer
+            num = ep->transfer->num - ep->transfer->num_transferred_total;
+            if (num > ep->transfer->max_packet_sz) { num = ep->transfer->max_packet_sz; }
+
+            ep->transfer->num_transferring = num;
+            ep->cmd->NBytes                = num;
+            ep->cmd->buff_addr_offset      = ep->buf_offset >> 6;
+
+            // Activate EP to receive next packet
+            ep->cmd->active = 1U;
+          }
+        }
+      }
+    }
+
+    // IN Packet
+    for (ep_idx = 1; ep_idx <= USBD1_MAX_ENDPOINT_NUM * 2U; ep_idx += 2U) {
+
+      if (intstat & (USB_INT_EP(ep_idx))) {
+        // Clear Interrupt status
+        USBHSD->INTSTAT = (1 << ep_idx);
+
+        ep = &endpoint[ep_idx];
+
+        ep->transfer->buf                   += ep->transfer->num_transferring;
+        ep->transfer->num_transferred_total += ep->transfer->num_transferring;
+
+        if (ep->transfer->num_transferred_total == ep->transfer->num) {
+          // All data has been transfered
+          if (SignalEndpointEvent != NULL) {
+            SignalEndpointEvent(0x80 | (ep_idx / 2), ARM_USBD_EVENT_IN);
+          }
+        } else {
+          // Still data to transfer
+          num = ep->transfer->num - ep->transfer->num_transferred_total;
+          if (num > ep->transfer->max_packet_sz) {
+            // Remaining data bigger than max packet
+            num = ep->transfer->max_packet_sz;
+          }
+
+          ep->transfer->num_transferring = num;
+
+          // Copy data into IN Endpoint buffer
+          memcpy (ep->buf, ep->transfer->buf, num);
+
+          ep->cmd->buff_addr_offset = ep->buf_offset >> 6;
+
+          // Set number of bytes to send
+          ep->cmd->NBytes = num;
+
+          // Activate EP to send next packet
+          ep->cmd->active = 1U;
+        }
+      }
+    }
+  }
+}
+
+ARM_DRIVER_USBD Driver_USBD1 = {
+  USBD_GetVersion,
+  USBD_GetCapabilities,
+  USBD_Initialize,
+  USBD_Uninitialize,
+  USBD_PowerControl,
+  USBD_DeviceConnect,
+  USBD_DeviceDisconnect,
+  USBD_DeviceGetState,
+  USBD_DeviceRemoteWakeup,
+  USBD_DeviceSetAddress,
+  USBD_ReadSetupPacket,
+  USBD_EndpointConfigure,
+  USBD_EndpointUnconfigure,
+  USBD_EndpointStall,
+  USBD_EndpointTransfer,
+  USBD_EndpointTransferGetResult,
+  USBD_EndpointTransferAbort,
+  USBD_GetFrameNumber
+};

CMSIS/DAP/Firmware/Examples/MCU-LINK/USBD_User_CDC_ACM_UART_0.c

@@ -0,0 +1,381 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::USB:Device:CDC
+ * Copyright (c) 2004-2021 Arm Limited (or its affiliates). All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    USBD_User_CDC_ACM_UART_0.c
+ * Purpose: USB Device Communication Device Class (CDC)
+ *          Abstract Control Model (ACM) USB <-> UART Bridge User module
+ * Rev.:    V1.0.8
+ *----------------------------------------------------------------------------*/
+/**
+ * \addtogroup usbd_cdcFunctions
+ *
+ * USBD_User_CDC_ACM_UART_0.c implements the application specific
+ * functionality of the CDC ACM class and is used to demonstrate a USB <-> UART
+ * bridge. All data received on USB is transmitted on UART and all data
+ * received on UART is transmitted on USB.
+ *
+ * Details of operation:
+ *   UART -> USB:
+ *     Initial reception on UART is started after the USB Host sets line coding
+ *     with SetLineCoding command. Having received a full UART buffer, any
+ *     new reception is restarted on the same buffer. Any data received on
+ *     the UART is sent over USB using the CDC0_ACM_UART_to_USB_Thread thread.
+ *   USB -> UART:
+ *     While the UART transmit is not busy, data transmission on the UART is
+ *     started in the USBD_CDC0_ACM_DataReceived callback as soon as data is
+ *     received on the USB. Further data received on USB is transmitted on
+ *     UART in the UART callback routine until there is no more data available.
+ *     In this case, the next UART transmit is restarted from the
+ *     USBD_CDC0_ACM_DataReceived callback as soon as new data is received
+ *     on the USB.
+ *
+ * The following constants in this module affect the module functionality:
+ *
+ *  - UART_PORT:        specifies UART Port
+ *      default value:  0 (=UART0)
+ *  - UART_BUFFER_SIZE: specifies UART data Buffer Size
+ *      default value:  512
+ *
+ * Notes:
+ *   If the USB is slower than the UART, data can get lost. This may happen
+ *   when USB is pausing during data reception because of the USB Host being
+ *   too loaded with other tasks and not polling the Bulk IN Endpoint often
+ *   enough (up to 2 seconds of gap in polling Bulk IN Endpoint may occur).
+ *   This problem can be solved by using a large enough UART buffer to
+ *   compensate up to a few seconds of received UART data or by using UART
+ *   flow control.
+ *   If the device that receives the UART data (usually a PC) is too loaded
+ *   with other tasks it can also loose UART data. This problem can only be
+ *   solved by using UART flow control.
+ *
+ *   This file has to be adapted in case of UART flow control usage.
+ */
+ 
+ 
+//! [code_USBD_User_CDC_ACM]
+#include <stdio.h>
+#include <string.h>
+ 
+#include "rl_usb.h"
+ 
+#include "Driver_USART.h"
+ 
+#include "DAP_config.h"
+#include "DAP.h"
+ 
+// UART Configuration ----------------------------------------------------------
+ 
+#define  UART_BUFFER_SIZE      (512)       // UART Buffer Size
+ 
+//------------------------------------------------------------------------------
+ 
+#define _UART_Driver_(n)        Driver_USART##n
+#define  UART_Driver_(n)       _UART_Driver_(n)
+extern   ARM_DRIVER_USART       UART_Driver_(DAP_UART_DRIVER);
+#define  ptrUART              (&UART_Driver_(DAP_UART_DRIVER))
+ 
+// Local Variables
+static            uint8_t       uart_rx_buf[UART_BUFFER_SIZE];
+static            uint8_t       uart_tx_buf[UART_BUFFER_SIZE];
+ 
+static   volatile int32_t       uart_rx_cnt         =   0;
+static   volatile int32_t       usb_tx_cnt          =   0;
+ 
+static   void                  *cdc_acm_bridge_tid  =   0U;
+static   CDC_LINE_CODING        cdc_acm_line_coding = { 0U, 0U, 0U, 0U };
+ 
+static            uint8_t       cdc_acm_active      =   1U;
+static        osMutexId_t       cdc_acm_mutex_id    =   NULL;
+ 
+// Acquire mutex
+__STATIC_INLINE void CDC_ACM_Lock (void) {
+  if (cdc_acm_mutex_id == NULL) {
+    cdc_acm_mutex_id = osMutexNew(NULL);
+  }
+  osMutexAcquire(cdc_acm_mutex_id, osWaitForever);
+}
+ 
+// Release mutex
+__STATIC_INLINE void CDC_ACM_Unlock (void) {
+  osMutexRelease(cdc_acm_mutex_id);
+}
+ 
+// Change communication settings.
+// \param[in]   line_coding   pointer to CDC_LINE_CODING structure.
+// \return      true          set line coding request processed.
+// \return      false         set line coding request not supported or not processed.
+static bool CDC_ACM_SetLineCoding (const CDC_LINE_CODING *line_coding) {
+  uint32_t data_bits = 0U, parity = 0U, stop_bits = 0U;
+  int32_t  status;
+ 
+  (void)ptrUART->Control (ARM_USART_ABORT_SEND,    0U);
+  (void)ptrUART->Control (ARM_USART_ABORT_RECEIVE, 0U);
+  (void)ptrUART->Control (ARM_USART_CONTROL_TX,    0U);
+  (void)ptrUART->Control (ARM_USART_CONTROL_RX,    0U);
+ 
+  switch (line_coding->bCharFormat) {
+    case 0:                             // 1 Stop bit
+      stop_bits = ARM_USART_STOP_BITS_1;
+      break;
+    case 1:                             // 1.5 Stop bits
+      stop_bits = ARM_USART_STOP_BITS_1_5;
+      break;
+    case 2:                             // 2 Stop bits
+      stop_bits = ARM_USART_STOP_BITS_2;
+      break;
+    default:
+      return false;
+  }
+ 
+  switch (line_coding->bParityType) {
+    case 0:                             // None
+      parity = ARM_USART_PARITY_NONE;
+      break;
+    case 1:                             // Odd
+      parity = ARM_USART_PARITY_ODD;
+      break;
+    case 2:                             // Even
+      parity = ARM_USART_PARITY_EVEN;
+      break;
+    default:
+      return false;
+  }
+ 
+  switch (line_coding->bDataBits) {
+    case 5:
+      data_bits = ARM_USART_DATA_BITS_5;
+      break;
+    case 6:
+      data_bits = ARM_USART_DATA_BITS_6;
+      break;
+    case 7:
+      data_bits = ARM_USART_DATA_BITS_7;
+      break;
+    case 8:
+      data_bits = ARM_USART_DATA_BITS_8;
+      break;
+    default:
+      return false;
+  }
+ 
+  status = ptrUART->Control(ARM_USART_MODE_ASYNCHRONOUS  |
+                            data_bits                    |
+                            parity                       |
+                            stop_bits                    ,
+                            line_coding->dwDTERate       );
+ 
+  if (status != ARM_DRIVER_OK) {
+    return false;
+  }
+ 
+  // Store requested settings to local variable
+  memcpy(&cdc_acm_line_coding, line_coding, sizeof(cdc_acm_line_coding));
+ 
+  uart_rx_cnt = 0;
+  usb_tx_cnt  = 0;
+ 
+  (void)ptrUART->Control (ARM_USART_CONTROL_TX, 1U);
+  (void)ptrUART->Control (ARM_USART_CONTROL_RX, 1U);
+ 
+  (void)ptrUART->Receive (uart_rx_buf, UART_BUFFER_SIZE);
+ 
+  return true;
+}
+ 
+// Activate or Deactivate USBD COM PORT
+// \param[in]   cmd  0=deactivate, 1=activate
+// \return      0=Ok, 0xFF=Error
+uint8_t USB_COM_PORT_Activate (uint32_t cmd) {
+  switch (cmd) {
+    case 0U:
+      cdc_acm_active = 0U;
+      USBD_CDC0_ACM_Uninitialize();
+      break;
+    case 1U:
+      USBD_CDC0_ACM_Initialize();
+      CDC_ACM_Lock();
+      CDC_ACM_SetLineCoding(&cdc_acm_line_coding);
+      cdc_acm_active = 1U;
+      CDC_ACM_Unlock();
+      break;
+  }
+
+  return 0U;
+}
+ 
+// Called when UART has transmitted or received requested number of bytes.
+// \param[in]   event         UART event
+//               - ARM_USART_EVENT_SEND_COMPLETE:    all requested data was sent
+//               - ARM_USART_EVENT_RECEIVE_COMPLETE: all requested data was received
+static void UART_Callback (uint32_t event) {
+  int32_t cnt;
+ 
+  if (cdc_acm_active == 0U) {
+    return;
+  }
+ 
+  if (event & ARM_USART_EVENT_SEND_COMPLETE) {
+    // USB -> UART
+    cnt = USBD_CDC_ACM_ReadData(0U, uart_tx_buf, UART_BUFFER_SIZE);
+    if (cnt > 0) {
+      (void)ptrUART->Send(uart_tx_buf, (uint32_t)(cnt));
+    }
+  }
+ 
+  if (event & ARM_USART_EVENT_RECEIVE_COMPLETE) {
+    // UART data received, restart new reception
+    uart_rx_cnt += UART_BUFFER_SIZE;
+    (void)ptrUART->Receive(uart_rx_buf, UART_BUFFER_SIZE);
+  }
+}
+ 
+// Thread: Sends data received on UART to USB
+// \param[in]     arg           not used.
+__NO_RETURN static void CDC0_ACM_UART_to_USB_Thread (void *arg) {
+  int32_t cnt, cnt_to_wrap;
+ 
+  (void)(arg);
+ 
+  for (;;) {
+    // UART - > USB
+    if (ptrUART->GetStatus().rx_busy != 0U) {
+      cnt  = uart_rx_cnt;
+      cnt += (int32_t)ptrUART->GetRxCount();
+      cnt -= usb_tx_cnt;
+      if (cnt >= (UART_BUFFER_SIZE - 32)) {
+        // Dump old data in UART receive buffer if USB is not consuming fast enough
+        cnt = (UART_BUFFER_SIZE - 32);
+        usb_tx_cnt = uart_rx_cnt - (UART_BUFFER_SIZE - 32);
+      }
+      if (cnt > 0) {
+        cnt_to_wrap = (int32_t)(UART_BUFFER_SIZE - ((uint32_t)usb_tx_cnt & (UART_BUFFER_SIZE - 1)));
+        if (cnt > cnt_to_wrap) {
+          cnt = cnt_to_wrap;
+        }
+        cnt = USBD_CDC_ACM_WriteData(0U, (uart_rx_buf + ((uint32_t)usb_tx_cnt & (UART_BUFFER_SIZE - 1))), cnt);
+        if (cnt > 0) {
+          usb_tx_cnt += cnt;
+        }
+      }
+    }
+    (void)osDelay(10U);
+  }
+}
+ 
+static osRtxThread_t        cdc0_acm_uart_to_usb_thread_cb_mem               __SECTION(.bss.os.thread.cb);
+static uint64_t             cdc0_acm_uart_to_usb_thread_stack_mem[512U / 8U] __SECTION(.bss.os.thread.cdc.stack);
+static const osThreadAttr_t cdc0_acm_uart_to_usb_thread_attr = {
+  "CDC0_ACM_UART_to_USB_Thread",
+  0U,
+ &cdc0_acm_uart_to_usb_thread_cb_mem,
+  sizeof(osRtxThread_t),
+ &cdc0_acm_uart_to_usb_thread_stack_mem[0],
+  sizeof(cdc0_acm_uart_to_usb_thread_stack_mem),
+  osPriorityNormal,
+  0U,
+  0U
+};
+ 
+ 
+// CDC ACM Callbacks -----------------------------------------------------------
+ 
+// Called when new data was received from the USB Host.
+// \param[in]   len           number of bytes available to read.
+void USBD_CDC0_ACM_DataReceived (uint32_t len) {
+  int32_t cnt;
+ 
+  (void)(len);
+ 
+  if (cdc_acm_active == 0U) {
+    return;
+  }
+ 
+  if (ptrUART->GetStatus().tx_busy == 0U) {
+    // Start USB -> UART
+    cnt = USBD_CDC_ACM_ReadData(0U, uart_tx_buf, UART_BUFFER_SIZE);
+    if (cnt > 0) {
+      (void)ptrUART->Send(uart_tx_buf, (uint32_t)(cnt));
+    }
+  }
+}
+ 
+// Called during USBD_Initialize to initialize the USB CDC class instance (ACM).
+void USBD_CDC0_ACM_Initialize (void) {
+  (void)ptrUART->Initialize   (UART_Callback);
+  (void)ptrUART->PowerControl (ARM_POWER_FULL);
+ 
+  cdc_acm_bridge_tid = osThreadNew (CDC0_ACM_UART_to_USB_Thread, NULL, &cdc0_acm_uart_to_usb_thread_attr);
+}
+ 
+ 
+// Called during USBD_Uninitialize to de-initialize the USB CDC class instance (ACM).
+void USBD_CDC0_ACM_Uninitialize (void) {
+  if (osThreadTerminate (cdc_acm_bridge_tid) == osOK) {
+    cdc_acm_bridge_tid = NULL;
+  }
+  (void)ptrUART->Control      (ARM_USART_ABORT_RECEIVE, 0U);
+  (void)ptrUART->PowerControl (ARM_POWER_OFF);
+  (void)ptrUART->Uninitialize ();
+}
+ 
+ 
+// Called upon USB Bus Reset Event.
+void USBD_CDC0_ACM_Reset (void) {
+  if (cdc_acm_active == 0U ) {
+    return;
+  }
+  (void)ptrUART->Control      (ARM_USART_ABORT_SEND,    0U);
+  (void)ptrUART->Control      (ARM_USART_ABORT_RECEIVE, 0U);
+}
+ 
+ 
+// Called upon USB Host request to change communication settings.
+// \param[in]   line_coding   pointer to CDC_LINE_CODING structure.
+// \return      true          set line coding request processed.
+// \return      false         set line coding request not supported or not processed.
+bool USBD_CDC0_ACM_SetLineCoding (const CDC_LINE_CODING *line_coding) {
+  bool ret = false;
+ 
+  CDC_ACM_Lock();
+  if (cdc_acm_active == 0U) {
+    // Store requested settings to local variable
+    memcpy(&cdc_acm_line_coding, line_coding, sizeof(cdc_acm_line_coding));
+    ret = true;
+  } else {
+    ret = CDC_ACM_SetLineCoding(line_coding);
+  }
+  CDC_ACM_Unlock();
+ 
+  return ret;
+}
+ 
+ 
+// Called upon USB Host request to retrieve communication settings.
+// \param[out]  line_coding   pointer to CDC_LINE_CODING structure.
+// \return      true          get line coding request processed.
+// \return      false         get line coding request not supported or not processed.
+bool USBD_CDC0_ACM_GetLineCoding (CDC_LINE_CODING *line_coding) {
+ 
+  // Load settings from ones stored on USBD_CDC0_ACM_SetLineCoding callback
+  *line_coding = cdc_acm_line_coding;
+ 
+  return true;
+}
+ 
+ 
+// Called upon USB Host request to set control line states.
+// \param [in]  state         control line settings bitmap.
+//                - bit 0: DTR state
+//                - bit 1: RTS state
+// \return      true          set control line state request processed.
+// \return      false         set control line state request not supported or not processed.
+bool USBD_CDC0_ACM_SetControlLineState (uint16_t state) {
+  // Add code for set control line state
+ 
+  (void)(state);
+ 
+  return true;
+}
+ 
+//! [code_USBD_User_CDC_ACM]

CMSIS/DAP/Firmware/Examples/MCU-LINK/USBD_User_CustomClass_0.c

@@ -0,0 +1,358 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::USB:Device
+ * Copyright (c) 2004-2016 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    USBD_User_CustomClass_0.c
+ * Purpose: USB Device Custom Class User module
+ * Rev.:    V6.7.3
+ *----------------------------------------------------------------------------*/
+/*
+ * USBD_User_CustomClass_0.c is a code template for the Custom Class 0 
+ * class request handling. It allows user to handle all Custom Class class 
+ * requests.
+ *
+ * Uncomment "Example code" lines to see example that receives data on 
+ * Endpoint 1 OUT and echoes it back on Endpoint 1 IN.
+ * To try the example you also have to enable Bulk Endpoint 1 IN/OUT in Custom 
+ * Class configuration in USBD_Config_CustomClass_0.h file.
+ */
+
+/**
+ * \addtogroup usbd_custom_classFunctions
+ *
+ */
+
+
+//! [code_USBD_User_CustomClass]
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <string.h>
+#include "cmsis_os2.h"
+#define   osObjectsExternal
+#include "osObjects.h"
+#include "rl_usb.h"
+#include "Driver_USBD.h"
+#include "DAP_config.h"
+#include "DAP.h"
+
+static volatile uint16_t USB_RequestIndexI;     // Request  Index In
+static volatile uint16_t USB_RequestIndexO;     // Request  Index Out
+static volatile uint16_t USB_RequestCountI;     // Request  Count In
+static volatile uint16_t USB_RequestCountO;     // Request  Count Out
+static volatile uint8_t  USB_RequestIdle;       // Request  Idle  Flag
+
+static volatile uint16_t USB_ResponseIndexI;    // Response Index In
+static volatile uint16_t USB_ResponseIndexO;    // Response Index Out
+static volatile uint16_t USB_ResponseCountI;    // Response Count In
+static volatile uint16_t USB_ResponseCountO;    // Response Count Out
+static volatile uint8_t  USB_ResponseIdle;      // Response Idle  Flag
+
+static uint8_t  USB_Request [DAP_PACKET_COUNT][DAP_PACKET_SIZE] __attribute__((section(".bss.USB_IO")));  // Request  Buffer
+static uint8_t  USB_Response[DAP_PACKET_COUNT][DAP_PACKET_SIZE] __attribute__((section(".bss.USB_IO")));  // Response Buffer
+static uint16_t USB_RespSize[DAP_PACKET_COUNT];                                                           // Response Size
+
+// \brief Callback function called during USBD_Initialize to initialize the USB Custom class instance
+void USBD_CustomClass0_Initialize (void) {
+  // Handle Custom Class Initialization
+
+  // Initialize variables
+  USB_RequestIndexI  = 0U;
+  USB_RequestIndexO  = 0U;
+  USB_RequestCountI  = 0U;
+  USB_RequestCountO  = 0U;
+  USB_RequestIdle    = 1U;
+  USB_ResponseIndexI = 0U;
+  USB_ResponseIndexO = 0U;
+  USB_ResponseCountI = 0U;
+  USB_ResponseCountO = 0U;
+  USB_ResponseIdle   = 1U;
+}
+
+// \brief Callback function called during USBD_Uninitialize to de-initialize the USB Custom class instance
+void USBD_CustomClass0_Uninitialize (void) {
+  // Handle Custom Class De-initialization
+}
+
+// \brief Callback function called upon USB Bus Reset signaling
+void USBD_CustomClass0_Reset (void) {
+  // Handle USB Bus Reset Event
+}
+
+// \brief Callback function called when Endpoint Start was requested (by activating interface or configuration)
+// \param[in]     ep_addr       endpoint address.
+void USBD_CustomClass0_EndpointStart (uint8_t ep_addr) {
+  // Start communication on Endpoint
+  if (ep_addr == USB_ENDPOINT_OUT(1U)) {
+    USB_RequestIdle = 0U;
+    USBD_EndpointRead(0U, USB_ENDPOINT_OUT(1U), USB_Request[0], DAP_PACKET_SIZE);
+  }
+}
+
+// \brief Callback function called when Endpoint Stop was requested (by de-activating interface or activating configuration 0)
+// \param[in]     ep_addr       endpoint address.
+void USBD_CustomClass0_EndpointStop (uint8_t ep_addr) {
+  // Handle Endpoint communication stopped
+  (void)ep_addr;
+}
+
+// \brief Callback function called when Custom Class 0 received SETUP PACKET on Control Endpoint 0
+//        (this callback will be called only for Class Requests (USB_REQUEST_CLASS) if it was not processed 
+//         previously by Device callback)
+// \param[in]     setup_packet            pointer to received setup packet.
+// \param[out]    buf                     pointer to data buffer used for data stage requested by setup packet.
+// \param[out]    len                     pointer to number of data bytes in data stage requested by setup packet.
+// \return        usbdRequestStatus       enumerator value indicating the function execution status
+// \return        usbdRequestNotProcessed:request was not processed; processing will be done by USB library
+// \return        usbdRequestOK:          request was processed successfully (send Zero-Length Packet if no data stage)
+// \return        usbdRequestStall:       request was processed but is not supported (stall Endpoint 0)
+usbdRequestStatus USBD_CustomClass0_Endpoint0_SetupPacketReceived (const USB_SETUP_PACKET *setup_packet, uint8_t **buf, uint32_t *len) {
+  (void)setup_packet;
+  (void)buf;
+  (void)len;
+
+  switch (setup_packet->bmRequestType.Recipient) {
+    case USB_REQUEST_TO_DEVICE:
+      break;
+    case USB_REQUEST_TO_INTERFACE:
+      break;
+    case USB_REQUEST_TO_ENDPOINT:
+      break;
+    default:
+      break;
+  }
+
+  return usbdRequestNotProcessed;
+}
+
+// \brief Callback function called when SETUP PACKET was processed by USB library
+//        (this callback will be called only for Class Requests (USB_REQUEST_CLASS) if it was not processed 
+//         previously by Device callback nor by Custom Class callback)
+// \param[in]     setup_packet            pointer to processed setup packet.
+void USBD_CustomClass0_Endpoint0_SetupPacketProcessed (const USB_SETUP_PACKET *setup_packet) {
+  (void)setup_packet;
+
+  switch (setup_packet->bmRequestType.Recipient) {
+    case USB_REQUEST_TO_DEVICE:
+      break;
+    case USB_REQUEST_TO_INTERFACE:
+      break;
+    case USB_REQUEST_TO_ENDPOINT:
+      break;
+    default:
+      break;
+  }
+}
+
+// \brief Callback function called when Custom Class 0 received OUT DATA on Control Endpoint 0
+//        (this callback will be called only for Class Requests (USB_REQUEST_CLASS) if it was not processed 
+//         previously by Device callback)
+// \param[in]     len                     number of received data bytes.
+// \return        usbdRequestStatus       enumerator value indicating the function execution status
+// \return        usbdRequestNotProcessed:request was not processed; processing will be done by USB library
+// \return        usbdRequestOK:          request was processed successfully (send Zero-Length Packet)
+// \return        usbdRequestStall:       request was processed but is not supported (stall Endpoint 0)
+// \return        usbdRequestNAK:         request was processed but the device is busy (return NAK)
+usbdRequestStatus USBD_CustomClass0_Endpoint0_OutDataReceived (uint32_t len) {
+  (void)len;
+  return usbdRequestNotProcessed;
+}
+
+// \brief Callback function called when Custom Class 0 sent IN DATA on Control Endpoint 0
+//        (this callback will be called only for Class Requests (USB_REQUEST_CLASS) if it was not processed 
+//         previously by Device callback)
+// \param[in]     len                     number of sent data bytes.
+// \return        usbdRequestStatus       enumerator value indicating the function execution status
+// \return        usbdRequestNotProcessed:request was not processed; processing will be done by USB library
+// \return        usbdRequestOK:          request was processed successfully (return ACK)
+// \return        usbdRequestStall:       request was processed but is not supported (stall Endpoint 0)
+// \return        usbdRequestNAK:         request was processed but the device is busy (return NAK)
+usbdRequestStatus USBD_CustomClass0_Endpoint0_InDataSent (uint32_t len) {
+  (void)len;
+  return usbdRequestNotProcessed;
+}
+
+// \brief Callback function called when DATA was sent or received on Endpoint n
+// \param[in]     event                   event on Endpoint:
+//                                          - ARM_USBD_EVENT_OUT = data OUT received
+//                                          - ARM_USBD_EVENT_IN  = data IN  sent
+void USBD_CustomClass0_Endpoint1_Event  (uint32_t event) {
+  // Handle Endpoint 1 events
+  uint32_t n;
+
+  if (event & ARM_USBD_EVENT_OUT) {
+    n = USBD_EndpointReadGetResult(0U, USB_ENDPOINT_OUT(1U));
+    if (n != 0U) {
+      if (USB_Request[USB_RequestIndexI][0] == ID_DAP_TransferAbort) {
+        DAP_TransferAbort = 1U;
+      } else {
+        USB_RequestIndexI++;
+        if (USB_RequestIndexI == DAP_PACKET_COUNT) {
+          USB_RequestIndexI = 0U;
+        }
+        USB_RequestCountI++;
+        osThreadFlagsSet(DAP_ThreadId, 0x01);
+      }
+    }
+    // Start reception of next request packet
+    if ((uint16_t)(USB_RequestCountI - USB_RequestCountO) != DAP_PACKET_COUNT) {
+      USBD_EndpointRead(0U, USB_ENDPOINT_OUT(1U), USB_Request[USB_RequestIndexI], DAP_PACKET_SIZE);
+    } else {
+      USB_RequestIdle = 1U;
+    }
+  }
+  if (event & ARM_USBD_EVENT_IN) {
+    if (USB_ResponseCountI != USB_ResponseCountO) {
+      // Load data from response buffer to be sent back
+      USBD_EndpointWrite(0U, USB_ENDPOINT_IN(1U), USB_Response[USB_ResponseIndexO], USB_RespSize[USB_ResponseIndexO]);
+      USB_ResponseIndexO++;
+      if (USB_ResponseIndexO == DAP_PACKET_COUNT) {
+        USB_ResponseIndexO = 0U;
+      }
+      USB_ResponseCountO++;
+    } else {
+      USB_ResponseIdle = 1U;
+    }
+  }
+}
+void USBD_CustomClass0_Endpoint2_Event  (uint32_t event) {
+  // Handle Endpoint 2 events
+  if (event & ARM_USBD_EVENT_IN) {
+    SWO_TransferComplete();
+  }
+}
+void USBD_CustomClass0_Endpoint3_Event  (uint32_t event) {
+  // Handle Endpoint 3 events
+  (void)event;
+}
+void USBD_CustomClass0_Endpoint4_Event  (uint32_t event) {
+  // Handle Endpoint 4 events
+  (void)event;
+}
+void USBD_CustomClass0_Endpoint5_Event  (uint32_t event) {
+  // Handle Endpoint 5 events
+  (void)event;
+}
+void USBD_CustomClass0_Endpoint6_Event  (uint32_t event) {
+  // Handle Endpoint 6 events
+  (void)event;
+}
+void USBD_CustomClass0_Endpoint7_Event  (uint32_t event) {
+  // Handle Endpoint 7 events
+  (void)event;
+}
+void USBD_CustomClass0_Endpoint8_Event  (uint32_t event) {
+  // Handle Endpoint 8 events
+  (void)event;
+}
+void USBD_CustomClass0_Endpoint9_Event  (uint32_t event) {
+  // Handle Endpoint 9 events
+  (void)event;
+}
+void USBD_CustomClass0_Endpoint10_Event (uint32_t event) {
+  // Handle Endpoint 10 events
+  (void)event;
+}
+void USBD_CustomClass0_Endpoint11_Event (uint32_t event) {
+  // Handle Endpoint 11 events
+  (void)event;
+}
+void USBD_CustomClass0_Endpoint12_Event (uint32_t event) {
+  // Handle Endpoint 12 events
+  (void)event;
+}
+void USBD_CustomClass0_Endpoint13_Event (uint32_t event) {
+  // Handle Endpoint 13 events
+  (void)event;
+}
+void USBD_CustomClass0_Endpoint14_Event (uint32_t event) {
+  // Handle Endpoint 14 events
+  (void)event;
+}
+void USBD_CustomClass0_Endpoint15_Event (uint32_t event) {
+  // Handle Endpoint 15 events
+  (void)event;
+}
+
+// DAP Thread.
+__NO_RETURN void DAP_Thread (void *argument) {
+  uint32_t flags;
+  uint32_t n;
+  (void)   argument;
+
+  for (;;) {
+    osThreadFlagsWait(0x81U, osFlagsWaitAny, osWaitForever);
+
+    // Process pending requests
+    while (USB_RequestCountI != USB_RequestCountO) {
+
+      // Handle Queue Commands
+      n = USB_RequestIndexO;
+      while (USB_Request[n][0] == ID_DAP_QueueCommands) {
+        USB_Request[n][0] = ID_DAP_ExecuteCommands;
+        n++;
+        if (n == DAP_PACKET_COUNT) {
+          n = 0U;
+        }
+        if (n == USB_RequestIndexI) {
+          flags = osThreadFlagsWait(0x81U, osFlagsWaitAny, osWaitForever);
+          if (flags & 0x80U) {
+            break;
+          }
+        }
+      }
+
+      // Execute DAP Command (process request and prepare response)
+      USB_RespSize[USB_ResponseIndexI] =
+        (uint16_t)DAP_ExecuteCommand(USB_Request[USB_RequestIndexO], USB_Response[USB_ResponseIndexI]);
+
+      // Update Request Index and Count
+      USB_RequestIndexO++;
+      if (USB_RequestIndexO == DAP_PACKET_COUNT) {
+        USB_RequestIndexO = 0U;
+      }
+      USB_RequestCountO++;
+
+      if (USB_RequestIdle) {
+        if ((uint16_t)(USB_RequestCountI - USB_RequestCountO) != DAP_PACKET_COUNT) {
+          USB_RequestIdle = 0U;
+          USBD_EndpointRead(0U, USB_ENDPOINT_OUT(1U), USB_Request[USB_RequestIndexI], DAP_PACKET_SIZE);
+        }
+      }
+
+      // Update Response Index and Count
+      USB_ResponseIndexI++;
+      if (USB_ResponseIndexI == DAP_PACKET_COUNT) {
+        USB_ResponseIndexI = 0U;
+      }
+      USB_ResponseCountI++;
+
+      if (USB_ResponseIdle) {
+        if (USB_ResponseCountI != USB_ResponseCountO) {
+          // Load data from response buffer to be sent back
+          n = USB_ResponseIndexO++;
+          if (USB_ResponseIndexO == DAP_PACKET_COUNT) {
+            USB_ResponseIndexO = 0U;
+          }
+          USB_ResponseCountO++;
+          USB_ResponseIdle = 0U;
+          USBD_EndpointWrite(0U, USB_ENDPOINT_IN(1U), USB_Response[n], USB_RespSize[n]);
+        }
+      }
+    }
+  }
+}
+
+// SWO Data Queue Transfer
+//   buf:    pointer to buffer with data
+//   num:    number of bytes to transfer
+void SWO_QueueTransfer (uint8_t *buf, uint32_t num) {
+  USBD_EndpointWrite(0U, USB_ENDPOINT_IN(2U), buf, num);
+}
+
+// SWO Data Abort Transfer
+void SWO_AbortTransfer (void) {
+  USBD_EndpointAbort(0U, USB_ENDPOINT_IN(2U));
+}
+
+//! [code_USBD_User_CustomClass]

CMSIS/DAP/Firmware/Examples/MCU-LINK/USB_LPC55xxx.h

@@ -0,0 +1,70 @@
+/* -----------------------------------------------------------------------------
+ * Copyright (c) 2021 ARM Ltd.
+ *
+ * This software is provided 'as-is', without any express or implied warranty.
+ * In no event will the authors be held liable for any damages arising from
+ * the use of this software. Permission is granted to anyone to use this
+ * software for any purpose, including commercial applications, and to alter
+ * it and redistribute it freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software in
+ *    a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ *
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ *
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ *
+ * $Date:        28. June 2021
+ * $Revision:    V1.0
+ *
+ * Project:      USB Driver Definitions for NXP LPC55xxx
+ * -------------------------------------------------------------------------- */
+
+#ifndef __USB_LPC55XXX_H
+#define __USB_LPC55XXX_H
+
+#include <stdint.h>
+
+// USB Device Endpoint Interrupt definitions
+#define USB_INT_EP_MSK                    (0x0FFFU)
+#define USB_INT_EP(ep_idx)                ((1U << (ep_idx)) & USB_INT_EP_MSK)
+
+// USB Driver State Flags
+// Device State Flags
+#define USBD_DRIVER_FLAG_INITIALIZED      (1U      )
+#define USBD_DRIVER_FLAG_POWERED          (1U << 1 )
+
+// Transfer information structure
+typedef struct {
+  uint32_t max_packet_sz;
+  uint32_t num;
+  uint32_t num_transferred_total;
+  uint32_t num_transferring;
+  uint8_t *buf;
+} EP_TRANSFER;
+
+// Endpoint command/status
+typedef struct {
+  uint32_t buff_addr_offset     : 11;
+  uint32_t NBytes               : 15;
+  uint32_t ep_type_periodic     : 1;
+  uint32_t toggle_value         : 1;
+  uint32_t toggle_reset         : 1;
+  uint32_t stall                : 1;
+  uint32_t ep_disabled          : 1;
+  uint32_t active               : 1;
+} EP_CMD;
+
+// Endpoint structure
+typedef struct __EP {
+  EP_CMD      * const cmd;
+  uint8_t     * const buf;
+  EP_TRANSFER * const transfer;
+  uint16_t            buf_offset;
+} EP;
+
+#endif /* __USB_LPC55XXX_H */

CMSIS/DAP/Firmware/Examples/MCU-LINK/board/clock_config.c

@@ -0,0 +1,150 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to set up clock using clock driver functions:
+ *
+ * 1. Setup clock sources.
+ *
+ * 2. Set up wait states of the flash.
+ *
+ * 3. Set up all dividers.
+ *
+ * 4. Set up all selectors to provide selected clocks.
+ */
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v7.0
+processor: LPC55S69
+package_id: LPC55S69JBD64
+mcu_data: ksdk2_0
+processor_version: 9.0.3
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+#include "fsl_power.h"
+#include "fsl_clock.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: FXCOM0_clock.outFreq, value: 48 MHz}
+- {id: FXCOM3_clock.outFreq, value: 48 MHz}
+- {id: System_clock.outFreq, value: 150 MHz, locked: true, accuracy: '0.001'}
+- {id: USB1_PHY_clock.outFreq, value: 16 MHz}
+settings:
+- {id: PLL0_Mode, value: Normal}
+- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
+- {id: ENABLE_CLKIN_ENA, value: Enabled}
+- {id: ENABLE_PLL_USB_OUT, value: Enabled}
+- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
+- {id: SYSCON.FCCLKSEL0.sel, value: SYSCON.FROHFDIV}
+- {id: SYSCON.FCCLKSEL3.sel, value: SYSCON.FROHFDIV}
+- {id: SYSCON.FRGCTRL3_DIV.scale, value: '256', locked: true}
+- {id: SYSCON.FROHFDIV.scale, value: '2', locked: true}
+- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
+- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
+- {id: SYSCON.PLL0M_MULT.scale, value: '150', locked: true}
+- {id: SYSCON.PLL0N_DIV.scale, value: '8', locked: true}
+- {id: SYSCON.PLL0_PDEC.scale, value: '2'}
+sources:
+- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
+- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    /*!< Set up the clock sources */
+    /*!< Configure FRO192M */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
+    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
+
+    CLOCK_SetupFROClocking(96000000U);                   /* Enable FRO HF(96MHz) output */
+
+    /*!< Configure XTAL32M */
+    POWER_DisablePD(kPDRUNCFG_PD_XTAL32M);                        /* Ensure XTAL32M is powered */
+    POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M);                       /* Ensure XTAL32M is powered */
+    CLOCK_SetupExtClocking(16000000U);                            /* Enable clk_in clock */
+    SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;       /* Enable clk_in from XTAL32M clock  */
+    ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;    /* Enable clk_in to system  */
+    ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK;       /* Enable clk_in to HS USB  */
+
+    POWER_SetVoltageForFreq(150000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(150000000U);          /*!< Set FLASH wait states for core */
+
+    /*!< Set up PLL */
+    CLOCK_AttachClk(kEXT_CLK_to_PLL0);                    /*!< Switch PLL0CLKSEL to EXT_CLK */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0);                  /* Ensure PLL is on  */
+    POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
+    const pll_setup_t pll0Setup = {
+        .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(31U),
+        .pllndec = SYSCON_PLL0NDEC_NDIV(8U),
+        .pllpdec = SYSCON_PLL0PDEC_PDIV(1U),
+        .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(150U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
+        .pllRate = 150000000U,
+        .flags =  PLL_SETUPFLAG_WAITLOCK
+    };
+    CLOCK_SetPLL0Freq(&pll0Setup);                       /*!< Configure PLL0 to the desired values */
+
+    /*!< Set up dividers */
+    #if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 3, 4)
+      CLOCK_SetClkDiv(kCLOCK_DivFlexFrg0, 0U, false);         /*!< Set DIV to value 0xFF and MULT to value 0U in related FLEXFRGCTRL register */
+    #else
+      CLOCK_SetClkDiv(kCLOCK_DivFlexFrg0, 256U, false);         /*!< Set DIV to value 0xFF and MULT to value 0U in related FLEXFRGCTRL register */
+    #endif
+    #if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 3, 4)
+      CLOCK_SetClkDiv(kCLOCK_DivFlexFrg3, 0U, false);         /*!< Set DIV to value 0xFF and MULT to value 0U in related FLEXFRGCTRL register */
+    #else
+      CLOCK_SetClkDiv(kCLOCK_DivFlexFrg3, 256U, false);         /*!< Set DIV to value 0xFF and MULT to value 0U in related FLEXFRGCTRL register */
+    #endif
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
+    CLOCK_SetClkDiv(kCLOCK_DivFrohfClk, 0U, true);               /*!< Reset FROHFDIV divider counter and halt it */
+    CLOCK_SetClkDiv(kCLOCK_DivFrohfClk, 2U, false);         /*!< Set FROHFDIV divider to value 2 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kPLL0_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL0 */
+    CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM0);                 /*!< Switch FLEXCOMM0 to FRO_HF_DIV */
+    CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM3);                 /*!< Switch FLEXCOMM3 to FRO_HF_DIV */
+
+    /*!< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+#endif
+}
+

CMSIS/DAP/Firmware/Examples/MCU-LINK/board/clock_config.h

@@ -0,0 +1,62 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         16000000U  /*!< Board xtal frequency in Hz */
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32K frequency in Hz */
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK             150000000U  /*!< Core clock frequency: 150000000Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
+

CMSIS/DAP/Firmware/Examples/MCU-LINK/board/peripherals.c

@@ -0,0 +1,77 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Peripherals v9.0
+processor: LPC55S69
+package_id: LPC55S69JBD64
+mcu_data: ksdk2_0
+processor_version: 9.0.3
+functionalGroups:
+- name: BOARD_InitPeripherals
+  UUID: 85f4cd0c-3b58-4e23-a413-239f6952f139
+  called_from_default_init: true
+  selectedCore: cm33_core0
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+component:
+- type: 'system'
+- type_id: 'system_54b53072540eeeb8f8e9343e71f28176'
+- global_system_definitions:
+  - user_definitions: ''
+  - user_includes: ''
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/***********************************************************************************************************************
+ * Included files
+ **********************************************************************************************************************/
+#include "peripherals.h"
+
+/***********************************************************************************************************************
+ * BOARD_InitPeripherals functional group
+ **********************************************************************************************************************/
+/***********************************************************************************************************************
+ * NVIC initialization code
+ **********************************************************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+instance:
+- name: 'NVIC'
+- type: 'nvic'
+- mode: 'general'
+- custom_name_enabled: 'false'
+- type_id: 'nvic_57b5eef3774cc60acaede6f5b8bddc67'
+- functional_group: 'BOARD_InitPeripherals'
+- peripheral: 'NVIC'
+- config_sets:
+  - nvic:
+    - interrupt_table: []
+    - interrupts: []
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/* Empty initialization function (commented out)
+static void NVIC_init(void) {
+} */
+
+/***********************************************************************************************************************
+ * Initialization functions
+ **********************************************************************************************************************/
+void BOARD_InitPeripherals(void)
+{
+  /* Initialize components */
+}
+
+/***********************************************************************************************************************
+ * BOARD_InitBootPeripherals function
+ **********************************************************************************************************************/
+void BOARD_InitBootPeripherals(void)
+{
+  BOARD_InitPeripherals();
+}

CMSIS/DAP/Firmware/Examples/MCU-LINK/board/peripherals.h

@@ -0,0 +1,33 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PERIPHERALS_H_
+#define _PERIPHERALS_H_
+
+/***********************************************************************************************************************
+ * Included files
+ **********************************************************************************************************************/
+#include "fsl_common.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/***********************************************************************************************************************
+ * Initialization functions
+ **********************************************************************************************************************/
+
+void BOARD_InitPeripherals(void);
+
+/***********************************************************************************************************************
+ * BOARD_InitBootPeripherals function
+ **********************************************************************************************************************/
+void BOARD_InitBootPeripherals(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* _PERIPHERALS_H_ */

CMSIS/DAP/Firmware/Examples/MCU-LINK/board/pin_mux.c

@@ -0,0 +1,337 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v9.0
+processor: LPC55S69
+package_id: LPC55S69JBD64
+mcu_data: ksdk2_0
+processor_version: 9.0.3
+pin_labels:
+- {pin_num: '36', pin_signal: PIO0_0/FC3_SCK/CTIMER0_MAT0/SCT_GPI0/SD1_CARD_INT_N/SECURE_GPIO0_0/ACMP0_A, label: _DBGIF_TCK_SWCLK, identifier: DBGIF_TCK_SWCLK}
+- {pin_num: '2', pin_signal: PIO0_1/FC3_CTS_SDA_SSEL0/CT_INP0/SCT_GPI1/SD1_CLK/CMP0_OUT/SECURE_GPIO0_1, label: _DBGIF_TDI, identifier: DBGIF_TDI}
+- {pin_num: '52', pin_signal: PIO0_2/FC3_TXD_SCL_MISO_WS/CT_INP1/SCT0_OUT0/SCT_GPI2/SECURE_GPIO0_2, label: _DBGIF_TMS_SWDIO, identifier: DBGIF_TMS_SWDIO}
+- {pin_num: '44', pin_signal: PIO0_28/FC0_SCK/SD1_CMD/CT_INP11/SCT0_OUT7/USB0_OVERCURRENTN/PLU_OUT1/SECURE_GPIO0_28, label: _DBGIF_TMS_SWDIO_TXEN, identifier: DBGIF_TMS_SWDIO_TXEN}
+- {pin_num: '58', pin_signal: PIO0_19/FC4_RTS_SCL_SSEL1/UTICK_CAP0/CTIMER0_MAT2/SCT0_OUT2/FC7_TXD_SCL_MISO_WS/PLU_IN4/SECURE_GPIO0_19, label: _DBGIF_RESET, identifier: DBG_IF_RESET;DBGIF_RESET}
+- {pin_num: '46', pin_signal: PIO0_13/FC1_CTS_SDA_SSEL0/UTICK_CAP0/CT_INP0/SCT_GPI0/FC1_RXD_SDA_MOSI_DATA/PLU_IN0/SECURE_GPIO0_13, label: _DBGIF_RESET_TXEN, identifier: DBG_IF_RESET_TXEN;DBGIF_RESET_TXEN}
+- {pin_num: '53', pin_signal: PIO0_3/FC3_RXD_SDA_MOSI_DATA/CTIMER0_MAT1/SCT0_OUT1/SCT_GPI3/SECURE_GPIO0_3, label: _DBGIF_TDO_SWO, identifier: DBG_IF_TDO_SWO;DBGIF_TDO_SWO}
+- {pin_num: '45', pin_signal: PIO0_24/FC0_RXD_SDA_MOSI_DATA/SD0_D0/CT_INP8/SCT_GPI0/SECURE_GPIO0_24, label: _FC0_TARGET_RXD, identifier: FC0_TARGET_RXD}
+- {pin_num: '51', pin_signal: PIO0_25/FC0_TXD_SCL_MISO_WS/SD0_D1/CT_INP9/SCT_GPI1/SECURE_GPIO0_25, label: _FC0_TARGET_TXD, identifier: FC0_TARGET_TXD}
+- {pin_num: '56', pin_signal: PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5, label: _LED1, identifier: LED1}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+#include "fsl_common.h"
+#include "fsl_gpio.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description   : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+    MCU_LINK_InitPins();
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+MCU_LINK_InitPins:
+- options: {callFromInitBoot: 'true', prefix: '', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: '36', peripheral: GPIO, signal: 'PIO0, 0', pin_signal: PIO0_0/FC3_SCK/CTIMER0_MAT0/SCT_GPI0/SD1_CARD_INT_N/SECURE_GPIO0_0/ACMP0_A, direction: INPUT,
+    slew_rate: fast}
+  - {pin_num: '2', peripheral: GPIO, signal: 'PIO0, 1', pin_signal: PIO0_1/FC3_CTS_SDA_SSEL0/CT_INP0/SCT_GPI1/SD1_CLK/CMP0_OUT/SECURE_GPIO0_1, direction: INPUT, slew_rate: fast}
+  - {pin_num: '52', peripheral: GPIO, signal: 'PIO0, 2', pin_signal: PIO0_2/FC3_TXD_SCL_MISO_WS/CT_INP1/SCT0_OUT0/SCT_GPI2/SECURE_GPIO0_2, direction: INPUT, mode: inactive,
+    slew_rate: fast}
+  - {pin_num: '44', peripheral: GPIO, signal: 'PIO0, 28', pin_signal: PIO0_28/FC0_SCK/SD1_CMD/CT_INP11/SCT0_OUT7/USB0_OVERCURRENTN/PLU_OUT1/SECURE_GPIO0_28, direction: OUTPUT,
+    gpio_init_state: 'false', slew_rate: fast}
+  - {pin_num: '58', peripheral: GPIO, signal: 'PIO0, 19', pin_signal: PIO0_19/FC4_RTS_SCL_SSEL1/UTICK_CAP0/CTIMER0_MAT2/SCT0_OUT2/FC7_TXD_SCL_MISO_WS/PLU_IN4/SECURE_GPIO0_19,
+    identifier: DBGIF_RESET, direction: INPUT, slew_rate: fast}
+  - {pin_num: '46', peripheral: GPIO, signal: 'PIO0, 13', pin_signal: PIO0_13/FC1_CTS_SDA_SSEL0/UTICK_CAP0/CT_INP0/SCT_GPI0/FC1_RXD_SDA_MOSI_DATA/PLU_IN0/SECURE_GPIO0_13,
+    identifier: DBGIF_RESET_TXEN, direction: OUTPUT, gpio_init_state: 'false'}
+  - {pin_num: '53', peripheral: FLEXCOMM3, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_3/FC3_RXD_SDA_MOSI_DATA/CTIMER0_MAT1/SCT0_OUT1/SCT_GPI3/SECURE_GPIO0_3, identifier: DBGIF_TDO_SWO,
+    slew_rate: fast}
+  - {pin_num: '45', peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_24/FC0_RXD_SDA_MOSI_DATA/SD0_D0/CT_INP8/SCT_GPI0/SECURE_GPIO0_24, slew_rate: fast}
+  - {pin_num: '51', peripheral: FLEXCOMM0, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_25/FC0_TXD_SCL_MISO_WS/SD0_D1/CT_INP9/SCT_GPI1/SECURE_GPIO0_25, slew_rate: fast}
+  - {pin_num: '23', peripheral: USBHSH, signal: USB_DP, pin_signal: USB1_DP}
+  - {pin_num: '24', peripheral: USBHSH, signal: USB_DM, pin_signal: USB1_DM}
+  - {pin_num: '25', peripheral: USBHSH, signal: USB_VBUS, pin_signal: USB1_VBUS}
+  - {pin_num: '22', peripheral: USBHSH, signal: USB_VSS, pin_signal: USB1_VSS22}
+  - {pin_num: '26', peripheral: USBHSH, signal: USB_VSS, pin_signal: USB1_VSS26}
+  - {pin_num: '41', peripheral: USBHSH, signal: USB_PORTPWRN, pin_signal: PIO1_2/CTIMER0_MAT3/SCT_GPI6/HS_SPI_SCK/USB1_PORTPWRN/PLU_OUT5}
+  - {pin_num: '56', peripheral: GPIO, signal: 'PIO0, 5', pin_signal: PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5, direction: OUTPUT,
+    gpio_init_state: 'true', mode: pullUp}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : MCU_LINK_InitPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+/* Function assigned for the Cortex-M33 (Core #0) */
+void MCU_LINK_InitPins(void)
+{
+    /* Enables the clock for the I/O controller.: Enable Clock. */
+    CLOCK_EnableClock(kCLOCK_Iocon);
+
+    /* Enables the clock for the GPIO0 module */
+    CLOCK_EnableClock(kCLOCK_Gpio0);
+
+    gpio_pin_config_t DBGIF_TCK_SWCLK_config = {
+        .pinDirection = kGPIO_DigitalInput,
+        .outputLogic = 0U
+    };
+    /* Initialize GPIO functionality on pin PIO0_0 (pin 36)  */
+    GPIO_PinInit(DBGIF_TCK_SWCLK_GPIO, DBGIF_TCK_SWCLK_PORT, DBGIF_TCK_SWCLK_PIN, &DBGIF_TCK_SWCLK_config);
+
+    gpio_pin_config_t DBGIF_TDI_config = {
+        .pinDirection = kGPIO_DigitalInput,
+        .outputLogic = 0U
+    };
+    /* Initialize GPIO functionality on pin PIO0_1 (pin 2)  */
+    GPIO_PinInit(DBGIF_TDI_GPIO, DBGIF_TDI_PORT, DBGIF_TDI_PIN, &DBGIF_TDI_config);
+
+    gpio_pin_config_t DBGIF_TMS_SWDIO_config = {
+        .pinDirection = kGPIO_DigitalInput,
+        .outputLogic = 0U
+    };
+    /* Initialize GPIO functionality on pin PIO0_2 (pin 52)  */
+    GPIO_PinInit(DBGIF_TMS_SWDIO_GPIO, DBGIF_TMS_SWDIO_PORT, DBGIF_TMS_SWDIO_PIN, &DBGIF_TMS_SWDIO_config);
+
+    gpio_pin_config_t LED1_config = {
+        .pinDirection = kGPIO_DigitalOutput,
+        .outputLogic = 1U
+    };
+    /* Initialize GPIO functionality on pin PIO0_5 (pin 56)  */
+    GPIO_PinInit(LED1_GPIO, LED1_PORT, LED1_PIN, &LED1_config);
+
+    gpio_pin_config_t DBGIF_RESET_TXEN_config = {
+        .pinDirection = kGPIO_DigitalOutput,
+        .outputLogic = 0U
+    };
+    /* Initialize GPIO functionality on pin PIO0_13 (pin 46)  */
+    GPIO_PinInit(DBGIF_RESET_TXEN_GPIO, DBGIF_RESET_TXEN_PORT, DBGIF_RESET_TXEN_PIN, &DBGIF_RESET_TXEN_config);
+
+    gpio_pin_config_t DBGIF_RESET_config = {
+        .pinDirection = kGPIO_DigitalInput,
+        .outputLogic = 0U
+    };
+    /* Initialize GPIO functionality on pin PIO0_19 (pin 58)  */
+    GPIO_PinInit(DBGIF_RESET_GPIO, DBGIF_RESET_PORT, DBGIF_RESET_PIN, &DBGIF_RESET_config);
+
+    gpio_pin_config_t DBGIF_TMS_SWDIO_TXEN_config = {
+        .pinDirection = kGPIO_DigitalOutput,
+        .outputLogic = 0U
+    };
+    /* Initialize GPIO functionality on pin PIO0_28 (pin 44)  */
+    GPIO_PinInit(DBGIF_TMS_SWDIO_TXEN_GPIO, DBGIF_TMS_SWDIO_TXEN_PORT, DBGIF_TMS_SWDIO_TXEN_PIN, &DBGIF_TMS_SWDIO_TXEN_config);
+
+    IOCON->PIO[0][0] = ((IOCON->PIO[0][0] &
+                         /* Mask bits to zero which are setting */
+                         (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_SLEW_MASK | IOCON_PIO_DIGIMODE_MASK)))
+
+                        /* Selects pin function.
+                         * : PORT00 (pin 36) is configured as PIO0_0. */
+                        | IOCON_PIO_FUNC(PIO0_0_FUNC_ALT0)
+
+                        /* Driver slew rate.
+                         * : Fast-mode, output slew rate is faster.
+                         * Refer to the appropriate specific device data sheet for details. */
+                        | IOCON_PIO_SLEW(PIO0_0_SLEW_FAST)
+
+                        /* Select Digital mode.
+                         * : Enable Digital mode.
+                         * Digital input is enabled. */
+                        | IOCON_PIO_DIGIMODE(PIO0_0_DIGIMODE_DIGITAL));
+
+    IOCON->PIO[0][1] = ((IOCON->PIO[0][1] &
+                         /* Mask bits to zero which are setting */
+                         (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_SLEW_MASK | IOCON_PIO_DIGIMODE_MASK)))
+
+                        /* Selects pin function.
+                         * : PORT01 (pin 2) is configured as PIO0_1. */
+                        | IOCON_PIO_FUNC(PIO0_1_FUNC_ALT0)
+
+                        /* Driver slew rate.
+                         * : Fast-mode, output slew rate is faster.
+                         * Refer to the appropriate specific device data sheet for details. */
+                        | IOCON_PIO_SLEW(PIO0_1_SLEW_FAST)
+
+                        /* Select Digital mode.
+                         * : Enable Digital mode.
+                         * Digital input is enabled. */
+                        | IOCON_PIO_DIGIMODE(PIO0_1_DIGIMODE_DIGITAL));
+
+    IOCON->PIO[0][13] = ((IOCON->PIO[0][13] &
+                          /* Mask bits to zero which are setting */
+                          (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK)))
+
+                         /* Selects pin function.
+                          * : PORT013 (pin 46) is configured as PIO0_13. */
+                         | IOCON_PIO_FUNC(PIO0_13_FUNC_ALT0)
+
+                         /* Select Digital mode.
+                          * : Enable Digital mode.
+                          * Digital input is enabled. */
+                         | IOCON_PIO_DIGIMODE(PIO0_13_DIGIMODE_DIGITAL));
+
+    IOCON->PIO[0][19] = ((IOCON->PIO[0][19] &
+                          /* Mask bits to zero which are setting */
+                          (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_SLEW_MASK | IOCON_PIO_DIGIMODE_MASK)))
+
+                         /* Selects pin function.
+                          * : PORT019 (pin 58) is configured as PIO0_19. */
+                         | IOCON_PIO_FUNC(PIO0_19_FUNC_ALT0)
+
+                         /* Driver slew rate.
+                          * : Fast-mode, output slew rate is faster.
+                          * Refer to the appropriate specific device data sheet for details. */
+                         | IOCON_PIO_SLEW(PIO0_19_SLEW_FAST)
+
+                         /* Select Digital mode.
+                          * : Enable Digital mode.
+                          * Digital input is enabled. */
+                         | IOCON_PIO_DIGIMODE(PIO0_19_DIGIMODE_DIGITAL));
+
+    IOCON->PIO[0][2] = ((IOCON->PIO[0][2] &
+                         /* Mask bits to zero which are setting */
+                         (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_SLEW_MASK | IOCON_PIO_DIGIMODE_MASK)))
+
+                        /* Selects pin function.
+                         * : PORT02 (pin 52) is configured as PIO0_2. */
+                        | IOCON_PIO_FUNC(PIO0_2_FUNC_ALT0)
+
+                        /* Selects function mode (on-chip pull-up/pull-down resistor control).
+                         * : Inactive.
+                         * Inactive (no pull-down/pull-up resistor enabled). */
+                        | IOCON_PIO_MODE(PIO0_2_MODE_INACTIVE)
+
+                        /* Driver slew rate.
+                         * : Fast-mode, output slew rate is faster.
+                         * Refer to the appropriate specific device data sheet for details. */
+                        | IOCON_PIO_SLEW(PIO0_2_SLEW_FAST)
+
+                        /* Select Digital mode.
+                         * : Enable Digital mode.
+                         * Digital input is enabled. */
+                        | IOCON_PIO_DIGIMODE(PIO0_2_DIGIMODE_DIGITAL));
+
+    IOCON->PIO[0][24] = ((IOCON->PIO[0][24] &
+                          /* Mask bits to zero which are setting */
+                          (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_SLEW_MASK | IOCON_PIO_DIGIMODE_MASK)))
+
+                         /* Selects pin function.
+                          * : PORT024 (pin 45) is configured as FC0_RXD_SDA_MOSI_DATA. */
+                         | IOCON_PIO_FUNC(PIO0_24_FUNC_ALT1)
+
+                         /* Driver slew rate.
+                          * : Fast-mode, output slew rate is faster.
+                          * Refer to the appropriate specific device data sheet for details. */
+                         | IOCON_PIO_SLEW(PIO0_24_SLEW_FAST)
+
+                         /* Select Digital mode.
+                          * : Enable Digital mode.
+                          * Digital input is enabled. */
+                         | IOCON_PIO_DIGIMODE(PIO0_24_DIGIMODE_DIGITAL));
+
+    IOCON->PIO[0][25] = ((IOCON->PIO[0][25] &
+                          /* Mask bits to zero which are setting */
+                          (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_SLEW_MASK | IOCON_PIO_DIGIMODE_MASK)))
+
+                         /* Selects pin function.
+                          * : PORT025 (pin 51) is configured as FC0_TXD_SCL_MISO_WS. */
+                         | IOCON_PIO_FUNC(PIO0_25_FUNC_ALT1)
+
+                         /* Driver slew rate.
+                          * : Fast-mode, output slew rate is faster.
+                          * Refer to the appropriate specific device data sheet for details. */
+                         | IOCON_PIO_SLEW(PIO0_25_SLEW_FAST)
+
+                         /* Select Digital mode.
+                          * : Enable Digital mode.
+                          * Digital input is enabled. */
+                         | IOCON_PIO_DIGIMODE(PIO0_25_DIGIMODE_DIGITAL));
+
+    IOCON->PIO[0][28] = ((IOCON->PIO[0][28] &
+                          /* Mask bits to zero which are setting */
+                          (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_SLEW_MASK | IOCON_PIO_DIGIMODE_MASK)))
+
+                         /* Selects pin function.
+                          * : PORT028 (pin 44) is configured as PIO0_28. */
+                         | IOCON_PIO_FUNC(PIO0_28_FUNC_ALT0)
+
+                         /* Driver slew rate.
+                          * : Fast-mode, output slew rate is faster.
+                          * Refer to the appropriate specific device data sheet for details. */
+                         | IOCON_PIO_SLEW(PIO0_28_SLEW_FAST)
+
+                         /* Select Digital mode.
+                          * : Enable Digital mode.
+                          * Digital input is enabled. */
+                         | IOCON_PIO_DIGIMODE(PIO0_28_DIGIMODE_DIGITAL));
+
+    IOCON->PIO[0][3] = ((IOCON->PIO[0][3] &
+                         /* Mask bits to zero which are setting */
+                         (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_SLEW_MASK | IOCON_PIO_DIGIMODE_MASK)))
+
+                        /* Selects pin function.
+                         * : PORT03 (pin 53) is configured as FC3_RXD_SDA_MOSI_DATA. */
+                        | IOCON_PIO_FUNC(PIO0_3_FUNC_ALT1)
+
+                        /* Driver slew rate.
+                         * : Fast-mode, output slew rate is faster.
+                         * Refer to the appropriate specific device data sheet for details. */
+                        | IOCON_PIO_SLEW(PIO0_3_SLEW_FAST)
+
+                        /* Select Digital mode.
+                         * : Enable Digital mode.
+                         * Digital input is enabled. */
+                        | IOCON_PIO_DIGIMODE(PIO0_3_DIGIMODE_DIGITAL));
+
+    IOCON->PIO[0][5] = ((IOCON->PIO[0][5] &
+                         /* Mask bits to zero which are setting */
+                         (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_DIGIMODE_MASK)))
+
+                        /* Selects pin function.
+                         * : PORT05 (pin 56) is configured as PIO0_5. */
+                        | IOCON_PIO_FUNC(PIO0_5_FUNC_ALT0)
+
+                        /* Selects function mode (on-chip pull-up/pull-down resistor control).
+                         * : Pull-up.
+                         * Pull-up resistor enabled. */
+                        | IOCON_PIO_MODE(PIO0_5_MODE_PULL_UP)
+
+                        /* Select Digital mode.
+                         * : Enable Digital mode.
+                         * Digital input is enabled. */
+                        | IOCON_PIO_DIGIMODE(PIO0_5_DIGIMODE_DIGITAL));
+
+    IOCON->PIO[1][2] = ((IOCON->PIO[1][2] &
+                         /* Mask bits to zero which are setting */
+                         (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK)))
+
+                        /* Selects pin function.
+                         * : PORT12 (pin 41) is configured as USB1_PORTPWRN. */
+                        | IOCON_PIO_FUNC(PIO1_2_FUNC_ALT7)
+
+                        /* Select Digital mode.
+                         * : Enable Digital mode.
+                         * Digital input is enabled. */
+                        | IOCON_PIO_DIGIMODE(PIO1_2_DIGIMODE_DIGITAL));
+}
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/

CMSIS/DAP/Firmware/Examples/MCU-LINK/board/pin_mux.h

@@ -0,0 +1,276 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
+#define PIO0_0_DIGIMODE_DIGITAL 0x01u
+/*!
+ * @brief Selects pin function.: Alternative connection 0. */
+#define PIO0_0_FUNC_ALT0 0x00u
+/*!
+ * @brief
+ * Driver slew rate.
+ * : Fast-mode, output slew rate is faster.
+ * Refer to the appropriate specific device data sheet for details.
+ */
+#define PIO0_0_SLEW_FAST 0x01u
+/*!
+ * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
+#define PIO0_13_DIGIMODE_DIGITAL 0x01u
+/*!
+ * @brief Selects pin function.: Alternative connection 0. */
+#define PIO0_13_FUNC_ALT0 0x00u
+/*!
+ * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
+#define PIO0_19_DIGIMODE_DIGITAL 0x01u
+/*!
+ * @brief Selects pin function.: Alternative connection 0. */
+#define PIO0_19_FUNC_ALT0 0x00u
+/*!
+ * @brief
+ * Driver slew rate.
+ * : Fast-mode, output slew rate is faster.
+ * Refer to the appropriate specific device data sheet for details.
+ */
+#define PIO0_19_SLEW_FAST 0x01u
+/*!
+ * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
+#define PIO0_1_DIGIMODE_DIGITAL 0x01u
+/*!
+ * @brief Selects pin function.: Alternative connection 0. */
+#define PIO0_1_FUNC_ALT0 0x00u
+/*!
+ * @brief
+ * Driver slew rate.
+ * : Fast-mode, output slew rate is faster.
+ * Refer to the appropriate specific device data sheet for details.
+ */
+#define PIO0_1_SLEW_FAST 0x01u
+/*!
+ * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
+#define PIO0_24_DIGIMODE_DIGITAL 0x01u
+/*!
+ * @brief Selects pin function.: Alternative connection 1. */
+#define PIO0_24_FUNC_ALT1 0x01u
+/*!
+ * @brief
+ * Driver slew rate.
+ * : Fast-mode, output slew rate is faster.
+ * Refer to the appropriate specific device data sheet for details.
+ */
+#define PIO0_24_SLEW_FAST 0x01u
+/*!
+ * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
+#define PIO0_25_DIGIMODE_DIGITAL 0x01u
+/*!
+ * @brief Selects pin function.: Alternative connection 1. */
+#define PIO0_25_FUNC_ALT1 0x01u
+/*!
+ * @brief
+ * Driver slew rate.
+ * : Fast-mode, output slew rate is faster.
+ * Refer to the appropriate specific device data sheet for details.
+ */
+#define PIO0_25_SLEW_FAST 0x01u
+/*!
+ * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
+#define PIO0_28_DIGIMODE_DIGITAL 0x01u
+/*!
+ * @brief Selects pin function.: Alternative connection 0. */
+#define PIO0_28_FUNC_ALT0 0x00u
+/*!
+ * @brief
+ * Driver slew rate.
+ * : Fast-mode, output slew rate is faster.
+ * Refer to the appropriate specific device data sheet for details.
+ */
+#define PIO0_28_SLEW_FAST 0x01u
+/*!
+ * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
+#define PIO0_2_DIGIMODE_DIGITAL 0x01u
+/*!
+ * @brief Selects pin function.: Alternative connection 0. */
+#define PIO0_2_FUNC_ALT0 0x00u
+/*!
+ * @brief
+ * Selects function mode (on-chip pull-up/pull-down resistor control).
+ * : Inactive.
+ * Inactive (no pull-down/pull-up resistor enabled).
+ */
+#define PIO0_2_MODE_INACTIVE 0x00u
+/*!
+ * @brief
+ * Driver slew rate.
+ * : Fast-mode, output slew rate is faster.
+ * Refer to the appropriate specific device data sheet for details.
+ */
+#define PIO0_2_SLEW_FAST 0x01u
+/*!
+ * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
+#define PIO0_3_DIGIMODE_DIGITAL 0x01u
+/*!
+ * @brief Selects pin function.: Alternative connection 1. */
+#define PIO0_3_FUNC_ALT1 0x01u
+/*!
+ * @brief
+ * Driver slew rate.
+ * : Fast-mode, output slew rate is faster.
+ * Refer to the appropriate specific device data sheet for details.
+ */
+#define PIO0_3_SLEW_FAST 0x01u
+/*!
+ * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
+#define PIO0_5_DIGIMODE_DIGITAL 0x01u
+/*!
+ * @brief Selects pin function.: Alternative connection 0. */
+#define PIO0_5_FUNC_ALT0 0x00u
+/*!
+ * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */
+#define PIO0_5_MODE_PULL_UP 0x02u
+/*!
+ * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
+#define PIO1_2_DIGIMODE_DIGITAL 0x01u
+/*!
+ * @brief Selects pin function.: Alternative connection 7. */
+#define PIO1_2_FUNC_ALT7 0x07u
+
+/*! @name PIO0_0 (number 36), _DBGIF_TCK_SWCLK
+  @{ */
+
+/* Symbols to be used with GPIO driver */
+#define DBGIF_TCK_SWCLK_GPIO GPIO                /*!<@brief GPIO peripheral base pointer */
+#define DBGIF_TCK_SWCLK_GPIO_PIN_MASK (1U << 0U) /*!<@brief GPIO pin mask */
+#define DBGIF_TCK_SWCLK_PORT 0U                  /*!<@brief PORT peripheral base pointer */
+#define DBGIF_TCK_SWCLK_PIN 0U                   /*!<@brief PORT pin number */
+#define DBGIF_TCK_SWCLK_PIN_MASK (1U << 0U)      /*!<@brief PORT pin mask */
+                                                 /* @} */
+
+/*! @name PIO0_1 (number 2), _DBGIF_TDI
+  @{ */
+
+/* Symbols to be used with GPIO driver */
+#define DBGIF_TDI_GPIO GPIO                /*!<@brief GPIO peripheral base pointer */
+#define DBGIF_TDI_GPIO_PIN_MASK (1U << 1U) /*!<@brief GPIO pin mask */
+#define DBGIF_TDI_PORT 0U                  /*!<@brief PORT peripheral base pointer */
+#define DBGIF_TDI_PIN 1U                   /*!<@brief PORT pin number */
+#define DBGIF_TDI_PIN_MASK (1U << 1U)      /*!<@brief PORT pin mask */
+                                           /* @} */
+
+/*! @name PIO0_2 (number 52), _DBGIF_TMS_SWDIO
+  @{ */
+
+/* Symbols to be used with GPIO driver */
+#define DBGIF_TMS_SWDIO_GPIO GPIO                /*!<@brief GPIO peripheral base pointer */
+#define DBGIF_TMS_SWDIO_GPIO_PIN_MASK (1U << 2U) /*!<@brief GPIO pin mask */
+#define DBGIF_TMS_SWDIO_PORT 0U                  /*!<@brief PORT peripheral base pointer */
+#define DBGIF_TMS_SWDIO_PIN 2U                   /*!<@brief PORT pin number */
+#define DBGIF_TMS_SWDIO_PIN_MASK (1U << 2U)      /*!<@brief PORT pin mask */
+                                                 /* @} */
+
+/*! @name PIO0_28 (number 44), _DBGIF_TMS_SWDIO_TXEN
+  @{ */
+
+/* Symbols to be used with GPIO driver */
+#define DBGIF_TMS_SWDIO_TXEN_GPIO GPIO                 /*!<@brief GPIO peripheral base pointer */
+#define DBGIF_TMS_SWDIO_TXEN_GPIO_PIN_MASK (1U << 28U) /*!<@brief GPIO pin mask */
+#define DBGIF_TMS_SWDIO_TXEN_PORT 0U                   /*!<@brief PORT peripheral base pointer */
+#define DBGIF_TMS_SWDIO_TXEN_PIN 28U                   /*!<@brief PORT pin number */
+#define DBGIF_TMS_SWDIO_TXEN_PIN_MASK (1U << 28U)      /*!<@brief PORT pin mask */
+                                                       /* @} */
+
+/*! @name PIO0_19 (number 58), _DBGIF_RESET
+  @{ */
+
+/* Symbols to be used with GPIO driver */
+#define DBGIF_RESET_GPIO GPIO                 /*!<@brief GPIO peripheral base pointer */
+#define DBGIF_RESET_GPIO_PIN_MASK (1U << 19U) /*!<@brief GPIO pin mask */
+#define DBGIF_RESET_PORT 0U                   /*!<@brief PORT peripheral base pointer */
+#define DBGIF_RESET_PIN 19U                   /*!<@brief PORT pin number */
+#define DBGIF_RESET_PIN_MASK (1U << 19U)      /*!<@brief PORT pin mask */
+                                              /* @} */
+
+/*! @name PIO0_13 (number 46), _DBGIF_RESET_TXEN
+  @{ */
+
+/* Symbols to be used with GPIO driver */
+#define DBGIF_RESET_TXEN_GPIO GPIO                 /*!<@brief GPIO peripheral base pointer */
+#define DBGIF_RESET_TXEN_GPIO_PIN_MASK (1U << 13U) /*!<@brief GPIO pin mask */
+#define DBGIF_RESET_TXEN_PORT 0U                   /*!<@brief PORT peripheral base pointer */
+#define DBGIF_RESET_TXEN_PIN 13U                   /*!<@brief PORT pin number */
+#define DBGIF_RESET_TXEN_PIN_MASK (1U << 13U)      /*!<@brief PORT pin mask */
+                                                   /* @} */
+
+/*! @name PIO0_3 (number 53), _DBGIF_TDO_SWO
+  @{ */
+#define DBGIF_TDO_SWO_PORT 0U                  /*!<@brief PORT peripheral base pointer */
+#define DBGIF_TDO_SWO_PIN 3U                   /*!<@brief PORT pin number */
+#define DBGIF_TDO_SWO_PIN_MASK (1U << 3U)      /*!<@brief PORT pin mask */
+                                               /* @} */
+
+/*! @name PIO0_24 (number 45), _FC0_TARGET_RXD
+  @{ */
+#define FC0_TARGET_RXD_PORT 0U                   /*!<@brief PORT peripheral base pointer */
+#define FC0_TARGET_RXD_PIN 24U                   /*!<@brief PORT pin number */
+#define FC0_TARGET_RXD_PIN_MASK (1U << 24U)      /*!<@brief PORT pin mask */
+                                                 /* @} */
+
+/*! @name PIO0_25 (number 51), _FC0_TARGET_TXD
+  @{ */
+#define FC0_TARGET_TXD_PORT 0U                   /*!<@brief PORT peripheral base pointer */
+#define FC0_TARGET_TXD_PIN 25U                   /*!<@brief PORT pin number */
+#define FC0_TARGET_TXD_PIN_MASK (1U << 25U)      /*!<@brief PORT pin mask */
+                                                 /* @} */
+
+/*! @name PIO0_5 (number 56), _LED1
+  @{ */
+
+/* Symbols to be used with GPIO driver */
+#define LED1_GPIO GPIO                /*!<@brief GPIO peripheral base pointer */
+#define LED1_GPIO_PIN_MASK (1U << 5U) /*!<@brief GPIO pin mask */
+#define LED1_PORT 0U                  /*!<@brief PORT peripheral base pointer */
+#define LED1_PIN 5U                   /*!<@brief PORT pin number */
+#define LED1_PIN_MASK (1U << 5U)      /*!<@brief PORT pin mask */
+                                      /* @} */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void MCU_LINK_InitPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/

CMSIS/DAP/Firmware/Examples/MCU-LINK/fsl_usart.c

@@ -0,0 +1,1284 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+ 
+ /*
+ * Modified by Arm
+ */
+#define FSL_USART_MODIFIED_BY_ARM 1U
+
+#include "fsl_usart.h"
+#include "fsl_device_registers.h"
+#include "fsl_flexcomm.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart"
+#endif
+
+/*!
+ * @brief Used for conversion from `flexcomm_usart_irq_handler_t` to `flexcomm_irq_handler_t`
+ */
+typedef union usart_to_flexcomm
+{
+    flexcomm_usart_irq_handler_t usart_master_handler;
+    flexcomm_irq_handler_t flexcomm_handler;
+} usart_to_flexcomm_t;
+
+enum
+{
+    kUSART_TxIdle, /* TX idle. */
+    kUSART_TxBusy, /* TX busy. */
+    kUSART_RxIdle, /* RX idle. */
+    kUSART_RxBusy  /* RX busy. */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief IRQ name array */
+static const IRQn_Type s_usartIRQ[] = USART_IRQS;
+
+/*! @brief Array to map USART instance number to base address. */
+static const uint32_t s_usartBaseAddrs[FSL_FEATURE_SOC_USART_COUNT] = USART_BASE_ADDRS;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/* Get the index corresponding to the USART */
+/*! brief Returns instance number for USART peripheral base address. */
+uint32_t USART_GetInstance(USART_Type *base)
+{
+    uint32_t i;
+
+    for (i = 0; i < (uint32_t)FSL_FEATURE_SOC_USART_COUNT; i++)
+    {
+        if ((uint32_t)base == s_usartBaseAddrs[i])
+        {
+            break;
+        }
+    }
+
+    assert(i < (uint32_t)FSL_FEATURE_SOC_USART_COUNT);
+    return i;
+}
+
+/*!
+ * brief Get the length of received data in RX ring buffer.
+ *
+ * param handle USART handle pointer.
+ * return Length of received data in RX ring buffer.
+ */
+size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle)
+{
+    size_t size;
+
+    /* Check arguments */
+    assert(NULL != handle);
+    uint16_t rxRingBufferHead = handle->rxRingBufferHead;
+    uint16_t rxRingBufferTail = handle->rxRingBufferTail;
+
+    if (rxRingBufferTail > rxRingBufferHead)
+    {
+        size = (size_t)rxRingBufferHead + handle->rxRingBufferSize - (size_t)rxRingBufferTail;
+    }
+    else
+    {
+        size = (size_t)rxRingBufferHead - (size_t)rxRingBufferTail;
+    }
+    return size;
+}
+
+static bool USART_TransferIsRxRingBufferFull(usart_handle_t *handle)
+{
+    bool full;
+
+    /* Check arguments */
+    assert(NULL != handle);
+
+    if (USART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U))
+    {
+        full = true;
+    }
+    else
+    {
+        full = false;
+    }
+    return full;
+}
+
+/*!
+ * brief Sets up the RX ring buffer.
+ *
+ * This function sets up the RX ring buffer to a specific USART handle.
+ *
+ * When the RX ring buffer is used, data received are stored into the ring buffer even when the
+ * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received
+ * in the ring buffer, the user can get the received data from the ring buffer directly.
+ *
+ * note When using the RX ring buffer, one byte is reserved for internal use. In other
+ * words, if p ringBufferSize is 32, then only 31 bytes are used for saving data.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ * param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer.
+ * param ringBufferSize size of the ring buffer.
+ */
+void USART_TransferStartRingBuffer(USART_Type *base, usart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize)
+{
+    /* Check arguments */
+    assert(NULL != base);
+    assert(NULL != handle);
+    assert(NULL != ringBuffer);
+
+    /* Setup the ringbuffer address */
+    handle->rxRingBuffer     = ringBuffer;
+    handle->rxRingBufferSize = ringBufferSize;
+    handle->rxRingBufferHead = 0U;
+    handle->rxRingBufferTail = 0U;
+    /* ring buffer is ready we can start receiving data */
+    base->FIFOINTENSET = USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK;
+}
+
+/*!
+ * brief Aborts the background transfer and uninstalls the ring buffer.
+ *
+ * This function aborts the background transfer and uninstalls the ring buffer.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ */
+void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle)
+{
+    /* Check arguments */
+    assert(NULL != base);
+    assert(NULL != handle);
+
+    if (handle->rxState == (uint8_t)kUSART_RxIdle)
+    {
+        base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK;
+    }
+    handle->rxRingBuffer     = NULL;
+    handle->rxRingBufferSize = 0U;
+    handle->rxRingBufferHead = 0U;
+    handle->rxRingBufferTail = 0U;
+}
+
+/*!
+ * brief Initializes a USART instance with user configuration structure and peripheral clock.
+ *
+ * This function configures the USART module with the user-defined settings. The user can configure the configuration
+ * structure and also get the default configuration by using the USART_GetDefaultConfig() function.
+ * Example below shows how to use this API to configure USART.
+ * code
+ *  usart_config_t usartConfig;
+ *  usartConfig.baudRate_Bps = 115200U;
+ *  usartConfig.parityMode = kUSART_ParityDisabled;
+ *  usartConfig.stopBitCount = kUSART_OneStopBit;
+ *  USART_Init(USART1, &usartConfig, 20000000U);
+ * endcode
+ *
+ * param base USART peripheral base address.
+ * param config Pointer to user-defined configuration structure.
+ * param srcClock_Hz USART clock source frequency in HZ.
+ * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * retval kStatus_InvalidArgument USART base address is not valid
+ * retval kStatus_Success Status USART initialize succeed
+ */
+status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz)
+{
+    int result;
+
+    /* check arguments */
+    assert(!((NULL == base) || (NULL == config) || (0U == srcClock_Hz)));
+    if ((NULL == base) || (NULL == config) || (0U == srcClock_Hz))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* initialize flexcomm to USART mode */
+    result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_USART);
+    if (kStatus_Success != result)
+    {
+        return result;
+    }
+
+    if (config->enableTx)
+    {
+        /* empty and enable txFIFO */
+        base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK | USART_FIFOCFG_ENABLETX_MASK;
+        /* setup trigger level */
+        base->FIFOTRIG &= ~(USART_FIFOTRIG_TXLVL_MASK);
+        base->FIFOTRIG |= USART_FIFOTRIG_TXLVL(config->txWatermark);
+        /* enable trigger interrupt */
+        base->FIFOTRIG |= USART_FIFOTRIG_TXLVLENA_MASK;
+    }
+
+    /* empty and enable rxFIFO */
+    if (config->enableRx)
+    {
+        base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK | USART_FIFOCFG_ENABLERX_MASK;
+        /* setup trigger level */
+        base->FIFOTRIG &= ~(USART_FIFOTRIG_RXLVL_MASK);
+        base->FIFOTRIG |= USART_FIFOTRIG_RXLVL(config->rxWatermark);
+        /* enable trigger interrupt */
+        base->FIFOTRIG |= USART_FIFOTRIG_RXLVLENA_MASK;
+    }
+    /* setup configuration and enable USART */
+    base->CFG = USART_CFG_PARITYSEL(config->parityMode) | USART_CFG_STOPLEN(config->stopBitCount) |
+                USART_CFG_DATALEN(config->bitCountPerChar) | USART_CFG_LOOP(config->loopback) |
+                USART_CFG_SYNCEN((uint32_t)config->syncMode >> 1) | USART_CFG_SYNCMST((uint8_t)config->syncMode) |
+                USART_CFG_CLKPOL(config->clockPolarity) | USART_CFG_MODE32K(config->enableMode32k) |
+                USART_CFG_CTSEN(config->enableHardwareFlowControl) | USART_CFG_ENABLE_MASK;
+
+    /* Setup baudrate */
+    if (config->enableMode32k)
+    {
+        if ((9600U % config->baudRate_Bps) == 0U)
+        {
+            base->BRG = 9600U / config->baudRate_Bps;
+        }
+        else
+        {
+            return kStatus_USART_BaudrateNotSupport;
+        }
+    }
+    else
+    {
+        result = USART_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz);
+        if (kStatus_Success != result)
+        {
+            return result;
+        }
+    }
+    /* Setting continuous Clock configuration. used for synchronous mode. */
+    USART_EnableContinuousSCLK(base, config->enableContinuousSCLK);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Deinitializes a USART instance.
+ *
+ * This function waits for TX complete, disables TX and RX, and disables the USART clock.
+ *
+ * param base USART peripheral base address.
+ */
+void USART_Deinit(USART_Type *base)
+{
+    /* Check arguments */
+    assert(NULL != base);
+    while (0U == (base->STAT & USART_STAT_TXIDLE_MASK))
+    {
+    }
+    /* Disable interrupts, disable dma requests, disable peripheral */
+    base->FIFOINTENCLR = USART_FIFOINTENCLR_TXERR_MASK | USART_FIFOINTENCLR_RXERR_MASK | USART_FIFOINTENCLR_TXLVL_MASK |
+                         USART_FIFOINTENCLR_RXLVL_MASK;
+    base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK | USART_FIFOCFG_DMARX_MASK);
+    base->CFG &= ~(USART_CFG_ENABLE_MASK);
+}
+
+/*!
+ * brief Gets the default configuration structure.
+ *
+ * This function initializes the USART configuration structure to a default value. The default
+ * values are:
+ *   usartConfig->baudRate_Bps = 115200U;
+ *   usartConfig->parityMode = kUSART_ParityDisabled;
+ *   usartConfig->stopBitCount = kUSART_OneStopBit;
+ *   usartConfig->bitCountPerChar = kUSART_8BitsPerChar;
+ *   usartConfig->loopback = false;
+ *   usartConfig->enableTx = false;
+ *   usartConfig->enableRx = false;
+ *
+ * param config Pointer to configuration structure.
+ */
+void USART_GetDefaultConfig(usart_config_t *config)
+{
+    /* Check arguments */
+    assert(NULL != config);
+
+    /* Initializes the configure structure to zero. */
+    (void)memset(config, 0, sizeof(*config));
+
+    /* Set always all members ! */
+    config->baudRate_Bps              = 115200U;
+    config->parityMode                = kUSART_ParityDisabled;
+    config->stopBitCount              = kUSART_OneStopBit;
+    config->bitCountPerChar           = kUSART_8BitsPerChar;
+    config->loopback                  = false;
+    config->enableRx                  = false;
+    config->enableTx                  = false;
+    config->enableMode32k             = false;
+    config->txWatermark               = kUSART_TxFifo0;
+    config->rxWatermark               = kUSART_RxFifo1;
+    config->syncMode                  = kUSART_SyncModeDisabled;
+    config->enableContinuousSCLK      = false;
+    config->clockPolarity             = kUSART_RxSampleOnFallingEdge;
+    config->enableHardwareFlowControl = false;
+}
+
+#ifdef  FSL_USART_MODIFIED_BY_ARM
+#define FRACT_BITS                 12U
+#define BAUDRATE_DIVIDER_MAX_ERROR  3U
+ /*!
+ * brief Sets the USART instance baud rate.
+ *
+ * This function configures the USART module baud rate. 
+ *
+ *  USART_SetBaudRate(USART1, 115200U, 20000000U);
+ * endcode
+ *
+ * param base USART peripheral base address.
+ * param baudrate_Bps USART baudrate to be set.
+ * param srcClock_Hz USART   clock source frequency in HZ (not used)
+ * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * retval kStatus_Success Set baudrate succeed.
+ * retval kStatus_InvalidArgument One or more arguments are invalid.
+ *
+ * Requirement:
+ *   FlexComm input clock must be set 48MHz (fro_hf / 2).
+ */
+status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz)
+{
+    uint32_t flexcomm_idx;
+    uint32_t flexcomm_clock;
+    uint32_t div, div_calc;         /* divider, 12 LSBs are fractonal part */
+    uint8_t  ovs, ovs_best;         /* oversampling                        */
+    uint32_t br_div, br_div_best;   /* baudate divider                      */
+    uint8_t  mul;
+    uint32_t delta;
+
+    (void)srcClock_Hz;
+
+    flexcomm_idx = FLEXCOMM_GetInstance(base);
+    flexcomm_clock   = CLOCK_GetFlexCommInputClock(flexcomm_idx);
+    if (flexcomm_clock != 48000000U)
+    {
+        /* FlexComm input clock must be 48000000 */
+        return kStatus_USART_BaudrateNotSupport;
+    }
+  
+    /* Calculate fixed point divider (12 LSBs are fractional part) */
+    div = (uint32_t)(((uint64_t)flexcomm_clock << FRACT_BITS) / (uint64_t)baudrate_Bps);
+
+    if ((div >> FRACT_BITS) < 5U)
+    {
+        return kStatus_USART_BaudrateNotSupport;
+    }
+  
+    br_div_best = 0U;
+    if ((div & ((1 << FRACT_BITS) - 1U)) == 0U)
+    {
+        /* Divider has no fractional part */
+        for (ovs = 16; ovs > 8U; ovs--)
+        {
+            br_div = div / ovs;
+            if ((br_div & ((1 << FRACT_BITS) - 1U)) == 0U)
+            {
+                ovs_best    = ovs;
+                br_div_best = br_div >> FRACT_BITS;
+                mul         = 0U;
+                break;
+            }
+        }
+    }
+
+    if (br_div_best == 0U)
+    {
+        /* Divider has fractional part */
+        if ((div >> FRACT_BITS) > 16)
+        {
+            /* Oversampling is fixed to 16 */
+            ovs_best = 16U;
+            br_div = (div / ovs_best)>> FRACT_BITS;
+            if (br_div <= 0xFFFFU)
+            {
+                br_div_best = br_div;
+            }
+            else
+            {
+              return kStatus_USART_BaudrateNotSupport;
+            }
+            /* div = (1 + (mul / 256)) * (ovs * br_div)  =>  mul = (256 * div) / (ovs * br_div) - 256 */
+            mul = ((((uint64_t)div * (uint64_t)256U) / ((uint64_t)ovs_best * (uint64_t)br_div_best)) >> FRACT_BITS) - 256U;
+
+        }
+        else
+        {
+            /* Baudrate divider is fixed to 1. */
+            br_div_best = 1U;
+            ovs_best = div >> FRACT_BITS;
+            mul = ((((uint64_t)div * (uint64_t)256U) / ((uint64_t)ovs_best * (uint64_t)br_div_best)) >> FRACT_BITS) - 256U;
+        }
+    }
+
+    div_calc = (uint32_t)(((uint64_t)ovs_best * (uint64_t)br_div_best * (uint64_t)mul) << FRACT_BITS) / 256U + (((uint64_t)ovs_best * (uint64_t)br_div_best) << FRACT_BITS);
+    delta    = (div < div_calc) ? (div_calc - div) : (div - div_calc);
+    if (((delta * 100U) / div) > BAUDRATE_DIVIDER_MAX_ERROR)
+    {
+        return kStatus_USART_BaudrateNotSupport;
+    }
+
+    CLOCK_SetClkDiv(kCLOCK_DivFlexFrg0 + flexcomm_idx, mul, false);
+    base->OSR = ovs_best - 1U;
+    base->BRG = br_div_best - 1U;
+
+    return kStatus_Success;
+}
+#else
+/*!
+ * brief Sets the USART instance baud rate.
+ *
+ * This function configures the USART module baud rate. This function is used to update
+ * the USART module baud rate after the USART module is initialized by the USART_Init.
+ * code
+ *  USART_SetBaudRate(USART1, 115200U, 20000000U);
+ * endcode
+ *
+ * param base USART peripheral base address.
+ * param baudrate_Bps USART baudrate to be set.
+ * param srcClock_Hz USART clock source frequency in HZ.
+ * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * retval kStatus_Success Set baudrate succeed.
+ * retval kStatus_InvalidArgument One or more arguments are invalid.
+ */
+status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz)
+{
+    uint32_t best_diff = (uint32_t)-1, best_osrval = 0xf, best_brgval = (uint32_t)-1;
+    uint32_t osrval, brgval, diff, baudrate;
+
+    /* check arguments */
+    assert(!((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz)));
+    if ((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* If synchronous master mode is enabled, only configure the BRG value. */
+    if ((base->CFG & USART_CFG_SYNCEN_MASK) != 0U)
+    {
+        if ((base->CFG & USART_CFG_SYNCMST_MASK) != 0U)
+        {
+            brgval    = srcClock_Hz / baudrate_Bps;
+            base->BRG = brgval - 1U;
+        }
+    }
+    else
+    {
+        /*
+         * Smaller values of OSR can make the sampling position within a data bit less accurate and may
+         * potentially cause more noise errors or incorrect data.
+         */
+        for (osrval = best_osrval; osrval >= 8U; osrval--)
+        {
+            brgval = (((srcClock_Hz * 10U) / ((osrval + 1U) * baudrate_Bps)) - 5U) / 10U;
+            if (brgval > 0xFFFFU)
+            {
+                continue;
+            }
+            baudrate = srcClock_Hz / ((osrval + 1U) * (brgval + 1U));
+            diff     = (baudrate_Bps < baudrate) ? (baudrate - baudrate_Bps) : (baudrate_Bps - baudrate);
+            if (diff < best_diff)
+            {
+                best_diff   = diff;
+                best_osrval = osrval;
+                best_brgval = brgval;
+            }
+        }
+
+        /* Check to see if actual baud rate is within 3% of desired baud rate
+         * based on the best calculated OSR and BRG value */
+        baudrate = srcClock_Hz / ((best_osrval + 1U) * (best_brgval + 1U));
+        diff     = (baudrate_Bps < baudrate) ? (baudrate - baudrate_Bps) : (baudrate_Bps - baudrate);
+        if (diff > ((baudrate_Bps / 100U) * 3U))
+        {
+            return kStatus_USART_BaudrateNotSupport;
+        }
+
+        /* value over range */
+        if (best_brgval > 0xFFFFU)
+        {
+            return kStatus_USART_BaudrateNotSupport;
+        }
+
+        base->OSR = best_osrval;
+        base->BRG = best_brgval;
+    }
+
+    return kStatus_Success;
+}
+#endif
+
+/*!
+ * brief Enable 32 kHz mode which USART uses clock from the RTC oscillator as the clock source.
+ *
+ * Please note that in order to use a 32 kHz clock to operate USART properly, the RTC oscillator
+ * and its 32 kHz output must be manully enabled by user, by calling RTC_Init and setting
+ * SYSCON_RTCOSCCTRL_EN bit to 1.
+ * And in 32kHz clocking mode the USART can only work at 9600 baudrate or at the baudrate that
+ * 9600 can evenly divide, eg: 4800, 3200.
+ *
+ * param base USART peripheral base address.
+ * param baudRate_Bps USART baudrate to be set..
+ * param enableMode32k true is 32k mode, false is normal mode.
+ * param srcClock_Hz USART clock source frequency in HZ.
+ * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * retval kStatus_Success Set baudrate succeed.
+ * retval kStatus_InvalidArgument One or more arguments are invalid.
+ */
+status_t USART_Enable32kMode(USART_Type *base, uint32_t baudRate_Bps, bool enableMode32k, uint32_t srcClock_Hz)
+{
+#ifdef FSL_USART_MODIFIED_BY_ARM
+  (void)base;
+  (void)baudRate_Bps;
+  (void)enableMode32k;
+  (void)srcClock_Hz;
+
+  return kStatus_USART_BaudrateNotSupport;
+#else
+    status_t result = kStatus_Success;
+    base->CFG &= ~(USART_CFG_ENABLE_MASK);
+    if (enableMode32k)
+    {
+        base->CFG |= USART_CFG_MODE32K_MASK;
+        if ((9600U % baudRate_Bps) == 0U)
+        {
+            base->BRG = 9600U / baudRate_Bps - 1U;
+        }
+        else
+        {
+            return kStatus_USART_BaudrateNotSupport;
+        }
+    }
+    else
+    {
+        base->CFG &= ~(USART_CFG_MODE32K_MASK);
+        result = USART_SetBaudRate(base, baudRate_Bps, srcClock_Hz);
+        if (kStatus_Success != result)
+        {
+            return result;
+        }
+    }
+    base->CFG |= USART_CFG_ENABLE_MASK;
+    return result;
+#endif
+}
+
+/*!
+ * brief Enable 9-bit data mode for USART.
+ *
+ * This function set the 9-bit mode for USART module. The 9th bit is not used for parity thus can be modified by user.
+ *
+ * param base USART peripheral base address.
+ * param enable true to enable, false to disable.
+ */
+void USART_Enable9bitMode(USART_Type *base, bool enable)
+{
+    assert(base != NULL);
+
+    uint32_t temp = 0U;
+
+    if (enable)
+    {
+        /* Set USART 9-bit mode, disable parity. */
+        temp = base->CFG & ~((uint32_t)USART_CFG_DATALEN_MASK | (uint32_t)USART_CFG_PARITYSEL_MASK);
+        temp |= (uint32_t)USART_CFG_DATALEN(0x2U);
+        base->CFG = temp;
+    }
+    else
+    {
+        /* Set USART to 8-bit mode. */
+        base->CFG &= ~((uint32_t)USART_CFG_DATALEN_MASK);
+        base->CFG |= (uint32_t)USART_CFG_DATALEN(0x1U);
+    }
+}
+
+/*!
+ * brief Transmit an address frame in 9-bit data mode.
+ *
+ * param base USART peripheral base address.
+ * param address USART slave address.
+ */
+void USART_SendAddress(USART_Type *base, uint8_t address)
+{
+    assert(base != NULL);
+    base->FIFOWR = ((uint32_t)address | 0x100UL);
+}
+
+/*!
+ * brief Writes to the TX register using a blocking method.
+ *
+ * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO
+ * to have room and writes data to the TX buffer.
+ *
+ * param base USART peripheral base address.
+ * param data Start address of the data to write.
+ * param length Size of the data to write.
+ * retval kStatus_USART_Timeout Transmission timed out and was aborted.
+ * retval kStatus_InvalidArgument Invalid argument.
+ * retval kStatus_Success Successfully wrote all data.
+ */
+status_t USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length)
+{
+    /* Check arguments */
+    assert(!((NULL == base) || (NULL == data)));
+#if UART_RETRY_TIMES
+    uint32_t waitTimes;
+#endif
+    if ((NULL == base) || (NULL == data))
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* Check whether txFIFO is enabled */
+    if (0U == (base->FIFOCFG & USART_FIFOCFG_ENABLETX_MASK))
+    {
+        return kStatus_InvalidArgument;
+    }
+    for (; length > 0U; length--)
+    {
+        /* Loop until txFIFO get some space for new data */
+#if UART_RETRY_TIMES
+        waitTimes = UART_RETRY_TIMES;
+        while ((0U == (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) && (--waitTimes != 0U))
+#else
+        while (0U == (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK))
+#endif
+        {
+        }
+#if UART_RETRY_TIMES
+        if (0U == waitTimes)
+        {
+            return kStatus_USART_Timeout;
+        }
+#endif
+        base->FIFOWR = *data;
+        data++;
+    }
+    /* Wait to finish transfer */
+#if UART_RETRY_TIMES
+    waitTimes = UART_RETRY_TIMES;
+    while ((0U == (base->STAT & USART_STAT_TXIDLE_MASK)) && (--waitTimes != 0U))
+#else
+    while (0U == (base->STAT & USART_STAT_TXIDLE_MASK))
+#endif
+    {
+    }
+#if UART_RETRY_TIMES
+    if (0U == waitTimes)
+    {
+        return kStatus_USART_Timeout;
+    }
+#endif
+    return kStatus_Success;
+}
+
+/*!
+ * brief Read RX data register using a blocking method.
+ *
+ * This function polls the RX register, waits for the RX register to be full or for RX FIFO to
+ * have data and read data from the TX register.
+ *
+ * param base USART peripheral base address.
+ * param data Start address of the buffer to store the received data.
+ * param length Size of the buffer.
+ * retval kStatus_USART_FramingError Receiver overrun happened while receiving data.
+ * retval kStatus_USART_ParityError Noise error happened while receiving data.
+ * retval kStatus_USART_NoiseError Framing error happened while receiving data.
+ * retval kStatus_USART_RxError Overflow or underflow rxFIFO happened.
+ * retval kStatus_USART_Timeout Transmission timed out and was aborted.
+ * retval kStatus_Success Successfully received all data.
+ */
+status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length)
+{
+    uint32_t statusFlag;
+    status_t status = kStatus_Success;
+#if UART_RETRY_TIMES
+    uint32_t waitTimes;
+#endif
+
+    /* check arguments */
+    assert(!((NULL == base) || (NULL == data)));
+    if ((NULL == base) || (NULL == data))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Check whether rxFIFO is enabled */
+    if ((base->FIFOCFG & USART_FIFOCFG_ENABLERX_MASK) == 0U)
+    {
+        return kStatus_Fail;
+    }
+    for (; length > 0U; length--)
+    {
+        /* loop until rxFIFO have some data to read */
+#if UART_RETRY_TIMES
+        waitTimes = UART_RETRY_TIMES;
+        while (((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) == 0U) && (--waitTimes != 0U))
+#else
+        while ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) == 0U)
+#endif
+        {
+        }
+#if UART_RETRY_TIMES
+        if (waitTimes == 0U)
+        {
+            status = kStatus_USART_Timeout;
+            break;
+        }
+#endif
+        /* check rxFIFO statusFlag */
+        if ((base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) != 0U)
+        {
+            base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;
+            base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK;
+            status = kStatus_USART_RxError;
+            break;
+        }
+        /* check receive statusFlag */
+        statusFlag = base->STAT;
+        /* Clear all status flags */
+        base->STAT |= statusFlag;
+        if ((statusFlag & USART_STAT_PARITYERRINT_MASK) != 0U)
+        {
+            status = kStatus_USART_ParityError;
+        }
+        if ((statusFlag & USART_STAT_FRAMERRINT_MASK) != 0U)
+        {
+            status = kStatus_USART_FramingError;
+        }
+        if ((statusFlag & USART_STAT_RXNOISEINT_MASK) != 0U)
+        {
+            status = kStatus_USART_NoiseError;
+        }
+
+        if (kStatus_Success == status)
+        {
+            *data = (uint8_t)base->FIFORD;
+            data++;
+        }
+        else
+        {
+            break;
+        }
+    }
+    return status;
+}
+
+/*!
+ * brief Initializes the USART handle.
+ *
+ * This function initializes the USART handle which can be used for other USART
+ * transactional APIs. Usually, for a specified USART instance,
+ * call this API once to get the initialized handle.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ * param callback The callback function.
+ * param userData The parameter of the callback function.
+ */
+status_t USART_TransferCreateHandle(USART_Type *base,
+                                    usart_handle_t *handle,
+                                    usart_transfer_callback_t callback,
+                                    void *userData)
+{
+    /* Check 'base' */
+    assert(!((NULL == base) || (NULL == handle)));
+
+    uint32_t instance = 0;
+    usart_to_flexcomm_t handler;
+    handler.usart_master_handler = USART_TransferHandleIRQ;
+
+    if ((NULL == base) || (NULL == handle))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    instance = USART_GetInstance(base);
+
+    (void)memset(handle, 0, sizeof(*handle));
+    /* Set the TX/RX state. */
+    handle->rxState = (uint8_t)kUSART_RxIdle;
+    handle->txState = (uint8_t)kUSART_TxIdle;
+    /* Set the callback and user data. */
+    handle->callback    = callback;
+    handle->userData    = userData;
+    handle->rxWatermark = (uint8_t)USART_FIFOTRIG_RXLVL_GET(base);
+    handle->txWatermark = (uint8_t)USART_FIFOTRIG_TXLVL_GET(base);
+
+    FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle);
+
+    /* Enable interrupt in NVIC. */
+    (void)EnableIRQ(s_usartIRQ[instance]);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Transmits a buffer of data using the interrupt method.
+ *
+ * This function sends data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be written to the TX register. When
+ * all data is written to the TX register in the IRQ handler, the USART driver calls the callback
+ * function and passes the ref kStatus_USART_TxIdle as status parameter.
+ *
+ * note The kStatus_USART_TxIdle is passed to the upper layer when all data is written
+ * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX,
+ * check the kUSART_TransmissionCompleteFlag to ensure that the TX is finished.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ * param xfer USART transfer structure. See  #usart_transfer_t.
+ * retval kStatus_Success Successfully start the data transmission.
+ * retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet.
+ * retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer)
+{
+    /* Check arguments */
+    assert(!((NULL == base) || (NULL == handle) || (NULL == xfer)));
+    if ((NULL == base) || (NULL == handle) || (NULL == xfer))
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* Check xfer members */
+    assert(!((0U == xfer->dataSize) || (NULL == xfer->txData)));
+    if ((0U == xfer->dataSize) || (NULL == xfer->txData))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Return error if current TX busy. */
+    if ((uint8_t)kUSART_TxBusy == handle->txState)
+    {
+        return kStatus_USART_TxBusy;
+    }
+    else
+    {
+        /* Disable IRQ when configuring transfer handle, in case interrupt occurs during the process and messes up the
+         * handle value. */
+        uint32_t interruptMask = USART_GetEnabledInterrupts(base);
+        USART_DisableInterrupts(base, interruptMask);
+        handle->txData        = xfer->txData;
+        handle->txDataSize    = xfer->dataSize;
+        handle->txDataSizeAll = xfer->dataSize;
+        handle->txState       = (uint8_t)kUSART_TxBusy;
+        /* Enable transmiter interrupt and the previously disabled interrupt. */
+        USART_EnableInterrupts(base, interruptMask | (uint32_t)kUSART_TxLevelInterruptEnable);
+    }
+    return kStatus_Success;
+}
+
+/*!
+ * brief Aborts the interrupt-driven data transmit.
+ *
+ * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out
+ * how many bytes are still not sent out.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ */
+void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle)
+{
+    assert(NULL != handle);
+
+    /* Disable interrupts */
+    USART_DisableInterrupts(base, (uint32_t)kUSART_TxLevelInterruptEnable);
+    /* Empty txFIFO */
+    base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK;
+
+    handle->txDataSize = 0U;
+    handle->txState    = (uint8_t)kUSART_TxIdle;
+}
+
+/*!
+ * brief Get the number of bytes that have been sent out to bus.
+ *
+ * This function gets the number of bytes that have been sent out to bus by interrupt method.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ * param count Send bytes count.
+ * retval kStatus_NoTransferInProgress No send in progress.
+ * retval kStatus_InvalidArgument Parameter is invalid.
+ * retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count)
+{
+    assert(NULL != handle);
+    assert(NULL != count);
+
+    if ((uint8_t)kUSART_TxIdle == handle->txState)
+    {
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->txDataSizeAll - handle->txDataSize -
+             ((base->FIFOSTAT & USART_FIFOSTAT_TXLVL_MASK) >> USART_FIFOSTAT_TXLVL_SHIFT);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Receives a buffer of data using an interrupt method.
+ *
+ * This function receives data using an interrupt method. This is a non-blocking function, which
+ *  returns without waiting for all data to be received.
+ * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and
+ * the parameter p receivedBytes shows how many bytes are copied from the ring buffer.
+ * After copying, if the data in the ring buffer is not enough to read, the receive
+ * request is saved by the USART driver. When the new data arrives, the receive request
+ * is serviced first. When all data is received, the USART driver notifies the upper layer
+ * through a callback function and passes the status parameter ref kStatus_USART_RxIdle.
+ * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer.
+ * The 5 bytes are copied to the xfer->data and this function returns with the
+ * parameter p receivedBytes set to 5. For the left 5 bytes, newly arrived data is
+ * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer.
+ * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt
+ * to receive data to the xfer->data. When all data is received, the upper layer is notified.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ * param xfer USART transfer structure, see #usart_transfer_t.
+ * param receivedBytes Bytes received from the ring buffer directly.
+ * retval kStatus_Success Successfully queue the transfer into transmit queue.
+ * retval kStatus_USART_RxBusy Previous receive request is not finished.
+ * retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t USART_TransferReceiveNonBlocking(USART_Type *base,
+                                          usart_handle_t *handle,
+                                          usart_transfer_t *xfer,
+                                          size_t *receivedBytes)
+{
+    uint32_t i;
+    /* How many bytes to copy from ring buffer to user memory. */
+    size_t bytesToCopy = 0U;
+    /* How many bytes to receive. */
+    size_t bytesToReceive;
+    /* How many bytes currently have received. */
+    size_t bytesCurrentReceived;
+    uint32_t interruptMask = 0U;
+
+    /* Check arguments */
+    assert(!((NULL == base) || (NULL == handle) || (NULL == xfer)));
+    if ((NULL == base) || (NULL == handle) || (NULL == xfer))
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* Check xfer members */
+    assert(!((0U == xfer->dataSize) || (NULL == xfer->rxData)));
+    if ((0U == xfer->dataSize) || (NULL == xfer->rxData))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Enable address detect when address match is enabled. */
+    if ((base->CFG & (uint32_t)USART_CFG_AUTOADDR_MASK) != 0U)
+    {
+        base->CTL |= (uint32_t)USART_CTL_ADDRDET_MASK;
+    }
+
+    /* How to get data:
+       1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize
+          to uart handle, enable interrupt to store received data to xfer->data. When
+          all data received, trigger callback.
+       2. If RX ring buffer is enabled and not empty, get data from ring buffer first.
+          If there are enough data in ring buffer, copy them to xfer->data and return.
+          If there are not enough data in ring buffer, copy all of them to xfer->data,
+          save the xfer->data remained empty space to uart handle, receive data
+          to this empty space and trigger callback when finished. */
+    if ((uint8_t)kUSART_RxBusy == handle->rxState)
+    {
+        return kStatus_USART_RxBusy;
+    }
+    else
+    {
+        bytesToReceive       = xfer->dataSize;
+        bytesCurrentReceived = 0U;
+        /* If RX ring buffer is used. */
+        if (handle->rxRingBuffer != NULL)
+        {
+            /* Disable IRQ, protect ring buffer. */
+            interruptMask = USART_GetEnabledInterrupts(base);
+            USART_DisableInterrupts(base, interruptMask);
+
+            /* How many bytes in RX ring buffer currently. */
+            bytesToCopy = USART_TransferGetRxRingBufferLength(handle);
+            if (bytesToCopy != 0U)
+            {
+                bytesToCopy = MIN(bytesToReceive, bytesToCopy);
+                bytesToReceive -= bytesToCopy;
+                /* Copy data from ring buffer to user memory. */
+                for (i = 0U; i < bytesToCopy; i++)
+                {
+                    xfer->rxData[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail];
+                    /* Wrap to 0. Not use modulo (%) because it might be large and slow. */
+                    if ((size_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
+                    {
+                        handle->rxRingBufferTail = 0U;
+                    }
+                    else
+                    {
+                        handle->rxRingBufferTail++;
+                    }
+                }
+            }
+            /* If ring buffer does not have enough data, still need to read more data. */
+            if (bytesToReceive != 0U)
+            {
+                /* No data in ring buffer, save the request to UART handle. */
+                handle->rxData        = xfer->rxData + bytesCurrentReceived;
+                handle->rxDataSize    = bytesToReceive;
+                handle->rxDataSizeAll = xfer->dataSize;
+                handle->rxState       = (uint8_t)kUSART_RxBusy;
+            }
+            /* Re-enable IRQ. */
+            USART_EnableInterrupts(base, interruptMask);
+            /* Call user callback since all data are received. */
+            if (0U == bytesToReceive)
+            {
+                if (handle->callback != NULL)
+                {
+                    handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData);
+                }
+            }
+        }
+        /* Ring buffer not used. */
+        else
+        {
+            /* Disable IRQ when configuring transfer handle, in case interrupt occurs during the process and messes up
+             * the handle value. */
+            interruptMask = USART_GetEnabledInterrupts(base);
+            USART_DisableInterrupts(base, interruptMask);
+            handle->rxData        = xfer->rxData + bytesCurrentReceived;
+            handle->rxDataSize    = bytesToReceive;
+            handle->rxDataSizeAll = bytesToReceive;
+            handle->rxState       = (uint8_t)kUSART_RxBusy;
+
+            /* Enable RX interrupt. */
+            base->FIFOINTENSET = USART_FIFOINTENSET_RXLVL_MASK;
+            /* Re-enable IRQ. */
+            USART_EnableInterrupts(base, interruptMask);
+        }
+        /* Return the how many bytes have read. */
+        if (receivedBytes != NULL)
+        {
+            *receivedBytes = bytesCurrentReceived;
+        }
+    }
+    return kStatus_Success;
+}
+
+/*!
+ * brief Aborts the interrupt-driven data receiving.
+ *
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out
+ * how many bytes not received yet.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ */
+void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle)
+{
+    assert(NULL != handle);
+
+    /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */
+    if (NULL == handle->rxRingBuffer)
+    {
+        /* Disable interrupts */
+        USART_DisableInterrupts(base, (uint32_t)kUSART_RxLevelInterruptEnable);
+        /* Empty rxFIFO */
+        base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;
+    }
+
+    handle->rxDataSize = 0U;
+    handle->rxState    = (uint8_t)kUSART_RxIdle;
+}
+
+/*!
+ * brief Get the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ * param count Receive bytes count.
+ * retval kStatus_NoTransferInProgress No receive in progress.
+ * retval kStatus_InvalidArgument Parameter is invalid.
+ * retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count)
+{
+    assert(NULL != handle);
+    assert(NULL != count);
+
+    if ((uint8_t)kUSART_RxIdle == handle->rxState)
+    {
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->rxDataSizeAll - handle->rxDataSize;
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief USART IRQ handle function.
+ *
+ * This function handles the USART transmit and receive IRQ request.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ */
+void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle)
+{
+    /* Check arguments */
+    assert((NULL != base) && (NULL != handle));
+
+    bool receiveEnabled = ((handle->rxDataSize != 0U) || (handle->rxRingBuffer != NULL));
+    bool sendEnabled    = (handle->txDataSize != 0U);
+    uint8_t rxdata;
+    size_t tmpsize;
+
+    /* If RX overrun. */
+    if ((base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) != 0U)
+    {
+        /* Clear rx error state. */
+        base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK;
+        /* clear rxFIFO */
+        base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;
+        /* Trigger callback. */
+        if (handle->callback != NULL)
+        {
+            handle->callback(base, handle, kStatus_USART_RxError, handle->userData);
+        }
+    }
+    while ((receiveEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) != 0U)) ||
+           (sendEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK) != 0U)))
+    {
+        /* Receive data */
+        if (receiveEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) != 0U))
+        {
+            /* Clear address detect when RXFIFO has data. */
+            base->CTL &= ~(uint32_t)USART_CTL_ADDRDET_MASK;
+            /* Receive to app bufffer if app buffer is present */
+            if (handle->rxDataSize != 0U)
+            {
+                rxdata          = (uint8_t)base->FIFORD;
+                *handle->rxData = rxdata;
+                handle->rxDataSize--;
+                handle->rxData++;
+                receiveEnabled = ((handle->rxDataSize != 0U) || (handle->rxRingBuffer != NULL));
+                if (0U == handle->rxDataSize)
+                {
+                    if (NULL == handle->rxRingBuffer)
+                    {
+                        base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK;
+                    }
+                    handle->rxState = (uint8_t)kUSART_RxIdle;
+                    if (handle->callback != NULL)
+                    {
+                        handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData);
+                    }
+                }
+            }
+            /* Otherwise receive to ring buffer if ring buffer is present */
+            else
+            {
+                if (handle->rxRingBuffer != NULL)
+                {
+                    /* If RX ring buffer is full, trigger callback to notify over run. */
+                    if (USART_TransferIsRxRingBufferFull(handle))
+                    {
+                        if (handle->callback != NULL)
+                        {
+                            handle->callback(base, handle, kStatus_USART_RxRingBufferOverrun, handle->userData);
+                        }
+                    }
+                    /* If ring buffer is still full after callback function, the oldest data is overridden. */
+                    if (USART_TransferIsRxRingBufferFull(handle))
+                    {
+                        /* Increase handle->rxRingBufferTail to make room for new data. */
+                        if ((size_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
+                        {
+                            handle->rxRingBufferTail = 0U;
+                        }
+                        else
+                        {
+                            handle->rxRingBufferTail++;
+                        }
+                    }
+                    /* Read data. */
+                    rxdata                                         = (uint8_t)base->FIFORD;
+                    handle->rxRingBuffer[handle->rxRingBufferHead] = rxdata;
+                    /* Increase handle->rxRingBufferHead. */
+                    if ((size_t)handle->rxRingBufferHead + 1U == handle->rxRingBufferSize)
+                    {
+                        handle->rxRingBufferHead = 0U;
+                    }
+                    else
+                    {
+                        handle->rxRingBufferHead++;
+                    }
+                }
+            }
+        }
+        /* Send data */
+        if (sendEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK) != 0U))
+        {
+            base->FIFOWR = *handle->txData;
+            handle->txDataSize--;
+            handle->txData++;
+            sendEnabled = handle->txDataSize != 0U;
+            if (!sendEnabled)
+            {
+                base->FIFOINTENCLR = USART_FIFOINTENCLR_TXLVL_MASK;
+
+                base->INTENSET = USART_INTENSET_TXIDLEEN_MASK;
+            }
+        }
+    }
+
+    /* Tx idle and the interrupt is enabled. */
+    if ((0U != (base->INTENSET & USART_INTENSET_TXIDLEEN_MASK)) && (0U != (base->INTSTAT & USART_INTSTAT_TXIDLE_MASK)))
+    {
+        /* Set txState to idle only when all data has been sent out to bus. */
+        handle->txState = (uint8_t)kUSART_TxIdle;
+        /* Disable tx idle interrupt */
+        base->INTENCLR = USART_INTENCLR_TXIDLECLR_MASK;
+
+        /* Trigger callback. */
+        if (handle->callback != NULL)
+        {
+            handle->callback(base, handle, kStatus_USART_TxIdle, handle->userData);
+        }
+    }
+
+    /* ring buffer is not used */
+    if (NULL == handle->rxRingBuffer)
+    {
+        tmpsize = handle->rxDataSize;
+
+        /* restore if rx transfer ends and rxLevel is different from default value */
+        if ((tmpsize == 0U) && (USART_FIFOTRIG_RXLVL_GET(base) != handle->rxWatermark))
+        {
+            base->FIFOTRIG =
+                (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | USART_FIFOTRIG_RXLVL(handle->rxWatermark);
+        }
+        /* decrease level if rx transfer is bellow */
+        if ((tmpsize != 0U) && (tmpsize < (USART_FIFOTRIG_RXLVL_GET(base) + 1U)))
+        {
+            base->FIFOTRIG = (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | (USART_FIFOTRIG_RXLVL(tmpsize - 1U));
+        }
+    }
+}

CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/main.c → CMSIS/DAP/Firmware/Examples/MCU-LINK/main.c

@@ -17,11 +17,11 @@
  *
  * ----------------------------------------------------------------------
  *
- * $Date:        21. May 2021
+ * $Date:        15. September 2021
  * $Revision:    V2.0.0
  *
- * Project:      CMSIS-DAP Examples LPC-Link2
- * Title:        main.c CMSIS-DAP Main module for LPC-Link2
+ * Project:      CMSIS-DAP Examples MCU-LINK
+ * Title:        main.c CMSIS-DAP Main module for MCU-LINK
  *
  *---------------------------------------------------------------------------*/
 
@@ -31,13 +31,38 @@
 #include "DAP_config.h"
 #include "DAP.h"
 
+#include "clock_config.h"
+#include "pin_mux.h"
+#include "fsl_dma.h"
+
+// Callbacks for USART0 Driver
+uint32_t USART0_GetFreq    (void) { return CLOCK_GetFlexCommClkFreq(0); }
+void     USART0_InitPins   (void) { /* Done in BOARD_InitBootPins function */ }
+void     USART0_DeinitPins (void) { /* Not implemented */ }
+
+// Callbacks for USART3 Driver
+uint32_t USART3_GetFreq    (void) { return CLOCK_GetFlexCommClkFreq(3); }
+void     USART3_InitPins   (void) { /* Done in BOARD_InitBootPins function */ }
+void     USART3_DeinitPins (void) { /* Not implemented */ }
+
 // Application Main program
 __NO_RETURN void app_main (void *argument) {
   (void)argument;
 
+  BOARD_InitBootPins();
+  BOARD_InitBootClocks();
+
+  DMA_Init(DMA0);
+
   DAP_Setup();                          // DAP Setup 
 
   USBD_Initialize(0U);                  // USB Device Initialization
+  char *ser_num;
+  ser_num = GetSerialNum();
+  if (ser_num != NULL) {
+    USBD_SetSerialNumber(0U, ser_num);  // Update Serial Number
+  }
+
   USBD_Connect(0U);                     // USB Device Connect
 
   while (!USBD_Configured(0U));         // Wait for USB Device to configure
@@ -49,7 +74,10 @@ __NO_RETURN void app_main (void *argument) {
   LED_CONNECTED_OUT(0U);                // Turn off Debugger Connected LED
 
   // Create DAP Thread
-  DAP_ThreadId = osThreadNew(DAP_Thread, NULL, NULL);
+  DAP_ThreadId = osThreadNew(DAP_Thread, NULL, &DAP_ThreadAttr);
+
+  // Create SWO Thread
+  SWO_ThreadId = osThreadNew(SWO_Thread, NULL, &SWO_ThreadAttr);
 
   osDelay(osWaitForever);
   for (;;) {}

CMSIS/DAP/Firmware/Examples/LPC-Link2/V1/osObjects.h → CMSIS/DAP/Firmware/Examples/MCU-LINK/osObjects.h

@@ -17,11 +17,11 @@
  *
  * ----------------------------------------------------------------------
  *
- * $Date:        1. December 2017
+ * $Date:        15. September 2021
  * $Revision:    V2.0.0
  *
- * Project:      CMSIS-DAP Examples LPC-Link2
- * Title:        osObjects.h CMSIS-DAP RTOS2 Objects for LPC-Link2
+ * Project:      CMSIS-DAP Examples MCU-LINK
+ * Title:        osObjects.h CMSIS-DAP RTOS2 Objects for MCU-LINK
  *
  *---------------------------------------------------------------------------*/
 
@@ -32,12 +32,22 @@
 
 #ifdef osObjectsExternal
 extern osThreadId_t DAP_ThreadId;
+extern osThreadId_t SWO_ThreadId;
 #else
+static const osThreadAttr_t DAP_ThreadAttr = {
+  .priority = osPriorityNormal
+};
+static const osThreadAttr_t SWO_ThreadAttr = {
+  .priority = osPriorityAboveNormal
+};
 extern osThreadId_t DAP_ThreadId;
        osThreadId_t DAP_ThreadId;
+extern osThreadId_t SWO_ThreadId;
+       osThreadId_t SWO_ThreadId;
 #endif
 
 extern void DAP_Thread (void *argument);
+extern void SWO_Thread (void *argument);
 
 extern void app_main (void *argument);
 

CMSIS/DAP/Firmware/Examples/MCU-LINK/ser_num.c

@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2021 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------
+ *
+ * $Date:        15. September 2021
+ * $Revision:    V1.0.0
+ *
+ * Project:      CMSIS-DAP Examples MCU-LINK
+ * Title:        ser_num.c CMSIS-DAP Serial Number module for MCU-LINK
+ *
+ *---------------------------------------------------------------------------*/
+
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+
+#include "ser_num.h"
+#include "fsl_iap_ffr.h"
+
+// Serial Number
+#define SER_NUM_PREFIX  "00A1"
+static char SerialNum[32];
+
+/**
+  \brief        Calculate 32-bit CRC (polynom: 0x04C11DB7, init value: 0xFFFFFFFF)
+  \param[in]    data  pointer to data
+  \param[in]    len   data length (in bytes)
+  \return             CRC32 value
+*/
+static uint32_t crc32 (const uint8_t *data, uint32_t len) {
+  uint32_t crc32;
+  uint32_t n;
+
+  crc32 = 0xFFFFFFFFU;
+  while (len != 0U) {
+    crc32 ^= ((uint32_t)*data++) << 24U;
+    for (n = 8U; n; n--) {
+      if (crc32 & 0x80000000U) {
+        crc32 <<= 1U;
+        crc32  ^= 0x04C11DB7U;
+      } else {
+        crc32 <<= 1U;
+      }
+    }
+    len--;
+  }
+  return (crc32);
+}
+
+/**
+  \brief        Get serial number string. First characters are fixed. Last eight
+                characters are Unique (calculated from devices's unique ID)
+  \return       Serial number string or NULL (callculation of unique ID failed)
+*/
+char *GetSerialNum (void) {
+  flash_config_t flash_config;
+  uint8_t  uuid_buf[16];
+  uint32_t uid;
+  char *str;
+
+  str = NULL;
+  if (FFR_Init(&flash_config) == kStatus_Success) {
+    if (FFR_GetUUID(&flash_config, uuid_buf) == kStatus_Success) {
+      uid = crc32(uuid_buf, 16U);
+      snprintf(SerialNum, sizeof(SerialNum), "%s%08X", SER_NUM_PREFIX, uid);
+      str = SerialNum;
+    }
+  }
+
+  return (str);
+}

CMSIS/DAP/Firmware/Examples/MCU-LINK/ser_num.h

@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2021 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------
+ *
+ * $Date:        15. September 2021
+ * $Revision:    V1.0.0
+ *
+ * Project:      CMSIS-DAP Examples MCU-LINK
+ * Title:        ser_num.h CMSIS-DAP Serial Number module for MCU-LINK
+ *
+ *---------------------------------------------------------------------------*/
+
+#ifndef __SER_NUM_H__
+#define __SER_NUM_H__
+
+char *GetSerialNum (void);
+
+#endif /* __SER_NUM_H__ */

CMSIS/DAP/Firmware/Include/DAP.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2021 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2022 ARM Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,8 +17,8 @@
  *
  * ----------------------------------------------------------------------
  *
- * $Date:        26. May 2021
- * $Revision:    V2.1.0
+ * $Date:        26. April 2022
+ * $Revision:    V2.1.1
  *
  * Project:      CMSIS-DAP Include
  * Title:        DAP.h Definitions
@@ -33,7 +33,7 @@
 #ifdef  DAP_FW_V1
 #define DAP_FW_VER                      "1.3.0"
 #else
-#define DAP_FW_VER                      "2.1.0"
+#define DAP_FW_VER                      "2.1.1"
 #endif
 
 // DAP Command IDs

CMSIS/DAP/Firmware/Source/DAP.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2021 ARM Limited. All rights reserved.
+ * Copyright (c) 2013-2022 ARM Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,8 +17,8 @@
  *
  * ----------------------------------------------------------------------
  *
- * $Date:        16. June 2021
- * $Revision:    V2.1.0
+ * $Date:        26. April 2022
+ * $Revision:    V2.1.1
  *
  * Project:      CMSIS-DAP Source
  * Title:        DAP.c CMSIS-DAP Commands
@@ -45,13 +45,9 @@
 
 
 // Clock Macros
-
 #define MAX_SWJ_CLOCK(delay_cycles) \
   ((CPU_CLOCK/2U) / (IO_PORT_WRITE_CYCLES + delay_cycles))
 
-#define CLOCK_DELAY(swj_clock) \
- (((CPU_CLOCK/2U) / swj_clock) - IO_PORT_WRITE_CYCLES)
-
 
          DAP_Data_t DAP_Data;           // DAP Data
 volatile uint8_t    DAP_TransferAbort;  // Transfer Abort Flag
@@ -60,6 +56,29 @@ volatile uint8_t    DAP_TransferAbort;  // Transfer Abort Flag
 static const char DAP_FW_Ver [] = DAP_FW_VER;
 
 
+// Common clock delay calculation routine
+//   clock:    requested SWJ frequency in Hertz
+static void Set_Clock_Delay(uint32_t clock) {
+  uint32_t delay;
+
+  if (clock >= MAX_SWJ_CLOCK(DELAY_FAST_CYCLES)) {
+    DAP_Data.fast_clock  = 1U;
+    DAP_Data.clock_delay = 1U;
+  } else {
+    DAP_Data.fast_clock  = 0U;
+
+    delay = ((CPU_CLOCK/2U) + (clock - 1U)) / clock;
+    if (delay > IO_PORT_WRITE_CYCLES) {
+      delay -= IO_PORT_WRITE_CYCLES;
+      delay  = (delay + (DELAY_SLOW_CYCLES - 1U)) / DELAY_SLOW_CYCLES;
+    } else {
+      delay  = 1U;
+    }
+
+    DAP_Data.clock_delay = delay;
+  }
+}
+
 
 // Get DAP Information
 //   id:      info identifier
@@ -111,7 +130,7 @@ static uint8_t DAP_Info(uint8_t id, uint8_t *info) {
       length = 2U;
       break;
     case DAP_ID_TIMESTAMP_CLOCK:
-#if (TIMESTAMP_CLOCK != 0U) 
+#if (TIMESTAMP_CLOCK != 0U)
       info[0] = (uint8_t)(TIMESTAMP_CLOCK >>  0);
       info[1] = (uint8_t)(TIMESTAMP_CLOCK >>  8);
       info[2] = (uint8_t)(TIMESTAMP_CLOCK >> 16);
@@ -227,7 +246,7 @@ static uint32_t DAP_Connect(const uint8_t *request, uint8_t *response) {
   } else {
     port = *request;
   }
-  
+
   switch (port) {
 #if (DAP_SWD != 0)
     case DAP_PORT_SWD:
@@ -286,9 +305,9 @@ static uint32_t DAP_SWJ_Pins(const uint8_t *request, uint8_t *response) {
   uint32_t select;
   uint32_t wait;
   uint32_t timestamp;
-  
+
   value  = (uint32_t) *(request+0);
-  select = (uint32_t) *(request+1); 
+  select = (uint32_t) *(request+1);
   wait   = (uint32_t)(*(request+2) <<  0) |
            (uint32_t)(*(request+3) <<  8) |
            (uint32_t)(*(request+4) << 16) |
@@ -320,7 +339,7 @@ static uint32_t DAP_SWJ_Pins(const uint8_t *request, uint8_t *response) {
 
   if (wait != 0U) {
 #if (TIMESTAMP_CLOCK != 0U)
-    if (wait > 3000000U) { 
+    if (wait > 3000000U) {
       wait = 3000000U;
     }
 #if (TIMESTAMP_CLOCK >= 1000000U)
@@ -398,22 +417,7 @@ static uint32_t DAP_SWJ_Clock(const uint8_t *request, uint8_t *response) {
     return ((4U << 16) | 1U);
   }
 
-  if (clock >= MAX_SWJ_CLOCK(DELAY_FAST_CYCLES)) {
-    DAP_Data.fast_clock  = 1U;
-    DAP_Data.clock_delay = 1U;
-  } else {
-    DAP_Data.fast_clock  = 0U;
-
-    delay = ((CPU_CLOCK/2U) + (clock - 1U)) / clock;
-    if (delay > IO_PORT_WRITE_CYCLES) {
-      delay -= IO_PORT_WRITE_CYCLES;
-      delay  = (delay + (DELAY_SLOW_CYCLES - 1U)) / DELAY_SLOW_CYCLES;
-    } else {
-      delay  = 1U;
-    }
-
-    DAP_Data.clock_delay = delay;
-  }
+  Set_Clock_Delay(clock);
 
   *response = DAP_OK;
 #else
@@ -433,7 +437,7 @@ static uint32_t DAP_SWJ_Sequence(const uint8_t *request, uint8_t *response) {
   uint32_t count;
 
   count = *request++;
-  if (count == 0U) { 
+  if (count == 0U) {
     count = 256U;
   }
 
@@ -462,7 +466,7 @@ static uint32_t DAP_SWD_Configure(const uint8_t *request, uint8_t *response) {
   value = *request;
   DAP_Data.swd_conf.turnaround = (value & 0x03U) + 1U;
   DAP_Data.swd_conf.data_phase = (value & 0x04U) ? 1U : 0U;
-  
+
   *response = DAP_OK;
 #else
   *response = DAP_ERROR;
@@ -496,7 +500,7 @@ static uint32_t DAP_SWD_Sequence(const uint8_t *request, uint8_t *response) {
   while (sequence_count--) {
     sequence_info = *request++;
     count = sequence_info & SWD_SEQUENCE_CLK;
-    if (count == 0U) { 
+    if (count == 0U) {
       count = 64U;
     }
     count = (count + 7U) / 8U;
@@ -646,7 +650,7 @@ static uint32_t DAP_JTAG_IDCode(const uint8_t *request, uint8_t *response) {
 id_error:
 #endif
   *response = DAP_ERROR;
-  return ((1U << 16) | 1U); 
+  return ((1U << 16) | 1U);
 }
 
 
@@ -660,11 +664,11 @@ static uint32_t DAP_TransferConfigure(const uint8_t *request, uint8_t *response)
   DAP_Data.transfer.idle_cycles =            *(request+0);
   DAP_Data.transfer.retry_count = (uint16_t) *(request+1) |
                                   (uint16_t)(*(request+2) << 8);
-  DAP_Data.transfer.match_retry = (uint16_t) *(request+3) | 
+  DAP_Data.transfer.match_retry = (uint16_t) *(request+3) |
                                   (uint16_t)(*(request+4) << 8);
 
   *response = DAP_OK;
-  return ((5U << 16) | 1U); 
+  return ((5U << 16) | 1U);
 }
 
 
@@ -727,7 +731,7 @@ static uint32_t DAP_SWD_Transfer(const uint8_t *request, uint8_t *response) {
           } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort);
           post_read = 0U;
         }
-        if (response_value != DAP_TRANSFER_OK) { 
+        if (response_value != DAP_TRANSFER_OK) {
           break;
         }
         // Store previous AP data
@@ -1402,14 +1406,14 @@ static uint32_t DAP_JTAG_TransferBlock(const uint8_t *request, uint8_t *response
 
   // Device index (JTAP TAP)
   DAP_Data.jtag_dev.index = *request++;
-  if (DAP_Data.jtag_dev.index >= DAP_Data.jtag_dev.count) { 
+  if (DAP_Data.jtag_dev.index >= DAP_Data.jtag_dev.count) {
     goto end;
   }
 
-  request_count = (uint32_t)(*(request+0) << 0) | 
+  request_count = (uint32_t)(*(request+0) << 0) |
                   (uint32_t)(*(request+1) << 8);
   request += 2;
-  if (request_count == 0U) { 
+  if (request_count == 0U) {
     goto end;
   }
 
@@ -1565,7 +1569,7 @@ static uint32_t DAP_JTAG_WriteAbort(const uint8_t *request, uint8_t *response) {
   DAP_Data.jtag_dev.index = *request;
   if (DAP_Data.jtag_dev.index >= DAP_Data.jtag_dev.count) {
     *response = DAP_ERROR;
-    return (1U); 
+    return (1U);
   }
 
   // Select JTAG chain
@@ -1581,7 +1585,7 @@ static uint32_t DAP_JTAG_WriteAbort(const uint8_t *request, uint8_t *response) {
   JTAG_WriteAbort(data);
 
   *response = DAP_OK;
-  return (1U); 
+  return (1U);
 }
 #endif
 
@@ -1775,7 +1779,7 @@ uint32_t DAP_ExecuteCommand(const uint8_t *request, uint8_t *response) {
       n = DAP_ProcessCommand(request, response);
       num += n;
       request  += (uint16_t)(n >> 16);
-      response += (uint16_t) n;  
+      response += (uint16_t) n;
     }
     return (num);
   }
@@ -1789,8 +1793,6 @@ void DAP_Setup(void) {
 
   // Default settings
   DAP_Data.debug_port  = 0U;
-  DAP_Data.fast_clock  = 0U;
-  DAP_Data.clock_delay = CLOCK_DELAY(DAP_DEFAULT_SWJ_CLOCK);
   DAP_Data.transfer.idle_cycles = 0U;
   DAP_Data.transfer.retry_count = 100U;
   DAP_Data.transfer.match_retry = 0U;
@@ -1803,5 +1805,8 @@ void DAP_Setup(void) {
   DAP_Data.jtag_dev.count = 0U;
 #endif
 
+  // Sets DAP_Data.fast_clock and DAP_Data.clock_delay.
+  Set_Clock_Delay(DAP_DEFAULT_SWJ_CLOCK);
+
   DAP_SETUP();  // Device specific setup
 }