Merge branch 'Add_Pack_Example Keil.LPC1800_DFP' into develop

CMSIS/Pack/Example/Boards/Keil/MCB1800/Blinky/Abstract.txt

@@ -0,0 +1,31 @@
+The 'Blinky' project is a simple program for the LPC1857
+microcontroller using Keil 'MCB1800' Evaluation Board, compliant 
+to Cortex Microcontroller Software Interface Standard (CMSIS v2.0).
+
+Example functionality:                                                   
+ - Clock Settings:
+   - XTAL    =           12.00 MHz
+   - SYSCLK  =          180.00 MHz
+
+ - Sys Timer is used in interrupt mode
+ - LEDs are blinking with speed depending on SysTick timer interrupt period
+ 
+
+The Blinky program is available in different targets:
+
+  LPC1857 Flash:       configured for on-chip Flash
+                       Valid Flash Signature is created with ElfDwT tool.
+                       See "Options for Target" - "User")
+
+  LPC1857 RAM:         runs from Internal RAM located on chip
+                       (may be used for target debugging)
+
+  LPC1857 Ext. Flash:  runs from NOR Flash located on board
+                       (used for production or target debugging)
+                       Set jumpers for boot pins to boot from External Flash
+                       and press RESET button while holding down ISP button!
+
+  LPC1857 SPIFI:       runs from SPIFI Flash located on board
+                       Set jumpers for boot pins to boot from SPIFI
+                       and press RESET button while holding down ISP button
+                       (when on-chip Flash contains a valid image)!

CMSIS/Pack/Example/Boards/Keil/MCB1800/Blinky/Blinky.c

@@ -0,0 +1,78 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Name:    Blinky.c
+ * Purpose: LED Flasher for MCB1800
+ *
+ *----------------------------------------------------------------------------*/
+
+#include "LPC18xx.h"                    /* LPC18xx Definitions                */
+#include "Board_LED.h"
+
+uint32_t LEDOn, LEDOff; 
+
+/*----------------------------------------------------------------------------
+  SysTick IRQ Handler
+ *----------------------------------------------------------------------------*/
+void SysTick_Handler (void) {
+  static uint32_t ticks;
+  
+  switch (ticks++) {
+    case  0: LEDOn  = 1; break;
+    case  5: LEDOff = 1; break;
+    case  9: ticks  = 0; break;
+    
+    default:
+      if (ticks > 10) {
+        ticks = 0;
+      }
+  }
+}
+
+/*----------------------------------------------------------------------------
+  Main function
+ *----------------------------------------------------------------------------*/
+int main (void) {
+  int32_t max_num = LED_GetCount() - 1;
+  int32_t num = 0;
+  int32_t dir = 1;
+
+  SystemCoreClockUpdate ();                 /* Update system core clock       */  
+  SysTick_Config(SystemCoreClock/100);      /* Generate interrupt each 10 ms  */
+  LED_Initialize();                         /* LED Initialization             */
+
+  while (1) {
+    if (LEDOn) {
+      LEDOn = 0;
+      LED_On (num);                         /* Turn specified LED on          */
+    }
+
+    if (LEDOff) {
+      LEDOff = 0;
+      LED_Off (num);                        /* Turn specified LED off         */
+
+      num += dir;                           /* Change LED number              */
+      
+      if (dir == 1 && num == max_num) {
+        dir = -1;                           /* Change direction to down       */
+      }
+      else if (num == 0) {
+        dir =  1;                           /* Change direction to up         */
+      }
+    }
+  }
+}

CMSIS/Pack/Example/Boards/Keil/MCB1800/Blinky/Blinky.uvoptx

@@ -0,0 +1,766 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>LPC1857 Flash</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\Flash\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>8</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>MCB1800 Schematics (MCB1800)</Title>
+          <Path>C:\Keil\ARM\PACK\Keil\LPC1800_DFP\2.6.0-dev1\Documents\MCB1800v1-3-schematics.pdf</Path>
+        </Book>
+        <Book>
+          <Number>1</Number>
+          <Title>User Manual (MCB1800)</Title>
+          <Path>C:\Keil\ARM\PACK\Keil\LPC1800_DFP\2.6.0-dev1\Documents\mcb1800.chm</Path>
+        </Book>
+        <Book>
+          <Number>2</Number>
+          <Title>MCB1800 Evaluation Board Web Page (MCB1800)</Title>
+          <Path>http://www.keil.com/mcb1800/</Path>
+        </Book>
+      </Books>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>0</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name>(105=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-UV1742AOE -O207 -S8 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC180000000 -TP21 -TDS802F -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD10000000 -FC1000 -FN2 -FF0LPC18xx43xx_512_BA.flm -FS01A000000 -FL080000 -FP0($$Device:LPC1857$Flash\LPC18xx43xx_512_BA.flm) -FF1LPC18xx43xx_512_BB.flm -FS11B000000 -FL180000 -FP1($$Device:LPC1857$Flash\LPC18xx43xx_512_BB.flm)</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>1</periodic>
+        <aLwin>1</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>LPC1857 RAM</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\RAM\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>8</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>MCB1800 Schematics (MCB1800)</Title>
+          <Path>C:\Keil\ARM\PACK\Keil\LPC1800_DFP\2.6.0-dev1\Documents\MCB1800v1-3-schematics.pdf</Path>
+        </Book>
+        <Book>
+          <Number>1</Number>
+          <Title>User Manual (MCB1800)</Title>
+          <Path>C:\Keil\ARM\PACK\Keil\LPC1800_DFP\2.6.0-dev1\Documents\mcb1800.chm</Path>
+        </Book>
+        <Book>
+          <Number>2</Number>
+          <Title>MCB1800 Evaluation Board Web Page (MCB1800)</Title>
+          <Path>http://www.keil.com/mcb1800/</Path>
+        </Book>
+      </Books>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>0</tLdApp>
+        <tGomain>0</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile>.\Debug_RAM.ini</tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name>(105=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-UV1742AOE -O207 -S8 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC180000000 -TP21 -TDS802F -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD10000000 -FC1000 -FN0</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <MemoryWindow1>
+        <Mm>
+          <WinNumber>1</WinNumber>
+          <SubType>2</SubType>
+          <ItemText>0x2FC</ItemText>
+          <AccSizeX>0</AccSizeX>
+        </Mm>
+      </MemoryWindow1>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>1</periodic>
+        <aLwin>1</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>LPC1857 Ext. Flash</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\ExtFlash\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>8</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>MCB1800 Schematics (MCB1800)</Title>
+          <Path>C:\Keil\ARM\PACK\Keil\LPC1800_DFP\2.6.0-dev1\Documents\MCB1800v1-3-schematics.pdf</Path>
+        </Book>
+        <Book>
+          <Number>1</Number>
+          <Title>User Manual (MCB1800)</Title>
+          <Path>C:\Keil\ARM\PACK\Keil\LPC1800_DFP\2.6.0-dev1\Documents\mcb1800.chm</Path>
+        </Book>
+        <Book>
+          <Number>2</Number>
+          <Title>MCB1800 Evaluation Board Web Page (MCB1800)</Title>
+          <Path>http://www.keil.com/mcb1800/</Path>
+        </Book>
+      </Books>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>0</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name>(105=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-UV1742AOE -O207 -S8 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC180000000 -TP21 -TDS802F -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD10000000 -FC1000 -FN1 -FF0S29GL064Nx2 -FS01C000000 -FL01000000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>1</periodic>
+        <aLwin>1</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>LPC1857 SPIFI</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\SPIFI\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>8</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>MCB1800 Schematics (MCB1800)</Title>
+          <Path>C:\Keil\ARM\PACK\Keil\LPC1800_DFP\2.6.0-dev1\Documents\MCB1800v1-3-schematics.pdf</Path>
+        </Book>
+        <Book>
+          <Number>1</Number>
+          <Title>User Manual (MCB1800)</Title>
+          <Path>C:\Keil\ARM\PACK\Keil\LPC1800_DFP\2.6.0-dev1\Documents\mcb1800.chm</Path>
+        </Book>
+        <Book>
+          <Number>2</Number>
+          <Title>MCB1800 Evaluation Board Web Page (MCB1800)</Title>
+          <Path>http://www.keil.com/mcb1800/</Path>
+        </Book>
+      </Books>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>0</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name>(105=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-UV1742AOE -O974 -S8 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC180000000 -TP21 -TDS802F -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD10000000 -FC4000 -FN1 -FF0LPC18xx43xx_S25FL032 -FS014000000 -FL0400000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>1</periodic>
+        <aLwin>1</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+    </TargetOption>
+  </Target>
+
+  <Group>
+    <GroupName>Source Files</GroupName>
+    <tvExp>1</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>1</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\Blinky.c</PathWithFileName>
+      <FilenameWithoutPath>Blinky.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>Documentation</GroupName>
+    <tvExp>1</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>2</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\Abstract.txt</PathWithFileName>
+      <FilenameWithoutPath>Abstract.txt</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>::Board Support</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>1</RteFlg>
+  </Group>
+
+  <Group>
+    <GroupName>::CMSIS</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>1</RteFlg>
+  </Group>
+
+  <Group>
+    <GroupName>::Device</GroupName>
+    <tvExp>1</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>1</RteFlg>
+  </Group>
+
+</ProjectOpt>

CMSIS/Pack/Example/Boards/Keil/MCB1800/Blinky/Blinky.uvprojx

@@ -0,0 +1,1863 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>LPC1857 Flash</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>5060020::V5.06 (build 20)::ARMCC</pCCUsed>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>LPC1857</Device>
+          <Vendor>NXP (founded by Philips)</Vendor>
+          <PackID>Keil.LPC1800_DFP.2.6.0-dev1</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IRAM(0x10000000,0x8000) IRAM2(0x20000000,0x10000) IROM(0x1A000000,0x80000) IROM2(0x1B000000,0x80000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD10000000 -FC1000 -FN2 -FF0LPC18xx43xx_512_BA -FS01A000000 -FL080000 -FF1LPC18xx43xx_512_BB -FS11B000000 -FL180000 -FP0($$Device:LPC1857$Flash\LPC18xx43xx_512_BA.flm) -FP1($$Device:LPC1857$Flash\LPC18xx43xx_512_BB.flm))</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:LPC1857$Device\Include\LPC18xx.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:LPC1857$SVD\LPC18xx.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\Flash\</OutputDirectory>
+          <OutputName>Blinky</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\Flash\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>1</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name>$K\ARM\BIN\ElfDwT.exe !L BASEADDRESS(0x1A000000)</UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>-REMAP -MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments>-REMAP -MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+            <RestoreSysVw>1</RestoreSysVw>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>0</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>1</RestoreTracepoints>
+            <RestoreSysVw>1</RestoreSysVw>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>1</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>BIN\UL2CM3.DLL</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M3"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>1</hadIRAM2>
+            <hadIROM2>1</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>1</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x8000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x1a000000</StartAddress>
+                <Size>0x80000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x1a000000</StartAddress>
+                <Size>0x80000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x1b000000</StartAddress>
+                <Size>0x80000</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x8000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>0</uC99>
+            <useXO>0</useXO>
+            <v6Lang>0</v6Lang>
+            <v6LangP>0</v6LangP>
+            <vShortEn>0</vShortEn>
+            <vShortWch>0</vShortWch>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x1A000000</TextAddressRange>
+            <DataAddressRange>0x10000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Source Files</GroupName>
+          <Files>
+            <File>
+              <FileName>Blinky.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Blinky.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Documentation</GroupName>
+          <Files>
+            <File>
+              <FileName>Abstract.txt</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\Abstract.txt</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::Board Support</GroupName>
+        </Group>
+        <Group>
+          <GroupName>::CMSIS</GroupName>
+        </Group>
+        <Group>
+          <GroupName>::Device</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+    <Target>
+      <TargetName>LPC1857 RAM</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>5060020::V5.06 (build 20)::ARMCC</pCCUsed>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>LPC1857</Device>
+          <Vendor>NXP (founded by Philips)</Vendor>
+          <PackID>Keil.LPC1800_DFP.2.6.0-dev1</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IRAM(0x10000000,0x8000) IRAM2(0x20000000,0x10000) IROM(0x1A000000,0x80000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD10000000 -FC1000 -FN2 -FF0LPC18xx43xx_512_BA -FS01A000000 -FL080000 -FF1LPC18xx43xx_512_BB -FS11B000000 -FL180000 -FP0($$Device:LPC1857$Flash\LPC18xx43xx_512_BA.flm))</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:LPC1857$Device\Include\LPC18xx.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:LPC1857$SVD\LPC18xx.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\RAM\</OutputDirectory>
+          <OutputName>Blinky</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\RAM\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>-REMAP -MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments>-REMAP -MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+            <RestoreSysVw>1</RestoreSysVw>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>0</LoadApplicationAtStartup>
+            <RunToMain>0</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>1</RestoreTracepoints>
+            <RestoreSysVw>1</RestoreSysVw>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>1</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile>.\Debug_RAM.ini</InitializationFile>
+            <Driver>BIN\UL2CM3.DLL</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M3"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>1</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>0</Im1Chk>
+            <Im2Chk>1</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x8000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x1a000000</StartAddress>
+                <Size>0x80000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x8000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>0</uC99>
+            <useXO>0</useXO>
+            <v6Lang>0</v6Lang>
+            <v6LangP>0</v6LangP>
+            <vShortEn>0</vShortEn>
+            <vShortWch>0</vShortWch>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x1A000000</TextAddressRange>
+            <DataAddressRange>0x10000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Source Files</GroupName>
+          <Files>
+            <File>
+              <FileName>Blinky.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Blinky.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Documentation</GroupName>
+          <Files>
+            <File>
+              <FileName>Abstract.txt</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\Abstract.txt</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::Board Support</GroupName>
+        </Group>
+        <Group>
+          <GroupName>::CMSIS</GroupName>
+        </Group>
+        <Group>
+          <GroupName>::Device</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+    <Target>
+      <TargetName>LPC1857 Ext. Flash</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>5060020::V5.06 (build 20)::ARMCC</pCCUsed>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>LPC1857</Device>
+          <Vendor>NXP (founded by Philips)</Vendor>
+          <PackID>Keil.LPC1800_DFP.2.6.0-dev1</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IRAM(0x10000000,0x8000) IRAM2(0x20000000,0x10000) IROM(0x1A000000,0x80000) IROM2(0x1B000000,0x80000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD10000000 -FC1000 -FN2 -FF0LPC18xx43xx_512_BA -FS01A000000 -FL080000 -FF1LPC18xx43xx_512_BB -FS11B000000 -FL180000 -FP0($$Device:LPC1857$Flash\LPC18xx43xx_512_BA.flm) -FP1($$Device:LPC1857$Flash\LPC18xx43xx_512_BB.flm))</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:LPC1857$Device\Include\LPC18xx.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:LPC1857$SVD\LPC18xx.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\ExtFlash\</OutputDirectory>
+          <OutputName>Blinky</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\ExtFlash\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>-REMAP -MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments>-REMAP -MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+            <RestoreSysVw>1</RestoreSysVw>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>0</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>1</RestoreTracepoints>
+            <RestoreSysVw>1</RestoreSysVw>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>1</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>BIN\UL2CM3.DLL</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4>.\Prog_Ext_NOR.ini</Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M3"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>1</hadIRAM2>
+            <hadIROM2>1</hadIROM2>
+            <StupSel>1</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>0</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>1</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>0</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x8000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x1a000000</StartAddress>
+                <Size>0x80000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x1c000000</StartAddress>
+                <Size>0x1000000</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x1a000000</StartAddress>
+                <Size>0x80000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x1b000000</StartAddress>
+                <Size>0x80000</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x8000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>0</uC99>
+            <useXO>0</useXO>
+            <v6Lang>0</v6Lang>
+            <v6LangP>0</v6LangP>
+            <vShortEn>0</vShortEn>
+            <vShortWch>0</vShortWch>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>NO_CRP</Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x1C000000</TextAddressRange>
+            <DataAddressRange>0x10000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Source Files</GroupName>
+          <Files>
+            <File>
+              <FileName>Blinky.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Blinky.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Documentation</GroupName>
+          <Files>
+            <File>
+              <FileName>Abstract.txt</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\Abstract.txt</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::Board Support</GroupName>
+        </Group>
+        <Group>
+          <GroupName>::CMSIS</GroupName>
+        </Group>
+        <Group>
+          <GroupName>::Device</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+    <Target>
+      <TargetName>LPC1857 SPIFI</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>5060020::V5.06 (build 20)::ARMCC</pCCUsed>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>LPC1857</Device>
+          <Vendor>NXP (founded by Philips)</Vendor>
+          <PackID>Keil.LPC1800_DFP.2.6.0-dev1</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IRAM(0x10000000,0x8000) IRAM2(0x20000000,0x10000) IROM(0x1A000000,0x80000) IROM2(0x1B000000,0x80000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD10000000 -FC1000 -FN2 -FF0LPC18xx43xx_512_BA -FS01A000000 -FL080000 -FF1LPC18xx43xx_512_BB -FS11B000000 -FL180000 -FP0($$Device:LPC1857$Flash\LPC18xx43xx_512_BA.flm) -FP1($$Device:LPC1857$Flash\LPC18xx43xx_512_BB.flm))</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:LPC1857$Device\Include\LPC18xx.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:LPC1857$SVD\LPC18xx.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\SPIFI\</OutputDirectory>
+          <OutputName>Blinky</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\SPIFI\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>-REMAP -MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments>-REMAP -MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+            <RestoreSysVw>1</RestoreSysVw>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>0</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>1</RestoreTracepoints>
+            <RestoreSysVw>1</RestoreSysVw>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>1</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>BIN\UL2CM3.DLL</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M3"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>1</hadIRAM2>
+            <hadIROM2>1</hadIROM2>
+            <StupSel>1</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>0</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>1</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>0</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x8000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x1a000000</StartAddress>
+                <Size>0x80000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x14000000</StartAddress>
+                <Size>0x400000</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x1a000000</StartAddress>
+                <Size>0x80000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x1b000000</StartAddress>
+                <Size>0x80000</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x8000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>0</uC99>
+            <useXO>0</useXO>
+            <v6Lang>0</v6Lang>
+            <v6LangP>0</v6LangP>
+            <vShortEn>0</vShortEn>
+            <vShortWch>0</vShortWch>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>NO_CRP</Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x14000000</TextAddressRange>
+            <DataAddressRange>0x10000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Source Files</GroupName>
+          <Files>
+            <File>
+              <FileName>Blinky.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Blinky.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Documentation</GroupName>
+          <Files>
+            <File>
+              <FileName>Abstract.txt</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\Abstract.txt</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::Board Support</GroupName>
+        </Group>
+        <Group>
+          <GroupName>::CMSIS</GroupName>
+        </Group>
+        <Group>
+          <GroupName>::Device</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis>
+      <api Capiversion="1.00" Cclass="Board Support" Cgroup="LED" exclusive="0">
+        <package name="MDK-Middleware" schemaVersion="1.0" url="http://www.keil.com/pack/" vendor="Keil" version="5.99.0"/>
+        <targetInfos>
+          <targetInfo name="LPC1857 Ext. Flash"/>
+          <targetInfo name="LPC1857 Flash"/>
+          <targetInfo name="LPC1857 RAM"/>
+          <targetInfo name="LPC1857 SPIFI"/>
+        </targetInfos>
+      </api>
+    </apis>
+    <components>
+      <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="3.30.0" condition="CMSIS Core">
+        <package name="CMSIS" schemaVersion="1.0" url="http://www.keil.com/pack/" vendor="ARM" version="4.0.1"/>
+        <targetInfos>
+          <targetInfo name="LPC1857 Ext. Flash"/>
+          <targetInfo name="LPC1857 Flash"/>
+          <targetInfo name="LPC1857 RAM"/>
+          <targetInfo name="LPC1857 SPIFI"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Board Support" Cgroup="LED" Cvendor="Keil" Cversion="1.00" condition="LPC1800 CMSIS SCU GPIO">
+        <package name="LPC1800_DFP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="Keil" version="1.99.1"/>
+        <targetInfos>
+          <targetInfo name="LPC1857 Ext. Flash"/>
+          <targetInfo name="LPC1857 Flash"/>
+          <targetInfo name="LPC1857 RAM"/>
+          <targetInfo name="LPC1857 SPIFI"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="GPIO" Cvendor="Keil" Cversion="1.00" condition="LPC1800 CMSIS">
+        <package name="LPC1800_DFP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="Keil" version="1.99.1"/>
+        <targetInfos>
+          <targetInfo name="LPC1857 Ext. Flash"/>
+          <targetInfo name="LPC1857 Flash"/>
+          <targetInfo name="LPC1857 RAM"/>
+          <targetInfo name="LPC1857 SPIFI"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="SCU" Cvendor="Keil" Cversion="1.00" condition="LPC1800 CMSIS">
+        <package name="LPC1800_DFP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="Keil" version="1.99.1"/>
+        <targetInfos>
+          <targetInfo name="LPC1857 Ext. Flash"/>
+          <targetInfo name="LPC1857 Flash"/>
+          <targetInfo name="LPC1857 RAM"/>
+          <targetInfo name="LPC1857 SPIFI"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="LPC1800 CMSIS">
+        <package name="LPC1800_DFP" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="Keil" version="2.6.0-dev1"/>
+        <targetInfos>
+          <targetInfo name="LPC1857 Ext. Flash"/>
+          <targetInfo name="LPC1857 Flash"/>
+          <targetInfo name="LPC1857 RAM"/>
+          <targetInfo name="LPC1857 SPIFI">
+            <c>
+              <Define>USE_SPIFI=1</Define>
+            </c>
+          </targetInfo>
+        </targetInfos>
+      </component>
+    </components>
+    <files>
+      <file attr="config" category="header" name="RTE_Driver\Config\RTE_Device.h">
+        <instance index="0">RTE\Device\LPC1857\RTE_Device.h</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="2.00" Dname="LPC1857" RTE_Components_h="#define RTE_DEVICE_STARTUP_LPC18XX    /* Device Startup for NXP18XX */" condition="LPC18xx CMSIS Device"/>
+        <package name="LPC18xx_DFP" url="http://www.keil.com/pack" vendor="Keil" version="0.0.1"/>
+        <targetInfos>
+          <targetInfo name="LPC1857 Ext. Flash"/>
+          <targetInfo name="LPC1857 Flash"/>
+          <targetInfo name="LPC1857 RAM"/>
+          <targetInfo name="LPC1857 SPIFI"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="source" name="Device\Source\ARM\startup_LPC18xx.s">
+        <instance index="0">RTE\Device\LPC1857\startup_LPC18xx.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" Dname="LPC1857" RTE_Components_h="#define RTE_DEVICE_STARTUP_LPC18XX    /* Device Startup for NXP18XX */" condition="LPC18xx CMSIS Device"/>
+        <package name="LPC18xx_DFP" url="http://www.keil.com/pack" vendor="Keil" version="0.0.1"/>
+        <targetInfos>
+          <targetInfo name="LPC1857 Ext. Flash"/>
+          <targetInfo name="LPC1857 Flash"/>
+          <targetInfo name="LPC1857 RAM"/>
+          <targetInfo name="LPC1857 SPIFI"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="source" name="Device\Source\system_LPC18xx.c" version="1.0.1">
+        <instance index="0">RTE\Device\LPC1857\system_LPC18xx.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="LPC1800 CMSIS"/>
+        <package name="LPC1800_DFP" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="Keil" version="2.6.0-dev1"/>
+        <targetInfos>
+          <targetInfo name="LPC1857 Ext. Flash"/>
+          <targetInfo name="LPC1857 Flash"/>
+          <targetInfo name="LPC1857 RAM"/>
+          <targetInfo name="LPC1857 SPIFI"/>
+        </targetInfos>
+      </file>
+    </files>
+  </RTE>
+
+</Project>

CMSIS/Pack/Example/Boards/Keil/MCB1800/Blinky/Debug_RAM.ini

@@ -0,0 +1,23 @@
+/******************************************************************************/
+/* Debug_RAM.ini: Initialization File for Debugging from Internal RAM on      */
+/*                NXP LPC18xx/LPC43xx                                         */
+/******************************************************************************/
+/* This file is part of the uVision/ARM development tools.                    */
+/* Copyright (c) 2005-2014 Keil Software. All rights reserved.                */
+/* This software may only be used under the terms of a valid, current,        */
+/* end user licence from KEIL for a compatible version of KEIL software       */
+/* development tools. Nothing else gives you the right to use this software.  */
+/******************************************************************************/
+
+FUNC void Setup (void) {
+  SP = _RDWORD(0x10000000);             // Setup Stack Pointer
+  PC = _RDWORD(0x10000004);             // Setup Program Counter
+  XPSR = 0x01000000;                    // Set Thumb bit
+  _WDWORD(0xE000ED08, 0x10000000);      // Setup Vector Table Offset Register
+  _WDWORD(0x40043100, 0x10000000);      // Set shadow pointer
+}
+
+LOAD %L INCREMENTAL                     // Download to RAM
+Setup();
+
+g, main

CMSIS/Pack/Example/Boards/Keil/MCB1800/Blinky/Prog_Ext_NOR.ini

@@ -0,0 +1,78 @@
+/******************************************************************************/
+/* Prog_Ext_NOR.INI: Initialization File for Programming of External NOR      */ 
+/*                   Flash for NXP LPC18xx/LPC43xx                            */
+/******************************************************************************/
+/* This file is part of the uVision/ARM development tools.                    */
+/* Copyright (c) 2005-2012 Keil Software. All rights reserved.                */
+/* This software may only be used under the terms of a valid, current,        */
+/* end user licence from KEIL for a compatible version of KEIL software       */
+/* development tools. Nothing else gives you the right to use this software.  */
+/******************************************************************************/
+
+// Setup pins for external data/address bus 
+_WDWORD(0x4008609C, 0x00000073);   // D0,  SFSP1_7    
+_WDWORD(0x400860A0, 0x00000073);   // D1,  SFSP1_8    
+_WDWORD(0x400860A4, 0x00000073);   // D2,  SFSP1_9    
+_WDWORD(0x400860A8, 0x00000073);   // D3,  SFSP1_10   
+_WDWORD(0x400860AC, 0x00000073);   // D4,  SFSP1_11   
+_WDWORD(0x400860B0, 0x00000073);   // D5,  SFSP1_12   
+_WDWORD(0x400860B4, 0x00000073);   // D6,  SFSP1_13   
+_WDWORD(0x400860B8, 0x00000073);   // D7,  SFSP1_14   
+_WDWORD(0x40086290, 0x00000072);   // D8,  SFSP5_4    
+_WDWORD(0x40086294, 0x00000072);   // D9,  SFSP5_5    
+_WDWORD(0x40086298, 0x00000072);   // D10, SFSP5_6    
+_WDWORD(0x4008629C, 0x00000072);   // D11, SFSP5_7    
+_WDWORD(0x40086280, 0x00000072);   // D12, SFSP5_0    
+_WDWORD(0x40086284, 0x00000072);   // D13, SFSP5_1    
+_WDWORD(0x40086288, 0x00000072);   // D14, SFSP5_2    
+_WDWORD(0x4008628C, 0x00000072);   // D15, SFSP5_3    
+_WDWORD(0x40086688, 0x00000072);   // D16, SFSPD_2    
+_WDWORD(0x4008668C, 0x00000072);   // D17, SFSPD_3    
+_WDWORD(0x40086690, 0x00000072);   // D18, SFSPD_4    
+_WDWORD(0x40086694, 0x00000072);   // D19, SFSPD_5    
+_WDWORD(0x40086698, 0x00000072);   // D20, SFSPD_6    
+_WDWORD(0x4008669C, 0x00000072);   // D21, SFSPD_7    
+_WDWORD(0x400866A0, 0x00000072);   // D22, SFSPD_8    
+_WDWORD(0x400866A4, 0x00000072);   // D23, SFSPD_9    
+_WDWORD(0x40086714, 0x00000073);   // D24, SFSPE_5    
+_WDWORD(0x40086718, 0x00000073);   // D25, SFSPE_6    
+_WDWORD(0x4008671C, 0x00000073);   // D26, SFSPE_7    
+_WDWORD(0x40086720, 0x00000073);   // D27, SFSPE_8    
+_WDWORD(0x40086724, 0x00000073);   // D28, SFSPE_9    
+_WDWORD(0x40086728, 0x00000073);   // D29, SFSPE_10   
+_WDWORD(0x4008672C, 0x00000073);   // D30, SFSPE_11   
+_WDWORD(0x40086730, 0x00000073);   // D31, SFSPE_12   
+
+_WDWORD(0x4008612C, 0x00000073);   // A2,  SFSP2_11   
+_WDWORD(0x40086130, 0x00000073);   // A3,  SFSP2_12   
+_WDWORD(0x40086134, 0x00000073);   // A4,  SFSP2_13   
+_WDWORD(0x40086080, 0x00000072);   // A5,  SFSP1_0    
+_WDWORD(0x40086084, 0x00000072);   // A6,  SFSP1_1    
+_WDWORD(0x40086088, 0x00000072);   // A7,  SFSP1_2    
+_WDWORD(0x40086120, 0x00000073);   // A8,  SFSP2_8    
+_WDWORD(0x4008611C, 0x00000073);   // A9,  SFSP2_7    
+_WDWORD(0x40086118, 0x00000072);   // A10, SFSP2_6    
+_WDWORD(0x40086108, 0x00000072);   // A11, SFSP2_2    
+_WDWORD(0x40086104, 0x00000072);   // A12, SFSP2_1    
+_WDWORD(0x40086100, 0x00000072);   // A13, SFSP2_0    
+_WDWORD(0x40086320, 0x00000071);   // A14, SFSP6_8    
+_WDWORD(0x4008631C, 0x00000071);   // A15, SFSP6_7    
+_WDWORD(0x400866C0, 0x00000072);   // A16, SFSPD_16   
+_WDWORD(0x400866BC, 0x00000072);   // A17, SFSPD_15   
+_WDWORD(0x40086700, 0x00000073);   // A18, SFSPE_0    
+_WDWORD(0x40086704, 0x00000073);   // A19, SFSPE_1    
+_WDWORD(0x40086708, 0x00000073);   // A20, SFSPE_2    
+_WDWORD(0x4008670C, 0x00000073);   // A21, SFSPE_3    
+_WDWORD(0x40086710, 0x00000073);   // A22, SFSPE_4    
+_WDWORD(0x40086510, 0x00000073);   // A23, SFSPA_4    
+
+_WDWORD(0x4008608C, 0x00000073);   // OE,  SFSP1_3   
+_WDWORD(0x40086094, 0x00000073);   // CS0, SFSP1_5    
+_WDWORD(0x40086098, 0x00000073);   // WE,  SFSP1_6   
+
+// enable CS0 and setup the timing
+// 90ns 32-bit Flash on CS0  
+_WDWORD(0x40005000, 0x00000001);   // Enable
+_WDWORD(0x40005200, 0x00000082);   // CS0: 32 bit, WE 
+_WDWORD(0x40005208, 0x00000002);   // CS0: WAITOEN = 2
+_WDWORD(0x4000520C, 0x0000000C);   // CS0: WAITRD  = 12

CMSIS/Pack/Example/Boards/Keil/MCB1800/Blinky/RTE/Device/LPC1857/RTE_Device.h

@@ -0,0 +1,2358 @@
+/* -----------------------------------------------------------------------------
+ * Copyright (c) 2013-2015 ARM Ltd.
+ *
+ * This software is provided 'as-is', without any express or implied warranty.
+ * In no event will the authors be held liable for any damages arising from
+ * the use of this software. Permission is granted to anyone to use this
+ * software for any purpose, including commercial applications, and to alter
+ * it and redistribute it freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software in
+ *    a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ *
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ *
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * $Date:        5. March 2015
+ * $Revision:    V2.1.1
+ *
+ * Project:      RTE Device Configuration for NXP LPC18xx
+ * -------------------------------------------------------------------------- */
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+#ifndef __RTE_DEVICE_H
+#define __RTE_DEVICE_H
+
+
+// <e> USB0 Controller [Driver_USBD0 and Driver_USBH0]
+// <i> Configuration settings for Driver_USBD0 in component ::Drivers:USB Device
+// <i> Configuration settings for Driver_USBH0 in component ::Drivers:USB Host
+#define   RTE_USB_USB0                  0
+
+//   <h> Pin Configuration
+//     <o> USB0_PPWR (Host) <0=>Not used <1=>P1_7 <2=>P2_0 <3=>P2_3 <4=>P6_3
+//     <i> VBUS drive signal (towards external charge pump or power management unit).
+#define   RTE_USB0_PPWR_ID              4
+#if      (RTE_USB0_PPWR_ID == 0)
+  #define RTE_USB0_PPWR_PIN_EN          0
+#elif    (RTE_USB0_PPWR_ID == 1)
+  #define RTE_USB0_PPWR_PORT            1
+  #define RTE_USB0_PPWR_BIT             7
+  #define RTE_USB0_PPWR_FUNC            4
+#elif    (RTE_USB0_PPWR_ID == 2)
+  #define RTE_USB0_PPWR_PORT            2
+  #define RTE_USB0_PPWR_BIT             0
+  #define RTE_USB0_PPWR_FUNC            3
+#elif    (RTE_USB0_PPWR_ID == 3)
+  #define RTE_USB0_PPWR_PORT            2
+  #define RTE_USB0_PPWR_BIT             3
+  #define RTE_USB0_PPWR_FUNC            7
+#elif    (RTE_USB0_PPWR_ID == 4)
+  #define RTE_USB0_PPWR_PORT            6
+  #define RTE_USB0_PPWR_BIT             3
+  #define RTE_USB0_PPWR_FUNC            1
+#else
+  #error "Invalid RTE_USB0_PPWR Pin Configuration!"
+#endif
+#ifndef   RTE_USB0_PPWR_PIN_EN
+  #define RTE_USB0_PPWR_PIN_EN          1
+#endif
+//     <o> USB0_PWR_FAULT (Host) <0=>Not used <1=>P1_5 <2=>P2_1 <3=>P2_4 <4=>P6_6 <5=>P8_0
+//     <i> Port power fault signal indicating overcurrent condition.
+//     <i> This signal monitors over-current on the USB bus
+//        (external circuitry required to detect over-current condition).
+#define   RTE_USB0_PWR_FAULT_ID         4
+#if      (RTE_USB0_PWR_FAULT_ID == 0)
+  #define RTE_USB0_PWR_FAULT_PIN_EN     0
+#elif    (RTE_USB0_PWR_FAULT_ID == 1)
+  #define RTE_USB0_PWR_FAULT_PORT       1
+  #define RTE_USB0_PWR_FAULT_BIT        5
+  #define RTE_USB0_PWR_FAULT_FUNC       4
+#elif    (RTE_USB0_PWR_FAULT_ID == 2)
+  #define RTE_USB0_PWR_FAULT_PORT       2
+  #define RTE_USB0_PWR_FAULT_BIT        1
+  #define RTE_USB0_PWR_FAULT_FUNC       3
+#elif    (RTE_USB0_PWR_FAULT_ID == 3)
+  #define RTE_USB0_PWR_FAULT_PORT       2
+  #define RTE_USB0_PWR_FAULT_BIT        4
+  #define RTE_USB0_PWR_FAULT_FUNC       7
+#elif    (RTE_USB0_PWR_FAULT_ID == 4)
+  #define RTE_USB0_PWR_FAULT_PORT       6
+  #define RTE_USB0_PWR_FAULT_BIT        6
+  #define RTE_USB0_PWR_FAULT_FUNC       3
+#elif    (RTE_USB0_PWR_FAULT_ID == 5)
+  #define RTE_USB0_PWR_FAULT_PORT       8
+  #define RTE_USB0_PWR_FAULT_BIT        0
+  #define RTE_USB0_PWR_FAULT_FUNC       1
+#else
+  #error "Invalid RTE_USB0_PWR_FAULT Pin Configuration!"
+#endif
+#ifndef   RTE_USB0_PWR_FAULT_PIN_EN
+  #define RTE_USB0_PWR_FAULT_PIN_EN     1
+#endif
+//     <o> USB0_IND0 <0=>Not used <1=>P1_4 <2=>P2_5 <3=>P2_6 <4=>P6_8 <5=>P8_2
+//     <i> USB0 port indicator LED control output 0
+#define   RTE_USB0_IND0_ID              5
+#if      (RTE_USB0_IND0_ID == 0)
+  #define RTE_USB0_IND0_PIN_EN          0
+#elif    (RTE_USB0_IND0_ID == 1)
+  #define RTE_USB0_IND0_PORT            1
+  #define RTE_USB0_IND0_BIT             4
+  #define RTE_USB0_IND0_FUNC            4
+#elif    (RTE_USB0_IND0_ID == 2)
+  #define RTE_USB0_IND0_PORT            2
+  #define RTE_USB0_IND0_BIT             5
+  #define RTE_USB0_IND0_FUNC            7
+#elif    (RTE_USB0_IND0_ID == 3)
+  #define RTE_USB0_IND0_PORT            2
+  #define RTE_USB0_IND0_BIT             6
+  #define RTE_USB0_IND0_FUNC            3
+#elif    (RTE_USB0_IND0_ID == 4)
+  #define RTE_USB0_IND0_PORT            6
+  #define RTE_USB0_IND0_BIT             8
+  #define RTE_USB0_IND0_FUNC            3
+#elif    (RTE_USB0_IND0_ID == 5)
+  #define RTE_USB0_IND0_PORT            8
+  #define RTE_USB0_IND0_BIT             2
+  #define RTE_USB0_IND0_FUNC            1
+#else
+  #error "Invalid RTE_USB0_IND0 Pin Configuration!"
+#endif
+#ifndef   RTE_USB0_IND0_PIN_EN
+  #define RTE_USB0_IND0_PIN_EN          1
+#endif
+//     <o> USB0_IND1 <0=>Not used <1=>P1_3 <2=>P2_2 <3=>P6_7 <4=>P8_1
+//     <i> USB0 port indicator LED control output 1
+#define   RTE_USB0_IND1_ID              4
+#if      (RTE_USB0_IND1_ID == 0)
+  #define RTE_USB0_IND1_PIN_EN          0
+#elif    (RTE_USB0_IND1_ID == 1)
+  #define RTE_USB0_IND1_PORT            1
+  #define RTE_USB0_IND1_BIT             3
+  #define RTE_USB0_IND1_FUNC            4
+#elif    (RTE_USB0_IND1_ID == 2)
+  #define RTE_USB0_IND1_PORT            2
+  #define RTE_USB0_IND1_BIT             2
+  #define RTE_USB0_IND1_FUNC            3
+#elif    (RTE_USB0_IND1_ID == 3)
+  #define RTE_USB0_IND1_PORT            6
+  #define RTE_USB0_IND1_BIT             7
+  #define RTE_USB0_IND1_FUNC            3
+#elif    (RTE_USB0_IND1_ID == 4)
+  #define RTE_USB0_IND1_PORT            8
+  #define RTE_USB0_IND1_BIT             1
+  #define RTE_USB0_IND1_FUNC            1
+#else
+  #error "Invalid RTE_USB0_IND1 Pin Configuration!"
+#endif
+#ifndef   RTE_USB0_IND1_PIN_EN
+  #define RTE_USB0_IND1_PIN_EN          1
+#endif
+//   </h> Pin Configuration
+
+//   <h> Device [Driver_USBD0]
+//   <i> Configuration settings for Driver_USBD0 in component ::Drivers:USB Device
+//     <o.0> High-speed
+//     <i> Enable high-speed functionality
+#define   RTE_USB_USB0_HS_EN            1
+//   </h> Device [Driver_USBD0]
+// </e> USB0 Controller [Driver_USBD0 and Driver_USBH0]
+
+// <e> USB1 Controller [Driver_USBD1 and Driver_USBH1]
+// <i> Configuration settings for Driver_USBD1 in component ::Drivers:USB Device
+// <i> Configuration settings for Driver_USBH1 in component ::Drivers:USB Host
+#define   RTE_USB_USB1                  0
+
+//   <h> Pin Configuration
+//     <o> USB1_PPWR (Host) <0=>Not used <1=>P9_5
+//     <i> VBUS drive signal (towards external charge pump or power management unit).
+#define   RTE_USB1_PPWR_ID              1
+#if      (RTE_USB1_PPWR_ID == 0)
+  #define RTE_USB1_PPWR_PIN_EN          0
+#elif    (RTE_USB1_PPWR_ID == 1)
+  #define RTE_USB1_PPWR_PORT            9
+  #define RTE_USB1_PPWR_BIT             5
+  #define RTE_USB1_PPWR_FUNC            2
+#else
+  #error "Invalid RTE_USB1_PPWR Pin Configuration!"
+#endif
+#ifndef   RTE_USB1_PPWR_PIN_EN
+  #define RTE_USB1_PPWR_PIN_EN          1
+#endif
+//     <o> USB1_PWR_FAULT (Host) <0=>Not used <1=>P9_6
+//     <i> Port power fault signal indicating overcurrent condition.
+//     <i> This signal monitors over-current on the USB bus
+//        (external circuitry required to detect over-current condition).
+#define   RTE_USB1_PWR_FAULT_ID         1
+#if      (RTE_USB1_PWR_FAULT_ID == 0)
+  #define RTE_USB1_PWR_FAULT_PIN_EN     0
+#elif    (RTE_USB1_PWR_FAULT_ID == 1)
+  #define RTE_USB1_PWR_FAULT_PORT       9
+  #define RTE_USB1_PWR_FAULT_BIT        6
+  #define RTE_USB1_PWR_FAULT_FUNC       2
+#else
+  #error "Invalid RTE_USB1_PWR_FAULT Pin Configuration!"
+#endif
+#ifndef   RTE_USB1_PWR_FAULT_PIN_EN
+  #define RTE_USB1_PWR_FAULT_PIN_EN     1
+#endif
+//     <o> USB1_IND0 <0=>Not used <1=>P3_2 <2=>P9_4
+//     <i> USB1 port indicator LED control output 0
+#define   RTE_USB1_IND0_ID              2
+#if      (RTE_USB1_IND0_ID == 0)
+  #define RTE_USB1_IND0_PIN_EN          0
+#elif    (RTE_USB1_IND0_ID == 1)
+  #define RTE_USB1_IND0_PORT            3
+  #define RTE_USB1_IND0_BIT             2
+  #define RTE_USB1_IND0_FUNC            3
+#elif    (RTE_USB1_IND0_ID == 2)
+  #define RTE_USB1_IND0_PORT            9
+  #define RTE_USB1_IND0_BIT             4
+  #define RTE_USB1_IND0_FUNC            2
+#else
+  #error "Invalid RTE_USB1_IND0 Pin Configuration!"
+#endif
+#ifndef   RTE_USB1_IND0_PIN_EN
+  #define RTE_USB1_IND0_PIN_EN          1
+#endif
+//     <o> USB1_IND1 <0=>Not used <1=>P3_1 <2=>P9_3
+//     <i> USB1 port indicator LED control output 1
+#define   RTE_USB1_IND1_ID              2
+#if      (RTE_USB1_IND1_ID == 0)
+  #define RTE_USB1_IND1_PIN_EN          0
+#elif    (RTE_USB1_IND1_ID == 1)
+  #define RTE_USB1_IND1_PORT            3
+  #define RTE_USB1_IND1_BIT             1
+  #define RTE_USB1_IND1_FUNC            3
+#elif    (RTE_USB1_IND1_ID == 2)
+  #define RTE_USB1_IND1_PORT            9
+  #define RTE_USB1_IND1_BIT             3
+  #define RTE_USB1_IND1_FUNC            2
+#else
+  #error "Invalid RTE_USB1_IND1 Pin Configuration!"
+#endif
+#ifndef   RTE_USB1_IND1_PIN_EN
+  #define RTE_USB1_IND1_PIN_EN          1
+#endif
+
+//     <e> On-chip full-speed PHY
+#define   RTE_USB_USB1_FS_PHY_EN        1
+
+//       <o> USB1_VBUS (Device) <0=>Not used <1=>P2_5
+//       <i> Monitors the presence of USB1 bus power.
+#define   RTE_USB1_VBUS_ID              1
+#if      (RTE_USB1_VBUS_ID == 0)
+  #define RTE_USB1_VBUS_PIN_EN          0
+#elif    (RTE_USB1_VBUS_ID == 1)
+  #define RTE_USB1_VBUS_PORT            2
+  #define RTE_USB1_VBUS_BIT             5
+  #define RTE_USB1_VBUS_FUNC            2
+#else
+  #error "Invalid RTE_USB1_VBUS Pin Configuration!"
+#endif
+#ifndef   RTE_USB1_VBUS_PIN_EN
+  #define RTE_USB1_VBUS_PIN_EN          1
+#endif
+//     </e> On-chip full-speed PHY
+
+//     <e> External high-speed ULPI PHY (UTMI+ Low Pin Interface)
+#define   RTE_USB_USB1_HS_PHY_EN        0
+
+//       <o> USB1_ULPI_CLK <0=>P8_8 <1=>PC_0
+//       <i> USB1 ULPI link CLK signal.
+//       <i> 60 MHz clock generated by the PHY.
+#define   RTE_USB1_ULPI_CLK_ID          0
+#if      (RTE_USB1_ULPI_CLK_ID == 0)
+  #define RTE_USB1_ULPI_CLK_PORT        8
+  #define RTE_USB1_ULPI_CLK_BIT         8
+  #define RTE_USB1_ULPI_CLK_FUNC        1
+#elif    (RTE_USB1_ULPI_CLK_ID == 1)
+  #define RTE_USB1_ULPI_CLK_PORT        0xC
+  #define RTE_USB1_ULPI_CLK_BIT         0
+  #define RTE_USB1_ULPI_CLK_FUNC        1
+#else
+  #error "Invalid RTE_USB1_ULPI_CLK Pin Configuration!"
+#endif
+//       <o> USB1_ULPI_DIR <0=>PB_1 <1=>PC_11
+//       <i> USB1 ULPI link DIR signal.
+//       <i> Controls the ULPI data line direction.
+#define   RTE_USB1_ULPI_DIR_ID          0
+#if      (RTE_USB1_ULPI_DIR_ID == 0)
+  #define RTE_USB1_ULPI_DIR_PORT        0xB
+  #define RTE_USB1_ULPI_DIR_BIT         1
+  #define RTE_USB1_ULPI_DIR_FUNC        1
+#elif    (RTE_USB1_ULPI_DIR_ID == 1)
+  #define RTE_USB1_ULPI_DIR_PORT        0xC
+  #define RTE_USB1_ULPI_DIR_BIT         11
+  #define RTE_USB1_ULPI_DIR_FUNC        1
+#else
+  #error "Invalid RTE_USB1_ULPI_DIR Pin Configuration!"
+#endif
+//       <o> USB1_ULPI_STP <0=>P8_7 <1=>PC_10
+//       <i> USB1 ULPI link STP signal.
+//       <i> Asserted to end or interrupt transfers to the PHY.
+#define   RTE_USB1_ULPI_STP_ID          0
+#if      (RTE_USB1_ULPI_STP_ID == 0)
+  #define RTE_USB1_ULPI_STP_PORT        8
+  #define RTE_USB1_ULPI_STP_BIT         7
+  #define RTE_USB1_ULPI_STP_FUNC        1
+#elif    (RTE_USB1_ULPI_STP_ID == 1)
+  #define RTE_USB1_ULPI_STP_PORT        0xC
+  #define RTE_USB1_ULPI_STP_BIT         10
+  #define RTE_USB1_ULPI_STP_FUNC        1
+#else
+  #error "Invalid RTE_USB1_ULPI_STP Pin Configuration!"
+#endif
+//       <o> USB1_ULPI_NXT <0=>P8_6 <1=>PC_9
+//       <i> USB1 ULPI link NXT signal.
+//       <i> Data flow control signal from the PHY.
+#define   RTE_USB1_ULPI_NXT_ID          0
+#if      (RTE_USB1_ULPI_NXT_ID == 0)
+  #define RTE_USB1_ULPI_NXT_PORT        8
+  #define RTE_USB1_ULPI_NXT_BIT         6
+  #define RTE_USB1_ULPI_NXT_FUNC        1
+#elif    (RTE_USB1_ULPI_NXT_ID == 1)
+  #define RTE_USB1_ULPI_NXT_PORT        0xC
+  #define RTE_USB1_ULPI_NXT_BIT         9
+  #define RTE_USB1_ULPI_NXT_FUNC        1
+#else
+  #error "Invalid RTE_USB1_ULPI_NXT Pin Configuration!"
+#endif
+//       <o> USB1_ULPI_D0 <0=>P8_5 <1=>PC_8 <2=>PD_11
+//       <i> USB1 ULPI link bidirectional data line 0.
+#define   RTE_USB1_ULPI_D0_ID           0
+#if      (RTE_USB1_ULPI_D0_ID == 0)
+  #define RTE_USB1_ULPI_D0_PORT         8
+  #define RTE_USB1_ULPI_D0_BIT          5
+  #define RTE_USB1_ULPI_D0_FUNC         1
+#elif    (RTE_USB1_ULPI_D0_ID == 1)
+  #define RTE_USB1_ULPI_D0_PORT         0xC
+  #define RTE_USB1_ULPI_D0_BIT          8
+  #define RTE_USB1_ULPI_D0_FUNC         1
+#elif    (RTE_USB1_ULPI_D0_ID == 2)
+  #define RTE_USB1_ULPI_D0_PORT         0xD
+  #define RTE_USB1_ULPI_D0_BIT          11
+  #define RTE_USB1_ULPI_D0_FUNC         5
+#else
+  #error "Invalid RTE_USB1_ULPI_D0 Pin Configuration!"
+#endif
+//       <o> USB1_ULPI_D1 <0=>P8_4 <1=>PC_7
+//       <i> USB1 ULPI link bidirectional data line 1.
+#define   RTE_USB1_ULPI_D1_ID           0
+#if      (RTE_USB1_ULPI_D1_ID == 0)
+  #define RTE_USB1_ULPI_D1_PORT         8
+  #define RTE_USB1_ULPI_D1_BIT          4
+  #define RTE_USB1_ULPI_D1_FUNC         1
+#elif    (RTE_USB1_ULPI_D1_ID == 1)
+  #define RTE_USB1_ULPI_D1_PORT         0xC
+  #define RTE_USB1_ULPI_D1_BIT          7
+  #define RTE_USB1_ULPI_D1_FUNC         1
+#else
+  #error "Invalid RTE_USB1_ULPI_D1 Pin Configuration!"
+#endif
+//       <o> USB1_ULPI_D2 <0=>P8_3 <1=>PC_6
+//       <i> USB1 ULPI link bidirectional data line 2.
+#define   RTE_USB1_ULPI_D2_ID           0
+#if      (RTE_USB1_ULPI_D2_ID == 0)
+  #define RTE_USB1_ULPI_D2_PORT         8
+  #define RTE_USB1_ULPI_D2_BIT          3
+  #define RTE_USB1_ULPI_D2_FUNC         1
+#elif    (RTE_USB1_ULPI_D2_ID == 1)
+  #define RTE_USB1_ULPI_D2_PORT         0xC
+  #define RTE_USB1_ULPI_D2_BIT          6
+  #define RTE_USB1_ULPI_D2_FUNC         1
+#else
+  #error "Invalid RTE_USB1_ULPI_D2 Pin Configuration!"
+#endif
+//       <o> USB1_ULPI_D3 <0=>PB_6 <1=>PC_5
+//       <i> USB1 ULPI link bidirectional data line 3.
+#define   RTE_USB1_ULPI_D3_ID           0
+#if      (RTE_USB1_ULPI_D3_ID == 0)
+  #define RTE_USB1_ULPI_D3_PORT         0xB
+  #define RTE_USB1_ULPI_D3_BIT          6
+  #define RTE_USB1_ULPI_D3_FUNC         1
+#elif    (RTE_USB1_ULPI_D3_ID == 1)
+  #define RTE_USB1_ULPI_D3_PORT         0xC
+  #define RTE_USB1_ULPI_D3_BIT          5
+  #define RTE_USB1_ULPI_D3_FUNC         1
+#else
+  #error "Invalid RTE_USB1_ULPI_D3 Pin Configuration!"
+#endif
+//       <o> USB1_ULPI_D4 <0=>PB_5 <1=>PC_4
+//       <i> USB1 ULPI link bidirectional data line 4.
+#define   RTE_USB1_ULPI_D4_ID           0
+#if      (RTE_USB1_ULPI_D4_ID == 0)
+  #define RTE_USB1_ULPI_D4_PORT         0xB
+  #define RTE_USB1_ULPI_D4_BIT          5
+  #define RTE_USB1_ULPI_D4_FUNC         1
+#elif    (RTE_USB1_ULPI_D4_ID == 1)
+  #define RTE_USB1_ULPI_D4_PORT         0xC
+  #define RTE_USB1_ULPI_D4_BIT          4
+  #define RTE_USB1_ULPI_D4_FUNC         1
+#else
+  #error "Invalid RTE_USB1_ULPI_D4 Pin Configuration!"
+#endif
+//       <o> USB1_ULPI_D5 <0=>PB_4 <1=>PC_3
+//       <i> USB1 ULPI link bidirectional data line 5.
+#define   RTE_USB1_ULPI_D5_ID           0
+#if      (RTE_USB1_ULPI_D5_ID == 0)
+  #define RTE_USB1_ULPI_D5_PORT         0xB
+  #define RTE_USB1_ULPI_D5_BIT          4
+  #define RTE_USB1_ULPI_D5_FUNC         1
+#elif    (RTE_USB1_ULPI_D5_ID == 1)
+  #define RTE_USB1_ULPI_D5_PORT         0xC
+  #define RTE_USB1_ULPI_D5_BIT          3
+  #define RTE_USB1_ULPI_D5_FUNC         0
+#else
+  #error "Invalid RTE_USB1_ULPI_D5 Pin Configuration!"
+#endif
+//       <o> USB1_ULPI_D6 <0=>PB_3 <1=>PC_2
+//       <i> USB1 ULPI link bidirectional data line 6.
+#define   RTE_USB1_ULPI_D6_ID           0
+#if      (RTE_USB1_ULPI_D6_ID == 0)
+  #define RTE_USB1_ULPI_D6_PORT         0xB
+  #define RTE_USB1_ULPI_D6_BIT          3
+  #define RTE_USB1_ULPI_D6_FUNC         1
+#elif    (RTE_USB1_ULPI_D6_ID == 1)
+  #define RTE_USB1_ULPI_D6_PORT         0xC
+  #define RTE_USB1_ULPI_D6_BIT          2
+  #define RTE_USB1_ULPI_D6_FUNC         0
+#else
+  #error "Invalid RTE_USB1_ULPI_D6 Pin Configuration!"
+#endif
+//       <o> USB1_ULPI_D7 <0=>PB_2 <1=>PC_1
+//       <i> USB1 ULPI link bidirectional data line 7.
+#define   RTE_USB1_ULPI_D7_ID           0
+#if      (RTE_USB1_ULPI_D7_ID == 0)
+  #define RTE_USB1_ULPI_D7_PORT         0xB
+  #define RTE_USB1_ULPI_D7_BIT          2
+  #define RTE_USB1_ULPI_D7_FUNC         1
+#elif    (RTE_USB1_ULPI_D7_ID == 1)
+  #define RTE_USB1_ULPI_D7_PORT         0xC
+  #define RTE_USB1_ULPI_D7_BIT          1
+  #define RTE_USB1_ULPI_D7_FUNC         0
+#else
+  #error "Invalid RTE_USB1_ULPI_D7 Pin Configuration!"
+#endif
+//     </e> External high-speed ULPI PHY (UTMI+ Low Pin Interface)
+//   </h> Pin Configuration
+// </e> USB1 Controller [Driver_USBD1 and Driver_USBH1]
+
+// <e> ENET (Ethernet Interface) [Driver_ETH_MAC0]
+// <i> Configuration settings for Driver_ETH_MAC0 in component ::Drivers:Ethernet MAC
+#define   RTE_ENET                      0
+
+//   <e> MII (Media Independent Interface)
+#define   RTE_ENET_MII                  0
+
+//     <o> ENET_TXD0 Pin <0=>P1_18
+#define   RTE_ENET_MII_TXD0_PORT_ID     0
+#if      (RTE_ENET_MII_TXD0_PORT_ID == 0)
+  #define RTE_ENET_MII_TXD0_PORT        1
+  #define RTE_ENET_MII_TXD0_PIN         18
+  #define RTE_ENET_MII_TXD0_FUNC        3
+#else
+  #error "Invalid ENET_TXD0 Pin Configuration!"
+#endif
+//     <o> ENET_TXD1 Pin <0=>P1_20
+#define   RTE_ENET_MII_TXD1_PORT_ID     0
+#if      (RTE_ENET_MII_TXD1_PORT_ID == 0)
+  #define RTE_ENET_MII_TXD1_PORT        1
+  #define RTE_ENET_MII_TXD1_PIN         20
+  #define RTE_ENET_MII_TXD1_FUNC        3
+#else
+  #error "Invalid ENET_TXD1 Pin Configuration!"
+#endif
+//     <o> ENET_TXD2 Pin <0=>P9_4 <1=>PC_2
+#define   RTE_ENET_MII_TXD2_PORT_ID     0
+#if      (RTE_ENET_MII_TXD2_PORT_ID == 0)
+  #define RTE_ENET_MII_TXD2_PORT        9
+  #define RTE_ENET_MII_TXD2_PIN         4
+  #define RTE_ENET_MII_TXD2_FUNC        5
+#elif    (RTE_ENET_MII_TXD2_PORT_ID == 1)
+  #define RTE_ENET_MII_TXD2_PORT        0xC
+  #define RTE_ENET_MII_TXD2_PIN         2
+  #define RTE_ENET_MII_TXD2_FUNC        3
+#else
+  #error "Invalid ENET_TXD2 Pin Configuration!"
+#endif
+//     <o> ENET_TXD3 Pin <0=>P9_5 <1=>PC_3
+#define   RTE_ENET_MII_TXD3_PORT_ID     0
+#if      (RTE_ENET_MII_TXD3_PORT_ID == 0)
+  #define RTE_ENET_MII_TXD3_PORT        9
+  #define RTE_ENET_MII_TXD3_PIN         5
+  #define RTE_ENET_MII_TXD3_FUNC        5
+#elif    (RTE_ENET_MII_TXD3_PORT_ID == 1)
+  #define RTE_ENET_MII_TXD3_PORT        0xC
+  #define RTE_ENET_MII_TXD3_PIN         3
+  #define RTE_ENET_MII_TXD3_FUNC        3
+#else
+  #error "Invalid ENET_TXD3 Pin Configuration!"
+#endif
+//     <o> ENET_TX_EN Pin <0=>P0_1 <1=>PC_4
+#define   RTE_ENET_MII_TX_EN_PORT_ID    0
+#if      (RTE_ENET_MII_TX_EN_PORT_ID == 0)
+  #define RTE_ENET_MII_TX_EN_PORT       0
+  #define RTE_ENET_MII_TX_EN_PIN        1
+  #define RTE_ENET_MII_TX_EN_FUNC       6
+#elif    (RTE_ENET_MII_TX_EN_PORT_ID == 1)
+  #define RTE_ENET_MII_TX_EN_PORT       0xC
+  #define RTE_ENET_MII_TX_EN_PIN        4
+  #define RTE_ENET_MII_TX_EN_FUNC       3
+#else
+  #error "Invalid ENET_TX_EN Pin Configuration!"
+#endif
+//     <o> ENET_TX_CLK Pin <0=>P1_19 <1=>CLK0
+#define   RTE_ENET_MII_TX_CLK_PORT_ID   0
+#if      (RTE_ENET_MII_TX_CLK_PORT_ID == 0)
+  #define RTE_ENET_MII_TX_CLK_PORT      1
+  #define RTE_ENET_MII_TX_CLK_PIN       19
+  #define RTE_ENET_MII_TX_CLK_FUNC      0
+#elif    (RTE_ENET_MII_TX_CLK_PORT_ID == 1)
+  #define RTE_ENET_MII_TX_CLK_PORT      0x10
+  #define RTE_ENET_MII_TX_CLK_PIN       0
+  #define RTE_ENET_MII_TX_CLK_FUNC      7
+#else
+  #error "Invalid ENET_TX_CLK Pin Configuration!"
+#endif
+//     <o> ENET_TX_ER Pin <0=>Not used <1=>PC_5 <2=>PC_14
+//     <i> Optional signal, rarely used
+#define   RTE_ENET_MII_TX_ER_PORT_ID    0
+#if      (RTE_ENET_MII_TX_ER_PORT_ID == 0)
+  #define RTE_ENET_MII_TX_ER_PIN_EN     0
+#elif    (RTE_ENET_MII_TX_ER_PORT_ID == 1)
+  #define RTE_ENET_MII_TX_ER_PORT       0xC
+  #define RTE_ENET_MII_TX_ER_PIN        5
+  #define RTE_ENET_MII_TX_ER_FUNC       3
+#elif    (RTE_ENET_MII_TX_ER_PORT_ID == 2)
+  #define RTE_ENET_MII_TX_ER_PORT       0xC
+  #define RTE_ENET_MII_TX_ER_PIN        14
+  #define RTE_ENET_MII_TX_ER_FUNC       6
+#else
+  #error "Invalid ENET_TX_ER Pin Configuration!"
+#endif
+#ifndef   RTE_ENET_MII_TX_ER_PIN_EN
+  #define RTE_ENET_MII_TX_ER_PIN_EN     1
+#endif
+//     <o> ENET_RXD0 Pin <0=>P1_15
+#define   RTE_ENET_MII_RXD0_PORT_ID     0
+#if      (RTE_ENET_MII_RXD0_PORT_ID == 0)
+  #define RTE_ENET_MII_RXD0_PORT        1
+  #define RTE_ENET_MII_RXD0_PIN         15
+  #define RTE_ENET_MII_RXD0_FUNC        3
+#else
+  #error "Invalid ENET_RXD0 Pin Configuration!"
+#endif
+//     <o> ENET_RXD1 Pin <0=>P0_0
+#define   RTE_ENET_MII_RXD1_PORT_ID     0
+#if      (RTE_ENET_MII_RXD1_PORT_ID == 0)
+  #define RTE_ENET_MII_RXD1_PORT        0
+  #define RTE_ENET_MII_RXD1_PIN         0
+  #define RTE_ENET_MII_RXD1_FUNC        2
+#else
+  #error "Invalid ENET_RXD1 Pin Configuration!"
+#endif
+//     <o> ENET_RXD2 Pin <0=>P9_3 <1=>PC_6
+#define   RTE_ENET_MII_RXD2_PORT_ID     0
+#if      (RTE_ENET_MII_RXD2_PORT_ID == 0)
+  #define RTE_ENET_MII_RXD2_PORT        9
+  #define RTE_ENET_MII_RXD2_PIN         3
+  #define RTE_ENET_MII_RXD2_FUNC        5
+#elif    (RTE_ENET_MII_RXD2_PORT_ID == 1)
+  #define RTE_ENET_MII_RXD2_PORT        0xC
+  #define RTE_ENET_MII_RXD2_PIN         6
+  #define RTE_ENET_MII_RXD2_FUNC        3
+#else
+  #error "Invalid ENET_RXD2 Pin Configuration!"
+#endif
+//     <o> ENET_RXD3 Pin <0=>P9_2 <1=>PC_7
+#define   RTE_ENET_MII_RXD3_PORT_ID     0
+#if      (RTE_ENET_MII_RXD3_PORT_ID == 0)
+  #define RTE_ENET_MII_RXD3_PORT        9
+  #define RTE_ENET_MII_RXD3_PIN         2
+  #define RTE_ENET_MII_RXD3_FUNC        5
+#elif    (RTE_ENET_MII_RXD3_PORT_ID == 1)
+  #define RTE_ENET_MII_RXD3_PORT        0xC
+  #define RTE_ENET_MII_RXD3_PIN         7
+  #define RTE_ENET_MII_RXD3_FUNC        3
+#else
+  #error "Invalid ENET_RXD3 Pin Configuration!"
+#endif
+//     <o> ENET_RX_DV Pin <0=>P1_16 <1=>PC_8
+#define   RTE_ENET_MII_RX_DV_PORT_ID    0
+#if      (RTE_ENET_MII_RX_DV_PORT_ID == 0)
+  #define RTE_ENET_MII_RX_DV_PORT       1
+  #define RTE_ENET_MII_RX_DV_PIN        16
+  #define RTE_ENET_MII_RX_DV_FUNC       7
+#elif    (RTE_ENET_MII_RX_DV_PORT_ID == 1)
+  #define RTE_ENET_MII_RX_DV_PORT       0xC
+  #define RTE_ENET_MII_RX_DV_PIN        8
+  #define RTE_ENET_MII_RX_DV_FUNC       3
+#else
+  #error "Invalid ENET_RX_DV Pin Configuration!"
+#endif
+//     <o> ENET_RX_CLK Pin <0=>PC_0
+#define   RTE_ENET_MII_RX_CLK_PORT_ID   0
+#if      (RTE_ENET_MII_RX_CLK_PORT_ID == 0)
+  #define RTE_ENET_MII_RX_CLK_PORT      0xC
+  #define RTE_ENET_MII_RX_CLK_PIN       0
+  #define RTE_ENET_MII_RX_CLK_FUNC      3
+#else
+  #error "Invalid ENET_RX_CLK Pin Configuration!"
+#endif
+//     <o> ENET_RX_ER Pin <0=>P9_1 <1=>PC_9
+#define   RTE_ENET_MII_RX_ER_PORT_ID    0
+#if      (RTE_ENET_MII_RX_ER_PORT_ID == 0)
+  #define RTE_ENET_MII_RX_ER_PORT       9
+  #define RTE_ENET_MII_RX_ER_PIN        1
+  #define RTE_ENET_MII_RX_ER_FUNC       5
+#elif    (RTE_ENET_MII_RX_ER_PORT_ID == 1)
+  #define RTE_ENET_MII_RX_ER_PORT       0xC
+  #define RTE_ENET_MII_RX_ER_PIN        9
+  #define RTE_ENET_MII_RX_ER_FUNC       3
+#else
+  #error "Invalid ENET_RX_ER Pin Configuration!"
+#endif
+//     <o> ENET_COL Pin <0=>P0_1 <1=>P4_1 <2=>P9_6
+#define   RTE_ENET_MII_COL_PORT_ID      0
+#if      (RTE_ENET_MII_COL_PORT_ID == 0)
+  #define RTE_ENET_MII_COL_PORT         0
+  #define RTE_ENET_MII_COL_PIN          1
+  #define RTE_ENET_MII_COL_FUNC         2
+#elif    (RTE_ENET_MII_COL_PORT_ID == 1)
+  #define RTE_ENET_MII_COL_PORT         4
+  #define RTE_ENET_MII_COL_PIN          1
+  #define RTE_ENET_MII_COL_FUNC         7
+#elif    (RTE_ENET_MII_COL_PORT_ID == 2)
+  #define RTE_ENET_MII_COL_PORT         9
+  #define RTE_ENET_MII_COL_PIN          6
+  #define RTE_ENET_MII_COL_FUNC         5
+#else
+  #error "Invalid ENET_COL Pin Configuration!"
+#endif
+//     <o> ENET_CRS Pin <0=>P1_16 <1=>P9_0
+#define   RTE_ENET_MII_CRS_PORT_ID      0
+#if      (RTE_ENET_MII_CRS_PORT_ID == 0)
+  #define RTE_ENET_MII_CRS_PORT         1
+  #define RTE_ENET_MII_CRS_PIN          16
+  #define RTE_ENET_MII_CRS_FUNC         3
+#elif    (RTE_ENET_MII_CRS_PORT_ID == 1)
+  #define RTE_ENET_MII_CRS_PORT         9
+  #define RTE_ENET_MII_CRS_PIN          0
+  #define RTE_ENET_MII_CRS_FUNC         5
+#else
+  #error "Invalid ENET_CRS Pin Configuration!"
+#endif
+//   </e> MII (Media Independent Interface)
+
+//   <e> RMII (Reduced Media Independent Interface)
+#define   RTE_ENET_RMII                 1
+
+//     <o> ENET_TXD0 Pin <0=>P1_18
+#define   RTE_ENET_RMII_TXD0_PORT_ID    0
+#if      (RTE_ENET_RMII_TXD0_PORT_ID == 0)
+  #define RTE_ENET_RMII_TXD0_PORT       1
+  #define RTE_ENET_RMII_TXD0_PIN        18
+  #define RTE_ENET_RMII_TXD0_FUNC       3
+#else
+  #error "Invalid ENET_TXD0 Pin Configuration!"
+#endif
+//     <o> ENET_TXD1 Pin <0=>P1_20
+#define   RTE_ENET_RMII_TXD1_PORT_ID    0
+#if      (RTE_ENET_RMII_TXD1_PORT_ID == 0)
+  #define RTE_ENET_RMII_TXD1_PORT       1
+  #define RTE_ENET_RMII_TXD1_PIN        20
+  #define RTE_ENET_RMII_TXD1_FUNC       3
+#else
+  #error "Invalid ENET_TXD1 Pin Configuration!"
+#endif
+//     <o> ENET_TX_EN Pin <0=>P0_1 <1=>PC_4
+#define   RTE_ENET_RMII_TX_EN_PORT_ID   0
+#if      (RTE_ENET_RMII_TX_EN_PORT_ID == 0)
+  #define RTE_ENET_RMII_TX_EN_PORT      0
+  #define RTE_ENET_RMII_TX_EN_PIN       1
+  #define RTE_ENET_RMII_TX_EN_FUNC      6
+#elif    (RTE_ENET_RMII_TX_EN_PORT_ID == 1)
+  #define RTE_ENET_RMII_TX_EN_PORT      0xC
+  #define RTE_ENET_RMII_TX_EN_PIN       4
+  #define RTE_ENET_RMII_TX_EN_FUNC      3
+#else
+  #error "Invalid ENET_TX_EN Pin Configuration!"
+#endif
+//     <o> ENET_REF_CLK Pin <0=>P1_19 <1=>CLK0
+#define   RTE_ENET_RMII_REF_CLK_PORT_ID 0
+#if      (RTE_ENET_RMII_REF_CLK_PORT_ID == 0)
+  #define RTE_ENET_RMII_REF_CLK_PORT    1
+  #define RTE_ENET_RMII_REF_CLK_PIN     19
+  #define RTE_ENET_RMII_REF_CLK_FUNC    0
+#elif    (RTE_ENET_RMII_REF_CLK_PORT_ID == 1)
+  #define RTE_ENET_RMII_REF_CLK_PORT    0x10
+  #define RTE_ENET_RMII_REF_CLK_PIN     0
+  #define RTE_ENET_RMII_REF_CLK_FUNC    7
+#else
+  #error "Invalid ENET_REF_CLK Pin Configuration!"
+#endif
+//     <o> ENET_RXD0 Pin <0=>P1_15
+#define   RTE_ENET_RMII_RXD0_PORT_ID    0
+#if      (RTE_ENET_RMII_RXD0_PORT_ID == 0)
+  #define RTE_ENET_RMII_RXD0_PORT       1
+  #define RTE_ENET_RMII_RXD0_PIN        15
+  #define RTE_ENET_RMII_RXD0_FUNC       3
+#else
+  #error "Invalid ENET_RXD0 Pin Configuration!"
+#endif
+//     <o> ENET_RXD1 Pin <0=>P0_0
+#define   RTE_ENET_RMII_RXD1_PORT_ID    0
+#if      (RTE_ENET_RMII_RXD1_PORT_ID == 0)
+  #define RTE_ENET_RMII_RXD1_PORT       0
+  #define RTE_ENET_RMII_RXD1_PIN        0
+  #define RTE_ENET_RMII_RXD1_FUNC       2
+#else
+  #error "Invalid ENET_RXD1 Pin Configuration!"
+#endif
+//     <o> ENET_RX_DV Pin <0=>P1_16 <1=>PC_8
+#define   RTE_ENET_RMII_RX_DV_PORT_ID   0
+#if      (RTE_ENET_RMII_RX_DV_PORT_ID == 0)
+  #define RTE_ENET_RMII_RX_DV_PORT      1
+  #define RTE_ENET_RMII_RX_DV_PIN       16
+  #define RTE_ENET_RMII_RX_DV_FUNC      7
+#elif    (RTE_ENET_RMII_RX_DV_PORT_ID == 1)
+  #define RTE_ENET_RMII_RX_DV_PORT      0xC
+  #define RTE_ENET_RMII_RX_DV_PIN       8
+  #define RTE_ENET_RMII_RX_DV_FUNC      3
+#else
+  #error "Invalid ENET_RX_DV Pin Configuration!"
+#endif
+//   </e> RMII (Reduced Media Independent Interface)
+
+//   <h> MIIM (Management Data Interface)
+//     <o> ENET_MDIO Pin <0=>P1_17
+#define   RTE_ENET_MDI_MDIO_PORT_ID     0
+#if      (RTE_ENET_MDI_MDIO_PORT_ID == 0)
+  #define RTE_ENET_MDI_MDIO_PORT        1
+  #define RTE_ENET_MDI_MDIO_PIN         17
+  #define RTE_ENET_MDI_MDIO_FUNC        3
+#else
+  #error "Invalid ENET_MDIO Pin Configuration!"
+#endif
+//     <o> ENET_MDC Pin <0=>P2_0 <1=>P7_7 <2=>PC_1
+#define   RTE_ENET_MDI_MDC_PORT_ID      2
+#if      (RTE_ENET_MDI_MDC_PORT_ID == 0)
+  #define RTE_ENET_MDI_MDC_PORT         2
+  #define RTE_ENET_MDI_MDC_PIN          0
+  #define RTE_ENET_MDI_MDC_FUNC         7
+#elif    (RTE_ENET_MDI_MDC_PORT_ID == 1)
+  #define RTE_ENET_MDI_MDC_PORT         7
+  #define RTE_ENET_MDI_MDC_PIN          7
+  #define RTE_ENET_MDI_MDC_FUNC         6
+#elif    (RTE_ENET_MDI_MDC_PORT_ID == 2)
+  #define RTE_ENET_MDI_MDC_PORT         0xC
+  #define RTE_ENET_MDI_MDC_PIN          1
+  #define RTE_ENET_MDI_MDC_FUNC         3
+#else
+  #error "Invalid ENET_MDC Pin Configuration!"
+#endif
+//   </h> MIIM (Management Data Interface)
+// </e> ENET (Ethernet Interface) [Driver_ETH_MAC0]
+
+// <e> SD/MMC Interface [Driver_MCI0]
+// <i> Configuration settings for Driver_MCI0 in component ::Drivers:MCI
+#define RTE_SDMMC                       0
+
+//   <h> SD/MMC Peripheral Bus
+//     <o> SD_CLK Pin <0=>PC_0 <1=>CLK0 <2=>CLK2
+#define   RTE_SD_CLK_PORT_ID            0
+#if      (RTE_SD_CLK_PORT_ID == 0)
+  #define RTE_SD_CLK_PORT               0xC
+  #define RTE_SD_CLK_PIN                0
+  #define RTE_SD_CLK_FUNC               7
+#elif    (RTE_SD_CLK_PORT_ID == 1)
+  #define RTE_SD_CLK_PORT               0x10
+  #define RTE_SD_CLK_PIN                0
+  #define RTE_SD_CLK_FUNC               4
+#elif    (RTE_SD_CLK_PORT_ID == 2)
+  #define RTE_SD_CLK_PORT               0x10
+  #define RTE_SD_CLK_PIN                2
+  #define RTE_SD_CLK_FUNC               4
+#else
+  #error "Invalid SD_CLK Pin Configuration!"
+#endif
+//     <o> SD_CMD Pin <0=>P1_6 <1=>PC_10
+#define   RTE_SD_CMD_PORT_ID            1
+#if      (RTE_SD_CMD_PORT_ID == 0)
+  #define RTE_SD_CMD_PORT               1
+  #define RTE_SD_CMD_PIN                6
+  #define RTE_SD_CMD_FUNC               7
+#elif    (RTE_SD_CMD_PORT_ID == 1)
+  #define RTE_SD_CMD_PORT               0xC
+  #define RTE_SD_CMD_PIN                10
+  #define RTE_SD_CMD_FUNC               7
+#else
+  #error "Invalid SD_CMD Pin Configuration!"
+#endif
+//     <o> SD_DAT0 Pin <0=>P1_9 <1=>PC_4
+#define   RTE_SD_DAT0_PORT_ID           1
+#if      (RTE_SD_DAT0_PORT_ID == 0)
+  #define RTE_SD_DAT0_PORT              1
+  #define RTE_SD_DAT0_PIN               9
+  #define RTE_SD_DAT0_FUNC              7
+#elif    (RTE_SD_DAT0_PORT_ID == 1)
+  #define RTE_SD_DAT0_PORT              0xC
+  #define RTE_SD_DAT0_PIN               4
+  #define RTE_SD_DAT0_FUNC              7
+#else
+  #error "Invalid SD_DAT0 Pin Configuration!"
+#endif
+//     <e> SD_DAT[1 .. 3]
+#define   RTE_SDMMC_BUS_WIDTH_4         1
+//       <o> SD_DAT1 Pin <0=>P1_10 <1=>PC_5
+#define   RTE_SD_DAT1_PORT_ID           1
+#if      (RTE_SD_DAT1_PORT_ID == 0)
+  #define RTE_SD_DAT1_PORT              1
+  #define RTE_SD_DAT1_PIN               10
+  #define RTE_SD_DAT1_FUNC              7
+#elif    (RTE_SD_DAT1_PORT_ID == 1)
+  #define RTE_SD_DAT1_PORT              0xC
+  #define RTE_SD_DAT1_PIN               5
+  #define RTE_SD_DAT1_FUNC              7
+#else
+  #error "Invalid SD_DAT1 Pin Configuration!"
+#endif
+//       <o> SD_DAT2 Pin <0=>P1_11 <1=>PC_6
+#define   RTE_SD_DAT2_PORT_ID           1
+#if      (RTE_SD_DAT2_PORT_ID == 0)
+  #define RTE_SD_DAT2_PORT              1
+  #define RTE_SD_DAT2_PIN               11
+  #define RTE_SD_DAT2_FUNC              7
+#elif    (RTE_SD_DAT2_PORT_ID == 1)
+  #define RTE_SD_DAT2_PORT              0xC
+  #define RTE_SD_DAT2_PIN               6
+  #define RTE_SD_DAT2_FUNC              7
+#else
+  #error "Invalid SD_DAT2 Pin Configuration!"
+#endif
+//       <o> SD_DAT3 Pin <0=>P1_12 <1=>PC_7
+#define   RTE_SD_DAT3_PORT_ID           1
+#if      (RTE_SD_DAT3_PORT_ID == 0)
+  #define RTE_SD_DAT3_PORT              1
+  #define RTE_SD_DAT3_PIN               12
+  #define RTE_SD_DAT3_FUNC              7
+#elif    (RTE_SD_DAT3_PORT_ID == 1)
+  #define RTE_SD_DAT3_PORT              0xC
+  #define RTE_SD_DAT3_PIN               7
+  #define RTE_SD_DAT3_FUNC              7
+#else
+  #error "Invalid SD_DAT3 Pin Configuration!"
+#endif
+//     </e> SD_DAT[1 .. 3]
+//     <e> SD_DAT[4 .. 7]
+#define   RTE_SDMMC_BUS_WIDTH_8         0
+//       <o> SD_DAT4 Pin <0=>PC_11
+#define   RTE_SD_DAT4_PORT_ID           0
+#if      (RTE_SD_DAT4_PORT_ID == 0)
+  #define RTE_SD_DAT4_PORT              0xC
+  #define RTE_SD_DAT4_PIN               11
+  #define RTE_SD_DAT4_FUNC              7
+#else
+  #error "Invalid SD_DAT4 Pin Configuration!"
+#endif
+//       <o> SD_DAT5 Pin <0=>PC_12
+#define   RTE_SD_DAT5_PORT_ID           0
+#if      (RTE_SD_DAT5_PORT_ID == 0)
+  #define RTE_SD_DAT5_PORT              0xC
+  #define RTE_SD_DAT5_PIN               12
+  #define RTE_SD_DAT5_FUNC              7
+#else
+  #error "Invalid SD_DAT5 Pin Configuration!"
+#endif
+//       <o> SD_DAT6 Pin <0=>PC_13
+#define   RTE_SD_DAT6_PORT_ID           0
+#if      (RTE_SD_DAT6_PORT_ID == 0)
+  #define RTE_SD_DAT6_PORT              0xC
+  #define RTE_SD_DAT6_PIN               13
+  #define RTE_SD_DAT6_FUNC              7
+#else
+  #error "Invalid SD_DAT6 Pin Configuration!"
+#endif
+//       <o> SD_DAT7 Pin <0=>PC_14
+#define   RTE_SD_DAT7_PORT_ID           0
+#if      (RTE_SD_DAT7_PORT_ID == 0)
+  #define RTE_SD_DAT7_PORT              0xC
+  #define RTE_SD_DAT7_PIN               14
+  #define RTE_SD_DAT7_FUNC              7
+#else
+  #error "Invalid SD_DAT7 Pin Configuration!"
+#endif
+//     </e> SD_DAT[4 .. 7]
+//   </h> SD/MMC Peripheral Bus
+
+//   <o> SD_CD (Card Detect) Pin <0=>Not used <1=>P1_13 <2=>PC_8
+//   <i> Configure Pin if exists
+#define   RTE_SD_CD_PORT_ID             2
+#if      (RTE_SD_CD_PORT_ID == 0)
+  #define RTE_SD_CD_PIN_EN              0
+#elif    (RTE_SD_CD_PORT_ID == 1)
+  #define RTE_SD_CD_PORT                1
+  #define RTE_SD_CD_PIN                 13
+  #define RTE_SD_CD_FUNC                7
+#elif    (RTE_SD_CD_PORT_ID == 2)
+  #define RTE_SD_CD_PORT                0xC
+  #define RTE_SD_CD_PIN                 8
+  #define RTE_SD_CD_FUNC                7
+#else
+  #error "Invalid SD_CD Pin Configuration!"
+#endif
+#ifndef   RTE_SD_CD_PIN_EN
+  #define RTE_SD_CD_PIN_EN              1
+#endif
+//   <o> SD_WP (Write Protect) Pin <0=>Not used <1=>PD_15 <2=>PF_10
+//   <i> Configure Pin if exists
+#define   RTE_SD_WP_PORT_ID             0
+#if      (RTE_SD_WP_PORT_ID == 0)
+  #define RTE_SD_WP_PIN_EN              0
+#elif    (RTE_SD_WP_PORT_ID == 1)
+  #define RTE_SD_WP_PORT                0xD
+  #define RTE_SD_WP_PIN                 15
+  #define RTE_SD_WP_FUNC                5
+#elif    (RTE_SD_WP_PORT_ID == 2)
+  #define RTE_SD_WP_PORT                0xF
+  #define RTE_SD_WP_PIN                 10
+  #define RTE_SD_WP_FUNC                6
+#else
+  #error "Invalid SD_WP Pin Configuration!"
+#endif
+#ifndef   RTE_SD_WP_PIN_EN
+  #define RTE_SD_WP_PIN_EN              1
+#endif
+//   <o> SD_POW (Power) Pin <0=>Not used <1=>P1_5 <2=>PC_9 <3=>PD_1
+//   <i> Configure Pin if exists
+#define   RTE_SD_POW_PORT_ID            0
+#if      (RTE_SD_POW_PORT_ID == 0)
+  #define RTE_SD_POW_PIN_EN             0
+#elif    (RTE_SD_POW_PORT_ID == 1)
+  #define RTE_SD_POW_PORT               1
+  #define RTE_SD_POW_PIN                5
+  #define RTE_SD_POW_FUNC               7
+#elif    (RTE_SD_POW_PORT_ID == 2)
+  #define RTE_SD_POW_PORT               0xC
+  #define RTE_SD_POW_PIN                9
+  #define RTE_SD_POW_FUNC               7
+#elif    (RTE_SD_POW_PORT_ID == 3)
+  #define RTE_SD_POW_PORT               0xD
+  #define RTE_SD_POW_PIN                1
+  #define RTE_SD_POW_FUNC               5
+#else
+  #error "Invalid SD_POW Pin Configuration!"
+#endif
+#ifndef   RTE_SD_POW_PIN_EN
+  #define RTE_SD_POW_PIN_EN             1
+#endif
+//   <o> SD_RST (Card Reset for MMC4.4) Pin <0=>Not used <1=>P1_3 <2=>PC_2
+//   <i> Configure Pin if exists
+#define   RTE_SD_RST_PORT_ID            0
+#if      (RTE_SD_RST_PORT_ID == 0)
+  #define RTE_SD_RST_PIN_EN             0
+#elif    (RTE_SD_RST_PORT_ID == 1)
+  #define RTE_SD_RST_PORT               1
+  #define RTE_SD_RST_PIN                3
+  #define RTE_SD_RST_FUNC               7
+#elif    (RTE_SD_RST_PORT_ID == 2)
+  #define RTE_SD_RST_PORT               0xC
+  #define RTE_SD_RST_PIN                2
+  #define RTE_SD_RST_FUNC               7
+#else
+  #error "Invalid SD_RST Pin Configuration!"
+#endif
+#ifndef   RTE_SD_RST_PIN_EN
+  #define RTE_SD_RST_PIN_EN             1
+#endif
+// </e> SD/MMC Interface [Driver_MCI0]
+
+// <e> I2C0 (Inter-integrated Circuit Interface 0) [Driver_I2C0]
+// <i> Configuration settings for Driver_I2C0 in component ::Drivers:I2C
+// </e> I2C0 (Inter-integrated Circuit Interface 0) [Driver_I2C0]
+#define   RTE_I2C0                      0
+
+// <e> I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1]
+// <i> Configuration settings for Driver_I2C1 in component ::Drivers:I2C
+#define   RTE_I2C1                      0
+
+//   <o> I2C1_SCL Pin <0=>P2_4 <1=>PE_15
+#define   RTE_I2C1_SCL_PORT_ID          0
+#if      (RTE_I2C1_SCL_PORT_ID == 0)
+  #define RTE_I2C1_SCL_PORT             2
+  #define RTE_I2C1_SCL_PIN              4
+  #define RTE_I2C1_SCL_FUNC             1
+#elif    (RTE_I2C1_SCL_PORT_ID == 1)
+  #define RTE_I2C1_SCL_PORT             0xE
+  #define RTE_I2C1_SCL_PIN              15
+  #define RTE_I2C1_SCL_FUNC             2
+#else
+  #error "Invalid I2C1_SCL Pin Configuration!"
+#endif
+//   <o> I2C1_SDA Pin <0=>P2_3 <1=>PE_13
+#define   RTE_I2C1_SDA_PORT_ID          0
+#if      (RTE_I2C1_SDA_PORT_ID == 0)
+  #define RTE_I2C1_SDA_PORT             2
+  #define RTE_I2C1_SDA_PIN              3
+  #define RTE_I2C1_SDA_FUNC             1
+#elif    (RTE_I2C1_SDA_PORT_ID == 1)
+  #define RTE_I2C1_SDA_PORT             0xE
+  #define RTE_I2C1_SDA_PIN              13
+  #define RTE_I2C1_SDA_FUNC             2
+#else
+  #error "Invalid I2C1_SDA Pin Configuration!"
+#endif
+// </e> I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1]
+
+// <e> USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0]
+#define   RTE_USART0                    0
+
+//   <h> Pin Configuration
+//     <o> TX <0=>P2_0 <1=>P6_4 <2=>P9_5 <3=>PF_10
+//     <i> USART0 Serial Output pin
+#define   RTE_USART0_TX_ID              0
+#if      (RTE_USART0_TX_ID == 0)
+  #define RTE_USART0_TX_PORT            2
+  #define RTE_USART0_TX_BIT             0
+  #define RTE_USART0_TX_FUNC            1
+#elif    (RTE_USART0_TX_ID == 1)
+  #define RTE_USART0_TX_PORT            6
+  #define RTE_USART0_TX_BIT             4
+  #define RTE_USART0_TX_FUNC            2
+#elif    (RTE_USART0_TX_ID == 2)
+  #define RTE_USART0_TX_PORT            9
+  #define RTE_USART0_TX_BIT             5
+  #define RTE_USART0_TX_FUNC            7
+#elif    (RTE_USART0_TX_ID == 3)
+  #define RTE_USART0_TX_PORT            0xF
+  #define RTE_USART0_TX_BIT             10
+  #define RTE_USART0_TX_FUNC            1
+#else
+  #error "Invalid USART0_TX Pin Configuration!"
+#endif
+//     <o> RX <0=>P2_1 <1=>P6_5 <2=>P9_6 <3=>PF_11
+//     <i> USART0 Serial Input pin
+#define   RTE_USART0_RX_ID              0
+#if      (RTE_USART0_RX_ID == 0)
+  #define RTE_USART0_RX_PORT            2
+  #define RTE_USART0_RX_BIT             1
+  #define RTE_USART0_RX_FUNC            1
+#elif    (RTE_USART0_RX_ID == 1)
+  #define RTE_USART0_RX_PORT            6
+  #define RTE_USART0_RX_BIT             5
+  #define RTE_USART0_RX_FUNC            2
+#elif    (RTE_USART0_RX_ID == 2)
+  #define RTE_USART0_RX_PORT            9
+  #define RTE_USART0_RX_BIT             6
+  #define RTE_USART0_RX_FUNC            7
+#elif    (RTE_USART0_RX_ID == 3)
+  #define RTE_USART0_RX_PORT            0xF
+  #define RTE_USART0_RX_BIT             11
+  #define RTE_USART0_RX_FUNC            1
+#else
+  #error "Invalid USART0_RX Pin Configuration!"
+#endif
+//     <o> UCLK (Synchronous and SmartCard mode) <0=>Not used <1=>P2_2 <2=>P6_1 <3=>PF_8
+//     <i> USART0 Serial Clock input/output synchronous mode
+#define   RTE_USART0_UCLK_ID            0
+#if      (RTE_USART0_UCLK_ID == 0)
+  #define RTE_USART0_UCLK_PIN_EN        0
+#elif    (RTE_USART0_UCLK_ID == 1)
+  #define RTE_USART0_UCLK_PORT          2
+  #define RTE_USART0_UCLK_BIT           2
+  #define RTE_USART0_UCLK_FUNC          1
+#elif    (RTE_USART0_UCLK_ID == 2)
+  #define RTE_USART0_UCLK_PORT          6
+  #define RTE_USART0_UCLK_BIT           1
+  #define RTE_USART0_UCLK_FUNC          2
+#elif    (RTE_USART0_UCLK_ID == 3)
+  #define RTE_USART0_UCLK_PORT          0xF
+  #define RTE_USART0_UCLK_BIT           8
+  #define RTE_USART0_UCLK_FUNC          1
+#else
+  #error "Invalid USART0_UCLK Pin Configuration!"
+#endif
+#ifndef   RTE_USART0_UCLK_PIN_EN
+  #define RTE_USART0_UCLK_PIN_EN        1
+#endif
+//   </h> Pin Configuration
+
+//   <h> DMA
+//     <e> Tx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>1 (DMAMUXPER1)  <1=>11 (DMAMUXPER11)
+//     </e>
+#define   RTE_USART0_DMA_TX_EN          0
+#define   RTE_USART0_DMA_TX_CH          0
+#define   RTE_USART0_DMA_TX_PERI_ID     0
+#if      (RTE_USART0_DMA_TX_PERI_ID == 0)
+  #define RTE_USART0_DMA_TX_PERI        1
+  #define RTE_USART0_DMA_TX_PERI_SEL    1
+#elif    (RTE_USART0_DMA_TX_PERI_ID == 1)
+  #define RTE_USART0_DMA_TX_PERI        11
+  #define RTE_USART0_DMA_TX_PERI_SEL    2
+#endif
+//     <e> Rx
+//       <o1> Channel    <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral <0=>2 (DMAMUXPER2)  <1=>12 (DMAMUXPER12)
+//     </e>
+#define   RTE_USART0_DMA_RX_EN          0
+#define   RTE_USART0_DMA_RX_CH          1
+#define   RTE_USART0_DMA_RX_PERI_ID     0
+#if      (RTE_USART0_DMA_RX_PERI_ID == 0)
+  #define RTE_USART0_DMA_RX_PERI        2
+  #define RTE_USART0_DMA_RX_PERI_SEL    1
+#elif    (RTE_USART0_DMA_RX_PERI_ID == 1)
+  #define RTE_USART0_DMA_RX_PERI        12
+  #define RTE_USART0_DMA_RX_PERI_SEL    2
+#endif
+//   </h> DMA
+// </e> USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0]
+
+// <e> UART1 (Universal asynchronous receiver transmitter) [Driver_USART1]
+#define   RTE_UART1                     0
+
+//   <h> Pin Configuration
+//     <o> TX <0=>P1_13 <1=>P3_4 <2=>P5_6 <3=>PC_13 <4=>PE_11
+//     <i> UART0 Serial Output pin
+#define   RTE_UART1_TX_ID               2
+#if      (RTE_UART1_TX_ID == 0)
+  #define RTE_UART1_TX_PORT             1
+  #define RTE_UART1_TX_BIT              13
+  #define RTE_UART1_TX_FUNC             1
+#elif    (RTE_UART1_TX_ID == 1)
+  #define RTE_UART1_TX_PORT             3
+  #define RTE_UART1_TX_BIT              4
+  #define RTE_UART1_TX_FUNC             4
+#elif    (RTE_UART1_TX_ID == 2)
+  #define RTE_UART1_TX_PORT             5
+  #define RTE_UART1_TX_BIT              6
+  #define RTE_UART1_TX_FUNC             4
+#elif    (RTE_UART1_TX_ID == 3)
+  #define RTE_UART1_TX_PORT             0xC
+  #define RTE_UART1_TX_BIT              13
+  #define RTE_UART1_TX_FUNC             2
+#elif    (RTE_UART1_TX_ID == 4)
+  #define RTE_UART1_TX_PORT             0xE
+  #define RTE_UART1_TX_BIT              11
+  #define RTE_UART1_TX_FUNC             2
+#else
+  #error "Invalid UART1_TX Pin Configuration!"
+#endif
+//   <o> RX <0=>P1_14 <1=>P3_5 <2=>P5_7 <3=>PC_14 <4=>PE_12
+//   <i> UART1 Serial Input pin
+#define   RTE_UART1_RX_ID               0
+#if      (RTE_UART1_RX_ID == 0)
+  #define RTE_UART1_RX_PORT             1
+  #define RTE_UART1_RX_BIT              14
+  #define RTE_UART1_RX_FUNC             1
+#elif    (RTE_UART1_RX_ID == 1)
+  #define RTE_UART1_RX_PORT             3
+  #define RTE_UART1_RX_BIT              5
+  #define RTE_UART1_RX_FUNC             4
+#elif    (RTE_UART1_RX_ID == 2)
+  #define RTE_UART1_RX_PORT             5
+  #define RTE_UART1_RX_BIT              7
+  #define RTE_UART1_RX_FUNC             4
+#elif    (RTE_UART1_RX_ID == 3)
+  #define RTE_UART1_RX_PORT             0xC
+  #define RTE_UART1_RX_BIT              14
+  #define RTE_UART1_RX_FUNC             2
+#elif    (RTE_UART1_RX_ID == 4)
+  #define RTE_UART1_RX_PORT             0xE
+  #define RTE_UART1_RX_BIT              12
+  #define RTE_UART1_RX_FUNC             2
+#else
+  #error "Invalid UART1_RX Pin Configuration!"
+#endif
+
+//     <h> Modem Lines
+//       <o> CTS <0=>Not used <1=>P1_11 <2=>P5_4 <3=>PC_2 <4=>PE_7
+#define   RTE_UART1_CTS_ID              1
+#if      (RTE_UART1_CTS_ID == 0)
+  #define RTE_UART1_CTS_PIN_EN          0
+#elif    (RTE_UART1_CTS_ID == 1)
+  #define RTE_UART1_CTS_PORT            1
+  #define RTE_UART1_CTS_BIT             11
+  #define RTE_UART1_CTS_FUNC            1
+#elif    (RTE_UART1_CTS_ID == 2)
+  #define RTE_UART1_CTS_PORT            5
+  #define RTE_UART1_CTS_BIT             4
+  #define RTE_UART1_CTS_FUNC            4
+#elif    (RTE_UART1_CTS_ID == 3)
+  #define RTE_UART1_CTS_PORT            0xC
+  #define RTE_UART1_CTS_BIT             2
+  #define RTE_UART1_CTS_FUNC            2
+#elif    (RTE_UART1_CTS_ID == 4)
+  #define RTE_UART1_CTS_PORT            0xE
+  #define RTE_UART1_CTS_BIT             7
+  #define RTE_UART1_CTS_FUNC            2
+#else
+  #error "Invalid UART1_CTS Pin Configuration!"
+#endif
+#ifndef   RTE_UART1_CTS_PIN_EN
+  #define RTE_UART1_CTS_PIN_EN          1
+#endif
+//       <o> RTS <0=>Not used <1=>P1_9  <2=>P5_2 <3=>PC_3 <4=>PE_5
+#define   RTE_UART1_RTS_ID              1
+#if      (RTE_UART1_RTS_ID == 0)
+  #define RTE_UART1_RTS_PIN_EN          0
+#elif    (RTE_UART1_RTS_ID == 1)
+  #define RTE_UART1_RTS_PORT            1
+  #define RTE_UART1_RTS_BIT             9
+  #define RTE_UART1_RTS_FUNC            1
+#elif    (RTE_UART1_RTS_ID == 2)
+  #define RTE_UART1_RTS_PORT            5
+  #define RTE_UART1_RTS_BIT             2
+  #define RTE_UART1_RTS_FUNC            4
+#elif    (RTE_UART1_RTS_ID == 3)
+  #define RTE_UART1_RTS_PORT            0xC
+  #define RTE_UART1_RTS_BIT             3
+  #define RTE_UART1_RTS_FUNC            2
+#elif    (RTE_UART1_RTS_ID == 4)
+  #define RTE_UART1_RTS_PORT            0xE
+  #define RTE_UART1_RTS_BIT             5
+  #define RTE_UART1_RTS_FUNC            2
+#else
+  #error "Invalid UART1_RTS Pin Configuration!"
+#endif
+#ifndef   RTE_UART1_RTS_PIN_EN
+  #define RTE_UART1_RTS_PIN_EN          1
+#endif
+//       <o> DCD <0=>Not used <1=>P1_12 <2=>P5_5 <3=>PC_11 <4=>PE_9
+#define   RTE_UART1_DCD_ID              1
+#if      (RTE_UART1_DCD_ID == 0)
+  #define RTE_UART1_DCD_PIN_EN          0
+#elif    (RTE_UART1_DCD_ID == 1)
+  #define RTE_UART1_DCD_PORT            1
+  #define RTE_UART1_DCD_BIT             12
+  #define RTE_UART1_DCD_FUNC            1
+#elif    (RTE_UART1_DCD_ID == 2)
+  #define RTE_UART1_DCD_PORT            5
+  #define RTE_UART1_DCD_BIT             5
+  #define RTE_UART1_DCD_FUNC            4
+#elif    (RTE_UART1_DCD_ID == 3)
+  #define RTE_UART1_DCD_PORT            0xC
+  #define RTE_UART1_DCD_BIT             11
+  #define RTE_UART1_DCD_FUNC            2
+#elif    (RTE_UART1_DCD_ID == 4)
+  #define RTE_UART1_DCD_PORT            0xE
+  #define RTE_UART1_DCD_BIT             9
+  #define RTE_UART1_DCD_FUNC            2
+#else
+  #error "Invalid UART1_DCD Pin Configuration!"
+#endif
+#ifndef   RTE_UART1_DCD_PIN_EN
+  #define RTE_UART1_DCD_PIN_EN          1
+#endif
+//       <o> DSR <0=>Not used <1=>P1_7 <2=>P5_0 <3=>PC_10 <4=>PE_8
+#define   RTE_UART1_DSR_ID              1
+#if      (RTE_UART1_DSR_ID == 0)
+  #define RTE_UART1_DSR_PIN_EN          0
+#elif    (RTE_UART1_DSR_ID == 1)
+  #define RTE_UART1_DSR_PORT            1
+  #define RTE_UART1_DSR_BIT             7
+  #define RTE_UART1_DSR_FUNC            1
+#elif    (RTE_UART1_DSR_ID == 2)
+  #define RTE_UART1_DSR_PORT            5
+  #define RTE_UART1_DSR_BIT             0
+  #define RTE_UART1_DSR_FUNC            4
+#elif    (RTE_UART1_DSR_ID == 3)
+  #define RTE_UART1_DSR_PORT            0xC
+  #define RTE_UART1_DSR_BIT             10
+  #define RTE_UART1_DSR_FUNC            2
+#elif    (RTE_UART1_DSR_ID == 4)
+  #define RTE_UART1_DSR_PORT            0xE
+  #define RTE_UART1_DSR_BIT             8
+  #define RTE_UART1_DSR_FUNC            2
+#else
+  #error "Invalid UART1_DSR Pin Configuration!"
+#endif
+#ifndef   RTE_UART1_DSR_PIN_EN
+  #define RTE_UART1_DSR_PIN_EN          1
+#endif
+//       <o> DTR <0=>Not used <1=>P1_8  <2=>P5_1 <3=>PC_12 <4=>PE_10
+#define   RTE_UART1_DTR_ID              1
+#if      (RTE_UART1_DTR_ID == 0)
+  #define RTE_UART1_DTR_PIN_EN          0
+#elif    (RTE_UART1_DTR_ID == 1)
+  #define RTE_UART1_DTR_PORT            1
+  #define RTE_UART1_DTR_BIT             8
+  #define RTE_UART1_DTR_FUNC            1
+#elif    (RTE_UART1_DTR_ID == 2)
+  #define RTE_UART1_DTR_PORT            5
+  #define RTE_UART1_DTR_BIT             1
+  #define RTE_UART1_DTR_FUNC            4
+#elif    (RTE_UART1_DTR_ID == 3)
+  #define RTE_UART1_DTR_PORT            0xC
+  #define RTE_UART1_DTR_BIT             12
+  #define RTE_UART1_DTR_FUNC            2
+#elif    (RTE_UART1_DTR_ID == 4)
+  #define RTE_UART1_DTR_PORT            0xE
+  #define RTE_UART1_DTR_BIT             10
+  #define RTE_UART1_DTR_FUNC            2
+#else
+  #error "Invalid UART1_DTR Pin Configuration!"
+#endif
+#ifndef   RTE_UART1_DTR_PIN_EN
+  #define RTE_UART1_DTR_PIN_EN          1
+#endif
+//       <o> RI <0=>Not used <1=>P1_10 <2=>P5_3 <3=>PC_1 <4=>PE_6
+#define   RTE_UART1_RI_ID               1
+#if      (RTE_UART1_RI_ID == 0)
+  #define RTE_UART1_RI_PIN_EN           0
+#elif    (RTE_UART1_RI_ID == 1)
+  #define RTE_UART1_RI_PORT             1
+  #define RTE_UART1_RI_BIT              10
+  #define RTE_UART1_RI_FUNC             1
+#elif    (RTE_UART1_RI_ID == 2)
+  #define RTE_UART1_RI_PORT             5
+  #define RTE_UART1_RI_BIT              3
+  #define RTE_UART1_RI_FUNC             4
+#elif    (RTE_UART1_RI_ID == 3)
+  #define RTE_UART1_RI_PORT             0xC
+  #define RTE_UART1_RI_BIT              1
+  #define RTE_UART1_RI_FUNC             2
+#elif    (RTE_UART1_RI_ID == 4)
+  #define RTE_UART1_RI_PORT             0xE
+  #define RTE_UART1_RI_BIT              6
+  #define RTE_UART1_RI_FUNC             2
+#else
+  #error "Invalid UART1_RI Pin Configuration!"
+#endif
+#ifndef   RTE_UART1_RI_PIN_EN
+  #define RTE_UART1_RI_PIN_EN           1
+#endif
+//     </h> Modem Lines
+//   </h> Pin Configuration
+
+//   <h> DMA
+//     <e> Tx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>3 (DMAMUXPER3)
+//     </e>
+#define   RTE_UART1_DMA_TX_EN           0
+#define   RTE_UART1_DMA_TX_CH           0
+#define   RTE_UART1_DMA_TX_PERI_ID      0
+#if      (RTE_UART1_DMA_TX_PERI_ID == 0)
+  #define RTE_UART1_DMA_TX_PERI         3
+  #define RTE_UART1_DMA_TX_PERI_SEL     1
+#endif
+//     <e> Rx
+//       <o1> Channel    <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral <0=>4 (DMAMUXPER4)
+//     </e>
+#define   RTE_UART1_DMA_RX_EN           0
+#define   RTE_UART1_DMA_RX_CH           1
+#define   RTE_UART1_DMA_RX_PERI_ID      0
+#if      (RTE_UART1_DMA_RX_PERI_ID == 0)
+  #define RTE_UART1_DMA_RX_PERI         4
+  #define RTE_UART1_DMA_RX_PERI_SEL     1
+#endif
+//   </h> DMA
+// </e> UART1 (Universal asynchronous receiver transmitter) [Driver_USART1]
+
+// <e> USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2]
+#define   RTE_USART2                    0
+
+//   <h> Pin Configuration
+//     <o> TX <0=>P1_15 <1=>P2_10 <2=>P7_1 <3=>PA_1
+//     <i> USART2 Serial Output pin
+#define   RTE_USART2_TX_ID              0
+#if      (RTE_USART2_TX_ID == 0)
+  #define RTE_USART2_TX_PORT            1
+  #define RTE_USART2_TX_BIT             15
+  #define RTE_USART2_TX_FUNC            1
+#elif    (RTE_USART2_TX_ID == 1)
+  #define RTE_USART2_TX_PORT            2
+  #define RTE_USART2_TX_BIT             10
+  #define RTE_USART2_TX_FUNC            2
+#elif    (RTE_USART2_TX_ID == 2)
+  #define RTE_USART2_TX_PORT            7
+  #define RTE_USART2_TX_BIT             1
+  #define RTE_USART2_TX_FUNC            6
+#elif    (RTE_USART2_TX_ID == 3)
+  #define RTE_USART2_TX_PORT            0xA
+  #define RTE_USART2_TX_BIT             1
+  #define RTE_USART2_TX_FUNC            3
+#else
+  #error "Invalid USART2_TX Pin Configuration!"
+#endif
+//     <o> RX <0=>P1_16 <1=>P2_11 <2=>P7_2 <3=>PA_2
+//     <i> USART2 Serial Input pin
+#define   RTE_USART2_RX_ID              0
+#if      (RTE_USART2_RX_ID == 0)
+  #define RTE_USART2_RX_PORT            1
+  #define RTE_USART2_RX_BIT             16
+  #define RTE_USART2_RX_FUNC            1
+#elif    (RTE_USART2_RX_ID == 1)
+  #define RTE_USART2_RX_PORT            2
+  #define RTE_USART2_RX_BIT             11
+  #define RTE_USART2_RX_FUNC            2
+#elif    (RTE_USART2_RX_ID == 2)
+  #define RTE_USART2_RX_PORT            7
+  #define RTE_USART2_RX_BIT             2
+  #define RTE_USART2_RX_FUNC            6
+#elif    (RTE_USART2_RX_ID == 3)
+  #define RTE_USART2_RX_PORT            0xA
+  #define RTE_USART2_RX_BIT             2
+  #define RTE_USART2_RX_FUNC            3
+#else
+  #error "Invalid USART2_RX Pin Configuration!"
+#endif
+//       <o> UCLK (Synchronous and SmartCard mode) <0=>Not used <1=>P1_17 <2=>P2_12
+//       <i> USART2 Serial Clock input/output synchronous mode
+#define   RTE_USART2_UCLK_ID            0
+#if      (RTE_USART2_UCLK_ID == 0)
+  #define RTE_USART2_UCLK_PIN_EN        0
+#elif    (RTE_USART2_UCLK_ID == 1)
+  #define RTE_USART2_UCLK_PORT          1
+  #define RTE_USART2_UCLK_BIT           17
+  #define RTE_USART2_UCLK_FUNC          1
+#elif    (RTE_USART2_UCLK_ID == 1)
+  #define RTE_USART2_UCLK_PORT          2
+  #define RTE_USART2_UCLK_BIT           12
+  #define RTE_USART2_UCLK_FUNC          7
+#else
+  #error "Invalid USART2_UCLK Pin Configuration!"
+#endif
+#ifndef   RTE_USART2_UCLK_PIN_EN
+  #define RTE_USART2_UCLK_PIN_EN        1
+#endif
+//   </h> Pin Configuration
+
+//   <h> DMA
+//     <e> Tx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>5 (DMAMUXPER5)
+//     </e>
+#define   RTE_USART2_DMA_TX_EN          0
+#define   RTE_USART2_DMA_TX_CH          0
+#define   RTE_USART2_DMA_TX_PERI_ID     0
+#if      (RTE_USART2_DMA_TX_PERI_ID == 0)
+  #define RTE_USART2_DMA_TX_PERI        5
+  #define RTE_USART2_DMA_TX_PERI_SEL    1
+#endif
+//     <e> Rx
+//       <o1> Channel    <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral <0=>6 (DMAMUXPER6)
+//     </e>
+#define   RTE_USART2_DMA_RX_EN          0
+#define   RTE_USART2_DMA_RX_CH          1
+#define   RTE_USART2_DMA_RX_PERI_ID     0
+#if      (RTE_USART2_DMA_RX_PERI_ID == 0)
+  #define RTE_USART2_DMA_RX_PERI        6
+  #define RTE_USART2_DMA_RX_PERI_SEL    1
+#endif
+//   </h> DMA
+// </e> USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2]
+
+// <e> USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3]
+#define   RTE_USART3                    0
+
+//   <h> Pin Configuration
+//     <o> TX <0=>P2_3 <1=>P4_1 <2=>P9_3 <3=>PF_2
+//     <i> USART3 Serial Output pin
+#define   RTE_USART3_TX_ID              0
+#if      (RTE_USART3_TX_ID == 0)
+  #define RTE_USART3_TX_PORT            2
+  #define RTE_USART3_TX_BIT             3
+  #define RTE_USART3_TX_FUNC            2
+#elif    (RTE_USART3_TX_ID == 1)
+  #define RTE_USART3_TX_PORT            4
+  #define RTE_USART3_TX_BIT             1
+  #define RTE_USART3_TX_FUNC            6
+#elif    (RTE_USART3_TX_ID == 2)
+  #define RTE_USART3_TX_PORT            9
+  #define RTE_USART3_TX_BIT             3
+  #define RTE_USART3_TX_FUNC            7
+#elif    (RTE_USART3_TX_ID == 3)
+  #define RTE_USART3_TX_PORT            0xF
+  #define RTE_USART3_TX_BIT             2
+  #define RTE_USART3_TX_FUNC            1
+#else
+  #error "Invalid USART3_TX Pin Configuration!"
+#endif
+//     <o> RX <0=>P2_4 <1=>P4_2 <2=>P9_4 <3=>PF_3
+//     <i> USART3 Serial Input pin
+#define   RTE_USART3_RX_ID              0
+#if      (RTE_USART3_RX_ID == 0)
+  #define RTE_USART3_RX_PORT            2
+  #define RTE_USART3_RX_BIT             4
+  #define RTE_USART3_RX_FUNC            2
+#elif    (RTE_USART3_RX_ID == 1)
+  #define RTE_USART3_RX_PORT            4
+  #define RTE_USART3_RX_BIT             2
+  #define RTE_USART3_RX_FUNC            6
+#elif    (RTE_USART3_RX_ID == 2)
+  #define RTE_USART3_RX_PORT            9
+  #define RTE_USART3_RX_BIT             4
+  #define RTE_USART3_RX_FUNC            7
+#elif    (RTE_USART3_RX_ID == 3)
+  #define RTE_USART3_RX_PORT            0xF
+  #define RTE_USART3_RX_BIT             3
+  #define RTE_USART3_RX_FUNC            1
+#else
+  #error "Invalid USART3_RX Pin Configuration!"
+#endif
+//     <o> UCLK (Synchronous and SmartCard mode) <0=>Not used <1=>P2_7 <2=>P4_0 <3=>PF_5
+//     <i> USART3 Serial Clock input/output synchronous mode
+#define   RTE_USART3_UCLK_ID            0
+#if      (RTE_USART3_UCLK_ID == 0)
+  #define RTE_USART3_UCLK_PIN_EN        0
+#elif    (RTE_USART3_UCLK_ID == 1)
+  #define RTE_USART3_UCLK_PORT          2
+  #define RTE_USART3_UCLK_BIT           7
+  #define RTE_USART3_UCLK_FUNC          2
+#elif    (RTE_USART3_UCLK_ID == 2)
+  #define RTE_USART3_UCLK_PORT          4
+  #define RTE_USART3_UCLK_BIT           0
+  #define RTE_USART3_UCLK_FUNC          6
+#elif    (RTE_USART3_UCLK_ID == 3)
+  #define RTE_USART3_UCLK_PORT          0xF
+  #define RTE_USART3_UCLK_BIT           5
+  #define RTE_USART3_UCLK_FUNC          1
+#else
+  #error "Invalid USART3_UCLK Pin Configuration!"
+#endif
+#ifndef   RTE_USART3_UCLK_PIN_EN
+  #define RTE_USART3_UCLK_PIN_EN        1
+#endif
+//   </h> Pin Configuration
+
+//   <h> DMA
+//     <e> Tx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>7 (DMAMUXPER7)  <1=>14 (DMAMUXPER14)
+//     </e>
+#define   RTE_USART3_DMA_TX_EN          0
+#define   RTE_USART3_DMA_TX_CH          0
+#define   RTE_USART3_DMA_TX_PERI_ID     0
+#if      (RTE_USART3_DMA_TX_PERI_ID == 0)
+  #define RTE_USART3_DMA_TX_PERI        7
+  #define RTE_USART3_DMA_TX_PERI_SEL    1
+#elif    (RTE_USART3_DMA_TX_PERI_ID == 1)
+  #define RTE_USART3_DMA_TX_PERI        14
+  #define RTE_USART3_DMA_TX_PERI_SEL    3
+#endif
+//     <e> Rx
+//       <o1> Channel    <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral <0=>8 (DMAMUXPER8)  <1=>13 (DMAMUXPER13)
+//     </e>
+#define   RTE_USART3_DMA_RX_EN          0
+#define   RTE_USART3_DMA_RX_CH          1
+#define   RTE_USART3_DMA_RX_PERI_ID     0
+#if      (RTE_USART3_DMA_RX_PERI_ID == 0)
+  #define RTE_USART3_DMA_RX_PERI        8
+  #define RTE_USART3_DMA_RX_PERI_SEL    1
+#elif    (RTE_USART3_DMA_RX_PERI_ID == 1)
+  #define RTE_USART3_DMA_RX_PERI        13
+  #define RTE_USART3_DMA_RX_PERI_SEL    3
+#endif
+//   </h> DMA
+// </e> USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3]
+
+// <e> SSP0 (Synchronous Serial Port 0) [Driver_SPI0]
+// <i> Configuration settings for Driver_SPI0 in component ::Drivers:SPI
+#define   RTE_SSP0                      0
+
+//   <h> Pin Configuration
+//     <o> SSP0_SSEL <0=>Not used <1=>P1_0 <2=>P3_6 <3=>P3_8 <4=>P9_0 <5=>PF_1
+//     <i> Slave Select for SSP0
+#define   RTE_SSP0_SSEL_PIN_SEL         5
+#if      (RTE_SSP0_SSEL_PIN_SEL == 0)
+#define   RTE_SSP0_SSEL_PIN_EN          0
+#elif    (RTE_SSP0_SSEL_PIN_SEL == 1)
+  #define RTE_SSP0_SSEL_PORT            1
+  #define RTE_SSP0_SSEL_BIT             0
+  #define RTE_SSP0_SSEL_FUNC            5
+  #define RTE_SSP0_SSEL_GPIO_FUNC       0
+  #define RTE_SSP0_SSEL_GPIO_PORT       0
+  #define RTE_SSP0_SSEL_GPIO_BIT        4
+#elif    (RTE_SSP0_SSEL_PIN_SEL == 2)
+  #define RTE_SSP0_SSEL_PORT            3
+  #define RTE_SSP0_SSEL_BIT             6
+  #define RTE_SSP0_SSEL_FUNC            2
+  #define RTE_SSP0_SSEL_GPIO_FUNC       0
+  #define RTE_SSP0_SSEL_GPIO_PORT       0
+  #define RTE_SSP0_SSEL_GPIO_BIT        6
+#elif    (RTE_SSP0_SSEL_PIN_SEL == 3)
+  #define RTE_SSP0_SSEL_PORT            3
+  #define RTE_SSP0_SSEL_BIT             8
+  #define RTE_SSP0_SSEL_FUNC            5
+  #define RTE_SSP0_SSEL_GPIO_FUNC       4
+  #define RTE_SSP0_SSEL_GPIO_PORT       5
+  #define RTE_SSP0_SSEL_GPIO_BIT        11
+#elif    (RTE_SSP0_SSEL_PIN_SEL == 4)
+  #define RTE_SSP0_SSEL_PORT            9
+  #define RTE_SSP0_SSEL_BIT             0
+  #define RTE_SSP0_SSEL_FUNC            7
+  #define RTE_SSP0_SSEL_GPIO_FUNC       0
+  #define RTE_SSP0_SSEL_GPIO_PORT       4
+  #define RTE_SSP0_SSEL_GPIO_BIT        12
+#elif    (RTE_SSP0_SSEL_PIN_SEL == 5)
+  #define RTE_SSP0_SSEL_PORT            0xF
+  #define RTE_SSP0_SSEL_BIT             1
+  #define RTE_SSP0_SSEL_FUNC            2
+  #define RTE_SSP0_SSEL_GPIO_FUNC       4
+  #define RTE_SSP0_SSEL_GPIO_PORT       7
+  #define RTE_SSP0_SSEL_GPIO_BIT        16
+#else
+  #error "Invalid SSP0 SSP0_SSEL Pin Configuration!"
+#endif
+#ifndef   RTE_SSP0_SSEL_PIN_EN
+#define   RTE_SSP0_SSEL_PIN_EN          1
+#endif
+//     <o> SSP0_SCK <0=>P3_0 <1=>P3_3 <2=>PF_0
+//     <i> Serial clock for SSP0
+#define   RTE_SSP0_SCK_PIN_SEL          2
+#if      (RTE_SSP0_SCK_PIN_SEL == 0)
+  #define RTE_SSP0_SCK_PORT             3
+  #define RTE_SSP0_SCK_BIT              0
+  #define RTE_SSP0_SCK_FUNC             4
+#elif    (RTE_SSP0_SCK_PIN_SEL == 1)
+  #define RTE_SSP0_SCK_PORT             3
+  #define RTE_SSP0_SCK_BIT              3
+  #define RTE_SSP0_SCK_FUNC             2
+#elif    (RTE_SSP0_SCK_PIN_SEL == 2)
+  #define RTE_SSP0_SCK_PORT             0xF
+  #define RTE_SSP0_SCK_BIT              0
+  #define RTE_SSP0_SCK_FUNC             0
+#else
+  #error "Invalid SSP0 SSP0_SCK Pin Configuration!"
+#endif
+//     <o> SSP0_MISO <0=>P1_1 <1=>P3_6 <2=>P3_7 <3=>P9_1 <4=>PF_2
+//     <i> Master In Slave Out for SSP0
+#define   RTE_SSP0_MISO_PIN_SEL         4
+#if      (RTE_SSP0_MISO_PIN_SEL == 0)
+  #define RTE_SSP0_MISO_PORT            1
+  #define RTE_SSP0_MISO_BIT             1
+  #define RTE_SSP0_MISO_FUNC            5
+#elif    (RTE_SSP0_MISO_PIN_SEL == 1)
+  #define RTE_SSP0_MISO_PORT            3
+  #define RTE_SSP0_MISO_BIT             6
+  #define RTE_SSP0_MISO_FUNC            5
+#elif    (RTE_SSP0_MISO_PIN_SEL == 2)
+  #define RTE_SSP0_MISO_PORT            3
+  #define RTE_SSP0_MISO_BIT             7
+  #define RTE_SSP0_MISO_FUNC            2
+#elif    (RTE_SSP0_MISO_PIN_SEL == 3)
+  #define RTE_SSP0_MISO_PORT            9
+  #define RTE_SSP0_MISO_BIT             1
+  #define RTE_SSP0_MISO_FUNC            7
+#elif    (RTE_SSP0_MISO_PIN_SEL == 4)
+  #define RTE_SSP0_MISO_PORT            0xF
+  #define RTE_SSP0_MISO_BIT             2
+  #define RTE_SSP0_MISO_FUNC            2
+#else
+  #error "Invalid SSP0 SSP0_MISO Pin Configuration!"
+#endif
+//     <o> SSP0_MOSI <0=>P1_2 <1=>P3_7 <2=>P3_8 <3=>P9_2 <4=>PF_3
+//     <i> Master Out Slave In for SSP0
+#define   RTE_SSP0_MOSI_PIN_SEL         4
+#if      (RTE_SSP0_MOSI_PIN_SEL == 0)
+  #define RTE_SSP0_MOSI_PORT            1
+  #define RTE_SSP0_MOSI_BIT             2
+  #define RTE_SSP0_MOSI_FUNC            5
+#elif    (RTE_SSP0_MOSI_PIN_SEL == 1)
+  #define RTE_SSP0_MOSI_PORT            3
+  #define RTE_SSP0_MOSI_BIT             7
+  #define RTE_SSP0_MOSI_FUNC            5
+#elif    (RTE_SSP0_MOSI_PIN_SEL == 2)
+  #define RTE_SSP0_MOSI_PORT            3
+  #define RTE_SSP0_MOSI_BIT             8
+  #define RTE_SSP0_MOSI_FUNC            2
+#elif    (RTE_SSP0_MOSI_PIN_SEL == 3)
+  #define RTE_SSP0_MOSI_PORT            9
+  #define RTE_SSP0_MOSI_BIT             2
+  #define RTE_SSP0_MOSI_FUNC            7
+#elif    (RTE_SSP0_MOSI_PIN_SEL == 4)
+  #define RTE_SSP0_MOSI_PORT            0xF
+  #define RTE_SSP0_MOSI_BIT             3
+  #define RTE_SSP0_MOSI_FUNC            2
+#else
+  #error "Invalid SSP0 SSP0_MOSI Pin Configuration!"
+#endif
+//   </h> Pin Configuration
+
+//   <h> DMA
+//     <e> Tx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>10 (DMAMUXPER10)
+//     </e>
+#define   RTE_SSP0_DMA_TX_EN            0
+#define   RTE_SSP0_DMA_TX_CH            0
+#define   RTE_SSP0_DMA_TX_PERI_ID       0
+#if      (RTE_SSP0_DMA_TX_PERI_ID == 0)
+  #define RTE_SSP0_DMA_TX_PERI          10
+  #define RTE_SSP0_DMA_TX_PERI_SEL      0
+#endif
+//     <e> Rx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>9 (DMAMUXPER9)
+//     </e>
+#define   RTE_SSP0_DMA_RX_EN            0
+#define   RTE_SSP0_DMA_RX_CH            1
+#define   RTE_SSP0_DMA_RX_PERI_ID       0
+#if      (RTE_SSP0_DMA_RX_PERI_ID == 0)
+  #define RTE_SSP0_DMA_RX_PERI          9
+  #define RTE_SSP0_DMA_RX_PERI_SEL      0
+#endif
+//   </h> DMA
+// </e> SSP0 (Synchronous Serial Port 0) [Driver_SPI0]
+
+// <e> SSP1 (Synchronous Serial Port 1) [Driver_SPI1]
+// <i> Configuration settings for Driver_SPI1 in component ::Drivers:SPI
+#define   RTE_SSP1                      0
+
+//   <h> Pin Configuration
+//     <o> SSP1_SSEL <0=>Not used <1=>P1_5 <2=>P1_20 <3=>PF_5
+//     <i> Slave Select for SSP1
+#define   RTE_SSP1_SSEL_PIN_SEL         1
+#if      (RTE_SSP1_SSEL_PIN_SEL == 0)
+  #define RTE_SSP1_SSEL_PIN_EN          0
+#elif    (RTE_SSP1_SSEL_PIN_SEL == 1)
+  #define RTE_SSP1_SSEL_PORT            1
+  #define RTE_SSP1_SSEL_BIT             5
+  #define RTE_SSP1_SSEL_FUNC            5
+  #define RTE_SSP1_SSEL_GPIO_FUNC       0
+  #define RTE_SSP1_SSEL_GPIO_PORT       1
+  #define RTE_SSP1_SSEL_GPIO_BIT        8
+#elif    (RTE_SSP1_SSEL_PIN_SEL == 2)
+  #define RTE_SSP1_SSEL_PORT            1
+  #define RTE_SSP1_SSEL_BIT             20
+  #define RTE_SSP1_SSEL_FUNC            1
+  #define RTE_SSP1_SSEL_GPIO_FUNC       0
+  #define RTE_SSP1_SSEL_GPIO_PORT       0
+  #define RTE_SSP1_SSEL_GPIO_BIT        15
+#elif    (RTE_SSP1_SSEL_PIN_SEL == 3)
+  #define RTE_SSP1_SSEL_PORT            0xF
+  #define RTE_SSP1_SSEL_BIT             5
+  #define RTE_SSP1_SSEL_FUNC            2
+  #define RTE_SSP1_SSEL_GPIO_FUNC       4
+  #define RTE_SSP1_SSEL_GPIO_PORT       7
+  #define RTE_SSP1_SSEL_GPIO_BIT        19
+#else
+  #error "Invalid SSP1 SSP1_SSEL Pin Configuration!"
+#endif
+#ifndef   RTE_SSP1_SSEL_PIN_EN
+#define   RTE_SSP1_SSEL_PIN_EN          1
+#endif
+//     <o> SSP1_SCK <0=>P1_19 <1=>PF_4 <2=>CLK0
+//     <i> Serial clock for SSP1
+#define   RTE_SSP1_SCK_PIN_SEL          0
+#if      (RTE_SSP1_SCK_PIN_SEL == 0)
+  #define RTE_SSP1_SCK_PORT             1
+  #define RTE_SSP1_SCK_BIT              19
+  #define RTE_SSP1_SCK_FUNC             1
+#elif    (RTE_SSP1_SCK_PIN_SEL == 1)
+  #define RTE_SSP1_SCK_PORT             0xF
+  #define RTE_SSP1_SCK_BIT              4
+  #define RTE_SSP1_SCK_FUNC             0
+#elif    (RTE_SSP1_SCK_PIN_SEL == 2)
+  #define RTE_SSP1_SCK_PORT             0x10
+  #define RTE_SSP1_SCK_BIT              0
+  #define RTE_SSP1_SCK_FUNC             6
+#else
+  #error "Invalid SSP1 SSP1_SCK Pin Configuration!"
+#endif
+//     <o> SSP1_MISO <0=>P0_0 <1=>P1_3 <2=>PF_6
+//     <i> Master In Slave Out for SSP1
+#define   RTE_SSP1_MISO_PIN_SEL         0
+#if      (RTE_SSP1_MISO_PIN_SEL == 0)
+  #define RTE_SSP1_MISO_PORT            0
+  #define RTE_SSP1_MISO_BIT             0
+  #define RTE_SSP1_MISO_FUNC            1
+#elif    (RTE_SSP1_MISO_PIN_SEL == 1)
+  #define RTE_SSP1_MISO_PORT            1
+  #define RTE_SSP1_MISO_BIT             3
+  #define RTE_SSP1_MISO_FUNC            5
+#elif    (RTE_SSP1_MISO_PIN_SEL == 2)
+  #define RTE_SSP1_MISO_PORT            0xF
+  #define RTE_SSP1_MISO_BIT             6
+  #define RTE_SSP1_MISO_FUNC            2
+#else
+  #error "Invalid SSP1 SSP1_MISO Pin Configuration!"
+#endif
+//     <o> SSP1_MOSI <0=>P0_1 <1=>P1_4 <2=>PF_7
+//     <i> Master Out Slave In for SSP1
+#define   RTE_SSP1_MOSI_PIN_SEL         0
+#if      (RTE_SSP1_MOSI_PIN_SEL == 0)
+  #define RTE_SSP1_MOSI_PORT            0
+  #define RTE_SSP1_MOSI_BIT             1
+  #define RTE_SSP1_MOSI_FUNC            1
+#elif    (RTE_SSP1_MOSI_PIN_SEL == 1)
+  #define RTE_SSP1_MOSI_PORT            1
+  #define RTE_SSP1_MOSI_BIT             4
+  #define RTE_SSP1_MOSI_FUNC            5
+#elif    (RTE_SSP1_MOSI_PIN_SEL == 2)
+  #define RTE_SSP1_MOSI_PORT            0xF
+  #define RTE_SSP1_MOSI_BIT             7
+  #define RTE_SSP1_MOSI_FUNC            2
+#else
+  #error "Invalid SSP1 SSP1_MOSI Pin Configuration!"
+#endif
+//   </h> Pin Configuration
+
+//   <h> DMA
+//     <e> Tx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>3 (DMAMUXPER3) <1=>5 (DMAMUXPER5) <2=>12 (DMAMUXPER12) <3=>14 (DMAMUXPER14)
+//     </e>
+#define   RTE_SSP1_DMA_TX_EN            0
+#define   RTE_SSP1_DMA_TX_CH            0
+#define   RTE_SSP1_DMA_TX_PERI_ID       0
+#if      (RTE_SSP1_DMA_TX_PERI_ID == 0)
+  #define RTE_SSP1_DMA_TX_PERI          3
+  #define RTE_SSP1_DMA_TX_PERI_SEL      3
+#elif    (RTE_SSP1_DMA_TX_PERI_ID == 1)
+  #define RTE_SSP1_DMA_TX_PERI          5
+  #define RTE_SSP1_DMA_TX_PERI_SEL      2
+#elif    (RTE_SSP1_DMA_TX_PERI_ID == 2)
+  #define RTE_SSP1_DMA_TX_PERI          12
+  #define RTE_SSP1_DMA_TX_PERI_SEL      0
+#elif    (RTE_SSP1_DMA_TX_PERI_ID == 3)
+  #define RTE_SSP1_DMA_TX_PERI          14
+  #define RTE_SSP1_DMA_TX_PERI_SEL      2
+#endif
+//     <e> Rx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>4 (DMAMUXPER4) <1=>6 (DMAMUXPER6) <2=>11 (DMAMUXPER11) <3=>13 (DMAMUXPER13)
+//     </e>
+#define   RTE_SSP1_DMA_RX_EN            0
+#define   RTE_SSP1_DMA_RX_CH            1
+#define   RTE_SSP1_DMA_RX_PERI_ID       0
+#if      (RTE_SSP1_DMA_RX_PERI_ID == 0)
+  #define RTE_SSP1_DMA_RX_PERI          4
+  #define RTE_SSP1_DMA_RX_PERI_SEL      3
+#elif    (RTE_SSP1_DMA_RX_PERI_ID == 1)
+  #define RTE_SSP1_DMA_RX_PERI          6
+  #define RTE_SSP1_DMA_RX_PERI_SEL      2
+#elif    (RTE_SSP1_DMA_RX_PERI_ID == 2)
+  #define RTE_SSP1_DMA_RX_PERI          11
+  #define RTE_SSP1_DMA_RX_PERI_SEL      0
+#elif    (RTE_SSP1_DMA_RX_PERI_ID == 3)
+  #define RTE_SSP1_DMA_RX_PERI          13
+  #define RTE_SSP1_DMA_RX_PERI_SEL      2
+#endif
+//   </h> DMA
+// </e> SSP1 (Synchronous Serial Port 1) [Driver_SPI1]
+
+// <e> I2S0 (Integrated Interchip Sound 0) [Driver_SAI0]
+// <i> Configuration settings for Driver_SAI0 in component ::Drivers:SAI
+#define   RTE_I2S0                      0
+
+//   <h> Pin Configuration
+//     <o> I2S0_RX_SCK <0=>Not used <1=>P3_0 <2=>P6_0 <3=>PF_4
+//     <i> Receive clock for I2S0
+#define   RTE_I2S0_RX_SCK_PIN_SEL       2
+#if      (RTE_I2S0_RX_SCK_PIN_SEL == 0)
+#define   RTE_I2S0_RX_SCK_PIN_EN        0
+#elif    (RTE_I2S0_RX_SCK_PIN_SEL == 1)
+  #define RTE_I2S0_RX_SCK_PORT          3
+  #define RTE_I2S0_RX_SCK_BIT           0
+  #define RTE_I2S0_RX_SCK_FUNC          0
+#elif    (RTE_I2S0_RX_SCK_PIN_SEL == 2)
+  #define RTE_I2S0_RX_SCK_PORT          6
+  #define RTE_I2S0_RX_SCK_BIT           0
+  #define RTE_I2S0_RX_SCK_FUNC          4
+#elif    (RTE_I2S0_RX_SCK_PIN_SEL == 3)
+  #define RTE_I2S0_RX_SCK_PORT          0xF
+  #define RTE_I2S0_RX_SCK_BIT           4
+  #define RTE_I2S0_RX_SCK_FUNC          7
+#else
+  #error "Invalid I2S0 I2S0_RX_SCK Pin Configuration!"
+#endif
+#ifndef   RTE_I2S0_RX_SCK_PIN_EN
+#define   RTE_I2S0_RX_SCK_PIN_EN        1
+#endif
+//     <o> I2S0_RX_WS <0=>Not used <1=>P3_1 <2=>P6_1
+//     <i> Receive word select for I2S0
+#define   RTE_I2S0_RX_WS_PIN_SEL        2
+#if      (RTE_I2S0_RX_WS_PIN_SEL == 0)
+#define   RTE_I2S0_RX_WS_PIN_EN         0
+#elif    (RTE_I2S0_RX_WS_PIN_SEL == 1)
+  #define RTE_I2S0_RX_WS_PORT           3
+  #define RTE_I2S0_RX_WS_BIT            1
+  #define RTE_I2S0_RX_WS_FUNC           1
+#elif    (RTE_I2S0_RX_WS_PIN_SEL == 2)
+  #define RTE_I2S0_RX_WS_PORT           6
+  #define RTE_I2S0_RX_WS_BIT            1
+  #define RTE_I2S0_RX_WS_FUNC           3
+#else
+  #error "Invalid I2S0 I2S0_RX_WS Pin Configuration!"
+#endif
+#ifndef   RTE_I2S0_RX_WS_PIN_EN
+#define   RTE_I2S0_RX_WS_PIN_EN         1
+#endif
+//     <o> I2S0_RX_SDA <0=>Not used <1=>P3_2 <2=>P6_2
+//     <i> Receive master clock for I2S0
+#define   RTE_I2S0_RX_SDA_PIN_SEL       2
+#if      (RTE_I2S0_RX_SDA_PIN_SEL == 0)
+#define   RTE_I2S0_RX_SDA_PIN_EN        0
+#elif    (RTE_I2S0_RX_SDA_PIN_SEL == 1)
+  #define RTE_I2S0_RX_SDA_PORT          3
+  #define RTE_I2S0_RX_SDA_BIT           2
+  #define RTE_I2S0_RX_SDA_FUNC          1
+#elif    (RTE_I2S0_RX_SDA_PIN_SEL == 2)
+  #define RTE_I2S0_RX_SDA_PORT          6
+  #define RTE_I2S0_RX_SDA_BIT           2
+  #define RTE_I2S0_RX_SDA_FUNC          3
+#else
+  #error "Invalid I2S0 I2S0_RX_SDA Pin Configuration!"
+#endif
+#ifndef   RTE_I2S0_RX_SDA_PIN_EN
+#define   RTE_I2S0_RX_SDA_PIN_EN       1
+#endif
+//     <o> I2S0_RX_MCLK <0=>Not used <1=>P1_19 <2=>P3_0 <3=>P6_0
+//     <i> Receive master clock for I2S0
+#define   RTE_I2S0_RX_MCLK_PIN_SEL      0
+#if      (RTE_I2S0_RX_MCLK_PIN_SEL == 0)
+#define   RTE_I2S0_RX_MCLK_PIN_EN       0
+#elif    (RTE_I2S0_RX_MCLK_PIN_SEL == 1)
+  #define RTE_I2S0_RX_MCLK_PORT         1
+  #define RTE_I2S0_RX_MCLK_BIT          19
+  #define RTE_I2S0_RX_MCLK_FUNC         6
+#elif    (RTE_I2S0_RX_MCLK_PIN_SEL == 2)
+  #define RTE_I2S0_RX_MCLK_PORT         3
+  #define RTE_I2S0_RX_MCLK_BIT          0
+  #define RTE_I2S0_RX_MCLK_FUNC         1
+#elif    (RTE_I2S0_RX_MCLK_PIN_SEL == 3)
+  #define RTE_I2S0_RX_MCLK_PORT         6
+  #define RTE_I2S0_RX_MCLK_BIT          0
+  #define RTE_I2S0_RX_MCLK_FUNC         1
+#else
+  #error "Invalid I2S0 I2S0_RX_MCLK Pin Configuration!"
+#endif
+#ifndef   RTE_I2S0_RX_MCLK_PIN_EN
+#define   RTE_I2S0_RX_MCLK_PIN_EN       1
+#endif
+//     <o> I2S0_TX_SCK <0=>Not used <1=>P3_0 <2=>P4_7
+//     <i> Transmit clock for I2S0
+#define   RTE_I2S0_TX_SCK_PIN_SEL       1
+#if      (RTE_I2S0_TX_SCK_PIN_SEL == 0)
+#define   RTE_I2S0_TX_SCK_PIN_EN        0
+#elif    (RTE_I2S0_TX_SCK_PIN_SEL == 1)
+  #define RTE_I2S0_TX_SCK_PORT          3
+  #define RTE_I2S0_TX_SCK_BIT           0
+  #define RTE_I2S0_TX_SCK_FUNC          2
+#elif    (RTE_I2S0_TX_SCK_PIN_SEL == 2)
+  #define RTE_I2S0_TX_SCK_PORT          4
+  #define RTE_I2S0_TX_SCK_BIT           7
+  #define RTE_I2S0_TX_SCK_FUNC          7
+#else
+  #error "Invalid I2S0 I2S0_TX_SCK Pin Configuration!"
+#endif
+#ifndef   RTE_I2S0_TX_SCK_PIN_EN
+#define   RTE_I2S0_TX_SCK_PIN_EN        1
+#endif
+//     <o> I2S0_TX_WS <0=>Not used <1=>P0_0 <2=>P3_1 <3=>P3_4 <4=>P7_1 <5=>P9_1 <6=>PC_13
+//     <i> Transmit word select for I2S0
+#define   RTE_I2S0_TX_WS_PIN_SEL        4
+#if      (RTE_I2S0_TX_WS_PIN_SEL == 0)
+#define   RTE_I2S0_TX_WS_PIN_EN         0
+#elif    (RTE_I2S0_TX_WS_PIN_SEL == 1)
+  #define RTE_I2S0_TX_WS_PORT           0
+  #define RTE_I2S0_TX_WS_BIT            0
+  #define RTE_I2S0_TX_WS_FUNC           6
+#elif    (RTE_I2S0_TX_WS_PIN_SEL == 2)
+  #define RTE_I2S0_TX_WS_PORT           3
+  #define RTE_I2S0_TX_WS_BIT            1
+  #define RTE_I2S0_TX_WS_FUNC           0
+#elif    (RTE_I2S0_TX_WS_PIN_SEL == 3)
+  #define RTE_I2S0_TX_WS_PORT           3
+  #define RTE_I2S0_TX_WS_BIT            4
+  #define RTE_I2S0_TX_WS_FUNC           5
+#elif    (RTE_I2S0_TX_WS_PIN_SEL == 4)
+  #define RTE_I2S0_TX_WS_PORT           7
+  #define RTE_I2S0_TX_WS_BIT            1
+  #define RTE_I2S0_TX_WS_FUNC           2
+#elif    (RTE_I2S0_TX_WS_PIN_SEL == 5)
+  #define RTE_I2S0_TX_WS_PORT           9
+  #define RTE_I2S0_TX_WS_BIT            1
+  #define RTE_I2S0_TX_WS_FUNC           4
+#elif    (RTE_I2S0_TX_WS_PIN_SEL == 6)
+  #define RTE_I2S0_TX_WS_PORT           0xC
+  #define RTE_I2S0_TX_WS_BIT            13
+  #define RTE_I2S0_TX_WS_FUNC           6
+#else
+  #error "Invalid I2S0 I2S0_TX_WS Pin Configuration!"
+#endif
+#ifndef   RTE_I2S0_TX_WS_PIN_EN
+#define   RTE_I2S0_TX_WS_PIN_EN         1
+#endif
+//     <o> I2S0_TX_SDA <0=>Not used <1=>P3_2 <2=>P3_5 <3=>P7_2 <4=>P9_2  <5=>PC_12
+//     <i> Transmit data for I2S0
+#define   RTE_I2S0_TX_SDA_PIN_SEL       3
+#if      (RTE_I2S0_TX_SDA_PIN_SEL == 0)
+#define   RTE_I2S0_TX_SDA_PIN_EN        0
+#elif    (RTE_I2S0_TX_SDA_PIN_SEL == 1)
+  #define RTE_I2S0_TX_SDA_PORT          3
+  #define RTE_I2S0_TX_SDA_BIT           2
+  #define RTE_I2S0_TX_SDA_FUNC          0
+#elif    (RTE_I2S0_TX_SDA_PIN_SEL == 2)
+  #define RTE_I2S0_TX_SDA_PORT          3
+  #define RTE_I2S0_TX_SDA_BIT           5
+  #define RTE_I2S0_TX_SDA_FUNC          5
+#elif    (RTE_I2S0_TX_SDA_PIN_SEL == 3)
+  #define RTE_I2S0_TX_SDA_PORT          7
+  #define RTE_I2S0_TX_SDA_BIT           2
+  #define RTE_I2S0_TX_SDA_FUNC          2
+#elif    (RTE_I2S0_TX_SDA_PIN_SEL == 4)
+  #define RTE_I2S0_TX_SDA_PORT          9
+  #define RTE_I2S0_TX_SDA_BIT           2
+  #define RTE_I2S0_TX_SDA_FUNC          4
+#elif    (RTE_I2S0_TX_SDA_PIN_SEL == 5)
+  #define RTE_I2S0_TX_SDA_PORT          0xC
+  #define RTE_I2S0_TX_SDA_BIT           12
+  #define RTE_I2S0_TX_SDA_FUNC          6
+#else
+  #error "Invalid I2S0 I2S0_TX_SDA Pin Configuration!"
+#endif
+#ifndef   RTE_I2S0_TX_SDA_PIN_EN
+#define   RTE_I2S0_TX_SDA_PIN_EN        1
+#endif
+//     <o> I2S0_TX_MCLK <0=>Not used <1=>P3_0 <2=>P3_3 <3=>PF_4 <4=>CLK2
+//     <i> Transmit master clock for I2S0
+#define   RTE_I2S0_TX_MCLK_PIN_SEL      2
+#if      (RTE_I2S0_TX_MCLK_PIN_SEL == 0)
+#define   RTE_I2S0_TX_MCLK_PIN_EN       0
+#elif    (RTE_I2S0_TX_MCLK_PIN_SEL == 1)
+  #define RTE_I2S0_TX_MCLK_PORT         3
+  #define RTE_I2S0_TX_MCLK_BIT          0
+  #define RTE_I2S0_TX_MCLK_FUNC         3
+#elif    (RTE_I2S0_TX_MCLK_PIN_SEL == 2)
+  #define RTE_I2S0_TX_MCLK_PORT         3
+  #define RTE_I2S0_TX_MCLK_BIT          3
+  #define RTE_I2S0_TX_MCLK_FUNC         6
+#elif    (RTE_I2S0_TX_MCLK_PIN_SEL == 3)
+  #define RTE_I2S0_TX_MCLK_PORT         0xf
+  #define RTE_I2S0_TX_MCLK_BIT          4
+  #define RTE_I2S0_TX_MCLK_FUNC         6
+#elif    (RTE_I2S0_TX_MCLK_PIN_SEL == 4)
+  #define RTE_I2S0_TX_MCLK_PORT         0x10
+  #define RTE_I2S0_TX_MCLK_BIT          2
+  #define RTE_I2S0_TX_MCLK_FUNC         6
+#else
+  #error "Invalid I2S0 I2S0_TX_MCLK Pin Configuration!"
+#endif
+#ifndef   RTE_I2S0_TX_MCLK_PIN_EN
+#define   RTE_I2S0_TX_MCLK_PIN_EN       1
+#endif
+//   </h> Pin Configuration
+
+//   <h> DMA
+//     <e> Tx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>9 (DMAMUXPER9)
+//     </e>
+#define   RTE_I2S0_DMA_TX_EN            0
+#define   RTE_I2S0_DMA_TX_CH            0
+#define   RTE_I2S0_DMA_TX_PERI_ID       0
+#if      (RTE_I2S0_DMA_TX_PERI_ID == 0)
+  #define RTE_I2S0_DMA_TX_PERI          9
+  #define RTE_I2S0_DMA_TX_PERI_SEL      1
+#endif
+//     <e> Rx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>10 (DMAMUXPER10)
+//     </e>
+#define   RTE_I2S0_DMA_RX_EN            0
+#define   RTE_I2S0_DMA_RX_CH            1
+#define   RTE_I2S0_DMA_RX_PERI_ID       0
+#if      (RTE_I2S0_DMA_RX_PERI_ID == 0)
+  #define RTE_I2S0_DMA_RX_PERI          10
+  #define RTE_I2S0_DMA_RX_PERI_SEL      1
+#endif
+//   </h> DMA
+// </e> I2S0 (Integrated Interchip Sound 0) [Driver_SAI0]
+
+// <e> I2S1 (Integrated Interchip Sound 1) [Driver_SAI1]
+// <i> Configuration settings for Driver_I2S1 in component ::Drivers:SAI
+#define   RTE_I2S1                      0
+
+//   <h> Pin Configuration
+//     <o> I2S1_RX_SCK <0=>Not used <1=>CLK2 <2=>CLK3
+//     <i> Receive clock for I2S1
+#define   RTE_I2S1_RX_SCK_PIN_SEL       0
+#if      (RTE_I2S1_RX_SCK_PIN_SEL == 0)
+#define   RTE_I2S1_RX_SCK_PIN_EN        0
+#elif    (RTE_I2S1_RX_SCK_PIN_SEL == 1)
+  #define RTE_I2S1_RX_SCK_PORT          0x10
+  #define RTE_I2S1_RX_SCK_BIT           2
+  #define RTE_I2S1_RX_SCK_FUNC          7
+#elif    (RTE_I2S1_RX_SCK_PIN_SEL == 2)
+  #define RTE_I2S1_RX_SCK_PORT          0x10
+  #define RTE_I2S1_RX_SCK_BIT           3
+  #define RTE_I2S1_RX_SCK_FUNC          7
+#else
+  #error "Invalid I2S1 I2S1_RX_SCK Pin Configuration!"
+#endif
+#ifndef   RTE_I2S1_RX_SCK_PIN_EN
+#define   RTE_I2S1_RX_SCK_PIN_EN        1
+#endif
+//     <o> I2S1_RX_WS <0=>Not used <1=>P3_5
+//     <i> Receive word select for I2S1
+#define   RTE_I2S1_RX_WS_PIN_SEL        0
+#if      (RTE_I2S1_RX_WS_PIN_SEL == 0)
+#define   RTE_I2S1_RX_WS_PIN_EN         0
+#elif    (RTE_I2S1_RX_WS_PIN_SEL == 1)
+  #define RTE_I2S1_RX_WS_PORT           3
+  #define RTE_I2S1_RX_WS_BIT            5
+  #define RTE_I2S1_RX_WS_FUNC           6
+#else
+  #error "Invalid I2S1 I2S1_RX_WS Pin Configuration!"
+#endif
+#ifndef   RTE_I2S1_RX_WS_PIN_EN
+#define   RTE_I2S1_RX_WS_PIN_EN         1
+#endif
+//     <o> I2S1_RX_SDA <0=>Not used <1=>P3_4
+//     <i> Receive master clock for I2S1
+#define   RTE_I2S1_RX_SDA_PIN_SEL       0
+#if      (RTE_I2S1_RX_SDA_PIN_SEL == 0)
+#define   RTE_I2S1_RX_SDA_PIN_EN        0
+#elif    (RTE_I2S1_RX_SDA_PIN_SEL == 1)
+  #define RTE_I2S1_RX_SDA_PORT          3
+  #define RTE_I2S1_RX_SDA_BIT           4
+  #define RTE_I2S1_RX_SDA_FUNC          6
+#else
+  #error "Invalid I2S1 I2S1_RX_SDA Pin Configuration!"
+#endif
+#ifndef   RTE_I2S1_RX_SDA_PIN_EN
+#define   RTE_I2S1_RX_SDA_PIN_EN       1
+#endif
+//     <o> I2S1_RX_MCLK <0=>Not used <1=>PA_0
+//     <i> Receive master clock for I2S1
+#define   RTE_I2S1_RX_MCLK_PIN_SEL      0
+#if      (RTE_I2S1_RX_MCLK_PIN_SEL == 0)
+#define   RTE_I2S1_RX_MCLK_PIN_EN       0
+#elif    (RTE_I2S1_RX_MCLK_PIN_SEL == 1)
+  #define RTE_I2S1_RX_MCLK_PORT         0x0A
+  #define RTE_I2S1_RX_MCLK_BIT          0
+  #define RTE_I2S1_RX_MCLK_FUNC         5
+#else
+  #error "Invalid I2S1 I2S1_RX_MCLK Pin Configuration!"
+#endif
+#ifndef   RTE_I2S1_RX_MCLK_PIN_EN
+#define   RTE_I2S1_RX_MCLK_PIN_EN       1
+#endif
+//     <o> I2S1_TX_SCK <0=>Not used <1=>P1_19 <2=>P3_3 <3=>P4_7
+//     <i> Transmit clock for I2S1
+#define   RTE_I2S1_TX_SCK_PIN_SEL       0
+#if      (RTE_I2S1_TX_SCK_PIN_SEL == 0)
+#define   RTE_I2S1_TX_SCK_PIN_EN        0
+#elif    (RTE_I2S1_TX_SCK_PIN_SEL == 1)
+  #define RTE_I2S1_TX_SCK_PORT          1
+  #define RTE_I2S1_TX_SCK_BIT           19
+  #define RTE_I2S1_TX_SCK_FUNC          7
+#elif    (RTE_I2S1_TX_SCK_PIN_SEL == 2)
+  #define RTE_I2S1_TX_SCK_PORT          3
+  #define RTE_I2S1_TX_SCK_BIT           3
+  #define RTE_I2S1_TX_SCK_FUNC          7
+#elif    (RTE_I2S1_TX_SCK_PIN_SEL == 3)
+  #define RTE_I2S1_TX_SCK_PORT          4
+  #define RTE_I2S1_TX_SCK_BIT           7
+  #define RTE_I2S1_TX_SCK_FUNC          6
+#else
+  #error "Invalid I2S1 I2S1_TX_SCK Pin Configuration!"
+#endif
+#ifndef   RTE_I2S1_TX_SCK_PIN_EN
+#define   RTE_I2S1_TX_SCK_PIN_EN        1
+#endif
+//     <o> I2S1_TX_WS <0=>Not used <1=>P0_0 <2=>PF_7
+//     <i> Transmit word select for I2S1
+#define   RTE_I2S1_TX_WS_PIN_SEL        0
+#if      (RTE_I2S1_TX_WS_PIN_SEL == 0)
+#define   RTE_I2S1_TX_WS_PIN_EN         0
+#elif    (RTE_I2S1_TX_WS_PIN_SEL == 1)
+  #define RTE_I2S1_TX_WS_PORT           0
+  #define RTE_I2S1_TX_WS_BIT            0
+  #define RTE_I2S1_TX_WS_FUNC           7
+#elif    (RTE_I2S1_TX_WS_PIN_SEL == 2)
+  #define RTE_I2S1_TX_WS_PORT           0x0F
+  #define RTE_I2S1_TX_WS_BIT            7
+  #define RTE_I2S1_TX_WS_FUNC           7
+#else
+  #error "Invalid I2S1 I2S1_TX_WS Pin Configuration!"
+#endif
+#ifndef   RTE_I2S1_TX_WS_PIN_EN
+#define   RTE_I2S1_TX_WS_PIN_EN         1
+#endif
+//     <o> I2S1_TX_SDA <0=>Not used <1=>P0_1 <2=>PF_6
+//     <i> Transmit data for I2S
+#define   RTE_I2S1_TX_SDA_PIN_SEL       0
+#if      (RTE_I2S1_TX_SDA_PIN_SEL == 0)
+#define   RTE_I2S1_TX_SDA_PIN_EN        0
+#elif    (RTE_I2S1_TX_SDA_PIN_SEL == 1)
+  #define RTE_I2S1_TX_SDA_PORT          0
+  #define RTE_I2S1_TX_SDA_BIT           1
+  #define RTE_I2S1_TX_SDA_FUNC          7
+#elif    (RTE_I2S1_TX_SDA_PIN_SEL == 2)
+  #define RTE_I2S1_TX_SDA_PORT          0x0F
+  #define RTE_I2S1_TX_SDA_BIT           6
+  #define RTE_I2S1_TX_SDA_FUNC          7
+#else
+  #error "Invalid I2S1 I2S1_TX_SDA Pin Configuration!"
+#endif
+#ifndef   RTE_I2S1_TX_SDA_PIN_EN
+#define   RTE_I2S1_TX_SDA_PIN_EN        1
+#endif
+//     <o> I2S1_TX_MCLK <0=>Not used <1=>P8_8 <2=>PF_0 <3=>CLK1
+//     <i> Transmit master clock for I2S1
+#define   RTE_I2S1_TX_MCLK_PIN_SEL      0
+#if      (RTE_I2S1_TX_MCLK_PIN_SEL == 0)
+#define   RTE_I2S1_TX_MCLK_PIN_EN       0
+#elif    (RTE_I2S1_TX_MCLK_PIN_SEL == 1)
+  #define RTE_I2S1_TX_MCLK_PORT         8
+  #define RTE_I2S1_TX_MCLK_BIT          8
+  #define RTE_I2S1_TX_MCLK_FUNC         7
+#elif    (RTE_I2S1_TX_MCLK_PIN_SEL == 2)
+  #define RTE_I2S1_TX_MCLK_PORT         0x0F
+  #define RTE_I2S1_TX_MCLK_BIT          0
+  #define RTE_I2S1_TX_MCLK_FUNC         7
+#elif    (RTE_I2S1_TX_MCLK_PIN_SEL == 3)
+  #define RTE_I2S1_TX_MCLK_PORT         0x10
+  #define RTE_I2S1_TX_MCLK_BIT          1
+  #define RTE_I2S1_TX_MCLK_FUNC         7
+#else
+  #error "Invalid I2S1 I2S1_TX_MCLK Pin Configuration!"
+#endif
+#ifndef   RTE_I2S1_TX_MCLK_PIN_EN
+#define   RTE_I2S1_TX_MCLK_PIN_EN       1
+#endif
+//   </h> Pin Configuration
+
+//   <h> DMA
+//     <e> Tx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>3 (DMAMUXPER3)
+//     </e>
+#define   RTE_I2S1_DMA_TX_EN            0
+#define   RTE_I2S1_DMA_TX_CH            0
+#define   RTE_I2S1_DMA_TX_PERI_ID       0
+#if      (RTE_I2S1_DMA_TX_PERI_ID == 0)
+  #define RTE_I2S1_DMA_TX_PERI          3
+  #define RTE_I2S1_DMA_TX_PERI_SEL      2
+#endif
+//     <e> Rx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>4 (DMAMUXPER4)
+//     </e>
+#define   RTE_I2S1_DMA_RX_EN            0
+#define   RTE_I2S1_DMA_RX_CH            1
+#define   RTE_I2S1_DMA_RX_PERI_ID       0
+#if      (RTE_I2S1_DMA_RX_PERI_ID == 0)
+  #define RTE_I2S1_DMA_RX_PERI          4
+  #define RTE_I2S1_DMA_RX_PERI_SEL      2
+#endif
+//   </h> DMA
+// </e> I2S1 (Integrated Interchip Sound 1) [Driver_SAI1]
+
+// <e> CAN0 Controller [Driver_CAN0]
+// <i> Configuration settings for Driver_CAN0 in component ::Drivers:CAN
+#define   RTE_CAN_CAN0                  0
+
+//   <h> Pin Configuration
+//     <o> CAN0_RD <0=>Not used <1=>P3_1 <2=>PE_2
+//     <i> CAN0 receiver input.
+#define   RTE_CAN0_RD_ID                0
+#if      (RTE_CAN0_RD_ID == 0)
+  #define RTE_CAN0_RD_PIN_EN            0
+#elif    (RTE_CAN0_RD_ID == 1)
+  #define RTE_CAN0_RD_PORT              3
+  #define RTE_CAN0_RD_BIT               1
+  #define RTE_CAN0_RD_FUNC              2
+#elif    (RTE_CAN0_RD_ID == 2)
+  #define RTE_CAN0_RD_PORT              0xE
+  #define RTE_CAN0_RD_BIT               2
+  #define RTE_CAN0_RD_FUNC              1
+#else
+  #error "Invalid RTE_CAN0_RD Pin Configuration!"
+#endif
+#ifndef   RTE_CAN0_RD_PIN_EN
+  #define RTE_CAN0_RD_PIN_EN            1
+#endif
+//     <o> CAN0_TD <0=>Not used <1=>P3_2 <2=>PE_3
+//     <i> CAN0 transmitter output.
+#define   RTE_CAN0_TD_ID                0
+#if      (RTE_CAN0_TD_ID == 0)
+  #define RTE_CAN0_TD_PIN_EN            0
+#elif    (RTE_CAN0_TD_ID == 1)
+  #define RTE_CAN0_TD_PORT              3
+  #define RTE_CAN0_TD_BIT               2
+  #define RTE_CAN0_TD_FUNC              2
+#elif    (RTE_CAN0_TD_ID == 2)
+  #define RTE_CAN0_TD_PORT              0xE
+  #define RTE_CAN0_TD_BIT               3
+  #define RTE_CAN0_TD_FUNC              1
+#else
+  #error "Invalid RTE_CAN0_TD Pin Configuration!"
+#endif
+#ifndef   RTE_CAN0_TD_PIN_EN
+  #define RTE_CAN0_TD_PIN_EN            1
+#endif
+//   </h> Pin Configuration
+// </e> CAN0 Controller [Driver_CAN0]
+
+// <e> CAN1 Controller [Driver_CAN1]
+// <i> Configuration settings for Driver_CAN1 in component ::Drivers:CAN
+#define   RTE_CAN_CAN1                  0
+
+//   <h> Pin Configuration
+//     <o> CAN1_RD <0=>Not used <1=>P1_18 <2=>P4_9 <3=>PE_1
+//     <i> CAN1 receiver input.
+#define   RTE_CAN1_RD_ID                0
+#if      (RTE_CAN1_RD_ID == 0)
+  #define RTE_CAN1_RD_PIN_EN            0
+#elif    (RTE_CAN1_RD_ID == 1)
+  #define RTE_CAN1_RD_PORT              1
+  #define RTE_CAN1_RD_BIT               18
+  #define RTE_CAN1_RD_FUNC              5
+#elif    (RTE_CAN1_RD_ID == 2)
+  #define RTE_CAN1_RD_PORT              4
+  #define RTE_CAN1_RD_BIT               9
+  #define RTE_CAN1_RD_FUNC              6
+#elif    (RTE_CAN1_RD_ID == 3)
+  #define RTE_CAN1_RD_PORT              0xE
+  #define RTE_CAN1_RD_BIT               1
+  #define RTE_CAN1_RD_FUNC              5
+#else
+  #error "Invalid RTE_CAN1_RD Pin Configuration!"
+#endif
+#ifndef   RTE_CAN1_RD_PIN_EN
+  #define RTE_CAN1_RD_PIN_EN            1
+#endif
+//     <o> CAN1_TD <0=>Not used <1=>P1_17 <2=>P4_8 <3=>PE_0
+//     <i> CAN1 transmitter output.
+#define   RTE_CAN1_TD_ID                0
+#if      (RTE_CAN1_TD_ID == 0)
+  #define RTE_CAN1_TD_PIN_EN            0
+#elif    (RTE_CAN1_TD_ID == 1)
+  #define RTE_CAN1_TD_PORT              1
+  #define RTE_CAN1_TD_BIT               17
+  #define RTE_CAN1_TD_FUNC              5
+#elif    (RTE_CAN1_TD_ID == 2)
+  #define RTE_CAN1_TD_PORT              4
+  #define RTE_CAN1_TD_BIT               8
+  #define RTE_CAN1_TD_FUNC              6
+#elif    (RTE_CAN1_TD_ID == 3)
+  #define RTE_CAN1_TD_PORT              0xE
+  #define RTE_CAN1_TD_BIT               0
+  #define RTE_CAN1_TD_FUNC              5
+#else
+  #error "Invalid RTE_CAN1_TD Pin Configuration!"
+#endif
+#ifndef   RTE_CAN1_TD_PIN_EN
+  #define RTE_CAN1_TD_PIN_EN            1
+#endif
+//   </h> Pin Configuration
+// </e> CAN1 Controller [Driver_CAN1]
+
+
+#endif  /* __RTE_DEVICE_H */

CMSIS/Pack/Example/Boards/Keil/MCB1800/Blinky/RTE/Device/LPC1857/startup_LPC18xx.s

@@ -0,0 +1,324 @@
+;/***********************************************************************
+; * $Id: startup_LPC18xx.s 6471 2011-02-16 17:13:35Z nxp27266 $
+; *
+; * Project: LPC18xx CMSIS Package
+; *
+; * Description: Cortex-M3 Core Device Startup File for the NXP LPC18xx
+; *              Device Series.
+; *
+; * Copyright(C) 2011, NXP Semiconductor
+; * All rights reserved.
+; *
+; *                                                      modified by KEIL
+; ***********************************************************************
+; * Software that is described herein is for illustrative purposes only
+; * which provides customers with programming information regarding the
+; * products. This software is supplied "AS IS" without any warranties.
+; * NXP Semiconductors assumes no responsibility or liability for the
+; * use of the software, conveys no license or title under any patent,
+; * copyright, or mask work right to the product. NXP Semiconductors
+; * reserves the right to make changes in the software without
+; * notification. NXP Semiconductors also make no representation or
+; * warranty that such application will be suitable for the specified
+; * use without further testing or modification.
+; **********************************************************************/
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+
+Sign_Value      EQU     0x5A5A5A5A
+
+__Vectors       DCD     __initial_sp              ; 0 Top of Stack
+                DCD     Reset_Handler             ; 1 Reset Handler
+                DCD     NMI_Handler               ; 2 NMI Handler
+                DCD     HardFault_Handler         ; 3 Hard Fault Handler
+                DCD     MemManage_Handler         ; 4 MPU Fault Handler
+                DCD     BusFault_Handler          ; 5 Bus Fault Handler
+                DCD     UsageFault_Handler        ; 6 Usage Fault Handler
+                DCD     Sign_Value                ; 7 Reserved
+                DCD     0                         ; 8 Reserved
+                DCD     0                         ; 9 Reserved
+                DCD     0                         ; 10 Reserved
+                DCD     SVC_Handler               ; 11 SVCall Handler
+                DCD     DebugMon_Handler          ; 12 Debug Monitor Handler
+                DCD     0                         ; 13 Reserved
+                DCD     PendSV_Handler            ; 14 PendSV Handler
+                DCD     SysTick_Handler           ; 15 SysTick Handler
+
+                ; External Interrupts
+                DCD     DAC_IRQHandler            ; 16 D/A Converter
+                DCD     0                         ; 17 Reserved
+                DCD     DMA_IRQHandler            ; 18 General Purpose DMA
+                DCD     0                         ; 19 Reserved
+                DCD     FLASHEEPROM_IRQHandler    ; 20 ORed flash bank A, flash bank B, EEPROM interrupt
+                DCD     ETH_IRQHandler            ; 21 Ethernet
+                DCD     SDIO_IRQHandler           ; 22 SD/MMC
+                DCD     LCD_IRQHandler            ; 23 LCD
+                DCD     USB0_IRQHandler           ; 24 USB0
+                DCD     USB1_IRQHandler           ; 25 USB1
+                DCD     SCT_IRQHandler            ; 26 State Configurable Timer
+                DCD     RIT_IRQHandler            ; 27 Repetitive Interrupt Timer
+                DCD     TIMER0_IRQHandler         ; 28 Timer0
+                DCD     TIMER1_IRQHandler         ; 29 Timer1
+                DCD     TIMER2_IRQHandler         ; 30 Timer2
+                DCD     TIMER3_IRQHandler         ; 31 Timer3
+                DCD     MCPWM_IRQHandler          ; 32 Motor Control PWM
+                DCD     ADC0_IRQHandler           ; 33 A/D Converter 0
+                DCD     I2C0_IRQHandler           ; 34 I2C0
+                DCD     I2C1_IRQHandler           ; 35 I2C1
+                DCD     0                         ; 36 Reserved
+                DCD     ADC1_IRQHandler           ; 37 A/D Converter 1
+                DCD     SSP0_IRQHandler           ; 38 SSP0
+                DCD     SSP1_IRQHandler           ; 39 SSP1
+                DCD     UART0_IRQHandler          ; 40 UART0
+                DCD     UART1_IRQHandler          ; 41 UART1
+                DCD     UART2_IRQHandler          ; 42 UART2
+                DCD     UART3_IRQHandler          ; 43 UART3
+                DCD     I2S0_IRQHandler           ; 44 I2S0
+                DCD     I2S1_IRQHandler           ; 45 I2S1
+                DCD     0                         ; 46 Reserved
+                DCD     0                         ; 47 Reserved
+                DCD     GPIO0_IRQHandler          ; 48 GPIO0
+                DCD     GPIO1_IRQHandler          ; 49 GPIO1
+                DCD     GPIO2_IRQHandler          ; 50 GPIO2
+                DCD     GPIO3_IRQHandler          ; 51 GPIO3
+                DCD     GPIO4_IRQHandler          ; 52 GPIO4
+                DCD     GPIO5_IRQHandler          ; 53 GPIO5
+                DCD     GPIO6_IRQHandler          ; 54 GPIO6
+                DCD     GPIO7_IRQHandler          ; 55 GPIO7
+                DCD     GINT0_IRQHandler          ; 56 GINT0
+                DCD     GINT1_IRQHandler          ; 57 GINT1
+                DCD     EVRT_IRQHandler           ; 58 Event Router
+                DCD     CAN1_IRQHandler           ; 59 C_CAN1
+                DCD     0                         ; 60 Reserved
+                DCD     0                         ; 61 Reserved
+                DCD     ATIMER_IRQHandler         ; 62 ATIMER
+                DCD     RTC_IRQHandler            ; 63 RTC
+                DCD     0                         ; 64 Reserved
+                DCD     WDT_IRQHandler            ; 65 WDT
+                DCD     0                         ; 66 Reserved
+                DCD     CAN0_IRQHandler           ; 67 C_CAN0
+                DCD     QEI_IRQHandler            ; 68 QEI
+
+
+;CRP address at offset 0x2FC relative to the BOOT Bank address
+                IF      :LNOT::DEF:NO_CRP
+                SPACE   (0x2FC - (. - __Vectors))
+;                EXPORT  CRP_Key
+CRP_Key         DCD     0xFFFFFFFF
+;                       0xFFFFFFFF => CRP Disabled
+;                       0x12345678 => CRP Level 1
+;                       0x87654321 => CRP Level 2
+;                       0x43218765 => CRP Level 3 (ARE YOU SURE?)
+;                       0x4E697370 => NO ISP      (ARE YOU SURE?)
+                ENDIF
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler           [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler             [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler       [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler       [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler        [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler      [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler             [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler        [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler          [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler         [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  DAC_IRQHandler          [WEAK]
+                EXPORT  DMA_IRQHandler          [WEAK]
+                EXPORT  FLASHEEPROM_IRQHandler  [WEAK]
+                EXPORT  ETH_IRQHandler          [WEAK]
+                EXPORT  SDIO_IRQHandler         [WEAK]
+                EXPORT  LCD_IRQHandler          [WEAK]
+                EXPORT  USB0_IRQHandler         [WEAK]
+                EXPORT  USB1_IRQHandler         [WEAK]
+                EXPORT  SCT_IRQHandler          [WEAK]
+                EXPORT  RIT_IRQHandler          [WEAK]
+                EXPORT  TIMER0_IRQHandler       [WEAK]
+                EXPORT  TIMER1_IRQHandler       [WEAK]
+                EXPORT  TIMER2_IRQHandler       [WEAK]
+                EXPORT  TIMER3_IRQHandler       [WEAK]
+                EXPORT  MCPWM_IRQHandler        [WEAK]
+                EXPORT  ADC0_IRQHandler         [WEAK]
+                EXPORT  I2C0_IRQHandler         [WEAK]
+                EXPORT  I2C1_IRQHandler         [WEAK]
+                EXPORT  ADC1_IRQHandler         [WEAK]
+                EXPORT  SSP0_IRQHandler         [WEAK]
+                EXPORT  SSP1_IRQHandler         [WEAK]
+                EXPORT  UART0_IRQHandler        [WEAK]
+                EXPORT  UART1_IRQHandler        [WEAK]
+                EXPORT  UART2_IRQHandler        [WEAK]
+                EXPORT  UART3_IRQHandler        [WEAK]
+                EXPORT  I2S0_IRQHandler         [WEAK]
+                EXPORT  I2S1_IRQHandler         [WEAK]
+                EXPORT  GPIO0_IRQHandler        [WEAK]
+                EXPORT  GPIO1_IRQHandler        [WEAK]
+                EXPORT  GPIO2_IRQHandler        [WEAK]
+                EXPORT  GPIO3_IRQHandler        [WEAK]
+                EXPORT  GPIO4_IRQHandler        [WEAK]
+                EXPORT  GPIO5_IRQHandler        [WEAK]
+                EXPORT  GPIO6_IRQHandler        [WEAK]
+                EXPORT  GPIO7_IRQHandler        [WEAK]
+                EXPORT  GINT0_IRQHandler        [WEAK]
+                EXPORT  GINT1_IRQHandler        [WEAK]
+                EXPORT  EVRT_IRQHandler         [WEAK]
+                EXPORT  CAN1_IRQHandler         [WEAK]
+                EXPORT  ATIMER_IRQHandler       [WEAK]
+                EXPORT  RTC_IRQHandler          [WEAK]
+                EXPORT  WDT_IRQHandler          [WEAK]
+                EXPORT  CAN0_IRQHandler         [WEAK]
+                EXPORT  QEI_IRQHandler          [WEAK]
+
+DAC_IRQHandler
+DMA_IRQHandler
+FLASHEEPROM_IRQHandler
+ETH_IRQHandler
+SDIO_IRQHandler
+LCD_IRQHandler
+USB0_IRQHandler
+USB1_IRQHandler
+SCT_IRQHandler
+RIT_IRQHandler
+TIMER0_IRQHandler
+TIMER1_IRQHandler
+TIMER2_IRQHandler
+TIMER3_IRQHandler
+MCPWM_IRQHandler
+ADC0_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+ADC1_IRQHandler
+SSP0_IRQHandler
+SSP1_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+I2S0_IRQHandler
+I2S1_IRQHandler
+GPIO0_IRQHandler
+GPIO1_IRQHandler
+GPIO2_IRQHandler
+GPIO3_IRQHandler
+GPIO4_IRQHandler
+GPIO5_IRQHandler
+GPIO6_IRQHandler
+GPIO7_IRQHandler
+GINT0_IRQHandler
+GINT1_IRQHandler
+EVRT_IRQHandler
+CAN1_IRQHandler
+ATIMER_IRQHandler
+RTC_IRQHandler
+WDT_IRQHandler
+CAN0_IRQHandler
+QEI_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END

CMSIS/Pack/Example/Boards/Keil/MCB1800/Blinky/RTE/Device/LPC1857/system_LPC18xx.c

@@ -0,0 +1,901 @@
+/* -----------------------------------------------------------------------------
+ * Copyright (c) 2013 - 2015 ARM Ltd.
+ *
+ * This software is provided 'as-is', without any express or implied warranty.
+ * In no event will the authors be held liable for any damages arising from
+ * the use of this software. Permission is granted to anyone to use this
+ * software for any purpose, including commercial applications, and to alter
+ * it and redistribute it freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software in
+ *    a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ *
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ *
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * $Date:        26. August 2015
+ * $Revision:    V5.0.1
+ *
+ * Project:      NXP LPC18xx System initialization
+ * -------------------------------------------------------------------------- */
+
+#include "LPC18xx.h"
+
+/*----------------------------------------------------------------------------
+  This file configures the clocks as follows:
+ -----------------------------------------------------------------------------
+ Clock Unit  |  Output clock  |  Source clock  |          Note
+ -----------------------------------------------------------------------------
+   PLL0USB   |    480 MHz     |      XTAL      | External crystal @ 12 MHz
+ -----------------------------------------------------------------------------
+    PLL1     |    180 MHz     |      XTAL      | External crystal @ 12 MHz
+ -----------------------------------------------------------------------------
+    CPU      |    180 MHz     |      PLL1      | CPU Clock ==  BASE_M4_CLK
+ -----------------------------------------------------------------------------
+   IDIV A    |     60 MHz     |      PLL1      | To the USB1 peripheral
+ -----------------------------------------------------------------------------
+   IDIV B    |     25 MHz     |   ENET_TX_CLK  | ENET_TX_CLK @ 50MHz
+ -----------------------------------------------------------------------------
+   IDIV C    |     12 MHz     |      IRC       | Internal oscillator @ 12 MHz
+ -----------------------------------------------------------------------------
+   IDIV D    |     12 MHz     |      IRC       | Internal oscillator @ 12 MHz
+ -----------------------------------------------------------------------------
+   IDIV E    |    5.3 MHz     |      PLL1      | To the LCD controller
+ -----------------------------------------------------------------------------*/
+
+
+/*----------------------------------------------------------------------------
+  Clock source selection definitions (do not change)
+ *----------------------------------------------------------------------------*/
+#define CLK_SRC_32KHZ       0x00
+#define CLK_SRC_IRC         0x01
+#define CLK_SRC_ENET_RX     0x02
+#define CLK_SRC_ENET_TX     0x03
+#define CLK_SRC_GP_CLKIN    0x04
+#define CLK_SRC_XTAL        0x06
+#define CLK_SRC_PLL0U       0x07
+#define CLK_SRC_PLL0A       0x08
+#define CLK_SRC_PLL1        0x09
+#define CLK_SRC_IDIVA       0x0C
+#define CLK_SRC_IDIVB       0x0D
+#define CLK_SRC_IDIVC       0x0E
+#define CLK_SRC_IDIVD       0x0F
+#define CLK_SRC_IDIVE       0x10
+
+
+/*----------------------------------------------------------------------------
+  Define external input frequency values
+ *----------------------------------------------------------------------------*/
+#define CLK_32KHZ            32768UL    /* 32 kHz oscillator frequency        */
+#define CLK_IRC           12000000UL    /* Internal oscillator frequency      */
+#define CLK_ENET_RX       50000000UL    /* Ethernet Rx frequency              */
+#define CLK_ENET_TX       50000000UL    /* Ethernet Tx frequency              */
+#define CLK_GP_CLKIN      12000000UL    /* General purpose clock input freq.  */
+#define CLK_XTAL          12000000UL    /* Crystal oscilator frequency        */
+
+
+/*----------------------------------------------------------------------------
+  Define clock sources
+ *----------------------------------------------------------------------------*/
+#define PLL1_CLK_SEL      CLK_SRC_XTAL    /* PLL1 input clock: XTAL           */
+#define PLL0USB_CLK_SEL   CLK_SRC_XTAL    /* PLL0USB input clock: XTAL        */
+#define IDIVA_CLK_SEL     CLK_SRC_PLL1    /* IDIVA input clock: PLL1          */
+#define IDIVB_CLK_SEL     CLK_SRC_ENET_TX /* IDIVB input clock: ENET TX       */
+#define IDIVC_CLK_SEL     CLK_SRC_IRC     /* IDIVC input clock: IRC           */
+#define IDIVD_CLK_SEL     CLK_SRC_IRC     /* IDIVD input clock: IRC           */
+#define IDIVE_CLK_SEL     CLK_SRC_PLL1    /* IDIVD input clock: PLL1          */
+
+
+/*----------------------------------------------------------------------------
+  Configure integer divider values
+ *----------------------------------------------------------------------------*/
+#define IDIVA_IDIV        2             /* Divide input clock by 3            */
+#define IDIVB_IDIV        1             /* Divide input clock by 2            */
+#define IDIVC_IDIV        0             /* Divide input clock by 1            */
+#define IDIVD_IDIV        0             /* Divide input clock by 1            */
+#define IDIVE_IDIV       33             /* Divide input clock by 34           */
+
+
+/*----------------------------------------------------------------------------
+  Define CPU clock input
+ *----------------------------------------------------------------------------*/
+#define CPU_CLK_SEL       CLK_SRC_PLL1  /* Default CPU clock source is PLL1   */
+
+
+/*----------------------------------------------------------------------------
+  Configure external memory controller options
+ *----------------------------------------------------------------------------*/
+#define USE_EXT_STAT_MEM_CS0 1          /* Use ext. static  memory with CS0   */
+#define USE_EXT_DYN_MEM_CS0  1          /* Use ext. dynamic memory with CS0   */
+
+
+/*----------------------------------------------------------------------------
+ * Configure PLL1
+ *----------------------------------------------------------------------------
+ * Integer mode:
+ *    - PLL1_DIRECT = 0 (Post divider enabled)
+ *    - PLL1_FBSEL  = 1 (Feedback divider runs from PLL output)
+ *    - Output frequency:
+ *                        FCLKOUT = (FCLKIN / N) * M
+ *                        FCCO    = FCLKOUT * 2 * P
+ *
+ * Non-integer:
+ *    - PLL1_DIRECT = 0 (Post divider enabled)
+ *    - PLL1_FBSEL  = 0 (Feedback divider runs from CCO clock)
+ *    - Output frequency:
+ *                        FCLKOUT = (FCLKIN / N) * M / (2 * P)
+ *                        FCCO    = FCLKOUT * 2 * P
+ *
+ * Direct mode:
+ *    - PLL1_DIRECT = 1         (Post divider disabled)
+ *    - PLL1_FBSEL  = dont care (Feedback divider runs from CCO clock)
+ *    - Output frequency:
+ *                        FCLKOUT = (FCLKIN / N) * M
+ *                        FCCO    = FCLKOUT
+ *
+ *----------------------------------------------------------------------------
+ * PLL1 requirements:
+ * | Frequency |  Minimum  |  Maximum  |               Note                   |
+ * |  FCLKIN   |    1MHz   |   25MHz   |   Clock source is external crystal   |
+ * |  FCLKIN   |    1MHz   |   50MHz   |                                      |
+ * |   FCCO    |  156MHz   |  320MHz   |                                      |
+ * |  FCLKOUT  | 9.75MHz   |  320MHz   |                                      |
+ *----------------------------------------------------------------------------
+ * Configuration examples:
+ * | Fclkout |  Fcco  |  N  |  M  |  P  | DIRECT | FBSEL | BYPASS |
+ * |  36MHz | 288MHz |  1  |  24 |  4  |   0    |   0   |    0   |
+ * |  72MHz | 288MHz |  1  |  24 |  2  |   0    |   0   |    0   |
+ * | 100MHz | 200MHz |  3  |  50 |  1  |   0    |   0   |    0   |
+ * | 120MHz | 240MHz |  1  |  20 |  1  |   0    |   0   |    0   |
+ * | 160MHz | 160MHz |  3  |  40 |  x  |   1    |   0   |    0   |
+ * | 180MHz | 180MHz |  1  |  15 |  x  |   1    |   0   |    0   |
+ *----------------------------------------------------------------------------
+ * Relations beetwen PLL dividers and definitions:
+ * N = PLL1_NSEL + 1,     M = PLL1_MSEL + 1,     P = 2 ^ PLL1_PSEL
+ *----------------------------------------------------------------------------*/
+
+/* PLL1 output clock: 180MHz, Fcco: 180MHz, N = 1, M = 15, P = x              */
+#define PLL1_NSEL   0           /* Range [0 -   3]: Pre-divider ratio N       */
+#define PLL1_MSEL  14           /* Range [0 - 255]: Feedback-divider ratio M  */
+#define PLL1_PSEL   0           /* Range [0 -   3]: Post-divider ratio P      */
+
+#define PLL1_BYPASS 0           /* 0: Use PLL, 1: PLL is bypassed             */
+#define PLL1_DIRECT 1           /* 0: Use PSEL, 1: Don't use PSEL             */
+#define PLL1_FBSEL  0           /* 0: FCCO is used as PLL feedback            */
+                                /* 1: FCLKOUT is used as PLL feedback         */
+
+
+/*----------------------------------------------------------------------------
+ * Configure PLL0USB
+ *----------------------------------------------------------------------------
+ *
+ *   Normal operating mode without post-divider and without pre-divider
+ *    - PLL0USB_DIRECTI = 1
+ *    - PLL0USB_DIRECTO = 1
+ *    - PLL0USB_BYPASS  = 0
+ *    - Output frequency:
+ *                        FOUT = FIN * 2 * M
+ *                        FCCO = FOUT
+ *
+ *   Normal operating mode with post-divider and without pre-divider
+ *    - PLL0USB_DIRECTI = 1
+ *    - PLL0USB_DIRECTO = 0
+ *    - PLL0USB_BYPASS  = 0
+ *    - Output frequency:
+ *                        FOUT = FIN * (M / P)
+ *                        FCCO = FOUT * 2 * P
+ *
+ *   Normal operating mode without post-divider and with pre-divider
+ *    - PLL0USB_DIRECTI = 0
+ *    - PLL0USB_DIRECTO = 1
+ *    - PLL0USB_BYPASS  = 0
+ *    - Output frequency:
+ *                        FOUT = FIN * 2 * M / N
+ *                        FCCO = FOUT
+ *
+ *   Normal operating mode with post-divider and with pre-divider
+ *    - PLL0USB_DIRECTI = 0
+ *    - PLL0USB_DIRECTO = 0
+ *    - PLL0USB_BYPASS  = 0
+ *    - Output frequency:
+ *                        FOUT = FIN * M / (P * N)
+ *                        FCCO = FOUT * 2 * P
+ *----------------------------------------------------------------------------
+ * PLL0 requirements:
+ * | Frequency |  Minimum  |  Maximum  |               Note                   |
+ * |  FCLKIN   |   14kHz   |   25MHz   |   Clock source is external crystal   |
+ * |  FCLKIN   |   14kHz   |  150MHz   |                                      |
+ * |   FCCO    |  275MHz   |  550MHz   |                                      |
+ * |  FCLKOUT  |  4.3MHz   |  550MHz   |                                      |
+ *----------------------------------------------------------------------------
+ * Configuration examples:
+ * | Fclkout |  Fcco  |  N  |  M  |  P  | DIRECTI | DIRECTO | BYPASS |
+ * | 120MHz | 480MHz |  x  |  20 |  2  |    1    |    0    |    0   |
+ * | 480MHz | 480MHz |  1  |  20 |  1  |    1    |    1    |    0   |
+ *----------------------------------------------------------------------------*/
+
+/* PLL0USB output clock: 480MHz, Fcco: 480MHz, N = 1, M = 20, P = 1           */
+#define PLL0USB_N       1       /* Range [1 -  256]: Pre-divider              */
+#define PLL0USB_M      20       /* Range [1 - 2^15]: Feedback-divider         */
+#define PLL0USB_P       1       /* Range [1 -   32]: Post-divider             */
+
+#define PLL0USB_DIRECTI 1       /* 0: Use N_DIV, 1: Don't use N_DIV           */
+#define PLL0USB_DIRECTO 1       /* 0: Use P_DIV, 1: Don't use P_DIV           */
+#define PLL0USB_BYPASS  0       /* 0: Use PLL, 1: PLL is bypassed             */
+
+
+/*----------------------------------------------------------------------------
+  End of configuration
+ *----------------------------------------------------------------------------*/
+
+/* PLL0 Setting Check */
+#if (PLL0USB_BYPASS == 0)
+ #if (PLL0USB_CLK_SEL == CLK_SRC_XTAL)
+  #define PLL0USB_CLKIN CLK_XTAL
+ #else
+  #define PLL0USB_CLKIN CLK_IRC
+ #endif
+
+ #if   ((PLL0USB_DIRECTI == 1) && (PLL0USB_DIRECTO == 1)) /* Mode 1a          */
+  #define PLL0USB_FOUT (PLL0USB_CLKIN * 2 * PLL0USB_M)
+  #define PLL0USB_FCCO (PLL0USB_FOUT)
+ #elif ((PLL0USB_DIRECTI == 1) && (PLL0USB_DIRECTO == 0)) /* Mode 1b          */
+  #define PLL0USB_FOUT (PLL0USB_CLKIN * PLL0USB_M / PLL0USB_P)
+  #define PLL0USB_FCCO (PLL0USB_FOUT * 2 * PLL0USB_P)
+ #elif ((PLL0USB_DIRECTI == 0) && (PLL0USB_DIRECTO == 1)) /* Mode 1c          */
+  #define PLL0USB_FOUT (PLL0USB_CLKIN * 2 * PLL0USB_M / PLL0USB_N)
+  #define PLL0USB_FCCO (PLL0USB_FOUT)
+ #else                                                    /* Mode 1d          */
+  #define PLL0USB_FOUT (PLL0USB_CLKIN * PLL0USB_M / (PLL0USB_P * PLL0USB_N))
+  #define PLL0USB_FCCO (PLL0USB_FOUT * 2 * PLL0USB_P)
+ #endif
+
+ #if (PLL0USB_FCCO < 275000000UL || PLL0USB_FCCO > 550000000UL)
+  #error "PLL0USB Fcco frequency out of range! (275MHz >= Fcco <= 550MHz)"
+ #endif
+ #if (PLL0USB_FOUT < 4300000UL || PLL0USB_FOUT > 550000000UL)
+  #error "PLL0USB output frequency out of range! (4.3MHz >= Fclkout <= 550MHz)"
+ #endif
+#endif
+
+/* PLL1 Setting Check */
+#if (PLL1_BYPASS == 0)
+ #if (PLL1_CLK_SEL == CLK_SRC_XTAL)
+  #define PLL1_CLKIN CLK_XTAL
+ #else
+  #define PLL1_CLKIN CLK_IRC
+ #endif
+
+ #if   (PLL1_DIRECT == 1)               /* Direct Mode                        */
+  #define PLL1_FCCO ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
+  #define PLL1_FOUT ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
+ #elif (PLL1_FBSEL  == 1)               /* Integer Mode                       */
+  #define PLL1_FCCO ((2 * (1 << PLL1_PSEL)) * (PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
+  #define PLL1_FOUT ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
+ #else                                  /* Noninteger Mode                    */
+  #define PLL1_FCCO ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
+  #define PLL1_FOUT (PLL1_FCCO / (2 * (1 << PLL1_PSEL)))
+ #endif
+ #if (PLL1_FCCO < 156000000UL || PLL1_FCCO > 320000000UL)
+  #error "PLL1 Fcco frequency out of range! (156MHz >= Fcco <= 320MHz)"
+ #endif
+ #if (PLL1_FOUT < 9750000UL || PLL1_FOUT > 204000000UL)
+  #error "PLL1 output frequency out of range! (9.75MHz >= Fclkout <= 204MHz)"
+ #endif
+#endif
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = CLK_IRC;    /* System Clock Frequency (Core Clock) */
+
+
+/******************************************************************************
+ * SetClock
+ ******************************************************************************/
+void SetClock (void) {
+  uint32_t x, i;
+  uint32_t selp, seli;
+
+  /* Set flash wait states to maximum                                         */
+  LPC_EMC->STATICWAITRD0  = 0x1F;
+
+  /* Switch BASE_M3_CLOCK to IRC                                              */
+  LPC_CGU->BASE_M3_CLK = (0x01        << 11) |  /* Autoblock En               */
+                         (CLK_SRC_IRC << 24) ;  /* Set clock source           */
+
+  /* Configure input to crystal oscilator                                     */
+  LPC_CGU->XTAL_OSC_CTRL = (0 << 0) |   /* Enable oscillator-pad              */
+                           (0 << 1) |   /* Operation with crystal connected   */
+                           (0 << 2) ;   /* Low-frequency mode                 */
+
+  /* Wait ~250us @ 12MHz */
+  for (i = 1500; i; i--);
+
+#if (USE_SPIFI)
+/* configure SPIFI clk to IRC via IDIVA (later IDIVA is configured to PLL1/3) */
+  LPC_CGU->IDIVA_CTRL     = (0              <<  0) |  /* Disable Power-down   */
+                            (0              <<  2) |  /* IDIV                 */
+                            (1              << 11) |  /* Autoblock En         */
+                            (CLK_SRC_IRC    << 24) ;  /* Clock source         */
+
+  LPC_CGU->BASE_SPIFI_CLK = (0              <<  0) |  /* Disable Power-down   */
+                            (0              <<  2) |  /* IDIV                 */
+                            (1              << 11) |  /* Autoblock En         */
+                            (CLK_SRC_IDIVA  << 24) ;  /* Clock source         */
+#endif
+
+/*----------------------------------------------------------------------------
+  PLL1 Setup
+ *----------------------------------------------------------------------------*/
+  /* Power down PLL                                                           */
+  LPC_CGU->PLL1_CTRL |= 1;
+
+#if ((PLL1_FOUT > 110000000UL) && (CPU_CLK_SEL == CLK_SRC_PLL1))
+  /* To run at full speed, CPU must first run at an intermediate speed        */
+  LPC_CGU->PLL1_CTRL = (0            << 0) | /* PLL1 Enabled                  */
+                       (PLL1_BYPASS  << 1) | /* CCO out sent to post-dividers */
+                       (PLL1_FBSEL   << 6) | /* PLL output used as feedback   */
+                       (0            << 7) | /* Direct on/off                 */
+                       (PLL1_PSEL    << 8) | /* PSEL                          */
+                       (0            << 11)| /* Autoblock Disabled            */
+                       (PLL1_NSEL    << 12)| /* NSEL                          */
+                       (PLL1_MSEL    << 16)| /* MSEL                          */
+                       (PLL1_CLK_SEL << 24); /* Clock source                  */
+  /* Wait for lock                                                            */
+  while (!(LPC_CGU->PLL1_STAT & 1));
+
+  /* CPU base clock is in the mid frequency range before final clock set      */
+  LPC_CGU->BASE_M3_CLK     = (0x01 << 11) |  /* Autoblock En                  */
+                             (0x09 << 24) ;  /* Clock source: PLL1            */
+
+  /* Max. BASE_M3_CLK frequency here is 102MHz, wait at least 20us */
+  for (i = 1050; i; i--);                    /* Wait minimum 2100 cycles      */
+#endif
+  /* Configure PLL1                                                           */
+  LPC_CGU->PLL1_CTRL = (0            << 0) | /* PLL1 Enabled                  */
+                       (PLL1_BYPASS  << 1) | /* CCO out sent to post-dividers */
+                       (PLL1_FBSEL   << 6) | /* PLL output used as feedback   */
+                       (PLL1_DIRECT  << 7) | /* Direct on/off                 */
+                       (PLL1_PSEL    << 8) | /* PSEL                          */
+                       (1            << 11)| /* Autoblock En                  */
+                       (PLL1_NSEL    << 12)| /* NSEL                          */
+                       (PLL1_MSEL    << 16)| /* MSEL                          */
+                       (PLL1_CLK_SEL << 24); /* Clock source                  */
+
+  /* Wait for lock                                                            */
+  while (!(LPC_CGU->PLL1_STAT & 1));
+
+  /* Set CPU base clock source                                                */
+  LPC_CGU->BASE_M3_CLK = (0x01        << 11) |  /* Autoblock En               */
+                         (CPU_CLK_SEL << 24) ;  /* Set clock source           */
+
+/*----------------------------------------------------------------------------
+  PLL0USB Setup
+ *----------------------------------------------------------------------------*/
+
+  /* Power down PLL0USB                                                       */
+  LPC_CGU->PLL0USB_CTRL  |= 1;
+
+  /* M divider                                                                */
+  x = 0x00004000;
+  switch (PLL0USB_M) {
+    case 0:  x = 0xFFFFFFFF;
+      break;
+    case 1:  x = 0x00018003;
+      break;
+    case 2:  x = 0x00010003;
+      break;
+    default:
+      for (i = PLL0USB_M; i <= 0x8000; i++) {
+        x = (((x ^ (x >> 1)) & 1) << 14) | ((x >> 1) & 0x3FFF);
+      }
+  }
+
+  if (PLL0USB_M < 60) selp = (PLL0USB_M >> 1) + 1;
+  else        selp = 31;
+
+  if      (PLL0USB_M > 16384) seli = 1;
+  else if (PLL0USB_M >  8192) seli = 2;
+  else if (PLL0USB_M >  2048) seli = 4;
+  else if (PLL0USB_M >=  501) seli = 8;
+  else if (PLL0USB_M >=   60) seli = 4 * (1024 / (PLL0USB_M + 9));
+  else                        seli = (PLL0USB_M & 0x3C) + 4;
+  LPC_CGU->PLL0USB_MDIV   =  (selp   << 17) |
+                             (seli   << 22) |
+                             (x      <<  0);
+
+  /* N divider                                                                */
+  x = 0x80;
+  switch (PLL0USB_N) {
+    case 0:  x = 0xFFFFFFFF;
+      break;
+    case 1:  x = 0x00000302;
+      break;
+    case 2:  x = 0x00000202;
+      break;
+    default:
+      for (i = PLL0USB_N; i <= 0x0100; i++) {
+        x =(((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F);
+      }
+  }
+  LPC_CGU->PLL0USB_NP_DIV = (x << 12);
+
+  /* P divider                                                                */
+  x = 0x10;
+  switch (PLL0USB_P) {
+    case 0:  x = 0xFFFFFFFF;
+      break;
+    case 1:  x = 0x00000062;
+      break;
+    case 2:  x = 0x00000042;
+      break;
+    default:
+      for (i = PLL0USB_P; i <= 0x200; i++) {
+        x = (((x ^ (x >> 2)) & 1) << 4) | ((x >> 1) &0x0F);
+      }
+  }
+  LPC_CGU->PLL0USB_NP_DIV |= x;
+
+  LPC_CGU->PLL0USB_CTRL  = (PLL0USB_CLK_SEL   << 24) | /* Clock source sel    */
+                           (1                 << 11) | /* Autoblock En        */
+                           (1                 << 4 ) | /* PLL0USB clock en    */
+                           (PLL0USB_DIRECTO   << 3 ) | /* Direct output       */
+                           (PLL0USB_DIRECTI   << 2 ) | /* Direct input        */
+                           (PLL0USB_BYPASS    << 1 ) | /* PLL bypass          */
+                           (0                 << 0 ) ; /* PLL0USB Enabled     */
+  while (!(LPC_CGU->PLL0USB_STAT & 1));
+
+
+/*----------------------------------------------------------------------------
+  Integer divider Setup
+ *----------------------------------------------------------------------------*/
+
+  /* Configure integer dividers                                               */
+  LPC_CGU->IDIVA_CTRL = (0              <<  0) |  /* Disable Power-down       */
+                        (IDIVA_IDIV     <<  2) |  /* IDIV                     */
+                        (1              << 11) |  /* Autoblock En             */
+                        (IDIVA_CLK_SEL  << 24) ;  /* Clock source             */
+
+  LPC_CGU->IDIVB_CTRL = (0              <<  0) |  /* Disable Power-down       */
+                        (IDIVB_IDIV     <<  2) |  /* IDIV                     */
+                        (1              << 11) |  /* Autoblock En             */
+                        (IDIVB_CLK_SEL  << 24) ;  /* Clock source             */
+
+  LPC_CGU->IDIVC_CTRL = (0              <<  0) |  /* Disable Power-down       */
+                        (IDIVC_IDIV     <<  2) |  /* IDIV                     */
+                        (1              << 11) |  /* Autoblock En             */
+                        (IDIVC_CLK_SEL  << 24) ;  /* Clock source             */
+
+  LPC_CGU->IDIVD_CTRL = (0              <<  0) |  /* Disable Power-down       */
+                        (IDIVD_IDIV     <<  2) |  /* IDIV                     */
+                        (1              << 11) |  /* Autoblock En             */
+                        (IDIVD_CLK_SEL  << 24) ;  /* Clock source             */
+
+  LPC_CGU->IDIVE_CTRL = (0              <<  0) |  /* Disable Power-down       */
+                        (IDIVE_IDIV     <<  2) |  /* IDIV                     */
+                        (1              << 11) |  /* Autoblock En             */
+                        (IDIVE_CLK_SEL  << 24) ;  /* Clock source             */
+}
+
+
+/*----------------------------------------------------------------------------
+  Approximate delay function (must be used after SystemCoreClockUpdate() call)
+ *----------------------------------------------------------------------------*/
+#define CPU_NANOSEC(x) (((uint64_t)(x) * SystemCoreClock)/1000000000)
+
+static void WaitUs (uint32_t us) {
+  uint32_t cyc = us * CPU_NANOSEC(1000)/4;
+  while(cyc--);
+}
+
+
+/*----------------------------------------------------------------------------
+  External Memory Controller Definitions
+ *----------------------------------------------------------------------------*/
+#define SDRAM_ADDR_BASE 0x28000000      /* SDRAM base address                 */
+/* Write Mode register macro                                                  */
+#define WR_MODE(x) (*((volatile uint32_t *)(SDRAM_ADDR_BASE | (x))))
+
+/* Pin Settings: Glith filter DIS, Input buffer EN, Fast Slew Rate, No Pullup */
+#define EMC_PIN_SET ((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4))
+#define EMC_NANOSEC(ns, freq, div) (((uint64_t)(ns) * ((freq)/((div)+1)))/1000000000)
+
+#define EMC_CLK_DLY_TIM_2  (0x7777)     /* 3.5 ns delay for the EMC clock out */
+#define EMC_CLK_DLY_TIM_0  (0x0000)     /* No delay for the EMC clock out     */
+
+typedef void (*emcdivby2) (volatile uint32_t *creg6, volatile uint32_t *emcdiv, uint32_t cfg);
+
+const uint16_t emcdivby2_opc[] =  {
+  0x6803,        /*      LDR  R3,[R0,#0]      ; Load CREG6          */
+  0xF443,0x3380, /*      ORR  R3,R3,#0x10000  ; Set Divided by 2    */
+  0x6003,        /*      STR  R3,[R0,#0]      ; Store CREG6         */
+  0x600A,        /*      STR  R2,[R1,#0]      ; EMCDIV_CFG = cfg    */
+  0x684B,        /* loop LDR  R3,[R1,#4]      ; Load EMCDIV_STAT    */
+  0x07DB,        /*      LSLS R3,R3,#31       ; Check EMCDIV_STAT.0 */
+  0xD0FC,        /*      BEQ  loop            ; Jump if 0           */
+  0x4770,        /*      BX   LR              ; Exit                */
+  0,
+};
+
+#define        emcdivby2_szw ((sizeof(emcdivby2_opc)+3)/4)
+#define        emcdivby2_ram 0x10000000
+
+/*----------------------------------------------------------------------------
+  Initialize external memory controller
+ *----------------------------------------------------------------------------*/
+
+void SystemInit_ExtMemCtl (void) {
+  uint32_t emcdivby2_buf[emcdivby2_szw];
+  uint32_t div, n;
+
+  /* Select and enable EMC branch clock */
+  LPC_CCU1->CLK_M3_EMC_CFG = (1 << 2) | (1 << 1) | 1;
+  while (!(LPC_CCU1->CLK_M3_EMC_STAT & 1));
+
+  /* Set EMC clock output delay */
+  if (SystemCoreClock < 80000000UL) {
+    LPC_SCU->EMCDELAYCLK = EMC_CLK_DLY_TIM_0; /* No EMC clock out delay       */
+  }
+  else {
+    LPC_SCU->EMCDELAYCLK = EMC_CLK_DLY_TIM_2; /* 2.0 ns EMC clock out delay   */
+  }
+
+  /* Configure EMC port pins */
+  LPC_SCU->SFSP1_0  = EMC_PIN_SET | 2;  /* P1_0:  A5                          */
+  LPC_SCU->SFSP1_1  = EMC_PIN_SET | 2;  /* P1_1:  A6                          */
+  LPC_SCU->SFSP1_2  = EMC_PIN_SET | 2;  /* P1_2:  A7                          */
+  LPC_SCU->SFSP1_3  = EMC_PIN_SET | 3;  /* P1_3:  OE                          */
+  LPC_SCU->SFSP1_4  = EMC_PIN_SET | 3;  /* P1_4:  BLS0                        */
+  LPC_SCU->SFSP1_5  = EMC_PIN_SET | 3;  /* P1_5:  CS0                         */
+  LPC_SCU->SFSP1_6  = EMC_PIN_SET | 3;  /* P1_6:  WE                          */
+  LPC_SCU->SFSP1_7  = EMC_PIN_SET | 3;  /* P1_7:  D0                          */
+  LPC_SCU->SFSP1_8  = EMC_PIN_SET | 3;  /* P1_8:  D1                          */
+  LPC_SCU->SFSP1_9  = EMC_PIN_SET | 3;  /* P1_9:  D2                          */
+  LPC_SCU->SFSP1_10 = EMC_PIN_SET | 3;  /* P1_10: D3                          */
+  LPC_SCU->SFSP1_11 = EMC_PIN_SET | 3;  /* P1_11: D4                          */
+  LPC_SCU->SFSP1_12 = EMC_PIN_SET | 3;  /* P1_12: D5                          */
+  LPC_SCU->SFSP1_13 = EMC_PIN_SET | 3;  /* P1_13: D6                          */
+  LPC_SCU->SFSP1_14 = EMC_PIN_SET | 3;  /* P1_14: D7                          */
+
+  LPC_SCU->SFSP2_0  = EMC_PIN_SET | 2;  /* P2_0:  A13                         */
+  LPC_SCU->SFSP2_1  = EMC_PIN_SET | 2;  /* P2_1:  A12                         */
+  LPC_SCU->SFSP2_2  = EMC_PIN_SET | 2;  /* P2_2:  A11                         */
+  LPC_SCU->SFSP2_6  = EMC_PIN_SET | 2;  /* P2_6:  A10                         */
+  LPC_SCU->SFSP2_7  = EMC_PIN_SET | 3;  /* P2_7:  A9                          */
+  LPC_SCU->SFSP2_8  = EMC_PIN_SET | 3;  /* P2_8:  A8                          */
+  LPC_SCU->SFSP2_9  = EMC_PIN_SET | 3;  /* P2_9:  A0                          */
+  LPC_SCU->SFSP2_10 = EMC_PIN_SET | 3;  /* P2_10: A1                          */
+  LPC_SCU->SFSP2_11 = EMC_PIN_SET | 3;  /* P2_11: A2                          */
+  LPC_SCU->SFSP2_12 = EMC_PIN_SET | 3;  /* P2_12: A3                          */
+  LPC_SCU->SFSP2_13 = EMC_PIN_SET | 3;  /* P2_13: A4                          */
+
+  LPC_SCU->SFSP5_0  = EMC_PIN_SET | 2;  /* P5_0:  D12                         */
+  LPC_SCU->SFSP5_1  = EMC_PIN_SET | 2;  /* P5_1:  D13                         */
+  LPC_SCU->SFSP5_2  = EMC_PIN_SET | 2;  /* P5_2:  D14                         */
+  LPC_SCU->SFSP5_3  = EMC_PIN_SET | 2;  /* P5_3:  D15                         */
+  LPC_SCU->SFSP5_4  = EMC_PIN_SET | 2;  /* P5_4:  D8                          */
+  LPC_SCU->SFSP5_5  = EMC_PIN_SET | 2;  /* P5_5:  D9                          */
+  LPC_SCU->SFSP5_6  = EMC_PIN_SET | 2;  /* P5_6:  D10                         */
+  LPC_SCU->SFSP5_7  = EMC_PIN_SET | 2;  /* P5_7:  D11                         */
+
+  LPC_SCU->SFSP6_1  = EMC_PIN_SET | 1;  /* P6_1:  DYCS1                       */
+  LPC_SCU->SFSP6_2  = EMC_PIN_SET | 1;  /* P6_3:  CKEOUT1                     */
+  LPC_SCU->SFSP6_3  = EMC_PIN_SET | 3;  /* P6_3:  CS1                         */
+  LPC_SCU->SFSP6_4  = EMC_PIN_SET | 3;  /* P6_4:  CAS                         */
+  LPC_SCU->SFSP6_5  = EMC_PIN_SET | 3;  /* P6_5:  RAS                         */
+  LPC_SCU->SFSP6_6  = EMC_PIN_SET | 1;  /* P6_6:  BLS1                        */
+  LPC_SCU->SFSP6_7  = EMC_PIN_SET | 1;  /* P6_7:  A15                         */
+  LPC_SCU->SFSP6_8  = EMC_PIN_SET | 1;  /* P6_8:  A14                         */
+  LPC_SCU->SFSP6_9  = EMC_PIN_SET | 3;  /* P6_9:  DYCS0                       */
+  LPC_SCU->SFSP6_10 = EMC_PIN_SET | 3;  /* P6_10: DQMOUT1                     */
+  LPC_SCU->SFSP6_11 = EMC_PIN_SET | 3;  /* P6_11: CKEOUT0                     */
+  LPC_SCU->SFSP6_12 = EMC_PIN_SET | 3;  /* P6_12: DQMOUT0                     */
+
+  LPC_SCU->SFSPA_4  = EMC_PIN_SET | 3;  /* PA_4:  A23                         */
+
+  LPC_SCU->SFSPD_0  = EMC_PIN_SET | 2;  /* PD_0:  DQMOUT2                     */
+  LPC_SCU->SFSPD_1  = EMC_PIN_SET | 2;  /* PD_1:  CKEOUT2                     */
+  LPC_SCU->SFSPD_2  = EMC_PIN_SET | 2;  /* PD_2:  D16                         */
+  LPC_SCU->SFSPD_3  = EMC_PIN_SET | 2;  /* PD_3:  D17                         */
+  LPC_SCU->SFSPD_4  = EMC_PIN_SET | 2;  /* PD_4:  D18                         */
+  LPC_SCU->SFSPD_5  = EMC_PIN_SET | 2;  /* PD_5:  D19                         */
+  LPC_SCU->SFSPD_6  = EMC_PIN_SET | 2;  /* PD_6:  D20                         */
+  LPC_SCU->SFSPD_7  = EMC_PIN_SET | 2;  /* PD_7:  D21                         */
+  LPC_SCU->SFSPD_8  = EMC_PIN_SET | 2;  /* PD_8:  D22                         */
+  LPC_SCU->SFSPD_9  = EMC_PIN_SET | 2;  /* PD_9:  D23                         */
+  LPC_SCU->SFSPD_10 = EMC_PIN_SET | 2;  /* PD_10: BLS3                        */
+  LPC_SCU->SFSPD_11 = EMC_PIN_SET | 2;  /* PD_11: CS3                         */
+  LPC_SCU->SFSPD_12 = EMC_PIN_SET | 2;  /* PD_12: CS2                         */
+  LPC_SCU->SFSPD_13 = EMC_PIN_SET | 2;  /* PD_13: BLS2                        */
+  LPC_SCU->SFSPD_14 = EMC_PIN_SET | 2;  /* PD_14: DYCS2                       */
+  LPC_SCU->SFSPD_15 = EMC_PIN_SET | 2;  /* PD_15: A17                         */
+  LPC_SCU->SFSPD_16 = EMC_PIN_SET | 2;  /* PD_16: A16                         */
+
+  LPC_SCU->SFSPE_0  = EMC_PIN_SET | 3;  /* PE_0:  A18                         */
+  LPC_SCU->SFSPE_1  = EMC_PIN_SET | 3;  /* PE_1:  A19                         */
+  LPC_SCU->SFSPE_2  = EMC_PIN_SET | 3;  /* PE_2:  A20                         */
+  LPC_SCU->SFSPE_3  = EMC_PIN_SET | 3;  /* PE_3:  A21                         */
+  LPC_SCU->SFSPE_4  = EMC_PIN_SET | 3;  /* PE_4:  A22                         */
+  LPC_SCU->SFSPE_5  = EMC_PIN_SET | 3;  /* PE_5:  D24                         */
+  LPC_SCU->SFSPE_6  = EMC_PIN_SET | 3;  /* PE_6:  D25                         */
+  LPC_SCU->SFSPE_7  = EMC_PIN_SET | 3;  /* PE_7:  D26                         */
+  LPC_SCU->SFSPE_8  = EMC_PIN_SET | 3;  /* PE_8:  D27                         */
+  LPC_SCU->SFSPE_9  = EMC_PIN_SET | 3;  /* PE_9:  D28                         */
+  LPC_SCU->SFSPE_10 = EMC_PIN_SET | 3;  /* PE_10: D29                         */
+  LPC_SCU->SFSPE_11 = EMC_PIN_SET | 3;  /* PE_11: D30                         */
+  LPC_SCU->SFSPE_12 = EMC_PIN_SET | 3;  /* PE_12: D31                         */
+  LPC_SCU->SFSPE_13 = EMC_PIN_SET | 3;  /* PE_13: DQMOUT3                     */
+  LPC_SCU->SFSPE_14 = EMC_PIN_SET | 3;  /* PE_14: DYCS3                       */
+  LPC_SCU->SFSPE_15 = EMC_PIN_SET | 3;  /* PE_15: CKEOUT3                     */
+
+  LPC_EMC->CONTROL  = 0x00000001;       /* EMC Enable                         */
+  LPC_EMC->CONFIG   = 0x00000000;       /* Little-endian, Clock Ratio 1:1     */
+
+  div = 0;
+  if (SystemCoreClock > 120000000UL) {
+    /* Use EMC clock divider and EMC clock output delay */
+    div = 1;
+    /* Following code must be executed in RAM to ensure stable operation      */
+    /* LPC_CCU1->CLK_M3_EMCDIV_CFG = (1 << 5) | (1 << 2) | (1 << 1) | 1;      */
+    /* LPC_CREG->CREG6 |= (1 << 16);       // EMC_CLK_DIV divided by 2        */
+    /* while (!(LPC_CCU1->CLK_M3_EMCDIV_STAT & 1));                           */
+
+    /* This code configures EMC clock divider and is executed in RAM          */
+    for (n = 0; n < emcdivby2_szw; n++) {
+      emcdivby2_buf[n] =  *((uint32_t *)emcdivby2_ram + n);
+      *((uint32_t *)emcdivby2_ram + n) = *((uint32_t *)emcdivby2_opc + n);
+    }
+    __ISB();
+    ((emcdivby2 )(emcdivby2_ram+1))(&LPC_CREG->CREG6, &LPC_CCU1->CLK_M3_EMCDIV_CFG, (1 << 5) | (1 << 2) | (1 << 1) | 1);
+    for (n = 0; n < emcdivby2_szw; n++) {
+      *((uint32_t *)emcdivby2_ram + n) = emcdivby2_buf[n];
+    }
+  }
+
+  /* Configure EMC clock-out pins                                             */
+  LPC_SCU->SFSCLK_0 = EMC_PIN_SET | 0;  /* CLK0                               */
+  LPC_SCU->SFSCLK_1 = EMC_PIN_SET | 0;  /* CLK1                               */
+  LPC_SCU->SFSCLK_2 = EMC_PIN_SET | 0;  /* CLK2                               */
+  LPC_SCU->SFSCLK_3 = EMC_PIN_SET | 0;  /* CLK3                               */
+
+  /* Static memory configuration (chip select 0)                              */
+#if (USE_EXT_STAT_MEM_CS0)
+  LPC_EMC->STATICCONFIG0  = (1 <<  7) | /* Byte lane state: use WE signal     */
+                            (2 <<  0) | /* Memory width 32-bit                */
+                            (1 <<  3);  /* Async page mode enable             */
+
+  LPC_EMC->STATICWAITOEN0 = (0 <<  0) ; /* Wait output enable: No delay       */
+
+  LPC_EMC->STATICWAITPAG0 = 2;
+
+  /* Set Static Memory Read Delay for 90ns External NOR Flash                 */
+  LPC_EMC->STATICWAITRD0  = 1 + EMC_NANOSEC(90, SystemCoreClock, div);
+  LPC_EMC->STATICCONFIG0 |= (1 << 19) ; /* Enable buffer                      */
+#endif
+
+  /* Dynamic memory configuration (chip select 0)                             */
+#if (USE_EXT_DYN_MEM_CS0)
+
+  /* Set Address mapping: 128Mb(4Mx32), 4 banks, row len = 12, column len = 8 */
+  LPC_EMC->DYNAMICCONFIG0    = (1 << 14) |  /* AM[14]   = 1                   */
+                               (0 << 12) |  /* AM[12]   = 0                   */
+                               (2 <<  9) |  /* AM[11:9] = 2                   */
+                               (2 <<  7) ;  /* AM[8:7]  = 2                   */
+
+  LPC_EMC->DYNAMICRASCAS0    = 0x00000303;  /* Latency: RAS 3, CAS 3 CCLK cyc.*/
+  LPC_EMC->DYNAMICREADCONFIG = 0x00000001;  /* Command delayed by 1/2 CCLK    */
+
+  LPC_EMC->DYNAMICRP         = EMC_NANOSEC (20, SystemCoreClock, div);
+  LPC_EMC->DYNAMICRAS        = EMC_NANOSEC (42, SystemCoreClock, div);
+  LPC_EMC->DYNAMICSREX       = EMC_NANOSEC (63, SystemCoreClock, div);
+  LPC_EMC->DYNAMICAPR        = EMC_NANOSEC (70, SystemCoreClock, div);
+  LPC_EMC->DYNAMICDAL        = EMC_NANOSEC (70, SystemCoreClock, div);
+  LPC_EMC->DYNAMICWR         = EMC_NANOSEC (30, SystemCoreClock, div);
+  LPC_EMC->DYNAMICRC         = EMC_NANOSEC (63, SystemCoreClock, div);
+  LPC_EMC->DYNAMICRFC        = EMC_NANOSEC (63, SystemCoreClock, div);
+  LPC_EMC->DYNAMICXSR        = EMC_NANOSEC (63, SystemCoreClock, div);
+  LPC_EMC->DYNAMICRRD        = EMC_NANOSEC (14, SystemCoreClock, div);
+  LPC_EMC->DYNAMICMRD        = EMC_NANOSEC (30, SystemCoreClock, div);
+
+  WaitUs (100);
+  LPC_EMC->DYNAMICCONTROL    = 0x00000183;  /* Issue NOP command              */
+  WaitUs (10);
+  LPC_EMC->DYNAMICCONTROL    = 0x00000103;  /* Issue PALL command             */
+  WaitUs (1);
+  LPC_EMC->DYNAMICCONTROL    = 0x00000183;  /* Issue NOP command              */
+  WaitUs (1);
+  LPC_EMC->DYNAMICREFRESH    = EMC_NANOSEC(  200, SystemCoreClock, div) / 16 + 1;
+  WaitUs (10);
+  LPC_EMC->DYNAMICREFRESH    = EMC_NANOSEC(15625, SystemCoreClock, div) / 16 + 1;
+  WaitUs (10);
+  LPC_EMC->DYNAMICCONTROL    = 0x00000083;  /* Issue MODE command             */
+
+  /* Mode register: Burst Length: 4, Burst Type: Sequential, CAS Latency: 3   */
+  WR_MODE(((3 << 4) | 2) << 12);
+
+  WaitUs (10);
+  LPC_EMC->DYNAMICCONTROL    = 0x00000002;  /* Issue NORMAL command           */
+  LPC_EMC->DYNAMICCONFIG0   |= (1 << 19);   /* Enable buffer                  */
+#endif
+}
+
+
+/*----------------------------------------------------------------------------
+  Measure frequency using frequency monitor
+ *----------------------------------------------------------------------------*/
+uint32_t MeasureFreq (uint32_t clk_sel) {
+  uint32_t fcnt, rcnt, fout;
+
+  /* Set register values */
+  LPC_CGU->FREQ_MON &= ~(1 << 23);                /* Stop frequency counters  */
+  LPC_CGU->FREQ_MON  = (clk_sel << 24) | 511;     /* RCNT == 511              */
+  LPC_CGU->FREQ_MON |= (1 << 23);                 /* Start RCNT and FCNT      */
+  while (LPC_CGU->FREQ_MON & (1 << 23)) {
+    fcnt = (LPC_CGU->FREQ_MON >> 9) & 0x3FFF;
+    rcnt = (LPC_CGU->FREQ_MON     ) & 0x01FF;
+    if (fcnt == 0 && rcnt == 0) {
+      return (0);                                 /* No input clock present   */
+    }
+  }
+  fcnt = (LPC_CGU->FREQ_MON >> 9) & 0x3FFF;
+  fout = fcnt * (12000000U/511U);                 /* FCNT * (IRC_CLK / RCNT)  */
+
+  return (fout);
+}
+
+
+/*----------------------------------------------------------------------------
+  Get PLL1 (divider and multiplier) parameters
+ *----------------------------------------------------------------------------*/
+static __inline uint32_t GetPLL1Param (void) {
+  uint32_t ctrl;
+  uint32_t p;
+  uint32_t div, mul;
+
+  ctrl = LPC_CGU->PLL1_CTRL;
+  div = ((ctrl >> 12) & 0x03) + 1;
+  mul = ((ctrl >> 16) & 0xFF) + 1;
+  p = 1 << ((ctrl >>  8) & 0x03);
+
+  if (ctrl & (1 << 1)) {
+    /* Bypass = 1, PLL1 input clock sent to post-dividers */
+    if (ctrl & (1 << 7)) {
+      div *= (2*p);
+    }
+  }
+  else {
+    /* Direct and integer mode */
+    if (((ctrl & (1 << 7)) == 0) && ((ctrl & (1 << 6)) == 0)) {
+      /* Non-integer mode */
+      div *= (2*p);
+    }
+  }
+  return ((div << 8) | (mul));
+}
+
+
+/*----------------------------------------------------------------------------
+  Get input clock source for specified clock generation block
+ *----------------------------------------------------------------------------*/
+int32_t GetClkSel (uint32_t clk_src) {
+  uint32_t reg;
+  int32_t clk_sel = -1;
+
+  switch (clk_src) {
+    case CLK_SRC_IRC:
+    case CLK_SRC_ENET_RX:
+    case CLK_SRC_ENET_TX:
+    case CLK_SRC_GP_CLKIN:
+      return (clk_src);
+
+    case CLK_SRC_32KHZ:
+      return ((LPC_CREG->CREG0 & 0x0A) != 0x02) ? (-1) : (CLK_SRC_32KHZ);
+    case CLK_SRC_XTAL:
+     return  (LPC_CGU->XTAL_OSC_CTRL & 1)       ? (-1) : (CLK_SRC_XTAL);
+
+    case CLK_SRC_PLL0U: reg = LPC_CGU->PLL0USB_CTRL;    break;
+    case CLK_SRC_PLL0A: reg = LPC_CGU->PLL0AUDIO_CTRL;  break;
+    case CLK_SRC_PLL1:  reg = (LPC_CGU->PLL1_STAT & 1) ? (LPC_CGU->PLL1_CTRL) : (0); break;
+
+    case CLK_SRC_IDIVA: reg = LPC_CGU->IDIVA_CTRL;      break;
+    case CLK_SRC_IDIVB: reg = LPC_CGU->IDIVB_CTRL;      break;
+    case CLK_SRC_IDIVC: reg = LPC_CGU->IDIVC_CTRL;      break;
+    case CLK_SRC_IDIVD: reg = LPC_CGU->IDIVD_CTRL;      break;
+    case CLK_SRC_IDIVE: reg = LPC_CGU->IDIVE_CTRL;      break;
+
+    default:
+      return (clk_sel);
+  }
+  if (!(reg & 1)) {
+    clk_sel = (reg >> 24) & 0x1F;
+  }
+  return (clk_sel);
+}
+
+
+/*----------------------------------------------------------------------------
+  Get clock frequency for specified clock source
+ *----------------------------------------------------------------------------*/
+uint32_t GetClockFreq (uint32_t clk_src) {
+  uint32_t tmp;
+  uint32_t mul        =  1;
+  uint32_t div        =  1;
+  uint32_t main_freq  =  0;
+  int32_t  clk_sel    = clk_src;
+
+  do {
+    switch (clk_sel) {
+      case CLK_SRC_32KHZ:    main_freq = CLK_32KHZ;     break;
+      case CLK_SRC_IRC:      main_freq = CLK_IRC;       break;
+      case CLK_SRC_ENET_RX:  main_freq = CLK_ENET_RX;   break;
+      case CLK_SRC_ENET_TX:  main_freq = CLK_ENET_TX;   break;
+      case CLK_SRC_GP_CLKIN: main_freq = CLK_GP_CLKIN;  break;
+      case CLK_SRC_XTAL:     main_freq = CLK_XTAL;      break;
+
+      case CLK_SRC_IDIVA: div *= ((LPC_CGU->IDIVA_CTRL >> 2) & 0x3) + 1; break;
+      case CLK_SRC_IDIVB: div *= ((LPC_CGU->IDIVB_CTRL >> 2) & 0x3) + 1; break;
+      case CLK_SRC_IDIVC: div *= ((LPC_CGU->IDIVC_CTRL >> 2) & 0x3) + 1; break;
+      case CLK_SRC_IDIVD: div *= ((LPC_CGU->IDIVD_CTRL >> 2) & 0x3) + 1; break;
+      case CLK_SRC_IDIVE: div *= ((LPC_CGU->IDIVE_CTRL >> 2) & 0x3) + 1; break;
+
+      case CLK_SRC_PLL0U: /* Not implemented */  break;
+      case CLK_SRC_PLL0A: /* Not implemented */  break;
+
+      case CLK_SRC_PLL1:
+        tmp = GetPLL1Param ();
+        mul *= (tmp     ) & 0xFF;       /* PLL input clock multiplier         */
+        div *= (tmp >> 8) & 0xFF;       /* PLL input clock divider            */
+        break;
+
+      default:
+        return (0);                     /* Clock not running or not supported */
+    }
+    if (main_freq == 0) {
+      clk_sel = GetClkSel (clk_sel);
+    }
+  }
+  while (main_freq == 0);
+
+  return ((main_freq * mul) / div);
+}
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock update
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void) {
+  /* Check BASE_M3_CLK connection */
+  uint32_t base_src = (LPC_CGU->BASE_M3_CLK >> 24) & 0x1F;
+
+  /* Update core clock frequency */
+  SystemCoreClock = GetClockFreq (base_src);
+}
+
+
+extern uint32_t __Vectors;                         /* see startup_LPC18xx.s   */
+
+/*----------------------------------------------------------------------------
+  Initialize the system
+ *----------------------------------------------------------------------------*/
+void SystemInit (void) {
+  /* Disable SysTick timer                                                    */
+  SysTick->CTRL &= ~(SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk);
+
+  /* Set vector table pointer */
+  SCB->VTOR = ((uint32_t)(&__Vectors)) & 0xFFF00000UL;
+
+  /* Configure PLL0 and PLL1, connect CPU clock to selected clock source */
+  SetClock();
+
+  /* Update SystemCoreClock variable */
+  SystemCoreClockUpdate();
+
+  /* Configure External Memory Controller */
+  SystemInit_ExtMemCtl ();
+}

CMSIS/Pack/Example/Boards/Keil/MCB1800/Blinky/RTE/RTE_Components.h

@@ -0,0 +1,15 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'Blinky' 
+ * Target:  'LPC1857 Flash' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+#define RTE_DEVICE_STARTUP_LPC18XX      /* Device Startup for NXP18XX */
+
+#endif /* RTE_COMPONENTS_H */

CMSIS/Pack/Example/Boards/Keil/MCB1800/Blinky_ULp/Abstract.txt

@@ -0,0 +1,48 @@
+The 'Blinky' project is a simple program for the LPC1857
+microcontroller using Keil 'MCB1800' Evaluation Board, compliant
+to Cortex Microcontroller Software Interface Standard (CMSIS v2.0).
+
+It demonstrates the use of ULINKpro Debugger.
+
+Example functionality:                                                   
+ - Clock Settings:
+   - XTAL    =           12.00 MHz
+   - CPU     =          120.00 MHz
+
+ - Sys Timer is used in interrupt mode
+ - LED blink with speed depending on potentiometer position
+ - AD settings: 12 bit resolution
+ - AD value is output onto ITM debug port #0
+
+
+The Blinky program is available in different targets:
+
+  SWO Trace:              configured for on-chip Flash
+                          shows use of LogicAnalyzer, ITM output, Exception Trace
+                          use connector "Cortex Debug + ETM" or "Cortex Debug" or "JTAG"
+
+  TracePort Trace:        configured for on-chip Flash
+                          shows use of LogicAnalyzer, ITM output, Exception Trace
+                          use connector "Cortex Debug + ETM"
+
+  Instruction Trace:      configured for on-chip Flash
+                          shows use of Instruction Trace
+                          use connector "Cortex Debug + ETM"
+
+  Embedded Trace Buffer:  configured for on-chip Flash
+                          shows use of Instruction Trace from the ETB
+                          use connector "Cortex Debug + ETM" or "Cortex Debug" or "JTAG"
+
+
+ULINKpro notes
+--------------
+LPC18xx_TP.ini enables synchronous 4bit Trace Interface
+ETM Trace pins:  TRACECK         PF_4
+                 TRACED0..3      PF_5..PF_8  (4 bit trace data)
+                 do not use these pins in your application!
+
+LPC18xx_TP.ini is not required for using the Embedded Trace Buffer.
+
+Instruction trace is very time and resource consuming
+therefore if you want to use instruction trace use
+nothing else (no LA, no exceptions, no ITM, no ...).

CMSIS/Pack/Example/Boards/Keil/MCB1800/Blinky_ULp/Blinky.c

@@ -0,0 +1,82 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Name:    Blinky.c
+ * Purpose: LED Flasher for MCB1800
+ *
+ *----------------------------------------------------------------------------*/
+
+#include <stdio.h>
+#include "LPC18xx.h"                    /* LPC18xx Definitions                */
+#include "Board_LED.h"
+#include "Board_ADC.h"
+
+char text[10];
+
+/* Import external variables from IRQ.c file                                  */
+extern volatile unsigned char clock_1s;
+
+/* variable to trace in LogicAnalyzer (should not read to often)              */
+volatile unsigned short AD_dbg;
+
+uint16_t AD_last;                       /* Last converted value               */
+
+/*----------------------------------------------------------------------------
+  Main function
+ *----------------------------------------------------------------------------*/
+int main (void) {
+  int32_t  res;
+  uint32_t AD_avg   = 0;
+  uint16_t AD_value = 0;
+  uint16_t AD_print = 0;
+
+  LED_Initialize();                     /* LED Initialization                 */
+  ADC_Initialize();                     /* ADC Initialization                 */
+
+  SystemCoreClockUpdate();
+  SysTick_Config(SystemCoreClock/100);  /* Generate interrupt each 10 ms      */
+
+  while (1) {                           /* Loop forever                       */    
+    
+    /* AD converter input                                                     */
+    res = ADC_GetValue();
+    if (res != -1) {                    /* If conversion has finished         */
+      AD_last = res;
+
+      AD_avg += AD_last << 8;           /* Add AD value to averaging          */
+      AD_avg ++;
+      if ((AD_avg & 0xFF) == 0x10) {    /* average over 16 values             */
+        AD_value = (AD_avg >> 8) >> 4;  /* average devided by 16              */
+        AD_avg = 0;
+      }
+    }
+
+    if (AD_value != AD_print) {
+      AD_print = AD_value;              /* Get unscaled value for printout    */
+      AD_dbg   = AD_value;
+
+      sprintf(text, "0x%04X", AD_value);/* format text for print out          */
+    }
+
+    /* Print message with AD value every second                               */
+    if (clock_1s) {
+      clock_1s = 0;
+
+      printf("AD value: %s\r\n", text);
+    }
+  }
+}

CMSIS/Pack/Example/Boards/Keil/MCB1800/Blinky_ULp/Blinky.uvoptx

@@ -0,0 +1,839 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>SWO Trace</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\Flash\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>8</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>MCB1800 Schematics (MCB1800)</Title>
+          <Path>C:\Keil\ARM\PACK\Keil\LPC1800_DFP\2.6.0-dev1\Documents\MCB1800v1-3-schematics.pdf</Path>
+        </Book>
+        <Book>
+          <Number>1</Number>
+          <Title>User Manual (MCB1800)</Title>
+          <Path>C:\Keil\ARM\PACK\Keil\LPC1800_DFP\2.6.0-dev1\Documents\mcb1800.chm</Path>
+        </Book>
+        <Book>
+          <Number>2</Number>
+          <Title>MCB1800 Evaluation Board Web Page (MCB1800)</Title>
+          <Path>http://www.keil.com/mcb1800/</Path>
+        </Book>
+      </Books>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>7</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\ULP2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ULP2CM3</Key>
+          <Name>-UP1205083 -O207 -S8 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO19 -TC120000000 -TP18 -TDX31 -TDD0 -TDS1 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD10000000 -FCFE0 -FN2 -FF0LPC18xx43xx_512_BA.flm -FS01A000000 -FL080000 -FP0($$Device:LPC1857$Flash\LPC18xx43xx_512_BA.flm) -FF1LPC18xx43xx_512_BB.flm -FS11B000000 -FL180000 -FP1($$Device:LPC1857$Flash\LPC18xx43xx_512_BB.flm)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-S0 -C0 -P0 -FD10000000 -FCFE0 -FN2 -FF0LPC18xx43xx_512_BA -FS01A000000 -FL080000 -FF1LPC18xx43xx_512_BB -FS11B000000 -FL180000 -FP0($$Device:LPC1857$Flash\LPC18xx43xx_512_BA.flm) -FP1($$Device:LPC1857$Flash\LPC18xx43xx_512_BB.flm))</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>1</periodic>
+        <aLwin>1</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>1</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>1</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+      <LogicAnalyzers>
+        <Wi>
+          <IntNumber>0</IntNumber>
+          <FirstString>`AD_dbg</FirstString>
+          <SecondString>FF00000000000000000000000000000000F88F400000000000000000000000000000000041445F64626700000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000700000001000000000000000000F03F18000000000000000000000000000000000000001403001A</SecondString>
+        </Wi>
+      </LogicAnalyzers>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>TracePort Trace</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\Flash\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>8</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>MCB1800 Schematics (MCB1800)</Title>
+          <Path>C:\Keil\ARM\PACK\Keil\LPC1800_DFP\2.6.0-dev1\Documents\MCB1800v1-3-schematics.pdf</Path>
+        </Book>
+        <Book>
+          <Number>1</Number>
+          <Title>User Manual (MCB1800)</Title>
+          <Path>C:\Keil\ARM\PACK\Keil\LPC1800_DFP\2.6.0-dev1\Documents\mcb1800.chm</Path>
+        </Book>
+        <Book>
+          <Number>2</Number>
+          <Title>MCB1800 Evaluation Board Web Page (MCB1800)</Title>
+          <Path>http://www.keil.com/mcb1800/</Path>
+        </Book>
+      </Books>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>7</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile>.\LPC18xx_TP.ini</tIfile>
+        <pMon>BIN\ULP2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ULP2CM3</Key>
+          <Name>-UP1205083 -O207 -S8 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO4115 -TC120000000 -TP8 -TDX28 -TDD0 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD10000000 -FCFE0 -FN2 -FF0LPC18xx43xx_512_BA.flm -FS01A000000 -FL080000 -FP0($$Device:LPC1857$Flash\LPC18xx43xx_512_BA.flm) -FF1LPC18xx43xx_512_BB.flm -FS11B000000 -FL180000 -FP1($$Device:LPC1857$Flash\LPC18xx43xx_512_BB.flm)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-S0 -C0 -P0 )  -FN2 -FCFE0 -FD10000000 -FF0LPC18xx43xx_512_BA -FF1LPC18xx43xx_512_BB -FL080000 -FL180000 -FS01A000000 -FS11B000000 -FP0($$Device:LPC1857$Flash\LPC18xx43xx_512_BA.flm) -FP1($$Device:LPC1857$Flash\LPC18xx43xx_512_BB.flm)</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>1</periodic>
+        <aLwin>1</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>1</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>1</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+      <LogicAnalyzers>
+        <Wi>
+          <IntNumber>0</IntNumber>
+          <FirstString>`AD_dbg</FirstString>
+          <SecondString>FF00000000000000000000000000000000F88F400000000000000000000000000000000041445F64626700000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000700000001000000000000000000F03F18000000000000000000000000000000000000001403001A</SecondString>
+        </Wi>
+      </LogicAnalyzers>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>Instruction Trace</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\Flash\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>8</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>MCB1800 Schematics (MCB1800)</Title>
+          <Path>C:\Keil\ARM\PACK\Keil\LPC1800_DFP\2.6.0-dev1\Documents\MCB1800v1-3-schematics.pdf</Path>
+        </Book>
+        <Book>
+          <Number>1</Number>
+          <Title>User Manual (MCB1800)</Title>
+          <Path>C:\Keil\ARM\PACK\Keil\LPC1800_DFP\2.6.0-dev1\Documents\mcb1800.chm</Path>
+        </Book>
+        <Book>
+          <Number>2</Number>
+          <Title>MCB1800 Evaluation Board Web Page (MCB1800)</Title>
+          <Path>http://www.keil.com/mcb1800/</Path>
+        </Book>
+      </Books>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>7</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile>.\LPC18xx_TP.ini</tIfile>
+        <pMon>BIN\ULP2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ULP2CM3</Key>
+          <Name>-UP1205083 -O207 -S8 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO12291 -TC120000000 -TP8 -TDX28 -TDD0 -TDS8000 -TDT0 -TDC1F -TIE0 -TIP0 -FO15 -FD10000000 -FCFE0 -FN2 -FF0LPC18xx43xx_512_BA.flm -FS01A000000 -FL080000 -FP0($$Device:LPC1857$Flash\LPC18xx43xx_512_BA.flm) -FF1LPC18xx43xx_512_BB.flm -FS11B000000 -FL180000 -FP1($$Device:LPC1857$Flash\LPC18xx43xx_512_BB.flm)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-S0 -C0 -P0 )  -FN2 -FCFE0 -FD10000000 -FF0LPC18xx43xx_512_BA -FF1LPC18xx43xx_512_BB -FL080000 -FL180000 -FS01A000000 -FS11B000000 -FP0($$Device:LPC1857$Flash\LPC18xx43xx_512_BA.flm) -FP1($$Device:LPC1857$Flash\LPC18xx43xx_512_BB.flm)</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>1</periodic>
+        <aLwin>1</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>2</eProf>
+        <aLa>1</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>1</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>Embedded Trace Buffer</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\Flash\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>8</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>MCB1800 Schematics (MCB1800)</Title>
+          <Path>C:\Keil\ARM\PACK\Keil\LPC1800_DFP\2.6.0-dev1\Documents\MCB1800v1-3-schematics.pdf</Path>
+        </Book>
+        <Book>
+          <Number>1</Number>
+          <Title>User Manual (MCB1800)</Title>
+          <Path>C:\Keil\ARM\PACK\Keil\LPC1800_DFP\2.6.0-dev1\Documents\mcb1800.chm</Path>
+        </Book>
+        <Book>
+          <Number>2</Number>
+          <Title>MCB1800 Evaluation Board Web Page (MCB1800)</Title>
+          <Path>http://www.keil.com/mcb1800/</Path>
+        </Book>
+      </Books>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>7</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\ULP2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ULP2CM3</Key>
+          <Name>-UP1205083 -O207 -S8 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO12291 -TC120000000 -TP38 -TDX31 -TDD0 -TDS8000 -TDT0 -TDC1F -TIE0 -TIP0 -FO15 -FD10000000 -FCFE0 -FN2 -FF0LPC18xx43xx_512_BA.flm -FS01A000000 -FL080000 -FP0($$Device:LPC1857$Flash\LPC18xx43xx_512_BA.flm) -FF1LPC18xx43xx_512_BB.flm -FS11B000000 -FL180000 -FP1($$Device:LPC1857$Flash\LPC18xx43xx_512_BB.flm)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-S0 -C0 -P0 ) -FN2 -FCFE0 -FD10000000 -FF0LPC18xx43xx_512_BA -FF1LPC18xx43xx_512_BB -FL080000 -FL180000 -FS01A000000 -FS11B000000 -FP0($$Device:LPC1857$Flash\LPC18xx43xx_512_BA.flm) -FP1($$Device:LPC1857$Flash\LPC18xx43xx_512_BB.flm)</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>1</periodic>
+        <aLwin>1</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>1</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>1</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+    </TargetOption>
+  </Target>
+
+  <Group>
+    <GroupName>Source Files</GroupName>
+    <tvExp>1</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>1</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\Blinky.c</PathWithFileName>
+      <FilenameWithoutPath>Blinky.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>2</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\IRQ.c</PathWithFileName>
+      <FilenameWithoutPath>IRQ.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>3</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\ITM_Retarget.c</PathWithFileName>
+      <FilenameWithoutPath>ITM_Retarget.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>Trace Configuration</GroupName>
+    <tvExp>1</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>4</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\LPC18xx_TP.ini</PathWithFileName>
+      <FilenameWithoutPath>LPC18xx_TP.ini</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>Documentation</GroupName>
+    <tvExp>1</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
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+      <GroupNumber>3</GroupNumber>
+      <FileNumber>5</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\Abstract.txt</PathWithFileName>
+      <FilenameWithoutPath>Abstract.txt</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>::Board Support</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>1</RteFlg>
+  </Group>
+
+  <Group>
+    <GroupName>::CMSIS</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
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+
+  <Group>
+    <GroupName>::Device</GroupName>
+    <tvExp>1</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>1</RteFlg>
+  </Group>
+
+</ProjectOpt>

CMSIS/Pack/Example/Boards/Keil/MCB1800/Blinky_ULp/Blinky.uvprojx

@@ -0,0 +1,2149 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>SWO Trace</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>5060020::V5.06 (build 20)::ARMCC</pCCUsed>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>LPC1857</Device>
+          <Vendor>NXP</Vendor>
+          <PackID>Keil.LPC1800_DFP.2.6.0-dev1</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IROM(0x1A000000,0x80000) IROM2(0x1B000000,0x80000) IRAM(0x10000000,0x8000) IRAM2(0x20000000,0x10000) CPUTYPE("Cortex-M3") CLOCK(180000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD10000000 -FCFE0 -FN2 -FF0LPC18xx43xx_512_BA -FS01A000000 -FL080000 -FF1LPC18xx43xx_512_BB -FS11B000000 -FL180000 -FP0($$Device:LPC1857$Flash\LPC18xx43xx_512_BA.flm) -FP1($$Device:LPC1857$Flash\LPC18xx43xx_512_BB.flm))</FlashDriverDll>
+          <DeviceId>6397</DeviceId>
+          <RegisterFile>$$Device:LPC1857$Device\Include\LPC18xx.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:LPC1857$SVD\LPC18xx.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\Flash\</OutputDirectory>
+          <OutputName>Blinky</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\Flash\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>1</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name>$K\ARM\BIN\ElfDwT.exe !L BASEADDRESS(0x1A000000)</UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>-MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments>-MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+            <RestoreSysVw>1</RestoreSysVw>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>1</RestoreTracepoints>
+            <RestoreSysVw>1</RestoreSysVw>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>7</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>BIN\ULP2CM3.DLL</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M3"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>1</hadIRAM2>
+            <hadIROM2>1</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x8000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x1a000000</StartAddress>
+                <Size>0x80000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x1a000000</StartAddress>
+                <Size>0x80000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x1b000000</StartAddress>
+                <Size>0x80000</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x8000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>0</uC99>
+            <useXO>0</useXO>
+            <v6Lang>0</v6Lang>
+            <v6LangP>0</v6LangP>
+            <vShortEn>0</vShortEn>
+            <vShortWch>0</vShortWch>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x1A000000</TextAddressRange>
+            <DataAddressRange>0x10000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Source Files</GroupName>
+          <Files>
+            <File>
+              <FileName>Blinky.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Blinky.c</FilePath>
+            </File>
+            <File>
+              <FileName>IRQ.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\IRQ.c</FilePath>
+            </File>
+            <File>
+              <FileName>ITM_Retarget.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\ITM_Retarget.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Trace Configuration</GroupName>
+          <Files>
+            <File>
+              <FileName>LPC18xx_TP.ini</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\LPC18xx_TP.ini</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Documentation</GroupName>
+          <Files>
+            <File>
+              <FileName>Abstract.txt</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\Abstract.txt</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::Board Support</GroupName>
+        </Group>
+        <Group>
+          <GroupName>::CMSIS</GroupName>
+        </Group>
+        <Group>
+          <GroupName>::Device</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+    <Target>
+      <TargetName>TracePort Trace</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>5060020::V5.06 (build 20)::ARMCC</pCCUsed>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>LPC1857</Device>
+          <Vendor>NXP</Vendor>
+          <PackID>Keil.LPC1800_DFP.2.6.0-dev1</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IROM(0x1A000000,0x80000) IROM2(0x1B000000,0x80000) IRAM(0x10000000,0x8000) IRAM2(0x20000000,0x10000) CPUTYPE("Cortex-M3") CLOCK(180000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD10000000 -FCFE0 -FN2 -FF0LPC18xx43xx_512_BA -FS01A000000 -FL080000 -FF1LPC18xx43xx_512_BB -FS11B000000 -FL180000 -FP0($$Device:LPC1857$Flash\LPC18xx43xx_512_BA.flm) -FP1($$Device:LPC1857$Flash\LPC18xx43xx_512_BB.flm))</FlashDriverDll>
+          <DeviceId>6397</DeviceId>
+          <RegisterFile>$$Device:LPC1857$Device\Include\LPC18xx.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:LPC1857$SVD\LPC18xx.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\Flash\</OutputDirectory>
+          <OutputName>Blinky</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\Flash\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>1</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name>$K\ARM\BIN\ElfDwT.exe !L BASEADDRESS(0x1A000000)</UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>-MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments>-MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+            <RestoreSysVw>1</RestoreSysVw>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>1</RestoreTracepoints>
+            <RestoreSysVw>1</RestoreSysVw>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>7</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile>.\LPC18xx_TP.ini</InitializationFile>
+            <Driver>BIN\ULP2CM3.DLL</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M3"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>1</hadIRAM2>
+            <hadIROM2>1</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x8000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x1a000000</StartAddress>
+                <Size>0x80000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x1a000000</StartAddress>
+                <Size>0x80000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x1b000000</StartAddress>
+                <Size>0x80000</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x8000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>0</uC99>
+            <useXO>0</useXO>
+            <v6Lang>0</v6Lang>
+            <v6LangP>0</v6LangP>
+            <vShortEn>0</vShortEn>
+            <vShortWch>0</vShortWch>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x1A000000</TextAddressRange>
+            <DataAddressRange>0x10000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Source Files</GroupName>
+          <Files>
+            <File>
+              <FileName>Blinky.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Blinky.c</FilePath>
+            </File>
+            <File>
+              <FileName>IRQ.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\IRQ.c</FilePath>
+            </File>
+            <File>
+              <FileName>ITM_Retarget.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\ITM_Retarget.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Trace Configuration</GroupName>
+          <Files>
+            <File>
+              <FileName>LPC18xx_TP.ini</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\LPC18xx_TP.ini</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Documentation</GroupName>
+          <Files>
+            <File>
+              <FileName>Abstract.txt</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\Abstract.txt</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::Board Support</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>1</IncludeInBuild>
+              <AlwaysBuild>2</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+              <ComprImg>1</ComprImg>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>2</wLevel>
+                <uThumb>2</uThumb>
+                <uSurpInc>2</uSurpInc>
+                <uC99>2</uC99>
+                <useXO>2</useXO>
+                <v6Lang>0</v6Lang>
+                <v6LangP>0</v6LangP>
+                <vShortEn>0</vShortEn>
+                <vShortWch>0</vShortWch>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <uSurpInc>2</uSurpInc>
+                <useXO>2</useXO>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+        </Group>
+        <Group>
+          <GroupName>::CMSIS</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>1</IncludeInBuild>
+              <AlwaysBuild>2</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+              <ComprImg>1</ComprImg>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>2</wLevel>
+                <uThumb>2</uThumb>
+                <uSurpInc>2</uSurpInc>
+                <uC99>2</uC99>
+                <useXO>2</useXO>
+                <v6Lang>0</v6Lang>
+                <v6LangP>0</v6LangP>
+                <vShortEn>0</vShortEn>
+                <vShortWch>0</vShortWch>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <uSurpInc>2</uSurpInc>
+                <useXO>2</useXO>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+        </Group>
+        <Group>
+          <GroupName>::Device</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>1</IncludeInBuild>
+              <AlwaysBuild>2</AlwaysBuild>
+              <GenerateAssemblyFile>2</GenerateAssemblyFile>
+              <AssembleAssemblyFile>2</AssembleAssemblyFile>
+              <PublicsOnly>2</PublicsOnly>
+              <StopOnExitCode>11</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+              <ComprImg>1</ComprImg>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>2</wLevel>
+                <uThumb>2</uThumb>
+                <uSurpInc>2</uSurpInc>
+                <uC99>2</uC99>
+                <useXO>2</useXO>
+                <v6Lang>0</v6Lang>
+                <v6LangP>0</v6LangP>
+                <vShortEn>0</vShortEn>
+                <vShortWch>0</vShortWch>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <uSurpInc>2</uSurpInc>
+                <useXO>2</useXO>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+        </Group>
+      </Groups>
+    </Target>
+    <Target>
+      <TargetName>Instruction Trace</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>5060020::V5.06 (build 20)::ARMCC</pCCUsed>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>LPC1857</Device>
+          <Vendor>NXP</Vendor>
+          <PackID>Keil.LPC1800_DFP.2.6.0-dev1</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IROM(0x1A000000,0x80000) IROM2(0x1B000000,0x80000) IRAM(0x10000000,0x8000) IRAM2(0x20000000,0x10000) CPUTYPE("Cortex-M3") CLOCK(180000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD10000000 -FCFE0 -FN2 -FF0LPC18xx43xx_512_BA -FS01A000000 -FL080000 -FF1LPC18xx43xx_512_BB -FS11B000000 -FL180000 -FP0($$Device:LPC1857$Flash\LPC18xx43xx_512_BA.flm) -FP1($$Device:LPC1857$Flash\LPC18xx43xx_512_BB.flm))</FlashDriverDll>
+          <DeviceId>6397</DeviceId>
+          <RegisterFile>$$Device:LPC1857$Device\Include\LPC18xx.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:LPC1857$SVD\LPC18xx.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\Flash\</OutputDirectory>
+          <OutputName>Blinky</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\Flash\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>1</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name>$K\ARM\BIN\ElfDwT.exe !L BASEADDRESS(0x1A000000)</UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>-MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments>-MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+            <RestoreSysVw>1</RestoreSysVw>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>1</RestoreTracepoints>
+            <RestoreSysVw>1</RestoreSysVw>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>7</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile>.\LPC18xx_TP.ini</InitializationFile>
+            <Driver>BIN\ULP2CM3.DLL</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M3"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>1</hadIRAM2>
+            <hadIROM2>1</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x8000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x1a000000</StartAddress>
+                <Size>0x80000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x1a000000</StartAddress>
+                <Size>0x80000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x1b000000</StartAddress>
+                <Size>0x80000</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x8000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>0</uC99>
+            <useXO>0</useXO>
+            <v6Lang>0</v6Lang>
+            <v6LangP>0</v6LangP>
+            <vShortEn>0</vShortEn>
+            <vShortWch>0</vShortWch>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x1A000000</TextAddressRange>
+            <DataAddressRange>0x10000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Source Files</GroupName>
+          <Files>
+            <File>
+              <FileName>Blinky.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Blinky.c</FilePath>
+            </File>
+            <File>
+              <FileName>IRQ.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\IRQ.c</FilePath>
+            </File>
+            <File>
+              <FileName>ITM_Retarget.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\ITM_Retarget.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Trace Configuration</GroupName>
+          <Files>
+            <File>
+              <FileName>LPC18xx_TP.ini</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\LPC18xx_TP.ini</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Documentation</GroupName>
+          <Files>
+            <File>
+              <FileName>Abstract.txt</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\Abstract.txt</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::Board Support</GroupName>
+        </Group>
+        <Group>
+          <GroupName>::CMSIS</GroupName>
+        </Group>
+        <Group>
+          <GroupName>::Device</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+    <Target>
+      <TargetName>Embedded Trace Buffer</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>5060020::V5.06 (build 20)::ARMCC</pCCUsed>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>LPC1857</Device>
+          <Vendor>NXP</Vendor>
+          <PackID>Keil.LPC1800_DFP.2.6.0-dev1</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IROM(0x1A000000,0x80000) IROM2(0x1B000000,0x80000) IRAM(0x10000000,0x8000) IRAM2(0x20000000,0x10000) CPUTYPE("Cortex-M3") CLOCK(180000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD10000000 -FCFE0 -FN2 -FF0LPC18xx43xx_512_BA -FS01A000000 -FL080000 -FF1LPC18xx43xx_512_BB -FS11B000000 -FL180000 -FP0($$Device:LPC1857$Flash\LPC18xx43xx_512_BA.flm) -FP1($$Device:LPC1857$Flash\LPC18xx43xx_512_BB.flm))</FlashDriverDll>
+          <DeviceId>6397</DeviceId>
+          <RegisterFile>$$Device:LPC1857$Device\Include\LPC18xx.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:LPC1857$SVD\LPC18xx.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\Flash\</OutputDirectory>
+          <OutputName>Blinky</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\Flash\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>1</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name>$K\ARM\BIN\ElfDwT.exe !L BASEADDRESS(0x1A000000)</UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>-MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments>-MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+            <RestoreSysVw>1</RestoreSysVw>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>1</RestoreTracepoints>
+            <RestoreSysVw>1</RestoreSysVw>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>7</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>BIN\ULP2CM3.DLL</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M3"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>1</hadIRAM2>
+            <hadIROM2>1</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x8000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x1a000000</StartAddress>
+                <Size>0x80000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x1a000000</StartAddress>
+                <Size>0x80000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x1b000000</StartAddress>
+                <Size>0x80000</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x8000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>0</uC99>
+            <useXO>0</useXO>
+            <v6Lang>0</v6Lang>
+            <v6LangP>0</v6LangP>
+            <vShortEn>0</vShortEn>
+            <vShortWch>0</vShortWch>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x1A000000</TextAddressRange>
+            <DataAddressRange>0x10000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Source Files</GroupName>
+          <Files>
+            <File>
+              <FileName>Blinky.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Blinky.c</FilePath>
+            </File>
+            <File>
+              <FileName>IRQ.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\IRQ.c</FilePath>
+            </File>
+            <File>
+              <FileName>ITM_Retarget.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\ITM_Retarget.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Trace Configuration</GroupName>
+          <Files>
+            <File>
+              <FileName>LPC18xx_TP.ini</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\LPC18xx_TP.ini</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Documentation</GroupName>
+          <Files>
+            <File>
+              <FileName>Abstract.txt</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\Abstract.txt</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::Board Support</GroupName>
+        </Group>
+        <Group>
+          <GroupName>::CMSIS</GroupName>
+        </Group>
+        <Group>
+          <GroupName>::Device</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis>
+      <api Capiversion="1.00" Cclass="Board Support" Cgroup="A/D Converter" exclusive="0">
+        <package name="MDK-Middleware" schemaVersion="1.0" url="http://www.keil.com/pack/" vendor="Keil" version="5.99.5"/>
+        <targetInfos>
+          <targetInfo name="Embedded Trace Buffer"/>
+          <targetInfo name="Instruction Trace"/>
+          <targetInfo name="SWO Trace"/>
+          <targetInfo name="TracePort Trace"/>
+        </targetInfos>
+      </api>
+      <api Capiversion="1.00" Cclass="Board Support" Cgroup="LED" exclusive="0">
+        <package name="MDK-Middleware" schemaVersion="1.0" url="http://www.keil.com/pack/" vendor="Keil" version="5.99.5"/>
+        <targetInfos>
+          <targetInfo name="Embedded Trace Buffer"/>
+          <targetInfo name="Instruction Trace"/>
+          <targetInfo name="SWO Trace"/>
+          <targetInfo name="TracePort Trace"/>
+        </targetInfos>
+      </api>
+    </apis>
+    <components>
+      <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="3.30.0" condition="CMSIS Core">
+        <package name="CMSIS" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="ARM" version="4.0.11"/>
+        <targetInfos>
+          <targetInfo name="Embedded Trace Buffer"/>
+          <targetInfo name="Instruction Trace"/>
+          <targetInfo name="SWO Trace"/>
+          <targetInfo name="TracePort Trace"/>
+        </targetInfos>
+      </component>
+      <component Cbundle="MCB1800" Cclass="Board Support" Cgroup="A/D Converter" Cvendor="Keil" Cversion="1.0.0" condition="LPC1800 CMSIS SCU">
+        <package name="LPC1800_DFP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="Keil" version="1.99.11"/>
+        <targetInfos>
+          <targetInfo name="Embedded Trace Buffer"/>
+          <targetInfo name="Instruction Trace"/>
+          <targetInfo name="SWO Trace"/>
+          <targetInfo name="TracePort Trace"/>
+        </targetInfos>
+      </component>
+      <component Cbundle="MCB1800" Cclass="Board Support" Cgroup="LED" Cvendor="Keil" Cversion="1.0.0" condition="LPC1800 CMSIS SCU GPIO">
+        <package name="LPC1800_DFP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="Keil" version="1.99.11"/>
+        <targetInfos>
+          <targetInfo name="Embedded Trace Buffer"/>
+          <targetInfo name="Instruction Trace"/>
+          <targetInfo name="SWO Trace"/>
+          <targetInfo name="TracePort Trace"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="GPIO" Cvendor="Keil" Cversion="1.00" condition="LPC1800 CMSIS">
+        <package name="LPC1800_DFP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="Keil" version="1.99.11"/>
+        <targetInfos>
+          <targetInfo name="Embedded Trace Buffer"/>
+          <targetInfo name="Instruction Trace"/>
+          <targetInfo name="SWO Trace"/>
+          <targetInfo name="TracePort Trace"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="SCU" Cvendor="Keil" Cversion="1.00" condition="LPC1800 CMSIS">
+        <package name="LPC1800_DFP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="Keil" version="1.99.11"/>
+        <targetInfos>
+          <targetInfo name="Embedded Trace Buffer"/>
+          <targetInfo name="Instruction Trace"/>
+          <targetInfo name="SWO Trace"/>
+          <targetInfo name="TracePort Trace"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="LPC1800 CMSIS">
+        <package name="LPC1800_DFP" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="Keil" version="2.6.0-dev1"/>
+        <targetInfos>
+          <targetInfo name="Embedded Trace Buffer"/>
+          <targetInfo name="Instruction Trace"/>
+          <targetInfo name="SWO Trace"/>
+          <targetInfo name="TracePort Trace"/>
+        </targetInfos>
+      </component>
+    </components>
+    <files>
+      <file attr="config" category="header" name="RTE_Driver\Config\RTE_Device.h" version="2.2.0">
+        <instance index="0">RTE\Device\LPC1857\RTE_Device.h</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="LPC1800 CMSIS"/>
+        <package name="LPC1800_DFP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="Keil" version="1.99.11"/>
+        <targetInfos>
+          <targetInfo name="Embedded Trace Buffer"/>
+          <targetInfo name="Instruction Trace"/>
+          <targetInfo name="SWO Trace"/>
+          <targetInfo name="TracePort Trace"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="source" name="Device\Source\ARM\startup_LPC18xx.s">
+        <instance index="0">RTE\Device\LPC1857\startup_LPC18xx.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="LPC1800 CMSIS"/>
+        <package name="LPC1800_DFP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="Keil" version="1.99.11"/>
+        <targetInfos>
+          <targetInfo name="Embedded Trace Buffer"/>
+          <targetInfo name="Instruction Trace"/>
+          <targetInfo name="SWO Trace"/>
+          <targetInfo name="TracePort Trace"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="source" name="Device\Source\system_LPC18xx.c" version="1.0.1">
+        <instance index="0">RTE\Device\LPC1857\system_LPC18xx.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="LPC1800 CMSIS"/>
+        <package name="LPC1800_DFP" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="Keil" version="2.6.0-dev1"/>
+        <targetInfos>
+          <targetInfo name="Embedded Trace Buffer"/>
+          <targetInfo name="Instruction Trace"/>
+          <targetInfo name="SWO Trace"/>
+          <targetInfo name="TracePort Trace"/>
+        </targetInfos>
+      </file>
+    </files>
+  </RTE>
+
+</Project>

CMSIS/Pack/Example/Boards/Keil/MCB1800/Blinky_ULp/IRQ.c

@@ -0,0 +1,45 @@
+/*----------------------------------------------------------------------------
+ * Name:    IRQ.c
+ * Purpose: IRQ Handler
+ *----------------------------------------------------------------------------
+ * This file is part of the uVision/ARM development tools.
+ * This software may only be used under the terms of a valid, current,
+ * end user licence from KEIL for a compatible version of KEIL software
+ * development tools. Nothing else gives you the right to use this software.
+ *
+ * This software is supplied "AS IS" without warranties of any kind.
+ *
+ * Copyright (c) 2004-2014 Keil - An ARM Company. All rights reserved.
+ *----------------------------------------------------------------------------*/
+
+#include "LPC18xx.h"                    /* LPC18xx Definitions                */
+#include "Board_LED.h"
+#include "Board_ADC.h"
+
+extern uint16_t AD_last;                /* Last converted value               */
+
+uint8_t clock_1s;                       /* Flag activated each second         */
+
+/*----------------------------------------------------------------------------
+  SysTick IRQ Handler (occurs every 10 ms)
+ *----------------------------------------------------------------------------*/
+void SysTick_Handler (void) {
+  static unsigned long ticks = 0;
+  static unsigned long timetick;
+  static unsigned int  leds = 0x01;
+
+  if (ticks++ >= 99) {                  /* Set Clock1s to 1 every second      */
+    ticks    = 0;
+    clock_1s = 1;
+  }
+
+  /* Blink the LEDs depending on ADC_ConvertedValue                           */
+  if (timetick++ >= (AD_last >> 8)) {
+    timetick   = 0;
+    leds     <<= 1;
+    if (leds == (1 << LED_GetCount())) leds = 0x01;
+    LED_SetOut (leds);
+  }
+
+  ADC_StartConversion();                /* Start ADC conversion               */
+}

CMSIS/Pack/Example/Boards/Keil/MCB1800/Blinky_ULp/ITM_Retarget.c

@@ -0,0 +1,40 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Name:    ITM_Retarget.c
+ * Purpose: CMSIS Retarget output to ITM Channel 0 template file
+ *
+ *----------------------------------------------------------------------------*/
+
+#include <stdio.h> 
+
+#include "LPC18xx.h"                    /* LPC18xx Definitions                */
+
+#pragma import(__use_no_semihosting_swi)
+
+volatile int ITM_RxBuffer = ITM_RXBUFFER_EMPTY;  /*  CMSIS Debug Input        */
+
+int fputc(int c, FILE *f) {
+  int  i;
+  for (i = 10; i; i--) __NOP();
+  return (ITM_SendChar(c));
+}
+
+int fgetc(FILE *f) {
+  while (ITM_CheckChar() != 1) __NOP();
+  return (ITM_ReceiveChar());
+}

CMSIS/Pack/Example/Boards/Keil/MCB1800/Blinky_ULp/LPC18xx_TP.ini

@@ -0,0 +1,44 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Name:    LPC18xx_TP.ini
+ * Purpose: LPC18xx Trace Port Initialization File
+ *
+ *----------------------------------------------------------------------------*/
+
+/******************************************************************************/
+// <<< Use Configuration Wizard in Context Menu >>>                           // 
+/******************************************************************************/
+
+/* Note:
+   Trace pins are:  TRACECLK     PF_4
+                    TRACEDATA0   PF_5
+                    TRACEDATA1   PF_6
+                    TRACEDATA2   PF_7
+                    TRACEDATA3   PF_8
+   do not use these pins in your application!
+ */
+
+FUNC void TraceSetup (void) {
+  _WDWORD(0x40086790, 0x000000B2);  // LPC_SCU->SFSPF_4 = 2;
+  _WDWORD(0x40086794, 0x000000B3);  // LPC_SCU->SFSPF_5 = 3;
+  _WDWORD(0x40086798, 0x000000B3);  // LPC_SCU->SFSPF_6 = 3;
+  _WDWORD(0x4008679C, 0x000000B3);  // LPC_SCU->SFSPF_7 = 3;
+  _WDWORD(0x400867A0, 0x000000B3);  // LPC_SCU->SFSPF_8 = 3;  
+}
+
+TraceSetup();                       // Trace Setup

CMSIS/Pack/Example/Boards/Keil/MCB1800/Blinky_ULp/RTE/Device/LPC1857/RTE_Device.h

@@ -0,0 +1,2358 @@
+/* -----------------------------------------------------------------------------
+ * Copyright (c) 2013-2015 ARM Ltd.
+ *
+ * This software is provided 'as-is', without any express or implied warranty.
+ * In no event will the authors be held liable for any damages arising from
+ * the use of this software. Permission is granted to anyone to use this
+ * software for any purpose, including commercial applications, and to alter
+ * it and redistribute it freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software in
+ *    a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ *
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ *
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * $Date:        5. March 2015
+ * $Revision:    V2.1.1
+ *
+ * Project:      RTE Device Configuration for NXP LPC18xx
+ * -------------------------------------------------------------------------- */
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+#ifndef __RTE_DEVICE_H
+#define __RTE_DEVICE_H
+
+
+// <e> USB0 Controller [Driver_USBD0 and Driver_USBH0]
+// <i> Configuration settings for Driver_USBD0 in component ::Drivers:USB Device
+// <i> Configuration settings for Driver_USBH0 in component ::Drivers:USB Host
+#define   RTE_USB_USB0                  0
+
+//   <h> Pin Configuration
+//     <o> USB0_PPWR (Host) <0=>Not used <1=>P1_7 <2=>P2_0 <3=>P2_3 <4=>P6_3
+//     <i> VBUS drive signal (towards external charge pump or power management unit).
+#define   RTE_USB0_PPWR_ID              1
+#if      (RTE_USB0_PPWR_ID == 0)
+  #define RTE_USB0_PPWR_PIN_EN          0
+#elif    (RTE_USB0_PPWR_ID == 1)
+  #define RTE_USB0_PPWR_PORT            1
+  #define RTE_USB0_PPWR_BIT             7
+  #define RTE_USB0_PPWR_FUNC            4
+#elif    (RTE_USB0_PPWR_ID == 2)
+  #define RTE_USB0_PPWR_PORT            2
+  #define RTE_USB0_PPWR_BIT             0
+  #define RTE_USB0_PPWR_FUNC            3
+#elif    (RTE_USB0_PPWR_ID == 3)
+  #define RTE_USB0_PPWR_PORT            2
+  #define RTE_USB0_PPWR_BIT             3
+  #define RTE_USB0_PPWR_FUNC            7
+#elif    (RTE_USB0_PPWR_ID == 4)
+  #define RTE_USB0_PPWR_PORT            6
+  #define RTE_USB0_PPWR_BIT             3
+  #define RTE_USB0_PPWR_FUNC            1
+#else
+  #error "Invalid RTE_USB0_PPWR Pin Configuration!"
+#endif
+#ifndef   RTE_USB0_PPWR_PIN_EN
+  #define RTE_USB0_PPWR_PIN_EN          1
+#endif
+//     <o> USB0_PWR_FAULT (Host) <0=>Not used <1=>P1_5 <2=>P2_1 <3=>P2_4 <4=>P6_6 <5=>P8_0
+//     <i> Port power fault signal indicating overcurrent condition.
+//     <i> This signal monitors over-current on the USB bus
+//        (external circuitry required to detect over-current condition).
+#define   RTE_USB0_PWR_FAULT_ID         1
+#if      (RTE_USB0_PWR_FAULT_ID == 0)
+  #define RTE_USB0_PWR_FAULT_PIN_EN     0
+#elif    (RTE_USB0_PWR_FAULT_ID == 1)
+  #define RTE_USB0_PWR_FAULT_PORT       1
+  #define RTE_USB0_PWR_FAULT_BIT        5
+  #define RTE_USB0_PWR_FAULT_FUNC       4
+#elif    (RTE_USB0_PWR_FAULT_ID == 2)
+  #define RTE_USB0_PWR_FAULT_PORT       2
+  #define RTE_USB0_PWR_FAULT_BIT        1
+  #define RTE_USB0_PWR_FAULT_FUNC       3
+#elif    (RTE_USB0_PWR_FAULT_ID == 3)
+  #define RTE_USB0_PWR_FAULT_PORT       2
+  #define RTE_USB0_PWR_FAULT_BIT        4
+  #define RTE_USB0_PWR_FAULT_FUNC       7
+#elif    (RTE_USB0_PWR_FAULT_ID == 4)
+  #define RTE_USB0_PWR_FAULT_PORT       6
+  #define RTE_USB0_PWR_FAULT_BIT        6
+  #define RTE_USB0_PWR_FAULT_FUNC       3
+#elif    (RTE_USB0_PWR_FAULT_ID == 5)
+  #define RTE_USB0_PWR_FAULT_PORT       8
+  #define RTE_USB0_PWR_FAULT_BIT        0
+  #define RTE_USB0_PWR_FAULT_FUNC       1
+#else
+  #error "Invalid RTE_USB0_PWR_FAULT Pin Configuration!"
+#endif
+#ifndef   RTE_USB0_PWR_FAULT_PIN_EN
+  #define RTE_USB0_PWR_FAULT_PIN_EN     1
+#endif
+//     <o> USB0_IND0 <0=>Not used <1=>P1_4 <2=>P2_5 <3=>P2_6 <4=>P6_8 <5=>P8_2
+//     <i> USB0 port indicator LED control output 0
+#define   RTE_USB0_IND0_ID              1
+#if      (RTE_USB0_IND0_ID == 0)
+  #define RTE_USB0_IND0_PIN_EN          0
+#elif    (RTE_USB0_IND0_ID == 1)
+  #define RTE_USB0_IND0_PORT            1
+  #define RTE_USB0_IND0_BIT             4
+  #define RTE_USB0_IND0_FUNC            4
+#elif    (RTE_USB0_IND0_ID == 2)
+  #define RTE_USB0_IND0_PORT            2
+  #define RTE_USB0_IND0_BIT             5
+  #define RTE_USB0_IND0_FUNC            7
+#elif    (RTE_USB0_IND0_ID == 3)
+  #define RTE_USB0_IND0_PORT            2
+  #define RTE_USB0_IND0_BIT             6
+  #define RTE_USB0_IND0_FUNC            3
+#elif    (RTE_USB0_IND0_ID == 4)
+  #define RTE_USB0_IND0_PORT            6
+  #define RTE_USB0_IND0_BIT             8
+  #define RTE_USB0_IND0_FUNC            3
+#elif    (RTE_USB0_IND0_ID == 5)
+  #define RTE_USB0_IND0_PORT            8
+  #define RTE_USB0_IND0_BIT             2
+  #define RTE_USB0_IND0_FUNC            1
+#else
+  #error "Invalid RTE_USB0_IND0 Pin Configuration!"
+#endif
+#ifndef   RTE_USB0_IND0_PIN_EN
+  #define RTE_USB0_IND0_PIN_EN          1
+#endif
+//     <o> USB0_IND1 <0=>Not used <1=>P1_3 <2=>P2_2 <3=>P6_7 <4=>P8_1
+//     <i> USB0 port indicator LED control output 1
+#define   RTE_USB0_IND1_ID              1
+#if      (RTE_USB0_IND1_ID == 0)
+  #define RTE_USB0_IND1_PIN_EN          0
+#elif    (RTE_USB0_IND1_ID == 1)
+  #define RTE_USB0_IND1_PORT            1
+  #define RTE_USB0_IND1_BIT             3
+  #define RTE_USB0_IND1_FUNC            4
+#elif    (RTE_USB0_IND1_ID == 2)
+  #define RTE_USB0_IND1_PORT            2
+  #define RTE_USB0_IND1_BIT             2
+  #define RTE_USB0_IND1_FUNC            3
+#elif    (RTE_USB0_IND1_ID == 3)
+  #define RTE_USB0_IND1_PORT            6
+  #define RTE_USB0_IND1_BIT             7
+  #define RTE_USB0_IND1_FUNC            3
+#elif    (RTE_USB0_IND1_ID == 4)
+  #define RTE_USB0_IND1_PORT            8
+  #define RTE_USB0_IND1_BIT             1
+  #define RTE_USB0_IND1_FUNC            1
+#else
+  #error "Invalid RTE_USB0_IND1 Pin Configuration!"
+#endif
+#ifndef   RTE_USB0_IND1_PIN_EN
+  #define RTE_USB0_IND1_PIN_EN          1
+#endif
+//   </h> Pin Configuration
+
+//   <h> Device [Driver_USBD0]
+//   <i> Configuration settings for Driver_USBD0 in component ::Drivers:USB Device
+//     <o.0> High-speed
+//     <i> Enable high-speed functionality
+#define   RTE_USB_USB0_HS_EN            0
+//   </h> Device [Driver_USBD0]
+// </e> USB0 Controller [Driver_USBD0 and Driver_USBH0]
+
+// <e> USB1 Controller [Driver_USBD1 and Driver_USBH1]
+// <i> Configuration settings for Driver_USBD1 in component ::Drivers:USB Device
+// <i> Configuration settings for Driver_USBH1 in component ::Drivers:USB Host
+#define   RTE_USB_USB1                  0
+
+//   <h> Pin Configuration
+//     <o> USB1_PPWR (Host) <0=>Not used <1=>P9_5
+//     <i> VBUS drive signal (towards external charge pump or power management unit).
+#define   RTE_USB1_PPWR_ID              1
+#if      (RTE_USB1_PPWR_ID == 0)
+  #define RTE_USB1_PPWR_PIN_EN          0
+#elif    (RTE_USB1_PPWR_ID == 1)
+  #define RTE_USB1_PPWR_PORT            9
+  #define RTE_USB1_PPWR_BIT             5
+  #define RTE_USB1_PPWR_FUNC            2
+#else
+  #error "Invalid RTE_USB1_PPWR Pin Configuration!"
+#endif
+#ifndef   RTE_USB1_PPWR_PIN_EN
+  #define RTE_USB1_PPWR_PIN_EN          1
+#endif
+//     <o> USB1_PWR_FAULT (Host) <0=>Not used <1=>P9_6
+//     <i> Port power fault signal indicating overcurrent condition.
+//     <i> This signal monitors over-current on the USB bus
+//        (external circuitry required to detect over-current condition).
+#define   RTE_USB1_PWR_FAULT_ID         1
+#if      (RTE_USB1_PWR_FAULT_ID == 0)
+  #define RTE_USB1_PWR_FAULT_PIN_EN     0
+#elif    (RTE_USB1_PWR_FAULT_ID == 1)
+  #define RTE_USB1_PWR_FAULT_PORT       9
+  #define RTE_USB1_PWR_FAULT_BIT        6
+  #define RTE_USB1_PWR_FAULT_FUNC       2
+#else
+  #error "Invalid RTE_USB1_PWR_FAULT Pin Configuration!"
+#endif
+#ifndef   RTE_USB1_PWR_FAULT_PIN_EN
+  #define RTE_USB1_PWR_FAULT_PIN_EN     1
+#endif
+//     <o> USB1_IND0 <0=>Not used <1=>P3_2 <2=>P9_4
+//     <i> USB1 port indicator LED control output 0
+#define   RTE_USB1_IND0_ID              1
+#if      (RTE_USB1_IND0_ID == 0)
+  #define RTE_USB1_IND0_PIN_EN          0
+#elif    (RTE_USB1_IND0_ID == 1)
+  #define RTE_USB1_IND0_PORT            3
+  #define RTE_USB1_IND0_BIT             2
+  #define RTE_USB1_IND0_FUNC            3
+#elif    (RTE_USB1_IND0_ID == 2)
+  #define RTE_USB1_IND0_PORT            9
+  #define RTE_USB1_IND0_BIT             4
+  #define RTE_USB1_IND0_FUNC            2
+#else
+  #error "Invalid RTE_USB1_IND0 Pin Configuration!"
+#endif
+#ifndef   RTE_USB1_IND0_PIN_EN
+  #define RTE_USB1_IND0_PIN_EN          1
+#endif
+//     <o> USB1_IND1 <0=>Not used <1=>P3_1 <2=>P9_3
+//     <i> USB1 port indicator LED control output 1
+#define   RTE_USB1_IND1_ID              1
+#if      (RTE_USB1_IND1_ID == 0)
+  #define RTE_USB1_IND1_PIN_EN          0
+#elif    (RTE_USB1_IND1_ID == 1)
+  #define RTE_USB1_IND1_PORT            3
+  #define RTE_USB1_IND1_BIT             1
+  #define RTE_USB1_IND1_FUNC            3
+#elif    (RTE_USB1_IND1_ID == 2)
+  #define RTE_USB1_IND1_PORT            9
+  #define RTE_USB1_IND1_BIT             3
+  #define RTE_USB1_IND1_FUNC            2
+#else
+  #error "Invalid RTE_USB1_IND1 Pin Configuration!"
+#endif
+#ifndef   RTE_USB1_IND1_PIN_EN
+  #define RTE_USB1_IND1_PIN_EN          1
+#endif
+
+//     <e> On-chip full-speed PHY
+#define   RTE_USB_USB1_FS_PHY_EN        1
+
+//       <o> USB1_VBUS (Device) <0=>Not used <1=>P2_5
+//       <i> Monitors the presence of USB1 bus power.
+#define   RTE_USB1_VBUS_ID              1
+#if      (RTE_USB1_VBUS_ID == 0)
+  #define RTE_USB1_VBUS_PIN_EN          0
+#elif    (RTE_USB1_VBUS_ID == 1)
+  #define RTE_USB1_VBUS_PORT            2
+  #define RTE_USB1_VBUS_BIT             5
+  #define RTE_USB1_VBUS_FUNC            2
+#else
+  #error "Invalid RTE_USB1_VBUS Pin Configuration!"
+#endif
+#ifndef   RTE_USB1_VBUS_PIN_EN
+  #define RTE_USB1_VBUS_PIN_EN          1
+#endif
+//     </e> On-chip full-speed PHY
+
+//     <e> External high-speed ULPI PHY (UTMI+ Low Pin Interface)
+#define   RTE_USB_USB1_HS_PHY_EN        0
+
+//       <o> USB1_ULPI_CLK <0=>P8_8 <1=>PC_0
+//       <i> USB1 ULPI link CLK signal.
+//       <i> 60 MHz clock generated by the PHY.
+#define   RTE_USB1_ULPI_CLK_ID          0
+#if      (RTE_USB1_ULPI_CLK_ID == 0)
+  #define RTE_USB1_ULPI_CLK_PORT        8
+  #define RTE_USB1_ULPI_CLK_BIT         8
+  #define RTE_USB1_ULPI_CLK_FUNC        1
+#elif    (RTE_USB1_ULPI_CLK_ID == 1)
+  #define RTE_USB1_ULPI_CLK_PORT        0xC
+  #define RTE_USB1_ULPI_CLK_BIT         0
+  #define RTE_USB1_ULPI_CLK_FUNC        1
+#else
+  #error "Invalid RTE_USB1_ULPI_CLK Pin Configuration!"
+#endif
+//       <o> USB1_ULPI_DIR <0=>PB_1 <1=>PC_11
+//       <i> USB1 ULPI link DIR signal.
+//       <i> Controls the ULPI data line direction.
+#define   RTE_USB1_ULPI_DIR_ID          0
+#if      (RTE_USB1_ULPI_DIR_ID == 0)
+  #define RTE_USB1_ULPI_DIR_PORT        0xB
+  #define RTE_USB1_ULPI_DIR_BIT         1
+  #define RTE_USB1_ULPI_DIR_FUNC        1
+#elif    (RTE_USB1_ULPI_DIR_ID == 1)
+  #define RTE_USB1_ULPI_DIR_PORT        0xC
+  #define RTE_USB1_ULPI_DIR_BIT         11
+  #define RTE_USB1_ULPI_DIR_FUNC        1
+#else
+  #error "Invalid RTE_USB1_ULPI_DIR Pin Configuration!"
+#endif
+//       <o> USB1_ULPI_STP <0=>P8_7 <1=>PC_10
+//       <i> USB1 ULPI link STP signal.
+//       <i> Asserted to end or interrupt transfers to the PHY.
+#define   RTE_USB1_ULPI_STP_ID          0
+#if      (RTE_USB1_ULPI_STP_ID == 0)
+  #define RTE_USB1_ULPI_STP_PORT        8
+  #define RTE_USB1_ULPI_STP_BIT         7
+  #define RTE_USB1_ULPI_STP_FUNC        1
+#elif    (RTE_USB1_ULPI_STP_ID == 1)
+  #define RTE_USB1_ULPI_STP_PORT        0xC
+  #define RTE_USB1_ULPI_STP_BIT         10
+  #define RTE_USB1_ULPI_STP_FUNC        1
+#else
+  #error "Invalid RTE_USB1_ULPI_STP Pin Configuration!"
+#endif
+//       <o> USB1_ULPI_NXT <0=>P8_6 <1=>PC_9
+//       <i> USB1 ULPI link NXT signal.
+//       <i> Data flow control signal from the PHY.
+#define   RTE_USB1_ULPI_NXT_ID          0
+#if      (RTE_USB1_ULPI_NXT_ID == 0)
+  #define RTE_USB1_ULPI_NXT_PORT        8
+  #define RTE_USB1_ULPI_NXT_BIT         6
+  #define RTE_USB1_ULPI_NXT_FUNC        1
+#elif    (RTE_USB1_ULPI_NXT_ID == 1)
+  #define RTE_USB1_ULPI_NXT_PORT        0xC
+  #define RTE_USB1_ULPI_NXT_BIT         9
+  #define RTE_USB1_ULPI_NXT_FUNC        1
+#else
+  #error "Invalid RTE_USB1_ULPI_NXT Pin Configuration!"
+#endif
+//       <o> USB1_ULPI_D0 <0=>P8_5 <1=>PC_8 <2=>PD_11
+//       <i> USB1 ULPI link bidirectional data line 0.
+#define   RTE_USB1_ULPI_D0_ID           0
+#if      (RTE_USB1_ULPI_D0_ID == 0)
+  #define RTE_USB1_ULPI_D0_PORT         8
+  #define RTE_USB1_ULPI_D0_BIT          5
+  #define RTE_USB1_ULPI_D0_FUNC         1
+#elif    (RTE_USB1_ULPI_D0_ID == 1)
+  #define RTE_USB1_ULPI_D0_PORT         0xC
+  #define RTE_USB1_ULPI_D0_BIT          8
+  #define RTE_USB1_ULPI_D0_FUNC         1
+#elif    (RTE_USB1_ULPI_D0_ID == 2)
+  #define RTE_USB1_ULPI_D0_PORT         0xD
+  #define RTE_USB1_ULPI_D0_BIT          11
+  #define RTE_USB1_ULPI_D0_FUNC         5
+#else
+  #error "Invalid RTE_USB1_ULPI_D0 Pin Configuration!"
+#endif
+//       <o> USB1_ULPI_D1 <0=>P8_4 <1=>PC_7
+//       <i> USB1 ULPI link bidirectional data line 1.
+#define   RTE_USB1_ULPI_D1_ID           0
+#if      (RTE_USB1_ULPI_D1_ID == 0)
+  #define RTE_USB1_ULPI_D1_PORT         8
+  #define RTE_USB1_ULPI_D1_BIT          4
+  #define RTE_USB1_ULPI_D1_FUNC         1
+#elif    (RTE_USB1_ULPI_D1_ID == 1)
+  #define RTE_USB1_ULPI_D1_PORT         0xC
+  #define RTE_USB1_ULPI_D1_BIT          7
+  #define RTE_USB1_ULPI_D1_FUNC         1
+#else
+  #error "Invalid RTE_USB1_ULPI_D1 Pin Configuration!"
+#endif
+//       <o> USB1_ULPI_D2 <0=>P8_3 <1=>PC_6
+//       <i> USB1 ULPI link bidirectional data line 2.
+#define   RTE_USB1_ULPI_D2_ID           0
+#if      (RTE_USB1_ULPI_D2_ID == 0)
+  #define RTE_USB1_ULPI_D2_PORT         8
+  #define RTE_USB1_ULPI_D2_BIT          3
+  #define RTE_USB1_ULPI_D2_FUNC         1
+#elif    (RTE_USB1_ULPI_D2_ID == 1)
+  #define RTE_USB1_ULPI_D2_PORT         0xC
+  #define RTE_USB1_ULPI_D2_BIT          6
+  #define RTE_USB1_ULPI_D2_FUNC         1
+#else
+  #error "Invalid RTE_USB1_ULPI_D2 Pin Configuration!"
+#endif
+//       <o> USB1_ULPI_D3 <0=>PB_6 <1=>PC_5
+//       <i> USB1 ULPI link bidirectional data line 3.
+#define   RTE_USB1_ULPI_D3_ID           0
+#if      (RTE_USB1_ULPI_D3_ID == 0)
+  #define RTE_USB1_ULPI_D3_PORT         0xB
+  #define RTE_USB1_ULPI_D3_BIT          6
+  #define RTE_USB1_ULPI_D3_FUNC         1
+#elif    (RTE_USB1_ULPI_D3_ID == 1)
+  #define RTE_USB1_ULPI_D3_PORT         0xC
+  #define RTE_USB1_ULPI_D3_BIT          5
+  #define RTE_USB1_ULPI_D3_FUNC         1
+#else
+  #error "Invalid RTE_USB1_ULPI_D3 Pin Configuration!"
+#endif
+//       <o> USB1_ULPI_D4 <0=>PB_5 <1=>PC_4
+//       <i> USB1 ULPI link bidirectional data line 4.
+#define   RTE_USB1_ULPI_D4_ID           0
+#if      (RTE_USB1_ULPI_D4_ID == 0)
+  #define RTE_USB1_ULPI_D4_PORT         0xB
+  #define RTE_USB1_ULPI_D4_BIT          5
+  #define RTE_USB1_ULPI_D4_FUNC         1
+#elif    (RTE_USB1_ULPI_D4_ID == 1)
+  #define RTE_USB1_ULPI_D4_PORT         0xC
+  #define RTE_USB1_ULPI_D4_BIT          4
+  #define RTE_USB1_ULPI_D4_FUNC         1
+#else
+  #error "Invalid RTE_USB1_ULPI_D4 Pin Configuration!"
+#endif
+//       <o> USB1_ULPI_D5 <0=>PB_4 <1=>PC_3
+//       <i> USB1 ULPI link bidirectional data line 5.
+#define   RTE_USB1_ULPI_D5_ID           0
+#if      (RTE_USB1_ULPI_D5_ID == 0)
+  #define RTE_USB1_ULPI_D5_PORT         0xB
+  #define RTE_USB1_ULPI_D5_BIT          4
+  #define RTE_USB1_ULPI_D5_FUNC         1
+#elif    (RTE_USB1_ULPI_D5_ID == 1)
+  #define RTE_USB1_ULPI_D5_PORT         0xC
+  #define RTE_USB1_ULPI_D5_BIT          3
+  #define RTE_USB1_ULPI_D5_FUNC         0
+#else
+  #error "Invalid RTE_USB1_ULPI_D5 Pin Configuration!"
+#endif
+//       <o> USB1_ULPI_D6 <0=>PB_3 <1=>PC_2
+//       <i> USB1 ULPI link bidirectional data line 6.
+#define   RTE_USB1_ULPI_D6_ID           0
+#if      (RTE_USB1_ULPI_D6_ID == 0)
+  #define RTE_USB1_ULPI_D6_PORT         0xB
+  #define RTE_USB1_ULPI_D6_BIT          3
+  #define RTE_USB1_ULPI_D6_FUNC         1
+#elif    (RTE_USB1_ULPI_D6_ID == 1)
+  #define RTE_USB1_ULPI_D6_PORT         0xC
+  #define RTE_USB1_ULPI_D6_BIT          2
+  #define RTE_USB1_ULPI_D6_FUNC         0
+#else
+  #error "Invalid RTE_USB1_ULPI_D6 Pin Configuration!"
+#endif
+//       <o> USB1_ULPI_D7 <0=>PB_2 <1=>PC_1
+//       <i> USB1 ULPI link bidirectional data line 7.
+#define   RTE_USB1_ULPI_D7_ID           0
+#if      (RTE_USB1_ULPI_D7_ID == 0)
+  #define RTE_USB1_ULPI_D7_PORT         0xB
+  #define RTE_USB1_ULPI_D7_BIT          2
+  #define RTE_USB1_ULPI_D7_FUNC         1
+#elif    (RTE_USB1_ULPI_D7_ID == 1)
+  #define RTE_USB1_ULPI_D7_PORT         0xC
+  #define RTE_USB1_ULPI_D7_BIT          1
+  #define RTE_USB1_ULPI_D7_FUNC         0
+#else
+  #error "Invalid RTE_USB1_ULPI_D7 Pin Configuration!"
+#endif
+//     </e> External high-speed ULPI PHY (UTMI+ Low Pin Interface)
+//   </h> Pin Configuration
+// </e> USB1 Controller [Driver_USBD1 and Driver_USBH1]
+
+// <e> ENET (Ethernet Interface) [Driver_ETH_MAC0]
+// <i> Configuration settings for Driver_ETH_MAC0 in component ::Drivers:Ethernet MAC
+#define   RTE_ENET                      0
+
+//   <e> MII (Media Independent Interface)
+#define   RTE_ENET_MII                  0
+
+//     <o> ENET_TXD0 Pin <0=>P1_18
+#define   RTE_ENET_MII_TXD0_PORT_ID     0
+#if      (RTE_ENET_MII_TXD0_PORT_ID == 0)
+  #define RTE_ENET_MII_TXD0_PORT        1
+  #define RTE_ENET_MII_TXD0_PIN         18
+  #define RTE_ENET_MII_TXD0_FUNC        3
+#else
+  #error "Invalid ENET_TXD0 Pin Configuration!"
+#endif
+//     <o> ENET_TXD1 Pin <0=>P1_20
+#define   RTE_ENET_MII_TXD1_PORT_ID     0
+#if      (RTE_ENET_MII_TXD1_PORT_ID == 0)
+  #define RTE_ENET_MII_TXD1_PORT        1
+  #define RTE_ENET_MII_TXD1_PIN         20
+  #define RTE_ENET_MII_TXD1_FUNC        3
+#else
+  #error "Invalid ENET_TXD1 Pin Configuration!"
+#endif
+//     <o> ENET_TXD2 Pin <0=>P9_4 <1=>PC_2
+#define   RTE_ENET_MII_TXD2_PORT_ID     0
+#if      (RTE_ENET_MII_TXD2_PORT_ID == 0)
+  #define RTE_ENET_MII_TXD2_PORT        9
+  #define RTE_ENET_MII_TXD2_PIN         4
+  #define RTE_ENET_MII_TXD2_FUNC        5
+#elif    (RTE_ENET_MII_TXD2_PORT_ID == 1)
+  #define RTE_ENET_MII_TXD2_PORT        0xC
+  #define RTE_ENET_MII_TXD2_PIN         2
+  #define RTE_ENET_MII_TXD2_FUNC        3
+#else
+  #error "Invalid ENET_TXD2 Pin Configuration!"
+#endif
+//     <o> ENET_TXD3 Pin <0=>P9_5 <1=>PC_3
+#define   RTE_ENET_MII_TXD3_PORT_ID     0
+#if      (RTE_ENET_MII_TXD3_PORT_ID == 0)
+  #define RTE_ENET_MII_TXD3_PORT        9
+  #define RTE_ENET_MII_TXD3_PIN         5
+  #define RTE_ENET_MII_TXD3_FUNC        5
+#elif    (RTE_ENET_MII_TXD3_PORT_ID == 1)
+  #define RTE_ENET_MII_TXD3_PORT        0xC
+  #define RTE_ENET_MII_TXD3_PIN         3
+  #define RTE_ENET_MII_TXD3_FUNC        3
+#else
+  #error "Invalid ENET_TXD3 Pin Configuration!"
+#endif
+//     <o> ENET_TX_EN Pin <0=>P0_1 <1=>PC_4
+#define   RTE_ENET_MII_TX_EN_PORT_ID    0
+#if      (RTE_ENET_MII_TX_EN_PORT_ID == 0)
+  #define RTE_ENET_MII_TX_EN_PORT       0
+  #define RTE_ENET_MII_TX_EN_PIN        1
+  #define RTE_ENET_MII_TX_EN_FUNC       6
+#elif    (RTE_ENET_MII_TX_EN_PORT_ID == 1)
+  #define RTE_ENET_MII_TX_EN_PORT       0xC
+  #define RTE_ENET_MII_TX_EN_PIN        4
+  #define RTE_ENET_MII_TX_EN_FUNC       3
+#else
+  #error "Invalid ENET_TX_EN Pin Configuration!"
+#endif
+//     <o> ENET_TX_CLK Pin <0=>P1_19 <1=>CLK0
+#define   RTE_ENET_MII_TX_CLK_PORT_ID   0
+#if      (RTE_ENET_MII_TX_CLK_PORT_ID == 0)
+  #define RTE_ENET_MII_TX_CLK_PORT      1
+  #define RTE_ENET_MII_TX_CLK_PIN       19
+  #define RTE_ENET_MII_TX_CLK_FUNC      0
+#elif    (RTE_ENET_MII_TX_CLK_PORT_ID == 1)
+  #define RTE_ENET_MII_TX_CLK_PORT      0x10
+  #define RTE_ENET_MII_TX_CLK_PIN       0
+  #define RTE_ENET_MII_TX_CLK_FUNC      7
+#else
+  #error "Invalid ENET_TX_CLK Pin Configuration!"
+#endif
+//     <o> ENET_TX_ER Pin <0=>Not used <1=>PC_5 <2=>PC_14
+//     <i> Optional signal, rarely used
+#define   RTE_ENET_MII_TX_ER_PORT_ID    0
+#if      (RTE_ENET_MII_TX_ER_PORT_ID == 0)
+  #define RTE_ENET_MII_TX_ER_PIN_EN     0
+#elif    (RTE_ENET_MII_TX_ER_PORT_ID == 1)
+  #define RTE_ENET_MII_TX_ER_PORT       0xC
+  #define RTE_ENET_MII_TX_ER_PIN        5
+  #define RTE_ENET_MII_TX_ER_FUNC       3
+#elif    (RTE_ENET_MII_TX_ER_PORT_ID == 2)
+  #define RTE_ENET_MII_TX_ER_PORT       0xC
+  #define RTE_ENET_MII_TX_ER_PIN        14
+  #define RTE_ENET_MII_TX_ER_FUNC       6
+#else
+  #error "Invalid ENET_TX_ER Pin Configuration!"
+#endif
+#ifndef   RTE_ENET_MII_TX_ER_PIN_EN
+  #define RTE_ENET_MII_TX_ER_PIN_EN     1
+#endif
+//     <o> ENET_RXD0 Pin <0=>P1_15
+#define   RTE_ENET_MII_RXD0_PORT_ID     0
+#if      (RTE_ENET_MII_RXD0_PORT_ID == 0)
+  #define RTE_ENET_MII_RXD0_PORT        1
+  #define RTE_ENET_MII_RXD0_PIN         15
+  #define RTE_ENET_MII_RXD0_FUNC        3
+#else
+  #error "Invalid ENET_RXD0 Pin Configuration!"
+#endif
+//     <o> ENET_RXD1 Pin <0=>P0_0
+#define   RTE_ENET_MII_RXD1_PORT_ID     0
+#if      (RTE_ENET_MII_RXD1_PORT_ID == 0)
+  #define RTE_ENET_MII_RXD1_PORT        0
+  #define RTE_ENET_MII_RXD1_PIN         0
+  #define RTE_ENET_MII_RXD1_FUNC        2
+#else
+  #error "Invalid ENET_RXD1 Pin Configuration!"
+#endif
+//     <o> ENET_RXD2 Pin <0=>P9_3 <1=>PC_6
+#define   RTE_ENET_MII_RXD2_PORT_ID     0
+#if      (RTE_ENET_MII_RXD2_PORT_ID == 0)
+  #define RTE_ENET_MII_RXD2_PORT        9
+  #define RTE_ENET_MII_RXD2_PIN         3
+  #define RTE_ENET_MII_RXD2_FUNC        5
+#elif    (RTE_ENET_MII_RXD2_PORT_ID == 1)
+  #define RTE_ENET_MII_RXD2_PORT        0xC
+  #define RTE_ENET_MII_RXD2_PIN         6
+  #define RTE_ENET_MII_RXD2_FUNC        3
+#else
+  #error "Invalid ENET_RXD2 Pin Configuration!"
+#endif
+//     <o> ENET_RXD3 Pin <0=>P9_2 <1=>PC_7
+#define   RTE_ENET_MII_RXD3_PORT_ID     0
+#if      (RTE_ENET_MII_RXD3_PORT_ID == 0)
+  #define RTE_ENET_MII_RXD3_PORT        9
+  #define RTE_ENET_MII_RXD3_PIN         2
+  #define RTE_ENET_MII_RXD3_FUNC        5
+#elif    (RTE_ENET_MII_RXD3_PORT_ID == 1)
+  #define RTE_ENET_MII_RXD3_PORT        0xC
+  #define RTE_ENET_MII_RXD3_PIN         7
+  #define RTE_ENET_MII_RXD3_FUNC        3
+#else
+  #error "Invalid ENET_RXD3 Pin Configuration!"
+#endif
+//     <o> ENET_RX_DV Pin <0=>P1_16 <1=>PC_8
+#define   RTE_ENET_MII_RX_DV_PORT_ID    0
+#if      (RTE_ENET_MII_RX_DV_PORT_ID == 0)
+  #define RTE_ENET_MII_RX_DV_PORT       1
+  #define RTE_ENET_MII_RX_DV_PIN        16
+  #define RTE_ENET_MII_RX_DV_FUNC       7
+#elif    (RTE_ENET_MII_RX_DV_PORT_ID == 1)
+  #define RTE_ENET_MII_RX_DV_PORT       0xC
+  #define RTE_ENET_MII_RX_DV_PIN        8
+  #define RTE_ENET_MII_RX_DV_FUNC       3
+#else
+  #error "Invalid ENET_RX_DV Pin Configuration!"
+#endif
+//     <o> ENET_RX_CLK Pin <0=>PC_0
+#define   RTE_ENET_MII_RX_CLK_PORT_ID   0
+#if      (RTE_ENET_MII_RX_CLK_PORT_ID == 0)
+  #define RTE_ENET_MII_RX_CLK_PORT      0xC
+  #define RTE_ENET_MII_RX_CLK_PIN       0
+  #define RTE_ENET_MII_RX_CLK_FUNC      3
+#else
+  #error "Invalid ENET_RX_CLK Pin Configuration!"
+#endif
+//     <o> ENET_RX_ER Pin <0=>P9_1 <1=>PC_9
+#define   RTE_ENET_MII_RX_ER_PORT_ID    0
+#if      (RTE_ENET_MII_RX_ER_PORT_ID == 0)
+  #define RTE_ENET_MII_RX_ER_PORT       9
+  #define RTE_ENET_MII_RX_ER_PIN        1
+  #define RTE_ENET_MII_RX_ER_FUNC       5
+#elif    (RTE_ENET_MII_RX_ER_PORT_ID == 1)
+  #define RTE_ENET_MII_RX_ER_PORT       0xC
+  #define RTE_ENET_MII_RX_ER_PIN        9
+  #define RTE_ENET_MII_RX_ER_FUNC       3
+#else
+  #error "Invalid ENET_RX_ER Pin Configuration!"
+#endif
+//     <o> ENET_COL Pin <0=>P0_1 <1=>P4_1 <2=>P9_6
+#define   RTE_ENET_MII_COL_PORT_ID      0
+#if      (RTE_ENET_MII_COL_PORT_ID == 0)
+  #define RTE_ENET_MII_COL_PORT         0
+  #define RTE_ENET_MII_COL_PIN          1
+  #define RTE_ENET_MII_COL_FUNC         2
+#elif    (RTE_ENET_MII_COL_PORT_ID == 1)
+  #define RTE_ENET_MII_COL_PORT         4
+  #define RTE_ENET_MII_COL_PIN          1
+  #define RTE_ENET_MII_COL_FUNC         7
+#elif    (RTE_ENET_MII_COL_PORT_ID == 2)
+  #define RTE_ENET_MII_COL_PORT         9
+  #define RTE_ENET_MII_COL_PIN          6
+  #define RTE_ENET_MII_COL_FUNC         5
+#else
+  #error "Invalid ENET_COL Pin Configuration!"
+#endif
+//     <o> ENET_CRS Pin <0=>P1_16 <1=>P9_0
+#define   RTE_ENET_MII_CRS_PORT_ID      0
+#if      (RTE_ENET_MII_CRS_PORT_ID == 0)
+  #define RTE_ENET_MII_CRS_PORT         1
+  #define RTE_ENET_MII_CRS_PIN          16
+  #define RTE_ENET_MII_CRS_FUNC         3
+#elif    (RTE_ENET_MII_CRS_PORT_ID == 1)
+  #define RTE_ENET_MII_CRS_PORT         9
+  #define RTE_ENET_MII_CRS_PIN          0
+  #define RTE_ENET_MII_CRS_FUNC         5
+#else
+  #error "Invalid ENET_CRS Pin Configuration!"
+#endif
+//   </e> MII (Media Independent Interface)
+
+//   <e> RMII (Reduced Media Independent Interface)
+#define   RTE_ENET_RMII                 0
+
+//     <o> ENET_TXD0 Pin <0=>P1_18
+#define   RTE_ENET_RMII_TXD0_PORT_ID    0
+#if      (RTE_ENET_RMII_TXD0_PORT_ID == 0)
+  #define RTE_ENET_RMII_TXD0_PORT       1
+  #define RTE_ENET_RMII_TXD0_PIN        18
+  #define RTE_ENET_RMII_TXD0_FUNC       3
+#else
+  #error "Invalid ENET_TXD0 Pin Configuration!"
+#endif
+//     <o> ENET_TXD1 Pin <0=>P1_20
+#define   RTE_ENET_RMII_TXD1_PORT_ID    0
+#if      (RTE_ENET_RMII_TXD1_PORT_ID == 0)
+  #define RTE_ENET_RMII_TXD1_PORT       1
+  #define RTE_ENET_RMII_TXD1_PIN        20
+  #define RTE_ENET_RMII_TXD1_FUNC       3
+#else
+  #error "Invalid ENET_TXD1 Pin Configuration!"
+#endif
+//     <o> ENET_TX_EN Pin <0=>P0_1 <1=>PC_4
+#define   RTE_ENET_RMII_TX_EN_PORT_ID   0
+#if      (RTE_ENET_RMII_TX_EN_PORT_ID == 0)
+  #define RTE_ENET_RMII_TX_EN_PORT      0
+  #define RTE_ENET_RMII_TX_EN_PIN       1
+  #define RTE_ENET_RMII_TX_EN_FUNC      6
+#elif    (RTE_ENET_RMII_TX_EN_PORT_ID == 1)
+  #define RTE_ENET_RMII_TX_EN_PORT      0xC
+  #define RTE_ENET_RMII_TX_EN_PIN       4
+  #define RTE_ENET_RMII_TX_EN_FUNC      3
+#else
+  #error "Invalid ENET_TX_EN Pin Configuration!"
+#endif
+//     <o> ENET_REF_CLK Pin <0=>P1_19 <1=>CLK0
+#define   RTE_ENET_RMII_REF_CLK_PORT_ID 0
+#if      (RTE_ENET_RMII_REF_CLK_PORT_ID == 0)
+  #define RTE_ENET_RMII_REF_CLK_PORT    1
+  #define RTE_ENET_RMII_REF_CLK_PIN     19
+  #define RTE_ENET_RMII_REF_CLK_FUNC    0
+#elif    (RTE_ENET_RMII_REF_CLK_PORT_ID == 1)
+  #define RTE_ENET_RMII_REF_CLK_PORT    0x10
+  #define RTE_ENET_RMII_REF_CLK_PIN     0
+  #define RTE_ENET_RMII_REF_CLK_FUNC    7
+#else
+  #error "Invalid ENET_REF_CLK Pin Configuration!"
+#endif
+//     <o> ENET_RXD0 Pin <0=>P1_15
+#define   RTE_ENET_RMII_RXD0_PORT_ID    0
+#if      (RTE_ENET_RMII_RXD0_PORT_ID == 0)
+  #define RTE_ENET_RMII_RXD0_PORT       1
+  #define RTE_ENET_RMII_RXD0_PIN        15
+  #define RTE_ENET_RMII_RXD0_FUNC       3
+#else
+  #error "Invalid ENET_RXD0 Pin Configuration!"
+#endif
+//     <o> ENET_RXD1 Pin <0=>P0_0
+#define   RTE_ENET_RMII_RXD1_PORT_ID    0
+#if      (RTE_ENET_RMII_RXD1_PORT_ID == 0)
+  #define RTE_ENET_RMII_RXD1_PORT       0
+  #define RTE_ENET_RMII_RXD1_PIN        0
+  #define RTE_ENET_RMII_RXD1_FUNC       2
+#else
+  #error "Invalid ENET_RXD1 Pin Configuration!"
+#endif
+//     <o> ENET_RX_DV Pin <0=>P1_16 <1=>PC_8
+#define   RTE_ENET_RMII_RX_DV_PORT_ID   0
+#if      (RTE_ENET_RMII_RX_DV_PORT_ID == 0)
+  #define RTE_ENET_RMII_RX_DV_PORT      1
+  #define RTE_ENET_RMII_RX_DV_PIN       16
+  #define RTE_ENET_RMII_RX_DV_FUNC      7
+#elif    (RTE_ENET_RMII_RX_DV_PORT_ID == 1)
+  #define RTE_ENET_RMII_RX_DV_PORT      0xC
+  #define RTE_ENET_RMII_RX_DV_PIN       8
+  #define RTE_ENET_RMII_RX_DV_FUNC      3
+#else
+  #error "Invalid ENET_RX_DV Pin Configuration!"
+#endif
+//   </e> RMII (Reduced Media Independent Interface)
+
+//   <h> MIIM (Management Data Interface)
+//     <o> ENET_MDIO Pin <0=>P1_17
+#define   RTE_ENET_MDI_MDIO_PORT_ID     0
+#if      (RTE_ENET_MDI_MDIO_PORT_ID == 0)
+  #define RTE_ENET_MDI_MDIO_PORT        1
+  #define RTE_ENET_MDI_MDIO_PIN         17
+  #define RTE_ENET_MDI_MDIO_FUNC        3
+#else
+  #error "Invalid ENET_MDIO Pin Configuration!"
+#endif
+//     <o> ENET_MDC Pin <0=>P2_0 <1=>P7_7 <2=>PC_1
+#define   RTE_ENET_MDI_MDC_PORT_ID      2
+#if      (RTE_ENET_MDI_MDC_PORT_ID == 0)
+  #define RTE_ENET_MDI_MDC_PORT         2
+  #define RTE_ENET_MDI_MDC_PIN          0
+  #define RTE_ENET_MDI_MDC_FUNC         7
+#elif    (RTE_ENET_MDI_MDC_PORT_ID == 1)
+  #define RTE_ENET_MDI_MDC_PORT         7
+  #define RTE_ENET_MDI_MDC_PIN          7
+  #define RTE_ENET_MDI_MDC_FUNC         6
+#elif    (RTE_ENET_MDI_MDC_PORT_ID == 2)
+  #define RTE_ENET_MDI_MDC_PORT         0xC
+  #define RTE_ENET_MDI_MDC_PIN          1
+  #define RTE_ENET_MDI_MDC_FUNC         3
+#else
+  #error "Invalid ENET_MDC Pin Configuration!"
+#endif
+//   </h> MIIM (Management Data Interface)
+// </e> ENET (Ethernet Interface) [Driver_ETH_MAC0]
+
+// <e> SD/MMC Interface [Driver_MCI0]
+// <i> Configuration settings for Driver_MCI0 in component ::Drivers:MCI
+#define RTE_SDMMC                       0
+
+//   <h> SD/MMC Peripheral Bus
+//     <o> SD_CLK Pin <0=>PC_0 <1=>CLK0 <2=>CLK2
+#define   RTE_SD_CLK_PORT_ID            0
+#if      (RTE_SD_CLK_PORT_ID == 0)
+  #define RTE_SD_CLK_PORT               0xC
+  #define RTE_SD_CLK_PIN                0
+  #define RTE_SD_CLK_FUNC               7
+#elif    (RTE_SD_CLK_PORT_ID == 1)
+  #define RTE_SD_CLK_PORT               0x10
+  #define RTE_SD_CLK_PIN                0
+  #define RTE_SD_CLK_FUNC               4
+#elif    (RTE_SD_CLK_PORT_ID == 2)
+  #define RTE_SD_CLK_PORT               0x10
+  #define RTE_SD_CLK_PIN                2
+  #define RTE_SD_CLK_FUNC               4
+#else
+  #error "Invalid SD_CLK Pin Configuration!"
+#endif
+//     <o> SD_CMD Pin <0=>P1_6 <1=>PC_10
+#define   RTE_SD_CMD_PORT_ID            0
+#if      (RTE_SD_CMD_PORT_ID == 0)
+  #define RTE_SD_CMD_PORT               1
+  #define RTE_SD_CMD_PIN                6
+  #define RTE_SD_CMD_FUNC               7
+#elif    (RTE_SD_CMD_PORT_ID == 1)
+  #define RTE_SD_CMD_PORT               0xC
+  #define RTE_SD_CMD_PIN                10
+  #define RTE_SD_CMD_FUNC               7
+#else
+  #error "Invalid SD_CMD Pin Configuration!"
+#endif
+//     <o> SD_DAT0 Pin <0=>P1_9 <1=>PC_4
+#define   RTE_SD_DAT0_PORT_ID           0
+#if      (RTE_SD_DAT0_PORT_ID == 0)
+  #define RTE_SD_DAT0_PORT              1
+  #define RTE_SD_DAT0_PIN               9
+  #define RTE_SD_DAT0_FUNC              7
+#elif    (RTE_SD_DAT0_PORT_ID == 1)
+  #define RTE_SD_DAT0_PORT              0xC
+  #define RTE_SD_DAT0_PIN               4
+  #define RTE_SD_DAT0_FUNC              7
+#else
+  #error "Invalid SD_DAT0 Pin Configuration!"
+#endif
+//     <e> SD_DAT[1 .. 3]
+#define   RTE_SDMMC_BUS_WIDTH_4         0
+//       <o> SD_DAT1 Pin <0=>P1_10 <1=>PC_5
+#define   RTE_SD_DAT1_PORT_ID           0
+#if      (RTE_SD_DAT1_PORT_ID == 0)
+  #define RTE_SD_DAT1_PORT              1
+  #define RTE_SD_DAT1_PIN               10
+  #define RTE_SD_DAT1_FUNC              7
+#elif    (RTE_SD_DAT1_PORT_ID == 1)
+  #define RTE_SD_DAT1_PORT              0xC
+  #define RTE_SD_DAT1_PIN               5
+  #define RTE_SD_DAT1_FUNC              7
+#else
+  #error "Invalid SD_DAT1 Pin Configuration!"
+#endif
+//       <o> SD_DAT2 Pin <0=>P1_11 <1=>PC_6
+#define   RTE_SD_DAT2_PORT_ID           0
+#if      (RTE_SD_DAT2_PORT_ID == 0)
+  #define RTE_SD_DAT2_PORT              1
+  #define RTE_SD_DAT2_PIN               11
+  #define RTE_SD_DAT2_FUNC              7
+#elif    (RTE_SD_DAT2_PORT_ID == 1)
+  #define RTE_SD_DAT2_PORT              0xC
+  #define RTE_SD_DAT2_PIN               6
+  #define RTE_SD_DAT2_FUNC              7
+#else
+  #error "Invalid SD_DAT2 Pin Configuration!"
+#endif
+//       <o> SD_DAT3 Pin <0=>P1_12 <1=>PC_7
+#define   RTE_SD_DAT3_PORT_ID           0
+#if      (RTE_SD_DAT3_PORT_ID == 0)
+  #define RTE_SD_DAT3_PORT              1
+  #define RTE_SD_DAT3_PIN               12
+  #define RTE_SD_DAT3_FUNC              7
+#elif    (RTE_SD_DAT3_PORT_ID == 1)
+  #define RTE_SD_DAT3_PORT              0xC
+  #define RTE_SD_DAT3_PIN               7
+  #define RTE_SD_DAT3_FUNC              7
+#else
+  #error "Invalid SD_DAT3 Pin Configuration!"
+#endif
+//     </e> SD_DAT[1 .. 3]
+//     <e> SD_DAT[4 .. 7]
+#define   RTE_SDMMC_BUS_WIDTH_8         0
+//       <o> SD_DAT4 Pin <0=>PC_11
+#define   RTE_SD_DAT4_PORT_ID           0
+#if      (RTE_SD_DAT4_PORT_ID == 0)
+  #define RTE_SD_DAT4_PORT              0xC
+  #define RTE_SD_DAT4_PIN               11
+  #define RTE_SD_DAT4_FUNC              7
+#else
+  #error "Invalid SD_DAT4 Pin Configuration!"
+#endif
+//       <o> SD_DAT5 Pin <0=>PC_12
+#define   RTE_SD_DAT5_PORT_ID           0
+#if      (RTE_SD_DAT5_PORT_ID == 0)
+  #define RTE_SD_DAT5_PORT              0xC
+  #define RTE_SD_DAT5_PIN               12
+  #define RTE_SD_DAT5_FUNC              7
+#else
+  #error "Invalid SD_DAT5 Pin Configuration!"
+#endif
+//       <o> SD_DAT6 Pin <0=>PC_13
+#define   RTE_SD_DAT6_PORT_ID           0
+#if      (RTE_SD_DAT6_PORT_ID == 0)
+  #define RTE_SD_DAT6_PORT              0xC
+  #define RTE_SD_DAT6_PIN               13
+  #define RTE_SD_DAT6_FUNC              7
+#else
+  #error "Invalid SD_DAT6 Pin Configuration!"
+#endif
+//       <o> SD_DAT7 Pin <0=>PC_14
+#define   RTE_SD_DAT7_PORT_ID           0
+#if      (RTE_SD_DAT7_PORT_ID == 0)
+  #define RTE_SD_DAT7_PORT              0xC
+  #define RTE_SD_DAT7_PIN               14
+  #define RTE_SD_DAT7_FUNC              7
+#else
+  #error "Invalid SD_DAT7 Pin Configuration!"
+#endif
+//     </e> SD_DAT[4 .. 7]
+//   </h> SD/MMC Peripheral Bus
+
+//   <o> SD_CD (Card Detect) Pin <0=>Not used <1=>P1_13 <2=>PC_8
+//   <i> Configure Pin if exists
+#define   RTE_SD_CD_PORT_ID             0
+#if      (RTE_SD_CD_PORT_ID == 0)
+  #define RTE_SD_CD_PIN_EN              0
+#elif    (RTE_SD_CD_PORT_ID == 1)
+  #define RTE_SD_CD_PORT                1
+  #define RTE_SD_CD_PIN                 13
+  #define RTE_SD_CD_FUNC                7
+#elif    (RTE_SD_CD_PORT_ID == 2)
+  #define RTE_SD_CD_PORT                0xC
+  #define RTE_SD_CD_PIN                 8
+  #define RTE_SD_CD_FUNC                7
+#else
+  #error "Invalid SD_CD Pin Configuration!"
+#endif
+#ifndef   RTE_SD_CD_PIN_EN
+  #define RTE_SD_CD_PIN_EN              1
+#endif
+//   <o> SD_WP (Write Protect) Pin <0=>Not used <1=>PD_15 <2=>PF_10
+//   <i> Configure Pin if exists
+#define   RTE_SD_WP_PORT_ID             0
+#if      (RTE_SD_WP_PORT_ID == 0)
+  #define RTE_SD_WP_PIN_EN              0
+#elif    (RTE_SD_WP_PORT_ID == 1)
+  #define RTE_SD_WP_PORT                0xD
+  #define RTE_SD_WP_PIN                 15
+  #define RTE_SD_WP_FUNC                5
+#elif    (RTE_SD_WP_PORT_ID == 2)
+  #define RTE_SD_WP_PORT                0xF
+  #define RTE_SD_WP_PIN                 10
+  #define RTE_SD_WP_FUNC                6
+#else
+  #error "Invalid SD_WP Pin Configuration!"
+#endif
+#ifndef   RTE_SD_WP_PIN_EN
+  #define RTE_SD_WP_PIN_EN              1
+#endif
+//   <o> SD_POW (Power) Pin <0=>Not used <1=>P1_5 <2=>PC_9 <3=>PD_1
+//   <i> Configure Pin if exists
+#define   RTE_SD_POW_PORT_ID            0
+#if      (RTE_SD_POW_PORT_ID == 0)
+  #define RTE_SD_POW_PIN_EN             0
+#elif    (RTE_SD_POW_PORT_ID == 1)
+  #define RTE_SD_POW_PORT               1
+  #define RTE_SD_POW_PIN                5
+  #define RTE_SD_POW_FUNC               7
+#elif    (RTE_SD_POW_PORT_ID == 2)
+  #define RTE_SD_POW_PORT               0xC
+  #define RTE_SD_POW_PIN                9
+  #define RTE_SD_POW_FUNC               7
+#elif    (RTE_SD_POW_PORT_ID == 3)
+  #define RTE_SD_POW_PORT               0xD
+  #define RTE_SD_POW_PIN                1
+  #define RTE_SD_POW_FUNC               5
+#else
+  #error "Invalid SD_POW Pin Configuration!"
+#endif
+#ifndef   RTE_SD_POW_PIN_EN
+  #define RTE_SD_POW_PIN_EN             1
+#endif
+//   <o> SD_RST (Card Reset for MMC4.4) Pin <0=>Not used <1=>P1_3 <2=>PC_2
+//   <i> Configure Pin if exists
+#define   RTE_SD_RST_PORT_ID            0
+#if      (RTE_SD_RST_PORT_ID == 0)
+  #define RTE_SD_RST_PIN_EN             0
+#elif    (RTE_SD_RST_PORT_ID == 1)
+  #define RTE_SD_RST_PORT               1
+  #define RTE_SD_RST_PIN                3
+  #define RTE_SD_RST_FUNC               7
+#elif    (RTE_SD_RST_PORT_ID == 2)
+  #define RTE_SD_RST_PORT               0xC
+  #define RTE_SD_RST_PIN                2
+  #define RTE_SD_RST_FUNC               7
+#else
+  #error "Invalid SD_RST Pin Configuration!"
+#endif
+#ifndef   RTE_SD_RST_PIN_EN
+  #define RTE_SD_RST_PIN_EN             1
+#endif
+// </e> SD/MMC Interface [Driver_MCI0]
+
+// <e> I2C0 (Inter-integrated Circuit Interface 0) [Driver_I2C0]
+// <i> Configuration settings for Driver_I2C0 in component ::Drivers:I2C
+// </e> I2C0 (Inter-integrated Circuit Interface 0) [Driver_I2C0]
+#define   RTE_I2C0                      0
+
+// <e> I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1]
+// <i> Configuration settings for Driver_I2C1 in component ::Drivers:I2C
+#define   RTE_I2C1                      0
+
+//   <o> I2C1_SCL Pin <0=>P2_4 <1=>PE_15
+#define   RTE_I2C1_SCL_PORT_ID          0
+#if      (RTE_I2C1_SCL_PORT_ID == 0)
+  #define RTE_I2C1_SCL_PORT             2
+  #define RTE_I2C1_SCL_PIN              4
+  #define RTE_I2C1_SCL_FUNC             1
+#elif    (RTE_I2C1_SCL_PORT_ID == 1)
+  #define RTE_I2C1_SCL_PORT             0xE
+  #define RTE_I2C1_SCL_PIN              15
+  #define RTE_I2C1_SCL_FUNC             2
+#else
+  #error "Invalid I2C1_SCL Pin Configuration!"
+#endif
+//   <o> I2C1_SDA Pin <0=>P2_3 <1=>PE_13
+#define   RTE_I2C1_SDA_PORT_ID          0
+#if      (RTE_I2C1_SDA_PORT_ID == 0)
+  #define RTE_I2C1_SDA_PORT             2
+  #define RTE_I2C1_SDA_PIN              3
+  #define RTE_I2C1_SDA_FUNC             1
+#elif    (RTE_I2C1_SDA_PORT_ID == 1)
+  #define RTE_I2C1_SDA_PORT             0xE
+  #define RTE_I2C1_SDA_PIN              13
+  #define RTE_I2C1_SDA_FUNC             2
+#else
+  #error "Invalid I2C1_SDA Pin Configuration!"
+#endif
+// </e> I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1]
+
+// <e> USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0]
+#define   RTE_USART0                    0
+
+//   <h> Pin Configuration
+//     <o> TX <0=>P2_0 <1=>P6_4 <2=>P9_5 <3=>PF_10
+//     <i> USART0 Serial Output pin
+#define   RTE_USART0_TX_ID              0
+#if      (RTE_USART0_TX_ID == 0)
+  #define RTE_USART0_TX_PORT            2
+  #define RTE_USART0_TX_BIT             0
+  #define RTE_USART0_TX_FUNC            1
+#elif    (RTE_USART0_TX_ID == 1)
+  #define RTE_USART0_TX_PORT            6
+  #define RTE_USART0_TX_BIT             4
+  #define RTE_USART0_TX_FUNC            2
+#elif    (RTE_USART0_TX_ID == 2)
+  #define RTE_USART0_TX_PORT            9
+  #define RTE_USART0_TX_BIT             5
+  #define RTE_USART0_TX_FUNC            7
+#elif    (RTE_USART0_TX_ID == 3)
+  #define RTE_USART0_TX_PORT            0xF
+  #define RTE_USART0_TX_BIT             10
+  #define RTE_USART0_TX_FUNC            1
+#else
+  #error "Invalid USART0_TX Pin Configuration!"
+#endif
+//     <o> RX <0=>P2_1 <1=>P6_5 <2=>P9_6 <3=>PF_11
+//     <i> USART0 Serial Input pin
+#define   RTE_USART0_RX_ID              0
+#if      (RTE_USART0_RX_ID == 0)
+  #define RTE_USART0_RX_PORT            2
+  #define RTE_USART0_RX_BIT             1
+  #define RTE_USART0_RX_FUNC            1
+#elif    (RTE_USART0_RX_ID == 1)
+  #define RTE_USART0_RX_PORT            6
+  #define RTE_USART0_RX_BIT             5
+  #define RTE_USART0_RX_FUNC            2
+#elif    (RTE_USART0_RX_ID == 2)
+  #define RTE_USART0_RX_PORT            9
+  #define RTE_USART0_RX_BIT             6
+  #define RTE_USART0_RX_FUNC            7
+#elif    (RTE_USART0_RX_ID == 3)
+  #define RTE_USART0_RX_PORT            0xF
+  #define RTE_USART0_RX_BIT             11
+  #define RTE_USART0_RX_FUNC            1
+#else
+  #error "Invalid USART0_RX Pin Configuration!"
+#endif
+//     <o> UCLK (Synchronous and SmartCard mode) <0=>Not used <1=>P2_2 <2=>P6_1 <3=>PF_8
+//     <i> USART0 Serial Clock input/output synchronous mode
+#define   RTE_USART0_UCLK_ID            0
+#if      (RTE_USART0_UCLK_ID == 0)
+  #define RTE_USART0_UCLK_PIN_EN        0
+#elif    (RTE_USART0_UCLK_ID == 1)
+  #define RTE_USART0_UCLK_PORT          2
+  #define RTE_USART0_UCLK_BIT           2
+  #define RTE_USART0_UCLK_FUNC          1
+#elif    (RTE_USART0_UCLK_ID == 2)
+  #define RTE_USART0_UCLK_PORT          6
+  #define RTE_USART0_UCLK_BIT           1
+  #define RTE_USART0_UCLK_FUNC          2
+#elif    (RTE_USART0_UCLK_ID == 3)
+  #define RTE_USART0_UCLK_PORT          0xF
+  #define RTE_USART0_UCLK_BIT           8
+  #define RTE_USART0_UCLK_FUNC          1
+#else
+  #error "Invalid USART0_UCLK Pin Configuration!"
+#endif
+#ifndef   RTE_USART0_UCLK_PIN_EN
+  #define RTE_USART0_UCLK_PIN_EN        1
+#endif
+//   </h> Pin Configuration
+
+//   <h> DMA
+//     <e> Tx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>1 (DMAMUXPER1)  <1=>11 (DMAMUXPER11)
+//     </e>
+#define   RTE_USART0_DMA_TX_EN          0
+#define   RTE_USART0_DMA_TX_CH          0
+#define   RTE_USART0_DMA_TX_PERI_ID     0
+#if      (RTE_USART0_DMA_TX_PERI_ID == 0)
+  #define RTE_USART0_DMA_TX_PERI        1
+  #define RTE_USART0_DMA_TX_PERI_SEL    1
+#elif    (RTE_USART0_DMA_TX_PERI_ID == 1)
+  #define RTE_USART0_DMA_TX_PERI        11
+  #define RTE_USART0_DMA_TX_PERI_SEL    2
+#endif
+//     <e> Rx
+//       <o1> Channel    <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral <0=>2 (DMAMUXPER2)  <1=>12 (DMAMUXPER12)
+//     </e>
+#define   RTE_USART0_DMA_RX_EN          0
+#define   RTE_USART0_DMA_RX_CH          1
+#define   RTE_USART0_DMA_RX_PERI_ID     0
+#if      (RTE_USART0_DMA_RX_PERI_ID == 0)
+  #define RTE_USART0_DMA_RX_PERI        2
+  #define RTE_USART0_DMA_RX_PERI_SEL    1
+#elif    (RTE_USART0_DMA_RX_PERI_ID == 1)
+  #define RTE_USART0_DMA_RX_PERI        12
+  #define RTE_USART0_DMA_RX_PERI_SEL    2
+#endif
+//   </h> DMA
+// </e> USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0]
+
+// <e> UART1 (Universal asynchronous receiver transmitter) [Driver_USART1]
+#define   RTE_UART1                     0
+
+//   <h> Pin Configuration
+//     <o> TX <0=>P1_13 <1=>P3_4 <2=>P5_6 <3=>PC_13 <4=>PE_11
+//     <i> UART0 Serial Output pin
+#define   RTE_UART1_TX_ID               2
+#if      (RTE_UART1_TX_ID == 0)
+  #define RTE_UART1_TX_PORT             1
+  #define RTE_UART1_TX_BIT              13
+  #define RTE_UART1_TX_FUNC             1
+#elif    (RTE_UART1_TX_ID == 1)
+  #define RTE_UART1_TX_PORT             3
+  #define RTE_UART1_TX_BIT              4
+  #define RTE_UART1_TX_FUNC             4
+#elif    (RTE_UART1_TX_ID == 2)
+  #define RTE_UART1_TX_PORT             5
+  #define RTE_UART1_TX_BIT              6
+  #define RTE_UART1_TX_FUNC             4
+#elif    (RTE_UART1_TX_ID == 3)
+  #define RTE_UART1_TX_PORT             0xC
+  #define RTE_UART1_TX_BIT              13
+  #define RTE_UART1_TX_FUNC             2
+#elif    (RTE_UART1_TX_ID == 4)
+  #define RTE_UART1_TX_PORT             0xE
+  #define RTE_UART1_TX_BIT              11
+  #define RTE_UART1_TX_FUNC             2
+#else
+  #error "Invalid UART1_TX Pin Configuration!"
+#endif
+//   <o> RX <0=>P1_14 <1=>P3_5 <2=>P5_7 <3=>PC_14 <4=>PE_12
+//   <i> UART1 Serial Input pin
+#define   RTE_UART1_RX_ID               0
+#if      (RTE_UART1_RX_ID == 0)
+  #define RTE_UART1_RX_PORT             1
+  #define RTE_UART1_RX_BIT              14
+  #define RTE_UART1_RX_FUNC             1
+#elif    (RTE_UART1_RX_ID == 1)
+  #define RTE_UART1_RX_PORT             3
+  #define RTE_UART1_RX_BIT              5
+  #define RTE_UART1_RX_FUNC             4
+#elif    (RTE_UART1_RX_ID == 2)
+  #define RTE_UART1_RX_PORT             5
+  #define RTE_UART1_RX_BIT              7
+  #define RTE_UART1_RX_FUNC             4
+#elif    (RTE_UART1_RX_ID == 3)
+  #define RTE_UART1_RX_PORT             0xC
+  #define RTE_UART1_RX_BIT              14
+  #define RTE_UART1_RX_FUNC             2
+#elif    (RTE_UART1_RX_ID == 4)
+  #define RTE_UART1_RX_PORT             0xE
+  #define RTE_UART1_RX_BIT              12
+  #define RTE_UART1_RX_FUNC             2
+#else
+  #error "Invalid UART1_RX Pin Configuration!"
+#endif
+
+//     <h> Modem Lines
+//       <o> CTS <0=>Not used <1=>P1_11 <2=>P5_4 <3=>PC_2 <4=>PE_7
+#define   RTE_UART1_CTS_ID              1
+#if      (RTE_UART1_CTS_ID == 0)
+  #define RTE_UART1_CTS_PIN_EN          0
+#elif    (RTE_UART1_CTS_ID == 1)
+  #define RTE_UART1_CTS_PORT            1
+  #define RTE_UART1_CTS_BIT             11
+  #define RTE_UART1_CTS_FUNC            1
+#elif    (RTE_UART1_CTS_ID == 2)
+  #define RTE_UART1_CTS_PORT            5
+  #define RTE_UART1_CTS_BIT             4
+  #define RTE_UART1_CTS_FUNC            4
+#elif    (RTE_UART1_CTS_ID == 3)
+  #define RTE_UART1_CTS_PORT            0xC
+  #define RTE_UART1_CTS_BIT             2
+  #define RTE_UART1_CTS_FUNC            2
+#elif    (RTE_UART1_CTS_ID == 4)
+  #define RTE_UART1_CTS_PORT            0xE
+  #define RTE_UART1_CTS_BIT             7
+  #define RTE_UART1_CTS_FUNC            2
+#else
+  #error "Invalid UART1_CTS Pin Configuration!"
+#endif
+#ifndef   RTE_UART1_CTS_PIN_EN
+  #define RTE_UART1_CTS_PIN_EN          1
+#endif
+//       <o> RTS <0=>Not used <1=>P1_9  <2=>P5_2 <3=>PC_3 <4=>PE_5
+#define   RTE_UART1_RTS_ID              1
+#if      (RTE_UART1_RTS_ID == 0)
+  #define RTE_UART1_RTS_PIN_EN          0
+#elif    (RTE_UART1_RTS_ID == 1)
+  #define RTE_UART1_RTS_PORT            1
+  #define RTE_UART1_RTS_BIT             9
+  #define RTE_UART1_RTS_FUNC            1
+#elif    (RTE_UART1_RTS_ID == 2)
+  #define RTE_UART1_RTS_PORT            5
+  #define RTE_UART1_RTS_BIT             2
+  #define RTE_UART1_RTS_FUNC            4
+#elif    (RTE_UART1_RTS_ID == 3)
+  #define RTE_UART1_RTS_PORT            0xC
+  #define RTE_UART1_RTS_BIT             3
+  #define RTE_UART1_RTS_FUNC            2
+#elif    (RTE_UART1_RTS_ID == 4)
+  #define RTE_UART1_RTS_PORT            0xE
+  #define RTE_UART1_RTS_BIT             5
+  #define RTE_UART1_RTS_FUNC            2
+#else
+  #error "Invalid UART1_RTS Pin Configuration!"
+#endif
+#ifndef   RTE_UART1_RTS_PIN_EN
+  #define RTE_UART1_RTS_PIN_EN          1
+#endif
+//       <o> DCD <0=>Not used <1=>P1_12 <2=>P5_5 <3=>PC_11 <4=>PE_9
+#define   RTE_UART1_DCD_ID              1
+#if      (RTE_UART1_DCD_ID == 0)
+  #define RTE_UART1_DCD_PIN_EN          0
+#elif    (RTE_UART1_DCD_ID == 1)
+  #define RTE_UART1_DCD_PORT            1
+  #define RTE_UART1_DCD_BIT             12
+  #define RTE_UART1_DCD_FUNC            1
+#elif    (RTE_UART1_DCD_ID == 2)
+  #define RTE_UART1_DCD_PORT            5
+  #define RTE_UART1_DCD_BIT             5
+  #define RTE_UART1_DCD_FUNC            4
+#elif    (RTE_UART1_DCD_ID == 3)
+  #define RTE_UART1_DCD_PORT            0xC
+  #define RTE_UART1_DCD_BIT             11
+  #define RTE_UART1_DCD_FUNC            2
+#elif    (RTE_UART1_DCD_ID == 4)
+  #define RTE_UART1_DCD_PORT            0xE
+  #define RTE_UART1_DCD_BIT             9
+  #define RTE_UART1_DCD_FUNC            2
+#else
+  #error "Invalid UART1_DCD Pin Configuration!"
+#endif
+#ifndef   RTE_UART1_DCD_PIN_EN
+  #define RTE_UART1_DCD_PIN_EN          1
+#endif
+//       <o> DSR <0=>Not used <1=>P1_7 <2=>P5_0 <3=>PC_10 <4=>PE_8
+#define   RTE_UART1_DSR_ID              1
+#if      (RTE_UART1_DSR_ID == 0)
+  #define RTE_UART1_DSR_PIN_EN          0
+#elif    (RTE_UART1_DSR_ID == 1)
+  #define RTE_UART1_DSR_PORT            1
+  #define RTE_UART1_DSR_BIT             7
+  #define RTE_UART1_DSR_FUNC            1
+#elif    (RTE_UART1_DSR_ID == 2)
+  #define RTE_UART1_DSR_PORT            5
+  #define RTE_UART1_DSR_BIT             0
+  #define RTE_UART1_DSR_FUNC            4
+#elif    (RTE_UART1_DSR_ID == 3)
+  #define RTE_UART1_DSR_PORT            0xC
+  #define RTE_UART1_DSR_BIT             10
+  #define RTE_UART1_DSR_FUNC            2
+#elif    (RTE_UART1_DSR_ID == 4)
+  #define RTE_UART1_DSR_PORT            0xE
+  #define RTE_UART1_DSR_BIT             8
+  #define RTE_UART1_DSR_FUNC            2
+#else
+  #error "Invalid UART1_DSR Pin Configuration!"
+#endif
+#ifndef   RTE_UART1_DSR_PIN_EN
+  #define RTE_UART1_DSR_PIN_EN          1
+#endif
+//       <o> DTR <0=>Not used <1=>P1_8  <2=>P5_1 <3=>PC_12 <4=>PE_10
+#define   RTE_UART1_DTR_ID              1
+#if      (RTE_UART1_DTR_ID == 0)
+  #define RTE_UART1_DTR_PIN_EN          0
+#elif    (RTE_UART1_DTR_ID == 1)
+  #define RTE_UART1_DTR_PORT            1
+  #define RTE_UART1_DTR_BIT             8
+  #define RTE_UART1_DTR_FUNC            1
+#elif    (RTE_UART1_DTR_ID == 2)
+  #define RTE_UART1_DTR_PORT            5
+  #define RTE_UART1_DTR_BIT             1
+  #define RTE_UART1_DTR_FUNC            4
+#elif    (RTE_UART1_DTR_ID == 3)
+  #define RTE_UART1_DTR_PORT            0xC
+  #define RTE_UART1_DTR_BIT             12
+  #define RTE_UART1_DTR_FUNC            2
+#elif    (RTE_UART1_DTR_ID == 4)
+  #define RTE_UART1_DTR_PORT            0xE
+  #define RTE_UART1_DTR_BIT             10
+  #define RTE_UART1_DTR_FUNC            2
+#else
+  #error "Invalid UART1_DTR Pin Configuration!"
+#endif
+#ifndef   RTE_UART1_DTR_PIN_EN
+  #define RTE_UART1_DTR_PIN_EN          1
+#endif
+//       <o> RI <0=>Not used <1=>P1_10 <2=>P5_3 <3=>PC_1 <4=>PE_6
+#define   RTE_UART1_RI_ID               1
+#if      (RTE_UART1_RI_ID == 0)
+  #define RTE_UART1_RI_PIN_EN           0
+#elif    (RTE_UART1_RI_ID == 1)
+  #define RTE_UART1_RI_PORT             1
+  #define RTE_UART1_RI_BIT              10
+  #define RTE_UART1_RI_FUNC             1
+#elif    (RTE_UART1_RI_ID == 2)
+  #define RTE_UART1_RI_PORT             5
+  #define RTE_UART1_RI_BIT              3
+  #define RTE_UART1_RI_FUNC             4
+#elif    (RTE_UART1_RI_ID == 3)
+  #define RTE_UART1_RI_PORT             0xC
+  #define RTE_UART1_RI_BIT              1
+  #define RTE_UART1_RI_FUNC             2
+#elif    (RTE_UART1_RI_ID == 4)
+  #define RTE_UART1_RI_PORT             0xE
+  #define RTE_UART1_RI_BIT              6
+  #define RTE_UART1_RI_FUNC             2
+#else
+  #error "Invalid UART1_RI Pin Configuration!"
+#endif
+#ifndef   RTE_UART1_RI_PIN_EN
+  #define RTE_UART1_RI_PIN_EN           1
+#endif
+//     </h> Modem Lines
+//   </h> Pin Configuration
+
+//   <h> DMA
+//     <e> Tx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>3 (DMAMUXPER3)
+//     </e>
+#define   RTE_UART1_DMA_TX_EN           0
+#define   RTE_UART1_DMA_TX_CH           0
+#define   RTE_UART1_DMA_TX_PERI_ID      0
+#if      (RTE_UART1_DMA_TX_PERI_ID == 0)
+  #define RTE_UART1_DMA_TX_PERI         3
+  #define RTE_UART1_DMA_TX_PERI_SEL     1
+#endif
+//     <e> Rx
+//       <o1> Channel    <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral <0=>4 (DMAMUXPER4)
+//     </e>
+#define   RTE_UART1_DMA_RX_EN           0
+#define   RTE_UART1_DMA_RX_CH           1
+#define   RTE_UART1_DMA_RX_PERI_ID      0
+#if      (RTE_UART1_DMA_RX_PERI_ID == 0)
+  #define RTE_UART1_DMA_RX_PERI         4
+  #define RTE_UART1_DMA_RX_PERI_SEL     1
+#endif
+//   </h> DMA
+// </e> UART1 (Universal asynchronous receiver transmitter) [Driver_USART1]
+
+// <e> USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2]
+#define   RTE_USART2                    0
+
+//   <h> Pin Configuration
+//     <o> TX <0=>P1_15 <1=>P2_10 <2=>P7_1 <3=>PA_1
+//     <i> USART2 Serial Output pin
+#define   RTE_USART2_TX_ID              0
+#if      (RTE_USART2_TX_ID == 0)
+  #define RTE_USART2_TX_PORT            1
+  #define RTE_USART2_TX_BIT             15
+  #define RTE_USART2_TX_FUNC            1
+#elif    (RTE_USART2_TX_ID == 1)
+  #define RTE_USART2_TX_PORT            2
+  #define RTE_USART2_TX_BIT             10
+  #define RTE_USART2_TX_FUNC            2
+#elif    (RTE_USART2_TX_ID == 2)
+  #define RTE_USART2_TX_PORT            7
+  #define RTE_USART2_TX_BIT             1
+  #define RTE_USART2_TX_FUNC            6
+#elif    (RTE_USART2_TX_ID == 3)
+  #define RTE_USART2_TX_PORT            0xA
+  #define RTE_USART2_TX_BIT             1
+  #define RTE_USART2_TX_FUNC            3
+#else
+  #error "Invalid USART2_TX Pin Configuration!"
+#endif
+//     <o> RX <0=>P1_16 <1=>P2_11 <2=>P7_2 <3=>PA_2
+//     <i> USART2 Serial Input pin
+#define   RTE_USART2_RX_ID              0
+#if      (RTE_USART2_RX_ID == 0)
+  #define RTE_USART2_RX_PORT            1
+  #define RTE_USART2_RX_BIT             16
+  #define RTE_USART2_RX_FUNC            1
+#elif    (RTE_USART2_RX_ID == 1)
+  #define RTE_USART2_RX_PORT            2
+  #define RTE_USART2_RX_BIT             11
+  #define RTE_USART2_RX_FUNC            2
+#elif    (RTE_USART2_RX_ID == 2)
+  #define RTE_USART2_RX_PORT            7
+  #define RTE_USART2_RX_BIT             2
+  #define RTE_USART2_RX_FUNC            6
+#elif    (RTE_USART2_RX_ID == 3)
+  #define RTE_USART2_RX_PORT            0xA
+  #define RTE_USART2_RX_BIT             2
+  #define RTE_USART2_RX_FUNC            3
+#else
+  #error "Invalid USART2_RX Pin Configuration!"
+#endif
+//       <o> UCLK (Synchronous and SmartCard mode) <0=>Not used <1=>P1_17 <2=>P2_12
+//       <i> USART2 Serial Clock input/output synchronous mode
+#define   RTE_USART2_UCLK_ID            0
+#if      (RTE_USART2_UCLK_ID == 0)
+  #define RTE_USART2_UCLK_PIN_EN        0
+#elif    (RTE_USART2_UCLK_ID == 1)
+  #define RTE_USART2_UCLK_PORT          1
+  #define RTE_USART2_UCLK_BIT           17
+  #define RTE_USART2_UCLK_FUNC          1
+#elif    (RTE_USART2_UCLK_ID == 1)
+  #define RTE_USART2_UCLK_PORT          2
+  #define RTE_USART2_UCLK_BIT           12
+  #define RTE_USART2_UCLK_FUNC          7
+#else
+  #error "Invalid USART2_UCLK Pin Configuration!"
+#endif
+#ifndef   RTE_USART2_UCLK_PIN_EN
+  #define RTE_USART2_UCLK_PIN_EN        1
+#endif
+//   </h> Pin Configuration
+
+//   <h> DMA
+//     <e> Tx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>5 (DMAMUXPER5)
+//     </e>
+#define   RTE_USART2_DMA_TX_EN          0
+#define   RTE_USART2_DMA_TX_CH          0
+#define   RTE_USART2_DMA_TX_PERI_ID     0
+#if      (RTE_USART2_DMA_TX_PERI_ID == 0)
+  #define RTE_USART2_DMA_TX_PERI        5
+  #define RTE_USART2_DMA_TX_PERI_SEL    1
+#endif
+//     <e> Rx
+//       <o1> Channel    <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral <0=>6 (DMAMUXPER6)
+//     </e>
+#define   RTE_USART2_DMA_RX_EN          0
+#define   RTE_USART2_DMA_RX_CH          1
+#define   RTE_USART2_DMA_RX_PERI_ID     0
+#if      (RTE_USART2_DMA_RX_PERI_ID == 0)
+  #define RTE_USART2_DMA_RX_PERI        6
+  #define RTE_USART2_DMA_RX_PERI_SEL    1
+#endif
+//   </h> DMA
+// </e> USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2]
+
+// <e> USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3]
+#define   RTE_USART3                    0
+
+//   <h> Pin Configuration
+//     <o> TX <0=>P2_3 <1=>P4_1 <2=>P9_3 <3=>PF_2
+//     <i> USART3 Serial Output pin
+#define   RTE_USART3_TX_ID              0
+#if      (RTE_USART3_TX_ID == 0)
+  #define RTE_USART3_TX_PORT            2
+  #define RTE_USART3_TX_BIT             3
+  #define RTE_USART3_TX_FUNC            2
+#elif    (RTE_USART3_TX_ID == 1)
+  #define RTE_USART3_TX_PORT            4
+  #define RTE_USART3_TX_BIT             1
+  #define RTE_USART3_TX_FUNC            6
+#elif    (RTE_USART3_TX_ID == 2)
+  #define RTE_USART3_TX_PORT            9
+  #define RTE_USART3_TX_BIT             3
+  #define RTE_USART3_TX_FUNC            7
+#elif    (RTE_USART3_TX_ID == 3)
+  #define RTE_USART3_TX_PORT            0xF
+  #define RTE_USART3_TX_BIT             2
+  #define RTE_USART3_TX_FUNC            1
+#else
+  #error "Invalid USART3_TX Pin Configuration!"
+#endif
+//     <o> RX <0=>P2_4 <1=>P4_2 <2=>P9_4 <3=>PF_3
+//     <i> USART3 Serial Input pin
+#define   RTE_USART3_RX_ID              0
+#if      (RTE_USART3_RX_ID == 0)
+  #define RTE_USART3_RX_PORT            2
+  #define RTE_USART3_RX_BIT             4
+  #define RTE_USART3_RX_FUNC            2
+#elif    (RTE_USART3_RX_ID == 1)
+  #define RTE_USART3_RX_PORT            4
+  #define RTE_USART3_RX_BIT             2
+  #define RTE_USART3_RX_FUNC            6
+#elif    (RTE_USART3_RX_ID == 2)
+  #define RTE_USART3_RX_PORT            9
+  #define RTE_USART3_RX_BIT             4
+  #define RTE_USART3_RX_FUNC            7
+#elif    (RTE_USART3_RX_ID == 3)
+  #define RTE_USART3_RX_PORT            0xF
+  #define RTE_USART3_RX_BIT             3
+  #define RTE_USART3_RX_FUNC            1
+#else
+  #error "Invalid USART3_RX Pin Configuration!"
+#endif
+//     <o> UCLK (Synchronous and SmartCard mode) <0=>Not used <1=>P2_7 <2=>P4_0 <3=>PF_5
+//     <i> USART3 Serial Clock input/output synchronous mode
+#define   RTE_USART3_UCLK_ID            0
+#if      (RTE_USART3_UCLK_ID == 0)
+  #define RTE_USART3_UCLK_PIN_EN        0
+#elif    (RTE_USART3_UCLK_ID == 1)
+  #define RTE_USART3_UCLK_PORT          2
+  #define RTE_USART3_UCLK_BIT           7
+  #define RTE_USART3_UCLK_FUNC          2
+#elif    (RTE_USART3_UCLK_ID == 2)
+  #define RTE_USART3_UCLK_PORT          4
+  #define RTE_USART3_UCLK_BIT           0
+  #define RTE_USART3_UCLK_FUNC          6
+#elif    (RTE_USART3_UCLK_ID == 3)
+  #define RTE_USART3_UCLK_PORT          0xF
+  #define RTE_USART3_UCLK_BIT           5
+  #define RTE_USART3_UCLK_FUNC          1
+#else
+  #error "Invalid USART3_UCLK Pin Configuration!"
+#endif
+#ifndef   RTE_USART3_UCLK_PIN_EN
+  #define RTE_USART3_UCLK_PIN_EN        1
+#endif
+//   </h> Pin Configuration
+
+//   <h> DMA
+//     <e> Tx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>7 (DMAMUXPER7)  <1=>14 (DMAMUXPER14)
+//     </e>
+#define   RTE_USART3_DMA_TX_EN          0
+#define   RTE_USART3_DMA_TX_CH          0
+#define   RTE_USART3_DMA_TX_PERI_ID     0
+#if      (RTE_USART3_DMA_TX_PERI_ID == 0)
+  #define RTE_USART3_DMA_TX_PERI        7
+  #define RTE_USART3_DMA_TX_PERI_SEL    1
+#elif    (RTE_USART3_DMA_TX_PERI_ID == 1)
+  #define RTE_USART3_DMA_TX_PERI        14
+  #define RTE_USART3_DMA_TX_PERI_SEL    3
+#endif
+//     <e> Rx
+//       <o1> Channel    <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral <0=>8 (DMAMUXPER8)  <1=>13 (DMAMUXPER13)
+//     </e>
+#define   RTE_USART3_DMA_RX_EN          0
+#define   RTE_USART3_DMA_RX_CH          1
+#define   RTE_USART3_DMA_RX_PERI_ID     0
+#if      (RTE_USART3_DMA_RX_PERI_ID == 0)
+  #define RTE_USART3_DMA_RX_PERI        8
+  #define RTE_USART3_DMA_RX_PERI_SEL    1
+#elif    (RTE_USART3_DMA_RX_PERI_ID == 1)
+  #define RTE_USART3_DMA_RX_PERI        13
+  #define RTE_USART3_DMA_RX_PERI_SEL    3
+#endif
+//   </h> DMA
+// </e> USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3]
+
+// <e> SSP0 (Synchronous Serial Port 0) [Driver_SPI0]
+// <i> Configuration settings for Driver_SPI0 in component ::Drivers:SPI
+#define   RTE_SSP0                      0
+
+//   <h> Pin Configuration
+//     <o> SSP0_SSEL <0=>Not used <1=>P1_0 <2=>P3_6 <3=>P3_8 <4=>P9_0 <5=>PF_1
+//     <i> Slave Select for SSP0
+#define   RTE_SSP0_SSEL_PIN_SEL         1
+#if      (RTE_SSP0_SSEL_PIN_SEL == 0)
+#define   RTE_SSP0_SSEL_PIN_EN          0
+#elif    (RTE_SSP0_SSEL_PIN_SEL == 1)
+  #define RTE_SSP0_SSEL_PORT            1
+  #define RTE_SSP0_SSEL_BIT             0
+  #define RTE_SSP0_SSEL_FUNC            5
+  #define RTE_SSP0_SSEL_GPIO_FUNC       0
+  #define RTE_SSP0_SSEL_GPIO_PORT       0
+  #define RTE_SSP0_SSEL_GPIO_BIT        4
+#elif    (RTE_SSP0_SSEL_PIN_SEL == 2)
+  #define RTE_SSP0_SSEL_PORT            3
+  #define RTE_SSP0_SSEL_BIT             6
+  #define RTE_SSP0_SSEL_FUNC            2
+  #define RTE_SSP0_SSEL_GPIO_FUNC       0
+  #define RTE_SSP0_SSEL_GPIO_PORT       0
+  #define RTE_SSP0_SSEL_GPIO_BIT        6
+#elif    (RTE_SSP0_SSEL_PIN_SEL == 3)
+  #define RTE_SSP0_SSEL_PORT            3
+  #define RTE_SSP0_SSEL_BIT             8
+  #define RTE_SSP0_SSEL_FUNC            5
+  #define RTE_SSP0_SSEL_GPIO_FUNC       4
+  #define RTE_SSP0_SSEL_GPIO_PORT       5
+  #define RTE_SSP0_SSEL_GPIO_BIT        11
+#elif    (RTE_SSP0_SSEL_PIN_SEL == 4)
+  #define RTE_SSP0_SSEL_PORT            9
+  #define RTE_SSP0_SSEL_BIT             0
+  #define RTE_SSP0_SSEL_FUNC            7
+  #define RTE_SSP0_SSEL_GPIO_FUNC       0
+  #define RTE_SSP0_SSEL_GPIO_PORT       4
+  #define RTE_SSP0_SSEL_GPIO_BIT        12
+#elif    (RTE_SSP0_SSEL_PIN_SEL == 5)
+  #define RTE_SSP0_SSEL_PORT            0xF
+  #define RTE_SSP0_SSEL_BIT             1
+  #define RTE_SSP0_SSEL_FUNC            2
+  #define RTE_SSP0_SSEL_GPIO_FUNC       4
+  #define RTE_SSP0_SSEL_GPIO_PORT       7
+  #define RTE_SSP0_SSEL_GPIO_BIT        16
+#else
+  #error "Invalid SSP0 SSP0_SSEL Pin Configuration!"
+#endif
+#ifndef   RTE_SSP0_SSEL_PIN_EN
+#define   RTE_SSP0_SSEL_PIN_EN          1
+#endif
+//     <o> SSP0_SCK <0=>P3_0 <1=>P3_3 <2=>PF_0
+//     <i> Serial clock for SSP0
+#define   RTE_SSP0_SCK_PIN_SEL          0
+#if      (RTE_SSP0_SCK_PIN_SEL == 0)
+  #define RTE_SSP0_SCK_PORT             3
+  #define RTE_SSP0_SCK_BIT              0
+  #define RTE_SSP0_SCK_FUNC             4
+#elif    (RTE_SSP0_SCK_PIN_SEL == 1)
+  #define RTE_SSP0_SCK_PORT             3
+  #define RTE_SSP0_SCK_BIT              3
+  #define RTE_SSP0_SCK_FUNC             2
+#elif    (RTE_SSP0_SCK_PIN_SEL == 2)
+  #define RTE_SSP0_SCK_PORT             0xF
+  #define RTE_SSP0_SCK_BIT              0
+  #define RTE_SSP0_SCK_FUNC             0
+#else
+  #error "Invalid SSP0 SSP0_SCK Pin Configuration!"
+#endif
+//     <o> SSP0_MISO <0=>P1_1 <1=>P3_6 <2=>P3_7 <3=>P9_1 <4=>PF_2
+//     <i> Master In Slave Out for SSP0
+#define   RTE_SSP0_MISO_PIN_SEL         0
+#if      (RTE_SSP0_MISO_PIN_SEL == 0)
+  #define RTE_SSP0_MISO_PORT            1
+  #define RTE_SSP0_MISO_BIT             1
+  #define RTE_SSP0_MISO_FUNC            5
+#elif    (RTE_SSP0_MISO_PIN_SEL == 1)
+  #define RTE_SSP0_MISO_PORT            3
+  #define RTE_SSP0_MISO_BIT             6
+  #define RTE_SSP0_MISO_FUNC            5
+#elif    (RTE_SSP0_MISO_PIN_SEL == 2)
+  #define RTE_SSP0_MISO_PORT            3
+  #define RTE_SSP0_MISO_BIT             7
+  #define RTE_SSP0_MISO_FUNC            2
+#elif    (RTE_SSP0_MISO_PIN_SEL == 3)
+  #define RTE_SSP0_MISO_PORT            9
+  #define RTE_SSP0_MISO_BIT             1
+  #define RTE_SSP0_MISO_FUNC            7
+#elif    (RTE_SSP0_MISO_PIN_SEL == 4)
+  #define RTE_SSP0_MISO_PORT            0xF
+  #define RTE_SSP0_MISO_BIT             2
+  #define RTE_SSP0_MISO_FUNC            2
+#else
+  #error "Invalid SSP0 SSP0_MISO Pin Configuration!"
+#endif
+//     <o> SSP0_MOSI <0=>P1_2 <1=>P3_7 <2=>P3_8 <3=>P9_2 <4=>PF_3
+//     <i> Master Out Slave In for SSP0
+#define   RTE_SSP0_MOSI_PIN_SEL         0
+#if      (RTE_SSP0_MOSI_PIN_SEL == 0)
+  #define RTE_SSP0_MOSI_PORT            1
+  #define RTE_SSP0_MOSI_BIT             2
+  #define RTE_SSP0_MOSI_FUNC            5
+#elif    (RTE_SSP0_MOSI_PIN_SEL == 1)
+  #define RTE_SSP0_MOSI_PORT            3
+  #define RTE_SSP0_MOSI_BIT             7
+  #define RTE_SSP0_MOSI_FUNC            5
+#elif    (RTE_SSP0_MOSI_PIN_SEL == 2)
+  #define RTE_SSP0_MOSI_PORT            3
+  #define RTE_SSP0_MOSI_BIT             8
+  #define RTE_SSP0_MOSI_FUNC            2
+#elif    (RTE_SSP0_MOSI_PIN_SEL == 3)
+  #define RTE_SSP0_MOSI_PORT            9
+  #define RTE_SSP0_MOSI_BIT             2
+  #define RTE_SSP0_MOSI_FUNC            7
+#elif    (RTE_SSP0_MOSI_PIN_SEL == 4)
+  #define RTE_SSP0_MOSI_PORT            0xF
+  #define RTE_SSP0_MOSI_BIT             3
+  #define RTE_SSP0_MOSI_FUNC            2
+#else
+  #error "Invalid SSP0 SSP0_MOSI Pin Configuration!"
+#endif
+//   </h> Pin Configuration
+
+//   <h> DMA
+//     <e> Tx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>10 (DMAMUXPER10)
+//     </e>
+#define   RTE_SSP0_DMA_TX_EN            0
+#define   RTE_SSP0_DMA_TX_CH            0
+#define   RTE_SSP0_DMA_TX_PERI_ID       0
+#if      (RTE_SSP0_DMA_TX_PERI_ID == 0)
+  #define RTE_SSP0_DMA_TX_PERI          10
+  #define RTE_SSP0_DMA_TX_PERI_SEL      0
+#endif
+//     <e> Rx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>9 (DMAMUXPER9)
+//     </e>
+#define   RTE_SSP0_DMA_RX_EN            0
+#define   RTE_SSP0_DMA_RX_CH            1
+#define   RTE_SSP0_DMA_RX_PERI_ID       0
+#if      (RTE_SSP0_DMA_RX_PERI_ID == 0)
+  #define RTE_SSP0_DMA_RX_PERI          9
+  #define RTE_SSP0_DMA_RX_PERI_SEL      0
+#endif
+//   </h> DMA
+// </e> SSP0 (Synchronous Serial Port 0) [Driver_SPI0]
+
+// <e> SSP1 (Synchronous Serial Port 1) [Driver_SPI1]
+// <i> Configuration settings for Driver_SPI1 in component ::Drivers:SPI
+#define   RTE_SSP1                      0
+
+//   <h> Pin Configuration
+//     <o> SSP1_SSEL <0=>Not used <1=>P1_5 <2=>P1_20 <3=>PF_5
+//     <i> Slave Select for SSP1
+#define   RTE_SSP1_SSEL_PIN_SEL         1
+#if      (RTE_SSP1_SSEL_PIN_SEL == 0)
+  #define RTE_SSP1_SSEL_PIN_EN          0
+#elif    (RTE_SSP1_SSEL_PIN_SEL == 1)
+  #define RTE_SSP1_SSEL_PORT            1
+  #define RTE_SSP1_SSEL_BIT             5
+  #define RTE_SSP1_SSEL_FUNC            5
+  #define RTE_SSP1_SSEL_GPIO_FUNC       0
+  #define RTE_SSP1_SSEL_GPIO_PORT       1
+  #define RTE_SSP1_SSEL_GPIO_BIT        8
+#elif    (RTE_SSP1_SSEL_PIN_SEL == 2)
+  #define RTE_SSP1_SSEL_PORT            1
+  #define RTE_SSP1_SSEL_BIT             20
+  #define RTE_SSP1_SSEL_FUNC            1
+  #define RTE_SSP1_SSEL_GPIO_FUNC       0
+  #define RTE_SSP1_SSEL_GPIO_PORT       0
+  #define RTE_SSP1_SSEL_GPIO_BIT        15
+#elif    (RTE_SSP1_SSEL_PIN_SEL == 3)
+  #define RTE_SSP1_SSEL_PORT            0xF
+  #define RTE_SSP1_SSEL_BIT             5
+  #define RTE_SSP1_SSEL_FUNC            2
+  #define RTE_SSP1_SSEL_GPIO_FUNC       4
+  #define RTE_SSP1_SSEL_GPIO_PORT       7
+  #define RTE_SSP1_SSEL_GPIO_BIT        19
+#else
+  #error "Invalid SSP1 SSP1_SSEL Pin Configuration!"
+#endif
+#ifndef   RTE_SSP1_SSEL_PIN_EN
+#define   RTE_SSP1_SSEL_PIN_EN          1
+#endif
+//     <o> SSP1_SCK <0=>P1_19 <1=>PF_4 <2=>CLK0
+//     <i> Serial clock for SSP1
+#define   RTE_SSP1_SCK_PIN_SEL          0
+#if      (RTE_SSP1_SCK_PIN_SEL == 0)
+  #define RTE_SSP1_SCK_PORT             1
+  #define RTE_SSP1_SCK_BIT              19
+  #define RTE_SSP1_SCK_FUNC             1
+#elif    (RTE_SSP1_SCK_PIN_SEL == 1)
+  #define RTE_SSP1_SCK_PORT             0xF
+  #define RTE_SSP1_SCK_BIT              4
+  #define RTE_SSP1_SCK_FUNC             0
+#elif    (RTE_SSP1_SCK_PIN_SEL == 2)
+  #define RTE_SSP1_SCK_PORT             0x10
+  #define RTE_SSP1_SCK_BIT              0
+  #define RTE_SSP1_SCK_FUNC             6
+#else
+  #error "Invalid SSP1 SSP1_SCK Pin Configuration!"
+#endif
+//     <o> SSP1_MISO <0=>P0_0 <1=>P1_3 <2=>PF_6
+//     <i> Master In Slave Out for SSP1
+#define   RTE_SSP1_MISO_PIN_SEL         0
+#if      (RTE_SSP1_MISO_PIN_SEL == 0)
+  #define RTE_SSP1_MISO_PORT            0
+  #define RTE_SSP1_MISO_BIT             0
+  #define RTE_SSP1_MISO_FUNC            1
+#elif    (RTE_SSP1_MISO_PIN_SEL == 1)
+  #define RTE_SSP1_MISO_PORT            1
+  #define RTE_SSP1_MISO_BIT             3
+  #define RTE_SSP1_MISO_FUNC            5
+#elif    (RTE_SSP1_MISO_PIN_SEL == 2)
+  #define RTE_SSP1_MISO_PORT            0xF
+  #define RTE_SSP1_MISO_BIT             6
+  #define RTE_SSP1_MISO_FUNC            2
+#else
+  #error "Invalid SSP1 SSP1_MISO Pin Configuration!"
+#endif
+//     <o> SSP1_MOSI <0=>P0_1 <1=>P1_4 <2=>PF_7
+//     <i> Master Out Slave In for SSP1
+#define   RTE_SSP1_MOSI_PIN_SEL         0
+#if      (RTE_SSP1_MOSI_PIN_SEL == 0)
+  #define RTE_SSP1_MOSI_PORT            0
+  #define RTE_SSP1_MOSI_BIT             1
+  #define RTE_SSP1_MOSI_FUNC            1
+#elif    (RTE_SSP1_MOSI_PIN_SEL == 1)
+  #define RTE_SSP1_MOSI_PORT            1
+  #define RTE_SSP1_MOSI_BIT             4
+  #define RTE_SSP1_MOSI_FUNC            5
+#elif    (RTE_SSP1_MOSI_PIN_SEL == 2)
+  #define RTE_SSP1_MOSI_PORT            0xF
+  #define RTE_SSP1_MOSI_BIT             7
+  #define RTE_SSP1_MOSI_FUNC            2
+#else
+  #error "Invalid SSP1 SSP1_MOSI Pin Configuration!"
+#endif
+//   </h> Pin Configuration
+
+//   <h> DMA
+//     <e> Tx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>3 (DMAMUXPER3) <1=>5 (DMAMUXPER5) <2=>12 (DMAMUXPER12) <3=>14 (DMAMUXPER14)
+//     </e>
+#define   RTE_SSP1_DMA_TX_EN            0
+#define   RTE_SSP1_DMA_TX_CH            0
+#define   RTE_SSP1_DMA_TX_PERI_ID       0
+#if      (RTE_SSP1_DMA_TX_PERI_ID == 0)
+  #define RTE_SSP1_DMA_TX_PERI          3
+  #define RTE_SSP1_DMA_TX_PERI_SEL      3
+#elif    (RTE_SSP1_DMA_TX_PERI_ID == 1)
+  #define RTE_SSP1_DMA_TX_PERI          5
+  #define RTE_SSP1_DMA_TX_PERI_SEL      2
+#elif    (RTE_SSP1_DMA_TX_PERI_ID == 2)
+  #define RTE_SSP1_DMA_TX_PERI          12
+  #define RTE_SSP1_DMA_TX_PERI_SEL      0
+#elif    (RTE_SSP1_DMA_TX_PERI_ID == 3)
+  #define RTE_SSP1_DMA_TX_PERI          14
+  #define RTE_SSP1_DMA_TX_PERI_SEL      2
+#endif
+//     <e> Rx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>4 (DMAMUXPER4) <1=>6 (DMAMUXPER6) <2=>11 (DMAMUXPER11) <3=>13 (DMAMUXPER13)
+//     </e>
+#define   RTE_SSP1_DMA_RX_EN            0
+#define   RTE_SSP1_DMA_RX_CH            1
+#define   RTE_SSP1_DMA_RX_PERI_ID       0
+#if      (RTE_SSP1_DMA_RX_PERI_ID == 0)
+  #define RTE_SSP1_DMA_RX_PERI          4
+  #define RTE_SSP1_DMA_RX_PERI_SEL      3
+#elif    (RTE_SSP1_DMA_RX_PERI_ID == 1)
+  #define RTE_SSP1_DMA_RX_PERI          6
+  #define RTE_SSP1_DMA_RX_PERI_SEL      2
+#elif    (RTE_SSP1_DMA_RX_PERI_ID == 2)
+  #define RTE_SSP1_DMA_RX_PERI          11
+  #define RTE_SSP1_DMA_RX_PERI_SEL      0
+#elif    (RTE_SSP1_DMA_RX_PERI_ID == 3)
+  #define RTE_SSP1_DMA_RX_PERI          13
+  #define RTE_SSP1_DMA_RX_PERI_SEL      2
+#endif
+//   </h> DMA
+// </e> SSP1 (Synchronous Serial Port 1) [Driver_SPI1]
+
+// <e> I2S0 (Integrated Interchip Sound 0) [Driver_SAI0]
+// <i> Configuration settings for Driver_SAI0 in component ::Drivers:SAI
+#define   RTE_I2S0                      0
+
+//   <h> Pin Configuration
+//     <o> I2S0_RX_SCK <0=>Not used <1=>P3_0 <2=>P6_0 <3=>PF_4
+//     <i> Receive clock for I2S0
+#define   RTE_I2S0_RX_SCK_PIN_SEL       2
+#if      (RTE_I2S0_RX_SCK_PIN_SEL == 0)
+#define   RTE_I2S0_RX_SCK_PIN_EN        0
+#elif    (RTE_I2S0_RX_SCK_PIN_SEL == 1)
+  #define RTE_I2S0_RX_SCK_PORT          3
+  #define RTE_I2S0_RX_SCK_BIT           0
+  #define RTE_I2S0_RX_SCK_FUNC          0
+#elif    (RTE_I2S0_RX_SCK_PIN_SEL == 2)
+  #define RTE_I2S0_RX_SCK_PORT          6
+  #define RTE_I2S0_RX_SCK_BIT           0
+  #define RTE_I2S0_RX_SCK_FUNC          4
+#elif    (RTE_I2S0_RX_SCK_PIN_SEL == 3)
+  #define RTE_I2S0_RX_SCK_PORT          0xF
+  #define RTE_I2S0_RX_SCK_BIT           4
+  #define RTE_I2S0_RX_SCK_FUNC          7
+#else
+  #error "Invalid I2S0 I2S0_RX_SCK Pin Configuration!"
+#endif
+#ifndef   RTE_I2S0_RX_SCK_PIN_EN
+#define   RTE_I2S0_RX_SCK_PIN_EN        1
+#endif
+//     <o> I2S0_RX_WS <0=>Not used <1=>P3_1 <2=>P6_1
+//     <i> Receive word select for I2S0
+#define   RTE_I2S0_RX_WS_PIN_SEL        2
+#if      (RTE_I2S0_RX_WS_PIN_SEL == 0)
+#define   RTE_I2S0_RX_WS_PIN_EN         0
+#elif    (RTE_I2S0_RX_WS_PIN_SEL == 1)
+  #define RTE_I2S0_RX_WS_PORT           3
+  #define RTE_I2S0_RX_WS_BIT            1
+  #define RTE_I2S0_RX_WS_FUNC           1
+#elif    (RTE_I2S0_RX_WS_PIN_SEL == 2)
+  #define RTE_I2S0_RX_WS_PORT           6
+  #define RTE_I2S0_RX_WS_BIT            1
+  #define RTE_I2S0_RX_WS_FUNC           3
+#else
+  #error "Invalid I2S0 I2S0_RX_WS Pin Configuration!"
+#endif
+#ifndef   RTE_I2S0_RX_WS_PIN_EN
+#define   RTE_I2S0_RX_WS_PIN_EN         1
+#endif
+//     <o> I2S0_RX_SDA <0=>Not used <1=>P3_2 <2=>P6_2
+//     <i> Receive master clock for I2S0
+#define   RTE_I2S0_RX_SDA_PIN_SEL       2
+#if      (RTE_I2S0_RX_SDA_PIN_SEL == 0)
+#define   RTE_I2S0_RX_SDA_PIN_EN        0
+#elif    (RTE_I2S0_RX_SDA_PIN_SEL == 1)
+  #define RTE_I2S0_RX_SDA_PORT          3
+  #define RTE_I2S0_RX_SDA_BIT           2
+  #define RTE_I2S0_RX_SDA_FUNC          1
+#elif    (RTE_I2S0_RX_SDA_PIN_SEL == 2)
+  #define RTE_I2S0_RX_SDA_PORT          6
+  #define RTE_I2S0_RX_SDA_BIT           2
+  #define RTE_I2S0_RX_SDA_FUNC          3
+#else
+  #error "Invalid I2S0 I2S0_RX_SDA Pin Configuration!"
+#endif
+#ifndef   RTE_I2S0_RX_SDA_PIN_EN
+#define   RTE_I2S0_RX_SDA_PIN_EN       1
+#endif
+//     <o> I2S0_RX_MCLK <0=>Not used <1=>P1_19 <2=>P3_0 <3=>P6_0
+//     <i> Receive master clock for I2S0
+#define   RTE_I2S0_RX_MCLK_PIN_SEL      0
+#if      (RTE_I2S0_RX_MCLK_PIN_SEL == 0)
+#define   RTE_I2S0_RX_MCLK_PIN_EN       0
+#elif    (RTE_I2S0_RX_MCLK_PIN_SEL == 1)
+  #define RTE_I2S0_RX_MCLK_PORT         1
+  #define RTE_I2S0_RX_MCLK_BIT          19
+  #define RTE_I2S0_RX_MCLK_FUNC         6
+#elif    (RTE_I2S0_RX_MCLK_PIN_SEL == 2)
+  #define RTE_I2S0_RX_MCLK_PORT         3
+  #define RTE_I2S0_RX_MCLK_BIT          0
+  #define RTE_I2S0_RX_MCLK_FUNC         1
+#elif    (RTE_I2S0_RX_MCLK_PIN_SEL == 3)
+  #define RTE_I2S0_RX_MCLK_PORT         6
+  #define RTE_I2S0_RX_MCLK_BIT          0
+  #define RTE_I2S0_RX_MCLK_FUNC         1
+#else
+  #error "Invalid I2S0 I2S0_RX_MCLK Pin Configuration!"
+#endif
+#ifndef   RTE_I2S0_RX_MCLK_PIN_EN
+#define   RTE_I2S0_RX_MCLK_PIN_EN       1
+#endif
+//     <o> I2S0_TX_SCK <0=>Not used <1=>P3_0 <2=>P4_7
+//     <i> Transmit clock for I2S0
+#define   RTE_I2S0_TX_SCK_PIN_SEL       1
+#if      (RTE_I2S0_TX_SCK_PIN_SEL == 0)
+#define   RTE_I2S0_TX_SCK_PIN_EN        0
+#elif    (RTE_I2S0_TX_SCK_PIN_SEL == 1)
+  #define RTE_I2S0_TX_SCK_PORT          3
+  #define RTE_I2S0_TX_SCK_BIT           0
+  #define RTE_I2S0_TX_SCK_FUNC          2
+#elif    (RTE_I2S0_TX_SCK_PIN_SEL == 2)
+  #define RTE_I2S0_TX_SCK_PORT          4
+  #define RTE_I2S0_TX_SCK_BIT           7
+  #define RTE_I2S0_TX_SCK_FUNC          7
+#else
+  #error "Invalid I2S0 I2S0_TX_SCK Pin Configuration!"
+#endif
+#ifndef   RTE_I2S0_TX_SCK_PIN_EN
+#define   RTE_I2S0_TX_SCK_PIN_EN        1
+#endif
+//     <o> I2S0_TX_WS <0=>Not used <1=>P0_0 <2=>P3_1 <3=>P3_4 <4=>P7_1 <5=>P9_1 <6=>PC_13
+//     <i> Transmit word select for I2S0
+#define   RTE_I2S0_TX_WS_PIN_SEL        4
+#if      (RTE_I2S0_TX_WS_PIN_SEL == 0)
+#define   RTE_I2S0_TX_WS_PIN_EN         0
+#elif    (RTE_I2S0_TX_WS_PIN_SEL == 1)
+  #define RTE_I2S0_TX_WS_PORT           0
+  #define RTE_I2S0_TX_WS_BIT            0
+  #define RTE_I2S0_TX_WS_FUNC           6
+#elif    (RTE_I2S0_TX_WS_PIN_SEL == 2)
+  #define RTE_I2S0_TX_WS_PORT           3
+  #define RTE_I2S0_TX_WS_BIT            1
+  #define RTE_I2S0_TX_WS_FUNC           0
+#elif    (RTE_I2S0_TX_WS_PIN_SEL == 3)
+  #define RTE_I2S0_TX_WS_PORT           3
+  #define RTE_I2S0_TX_WS_BIT            4
+  #define RTE_I2S0_TX_WS_FUNC           5
+#elif    (RTE_I2S0_TX_WS_PIN_SEL == 4)
+  #define RTE_I2S0_TX_WS_PORT           7
+  #define RTE_I2S0_TX_WS_BIT            1
+  #define RTE_I2S0_TX_WS_FUNC           2
+#elif    (RTE_I2S0_TX_WS_PIN_SEL == 5)
+  #define RTE_I2S0_TX_WS_PORT           9
+  #define RTE_I2S0_TX_WS_BIT            1
+  #define RTE_I2S0_TX_WS_FUNC           4
+#elif    (RTE_I2S0_TX_WS_PIN_SEL == 6)
+  #define RTE_I2S0_TX_WS_PORT           0xC
+  #define RTE_I2S0_TX_WS_BIT            13
+  #define RTE_I2S0_TX_WS_FUNC           6
+#else
+  #error "Invalid I2S0 I2S0_TX_WS Pin Configuration!"
+#endif
+#ifndef   RTE_I2S0_TX_WS_PIN_EN
+#define   RTE_I2S0_TX_WS_PIN_EN         1
+#endif
+//     <o> I2S0_TX_SDA <0=>Not used <1=>P3_2 <2=>P3_5 <3=>P7_2 <4=>P9_2  <5=>PC_12
+//     <i> Transmit data for I2S0
+#define   RTE_I2S0_TX_SDA_PIN_SEL       3
+#if      (RTE_I2S0_TX_SDA_PIN_SEL == 0)
+#define   RTE_I2S0_TX_SDA_PIN_EN        0
+#elif    (RTE_I2S0_TX_SDA_PIN_SEL == 1)
+  #define RTE_I2S0_TX_SDA_PORT          3
+  #define RTE_I2S0_TX_SDA_BIT           2
+  #define RTE_I2S0_TX_SDA_FUNC          0
+#elif    (RTE_I2S0_TX_SDA_PIN_SEL == 2)
+  #define RTE_I2S0_TX_SDA_PORT          3
+  #define RTE_I2S0_TX_SDA_BIT           5
+  #define RTE_I2S0_TX_SDA_FUNC          5
+#elif    (RTE_I2S0_TX_SDA_PIN_SEL == 3)
+  #define RTE_I2S0_TX_SDA_PORT          7
+  #define RTE_I2S0_TX_SDA_BIT           2
+  #define RTE_I2S0_TX_SDA_FUNC          2
+#elif    (RTE_I2S0_TX_SDA_PIN_SEL == 4)
+  #define RTE_I2S0_TX_SDA_PORT          9
+  #define RTE_I2S0_TX_SDA_BIT           2
+  #define RTE_I2S0_TX_SDA_FUNC          4
+#elif    (RTE_I2S0_TX_SDA_PIN_SEL == 5)
+  #define RTE_I2S0_TX_SDA_PORT          0xC
+  #define RTE_I2S0_TX_SDA_BIT           12
+  #define RTE_I2S0_TX_SDA_FUNC          6
+#else
+  #error "Invalid I2S0 I2S0_TX_SDA Pin Configuration!"
+#endif
+#ifndef   RTE_I2S0_TX_SDA_PIN_EN
+#define   RTE_I2S0_TX_SDA_PIN_EN        1
+#endif
+//     <o> I2S0_TX_MCLK <0=>Not used <1=>P3_0 <2=>P3_3 <3=>PF_4 <4=>CLK2
+//     <i> Transmit master clock for I2S0
+#define   RTE_I2S0_TX_MCLK_PIN_SEL      2
+#if      (RTE_I2S0_TX_MCLK_PIN_SEL == 0)
+#define   RTE_I2S0_TX_MCLK_PIN_EN       0
+#elif    (RTE_I2S0_TX_MCLK_PIN_SEL == 1)
+  #define RTE_I2S0_TX_MCLK_PORT         3
+  #define RTE_I2S0_TX_MCLK_BIT          0
+  #define RTE_I2S0_TX_MCLK_FUNC         3
+#elif    (RTE_I2S0_TX_MCLK_PIN_SEL == 2)
+  #define RTE_I2S0_TX_MCLK_PORT         3
+  #define RTE_I2S0_TX_MCLK_BIT          3
+  #define RTE_I2S0_TX_MCLK_FUNC         6
+#elif    (RTE_I2S0_TX_MCLK_PIN_SEL == 3)
+  #define RTE_I2S0_TX_MCLK_PORT         0xf
+  #define RTE_I2S0_TX_MCLK_BIT          4
+  #define RTE_I2S0_TX_MCLK_FUNC         6
+#elif    (RTE_I2S0_TX_MCLK_PIN_SEL == 4)
+  #define RTE_I2S0_TX_MCLK_PORT         0x10
+  #define RTE_I2S0_TX_MCLK_BIT          2
+  #define RTE_I2S0_TX_MCLK_FUNC         6
+#else
+  #error "Invalid I2S0 I2S0_TX_MCLK Pin Configuration!"
+#endif
+#ifndef   RTE_I2S0_TX_MCLK_PIN_EN
+#define   RTE_I2S0_TX_MCLK_PIN_EN       1
+#endif
+//   </h> Pin Configuration
+
+//   <h> DMA
+//     <e> Tx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>9 (DMAMUXPER9)
+//     </e>
+#define   RTE_I2S0_DMA_TX_EN            0
+#define   RTE_I2S0_DMA_TX_CH            0
+#define   RTE_I2S0_DMA_TX_PERI_ID       0
+#if      (RTE_I2S0_DMA_TX_PERI_ID == 0)
+  #define RTE_I2S0_DMA_TX_PERI          9
+  #define RTE_I2S0_DMA_TX_PERI_SEL      1
+#endif
+//     <e> Rx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>10 (DMAMUXPER10)
+//     </e>
+#define   RTE_I2S0_DMA_RX_EN            0
+#define   RTE_I2S0_DMA_RX_CH            1
+#define   RTE_I2S0_DMA_RX_PERI_ID       0
+#if      (RTE_I2S0_DMA_RX_PERI_ID == 0)
+  #define RTE_I2S0_DMA_RX_PERI          10
+  #define RTE_I2S0_DMA_RX_PERI_SEL      1
+#endif
+//   </h> DMA
+// </e> I2S0 (Integrated Interchip Sound 0) [Driver_SAI0]
+
+// <e> I2S1 (Integrated Interchip Sound 1) [Driver_SAI1]
+// <i> Configuration settings for Driver_I2S1 in component ::Drivers:SAI
+#define   RTE_I2S1                      0
+
+//   <h> Pin Configuration
+//     <o> I2S1_RX_SCK <0=>Not used <1=>CLK2 <2=>CLK3
+//     <i> Receive clock for I2S1
+#define   RTE_I2S1_RX_SCK_PIN_SEL       0
+#if      (RTE_I2S1_RX_SCK_PIN_SEL == 0)
+#define   RTE_I2S1_RX_SCK_PIN_EN        0
+#elif    (RTE_I2S1_RX_SCK_PIN_SEL == 1)
+  #define RTE_I2S1_RX_SCK_PORT          0x10
+  #define RTE_I2S1_RX_SCK_BIT           2
+  #define RTE_I2S1_RX_SCK_FUNC          7
+#elif    (RTE_I2S1_RX_SCK_PIN_SEL == 2)
+  #define RTE_I2S1_RX_SCK_PORT          0x10
+  #define RTE_I2S1_RX_SCK_BIT           3
+  #define RTE_I2S1_RX_SCK_FUNC          7
+#else
+  #error "Invalid I2S1 I2S1_RX_SCK Pin Configuration!"
+#endif
+#ifndef   RTE_I2S1_RX_SCK_PIN_EN
+#define   RTE_I2S1_RX_SCK_PIN_EN        1
+#endif
+//     <o> I2S1_RX_WS <0=>Not used <1=>P3_5
+//     <i> Receive word select for I2S1
+#define   RTE_I2S1_RX_WS_PIN_SEL        0
+#if      (RTE_I2S1_RX_WS_PIN_SEL == 0)
+#define   RTE_I2S1_RX_WS_PIN_EN         0
+#elif    (RTE_I2S1_RX_WS_PIN_SEL == 1)
+  #define RTE_I2S1_RX_WS_PORT           3
+  #define RTE_I2S1_RX_WS_BIT            5
+  #define RTE_I2S1_RX_WS_FUNC           6
+#else
+  #error "Invalid I2S1 I2S1_RX_WS Pin Configuration!"
+#endif
+#ifndef   RTE_I2S1_RX_WS_PIN_EN
+#define   RTE_I2S1_RX_WS_PIN_EN         1
+#endif
+//     <o> I2S1_RX_SDA <0=>Not used <1=>P3_4
+//     <i> Receive master clock for I2S1
+#define   RTE_I2S1_RX_SDA_PIN_SEL       0
+#if      (RTE_I2S1_RX_SDA_PIN_SEL == 0)
+#define   RTE_I2S1_RX_SDA_PIN_EN        0
+#elif    (RTE_I2S1_RX_SDA_PIN_SEL == 1)
+  #define RTE_I2S1_RX_SDA_PORT          3
+  #define RTE_I2S1_RX_SDA_BIT           4
+  #define RTE_I2S1_RX_SDA_FUNC          6
+#else
+  #error "Invalid I2S1 I2S1_RX_SDA Pin Configuration!"
+#endif
+#ifndef   RTE_I2S1_RX_SDA_PIN_EN
+#define   RTE_I2S1_RX_SDA_PIN_EN       1
+#endif
+//     <o> I2S1_RX_MCLK <0=>Not used <1=>PA_0
+//     <i> Receive master clock for I2S1
+#define   RTE_I2S1_RX_MCLK_PIN_SEL      0
+#if      (RTE_I2S1_RX_MCLK_PIN_SEL == 0)
+#define   RTE_I2S1_RX_MCLK_PIN_EN       0
+#elif    (RTE_I2S1_RX_MCLK_PIN_SEL == 1)
+  #define RTE_I2S1_RX_MCLK_PORT         0x0A
+  #define RTE_I2S1_RX_MCLK_BIT          0
+  #define RTE_I2S1_RX_MCLK_FUNC         5
+#else
+  #error "Invalid I2S1 I2S1_RX_MCLK Pin Configuration!"
+#endif
+#ifndef   RTE_I2S1_RX_MCLK_PIN_EN
+#define   RTE_I2S1_RX_MCLK_PIN_EN       1
+#endif
+//     <o> I2S1_TX_SCK <0=>Not used <1=>P1_19 <2=>P3_3 <3=>P4_7
+//     <i> Transmit clock for I2S1
+#define   RTE_I2S1_TX_SCK_PIN_SEL       0
+#if      (RTE_I2S1_TX_SCK_PIN_SEL == 0)
+#define   RTE_I2S1_TX_SCK_PIN_EN        0
+#elif    (RTE_I2S1_TX_SCK_PIN_SEL == 1)
+  #define RTE_I2S1_TX_SCK_PORT          1
+  #define RTE_I2S1_TX_SCK_BIT           19
+  #define RTE_I2S1_TX_SCK_FUNC          7
+#elif    (RTE_I2S1_TX_SCK_PIN_SEL == 2)
+  #define RTE_I2S1_TX_SCK_PORT          3
+  #define RTE_I2S1_TX_SCK_BIT           3
+  #define RTE_I2S1_TX_SCK_FUNC          7
+#elif    (RTE_I2S1_TX_SCK_PIN_SEL == 3)
+  #define RTE_I2S1_TX_SCK_PORT          4
+  #define RTE_I2S1_TX_SCK_BIT           7
+  #define RTE_I2S1_TX_SCK_FUNC          6
+#else
+  #error "Invalid I2S1 I2S1_TX_SCK Pin Configuration!"
+#endif
+#ifndef   RTE_I2S1_TX_SCK_PIN_EN
+#define   RTE_I2S1_TX_SCK_PIN_EN        1
+#endif
+//     <o> I2S1_TX_WS <0=>Not used <1=>P0_0 <2=>PF_7
+//     <i> Transmit word select for I2S1
+#define   RTE_I2S1_TX_WS_PIN_SEL        0
+#if      (RTE_I2S1_TX_WS_PIN_SEL == 0)
+#define   RTE_I2S1_TX_WS_PIN_EN         0
+#elif    (RTE_I2S1_TX_WS_PIN_SEL == 1)
+  #define RTE_I2S1_TX_WS_PORT           0
+  #define RTE_I2S1_TX_WS_BIT            0
+  #define RTE_I2S1_TX_WS_FUNC           7
+#elif    (RTE_I2S1_TX_WS_PIN_SEL == 2)
+  #define RTE_I2S1_TX_WS_PORT           0x0F
+  #define RTE_I2S1_TX_WS_BIT            7
+  #define RTE_I2S1_TX_WS_FUNC           7
+#else
+  #error "Invalid I2S1 I2S1_TX_WS Pin Configuration!"
+#endif
+#ifndef   RTE_I2S1_TX_WS_PIN_EN
+#define   RTE_I2S1_TX_WS_PIN_EN         1
+#endif
+//     <o> I2S1_TX_SDA <0=>Not used <1=>P0_1 <2=>PF_6
+//     <i> Transmit data for I2S
+#define   RTE_I2S1_TX_SDA_PIN_SEL       0
+#if      (RTE_I2S1_TX_SDA_PIN_SEL == 0)
+#define   RTE_I2S1_TX_SDA_PIN_EN        0
+#elif    (RTE_I2S1_TX_SDA_PIN_SEL == 1)
+  #define RTE_I2S1_TX_SDA_PORT          0
+  #define RTE_I2S1_TX_SDA_BIT           1
+  #define RTE_I2S1_TX_SDA_FUNC          7
+#elif    (RTE_I2S1_TX_SDA_PIN_SEL == 2)
+  #define RTE_I2S1_TX_SDA_PORT          0x0F
+  #define RTE_I2S1_TX_SDA_BIT           6
+  #define RTE_I2S1_TX_SDA_FUNC          7
+#else
+  #error "Invalid I2S1 I2S1_TX_SDA Pin Configuration!"
+#endif
+#ifndef   RTE_I2S1_TX_SDA_PIN_EN
+#define   RTE_I2S1_TX_SDA_PIN_EN        1
+#endif
+//     <o> I2S1_TX_MCLK <0=>Not used <1=>P8_8 <2=>PF_0 <3=>CLK1
+//     <i> Transmit master clock for I2S1
+#define   RTE_I2S1_TX_MCLK_PIN_SEL      0
+#if      (RTE_I2S1_TX_MCLK_PIN_SEL == 0)
+#define   RTE_I2S1_TX_MCLK_PIN_EN       0
+#elif    (RTE_I2S1_TX_MCLK_PIN_SEL == 1)
+  #define RTE_I2S1_TX_MCLK_PORT         8
+  #define RTE_I2S1_TX_MCLK_BIT          8
+  #define RTE_I2S1_TX_MCLK_FUNC         7
+#elif    (RTE_I2S1_TX_MCLK_PIN_SEL == 2)
+  #define RTE_I2S1_TX_MCLK_PORT         0x0F
+  #define RTE_I2S1_TX_MCLK_BIT          0
+  #define RTE_I2S1_TX_MCLK_FUNC         7
+#elif    (RTE_I2S1_TX_MCLK_PIN_SEL == 3)
+  #define RTE_I2S1_TX_MCLK_PORT         0x10
+  #define RTE_I2S1_TX_MCLK_BIT          1
+  #define RTE_I2S1_TX_MCLK_FUNC         7
+#else
+  #error "Invalid I2S1 I2S1_TX_MCLK Pin Configuration!"
+#endif
+#ifndef   RTE_I2S1_TX_MCLK_PIN_EN
+#define   RTE_I2S1_TX_MCLK_PIN_EN       1
+#endif
+//   </h> Pin Configuration
+
+//   <h> DMA
+//     <e> Tx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>3 (DMAMUXPER3)
+//     </e>
+#define   RTE_I2S1_DMA_TX_EN            0
+#define   RTE_I2S1_DMA_TX_CH            0
+#define   RTE_I2S1_DMA_TX_PERI_ID       0
+#if      (RTE_I2S1_DMA_TX_PERI_ID == 0)
+  #define RTE_I2S1_DMA_TX_PERI          3
+  #define RTE_I2S1_DMA_TX_PERI_SEL      2
+#endif
+//     <e> Rx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>4 (DMAMUXPER4)
+//     </e>
+#define   RTE_I2S1_DMA_RX_EN            0
+#define   RTE_I2S1_DMA_RX_CH            1
+#define   RTE_I2S1_DMA_RX_PERI_ID       0
+#if      (RTE_I2S1_DMA_RX_PERI_ID == 0)
+  #define RTE_I2S1_DMA_RX_PERI          4
+  #define RTE_I2S1_DMA_RX_PERI_SEL      2
+#endif
+//   </h> DMA
+// </e> I2S1 (Integrated Interchip Sound 1) [Driver_SAI1]
+
+// <e> CAN0 Controller [Driver_CAN0]
+// <i> Configuration settings for Driver_CAN0 in component ::Drivers:CAN
+#define   RTE_CAN_CAN0                  0
+
+//   <h> Pin Configuration
+//     <o> CAN0_RD <0=>Not used <1=>P3_1 <2=>PE_2
+//     <i> CAN0 receiver input.
+#define   RTE_CAN0_RD_ID                0
+#if      (RTE_CAN0_RD_ID == 0)
+  #define RTE_CAN0_RD_PIN_EN            0
+#elif    (RTE_CAN0_RD_ID == 1)
+  #define RTE_CAN0_RD_PORT              3
+  #define RTE_CAN0_RD_BIT               1
+  #define RTE_CAN0_RD_FUNC              2
+#elif    (RTE_CAN0_RD_ID == 2)
+  #define RTE_CAN0_RD_PORT              0xE
+  #define RTE_CAN0_RD_BIT               2
+  #define RTE_CAN0_RD_FUNC              1
+#else
+  #error "Invalid RTE_CAN0_RD Pin Configuration!"
+#endif
+#ifndef   RTE_CAN0_RD_PIN_EN
+  #define RTE_CAN0_RD_PIN_EN            1
+#endif
+//     <o> CAN0_TD <0=>Not used <1=>P3_2 <2=>PE_3
+//     <i> CAN0 transmitter output.
+#define   RTE_CAN0_TD_ID                0
+#if      (RTE_CAN0_TD_ID == 0)
+  #define RTE_CAN0_TD_PIN_EN            0
+#elif    (RTE_CAN0_TD_ID == 1)
+  #define RTE_CAN0_TD_PORT              3
+  #define RTE_CAN0_TD_BIT               2
+  #define RTE_CAN0_TD_FUNC              2
+#elif    (RTE_CAN0_TD_ID == 2)
+  #define RTE_CAN0_TD_PORT              0xE
+  #define RTE_CAN0_TD_BIT               3
+  #define RTE_CAN0_TD_FUNC              1
+#else
+  #error "Invalid RTE_CAN0_TD Pin Configuration!"
+#endif
+#ifndef   RTE_CAN0_TD_PIN_EN
+  #define RTE_CAN0_TD_PIN_EN            1
+#endif
+//   </h> Pin Configuration
+// </e> CAN0 Controller [Driver_CAN0]
+
+// <e> CAN1 Controller [Driver_CAN1]
+// <i> Configuration settings for Driver_CAN1 in component ::Drivers:CAN
+#define   RTE_CAN_CAN1                  0
+
+//   <h> Pin Configuration
+//     <o> CAN1_RD <0=>Not used <1=>P1_18 <2=>P4_9 <3=>PE_1
+//     <i> CAN1 receiver input.
+#define   RTE_CAN1_RD_ID                0
+#if      (RTE_CAN1_RD_ID == 0)
+  #define RTE_CAN1_RD_PIN_EN            0
+#elif    (RTE_CAN1_RD_ID == 1)
+  #define RTE_CAN1_RD_PORT              1
+  #define RTE_CAN1_RD_BIT               18
+  #define RTE_CAN1_RD_FUNC              5
+#elif    (RTE_CAN1_RD_ID == 2)
+  #define RTE_CAN1_RD_PORT              4
+  #define RTE_CAN1_RD_BIT               9
+  #define RTE_CAN1_RD_FUNC              6
+#elif    (RTE_CAN1_RD_ID == 3)
+  #define RTE_CAN1_RD_PORT              0xE
+  #define RTE_CAN1_RD_BIT               1
+  #define RTE_CAN1_RD_FUNC              5
+#else
+  #error "Invalid RTE_CAN1_RD Pin Configuration!"
+#endif
+#ifndef   RTE_CAN1_RD_PIN_EN
+  #define RTE_CAN1_RD_PIN_EN            1
+#endif
+//     <o> CAN1_TD <0=>Not used <1=>P1_17 <2=>P4_8 <3=>PE_0
+//     <i> CAN1 transmitter output.
+#define   RTE_CAN1_TD_ID                0
+#if      (RTE_CAN1_TD_ID == 0)
+  #define RTE_CAN1_TD_PIN_EN            0
+#elif    (RTE_CAN1_TD_ID == 1)
+  #define RTE_CAN1_TD_PORT              1
+  #define RTE_CAN1_TD_BIT               17
+  #define RTE_CAN1_TD_FUNC              5
+#elif    (RTE_CAN1_TD_ID == 2)
+  #define RTE_CAN1_TD_PORT              4
+  #define RTE_CAN1_TD_BIT               8
+  #define RTE_CAN1_TD_FUNC              6
+#elif    (RTE_CAN1_TD_ID == 3)
+  #define RTE_CAN1_TD_PORT              0xE
+  #define RTE_CAN1_TD_BIT               0
+  #define RTE_CAN1_TD_FUNC              5
+#else
+  #error "Invalid RTE_CAN1_TD Pin Configuration!"
+#endif
+#ifndef   RTE_CAN1_TD_PIN_EN
+  #define RTE_CAN1_TD_PIN_EN            1
+#endif
+//   </h> Pin Configuration
+// </e> CAN1 Controller [Driver_CAN1]
+
+
+#endif  /* __RTE_DEVICE_H */

CMSIS/Pack/Example/Boards/Keil/MCB1800/Blinky_ULp/RTE/Device/LPC1857/startup_LPC18xx.s

@@ -0,0 +1,324 @@
+;/***********************************************************************
+; * $Id: startup_LPC18xx.s 6471 2011-02-16 17:13:35Z nxp27266 $
+; *
+; * Project: LPC18xx CMSIS Package
+; *
+; * Description: Cortex-M3 Core Device Startup File for the NXP LPC18xx
+; *              Device Series.
+; *
+; * Copyright(C) 2011, NXP Semiconductor
+; * All rights reserved.
+; *
+; *                                                      modified by KEIL
+; ***********************************************************************
+; * Software that is described herein is for illustrative purposes only
+; * which provides customers with programming information regarding the
+; * products. This software is supplied "AS IS" without any warranties.
+; * NXP Semiconductors assumes no responsibility or liability for the
+; * use of the software, conveys no license or title under any patent,
+; * copyright, or mask work right to the product. NXP Semiconductors
+; * reserves the right to make changes in the software without
+; * notification. NXP Semiconductors also make no representation or
+; * warranty that such application will be suitable for the specified
+; * use without further testing or modification.
+; **********************************************************************/
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+
+Sign_Value      EQU     0x5A5A5A5A
+
+__Vectors       DCD     __initial_sp              ; 0 Top of Stack
+                DCD     Reset_Handler             ; 1 Reset Handler
+                DCD     NMI_Handler               ; 2 NMI Handler
+                DCD     HardFault_Handler         ; 3 Hard Fault Handler
+                DCD     MemManage_Handler         ; 4 MPU Fault Handler
+                DCD     BusFault_Handler          ; 5 Bus Fault Handler
+                DCD     UsageFault_Handler        ; 6 Usage Fault Handler
+                DCD     Sign_Value                ; 7 Reserved
+                DCD     0                         ; 8 Reserved
+                DCD     0                         ; 9 Reserved
+                DCD     0                         ; 10 Reserved
+                DCD     SVC_Handler               ; 11 SVCall Handler
+                DCD     DebugMon_Handler          ; 12 Debug Monitor Handler
+                DCD     0                         ; 13 Reserved
+                DCD     PendSV_Handler            ; 14 PendSV Handler
+                DCD     SysTick_Handler           ; 15 SysTick Handler
+
+                ; External Interrupts
+                DCD     DAC_IRQHandler            ; 16 D/A Converter
+                DCD     0                         ; 17 Reserved
+                DCD     DMA_IRQHandler            ; 18 General Purpose DMA
+                DCD     0                         ; 19 Reserved
+                DCD     FLASHEEPROM_IRQHandler    ; 20 ORed flash bank A, flash bank B, EEPROM interrupt
+                DCD     ETH_IRQHandler            ; 21 Ethernet
+                DCD     SDIO_IRQHandler           ; 22 SD/MMC
+                DCD     LCD_IRQHandler            ; 23 LCD
+                DCD     USB0_IRQHandler           ; 24 USB0
+                DCD     USB1_IRQHandler           ; 25 USB1
+                DCD     SCT_IRQHandler            ; 26 State Configurable Timer
+                DCD     RIT_IRQHandler            ; 27 Repetitive Interrupt Timer
+                DCD     TIMER0_IRQHandler         ; 28 Timer0
+                DCD     TIMER1_IRQHandler         ; 29 Timer1
+                DCD     TIMER2_IRQHandler         ; 30 Timer2
+                DCD     TIMER3_IRQHandler         ; 31 Timer3
+                DCD     MCPWM_IRQHandler          ; 32 Motor Control PWM
+                DCD     ADC0_IRQHandler           ; 33 A/D Converter 0
+                DCD     I2C0_IRQHandler           ; 34 I2C0
+                DCD     I2C1_IRQHandler           ; 35 I2C1
+                DCD     0                         ; 36 Reserved
+                DCD     ADC1_IRQHandler           ; 37 A/D Converter 1
+                DCD     SSP0_IRQHandler           ; 38 SSP0
+                DCD     SSP1_IRQHandler           ; 39 SSP1
+                DCD     UART0_IRQHandler          ; 40 UART0
+                DCD     UART1_IRQHandler          ; 41 UART1
+                DCD     UART2_IRQHandler          ; 42 UART2
+                DCD     UART3_IRQHandler          ; 43 UART3
+                DCD     I2S0_IRQHandler           ; 44 I2S0
+                DCD     I2S1_IRQHandler           ; 45 I2S1
+                DCD     0                         ; 46 Reserved
+                DCD     0                         ; 47 Reserved
+                DCD     GPIO0_IRQHandler          ; 48 GPIO0
+                DCD     GPIO1_IRQHandler          ; 49 GPIO1
+                DCD     GPIO2_IRQHandler          ; 50 GPIO2
+                DCD     GPIO3_IRQHandler          ; 51 GPIO3
+                DCD     GPIO4_IRQHandler          ; 52 GPIO4
+                DCD     GPIO5_IRQHandler          ; 53 GPIO5
+                DCD     GPIO6_IRQHandler          ; 54 GPIO6
+                DCD     GPIO7_IRQHandler          ; 55 GPIO7
+                DCD     GINT0_IRQHandler          ; 56 GINT0
+                DCD     GINT1_IRQHandler          ; 57 GINT1
+                DCD     EVRT_IRQHandler           ; 58 Event Router
+                DCD     CAN1_IRQHandler           ; 59 C_CAN1
+                DCD     0                         ; 60 Reserved
+                DCD     0                         ; 61 Reserved
+                DCD     ATIMER_IRQHandler         ; 62 ATIMER
+                DCD     RTC_IRQHandler            ; 63 RTC
+                DCD     0                         ; 64 Reserved
+                DCD     WDT_IRQHandler            ; 65 WDT
+                DCD     0                         ; 66 Reserved
+                DCD     CAN0_IRQHandler           ; 67 C_CAN0
+                DCD     QEI_IRQHandler            ; 68 QEI
+
+
+;CRP address at offset 0x2FC relative to the BOOT Bank address
+                IF      :LNOT::DEF:NO_CRP
+                SPACE   (0x2FC - (. - __Vectors))
+;                EXPORT  CRP_Key
+CRP_Key         DCD     0xFFFFFFFF
+;                       0xFFFFFFFF => CRP Disabled
+;                       0x12345678 => CRP Level 1
+;                       0x87654321 => CRP Level 2
+;                       0x43218765 => CRP Level 3 (ARE YOU SURE?)
+;                       0x4E697370 => NO ISP      (ARE YOU SURE?)
+                ENDIF
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler           [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler             [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler       [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler       [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler        [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler      [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler             [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler        [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler          [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler         [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  DAC_IRQHandler          [WEAK]
+                EXPORT  DMA_IRQHandler          [WEAK]
+                EXPORT  FLASHEEPROM_IRQHandler  [WEAK]
+                EXPORT  ETH_IRQHandler          [WEAK]
+                EXPORT  SDIO_IRQHandler         [WEAK]
+                EXPORT  LCD_IRQHandler          [WEAK]
+                EXPORT  USB0_IRQHandler         [WEAK]
+                EXPORT  USB1_IRQHandler         [WEAK]
+                EXPORT  SCT_IRQHandler          [WEAK]
+                EXPORT  RIT_IRQHandler          [WEAK]
+                EXPORT  TIMER0_IRQHandler       [WEAK]
+                EXPORT  TIMER1_IRQHandler       [WEAK]
+                EXPORT  TIMER2_IRQHandler       [WEAK]
+                EXPORT  TIMER3_IRQHandler       [WEAK]
+                EXPORT  MCPWM_IRQHandler        [WEAK]
+                EXPORT  ADC0_IRQHandler         [WEAK]
+                EXPORT  I2C0_IRQHandler         [WEAK]
+                EXPORT  I2C1_IRQHandler         [WEAK]
+                EXPORT  ADC1_IRQHandler         [WEAK]
+                EXPORT  SSP0_IRQHandler         [WEAK]
+                EXPORT  SSP1_IRQHandler         [WEAK]
+                EXPORT  UART0_IRQHandler        [WEAK]
+                EXPORT  UART1_IRQHandler        [WEAK]
+                EXPORT  UART2_IRQHandler        [WEAK]
+                EXPORT  UART3_IRQHandler        [WEAK]
+                EXPORT  I2S0_IRQHandler         [WEAK]
+                EXPORT  I2S1_IRQHandler         [WEAK]
+                EXPORT  GPIO0_IRQHandler        [WEAK]
+                EXPORT  GPIO1_IRQHandler        [WEAK]
+                EXPORT  GPIO2_IRQHandler        [WEAK]
+                EXPORT  GPIO3_IRQHandler        [WEAK]
+                EXPORT  GPIO4_IRQHandler        [WEAK]
+                EXPORT  GPIO5_IRQHandler        [WEAK]
+                EXPORT  GPIO6_IRQHandler        [WEAK]
+                EXPORT  GPIO7_IRQHandler        [WEAK]
+                EXPORT  GINT0_IRQHandler        [WEAK]
+                EXPORT  GINT1_IRQHandler        [WEAK]
+                EXPORT  EVRT_IRQHandler         [WEAK]
+                EXPORT  CAN1_IRQHandler         [WEAK]
+                EXPORT  ATIMER_IRQHandler       [WEAK]
+                EXPORT  RTC_IRQHandler          [WEAK]
+                EXPORT  WDT_IRQHandler          [WEAK]
+                EXPORT  CAN0_IRQHandler         [WEAK]
+                EXPORT  QEI_IRQHandler          [WEAK]
+
+DAC_IRQHandler
+DMA_IRQHandler
+FLASHEEPROM_IRQHandler
+ETH_IRQHandler
+SDIO_IRQHandler
+LCD_IRQHandler
+USB0_IRQHandler
+USB1_IRQHandler
+SCT_IRQHandler
+RIT_IRQHandler
+TIMER0_IRQHandler
+TIMER1_IRQHandler
+TIMER2_IRQHandler
+TIMER3_IRQHandler
+MCPWM_IRQHandler
+ADC0_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+ADC1_IRQHandler
+SSP0_IRQHandler
+SSP1_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+I2S0_IRQHandler
+I2S1_IRQHandler
+GPIO0_IRQHandler
+GPIO1_IRQHandler
+GPIO2_IRQHandler
+GPIO3_IRQHandler
+GPIO4_IRQHandler
+GPIO5_IRQHandler
+GPIO6_IRQHandler
+GPIO7_IRQHandler
+GINT0_IRQHandler
+GINT1_IRQHandler
+EVRT_IRQHandler
+CAN1_IRQHandler
+ATIMER_IRQHandler
+RTC_IRQHandler
+WDT_IRQHandler
+CAN0_IRQHandler
+QEI_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END

CMSIS/Pack/Example/Boards/Keil/MCB1800/Blinky_ULp/RTE/Device/LPC1857/system_LPC18xx.c

@@ -0,0 +1,901 @@
+/* -----------------------------------------------------------------------------
+ * Copyright (c) 2013 - 2015 ARM Ltd.
+ *
+ * This software is provided 'as-is', without any express or implied warranty.
+ * In no event will the authors be held liable for any damages arising from
+ * the use of this software. Permission is granted to anyone to use this
+ * software for any purpose, including commercial applications, and to alter
+ * it and redistribute it freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software in
+ *    a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ *
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ *
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * $Date:        26. August 2015
+ * $Revision:    V5.0.1
+ *
+ * Project:      NXP LPC18xx System initialization
+ * -------------------------------------------------------------------------- */
+
+#include "LPC18xx.h"
+
+/*----------------------------------------------------------------------------
+  This file configures the clocks as follows:
+ -----------------------------------------------------------------------------
+ Clock Unit  |  Output clock  |  Source clock  |          Note
+ -----------------------------------------------------------------------------
+   PLL0USB   |    480 MHz     |      XTAL      | External crystal @ 12 MHz
+ -----------------------------------------------------------------------------
+    PLL1     |    120 MHz     |      XTAL      | External crystal @ 12 MHz
+ -----------------------------------------------------------------------------
+    CPU      |    120 MHz     |      PLL1      | CPU Clock ==  BASE_M4_CLK
+ -----------------------------------------------------------------------------
+   IDIV A    |     60 MHz     |      PLL1      | To the USB1 peripheral
+ -----------------------------------------------------------------------------
+   IDIV B    |     25 MHz     |   ENET_TX_CLK  | ENET_TX_CLK @ 50MHz
+ -----------------------------------------------------------------------------
+   IDIV C    |     12 MHz     |      IRC       | Internal oscillator @ 12 MHz
+ -----------------------------------------------------------------------------
+   IDIV D    |     12 MHz     |      IRC       | Internal oscillator @ 12 MHz
+ -----------------------------------------------------------------------------
+   IDIV E    |    5.2 MHz     |      PLL1      | To the LCD controller
+ -----------------------------------------------------------------------------*/
+
+
+/*----------------------------------------------------------------------------
+  Clock source selection definitions (do not change)
+ *----------------------------------------------------------------------------*/
+#define CLK_SRC_32KHZ       0x00
+#define CLK_SRC_IRC         0x01
+#define CLK_SRC_ENET_RX     0x02
+#define CLK_SRC_ENET_TX     0x03
+#define CLK_SRC_GP_CLKIN    0x04
+#define CLK_SRC_XTAL        0x06
+#define CLK_SRC_PLL0U       0x07
+#define CLK_SRC_PLL0A       0x08
+#define CLK_SRC_PLL1        0x09
+#define CLK_SRC_IDIVA       0x0C
+#define CLK_SRC_IDIVB       0x0D
+#define CLK_SRC_IDIVC       0x0E
+#define CLK_SRC_IDIVD       0x0F
+#define CLK_SRC_IDIVE       0x10
+
+
+/*----------------------------------------------------------------------------
+  Define external input frequency values
+ *----------------------------------------------------------------------------*/
+#define CLK_32KHZ            32768UL    /* 32 kHz oscillator frequency        */
+#define CLK_IRC           12000000UL    /* Internal oscillator frequency      */
+#define CLK_ENET_RX       50000000UL    /* Ethernet Rx frequency              */
+#define CLK_ENET_TX       50000000UL    /* Ethernet Tx frequency              */
+#define CLK_GP_CLKIN      12000000UL    /* General purpose clock input freq.  */
+#define CLK_XTAL          12000000UL    /* Crystal oscilator frequency        */
+
+
+/*----------------------------------------------------------------------------
+  Define clock sources
+ *----------------------------------------------------------------------------*/
+#define PLL1_CLK_SEL      CLK_SRC_XTAL    /* PLL1 input clock: XTAL           */
+#define PLL0USB_CLK_SEL   CLK_SRC_XTAL    /* PLL0USB input clock: XTAL        */
+#define IDIVA_CLK_SEL     CLK_SRC_PLL1    /* IDIVA input clock: PLL1          */
+#define IDIVB_CLK_SEL     CLK_SRC_ENET_TX /* IDIVB input clock: ENET TX       */
+#define IDIVC_CLK_SEL     CLK_SRC_IRC     /* IDIVC input clock: IRC           */
+#define IDIVD_CLK_SEL     CLK_SRC_IRC     /* IDIVD input clock: IRC           */
+#define IDIVE_CLK_SEL     CLK_SRC_PLL1    /* IDIVD input clock: PLL1          */
+
+
+/*----------------------------------------------------------------------------
+  Configure integer divider values
+ *----------------------------------------------------------------------------*/
+#define IDIVA_IDIV        1             /* Divide input clock by 2            */
+#define IDIVB_IDIV        1             /* Divide input clock by 2            */
+#define IDIVC_IDIV        0             /* Divide input clock by 1            */
+#define IDIVD_IDIV        0             /* Divide input clock by 1            */
+#define IDIVE_IDIV       22             /* Divide input clock by 23           */
+
+
+/*----------------------------------------------------------------------------
+  Define CPU clock input
+ *----------------------------------------------------------------------------*/
+#define CPU_CLK_SEL       CLK_SRC_PLL1  /* Default CPU clock source is PLL1   */
+
+
+/*----------------------------------------------------------------------------
+  Configure external memory controller options
+ *----------------------------------------------------------------------------*/
+#define USE_EXT_STAT_MEM_CS0 1          /* Use ext. static  memory with CS0   */
+#define USE_EXT_DYN_MEM_CS0  1          /* Use ext. dynamic memory with CS0   */
+
+
+/*----------------------------------------------------------------------------
+ * Configure PLL1
+ *----------------------------------------------------------------------------
+ * Integer mode:
+ *    - PLL1_DIRECT = 0 (Post divider enabled)
+ *    - PLL1_FBSEL  = 1 (Feedback divider runs from PLL output)
+ *    - Output frequency:
+ *                        FCLKOUT = (FCLKIN / N) * M
+ *                        FCCO    = FCLKOUT * 2 * P
+ *
+ * Non-integer:
+ *    - PLL1_DIRECT = 0 (Post divider enabled)
+ *    - PLL1_FBSEL  = 0 (Feedback divider runs from CCO clock)
+ *    - Output frequency:
+ *                        FCLKOUT = (FCLKIN / N) * M / (2 * P)
+ *                        FCCO    = FCLKOUT * 2 * P
+ *
+ * Direct mode:
+ *    - PLL1_DIRECT = 1         (Post divider disabled)
+ *    - PLL1_FBSEL  = dont care (Feedback divider runs from CCO clock)
+ *    - Output frequency:
+ *                        FCLKOUT = (FCLKIN / N) * M
+ *                        FCCO    = FCLKOUT
+ *
+ *----------------------------------------------------------------------------
+ * PLL1 requirements:
+ * | Frequency |  Minimum  |  Maximum  |               Note                   |
+ * |  FCLKIN   |    1MHz   |   25MHz   |   Clock source is external crystal   |
+ * |  FCLKIN   |    1MHz   |   50MHz   |                                      |
+ * |   FCCO    |  156MHz   |  320MHz   |                                      |
+ * |  FCLKOUT  | 9.75MHz   |  320MHz   |                                      |
+ *----------------------------------------------------------------------------
+ * Configuration examples:
+ * | Fclkout |  Fcco  |  N  |  M  |  P  | DIRECT | FBSEL | BYPASS |
+ * |  36MHz | 288MHz |  1  |  24 |  4  |   0    |   0   |    0   |
+ * |  72MHz | 288MHz |  1  |  24 |  2  |   0    |   0   |    0   |
+ * | 100MHz | 200MHz |  3  |  50 |  1  |   0    |   0   |    0   |
+ * | 120MHz | 240MHz |  1  |  20 |  1  |   0    |   0   |    0   |
+ * | 160MHz | 160MHz |  3  |  40 |  x  |   1    |   0   |    0   |
+ * | 180MHz | 180MHz |  1  |  15 |  x  |   1    |   0   |    0   |
+ *----------------------------------------------------------------------------
+ * Relations beetwen PLL dividers and definitions:
+ * N = PLL1_NSEL + 1,     M = PLL1_MSEL + 1,     P = 2 ^ PLL1_PSEL
+ *----------------------------------------------------------------------------*/
+
+/* PLL1 output clock: 120MHz, Fcco: 240MHz, N = 1, M = 20, P = 1              */
+#define PLL1_NSEL   0           /* Range [0 -   3]: Pre-divider ratio N       */
+#define PLL1_MSEL  19           /* Range [0 - 255]: Feedback-divider ratio M  */
+#define PLL1_PSEL   0           /* Range [0 -   3]: Post-divider ratio P      */
+
+#define PLL1_BYPASS 0           /* 0: Use PLL, 1: PLL is bypassed             */
+#define PLL1_DIRECT 0           /* 0: Use PSEL, 1: Don't use PSEL             */
+#define PLL1_FBSEL  0           /* 0: FCCO is used as PLL feedback            */
+                                /* 1: FCLKOUT is used as PLL feedback         */
+
+
+/*----------------------------------------------------------------------------
+ * Configure PLL0USB
+ *----------------------------------------------------------------------------
+ *
+ *   Normal operating mode without post-divider and without pre-divider
+ *    - PLL0USB_DIRECTI = 1
+ *    - PLL0USB_DIRECTO = 1
+ *    - PLL0USB_BYPASS  = 0
+ *    - Output frequency:
+ *                        FOUT = FIN * 2 * M
+ *                        FCCO = FOUT
+ *
+ *   Normal operating mode with post-divider and without pre-divider
+ *    - PLL0USB_DIRECTI = 1
+ *    - PLL0USB_DIRECTO = 0
+ *    - PLL0USB_BYPASS  = 0
+ *    - Output frequency:
+ *                        FOUT = FIN * (M / P)
+ *                        FCCO = FOUT * 2 * P
+ *
+ *   Normal operating mode without post-divider and with pre-divider
+ *    - PLL0USB_DIRECTI = 0
+ *    - PLL0USB_DIRECTO = 1
+ *    - PLL0USB_BYPASS  = 0
+ *    - Output frequency:
+ *                        FOUT = FIN * 2 * M / N
+ *                        FCCO = FOUT
+ *
+ *   Normal operating mode with post-divider and with pre-divider
+ *    - PLL0USB_DIRECTI = 0
+ *    - PLL0USB_DIRECTO = 0
+ *    - PLL0USB_BYPASS  = 0
+ *    - Output frequency:
+ *                        FOUT = FIN * M / (P * N)
+ *                        FCCO = FOUT * 2 * P
+ *----------------------------------------------------------------------------
+ * PLL0 requirements:
+ * | Frequency |  Minimum  |  Maximum  |               Note                   |
+ * |  FCLKIN   |   14kHz   |   25MHz   |   Clock source is external crystal   |
+ * |  FCLKIN   |   14kHz   |  150MHz   |                                      |
+ * |   FCCO    |  275MHz   |  550MHz   |                                      |
+ * |  FCLKOUT  |  4.3MHz   |  550MHz   |                                      |
+ *----------------------------------------------------------------------------
+ * Configuration examples:
+ * | Fclkout |  Fcco  |  N  |  M  |  P  | DIRECTI | DIRECTO | BYPASS |
+ * | 120MHz | 480MHz |  x  |  20 |  2  |    1    |    0    |    0   |
+ * | 480MHz | 480MHz |  1  |  20 |  1  |    1    |    1    |    0   |
+ *----------------------------------------------------------------------------*/
+
+/* PLL0USB output clock: 480MHz, Fcco: 480MHz, N = 1, M = 20, P = 1           */
+#define PLL0USB_N       1       /* Range [1 -  256]: Pre-divider              */
+#define PLL0USB_M      20       /* Range [1 - 2^15]: Feedback-divider         */
+#define PLL0USB_P       1       /* Range [1 -   32]: Post-divider             */
+
+#define PLL0USB_DIRECTI 1       /* 0: Use N_DIV, 1: Don't use N_DIV           */
+#define PLL0USB_DIRECTO 1       /* 0: Use P_DIV, 1: Don't use P_DIV           */
+#define PLL0USB_BYPASS  0       /* 0: Use PLL, 1: PLL is bypassed             */
+
+
+/*----------------------------------------------------------------------------
+  End of configuration
+ *----------------------------------------------------------------------------*/
+
+/* PLL0 Setting Check */
+#if (PLL0USB_BYPASS == 0)
+ #if (PLL0USB_CLK_SEL == CLK_SRC_XTAL)
+  #define PLL0USB_CLKIN CLK_XTAL
+ #else
+  #define PLL0USB_CLKIN CLK_IRC
+ #endif
+
+ #if   ((PLL0USB_DIRECTI == 1) && (PLL0USB_DIRECTO == 1)) /* Mode 1a          */
+  #define PLL0USB_FOUT (PLL0USB_CLKIN * 2 * PLL0USB_M)
+  #define PLL0USB_FCCO (PLL0USB_FOUT)
+ #elif ((PLL0USB_DIRECTI == 1) && (PLL0USB_DIRECTO == 0)) /* Mode 1b          */
+  #define PLL0USB_FOUT (PLL0USB_CLKIN * PLL0USB_M / PLL0USB_P)
+  #define PLL0USB_FCCO (PLL0USB_FOUT * 2 * PLL0USB_P)
+ #elif ((PLL0USB_DIRECTI == 0) && (PLL0USB_DIRECTO == 1)) /* Mode 1c          */
+  #define PLL0USB_FOUT (PLL0USB_CLKIN * 2 * PLL0USB_M / PLL0USB_N)
+  #define PLL0USB_FCCO (PLL0USB_FOUT)
+ #else                                                    /* Mode 1d          */
+  #define PLL0USB_FOUT (PLL0USB_CLKIN * PLL0USB_M / (PLL0USB_P * PLL0USB_N))
+  #define PLL0USB_FCCO (PLL0USB_FOUT * 2 * PLL0USB_P)
+ #endif
+
+ #if (PLL0USB_FCCO < 275000000UL || PLL0USB_FCCO > 550000000UL)
+  #error "PLL0USB Fcco frequency out of range! (275MHz >= Fcco <= 550MHz)"
+ #endif
+ #if (PLL0USB_FOUT < 4300000UL || PLL0USB_FOUT > 550000000UL)
+  #error "PLL0USB output frequency out of range! (4.3MHz >= Fclkout <= 550MHz)"
+ #endif
+#endif
+
+/* PLL1 Setting Check */
+#if (PLL1_BYPASS == 0)
+ #if (PLL1_CLK_SEL == CLK_SRC_XTAL)
+  #define PLL1_CLKIN CLK_XTAL
+ #else
+  #define PLL1_CLKIN CLK_IRC
+ #endif
+
+ #if   (PLL1_DIRECT == 1)               /* Direct Mode                        */
+  #define PLL1_FCCO ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
+  #define PLL1_FOUT ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
+ #elif (PLL1_FBSEL  == 1)               /* Integer Mode                       */
+  #define PLL1_FCCO ((2 * (1 << PLL1_PSEL)) * (PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
+  #define PLL1_FOUT ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
+ #else                                  /* Noninteger Mode                    */
+  #define PLL1_FCCO ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
+  #define PLL1_FOUT (PLL1_FCCO / (2 * (1 << PLL1_PSEL)))
+ #endif
+ #if (PLL1_FCCO < 156000000UL || PLL1_FCCO > 320000000UL)
+  #error "PLL1 Fcco frequency out of range! (156MHz >= Fcco <= 320MHz)"
+ #endif
+ #if (PLL1_FOUT < 9750000UL || PLL1_FOUT > 204000000UL)
+  #error "PLL1 output frequency out of range! (9.75MHz >= Fclkout <= 204MHz)"
+ #endif
+#endif
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = CLK_IRC;    /* System Clock Frequency (Core Clock) */
+
+
+/******************************************************************************
+ * SetClock
+ ******************************************************************************/
+void SetClock (void) {
+  uint32_t x, i;
+  uint32_t selp, seli;
+
+  /* Set flash wait states to maximum                                         */
+  LPC_EMC->STATICWAITRD0  = 0x1F;
+
+  /* Switch BASE_M3_CLOCK to IRC                                              */
+  LPC_CGU->BASE_M3_CLK = (0x01        << 11) |  /* Autoblock En               */
+                         (CLK_SRC_IRC << 24) ;  /* Set clock source           */
+
+  /* Configure input to crystal oscilator                                     */
+  LPC_CGU->XTAL_OSC_CTRL = (0 << 0) |   /* Enable oscillator-pad              */
+                           (0 << 1) |   /* Operation with crystal connected   */
+                           (0 << 2) ;   /* Low-frequency mode                 */
+
+  /* Wait ~250us @ 12MHz */
+  for (i = 1500; i; i--);
+
+#if (USE_SPIFI)
+/* configure SPIFI clk to IRC via IDIVA (later IDIVA is configured to PLL1/3) */
+  LPC_CGU->IDIVA_CTRL     = (0              <<  0) |  /* Disable Power-down   */
+                            (0              <<  2) |  /* IDIV                 */
+                            (1              << 11) |  /* Autoblock En         */
+                            (CLK_SRC_IRC    << 24) ;  /* Clock source         */
+
+  LPC_CGU->BASE_SPIFI_CLK = (0              <<  0) |  /* Disable Power-down   */
+                            (0              <<  2) |  /* IDIV                 */
+                            (1              << 11) |  /* Autoblock En         */
+                            (CLK_SRC_IDIVA  << 24) ;  /* Clock source         */
+#endif
+
+/*----------------------------------------------------------------------------
+  PLL1 Setup
+ *----------------------------------------------------------------------------*/
+  /* Power down PLL                                                           */
+  LPC_CGU->PLL1_CTRL |= 1;
+
+#if ((PLL1_FOUT > 110000000UL) && (CPU_CLK_SEL == CLK_SRC_PLL1))
+  /* To run at full speed, CPU must first run at an intermediate speed        */
+  LPC_CGU->PLL1_CTRL = (0            << 0) | /* PLL1 Enabled                  */
+                       (PLL1_BYPASS  << 1) | /* CCO out sent to post-dividers */
+                       (PLL1_FBSEL   << 6) | /* PLL output used as feedback   */
+                       (0            << 7) | /* Direct on/off                 */
+                       (PLL1_PSEL    << 8) | /* PSEL                          */
+                       (0            << 11)| /* Autoblock Disabled            */
+                       (PLL1_NSEL    << 12)| /* NSEL                          */
+                       (PLL1_MSEL    << 16)| /* MSEL                          */
+                       (PLL1_CLK_SEL << 24); /* Clock source                  */
+  /* Wait for lock                                                            */
+  while (!(LPC_CGU->PLL1_STAT & 1));
+
+  /* CPU base clock is in the mid frequency range before final clock set      */
+  LPC_CGU->BASE_M3_CLK     = (0x01 << 11) |  /* Autoblock En                  */
+                             (0x09 << 24) ;  /* Clock source: PLL1            */
+
+  /* Max. BASE_M3_CLK frequency here is 102MHz, wait at least 20us */
+  for (i = 1050; i; i--);                    /* Wait minimum 2100 cycles      */
+#endif
+  /* Configure PLL1                                                           */
+  LPC_CGU->PLL1_CTRL = (0            << 0) | /* PLL1 Enabled                  */
+                       (PLL1_BYPASS  << 1) | /* CCO out sent to post-dividers */
+                       (PLL1_FBSEL   << 6) | /* PLL output used as feedback   */
+                       (PLL1_DIRECT  << 7) | /* Direct on/off                 */
+                       (PLL1_PSEL    << 8) | /* PSEL                          */
+                       (1            << 11)| /* Autoblock En                  */
+                       (PLL1_NSEL    << 12)| /* NSEL                          */
+                       (PLL1_MSEL    << 16)| /* MSEL                          */
+                       (PLL1_CLK_SEL << 24); /* Clock source                  */
+
+  /* Wait for lock                                                            */
+  while (!(LPC_CGU->PLL1_STAT & 1));
+
+  /* Set CPU base clock source                                                */
+  LPC_CGU->BASE_M3_CLK = (0x01        << 11) |  /* Autoblock En               */
+                         (CPU_CLK_SEL << 24) ;  /* Set clock source           */
+
+/*----------------------------------------------------------------------------
+  PLL0USB Setup
+ *----------------------------------------------------------------------------*/
+
+  /* Power down PLL0USB                                                       */
+  LPC_CGU->PLL0USB_CTRL  |= 1;
+
+  /* M divider                                                                */
+  x = 0x00004000;
+  switch (PLL0USB_M) {
+    case 0:  x = 0xFFFFFFFF;
+      break;
+    case 1:  x = 0x00018003;
+      break;
+    case 2:  x = 0x00010003;
+      break;
+    default:
+      for (i = PLL0USB_M; i <= 0x8000; i++) {
+        x = (((x ^ (x >> 1)) & 1) << 14) | ((x >> 1) & 0x3FFF);
+      }
+  }
+
+  if (PLL0USB_M < 60) selp = (PLL0USB_M >> 1) + 1;
+  else        selp = 31;
+
+  if      (PLL0USB_M > 16384) seli = 1;
+  else if (PLL0USB_M >  8192) seli = 2;
+  else if (PLL0USB_M >  2048) seli = 4;
+  else if (PLL0USB_M >=  501) seli = 8;
+  else if (PLL0USB_M >=   60) seli = 4 * (1024 / (PLL0USB_M + 9));
+  else                        seli = (PLL0USB_M & 0x3C) + 4;
+  LPC_CGU->PLL0USB_MDIV   =  (selp   << 17) |
+                             (seli   << 22) |
+                             (x      <<  0);
+
+  /* N divider                                                                */
+  x = 0x80;
+  switch (PLL0USB_N) {
+    case 0:  x = 0xFFFFFFFF;
+      break;
+    case 1:  x = 0x00000302;
+      break;
+    case 2:  x = 0x00000202;
+      break;
+    default:
+      for (i = PLL0USB_N; i <= 0x0100; i++) {
+        x =(((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F);
+      }
+  }
+  LPC_CGU->PLL0USB_NP_DIV = (x << 12);
+
+  /* P divider                                                                */
+  x = 0x10;
+  switch (PLL0USB_P) {
+    case 0:  x = 0xFFFFFFFF;
+      break;
+    case 1:  x = 0x00000062;
+      break;
+    case 2:  x = 0x00000042;
+      break;
+    default:
+      for (i = PLL0USB_P; i <= 0x200; i++) {
+        x = (((x ^ (x >> 2)) & 1) << 4) | ((x >> 1) &0x0F);
+      }
+  }
+  LPC_CGU->PLL0USB_NP_DIV |= x;
+
+  LPC_CGU->PLL0USB_CTRL  = (PLL0USB_CLK_SEL   << 24) | /* Clock source sel    */
+                           (1                 << 11) | /* Autoblock En        */
+                           (1                 << 4 ) | /* PLL0USB clock en    */
+                           (PLL0USB_DIRECTO   << 3 ) | /* Direct output       */
+                           (PLL0USB_DIRECTI   << 2 ) | /* Direct input        */
+                           (PLL0USB_BYPASS    << 1 ) | /* PLL bypass          */
+                           (0                 << 0 ) ; /* PLL0USB Enabled     */
+  while (!(LPC_CGU->PLL0USB_STAT & 1));
+
+
+/*----------------------------------------------------------------------------
+  Integer divider Setup
+ *----------------------------------------------------------------------------*/
+
+  /* Configure integer dividers                                               */
+  LPC_CGU->IDIVA_CTRL = (0              <<  0) |  /* Disable Power-down       */
+                        (IDIVA_IDIV     <<  2) |  /* IDIV                     */
+                        (1              << 11) |  /* Autoblock En             */
+                        (IDIVA_CLK_SEL  << 24) ;  /* Clock source             */
+
+  LPC_CGU->IDIVB_CTRL = (0              <<  0) |  /* Disable Power-down       */
+                        (IDIVB_IDIV     <<  2) |  /* IDIV                     */
+                        (1              << 11) |  /* Autoblock En             */
+                        (IDIVB_CLK_SEL  << 24) ;  /* Clock source             */
+
+  LPC_CGU->IDIVC_CTRL = (0              <<  0) |  /* Disable Power-down       */
+                        (IDIVC_IDIV     <<  2) |  /* IDIV                     */
+                        (1              << 11) |  /* Autoblock En             */
+                        (IDIVC_CLK_SEL  << 24) ;  /* Clock source             */
+
+  LPC_CGU->IDIVD_CTRL = (0              <<  0) |  /* Disable Power-down       */
+                        (IDIVD_IDIV     <<  2) |  /* IDIV                     */
+                        (1              << 11) |  /* Autoblock En             */
+                        (IDIVD_CLK_SEL  << 24) ;  /* Clock source             */
+
+  LPC_CGU->IDIVE_CTRL = (0              <<  0) |  /* Disable Power-down       */
+                        (IDIVE_IDIV     <<  2) |  /* IDIV                     */
+                        (1              << 11) |  /* Autoblock En             */
+                        (IDIVE_CLK_SEL  << 24) ;  /* Clock source             */
+}
+
+
+/*----------------------------------------------------------------------------
+  Approximate delay function (must be used after SystemCoreClockUpdate() call)
+ *----------------------------------------------------------------------------*/
+#define CPU_NANOSEC(x) (((uint64_t)(x) * SystemCoreClock)/1000000000)
+
+static void WaitUs (uint32_t us) {
+  uint32_t cyc = us * CPU_NANOSEC(1000)/4;
+  while(cyc--);
+}
+
+
+/*----------------------------------------------------------------------------
+  External Memory Controller Definitions
+ *----------------------------------------------------------------------------*/
+#define SDRAM_ADDR_BASE 0x28000000      /* SDRAM base address                 */
+/* Write Mode register macro                                                  */
+#define WR_MODE(x) (*((volatile uint32_t *)(SDRAM_ADDR_BASE | (x))))
+
+/* Pin Settings: Glith filter DIS, Input buffer EN, Fast Slew Rate, No Pullup */
+#define EMC_PIN_SET ((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4))
+#define EMC_NANOSEC(ns, freq, div) (((uint64_t)(ns) * ((freq)/((div)+1)))/1000000000)
+
+#define EMC_CLK_DLY_TIM_2  (0x7777)     /* 3.5 ns delay for the EMC clock out */
+#define EMC_CLK_DLY_TIM_0  (0x0000)     /* No delay for the EMC clock out     */
+
+typedef void (*emcdivby2) (volatile uint32_t *creg6, volatile uint32_t *emcdiv, uint32_t cfg);
+
+const uint16_t emcdivby2_opc[] =  {
+  0x6803,        /*      LDR  R3,[R0,#0]      ; Load CREG6          */
+  0xF443,0x3380, /*      ORR  R3,R3,#0x10000  ; Set Divided by 2    */
+  0x6003,        /*      STR  R3,[R0,#0]      ; Store CREG6         */
+  0x600A,        /*      STR  R2,[R1,#0]      ; EMCDIV_CFG = cfg    */
+  0x684B,        /* loop LDR  R3,[R1,#4]      ; Load EMCDIV_STAT    */
+  0x07DB,        /*      LSLS R3,R3,#31       ; Check EMCDIV_STAT.0 */
+  0xD0FC,        /*      BEQ  loop            ; Jump if 0           */
+  0x4770,        /*      BX   LR              ; Exit                */
+  0,
+};
+
+#define        emcdivby2_szw ((sizeof(emcdivby2_opc)+3)/4)
+#define        emcdivby2_ram 0x10000000
+
+/*----------------------------------------------------------------------------
+  Initialize external memory controller
+ *----------------------------------------------------------------------------*/
+
+void SystemInit_ExtMemCtl (void) {
+  uint32_t emcdivby2_buf[emcdivby2_szw];
+  uint32_t div, n;
+
+  /* Select and enable EMC branch clock */
+  LPC_CCU1->CLK_M3_EMC_CFG = (1 << 2) | (1 << 1) | 1;
+  while (!(LPC_CCU1->CLK_M3_EMC_STAT & 1));
+
+  /* Set EMC clock output delay */
+  if (SystemCoreClock < 80000000UL) {
+    LPC_SCU->EMCDELAYCLK = EMC_CLK_DLY_TIM_0; /* No EMC clock out delay       */
+  }
+  else {
+    LPC_SCU->EMCDELAYCLK = EMC_CLK_DLY_TIM_2; /* 2.0 ns EMC clock out delay   */
+  }
+
+  /* Configure EMC port pins */
+  LPC_SCU->SFSP1_0  = EMC_PIN_SET | 2;  /* P1_0:  A5                          */
+  LPC_SCU->SFSP1_1  = EMC_PIN_SET | 2;  /* P1_1:  A6                          */
+  LPC_SCU->SFSP1_2  = EMC_PIN_SET | 2;  /* P1_2:  A7                          */
+  LPC_SCU->SFSP1_3  = EMC_PIN_SET | 3;  /* P1_3:  OE                          */
+  LPC_SCU->SFSP1_4  = EMC_PIN_SET | 3;  /* P1_4:  BLS0                        */
+  LPC_SCU->SFSP1_5  = EMC_PIN_SET | 3;  /* P1_5:  CS0                         */
+  LPC_SCU->SFSP1_6  = EMC_PIN_SET | 3;  /* P1_6:  WE                          */
+  LPC_SCU->SFSP1_7  = EMC_PIN_SET | 3;  /* P1_7:  D0                          */
+  LPC_SCU->SFSP1_8  = EMC_PIN_SET | 3;  /* P1_8:  D1                          */
+  LPC_SCU->SFSP1_9  = EMC_PIN_SET | 3;  /* P1_9:  D2                          */
+  LPC_SCU->SFSP1_10 = EMC_PIN_SET | 3;  /* P1_10: D3                          */
+  LPC_SCU->SFSP1_11 = EMC_PIN_SET | 3;  /* P1_11: D4                          */
+  LPC_SCU->SFSP1_12 = EMC_PIN_SET | 3;  /* P1_12: D5                          */
+  LPC_SCU->SFSP1_13 = EMC_PIN_SET | 3;  /* P1_13: D6                          */
+  LPC_SCU->SFSP1_14 = EMC_PIN_SET | 3;  /* P1_14: D7                          */
+
+  LPC_SCU->SFSP2_0  = EMC_PIN_SET | 2;  /* P2_0:  A13                         */
+  LPC_SCU->SFSP2_1  = EMC_PIN_SET | 2;  /* P2_1:  A12                         */
+  LPC_SCU->SFSP2_2  = EMC_PIN_SET | 2;  /* P2_2:  A11                         */
+  LPC_SCU->SFSP2_6  = EMC_PIN_SET | 2;  /* P2_6:  A10                         */
+  LPC_SCU->SFSP2_7  = EMC_PIN_SET | 3;  /* P2_7:  A9                          */
+  LPC_SCU->SFSP2_8  = EMC_PIN_SET | 3;  /* P2_8:  A8                          */
+  LPC_SCU->SFSP2_9  = EMC_PIN_SET | 3;  /* P2_9:  A0                          */
+  LPC_SCU->SFSP2_10 = EMC_PIN_SET | 3;  /* P2_10: A1                          */
+  LPC_SCU->SFSP2_11 = EMC_PIN_SET | 3;  /* P2_11: A2                          */
+  LPC_SCU->SFSP2_12 = EMC_PIN_SET | 3;  /* P2_12: A3                          */
+  LPC_SCU->SFSP2_13 = EMC_PIN_SET | 3;  /* P2_13: A4                          */
+
+  LPC_SCU->SFSP5_0  = EMC_PIN_SET | 2;  /* P5_0:  D12                         */
+  LPC_SCU->SFSP5_1  = EMC_PIN_SET | 2;  /* P5_1:  D13                         */
+  LPC_SCU->SFSP5_2  = EMC_PIN_SET | 2;  /* P5_2:  D14                         */
+  LPC_SCU->SFSP5_3  = EMC_PIN_SET | 2;  /* P5_3:  D15                         */
+  LPC_SCU->SFSP5_4  = EMC_PIN_SET | 2;  /* P5_4:  D8                          */
+  LPC_SCU->SFSP5_5  = EMC_PIN_SET | 2;  /* P5_5:  D9                          */
+  LPC_SCU->SFSP5_6  = EMC_PIN_SET | 2;  /* P5_6:  D10                         */
+  LPC_SCU->SFSP5_7  = EMC_PIN_SET | 2;  /* P5_7:  D11                         */
+
+  LPC_SCU->SFSP6_1  = EMC_PIN_SET | 1;  /* P6_1:  DYCS1                       */
+  LPC_SCU->SFSP6_2  = EMC_PIN_SET | 1;  /* P6_3:  CKEOUT1                     */
+  LPC_SCU->SFSP6_3  = EMC_PIN_SET | 3;  /* P6_3:  CS1                         */
+  LPC_SCU->SFSP6_4  = EMC_PIN_SET | 3;  /* P6_4:  CAS                         */
+  LPC_SCU->SFSP6_5  = EMC_PIN_SET | 3;  /* P6_5:  RAS                         */
+  LPC_SCU->SFSP6_6  = EMC_PIN_SET | 1;  /* P6_6:  BLS1                        */
+  LPC_SCU->SFSP6_7  = EMC_PIN_SET | 1;  /* P6_7:  A15                         */
+  LPC_SCU->SFSP6_8  = EMC_PIN_SET | 1;  /* P6_8:  A14                         */
+  LPC_SCU->SFSP6_9  = EMC_PIN_SET | 3;  /* P6_9:  DYCS0                       */
+  LPC_SCU->SFSP6_10 = EMC_PIN_SET | 3;  /* P6_10: DQMOUT1                     */
+  LPC_SCU->SFSP6_11 = EMC_PIN_SET | 3;  /* P6_11: CKEOUT0                     */
+  LPC_SCU->SFSP6_12 = EMC_PIN_SET | 3;  /* P6_12: DQMOUT0                     */
+
+  LPC_SCU->SFSPA_4  = EMC_PIN_SET | 3;  /* PA_4:  A23                         */
+
+  LPC_SCU->SFSPD_0  = EMC_PIN_SET | 2;  /* PD_0:  DQMOUT2                     */
+  LPC_SCU->SFSPD_1  = EMC_PIN_SET | 2;  /* PD_1:  CKEOUT2                     */
+  LPC_SCU->SFSPD_2  = EMC_PIN_SET | 2;  /* PD_2:  D16                         */
+  LPC_SCU->SFSPD_3  = EMC_PIN_SET | 2;  /* PD_3:  D17                         */
+  LPC_SCU->SFSPD_4  = EMC_PIN_SET | 2;  /* PD_4:  D18                         */
+  LPC_SCU->SFSPD_5  = EMC_PIN_SET | 2;  /* PD_5:  D19                         */
+  LPC_SCU->SFSPD_6  = EMC_PIN_SET | 2;  /* PD_6:  D20                         */
+  LPC_SCU->SFSPD_7  = EMC_PIN_SET | 2;  /* PD_7:  D21                         */
+  LPC_SCU->SFSPD_8  = EMC_PIN_SET | 2;  /* PD_8:  D22                         */
+  LPC_SCU->SFSPD_9  = EMC_PIN_SET | 2;  /* PD_9:  D23                         */
+  LPC_SCU->SFSPD_10 = EMC_PIN_SET | 2;  /* PD_10: BLS3                        */
+  LPC_SCU->SFSPD_11 = EMC_PIN_SET | 2;  /* PD_11: CS3                         */
+  LPC_SCU->SFSPD_12 = EMC_PIN_SET | 2;  /* PD_12: CS2                         */
+  LPC_SCU->SFSPD_13 = EMC_PIN_SET | 2;  /* PD_13: BLS2                        */
+  LPC_SCU->SFSPD_14 = EMC_PIN_SET | 2;  /* PD_14: DYCS2                       */
+  LPC_SCU->SFSPD_15 = EMC_PIN_SET | 2;  /* PD_15: A17                         */
+  LPC_SCU->SFSPD_16 = EMC_PIN_SET | 2;  /* PD_16: A16                         */
+
+  LPC_SCU->SFSPE_0  = EMC_PIN_SET | 3;  /* PE_0:  A18                         */
+  LPC_SCU->SFSPE_1  = EMC_PIN_SET | 3;  /* PE_1:  A19                         */
+  LPC_SCU->SFSPE_2  = EMC_PIN_SET | 3;  /* PE_2:  A20                         */
+  LPC_SCU->SFSPE_3  = EMC_PIN_SET | 3;  /* PE_3:  A21                         */
+  LPC_SCU->SFSPE_4  = EMC_PIN_SET | 3;  /* PE_4:  A22                         */
+  LPC_SCU->SFSPE_5  = EMC_PIN_SET | 3;  /* PE_5:  D24                         */
+  LPC_SCU->SFSPE_6  = EMC_PIN_SET | 3;  /* PE_6:  D25                         */
+  LPC_SCU->SFSPE_7  = EMC_PIN_SET | 3;  /* PE_7:  D26                         */
+  LPC_SCU->SFSPE_8  = EMC_PIN_SET | 3;  /* PE_8:  D27                         */
+  LPC_SCU->SFSPE_9  = EMC_PIN_SET | 3;  /* PE_9:  D28                         */
+  LPC_SCU->SFSPE_10 = EMC_PIN_SET | 3;  /* PE_10: D29                         */
+  LPC_SCU->SFSPE_11 = EMC_PIN_SET | 3;  /* PE_11: D30                         */
+  LPC_SCU->SFSPE_12 = EMC_PIN_SET | 3;  /* PE_12: D31                         */
+  LPC_SCU->SFSPE_13 = EMC_PIN_SET | 3;  /* PE_13: DQMOUT3                     */
+  LPC_SCU->SFSPE_14 = EMC_PIN_SET | 3;  /* PE_14: DYCS3                       */
+  LPC_SCU->SFSPE_15 = EMC_PIN_SET | 3;  /* PE_15: CKEOUT3                     */
+
+  LPC_EMC->CONTROL  = 0x00000001;       /* EMC Enable                         */
+  LPC_EMC->CONFIG   = 0x00000000;       /* Little-endian, Clock Ratio 1:1     */
+
+  div = 0;
+  if (SystemCoreClock > 120000000UL) {
+    /* Use EMC clock divider and EMC clock output delay */
+    div = 1;
+    /* Following code must be executed in RAM to ensure stable operation      */
+    /* LPC_CCU1->CLK_M3_EMCDIV_CFG = (1 << 5) | (1 << 2) | (1 << 1) | 1;      */
+    /* LPC_CREG->CREG6 |= (1 << 16);       // EMC_CLK_DIV divided by 2        */
+    /* while (!(LPC_CCU1->CLK_M3_EMCDIV_STAT & 1));                           */
+
+    /* This code configures EMC clock divider and is executed in RAM          */
+    for (n = 0; n < emcdivby2_szw; n++) {
+      emcdivby2_buf[n] =  *((uint32_t *)emcdivby2_ram + n);
+      *((uint32_t *)emcdivby2_ram + n) = *((uint32_t *)emcdivby2_opc + n);
+    }
+    __ISB();
+    ((emcdivby2 )(emcdivby2_ram+1))(&LPC_CREG->CREG6, &LPC_CCU1->CLK_M3_EMCDIV_CFG, (1 << 5) | (1 << 2) | (1 << 1) | 1);
+    for (n = 0; n < emcdivby2_szw; n++) {
+      *((uint32_t *)emcdivby2_ram + n) = emcdivby2_buf[n];
+    }
+  }
+
+  /* Configure EMC clock-out pins                                             */
+  LPC_SCU->SFSCLK_0 = EMC_PIN_SET | 0;  /* CLK0                               */
+  LPC_SCU->SFSCLK_1 = EMC_PIN_SET | 0;  /* CLK1                               */
+  LPC_SCU->SFSCLK_2 = EMC_PIN_SET | 0;  /* CLK2                               */
+  LPC_SCU->SFSCLK_3 = EMC_PIN_SET | 0;  /* CLK3                               */
+
+  /* Static memory configuration (chip select 0)                              */
+#if (USE_EXT_STAT_MEM_CS0)
+  LPC_EMC->STATICCONFIG0  = (1 <<  7) | /* Byte lane state: use WE signal     */
+                            (2 <<  0) | /* Memory width 32-bit                */
+                            (1 <<  3);  /* Async page mode enable             */
+
+  LPC_EMC->STATICWAITOEN0 = (0 <<  0) ; /* Wait output enable: No delay       */
+
+  LPC_EMC->STATICWAITPAG0 = 2;
+
+  /* Set Static Memory Read Delay for 90ns External NOR Flash                 */
+  LPC_EMC->STATICWAITRD0  = 1 + EMC_NANOSEC(90, SystemCoreClock, div);
+  LPC_EMC->STATICCONFIG0 |= (1 << 19) ; /* Enable buffer                      */
+#endif
+
+  /* Dynamic memory configuration (chip select 0)                             */
+#if (USE_EXT_DYN_MEM_CS0)
+
+  /* Set Address mapping: 128Mb(4Mx32), 4 banks, row len = 12, column len = 8 */
+  LPC_EMC->DYNAMICCONFIG0    = (1 << 14) |  /* AM[14]   = 1                   */
+                               (0 << 12) |  /* AM[12]   = 0                   */
+                               (2 <<  9) |  /* AM[11:9] = 2                   */
+                               (2 <<  7) ;  /* AM[8:7]  = 2                   */
+
+  LPC_EMC->DYNAMICRASCAS0    = 0x00000303;  /* Latency: RAS 3, CAS 3 CCLK cyc.*/
+  LPC_EMC->DYNAMICREADCONFIG = 0x00000001;  /* Command delayed by 1/2 CCLK    */
+
+  LPC_EMC->DYNAMICRP         = EMC_NANOSEC (20, SystemCoreClock, div);
+  LPC_EMC->DYNAMICRAS        = EMC_NANOSEC (42, SystemCoreClock, div);
+  LPC_EMC->DYNAMICSREX       = EMC_NANOSEC (63, SystemCoreClock, div);
+  LPC_EMC->DYNAMICAPR        = EMC_NANOSEC (70, SystemCoreClock, div);
+  LPC_EMC->DYNAMICDAL        = EMC_NANOSEC (70, SystemCoreClock, div);
+  LPC_EMC->DYNAMICWR         = EMC_NANOSEC (30, SystemCoreClock, div);
+  LPC_EMC->DYNAMICRC         = EMC_NANOSEC (63, SystemCoreClock, div);
+  LPC_EMC->DYNAMICRFC        = EMC_NANOSEC (63, SystemCoreClock, div);
+  LPC_EMC->DYNAMICXSR        = EMC_NANOSEC (63, SystemCoreClock, div);
+  LPC_EMC->DYNAMICRRD        = EMC_NANOSEC (14, SystemCoreClock, div);
+  LPC_EMC->DYNAMICMRD        = EMC_NANOSEC (30, SystemCoreClock, div);
+
+  WaitUs (100);
+  LPC_EMC->DYNAMICCONTROL    = 0x00000183;  /* Issue NOP command              */
+  WaitUs (10);
+  LPC_EMC->DYNAMICCONTROL    = 0x00000103;  /* Issue PALL command             */
+  WaitUs (1);
+  LPC_EMC->DYNAMICCONTROL    = 0x00000183;  /* Issue NOP command              */
+  WaitUs (1);
+  LPC_EMC->DYNAMICREFRESH    = EMC_NANOSEC(  200, SystemCoreClock, div) / 16 + 1;
+  WaitUs (10);
+  LPC_EMC->DYNAMICREFRESH    = EMC_NANOSEC(15625, SystemCoreClock, div) / 16 + 1;
+  WaitUs (10);
+  LPC_EMC->DYNAMICCONTROL    = 0x00000083;  /* Issue MODE command             */
+
+  /* Mode register: Burst Length: 4, Burst Type: Sequential, CAS Latency: 3   */
+  WR_MODE(((3 << 4) | 2) << 12);
+
+  WaitUs (10);
+  LPC_EMC->DYNAMICCONTROL    = 0x00000002;  /* Issue NORMAL command           */
+  LPC_EMC->DYNAMICCONFIG0   |= (1 << 19);   /* Enable buffer                  */
+#endif
+}
+
+
+/*----------------------------------------------------------------------------
+  Measure frequency using frequency monitor
+ *----------------------------------------------------------------------------*/
+uint32_t MeasureFreq (uint32_t clk_sel) {
+  uint32_t fcnt, rcnt, fout;
+
+  /* Set register values */
+  LPC_CGU->FREQ_MON &= ~(1 << 23);                /* Stop frequency counters  */
+  LPC_CGU->FREQ_MON  = (clk_sel << 24) | 511;     /* RCNT == 511              */
+  LPC_CGU->FREQ_MON |= (1 << 23);                 /* Start RCNT and FCNT      */
+  while (LPC_CGU->FREQ_MON & (1 << 23)) {
+    fcnt = (LPC_CGU->FREQ_MON >> 9) & 0x3FFF;
+    rcnt = (LPC_CGU->FREQ_MON     ) & 0x01FF;
+    if (fcnt == 0 && rcnt == 0) {
+      return (0);                                 /* No input clock present   */
+    }
+  }
+  fcnt = (LPC_CGU->FREQ_MON >> 9) & 0x3FFF;
+  fout = fcnt * (12000000U/511U);                 /* FCNT * (IRC_CLK / RCNT)  */
+
+  return (fout);
+}
+
+
+/*----------------------------------------------------------------------------
+  Get PLL1 (divider and multiplier) parameters
+ *----------------------------------------------------------------------------*/
+static __inline uint32_t GetPLL1Param (void) {
+  uint32_t ctrl;
+  uint32_t p;
+  uint32_t div, mul;
+
+  ctrl = LPC_CGU->PLL1_CTRL;
+  div = ((ctrl >> 12) & 0x03) + 1;
+  mul = ((ctrl >> 16) & 0xFF) + 1;
+  p = 1 << ((ctrl >>  8) & 0x03);
+
+  if (ctrl & (1 << 1)) {
+    /* Bypass = 1, PLL1 input clock sent to post-dividers */
+    if (ctrl & (1 << 7)) {
+      div *= (2*p);
+    }
+  }
+  else {
+    /* Direct and integer mode */
+    if (((ctrl & (1 << 7)) == 0) && ((ctrl & (1 << 6)) == 0)) {
+      /* Non-integer mode */
+      div *= (2*p);
+    }
+  }
+  return ((div << 8) | (mul));
+}
+
+
+/*----------------------------------------------------------------------------
+  Get input clock source for specified clock generation block
+ *----------------------------------------------------------------------------*/
+int32_t GetClkSel (uint32_t clk_src) {
+  uint32_t reg;
+  int32_t clk_sel = -1;
+
+  switch (clk_src) {
+    case CLK_SRC_IRC:
+    case CLK_SRC_ENET_RX:
+    case CLK_SRC_ENET_TX:
+    case CLK_SRC_GP_CLKIN:
+      return (clk_src);
+
+    case CLK_SRC_32KHZ:
+      return ((LPC_CREG->CREG0 & 0x0A) != 0x02) ? (-1) : (CLK_SRC_32KHZ);
+    case CLK_SRC_XTAL:
+     return  (LPC_CGU->XTAL_OSC_CTRL & 1)       ? (-1) : (CLK_SRC_XTAL);
+
+    case CLK_SRC_PLL0U: reg = LPC_CGU->PLL0USB_CTRL;    break;
+    case CLK_SRC_PLL0A: reg = LPC_CGU->PLL0AUDIO_CTRL;  break;
+    case CLK_SRC_PLL1:  reg = (LPC_CGU->PLL1_STAT & 1) ? (LPC_CGU->PLL1_CTRL) : (0); break;
+
+    case CLK_SRC_IDIVA: reg = LPC_CGU->IDIVA_CTRL;      break;
+    case CLK_SRC_IDIVB: reg = LPC_CGU->IDIVB_CTRL;      break;
+    case CLK_SRC_IDIVC: reg = LPC_CGU->IDIVC_CTRL;      break;
+    case CLK_SRC_IDIVD: reg = LPC_CGU->IDIVD_CTRL;      break;
+    case CLK_SRC_IDIVE: reg = LPC_CGU->IDIVE_CTRL;      break;
+
+    default:
+      return (clk_sel);
+  }
+  if (!(reg & 1)) {
+    clk_sel = (reg >> 24) & 0x1F;
+  }
+  return (clk_sel);
+}
+
+
+/*----------------------------------------------------------------------------
+  Get clock frequency for specified clock source
+ *----------------------------------------------------------------------------*/
+uint32_t GetClockFreq (uint32_t clk_src) {
+  uint32_t tmp;
+  uint32_t mul        =  1;
+  uint32_t div        =  1;
+  uint32_t main_freq  =  0;
+  int32_t  clk_sel    = clk_src;
+
+  do {
+    switch (clk_sel) {
+      case CLK_SRC_32KHZ:    main_freq = CLK_32KHZ;     break;
+      case CLK_SRC_IRC:      main_freq = CLK_IRC;       break;
+      case CLK_SRC_ENET_RX:  main_freq = CLK_ENET_RX;   break;
+      case CLK_SRC_ENET_TX:  main_freq = CLK_ENET_TX;   break;
+      case CLK_SRC_GP_CLKIN: main_freq = CLK_GP_CLKIN;  break;
+      case CLK_SRC_XTAL:     main_freq = CLK_XTAL;      break;
+
+      case CLK_SRC_IDIVA: div *= ((LPC_CGU->IDIVA_CTRL >> 2) & 0x3) + 1; break;
+      case CLK_SRC_IDIVB: div *= ((LPC_CGU->IDIVB_CTRL >> 2) & 0x3) + 1; break;
+      case CLK_SRC_IDIVC: div *= ((LPC_CGU->IDIVC_CTRL >> 2) & 0x3) + 1; break;
+      case CLK_SRC_IDIVD: div *= ((LPC_CGU->IDIVD_CTRL >> 2) & 0x3) + 1; break;
+      case CLK_SRC_IDIVE: div *= ((LPC_CGU->IDIVE_CTRL >> 2) & 0x3) + 1; break;
+
+      case CLK_SRC_PLL0U: /* Not implemented */  break;
+      case CLK_SRC_PLL0A: /* Not implemented */  break;
+
+      case CLK_SRC_PLL1:
+        tmp = GetPLL1Param ();
+        mul *= (tmp     ) & 0xFF;       /* PLL input clock multiplier         */
+        div *= (tmp >> 8) & 0xFF;       /* PLL input clock divider            */
+        break;
+
+      default:
+        return (0);                     /* Clock not running or not supported */
+    }
+    if (main_freq == 0) {
+      clk_sel = GetClkSel (clk_sel);
+    }
+  }
+  while (main_freq == 0);
+
+  return ((main_freq * mul) / div);
+}
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock update
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void) {
+  /* Check BASE_M3_CLK connection */
+  uint32_t base_src = (LPC_CGU->BASE_M3_CLK >> 24) & 0x1F;
+
+  /* Update core clock frequency */
+  SystemCoreClock = GetClockFreq (base_src);
+}
+
+
+extern uint32_t __Vectors;                         /* see startup_LPC18xx.s   */
+
+/*----------------------------------------------------------------------------
+  Initialize the system
+ *----------------------------------------------------------------------------*/
+void SystemInit (void) {
+  /* Disable SysTick timer                                                    */
+  SysTick->CTRL &= ~(SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk);
+
+  /* Set vector table pointer */
+  SCB->VTOR = ((uint32_t)(&__Vectors)) & 0xFFF00000UL;
+
+  /* Configure PLL0 and PLL1, connect CPU clock to selected clock source */
+  SetClock();
+
+  /* Update SystemCoreClock variable */
+  SystemCoreClockUpdate();
+
+  /* Configure External Memory Controller */
+  SystemInit_ExtMemCtl ();
+}

CMSIS/Pack/Example/Boards/Keil/MCB1800/Blinky_ULp/RTE/RTE_Components.h

@@ -0,0 +1,15 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'Blinky' 
+ * Target:  'SWO Trace' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+#define RTE_DEVICE_STARTUP_LPC18XX      /* Device Startup for NXP18XX */
+
+#endif /* RTE_COMPONENTS_H */

CMSIS/Pack/Example/Boards/Keil/MCB1800/Common/ADC_MCB1800.c

@@ -0,0 +1,142 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Name:    ADC_MCB1800.c
+ * Purpose: A/D Converter interface for MCB1800 evaluation board
+ * Rev.:    1.00
+ *
+ *----------------------------------------------------------------------------*/
+
+#include "LPC18xx.h"
+#include "SCU_LPC18xx.h"
+#include "Board_ADC.h"
+
+#define ADC_RESOLUTION        10        /* Number of A/D converter bits       */
+
+/* Clock Control Unit register bits */
+#define CCU_CLK_CFG_RUN      (1 << 0)
+#define CCU_CLK_CFG_AUTO     (1 << 1)
+#define CCU_CLK_STAT_RUN     (1 << 0)
+
+static volatile uint16_t AD_last;       /* Last converted value               */
+static volatile uint8_t  AD_done;       /* AD conversion done flag            */
+
+
+/**
+  \fn          int32_t ADC_Initialize (void)
+  \brief       Initialize Analog-to-Digital Converter
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t ADC_Initialize (void) {
+
+  /* Enable ADC0 clock */
+  LPC_CCU1->CLK_APB3_ADC0_CFG = CCU_CLK_CFG_AUTO | CCU_CLK_CFG_RUN;
+  while (!(LPC_CCU1->CLK_APB3_ADC0_STAT & CCU_CLK_STAT_RUN));
+
+  /* Configure ADC0_1 */
+  LPC_ADC0->CR = (1 <<  1) |            /* Select ADC0_1 pin for conversion   */
+                 (2 <<  8) |            /* 12MHz / (2+1) = 4MHz               */
+                 (1 << 21) ;            /* ADC is operational                 */
+
+  /* Enable ADC0 Channel 1 interrupt */
+  LPC_ADC0->INTEN |=  (1 << 1);
+  NVIC_EnableIRQ (ADC0_IRQn);
+
+  return 0;
+}
+
+/**
+  \fn          int32_t ADC_Uninitialize (void)
+  \brief       De-initialize Analog-to-Digital Converter
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t ADC_Uninitialize (void) {
+
+  /* Disable ADC0 Channel 1 interrupt */
+  NVIC_DisableIRQ (ADC0_IRQn);
+  LPC_ADC0->INTEN &= ~(1 << 1);
+
+  /* Disable ADC0 clock */
+  LPC_CCU1->CLK_APB3_ADC0_CFG = 0;
+
+  return 0;
+}
+
+/**
+  \fn          int32_t ADC_StartConversion (void)
+  \brief       Start conversion
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t ADC_StartConversion (void) {
+
+  LPC_ADC0->CR |= (1 << 24);            /* Start conversion                   */
+
+  return 0;
+}
+
+/**
+  \fn          int32_t ADC_ConversionDone (void)
+  \brief       Check if conversion finished
+  \returns
+   - \b  0: conversion finished
+   - \b -1: conversion in progress
+*/
+int32_t ADC_ConversionDone (void) {
+  return (AD_done ? 0 : -1);
+}
+
+/**
+  \fn          int32_t ADC_GetValue (void)
+  \brief       Get converted value
+  \returns
+   - <b> >=0</b>: converted value
+   - \b -1: conversion in progress or failed
+*/
+int32_t ADC_GetValue (void) {
+
+  if (AD_done) {
+    AD_done = 0;
+    return AD_last;
+  }
+  return -1;
+}
+
+/**
+  \fn          uint32_t ADC_GetResolution (void)
+  \brief       Get resolution of Analog-to-Digital Converter
+  \returns     Resolution (in bits)
+*/
+uint32_t ADC_GetResolution (void) {
+  return ADC_RESOLUTION;
+}
+
+/**
+  \fn          void ADC0_IRQHandler (void)
+  \brief       Analog-to-Digital Converter Interrupt Handler
+*/
+void ADC0_IRQHandler (void) {
+
+  LPC_ADC0->GDR;                            /* Clear IRQ request flag         */
+  AD_last = (LPC_ADC0->DR[1] >> 6) & 0x3FF; /* Read value and clear IRQ       */
+  AD_done = 1;
+}

CMSIS/Pack/Example/Boards/Keil/MCB1800/Common/Audio_UDA1380.c

@@ -0,0 +1,885 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Name:    Audio_USA1380.c
+ * Purpose: Audio codec UDA1380 interface
+ * Rev.:    1.01
+ *
+ *----------------------------------------------------------------------------*/
+
+ #include "Driver_I2C.h"
+#include "Driver_SAI.h"
+#include "Board_Audio.h"
+
+#include "SCU_LPC18xx.h"
+#include "GPIO_LPC18xx.h"
+
+// Auto gain control
+#ifndef AUDIO_VOLUME_AUTO_GAIN
+#define AUDIO_VOLUME_AUTO_GAIN    0x80
+#endif
+
+// UDA1380 input selection
+#ifndef UDA1380_INPUT_LINE_IN
+#define UDA1380_INPUT_MIC         1
+#endif
+
+// PGA gain (from 0 to 24 dB in steps of 3dB)
+#ifndef UDA1380_PGA_GAIN
+#define UDA1380_PGA_GAIN          6
+#endif
+
+// VGA gain (from 0 to 30 dB in steps of 2dB)
+#ifndef UDA1380_VGA_GAIN
+#define UDA1380_VGA_GAIN          0
+#endif
+
+// AGC time constant settings (see AGC register in UDA1380 datasheet)
+#ifndef UDA1380_AGC_TIME
+#define UDA1380_AGC_TIME          0
+#endif
+
+
+// UDA1380 Reset GPIO Definitions
+const GPIO_ID UDA1380_RESET_GPIO = { 4, 0 };
+
+// UDA1380 Reset pin definitions
+const PIN_ID UDA1380_RESET_PIN   = { 8, 0, (SCU_PIN_CFG_PULLUP_DIS | SCU_PIN_CFG_MODE(0))};
+
+
+#ifndef UDA1380_I2C_PORT
+#define UDA1380_I2C_PORT          0         // I2C Port number
+#endif
+
+#define UDA1380_I2C_ADDR          0x1A      // UDA1380 I2C address
+
+// I2C Driver
+#define _I2C_Driver_(n)  Driver_I2C##n
+#define  I2C_Driver_(n) _I2C_Driver_(n)
+extern ARM_DRIVER_I2C    I2C_Driver_(UDA1380_I2C_PORT);
+#define ptrI2C         (&I2C_Driver_(UDA1380_I2C_PORT))
+
+#ifndef UDA1380_SAI_PORT
+#define UDA1380_SAI_PORT          0         // SAI Port number
+#endif
+
+// SAI Driver
+#define _SAI_Driver_(n)  Driver_SAI##n
+#define  SAI_Driver_(n) _SAI_Driver_(n)
+extern ARM_DRIVER_SAI    SAI_Driver_(UDA1380_SAI_PORT);
+#define ptrSAI         (&SAI_Driver_(UDA1380_SAI_PORT))
+
+// UDA1380 Register addresses
+#define REG_CLOCK_SETTINGS        0x00U
+#define REG_I2S_BUS_SETTINGS      0x01U
+#define REG_POWER_CONTROL         0x02U
+#define REG_ANALOG_MIXER          0x03U
+#define REG_HEADPHONE_AMPLIFIER   0x04U
+#define REG_MASTER_VOLUME         0x10U
+#define REG_MIXER_VOLUME          0x11U
+#define REG_MODE_SEL_BASS_TREBLE  0x12U
+#define REG_MASTER_MUTE           0x13U
+#define REG_MIXER                 0x14U
+#define REG_DECIMATOR_VOLUME      0x20U
+#define REG_PGA_SETTINGS          0x21U
+#define REG_ADC_SETTINGS          0x22U
+#define REG_AGC_SETTINGS          0x23U
+
+Audio_SignalEvent_t Callback_event;
+
+typedef struct _STREAM_FLAGS {
+  uint8_t running  :1U;
+  uint8_t paused   :1U;
+  uint8_t mono     :1U;
+  uint8_t agc      :1U;
+} flags;
+
+typedef struct _STREAM {
+  uint32_t data_size;
+  void    *data_buf;
+  flags    flag;
+  uint8_t  data_bits;
+  uint32_t freq;
+  uint8_t  vol_lch;
+  uint8_t  vol_rch;
+} STREAM;
+
+// Local variables
+static uint8_t  DeviceAddr;
+static uint8_t  SignalSendComplete;
+static uint8_t  SignalTxUnderflow;
+static STREAM   Stream[2U];
+
+#define STREAM_OUT ( 0U )
+#define STREAM_IN  ( 1U )
+#define STREAM_IDX(stream) ((stream & 0x80U) == 0U ? STREAM_OUT : STREAM_IN)
+
+// Callback
+/**
+  \fn          void (uint8_t reg, uint16_t reg_val)
+  \brief       UDA1380 callback function
+  \param[in]   event
+*/
+void UDA1380_cb (uint32_t event) {
+
+  if (event & ARM_SAI_EVENT_FRAME_ERROR) {
+    // Audio interface does not support FRAME ERRORS
+    event &= ~ARM_SAI_EVENT_FRAME_ERROR;
+  }
+
+  if (event & ARM_SAI_EVENT_TX_UNDERFLOW) {
+    if ((Stream[STREAM_OUT].flag.running == 0U) ||
+        (Stream[STREAM_OUT].flag.paused  == 1U)) {
+        SignalTxUnderflow = 1;
+        // TX running only because of codec clock
+        event &= ~ARM_SAI_EVENT_TX_UNDERFLOW;
+      }
+  }
+
+  if (event & ARM_SAI_EVENT_SEND_COMPLETE) {
+    if (Stream[STREAM_OUT].flag.paused == 1U) {
+        SignalSendComplete = 1;
+        // TX running only because of codec clock
+        event &= ~ARM_SAI_EVENT_SEND_COMPLETE;
+      }
+  }
+
+  if ((Callback_event != NULL) && (event != 0U)) {
+    Callback_event (event);
+  }
+}
+
+// Local functions
+/**
+  \fn          int32_t UDA1380_RegRead (uint8_t reg, uint16_t * reg_val)
+  \brief       Read value from UDA1380 register
+  \param[in]   reg      UDA1380 register address
+  \param[Out]  reg_val  Pointer to value read from UDA1380 register
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+static int32_t UDA1380_RegRead (uint8_t reg, uint16_t *reg_val) {
+  uint8_t  val[2];
+
+  if (ptrI2C->MasterTransmit (DeviceAddr, &reg, 1U, false) != ARM_DRIVER_OK) {
+    return -1;
+  }
+  while (ptrI2C->GetStatus().busy);
+
+  if (ptrI2C->MasterReceive  (DeviceAddr, val, 2U, false) != ARM_DRIVER_OK) {
+    return -1;
+  }
+  while (ptrI2C->GetStatus().busy);
+
+  *reg_val  = val[0] << 8;
+  *reg_val |= val[1];
+
+  return 0;
+}
+
+/**
+  \fn          int32_t UDA1380_RegWrite (uint8_t reg, uint16_t reg_val)
+  \brief       Write value to UDA1380 register
+  \param[in]   reg      UDA1380 register address
+  \param[in]   reg_val  Value to be written to UDA1380 register
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+static int32_t UDA1380_RegWrite (uint8_t reg, uint16_t reg_val) {
+  uint8_t   val[3];
+  uint16_t  rd_val;
+
+  val[0] =  reg;
+  val[1] = (reg_val >> 8) & 0xFFU;
+  val[2] =  reg_val & 0xFFU;
+
+  if (ptrI2C->MasterTransmit (DeviceAddr, val, 3U, false) != ARM_DRIVER_OK) {
+    return -1;
+  }
+  while (ptrI2C->GetStatus().busy);
+
+  UDA1380_RegRead (reg, &rd_val);
+  while (ptrI2C->GetStatus().busy);
+
+  if (reg_val != rd_val) {
+    return -1;
+  }
+
+  return 0;
+}
+
+/**
+  \fn          int32_t SAI_Configure (uint8_t stream)
+  \brief       Configure SAI for selected stream
+  \param[in]   stream
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+static int32_t SAI_Configure (uint8_t stream) {
+  uint32_t cfg, freq_set;
+  STREAM *ptrStream;
+
+  ptrStream = &Stream[STREAM_IDX(stream)];
+
+  cfg = ARM_SAI_MODE_MASTER                      |
+        ARM_SAI_PROTOCOL_I2S                     |
+        ARM_SAI_DATA_SIZE(ptrStream->data_bits)  |
+        ARM_SAI_COMPANDING_NONE                  |
+        ARM_SAI_MSB_FIRST                        |
+        ARM_SAI_MCLK_PIN_INACTIVE;
+
+  if (ptrStream->flag.mono == 1U) {
+    cfg |= ARM_SAI_MONO_MODE;
+  }
+
+  freq_set = ARM_SAI_MCLK_PRESCALER(256U);
+
+  switch (stream) {
+    case AUDIO_STREAM_OUT:
+      cfg |= ARM_SAI_CONFIGURE_TX |
+             ARM_SAI_ASYNCHRONOUS;
+      freq_set |= (ptrStream->freq & ARM_SAI_AUDIO_FREQ_Msk);
+      break;
+    case AUDIO_STREAM_IN:
+      cfg |= ARM_SAI_CONFIGURE_RX |
+             ARM_SAI_ASYNCHRONOUS;
+      freq_set |= (ptrStream->freq & ARM_SAI_AUDIO_FREQ_Msk);
+      break;
+    default: return (-1);
+  }
+
+  if (ptrSAI->Control (cfg, ARM_SAI_FRAME_LENGTH(ptrStream->data_bits * 2U), freq_set) != ARM_DRIVER_OK) {
+    return -1;
+  }
+
+  return 0;
+}
+
+
+// Driver functions
+
+/**
+  \fn          int32_t Audio_Initialize (Audio_SignalEvent_t cb_event)
+  \brief       Initialize Audio Interface
+  \param[in]   cb_event  pointer to event notification function
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t Audio_Initialize (Audio_SignalEvent_t cb_event) {
+  uint16_t reg_val, val;
+
+  Callback_event = cb_event;
+
+  // Clear Stream flags
+  Stream[STREAM_IN].flag.running  = 0U;
+  Stream[STREAM_IN].flag.paused   = 0U;
+  Stream[STREAM_IN].flag.mono     = 0U;
+  Stream[STREAM_IN].flag.agc      = 0U;
+  Stream[STREAM_OUT].flag.running = 0U;
+  Stream[STREAM_OUT].flag.paused  = 0U;
+  Stream[STREAM_OUT].flag.mono    = 0U;
+  Stream[STREAM_OUT].data_size    = 0U;
+  Stream[STREAM_OUT].data_buf     = NULL;
+
+  // Set Default values
+  Stream[STREAM_IN].data_bits     = 8U;
+  Stream[STREAM_IN].freq          = 8000U;
+  Stream[STREAM_OUT].data_bits    = 8U;
+  Stream[STREAM_OUT].freq         = 8000U;
+
+  SignalSendComplete = 0U;
+  SignalTxUnderflow  = 0U;
+
+  // Reset pin configuration
+  SCU_PinConfigure(UDA1380_RESET_PIN.port,
+                   UDA1380_RESET_PIN.num,
+                   UDA1380_RESET_PIN.config_val);
+
+  GPIO_PortClock(1);
+  GPIO_PinWrite(UDA1380_RESET_GPIO.port, UDA1380_RESET_GPIO.num, 0U);
+  GPIO_SetDir(UDA1380_RESET_GPIO.port, UDA1380_RESET_GPIO.num, GPIO_DIR_OUTPUT);
+
+  // I2C Initialization and configuration
+  ptrI2C->Initialize   (NULL);
+  ptrI2C->PowerControl (ARM_POWER_FULL);
+  ptrI2C->Control      (ARM_I2C_BUS_SPEED, ARM_I2C_BUS_SPEED_FAST);
+  ptrI2C->Control      (ARM_I2C_BUS_CLEAR, 0U);
+
+  // SAI Initialization
+  ptrSAI->Initialize   (UDA1380_cb);
+  ptrSAI->PowerControl (ARM_POWER_FULL);
+
+  // Set default TX SAI configuration
+  SAI_Configure (AUDIO_STREAM_OUT);
+
+  // Reset codec procedure
+  // Start transmitter to run Codec clock
+  ptrSAI->Control      (ARM_SAI_CONTROL_TX, 1U, 0U);
+  //Wait
+  for (val = 0xFFFFU; val; val--) { __nop(); }
+  // reset
+  GPIO_PinWrite(UDA1380_RESET_GPIO.port, UDA1380_RESET_GPIO.num, 1U);
+  // Wait
+  for (val = 0xFFFFU; val; val--) { __nop(); }
+  GPIO_PinWrite(UDA1380_RESET_GPIO.port, UDA1380_RESET_GPIO.num, 0U);
+  // Wait
+  for (val = 0xFFFFU; val; val--) { __nop(); }
+
+  // Disable SAI receiver
+  ptrSAI->Control      (ARM_SAI_CONTROL_RX, 0, 0);
+
+  // Init UDA1380 device
+  DeviceAddr = UDA1380_I2C_ADDR;
+
+  // UDA1370 Power control settings
+  // Power on: WSPLL, headphone drive, DAC, BIAS, LNA, PGAL, ADCL, PGAR, ADCR;
+  reg_val = (1U << 15) | (1U << 13) | (1U << 10) | (1U << 8) |
+            (1U <<  4) | (1U <<  3) | (1U <<  2) | (1U << 1) | 1U;
+  if (UDA1380_RegWrite (REG_POWER_CONTROL, reg_val) == -1)    { return -1; }
+
+  // Enable clocks: ADC, DEC, DAC,INT
+  if (UDA1380_RegWrite (REG_CLOCK_SETTINGS,   0x0F30U) == -1) { return -1; }
+
+  // Mute Analog mixer
+  if (UDA1380_RegWrite (REG_ANALOG_MIXER,     0x3F3FU) == -1) { return -1; }
+
+  if (UDA1380_RegWrite (REG_MASTER_MUTE,           0U) == -1) { return -1; }
+
+  // Configure Audio input
+#ifdef UDA1380_INPUT_MIC
+  // Select Microphone as input and set VGA gain
+  val = 0x0DU |((UDA1380_VGA_GAIN / 2U) << 8);
+  if (UDA1380_RegWrite (REG_ADC_SETTINGS,         val) == -1) { return -1; }
+  // Set PGA Gain to 0dB
+  if (UDA1380_RegWrite (REG_PGA_SETTINGS,     0x0000U) == -1) { return -1; }
+#endif
+
+#ifdef UDA1380_INPUT_LINE_IN
+  // Select Line in as input and set VGA gain to 0
+  if (UDA1380_RegWrite (REG_ADC_SETTINGS,     0x0001U) == -1) { return -1; }
+
+  // Set PGA Gain
+  val = UDA1380_PGA_GAIN / 3;
+  val |= val << 8;
+  if (UDA1380_RegWrite (REG_PGA_SETTINGS,         val) == -1) { return -1; }
+#endif
+
+  if (UDA1380_RegWrite (REG_AGC_SETTINGS,           0) == -1) { return -1; }
+
+  return 0;
+}
+
+/**
+  \fn          int32_t Audio_Uninitialize (void)
+  \brief       De-initialize Audio Interface
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t Audio_Uninitialize (void) {
+
+  // Abort SAI Send and receive
+  ptrSAI->Control (ARM_SAI_ABORT_SEND,    0U, 0U);
+  ptrSAI->Control (ARM_SAI_ABORT_RECEIVE, 0U, 0u);
+
+  // Disable clocks: ADC, DEC, DAC,INT
+  if (UDA1380_RegWrite (REG_CLOCK_SETTINGS, 0U) == -1) { return -1; }
+
+  // UDA1370 Power Power Off
+  if (UDA1380_RegWrite (REG_POWER_CONTROL,  0U) == -1) { return -1; }
+
+  // Disable SAI transmitter and receiver
+  ptrSAI->Control (ARM_SAI_CONTROL_TX, 0U, 0U);
+  ptrSAI->Control (ARM_SAI_CONTROL_RX, 0U, 0U);
+
+  return 0;
+}
+
+/**
+  \fn          int32_t Audio_SendData (const void *data, uint32_t num)
+  \brief       Start sending data to Audio output stream
+  \param[in]   data  pointer to buffer with data to send
+  \param[in]   num   number of data items to send
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t Audio_SendData (const void *data, uint32_t num) {
+  if ((Stream[STREAM_OUT].flag.running == 0U) ||
+      (Stream[STREAM_OUT].flag.paused  == 1U)) {
+    // Save data info
+    Stream[STREAM_OUT].data_buf = (void *)data;
+    Stream[STREAM_OUT].data_size = num;
+  } else {
+    Stream[STREAM_OUT].data_buf = NULL;
+    Stream[STREAM_OUT].data_size = 0;
+    if (ptrSAI->Send (data, num) != ARM_DRIVER_OK) { return -1; }
+  }
+  return 0;
+}
+
+/**
+  \fn          int32_t Audio_ReceiveData (void *data, uint32_t num)
+  \brief       Start receiving data from Audio input stream
+  \param[out]  data  pointer to buffer for data to receive
+  \param[in]   num   number of data items to send
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t Audio_ReceiveData (void *data, uint32_t num) {
+  if (ptrSAI->Receive (data, num) != ARM_DRIVER_OK) { return -1; }
+  return 0;
+}
+
+/**
+  \fn          int32_t Audio_Start (uint8_t stream)
+  \brief       Start Audio stream
+  \param[in]   stream  stream identifier
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t Audio_Start (uint8_t stream) {
+  void * data;
+  uint32_t num, evt = 0;
+
+  switch (stream) {
+    case AUDIO_STREAM_OUT:
+      Stream[STREAM_OUT].flag.running = 1U;
+      if (Stream[STREAM_OUT].flag.paused == 0U) {
+        if (Stream[STREAM_OUT].data_size != 0U) {
+          SignalSendComplete = 0U;
+          SignalTxUnderflow  = 0U;
+          num  = Stream[STREAM_OUT].data_size;
+          data = Stream[STREAM_OUT].data_buf;
+          Stream[STREAM_OUT].data_size = 0U;
+          Stream[STREAM_OUT].data_buf  = NULL;;
+          if (ptrSAI->Send (data, num) != ARM_DRIVER_OK) { return -1; }
+        } else {
+          if (SignalSendComplete == 1U) { evt |= AUDIO_EVENT_SEND_COMPLETE; }
+          if (SignalTxUnderflow  == 1U) { evt |= AUDIO_EVENT_TX_UNDERFLOW ; }
+
+          SignalSendComplete = 0U;
+          SignalTxUnderflow  = 0U;
+          if ((Callback_event != NULL) && (evt != 0U)) { Callback_event (evt); }
+        }
+      }
+      break;
+    case AUDIO_STREAM_IN:
+      Stream[STREAM_IN].flag.running = 1U;
+      ptrSAI->Control (ARM_SAI_CONTROL_RX, 1U, 0U);
+      break;
+    default: return (-1);
+  }
+
+  return 0;
+}
+
+/**
+  \fn          int32_t Audio_Stop (uint8_t stream)
+  \brief       Stop Audio stream
+  \param[in]   stream  stream identifier
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t Audio_Stop (uint8_t stream) {
+ 
+  switch (stream) {
+    case AUDIO_STREAM_OUT:
+      Stream[STREAM_OUT].flag.running = 0U;
+      // Abort transfer
+      ptrSAI->Control (ARM_SAI_ABORT_SEND, 1U, 0U);
+      break;
+    case AUDIO_STREAM_IN:
+      Stream[STREAM_IN].flag.running = 0U;
+      ptrSAI->Control (ARM_SAI_CONTROL_RX, 0U, 0U);
+      // Abort transfer
+      ptrSAI->Control (ARM_SAI_ABORT_RECEIVE, 1U, 0U);
+      break;
+    default: return (-1);
+  }
+
+  return 0;
+}
+
+/**
+  \fn          int32_t Audio_Pause (uint8_t stream)
+  \brief       Pause Audio stream
+  \param[in]   stream  stream identifier
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t Audio_Pause (uint8_t stream) {
+
+  switch (stream) {
+    case AUDIO_STREAM_OUT:
+      if (Stream[STREAM_OUT].flag.running == 0U) { return 0; }
+      SignalSendComplete = 0U;
+      SignalTxUnderflow  = 0U;
+      Stream[STREAM_OUT].flag.paused  = 1U;
+      break;
+    case AUDIO_STREAM_IN:
+      if (Stream[STREAM_IN].flag.running == 0U) { return 0; }
+      Stream[STREAM_IN].flag.paused  = 1U;
+      ptrSAI->Control (ARM_SAI_CONTROL_RX, 0U, 0U);
+      break;
+    default: return (-1);
+  }
+
+  return 0;
+}
+
+/**
+  \fn          int32_t Audio_Resume (uint8_t stream)
+  \brief       Resume Audio stream
+  \param[in]   stream  stream identifier
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t Audio_Resume (uint8_t stream) {
+  uint32_t num, evt = 0;
+  void * data;
+
+  switch (stream) {
+    case AUDIO_STREAM_OUT:
+      if ((Stream[STREAM_OUT].flag.paused  == 1U) &&
+          (Stream[STREAM_OUT].flag.running == 1U)) {
+        Stream[STREAM_OUT].flag.paused      = 0U;
+        if (Stream[STREAM_OUT].data_size != 0) {
+          SignalSendComplete = 0U;
+          SignalTxUnderflow  = 0U;
+          num  = Stream[STREAM_OUT].data_size;
+          data = Stream[STREAM_OUT].data_buf;
+          Stream[STREAM_OUT].data_size = 0U;
+          Stream[STREAM_OUT].data_buf  = NULL;
+          if (ptrSAI->Send (data, num) != ARM_DRIVER_OK) { return -1; }
+        } else {
+          if (SignalSendComplete == 1U) { evt |= AUDIO_EVENT_SEND_COMPLETE; }
+          if (SignalTxUnderflow  == 1U) { evt |= AUDIO_EVENT_TX_UNDERFLOW ; }
+
+          SignalSendComplete = 0U;
+          SignalTxUnderflow  = 0U;
+
+          if ((Callback_event != NULL) && (evt != 0U)) { Callback_event (evt); }
+        }
+      }
+      break;
+    case AUDIO_STREAM_IN:
+      if (Stream[STREAM_IN].flag.paused != 0U) {
+        Stream[STREAM_IN].flag.paused  = 0U ;
+        ptrSAI->Control (ARM_SAI_CONTROL_RX, 1U, 0U);
+      }
+      break;
+    default: return (-1);
+  }
+
+  return 0;
+}
+
+/**
+  \fn          int32_t Audio_SetVolume (uint8_t stream, uint8_t channel, uint8_t volume)
+  \brief       Set volume level for Audio stream
+  \param[in]   stream   stream identifier
+  \param[in]   channel  channel identifier
+  \param[in]   volume   volume level (0..100)
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t Audio_SetVolume (uint8_t stream, uint8_t channel, uint8_t volume) {
+  uint32_t out_vol;
+  int32_t   in_vol;
+  uint16_t reg_val;
+  STREAM *ptrStream;
+
+  ptrStream = &Stream[STREAM_IDX(stream)];
+
+  switch (stream) {
+    case AUDIO_STREAM_OUT:
+      // Check if Volume is in range
+      if (volume > 100U) { return -1; }
+
+      // Scale master volume value
+      out_vol  = (252U * volume) / 100U;
+      out_vol  = 252U - out_vol;
+      out_vol &= 0xFFU;
+
+      reg_val = 0U;
+
+      // Set master volume
+      switch (channel) {
+        case AUDIO_CHANNEL_LEFT:
+          ptrStream->vol_lch = out_vol;
+          reg_val           |= out_vol | (ptrStream->vol_rch << 8);
+          break;
+        case AUDIO_CHANNEL_RIGHT:
+          ptrStream->vol_rch = out_vol;
+          reg_val           |= ((out_vol & 0xFFU) << 8) |  ptrStream->vol_lch;
+          break;
+        case AUDIO_CHANNEL_MASTER:
+          ptrStream->vol_lch = out_vol;
+          ptrStream->vol_rch = out_vol;
+          reg_val           |= ((out_vol & 0xFFU) << 8) | (out_vol);
+          break;
+        default: return -1;
+      }
+      if (UDA1380_RegWrite (REG_MASTER_VOLUME,  reg_val) == -1) { return -1; }
+      break;
+    case AUDIO_STREAM_IN:
+
+      if (volume & AUDIO_VOLUME_AUTO_GAIN) {
+#ifdef UDA1380_INPUT_MIC
+        if (channel != AUDIO_CHANNEL_MASTER) { return -1; }
+
+        // Volume level
+        volume &= ~AUDIO_VOLUME_AUTO_GAIN;
+
+        // Check if Volume is in range
+        if (volume > 100U) { return -1; }
+
+        // Set AGC flag;
+        ptrStream->flag.agc = 1U;
+
+        // Scale volume
+        volume /= 25;
+        if (volume > 3) { volume = 3 ; }
+        reg_val = 1 | (volume << 2) | ((UDA1380_AGC_TIME & 7) << 8);
+
+        // Enable and configure AGC
+        if (UDA1380_RegWrite (REG_AGC_SETTINGS,  reg_val) == -1) { return -1; }
+#else
+        return -1;
+#endif
+      } else {
+
+        // Clear AGC flag
+        ptrStream->flag.agc = 0U;
+
+        // Check if Volume is in range
+        if (volume > 100U) { return -1; }
+
+        // Decimator volume
+        in_vol  = (176 * volume) / 100;
+        in_vol -= 128;
+
+        reg_val = 0;
+
+        // Set master volume
+        switch (channel) {
+          case AUDIO_CHANNEL_LEFT:
+            ptrStream->vol_lch = in_vol;
+            reg_val           |= ((in_vol & 0xFFU) << 8) | ptrStream->vol_rch;
+            break;
+          case AUDIO_CHANNEL_RIGHT:
+            ptrStream->vol_rch = in_vol;
+            reg_val           |= in_vol | ((ptrStream->vol_lch & 0xFFU) << 8);
+            break;
+          case AUDIO_CHANNEL_MASTER:
+            ptrStream->vol_lch = in_vol;
+            ptrStream->vol_rch = in_vol;
+            reg_val           |= ((in_vol & 0xFFU) << 8) | (in_vol);
+            break;
+          default: return -1;
+        }
+        if (UDA1380_RegWrite (REG_DECIMATOR_VOLUME,  reg_val) == -1) { return -1; }
+
+#ifdef UDA1380_INPUT_MIC
+        // Disable AGC
+        if (UDA1380_RegWrite (REG_AGC_SETTINGS,            0) == -1) { return -1; }
+#endif
+      }
+
+      break;
+    default: return (-1);
+  }
+
+  return 0;
+}
+
+/**
+  \fn          int32_t Audio_SetMute (uint8_t stream, uint8_t channel, bool mute)
+  \brief       Set mute state for Audio stream
+  \param[in]   stream   stream identifier
+  \param[in]   channel  channel identifier
+  \param[in]   mute     mute state
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t Audio_SetMute (uint8_t stream, uint8_t channel, bool mute) {
+  uint16_t reg_val;
+  STREAM *ptrStream;
+
+  ptrStream = &Stream[STREAM_IDX(stream)];
+
+  reg_val = 0U;
+  switch (stream) {
+    case AUDIO_STREAM_OUT:
+      switch (channel) {
+        case AUDIO_CHANNEL_LEFT:
+          // Set or Reset mute on left channel
+          if (mute == true) { reg_val = 0xFCU; }
+          else              { reg_val = ptrStream->vol_lch; }
+
+          // Right channel volume is unchanged
+          reg_val |= (ptrStream->vol_rch << 8);
+          break;
+        case AUDIO_CHANNEL_RIGHT:
+          // Set or Reset mute on Right channel
+          if (mute == true) { reg_val = (0xFCU << 8); }
+          else              { reg_val = (ptrStream->vol_rch << 8); }
+
+          // Left channel volume is unchanged
+          reg_val |= ptrStream->vol_lch;
+          break;
+        case AUDIO_CHANNEL_MASTER:
+          // Set or reset mute on both channels (left and right)
+          if (mute == true) { reg_val = (0xFCU << 8) | 0xFCU; }
+          else              { reg_val = (ptrStream->vol_rch << 8) | ptrStream->vol_lch; }
+          break;
+        default: return -1;
+      }
+      if (UDA1380_RegWrite (REG_MASTER_VOLUME,  reg_val) == -1) { return -1; }
+      break;
+    case AUDIO_STREAM_IN:
+#ifdef UDA1380_INPUT_MIC
+      if (ptrStream->flag.agc != 0U) { return -1; }
+#endif
+      switch (channel) {
+        case AUDIO_CHANNEL_LEFT:
+          // Set or Reset mute on left channel
+          if (mute == true) { reg_val = (0x80U << 8); }
+          else              { reg_val = (ptrStream->vol_lch << 8); }
+
+          // Right channel volume is unchanged
+          reg_val |= ptrStream->vol_rch;
+          break;
+        case AUDIO_CHANNEL_RIGHT:
+          // Set or Reset mute on Right channel
+          if (mute == true) { reg_val = 0x80U; }
+          else              { reg_val = ptrStream->vol_rch; }
+
+          // Left channel volume is unchanged
+          reg_val |= ptrStream->vol_lch << 8;
+          break;
+        case AUDIO_CHANNEL_MASTER:
+          // Set or reset mute on both channels (left and right)
+          if (mute == true) { reg_val = (0x80U << 8) | 0x80U; }
+          else              { reg_val = (ptrStream->vol_lch << 8) | ptrStream->vol_rch; }
+          break;
+        default: return -1;
+      }
+      if (UDA1380_RegWrite (REG_DECIMATOR_VOLUME,  reg_val) == -1) { return -1; }
+      break;
+    default: return (-1);
+  }
+
+  return 0;
+}
+
+/**
+  \fn          int32_t Audio_SetDataFormat (uint8_t stream, uint8_t format)
+  \brief       Set Audio data format
+  \param[in]   stream  stream identifier
+  \param[in]   format  data format
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t Audio_SetDataFormat (uint8_t stream, uint8_t format) {
+  STREAM *ptrStream;
+
+  ptrStream = &Stream[STREAM_IDX(stream)];
+
+  switch (format) {
+    case AUDIO_DATA_8_MONO:
+      ptrStream->data_bits = 8U;
+      ptrStream->flag.mono = 1U;
+      break;
+    case AUDIO_DATA_16_MONO:
+      ptrStream->data_bits = 16U;
+      ptrStream->flag.mono = 1U;
+      break;
+    case AUDIO_DATA_32_MONO:
+      ptrStream->data_bits = 32U;
+      ptrStream->flag.mono = 1U;
+      break;
+    case AUDIO_DATA_8_STEREO:
+      ptrStream->data_bits = 8U;
+      ptrStream->flag.mono = 0U;
+      break;
+    case AUDIO_DATA_16_STEREO:
+      ptrStream->data_bits = 16U;
+      ptrStream->flag.mono = 0U;
+      break;
+    case AUDIO_DATA_32_STEREO:
+      ptrStream->data_bits = 32U;
+      ptrStream->flag.mono = 0U;
+      break;
+    default: return -1;
+  }
+
+  return (SAI_Configure (stream));
+}
+
+/**
+  \fn          int32_t Audio_SetFrequency (uint8_t stream, uint32_t frequency)
+  \brief       Set Audio stream frequency
+  \param[in]   stream     stream identifier
+  \param[in]   frequency  Audio frequency in Hz
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t Audio_SetFrequency (uint8_t stream, uint32_t frequency) {
+  uint16_t  reg_val;
+  uint16_t  pll;
+  STREAM   *ptrStream;
+
+  ptrStream = &Stream[STREAM_IDX(stream)];
+
+  // Configure Clock register
+  if (UDA1380_RegRead (REG_CLOCK_SETTINGS, &reg_val) == -1) { return -1; }
+
+  // Set proper PLL (in REG_CLOCK_SETTINGS), regarding input freq range
+  if      (frequency <    6250U) { return -1; }
+  if      (frequency <=  12500U) { pll = 0U;  }
+  else if (frequency <=  25000U) { pll = 1U;  }
+  else if (frequency <=  50000U) { pll = 2U;  }
+  else if (frequency <= 100000U) { pll = 3U;  }
+  else                           { return -1; }
+
+  reg_val &= ~3U;
+  reg_val |=  pll;
+
+  // ADC_CLK and DAC_CLK are derived from the WSPLL
+  reg_val |= (1U << 4) | (1U << 5);
+
+  if (UDA1380_RegWrite (REG_CLOCK_SETTINGS, reg_val) == -1) { return -1; }
+
+  ptrStream->freq = frequency;
+
+  return (SAI_Configure (stream));
+}

CMSIS/Pack/Example/Boards/Keil/MCB1800/Common/Buttons_MCB1800.c

@@ -0,0 +1,125 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Name:    Buttons_MCB1800.c
+ * Purpose: Buttons interface for MCB1800 evaluation board
+ * Rev.:    1.00
+ *----------------------------------------------------------------------------*/
+
+#include "LPC18xx.h"
+#include "SCU_LPC18xx.h"
+#include "GPIO_LPC18xx.h"
+#include "Board_Buttons.h"
+
+#define BUTTONS_COUNT                  (4)
+#define BUTTON_P4_0                    (1 << 0)
+#define BUTTON_P4_3                    (1 << 1)
+#define BUTTON_P4_4                    (1 << 2)
+#define BUTTON_WAKEUP0                 (1 << 3)
+
+/* Button pins:
+   - BUTTON0: P4_0 = GPIO2[0]
+   - BUTTON1: P4_3 = GPIO2[3]
+   - BUTTON2: P4_4 = GPIO2[4]
+   - BUTTON3: WAKEUP0         */
+
+/* Button GPIO definitions */
+const GPIO_ID BUTTON_GPIO[] = {
+  { 2, 0 },
+  { 2, 3 },
+  { 2, 4 }
+};
+
+/* Button pin definitions */
+const PIN_ID BUTTON_PIN[] = {
+  { 4, 0, (SCU_CFG_MODE_FUNC0 | SCU_SFS_EZI)},
+  { 4, 3, (SCU_CFG_MODE_FUNC0 | SCU_SFS_EZI)},
+  { 4, 4, (SCU_CFG_MODE_FUNC0 | SCU_SFS_EZI)}
+};
+
+
+/**
+  \fn          int32_t Buttons_Initialize (void)
+  \brief       Initialize buttons
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t Buttons_Initialize (void) {
+
+  /* Enable GPIO clock */
+  GPIO_PortClock   (1);
+
+  /* Configure Pins */
+  SCU_PinConfigure (BUTTON_PIN[0].port, BUTTON_PIN[0].num, BUTTON_PIN[0].config_val);
+  SCU_PinConfigure (BUTTON_PIN[1].port, BUTTON_PIN[1].num, BUTTON_PIN[1].config_val);
+  SCU_PinConfigure (BUTTON_PIN[2].port, BUTTON_PIN[2].num, BUTTON_PIN[2].config_val);
+
+  /* Configure WAKEUP0 input */
+  LPC_CREG->CREG0          &= ~(3<<14); /* WAKEUP0 input to event router      */
+  LPC_EVENTROUTER->HILO    &= ~ 1;      /* Detect low level or falling edge   */
+  LPC_EVENTROUTER->EDGE    &= ~ 1;      /* Activate level detect              */
+  LPC_EVENTROUTER->CLR_STAT =   1;      /* Clear status event bit 0           */
+
+  return 0;
+}
+
+/**
+  \fn          int32_t Buttons_Uninitialize (void)
+  \brief       De-initialize buttons
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t Buttons_Uninitialize (void) {
+
+  /* Unconfigure Pins */
+  SCU_PinConfigure (BUTTON_PIN[0].port, BUTTON_PIN[0].num, 0);
+  SCU_PinConfigure (BUTTON_PIN[1].port, BUTTON_PIN[1].num, 0);
+  SCU_PinConfigure (BUTTON_PIN[2].port, BUTTON_PIN[2].num, 0);
+
+  return 0;
+}
+
+/**
+  \fn          uint32_t Buttons_GetState (void)
+  \brief       Get buttons state
+  \returns     Buttons state
+*/
+uint32_t Buttons_GetState (void) {
+  uint32_t val;
+
+  val = 0;
+  if (!(GPIO_PinRead (BUTTON_GPIO[0].port, BUTTON_GPIO[0].num))) val |= BUTTON_P4_0;
+  if (!(GPIO_PinRead (BUTTON_GPIO[1].port, BUTTON_GPIO[1].num))) val |= BUTTON_P4_3;
+  if (!(GPIO_PinRead (BUTTON_GPIO[2].port, BUTTON_GPIO[2].num))) val |= BUTTON_P4_4;
+
+  /* Check WAKEUP0 input */
+  LPC_EVENTROUTER->CLR_STAT = 1;        /* Clear STATUS event bit 0           */
+  if (LPC_EVENTROUTER->STATUS & 1)                               val |= BUTTON_WAKEUP0;
+
+  return val;
+}
+
+/**
+  \fn          uint32_t Buttons_GetCount (void)
+  \brief       Get number of available buttons
+  \return      Number of available buttons
+*/
+uint32_t Buttons_GetCount (void) {
+  return BUTTONS_COUNT;
+}

CMSIS/Pack/Example/Boards/Keil/MCB1800/Common/EEPROM_24LC128.c

@@ -0,0 +1,170 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Name:    EEPROM_24LC128.c
+ * Purpose: EEPROM 24LC128 interface
+ * Rev.:    1.00
+ *----------------------------------------------------------------------------*/
+
+#include <string.h>
+#include "Driver_I2C.h"
+#include "Board_EEPROM.h"
+
+#ifndef EEPROM_I2C_PORT
+#define EEPROM_I2C_PORT       0         /* I2C Port number                    */
+#endif
+
+#define EEPROM_I2C_ADDR       0x51      /* 24LC128 EEPROM I2C address         */
+
+/* I2C Driver */
+#define _I2C_Driver_(n)       Driver_I2C##n
+#define  I2C_Driver_(n)      _I2C_Driver_(n)
+extern ARM_DRIVER_I2C         I2C_Driver_(EEPROM_I2C_PORT);
+#define ptrI2C              (&I2C_Driver_(EEPROM_I2C_PORT))
+
+#define EEPROM_MAX_ADDR       16384     /* Max memory locations available     */
+#define EEPROM_MAX_WRITE      64        /* Max bytes to write in one step     */
+
+#define A_WR                  0         /* Master will write to the I2C       */
+#define A_RD                  1         /* Master will read from the I2C      */
+
+static uint8_t DeviceAddr;
+static uint8_t wr_buf[EEPROM_MAX_WRITE + 2];
+
+
+static int32_t EEPROM_WriteBuf (uint16_t addr, const uint8_t *buf, uint32_t len) {
+
+  wr_buf[0] = (uint8_t)(addr >> 8);
+  wr_buf[1] = (uint8_t)(addr & 0xFF);
+
+  memcpy (&wr_buf[2], &buf[0], len);
+
+  ptrI2C->MasterTransmit (DeviceAddr, wr_buf, len + 2, false);
+  while (ptrI2C->GetStatus().busy);
+  if (ptrI2C->GetDataCount () != (len + 2)) return -1;
+
+  /* Acknowledge polling */
+  do {
+    ptrI2C->MasterReceive (DeviceAddr, &wr_buf[0], 1, false);
+    while (ptrI2C->GetStatus().busy);
+  } while (ptrI2C->GetDataCount () < 0);
+
+  return 0;
+}
+
+static int32_t EEPROM_ReadBuf (uint16_t addr, uint8_t *buf, uint32_t len) {
+  uint8_t a[2];
+
+  a[0] = (uint8_t)(addr >> 8);
+  a[1] = (uint8_t)(addr & 0xFF);
+
+  ptrI2C->MasterTransmit (DeviceAddr, a, 2, true);
+  while (ptrI2C->GetStatus().busy);
+  ptrI2C->MasterReceive (DeviceAddr, buf, len, false);
+  while (ptrI2C->GetStatus().busy);
+  if (ptrI2C->GetDataCount () != len) return -1;
+
+  return 0;
+}
+
+
+/**
+  \fn          int32_t EEPROM_Initialize (void)
+  \brief       Initialize EEPROM
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t EEPROM_Initialize (void) {
+  uint8_t val;
+
+  ptrI2C->Initialize   (NULL);
+  ptrI2C->PowerControl (ARM_POWER_FULL);
+  ptrI2C->Control      (ARM_I2C_BUS_SPEED, ARM_I2C_BUS_SPEED_FAST);
+  ptrI2C->Control      (ARM_I2C_BUS_CLEAR, 0);
+
+  /* Init 24LC128 EEPROM device */
+  DeviceAddr = EEPROM_I2C_ADDR;
+
+  /* Read min and max address */
+  if (EEPROM_ReadBuf (0x00, &val, 1) == 0) {
+    return (EEPROM_ReadBuf (EEPROM_MAX_ADDR-1, &val, 1));
+  }
+  return -1;
+}
+
+/**
+  \fn          int32_t EEPROM_Uninitialize (void)
+  \brief       De-initialize EEPROM
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t EEPROM_Uninitialize (void) {
+  return 0;
+}
+
+/**
+  \fn          uint32_t EEPROM_GetSize (void)
+  \brief       Get EEPROM memory size in bytes
+  \returns     Memory size in bytes
+*/
+uint32_t EEPROM_GetSize (void) {
+  return EEPROM_MAX_ADDR;
+}
+
+/**
+  \fn          int32_t EEPROM_ReadData (uint32_t addr, uint8_t *buf, uint32_t len)
+  \brief       Read data from EEPROM
+  \param[in]   addr   EEPROM address
+  \param[in]   buf    Pointer where data will be read from EEPROM
+  \param[in]   len    Number of data bytes to read
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t EEPROM_ReadData (uint32_t addr, uint8_t *buf, uint32_t len) {
+  if (addr < EEPROM_MAX_ADDR) {
+    return (EEPROM_ReadBuf ((uint16_t)addr, buf, len));
+  }
+  return -1;
+}
+
+/**
+  \fn          int32_t EEPROM_WriteData (uint32_t addr, const uint8_t *buf, uint32_t len)
+  \brief       Write data to EEPROM
+  \param[in]   addr   EEPROM address
+  \param[in]   buf    Pointer with data to write to EEPROM
+  \param[in]   len    Number of data bytes to write
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t EEPROM_WriteData (uint32_t addr, const uint8_t *buf, uint32_t len) {
+  uint32_t len_cur;
+
+  if (addr < EEPROM_MAX_ADDR) {
+    while (len) {
+      len_cur = ((len > EEPROM_MAX_WRITE) ? EEPROM_MAX_WRITE : len);
+      if (EEPROM_WriteBuf ((uint16_t)addr, buf, len_cur) == -1) return -1;
+      len  -= len_cur;
+      addr += len_cur;
+    }
+    return 0;
+  }
+  return -1;
+}

CMSIS/Pack/Example/Boards/Keil/MCB1800/Common/GLCD_Config.h

@@ -0,0 +1,75 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Name:    GLCD_Config.h
+ * Purpose: Graphic LCD interface configuration file for MCB1800 evaluation board
+ * Rev.:    1.00
+ *----------------------------------------------------------------------------*/
+
+#ifndef __GLCD_CONFIG_H
+#define __GLCD_CONFIG_H
+
+/*---------------------- Graphic LCD orientation configuration ---------------*/
+#ifndef GLCD_MIRROR_X
+#define GLCD_MIRROR_X   0               /* Mirror X axis = 1:yes, 0:no */
+#endif
+#ifndef GLCD_MIRROR_Y
+#define GLCD_MIRROR_Y   1               /* Mirror Y axis = 1:yes, 0:no */
+#endif
+#ifndef GLCD_SWAP_XY
+#define GLCD_SWAP_XY    1               /* Swap X&Y axis = 1:yes, 0:no */
+#endif
+
+/*---------------------- Graphic LCD physical definitions --------------------*/
+#define GLCD_SIZE_X     240             /* Screen size X (in pixels) */
+#define GLCD_SIZE_Y     320             /* Screen size Y (in pixels) */
+#define GLCD_BPP        16              /* Bits per pixel            */
+
+#if    (GLCD_SWAP_XY)
+#define GLCD_WIDTH      GLCD_SIZE_Y     /* Screen Width  (in pixels) */
+#define GLCD_HEIGHT     GLCD_SIZE_X     /* Screen Height (in pixels) */
+#else
+#define GLCD_WIDTH      GLCD_SIZE_X     /* Screen Width  (in pixels) */
+#define GLCD_HEIGHT     GLCD_SIZE_Y     /* Screen Height (in pixels) */
+#endif
+
+/*---------------------- Graphic LCD color definitions -----------------------*/
+/* Color coding (16-bit): 
+     15..11 = R4..0 (Red)
+     10..5  = G5..0 (Green)
+      4..0  = B4..0 (Blue)
+*/
+
+/* GLCD RGB color definitions                            */
+#define GLCD_COLOR_BLACK        0x0000  /*   0,   0,   0 */
+#define GLCD_COLOR_NAVY         0x000F  /*   0,   0, 128 */
+#define GLCD_COLOR_DARK_GREEN   0x03E0  /*   0, 128,   0 */
+#define GLCD_COLOR_DARK_CYAN    0x03EF  /*   0, 128, 128 */
+#define GLCD_COLOR_MAROON       0x7800  /* 128,   0,   0 */
+#define GLCD_COLOR_PURPLE       0x780F  /* 128,   0, 128 */
+#define GLCD_COLOR_OLIVE        0x7BE0  /* 128, 128,   0 */
+#define GLCD_COLOR_LIGHT_GREY   0xC618  /* 192, 192, 192 */
+#define GLCD_COLOR_DARK_GREY    0x7BEF  /* 128, 128, 128 */
+#define GLCD_COLOR_BLUE         0x001F  /*   0,   0, 255 */
+#define GLCD_COLOR_GREEN        0x07E0  /*   0, 255,   0 */
+#define GLCD_COLOR_CYAN         0x07FF  /*   0, 255, 255 */
+#define GLCD_COLOR_RED          0xF800  /* 255,   0,   0 */
+#define GLCD_COLOR_MAGENTA      0xF81F  /* 255,   0, 255 */
+#define GLCD_COLOR_YELLOW       0xFFE0  /* 255, 255, 0   */
+#define GLCD_COLOR_WHITE        0xFFFF  /* 255, 255, 255 */
+
+#endif /* __GLCD_CONFIG_H */

CMSIS/Pack/Example/Boards/Keil/MCB1800/Common/GLCD_Fonts.c

@@ -0,0 +1,721 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Name:    GLCD_Fonts.c
+ * Purpose: Graphic fonts 6x8 (WxH) and 16x24 with horizontal pixel packing
+ * Rev.:    1.00
+ *----------------------------------------------------------------------------*/
+
+#include "Board_GLCD.h"
+
+static const uint8_t Font_6x8_h[(144-32)*8] = {
+  /* 0x20: Space ' ' */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x21: '!' */
+  0x04, 0x04, 0x04, 0x04, 0x04, 0x00, 0x04, 0x00,
+  /* 0x22: '"' */
+  0x0A, 0x0A, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x23: '#' */
+  0x0A, 0x0A, 0x1F, 0x0A, 0x1F, 0x0A, 0x0A, 0x00,
+  /* 0x24: '$' */
+  0x04, 0x1E, 0x05, 0x0E, 0x14, 0x0F, 0x04, 0x00,
+  /* 0x25: '%' */
+  0x03, 0x13, 0x08, 0x04, 0x02, 0x19, 0x18, 0x00,
+  /* 0x26: '&' */
+  0x02, 0x05, 0x05, 0x02, 0x15, 0x09, 0x16, 0x00,
+  /* 0x27: ''' */
+  0x0C, 0x0C, 0x04, 0x02, 0x00, 0x00, 0x00, 0x00,
+  /* 0x28: '(' */
+  0x08, 0x04, 0x02, 0x02, 0x02, 0x04, 0x08, 0x00,
+  /* 0x29: ')' */
+  0x02, 0x04, 0x08, 0x08, 0x08, 0x04, 0x02, 0x00,
+  /* 0x2A: '*' */
+  0x00, 0x04, 0x15, 0x0E, 0x0E, 0x15, 0x04, 0x00,
+  /* 0x2B: '+' */
+  0x00, 0x04, 0x04, 0x1F, 0x04, 0x04, 0x00, 0x00,
+  /* 0x2C: ',' */
+  0x00, 0x00, 0x00, 0x00, 0x0C, 0x0C, 0x04, 0x02,
+  /* 0x2D: '-' */
+  0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00,
+  /* 0x2E: '.' */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x0C, 0x00,
+  /* 0x2F: '/' */
+  0x00, 0x10, 0x08, 0x04, 0x02, 0x01, 0x00, 0x00,
+  /* 0x30: '0' */
+  0x0E, 0x11, 0x13, 0x15, 0x19, 0x11, 0x0E, 0x00,
+  /* 0x31: '1' */
+  0x04, 0x06, 0x04, 0x04, 0x04, 0x04, 0x0E, 0x00,
+  /* 0x32: '2' */
+  0x0E, 0x11, 0x10, 0x0E, 0x01, 0x01, 0x1F, 0x00,
+  /* 0x33: '3' */
+  0x1F, 0x10, 0x08, 0x0C, 0x10, 0x11, 0x0E, 0x00,
+  /* 0x34: '4' */
+  0x08, 0x0C, 0x0A, 0x09, 0x1F, 0x08, 0x08, 0x00,
+  /* 0x35: '5' */
+  0x1F, 0x01, 0x0F, 0x10, 0x10, 0x11, 0x0E, 0x00,
+  /* 0x36: '6' */
+  0x1C, 0x02, 0x01, 0x0F, 0x11, 0x11, 0x0E, 0x00,
+  /* 0x37: '7' */
+  0x1F, 0x10, 0x10, 0x08, 0x04, 0x02, 0x01, 0x00,
+  /* 0x38: '8' */
+  0x0E, 0x11, 0x11, 0x0E, 0x11, 0x11, 0x0E, 0x00,
+  /* 0x39: '9' */
+  0x0E, 0x11, 0x11, 0x1E, 0x10, 0x08, 0x07, 0x00,
+  /* 0x3A: ':' */
+  0x00, 0x00, 0x04, 0x00, 0x04, 0x00, 0x00, 0x00,
+  /* 0x3B: ';' */
+  0x00, 0x00, 0x04, 0x00, 0x04, 0x04, 0x02, 0x00,
+  /* 0x3C: '<' */
+  0x10, 0x08, 0x04, 0x02, 0x04, 0x08, 0x10, 0x00,
+  /* 0x3D: '=' */
+  0x00, 0x00, 0x1F, 0x00, 0x1F, 0x00, 0x00, 0x00,
+  /* 0x3E: '>' */
+  0x02, 0x04, 0x08, 0x10, 0x08, 0x04, 0x02, 0x00,
+  /* 0x3F: '?' */
+  0x0E, 0x11, 0x10, 0x0C, 0x04, 0x00, 0x04, 0x00,
+  /* 0x40: '@' */
+  0x0E, 0x11, 0x15, 0x1D, 0x0D, 0x01, 0x1E, 0x00,
+  /* 0x41: 'A' */
+  0x04, 0x0A, 0x11, 0x11, 0x1F, 0x11, 0x11, 0x00,
+  /* 0x42: 'B' */
+  0x0F, 0x11, 0x11, 0x0F, 0x11, 0x11, 0x0F, 0x00,
+  /* 0x43: 'C' */
+  0x0E, 0x11, 0x01, 0x01, 0x01, 0x11, 0x0E, 0x00,
+  /* 0x44: 'D' */
+  0x0F, 0x11, 0x11, 0x11, 0x11, 0x11, 0x0F, 0x00,
+  /* 0x45: 'E' */
+  0x1F, 0x01, 0x01, 0x0F, 0x01, 0x01, 0x1F, 0x00,
+  /* 0x46: 'F' */
+  0x1F, 0x01, 0x01, 0x0F, 0x01, 0x01, 0x01, 0x00,
+  /* 0x47: 'G' */
+  0x1E, 0x11, 0x01, 0x01, 0x19, 0x11, 0x1E, 0x00,
+  /* 0x48: 'H' */
+  0x11, 0x11, 0x11, 0x1F, 0x11, 0x11, 0x11, 0x00,
+  /* 0x49: 'I' */
+  0x0E, 0x04, 0x04, 0x04, 0x04, 0x04, 0x0E, 0x00,
+  /* 0x4A: 'J' */
+  0x1C, 0x08, 0x08, 0x08, 0x08, 0x09, 0x06, 0x00,
+  /* 0x4B: 'K' */
+  0x11, 0x09, 0x05, 0x03, 0x05, 0x09, 0x11, 0x00,
+  /* 0x4C: 'L' */
+  0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x1F, 0x00,
+  /* 0x4D: 'M' */
+  0x11, 0x1B, 0x15, 0x15, 0x15, 0x11, 0x11, 0x00,
+  /* 0x4E: 'N' */
+  0x11, 0x11, 0x13, 0x15, 0x19, 0x11, 0x11, 0x00,
+  /* 0x4F: 'O' */
+  0x0E, 0x11, 0x11, 0x11, 0x11, 0x11, 0x0E, 0x00,
+  /* 0x50: 'P' */
+  0x0F, 0x11, 0x11, 0x0F, 0x01, 0x01, 0x01, 0x00,
+  /* 0x51: 'Q' */
+  0x0E, 0x11, 0x11, 0x11, 0x15, 0x09, 0x16, 0x00,
+  /* 0x52: 'R' */
+  0x0F, 0x11, 0x11, 0x0F, 0x05, 0x09, 0x11, 0x00,
+  /* 0x53: 'S' */
+  0x0E, 0x11, 0x01, 0x0E, 0x10, 0x11, 0x0E, 0x00,
+  /* 0x54: 'T' */
+  0x1F, 0x15, 0x04, 0x04, 0x04, 0x04, 0x04, 0x00,
+  /* 0x55: 'U' */
+  0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x0E, 0x00,
+  /* 0x56: 'V' */
+  0x11, 0x11, 0x11, 0x11, 0x11, 0x0A, 0x04, 0x00,
+  /* 0x57: 'W' */
+  0x11, 0x11, 0x11, 0x15, 0x15, 0x15, 0x0A, 0x00,
+  /* 0x58: 'X' */
+  0x11, 0x11, 0x0A, 0x04, 0x0A, 0x11, 0x11, 0x00,
+  /* 0x59: 'Y' */
+  0x11, 0x11, 0x0A, 0x04, 0x04, 0x04, 0x04, 0x00,
+  /* 0x5A: 'Z' */
+  0x1F, 0x10, 0x08, 0x0E, 0x02, 0x01, 0x1F, 0x00,
+  /* 0x5B: '[' */
+  0x1E, 0x02, 0x02, 0x02, 0x02, 0x02, 0x1E, 0x00,
+  /* 0x5C: '\' */
+  0x00, 0x01, 0x02, 0x04, 0x08, 0x10, 0x00, 0x00,
+  /* 0x5D: ']' */
+  0x1E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x00,
+  /* 0x5E: '^' */
+  0x04, 0x0A, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x5F: '_' */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00,
+  /* 0x60: ''' */
+  0x06, 0x06, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00,
+  /* 0x61: 'a' */
+  0x00, 0x00, 0x06, 0x08, 0x0E, 0x09, 0x1E, 0x00,
+  /* 0x62: 'b' */
+  0x01, 0x01, 0x0D, 0x13, 0x11, 0x13, 0x0D, 0x00,
+  /* 0x63: 'c' */
+  0x00, 0x00, 0x0E, 0x11, 0x01, 0x11, 0x0E, 0x00,
+  /* 0x64: 'd' */
+  0x10, 0x10, 0x16, 0x19, 0x11, 0x19, 0x16, 0x00,
+  /* 0x65: 'e' */
+  0x00, 0x00, 0x0E, 0x11, 0x1F, 0x01, 0x0E, 0x00,
+  /* 0x66: 'f' */
+  0x08, 0x14, 0x04, 0x0E, 0x04, 0x04, 0x04, 0x00,
+  /* 0x67: 'g' */
+  0x00, 0x00, 0x0E, 0x19, 0x19, 0x16, 0x10, 0x0E,
+  /* 0x68: 'h' */
+  0x01, 0x01, 0x0D, 0x13, 0x11, 0x11, 0x11, 0x00,
+  /* 0x69: 'i' */
+  0x04, 0x00, 0x06, 0x04, 0x04, 0x04, 0x0E, 0x00,
+  /* 0x6A: 'j' */
+  0x08, 0x00, 0x08, 0x08, 0x08, 0x09, 0x06, 0x00,
+  /* 0x6B: 'k' */
+  0x01, 0x01, 0x09, 0x05, 0x03, 0x05, 0x09, 0x00,
+  /* 0x6C: 'l' */
+  0x06, 0x04, 0x04, 0x04, 0x04, 0x04, 0x0E, 0x00,
+  /* 0x6D: 'm' */
+  0x00, 0x00, 0x0B, 0x15, 0x15, 0x15, 0x15, 0x00,
+  /* 0x6E: 'n' */
+  0x00, 0x00, 0x0D, 0x13, 0x11, 0x11, 0x11, 0x00,
+  /* 0x6F: 'o' */
+  0x00, 0x00, 0x0E, 0x11, 0x11, 0x11, 0x0E, 0x00,
+  /* 0x70: 'p' */
+  0x00, 0x00, 0x0D, 0x13, 0x13, 0x0D, 0x01, 0x01,
+  /* 0x71: 'q' */
+  0x00, 0x00, 0x16, 0x19, 0x19, 0x16, 0x10, 0x10,
+  /* 0x72: 'r' */
+  0x00, 0x00, 0x0D, 0x13, 0x01, 0x01, 0x01, 0x00,
+  /* 0x73: 's' */
+  0x00, 0x00, 0x1E, 0x01, 0x0E, 0x10, 0x0F, 0x00,
+  /* 0x74: 't' */
+  0x04, 0x04, 0x1F, 0x04, 0x04, 0x14, 0x08, 0x00,
+  /* 0x75: 'u' */
+  0x00, 0x00, 0x11, 0x11, 0x11, 0x19, 0x16, 0x00,
+  /* 0x76: 'v' */
+  0x00, 0x00, 0x11, 0x11, 0x11, 0x0A, 0x04, 0x00,
+  /* 0x77: 'w' */
+  0x00, 0x00, 0x11, 0x11, 0x15, 0x15, 0x0A, 0x00,
+  /* 0x78: 'x' */
+  0x00, 0x00, 0x11, 0x0A, 0x04, 0x0A, 0x11, 0x00,
+  /* 0x79: 'y' */
+  0x00, 0x00, 0x11, 0x11, 0x1E, 0x10, 0x11, 0x0E,
+  /* 0x7A: 'z' */
+  0x00, 0x00, 0x1F, 0x08, 0x04, 0x02, 0x1F, 0x00,
+  /* 0x7B: '{' */
+  0x08, 0x04, 0x04, 0x02, 0x04, 0x04, 0x08, 0x00,
+  /* 0x7C: '|' */
+  0x04, 0x04, 0x04, 0x00, 0x04, 0x04, 0x04, 0x00,
+  /* 0x7D: '}' */
+  0x02, 0x04, 0x04, 0x08, 0x04, 0x04, 0x02, 0x00,
+  /* 0x7E: '~' */
+  0x02, 0x15, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x7F: ' ' */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+  /* Special Symbols  starting at character 0x80 */
+  /* 0x80: Circle - Empty */
+  0x00, 0x00, 0x0C, 0x12, 0x12, 0x0C, 0x00, 0x00,
+  /* 0x81: Circle - Full */
+  0x00, 0x00, 0x0C, 0x1E, 0x1E, 0x0C, 0x00, 0x00,
+  /* 0x82: Square - Empty */
+  0x00, 0x00, 0x1E, 0x12, 0x12, 0x1E, 0x00, 0x00,
+  /* 0x83: Square - Full */
+  0x00, 0x00, 0x1E, 0x1E, 0x1E, 0x1E, 0x00, 0x00,
+  /* 0x84: Up - Empty */
+  0x00, 0x00, 0x0C, 0x0C, 0x12, 0x1E, 0x00, 0x00,
+  /* 0x85: Up - Full */
+  0x00, 0x00, 0x0C, 0x0C, 0x1E, 0x1E, 0x00, 0x00,
+  /* 0x86: Down - Empty */
+  0x00, 0x00, 0x1E, 0x12, 0x0C, 0x0C, 0x00, 0x00,
+  /* 0x87: Down - Full */
+  0x00, 0x00, 0x1E, 0x1E, 0x0C, 0x0C, 0x00, 0x00,
+  /* 0x88: Left - Empty */
+  0x00, 0x00, 0x18, 0x16, 0x16, 0x18, 0x00, 0x00,
+  /* 0x89: Left - Full */
+  0x00, 0x00, 0x18, 0x1E, 0x1E, 0x18, 0x00, 0x00,
+  /* 0x8A: Right - Empty */
+  0x00, 0x00, 0x06, 0x1A, 0x1A, 0x06, 0x00, 0x00,
+  /* 0x8B: Right - Full */
+  0x00, 0x00, 0x06, 0x1E, 0x1E, 0x06, 0x00, 0x00,
+  /* 0x8C: Wait - Empty */
+  0x00, 0x00, 0x0C, 0x12, 0x12, 0x0C, 0x00, 0x00,
+  /* 0x8D: Wait - Full */
+  0x00, 0x00, 0x0C, 0x1E, 0x1E, 0x0C, 0x00, 0x00,
+  /* 0x8E: Walk - Empty */
+  0x00, 0x00, 0x1E, 0x12, 0x12, 0x1E, 0x00, 0x00,
+  /* 0x8F: Walk - Full */
+  0x00, 0x00, 0x1E, 0x1E, 0x1E, 0x1E, 0x00, 0x00,
+};
+
+static const uint8_t Font_16x24_h[(144-32)*48] = {
+  /* 0x20: Space ' ' */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x21: '!' */
+  0x00, 0x00, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01,
+  0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00,
+  0x80, 0x01, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x22: '"' */
+  0x00, 0x00, 0x00, 0x00, 0xCC, 0x00, 0xCC, 0x00, 0xCC, 0x00, 0xCC, 0x00, 0xCC, 0x00, 0xCC, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x23: '#' */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x0C, 0x60, 0x0C,
+  0x60, 0x0C, 0x30, 0x06, 0x30, 0x06, 0xFE, 0x1F, 0xFE, 0x1F, 0x30, 0x06, 0x38, 0x07, 0x18, 0x03,
+  0xFE, 0x1F, 0xFE, 0x1F, 0x18, 0x03, 0x18, 0x03, 0x8C, 0x01, 0x8C, 0x01, 0x8C, 0x01, 0x00, 0x00,
+  /* 0x24: '$' */
+  0x00, 0x00, 0x80, 0x00, 0xE0, 0x03, 0xF8, 0x0F, 0x9C, 0x0E, 0x8C, 0x1C, 0x8C, 0x18, 0x8C, 0x00,
+  0x98, 0x00, 0xF8, 0x01, 0xE0, 0x07, 0x80, 0x0E, 0x80, 0x1C, 0x8C, 0x18, 0x8C, 0x18, 0x9C, 0x18,
+  0xB8, 0x0C, 0xF0, 0x0F, 0xE0, 0x03, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x25: '%' */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0E, 0x18, 0x1B, 0x0C, 0x11, 0x0C, 0x11, 0x06, 0x11, 0x06,
+  0x11, 0x03, 0x11, 0x03, 0x9B, 0x01, 0x8E, 0x01, 0xC0, 0x38, 0xC0, 0x6C, 0x60, 0x44, 0x60, 0x44,
+  0x30, 0x44, 0x30, 0x44, 0x18, 0x44, 0x18, 0x6C, 0x0C, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x26: '&' */
+  0x00, 0x00, 0xE0, 0x01, 0xF0, 0x03, 0x38, 0x07, 0x18, 0x06, 0x18, 0x06, 0x30, 0x03, 0xF0, 0x01,
+  0xF0, 0x00, 0xF8, 0x00, 0x9C, 0x31, 0x0E, 0x33, 0x06, 0x1E, 0x06, 0x1C, 0x06, 0x1C, 0x06, 0x3F,
+  0xFC, 0x73, 0xF0, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x27: ''' */
+  0x00, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x28: '(' */
+  0x00, 0x00, 0x00, 0x02, 0x00, 0x03, 0x80, 0x01, 0xC0, 0x00, 0xC0, 0x00, 0x60, 0x00, 0x60, 0x00,
+  0x30, 0x00, 0x30, 0x00, 0x30, 0x00, 0x30, 0x00, 0x30, 0x00, 0x30, 0x00, 0x30, 0x00, 0x30, 0x00,
+  0x60, 0x00, 0x60, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0x80, 0x01, 0x00, 0x03, 0x00, 0x02, 0x00, 0x00,
+  /* 0x29: ')' */
+  0x00, 0x00, 0x20, 0x00, 0x60, 0x00, 0xC0, 0x00, 0x80, 0x01, 0x80, 0x01, 0x00, 0x03, 0x00, 0x03,
+  0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06,
+  0x00, 0x03, 0x00, 0x03, 0x80, 0x01, 0x80, 0x01, 0xC0, 0x00, 0x60, 0x00, 0x20, 0x00, 0x00, 0x00,
+  /* 0x2A: '*' */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0xC0, 0x00,
+  0xD8, 0x06, 0xF8, 0x07, 0xE0, 0x01, 0x30, 0x03, 0x38, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x2B: '+' */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x80, 0x01,
+  0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0xFC, 0x3F, 0xFC, 0x3F, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01,
+  0x80, 0x01, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x2C: ',' */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x80, 0x01, 0x80, 0x01, 0x00, 0x01, 0x00, 0x01, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x2D: '-' */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x07, 0xE0, 0x07, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x2E: '.' */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x2F: '/' */
+  0x00, 0x00, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x03, 0x00, 0x03,
+  0x00, 0x03, 0x80, 0x03, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00,
+  0x60, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x30: '0' */
+  0x00, 0x00, 0xE0, 0x03, 0xF0, 0x07, 0x38, 0x0E, 0x18, 0x0C, 0x0C, 0x18, 0x0C, 0x18, 0x0C, 0x18,
+  0x0C, 0x18, 0x0C, 0x18, 0x0C, 0x18, 0x0C, 0x18, 0x0C, 0x18, 0x0C, 0x18, 0x18, 0x0C, 0x38, 0x0E,
+  0xF0, 0x07, 0xE0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x31: '1' */
+  0x00, 0x00, 0x00, 0x01, 0x80, 0x01, 0xC0, 0x01, 0xF0, 0x01, 0x98, 0x01, 0x88, 0x01, 0x80, 0x01,
+  0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01,
+  0x80, 0x01, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x32: '2' */
+  0x00, 0x00, 0xE0, 0x03, 0xF8, 0x0F, 0x18, 0x0C, 0x0C, 0x18, 0x0C, 0x18, 0x00, 0x18, 0x00, 0x18,
+  0x00, 0x0C, 0x00, 0x06, 0x00, 0x03, 0x80, 0x01, 0xC0, 0x00, 0x60, 0x00, 0x30, 0x00, 0x18, 0x00,
+  0xFC, 0x1F, 0xFC, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x33: '3' */
+  0x00, 0x00, 0xE0, 0x01, 0xF8, 0x07, 0x18, 0x0E, 0x0C, 0x0C, 0x0C, 0x0C, 0x00, 0x0C, 0x00, 0x06,
+  0xC0, 0x03, 0xC0, 0x07, 0x00, 0x0C, 0x00, 0x18, 0x00, 0x18, 0x0C, 0x18, 0x0C, 0x18, 0x18, 0x0C,
+  0xF8, 0x07, 0xE0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x34: '4' */
+  0x00, 0x00, 0x00, 0x0C, 0x00, 0x0E, 0x00, 0x0F, 0x00, 0x0F, 0x80, 0x0D, 0xC0, 0x0C, 0x60, 0x0C,
+  0x60, 0x0C, 0x30, 0x0C, 0x18, 0x0C, 0x0C, 0x0C, 0xFC, 0x3F, 0xFC, 0x3F, 0x00, 0x0C, 0x00, 0x0C,
+  0x00, 0x0C, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x35: '5' */
+  0x00, 0x00, 0xF8, 0x0F, 0xF8, 0x0F, 0x18, 0x00, 0x18, 0x00, 0x0C, 0x00, 0xEC, 0x03, 0xFC, 0x07,
+  0x1C, 0x0E, 0x00, 0x1C, 0x00, 0x18, 0x00, 0x18, 0x00, 0x18, 0x0C, 0x18, 0x1C, 0x0C, 0x18, 0x0E,
+  0xF8, 0x07, 0xE0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x36: '6' */
+  0x00, 0x00, 0xC0, 0x07, 0xF0, 0x0F, 0x38, 0x1C, 0x18, 0x18, 0x18, 0x00, 0x0C, 0x00, 0xCC, 0x03,
+  0xEC, 0x0F, 0x3C, 0x0E, 0x1C, 0x1C, 0x0C, 0x18, 0x0C, 0x18, 0x0C, 0x18, 0x18, 0x1C, 0x38, 0x0E,
+  0xF0, 0x07, 0xE0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x37: '7' */
+  0x00, 0x00, 0xFC, 0x1F, 0xFC, 0x1F, 0x00, 0x0C, 0x00, 0x06, 0x00, 0x06, 0x00, 0x03, 0x80, 0x03,
+  0x80, 0x01, 0xC0, 0x01, 0xC0, 0x00, 0xE0, 0x00, 0x60, 0x00, 0x60, 0x00, 0x70, 0x00, 0x30, 0x00,
+  0x30, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x38: '8' */
+  0x00, 0x00, 0xE0, 0x03, 0xF0, 0x07, 0x38, 0x0E, 0x18, 0x0C, 0x18, 0x0C, 0x18, 0x0C, 0x38, 0x06,
+  0xF0, 0x07, 0xF0, 0x07, 0x18, 0x0C, 0x0C, 0x18, 0x0C, 0x18, 0x0C, 0x18, 0x0C, 0x18, 0x38, 0x0C,
+  0xF8, 0x0F, 0xE0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x39: '9' */
+  0x00, 0x00, 0xE0, 0x03, 0xF0, 0x07, 0x38, 0x0E, 0x1C, 0x0C, 0x0C, 0x18, 0x0C, 0x18, 0x0C, 0x18,
+  0x1C, 0x1C, 0x38, 0x1E, 0xF8, 0x1B, 0xE0, 0x19, 0x00, 0x18, 0x00, 0x0C, 0x00, 0x0C, 0x1C, 0x0E,
+  0xF8, 0x07, 0xF0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x3A: ':' */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x80, 0x01,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x80, 0x01, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x3B: ';' */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x80, 0x01,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x80, 0x01, 0x80, 0x01, 0x00, 0x01, 0x00, 0x01, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x3C: '<' */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x10, 0x00, 0x1C, 0x80, 0x0F, 0xE0, 0x03, 0xF8, 0x00, 0x18, 0x00, 0xF8, 0x00, 0xE0, 0x03,
+  0x80, 0x0F, 0x00, 0x1C, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x3D: '=' */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0xF8, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x3E: '>' */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x08, 0x00, 0x38, 0x00, 0xF0, 0x01, 0xC0, 0x07, 0x00, 0x1F, 0x00, 0x18, 0x00, 0x1F, 0xC0, 0x07,
+  0xF0, 0x01, 0x38, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x3F: '?' */
+  0x00, 0x00, 0xE0, 0x03, 0xF8, 0x0F, 0x18, 0x0C, 0x0C, 0x18, 0x0C, 0x18, 0x00, 0x18, 0x00, 0x0C,
+  0x00, 0x06, 0x00, 0x03, 0x80, 0x01, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0xC0, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x40: '@' */
+  0x00, 0x00, 0x00, 0x00, 0xE0, 0x07, 0x18, 0x18, 0x04, 0x20, 0xC2, 0x29, 0x22, 0x4A, 0x11, 0x44,
+  0x09, 0x44, 0x09, 0x44, 0x09, 0x44, 0x09, 0x22, 0x11, 0x13, 0xE2, 0x0C, 0x02, 0x40, 0x04, 0x20,
+  0x18, 0x18, 0xE0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x41: 'A' */
+  0x00, 0x00, 0x80, 0x03, 0x80, 0x03, 0xC0, 0x06, 0xC0, 0x06, 0xC0, 0x06, 0x60, 0x0C, 0x60, 0x0C,
+  0x30, 0x18, 0x30, 0x18, 0x30, 0x18, 0xF8, 0x3F, 0xF8, 0x3F, 0x1C, 0x70, 0x0C, 0x60, 0x0C, 0x60,
+  0x06, 0xC0, 0x06, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x42: 'B' */
+  0x00, 0x00, 0xFC, 0x03, 0xFC, 0x0F, 0x0C, 0x0C, 0x0C, 0x18, 0x0C, 0x18, 0x0C, 0x18, 0x0C, 0x0C,
+  0xFC, 0x07, 0xFC, 0x0F, 0x0C, 0x18, 0x0C, 0x30, 0x0C, 0x30, 0x0C, 0x30, 0x0C, 0x30, 0x0C, 0x18,
+  0xFC, 0x1F, 0xFC, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x43: 'C' */
+  0x00, 0x00, 0xC0, 0x07, 0xF0, 0x1F, 0x38, 0x38, 0x1C, 0x30, 0x0C, 0x70, 0x06, 0x60, 0x06, 0x00,
+  0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x60, 0x0C, 0x70, 0x1C, 0x30,
+  0xF0, 0x1F, 0xE0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x44: 'D' */
+  0x00, 0x00, 0xFE, 0x03, 0xFE, 0x0F, 0x06, 0x0E, 0x06, 0x18, 0x06, 0x18, 0x06, 0x30, 0x06, 0x30,
+  0x06, 0x30, 0x06, 0x30, 0x06, 0x30, 0x06, 0x30, 0x06, 0x30, 0x06, 0x18, 0x06, 0x18, 0x06, 0x0E,
+  0xFE, 0x0F, 0xFE, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x45: 'E' */
+  0x00, 0x00, 0xFC, 0x3F, 0xFC, 0x3F, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00,
+  0xFC, 0x1F, 0xFC, 0x1F, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00,
+  0xFC, 0x3F, 0xFC, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x46: 'F' */
+  0x00, 0x00, 0xF8, 0x3F, 0xF8, 0x3F, 0x18, 0x00, 0x18, 0x00, 0x18, 0x00, 0x18, 0x00, 0x18, 0x00,
+  0xF8, 0x1F, 0xF8, 0x1F, 0x18, 0x00, 0x18, 0x00, 0x18, 0x00, 0x18, 0x00, 0x18, 0x00, 0x18, 0x00,
+  0x18, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x47: 'G' */
+  0x00, 0x00, 0xE0, 0x0F, 0xF8, 0x3F, 0x3C, 0x78, 0x0E, 0x60, 0x06, 0xE0, 0x07, 0xC0, 0x03, 0x00,
+  0x03, 0x00, 0x03, 0xFE, 0x03, 0xFE, 0x03, 0xC0, 0x07, 0xC0, 0x06, 0xC0, 0x0E, 0xC0, 0x3C, 0xF0,
+  0xF8, 0x3F, 0xE0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x48: 'H' */
+  0x00, 0x00, 0x0C, 0x30, 0x0C, 0x30, 0x0C, 0x30, 0x0C, 0x30, 0x0C, 0x30, 0x0C, 0x30, 0x0C, 0x30,
+  0xFC, 0x3F, 0xFC, 0x3F, 0x0C, 0x30, 0x0C, 0x30, 0x0C, 0x30, 0x0C, 0x30, 0x0C, 0x30, 0x0C, 0x30,
+  0x0C, 0x30, 0x0C, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x49: 'I' */
+  0x00, 0x00, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01,
+  0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01,
+  0x80, 0x01, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x4A: 'J' */
+  0x00, 0x00, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06,
+  0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x18, 0x06, 0x18, 0x06, 0x38, 0x07,
+  0xF0, 0x03, 0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x4B: 'K' */
+  0x00, 0x00, 0x06, 0x30, 0x06, 0x18, 0x06, 0x0C, 0x06, 0x06, 0x06, 0x03, 0x86, 0x01, 0xC6, 0x00,
+  0x66, 0x00, 0x76, 0x00, 0xDE, 0x00, 0x8E, 0x01, 0x06, 0x03, 0x06, 0x06, 0x06, 0x0C, 0x06, 0x18,
+  0x06, 0x30, 0x06, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x4C: 'L' */
+  0x00, 0x00, 0x18, 0x00, 0x18, 0x00, 0x18, 0x00, 0x18, 0x00, 0x18, 0x00, 0x18, 0x00, 0x18, 0x00,
+  0x18, 0x00, 0x18, 0x00, 0x18, 0x00, 0x18, 0x00, 0x18, 0x00, 0x18, 0x00, 0x18, 0x00, 0x18, 0x00,
+  0xF8, 0x1F, 0xF8, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x4D: 'M' */
+  0x00, 0x00, 0x0E, 0xE0, 0x1E, 0xF0, 0x1E, 0xF0, 0x1E, 0xF0, 0x36, 0xD8, 0x36, 0xD8, 0x36, 0xD8,
+  0x36, 0xD8, 0x66, 0xCC, 0x66, 0xCC, 0x66, 0xCC, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6,
+  0x86, 0xC3, 0x86, 0xC3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x4E: 'N' */
+  0x00, 0x00, 0x0C, 0x30, 0x1C, 0x30, 0x3C, 0x30, 0x3C, 0x30, 0x6C, 0x30, 0x6C, 0x30, 0xCC, 0x30,
+  0xCC, 0x30, 0x8C, 0x31, 0x0C, 0x33, 0x0C, 0x33, 0x0C, 0x36, 0x0C, 0x36, 0x0C, 0x3C, 0x0C, 0x3C,
+  0x0C, 0x38, 0x0C, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x4F: 'O' */
+  0x00, 0x00, 0xE0, 0x07, 0xF8, 0x1F, 0x1C, 0x38, 0x0E, 0x70, 0x06, 0x60, 0x03, 0xC0, 0x03, 0xC0,
+  0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0x06, 0x60, 0x0E, 0x70, 0x1C, 0x38,
+  0xF8, 0x1F, 0xE0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x50: 'P' */
+  0x00, 0x00, 0xFC, 0x0F, 0xFC, 0x1F, 0x0C, 0x38, 0x0C, 0x30, 0x0C, 0x30, 0x0C, 0x30, 0x0C, 0x30,
+  0x0C, 0x18, 0xFC, 0x1F, 0xFC, 0x07, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00,
+  0x0C, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x51: 'Q' */
+  0x00, 0x00, 0xE0, 0x07, 0xF8, 0x1F, 0x1C, 0x38, 0x0E, 0x70, 0x06, 0x60, 0x03, 0xE0, 0x03, 0xC0,
+  0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0x07, 0xE0, 0x06, 0x63, 0x0E, 0x3F, 0x1C, 0x3C,
+  0xF8, 0x3F, 0xE0, 0xF7, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x52: 'R' */
+  0x00, 0x00, 0xFE, 0x0F, 0xFE, 0x1F, 0x06, 0x38, 0x06, 0x30, 0x06, 0x30, 0x06, 0x30, 0x06, 0x38,
+  0xFE, 0x1F, 0xFE, 0x07, 0x06, 0x03, 0x06, 0x06, 0x06, 0x0C, 0x06, 0x18, 0x06, 0x18, 0x06, 0x30,
+  0x06, 0x30, 0x06, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x53: 'S' */
+  0x00, 0x00, 0xE0, 0x03, 0xF8, 0x0F, 0x1C, 0x0C, 0x0C, 0x18, 0x0C, 0x18, 0x0C, 0x00, 0x1C, 0x00,
+  0xF8, 0x03, 0xE0, 0x0F, 0x00, 0x1E, 0x00, 0x38, 0x06, 0x30, 0x06, 0x30, 0x0E, 0x30, 0x1C, 0x1C,
+  0xF8, 0x0F, 0xE0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x54: 'T' */
+  0x00, 0x00, 0xFE, 0x7F, 0xFE, 0x7F, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01,
+  0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01,
+  0x80, 0x01, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x55: 'U' */
+  0x00, 0x00, 0x0C, 0x30, 0x0C, 0x30, 0x0C, 0x30, 0x0C, 0x30, 0x0C, 0x30, 0x0C, 0x30, 0x0C, 0x30,
+  0x0C, 0x30, 0x0C, 0x30, 0x0C, 0x30, 0x0C, 0x30, 0x0C, 0x30, 0x0C, 0x30, 0x0C, 0x30, 0x18, 0x18,
+  0xF8, 0x1F, 0xE0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x56: 'V' */
+  0x00, 0x00, 0x03, 0x60, 0x06, 0x30, 0x06, 0x30, 0x06, 0x30, 0x0C, 0x18, 0x0C, 0x18, 0x0C, 0x18,
+  0x18, 0x0C, 0x18, 0x0C, 0x38, 0x0E, 0x30, 0x06, 0x30, 0x06, 0x70, 0x07, 0x60, 0x03, 0x60, 0x03,
+  0xC0, 0x01, 0xC0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x57: 'W' */
+  0x00, 0x00, 0x03, 0x60, 0xC3, 0x61, 0xC3, 0x61, 0xC3, 0x61, 0x66, 0x33, 0x66, 0x33, 0x66, 0x33,
+  0x66, 0x33, 0x66, 0x33, 0x66, 0x33, 0x6C, 0x1B, 0x6C, 0x1B, 0x6C, 0x1B, 0x2C, 0x1A, 0x3C, 0x1E,
+  0x38, 0x0E, 0x38, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x58: 'X' */
+  0x00, 0x00, 0x0F, 0xE0, 0x0C, 0x70, 0x18, 0x30, 0x30, 0x18, 0x70, 0x0C, 0x60, 0x0E, 0xC0, 0x07,
+  0x80, 0x03, 0x80, 0x03, 0xC0, 0x03, 0xE0, 0x06, 0x70, 0x0C, 0x30, 0x1C, 0x18, 0x18, 0x0C, 0x30,
+  0x0E, 0x60, 0x07, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x59: 'Y' */
+  0x00, 0x00, 0x03, 0xC0, 0x06, 0x60, 0x0C, 0x30, 0x1C, 0x38, 0x38, 0x18, 0x30, 0x0C, 0x60, 0x06,
+  0xE0, 0x07, 0xC0, 0x03, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01,
+  0x80, 0x01, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x5A: 'Z' */
+  0x00, 0x00, 0xFC, 0x7F, 0xFC, 0x7F, 0x00, 0x60, 0x00, 0x30, 0x00, 0x18, 0x00, 0x0C, 0x00, 0x06,
+  0x00, 0x03, 0x80, 0x01, 0xC0, 0x00, 0x60, 0x00, 0x30, 0x00, 0x18, 0x00, 0x0C, 0x00, 0x06, 0x00,
+  0xFE, 0x7F, 0xFE, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x5B: '[' */
+  0x00, 0x00, 0xE0, 0x03, 0xE0, 0x03, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00,
+  0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00,
+  0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0xE0, 0x03, 0xE0, 0x03, 0x00, 0x00,
+  /* 0x5C: '\' */
+  0x00, 0x00, 0x30, 0x00, 0x30, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0xC0, 0x00, 0xC0, 0x00,
+  0xC0, 0x00, 0xC0, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03,
+  0x00, 0x06, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x5D: ']' */
+  0x00, 0x00, 0xE0, 0x03, 0xE0, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03,
+  0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03,
+  0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0xE0, 0x03, 0xE0, 0x03, 0x00, 0x00,
+  /* 0x5E: '^' */
+  0x00, 0x00, 0x00, 0x00, 0xC0, 0x01, 0xC0, 0x01, 0x60, 0x03, 0x60, 0x03, 0x60, 0x03, 0x30, 0x06,
+  0x30, 0x06, 0x18, 0x0C, 0x18, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x5F: '_' */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x60: ''' */
+  0x00, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x61: 'a' */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x03, 0xF8, 0x07,
+  0x1C, 0x0C, 0x0C, 0x0C, 0x00, 0x0F, 0xF0, 0x0F, 0xF8, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x1C, 0x0F,
+  0xF8, 0x0F, 0xF0, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x62: 'b' */
+  0x00, 0x00, 0x18, 0x00, 0x18, 0x00, 0x18, 0x00, 0x18, 0x00, 0x18, 0x00, 0xD8, 0x03, 0xF8, 0x0F,
+  0x38, 0x0C, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x38, 0x0C,
+  0xF8, 0x0F, 0xD8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x63: 'c' */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0xF0, 0x07,
+  0x30, 0x0E, 0x18, 0x0C, 0x18, 0x00, 0x18, 0x00, 0x18, 0x00, 0x18, 0x00, 0x18, 0x0C, 0x30, 0x0E,
+  0xF0, 0x07, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x64: 'd' */
+  0x00, 0x00, 0x00, 0x18, 0x00, 0x18, 0x00, 0x18, 0x00, 0x18, 0x00, 0x18, 0xC0, 0x1B, 0xF0, 0x1F,
+  0x30, 0x1C, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x30, 0x1C,
+  0xF0, 0x1F, 0xC0, 0x1B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x65: 'e' */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0xF0, 0x0F,
+  0x30, 0x0C, 0x18, 0x18, 0xF8, 0x1F, 0xF8, 0x1F, 0x18, 0x00, 0x18, 0x00, 0x38, 0x18, 0x30, 0x1C,
+  0xF0, 0x0F, 0xC0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x66: 'f' */
+  0x00, 0x00, 0x80, 0x0F, 0xC0, 0x0F, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xF0, 0x07, 0xF0, 0x07,
+  0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00,
+  0xC0, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x67: 'g' */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x0D, 0xF8, 0x0F,
+  0x18, 0x0E, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x18, 0x0E,
+  0xF8, 0x0F, 0xE0, 0x0D, 0x00, 0x0C, 0x0C, 0x0C, 0x1C, 0x06, 0xF8, 0x07, 0xF0, 0x01, 0x00, 0x00,
+  /* 0x68: 'h' */
+  0x00, 0x00, 0x18, 0x00, 0x18, 0x00, 0x18, 0x00, 0x18, 0x00, 0x18, 0x00, 0xD8, 0x07, 0xF8, 0x0F,
+  0x38, 0x1C, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+  0x18, 0x18, 0x18, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x69: 'i' */
+  0x00, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0xC0, 0x00,
+  0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00,
+  0xC0, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x6A: 'j' */
+  0x00, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0xC0, 0x00,
+  0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00,
+  0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xF8, 0x00, 0x78, 0x00, 0x00, 0x00,
+  /* 0x6B: 'k' */
+  0x00, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x0C, 0x0C, 0x06,
+  0x0C, 0x03, 0x8C, 0x01, 0xCC, 0x00, 0x6C, 0x00, 0xFC, 0x00, 0x9C, 0x01, 0x8C, 0x03, 0x0C, 0x03,
+  0x0C, 0x06, 0x0C, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x6C: 'l' */
+  0x00, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00,
+  0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00,
+  0xC0, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x6D: 'm' */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x3C, 0xFF, 0x7E,
+  0xC7, 0xE3, 0x83, 0xC1, 0x83, 0xC1, 0x83, 0xC1, 0x83, 0xC1, 0x83, 0xC1, 0x83, 0xC1, 0x83, 0xC1,
+  0x83, 0xC1, 0x83, 0xC1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x6E: 'n' */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x98, 0x07, 0xF8, 0x0F,
+  0x38, 0x1C, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+  0x18, 0x18, 0x18, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x6F: 'o' */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0xF0, 0x0F,
+  0x30, 0x0C, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x30, 0x0C,
+  0xF0, 0x0F, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x70: 'p' */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xD8, 0x03, 0xF8, 0x0F,
+  0x38, 0x0C, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x38, 0x0C,
+  0xF8, 0x0F, 0xD8, 0x03, 0x18, 0x00, 0x18, 0x00, 0x18, 0x00, 0x18, 0x00, 0x18, 0x00, 0x00, 0x00,
+  /* 0x71: 'q' */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x1B, 0xF0, 0x1F,
+  0x30, 0x1C, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x30, 0x1C,
+  0xF0, 0x1F, 0xC0, 0x1B, 0x00, 0x18, 0x00, 0x18, 0x00, 0x18, 0x00, 0x18, 0x00, 0x18, 0x00, 0x00,
+  /* 0x72: 'r' */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xB0, 0x07, 0xF0, 0x03,
+  0x70, 0x00, 0x30, 0x00, 0x30, 0x00, 0x30, 0x00, 0x30, 0x00, 0x30, 0x00, 0x30, 0x00, 0x30, 0x00,
+  0x30, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x73: 's' */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x03, 0xF0, 0x03,
+  0x38, 0x0E, 0x18, 0x0C, 0x38, 0x00, 0xF0, 0x03, 0xC0, 0x07, 0x00, 0x0C, 0x18, 0x0C, 0x38, 0x0E,
+  0xF0, 0x07, 0xE0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x74: 't' */
+  0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xF0, 0x07, 0xF0, 0x07,
+  0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00,
+  0xC0, 0x07, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x75: 'u' */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x18, 0x18,
+  0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x38, 0x1C,
+  0xF0, 0x1F, 0xE0, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x76: 'v' */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x18, 0x18, 0x0C,
+  0x18, 0x0C, 0x18, 0x0C, 0x30, 0x06, 0x30, 0x06, 0x30, 0x06, 0x60, 0x03, 0x60, 0x03, 0x60, 0x03,
+  0xC0, 0x01, 0xC0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x77: 'w' */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC1, 0x41, 0xC1, 0x41,
+  0xC3, 0x61, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x1C, 0x1C,
+  0x1C, 0x1C, 0x1C, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x78: 'x' */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x38, 0x38, 0x1C,
+  0x30, 0x0C, 0x60, 0x06, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0x03, 0xC0, 0x03, 0x60, 0x06, 0x30, 0x0C,
+  0x38, 0x1C, 0x1C, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x79: 'y' */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x30, 0x30, 0x18,
+  0x30, 0x18, 0x70, 0x18, 0x60, 0x0C, 0x60, 0x0C, 0xE0, 0x0C, 0xC0, 0x06, 0xC0, 0x06, 0x80, 0x03,
+  0x80, 0x03, 0x80, 0x03, 0x80, 0x01, 0x80, 0x01, 0xC0, 0x01, 0xF0, 0x00, 0x70, 0x00, 0x00, 0x00,
+  /* 0x7A: 'z' */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x1F, 0xFC, 0x1F,
+  0x00, 0x0C, 0x00, 0x06, 0x00, 0x03, 0x80, 0x01, 0xC0, 0x00, 0x60, 0x00, 0x30, 0x00, 0x18, 0x00,
+  0xFC, 0x1F, 0xFC, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x7B: '{' */
+  0x00, 0x00, 0x00, 0x03, 0x80, 0x01, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00,
+  0xC0, 0x00, 0x60, 0x00, 0x60, 0x00, 0x30, 0x00, 0x60, 0x00, 0x40, 0x00, 0xC0, 0x00, 0xC0, 0x00,
+  0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0x80, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00,
+  /* 0x7C: '|' */
+  0x00, 0x00, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01,
+  0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01,
+  0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x00, 0x00,
+  /* 0x7D: '}' */
+  0x00, 0x00, 0x60, 0x00, 0xC0, 0x00, 0xC0, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01,
+  0x80, 0x01, 0x00, 0x03, 0x00, 0x03, 0x00, 0x06, 0x00, 0x03, 0x00, 0x01, 0x80, 0x01, 0x80, 0x01,
+  0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0x80, 0x01, 0xC0, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x7E: '~' */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0xF0, 0x10, 0xF8, 0x1F, 0x08, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x7F: ' ' */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+  /* Special Symbols  starting at character 0x80 */
+  /* 0x80: Circle - Empty */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0x30, 0x0C, 0x08, 0x10,
+  0x04, 0x20, 0x04, 0x20, 0x02, 0x40, 0x02, 0x40, 0x02, 0x40, 0x02, 0x40, 0x02, 0x40, 0x04, 0x20,
+  0x04, 0x20, 0x08, 0x10, 0x30, 0x0C, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x81: Circle - Full */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x03, 0xF0, 0x0F, 0xF8, 0x1F,
+  0xFC, 0x3F, 0xFC, 0x3F, 0xFE, 0x7F, 0xFE, 0x7F, 0xFE, 0x7F, 0xFE, 0x7F, 0xFE, 0x7F, 0xFC, 0x3F,
+  0xFC, 0x3F, 0xF8, 0x1F, 0xF0, 0x0F, 0xC0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x82: Square - Empty */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x07,
+  0xF0, 0x0F, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0xF0, 0x0F,
+  0xE0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x83: Square - Full */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x07,
+  0xF0, 0x0F, 0xF8, 0x1F, 0xF8, 0x1F, 0xF8, 0x1F, 0xF8, 0x1F, 0xF8, 0x1F, 0xF8, 0x1F, 0xF0, 0x0F,
+  0xE0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x84: Up - Empty */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0xC0, 0x03, 0x60, 0x06, 0x30, 0x0C,
+  0x18, 0x18, 0x18, 0x18, 0xF8, 0x1F, 0xF8, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x85: Up - Full */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0xC0, 0x03, 0xE0, 0x07, 0xF0, 0x0F,
+  0xF8, 0x1F, 0xF8, 0x1F, 0xF8, 0x1F, 0xF8, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x86: Down - Empty */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x1F, 0xF8, 0x1F, 0x18, 0x18, 0x18, 0x18,
+  0x30, 0x0C, 0x60, 0x06, 0xC0, 0x03, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x87: Down - Full */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x1F, 0xF8, 0x1F, 0xF8, 0x1F, 0xF8, 0x1F,
+  0xF0, 0x0F, 0xE0, 0x07, 0xC0, 0x03, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x88: Left - Empty */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01,
+  0xF0, 0x01, 0x98, 0x01, 0x8C, 0x01, 0x86, 0x01, 0x86, 0x01, 0x8C, 0x01, 0x98, 0x01, 0xF0, 0x01,
+  0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x89: Left - Full */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x01,
+  0xF0, 0x01, 0xF8, 0x01, 0xFC, 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFC, 0x01, 0xF8, 0x01, 0xF0, 0x01,
+  0xE0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x8A: Right - Empty */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
+  0x80, 0x0F, 0x80, 0x19, 0x80, 0x31, 0x80, 0x61, 0x80, 0x61, 0x80, 0x31, 0x80, 0x19, 0x80, 0x0F,
+  0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x8B: Right - Full */
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
+  0x80, 0x0F, 0x80, 0x1F, 0x80, 0x3F, 0x80, 0x7F, 0x80, 0x7F, 0x80, 0x3F, 0x80, 0x1F, 0x80, 0x0F,
+  0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  /* 0x8C: Wait - Empty */
+  0x00, 0x00, 0xC0, 0x01, 0x20, 0x02, 0x20, 0x02, 0x40, 0x01, 0x30, 0x06, 0x08, 0x08, 0x08, 0x08,
+  0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x20, 0x02, 0x20, 0x02, 0x20, 0x02,
+  0x20, 0x02, 0x20, 0x02, 0x20, 0x02, 0x20, 0x02, 0x20, 0x02, 0x20, 0x02, 0x20, 0x02, 0x00, 0x00,
+  /* 0x8D: Wait - Full */
+  0x00, 0x00, 0xC0, 0x01, 0xE0, 0x03, 0xE0, 0x03, 0xC0, 0x01, 0xF0, 0x07, 0xD8, 0x0D, 0xD8, 0x0D,
+  0xD8, 0x0D, 0xD8, 0x0D, 0xD8, 0x0D, 0xD8, 0x0D, 0xD8, 0x0D, 0x60, 0x03, 0x60, 0x03, 0x60, 0x03,
+  0x60, 0x03, 0x60, 0x03, 0x60, 0x03, 0x60, 0x03, 0x60, 0x03, 0x60, 0x03, 0x60, 0x03, 0x00, 0x00,
+  /* 0x8E: Walk - Empty */
+  0x00, 0x00, 0xC0, 0x01, 0x20, 0x02, 0x20, 0x02, 0x40, 0x01, 0x30, 0x06, 0x08, 0x08, 0x08, 0x08,
+  0x08, 0x08, 0x04, 0x10, 0x02, 0x20, 0x02, 0x20, 0x40, 0x01, 0x20, 0x02, 0x20, 0x02, 0x10, 0x04,
+  0x08, 0x08, 0x08, 0x08, 0x04, 0x10, 0x04, 0x10, 0x04, 0x20, 0x04, 0x40, 0x00, 0x00, 0x00, 0x00,
+  /* 0x8F: Walk - Full */
+  0x00, 0x00, 0xC0, 0x01, 0xE0, 0x03, 0xE0, 0x03, 0xC0, 0x01, 0xF0, 0x07, 0xD8, 0x0D, 0xD8, 0x0D,
+  0xD8, 0x0D, 0xCC, 0x19, 0xC6, 0x31, 0xC2, 0x61, 0xC0, 0x01, 0x60, 0x03, 0x60, 0x03, 0x70, 0x06,
+  0x38, 0x0C, 0x18, 0x0C, 0x0C, 0x18, 0x0C, 0x18, 0x0C, 0x30, 0x0C, 0x60, 0x00, 0x00, 0x00, 0x00,
+};
+
+GLCD_FONT GLCD_Font_6x8 = {
+  6,                                    ///< Character width
+  8,                                    ///< Character height
+  32,                                   ///< Character offset
+  112,                                  ///< Character count
+  Font_6x8_h                            ///< Characters bitmaps
+};
+
+GLCD_FONT GLCD_Font_16x24 = {
+  16,                                   ///< Character width
+  24,                                   ///< Character height
+  32,                                   ///< Character offset
+  112,                                  ///< Character count
+  Font_16x24_h                          ///< Characters bitmaps
+};

CMSIS/Pack/Example/Boards/Keil/MCB1800/Common/GLCD_MCB1800.c

@@ -0,0 +1,660 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Name:    GLCD_MCB1800.c
+ * Purpose: Graphic LCD interface (240x320 pixels) for Graphic LCD with
+ *          SPI interface (in RGB mode) for MCB1800 evaluation board
+ * Rev.:    1.00
+ *----------------------------------------------------------------------------*/
+
+#include "LPC18xx.h"
+#include "SCU_LPC18xx.h"
+#include "GPIO_LPC18xx.h"
+#include "GLCD_Config.h"
+#include "Board_GLCD.h"
+#include "Driver_SPI.h"
+
+/* GLCD pins:
+   - LCD_VD19  : P4_1
+   - LCD_VD3   : P4_2
+   - LCD_VSYNC : P4_5
+   - LCD_EN    : P4_6
+   - LCD_DOTCLK: P4_7
+   - LCD_VD11  : P4_9
+   - LCD_VD10  : P4_10
+   - LCD_BL_EN : P7_0  = GPIO3[8]
+   - LCD_HSYNC : P7_6
+   - LCD_VD12  : P8_3
+   - LCD_VD7   : P8_4
+   - LCD_VD6   : P8_5
+   - LCD_VD5   : P8_6
+   - LCD_VD4   : P8_7
+   - LCD_VD23  : PB_0
+   - LCD_VD22  : PB_1
+   - LCD_VD21  : PB_2
+   - LCD_VD20  : PB_3
+   - LCD_VD15  : PB_4
+   - LCD_VD14  : PB_5
+   - LCD_VD13  : PB_6             */
+
+#define     GLCD_PIN_NUMBER             21
+
+/* GLCD GPIO definitions */
+const GPIO_ID GLCD_GPIO[] = {
+  { 3, 8 }          /* Only backlight control is used as GPIO pin */
+};
+
+/* GLCD pin definitions */
+const PIN_ID GLCD_PIN[] = {
+  {  4,  1, (SCU_CFG_MODE_FUNC5 | SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN | SCU_PIN_CFG_HIGH_SPEED_SLEW_RATE_EN)},
+  {  4,  2, (SCU_CFG_MODE_FUNC2 | SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN | SCU_PIN_CFG_HIGH_SPEED_SLEW_RATE_EN)},
+  {  4,  5, (SCU_CFG_MODE_FUNC2 | SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN | SCU_PIN_CFG_HIGH_SPEED_SLEW_RATE_EN)},
+  {  4,  6, (SCU_CFG_MODE_FUNC2 | SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN | SCU_PIN_CFG_HIGH_SPEED_SLEW_RATE_EN)},
+  {  4,  7, (SCU_CFG_MODE_FUNC0 | SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN | SCU_PIN_CFG_HIGH_SPEED_SLEW_RATE_EN)},
+  {  4,  9, (SCU_CFG_MODE_FUNC2 | SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN | SCU_PIN_CFG_HIGH_SPEED_SLEW_RATE_EN)},
+  {  4, 10, (SCU_CFG_MODE_FUNC2 | SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN | SCU_PIN_CFG_HIGH_SPEED_SLEW_RATE_EN)},
+  {  7,  0, (SCU_CFG_MODE_FUNC0 | SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN | SCU_PIN_CFG_HIGH_SPEED_SLEW_RATE_EN)},
+  {  7,  6, (SCU_CFG_MODE_FUNC3 | SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN | SCU_PIN_CFG_HIGH_SPEED_SLEW_RATE_EN)},
+  {  8,  3, (SCU_CFG_MODE_FUNC3 | SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN | SCU_PIN_CFG_HIGH_SPEED_SLEW_RATE_EN)},
+  {  8,  4, (SCU_CFG_MODE_FUNC3 | SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN | SCU_PIN_CFG_HIGH_SPEED_SLEW_RATE_EN)},
+  {  8,  5, (SCU_CFG_MODE_FUNC3 | SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN | SCU_PIN_CFG_HIGH_SPEED_SLEW_RATE_EN)},
+  {  8,  6, (SCU_CFG_MODE_FUNC3 | SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN | SCU_PIN_CFG_HIGH_SPEED_SLEW_RATE_EN)},
+  {  8,  7, (SCU_CFG_MODE_FUNC3 | SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN | SCU_PIN_CFG_HIGH_SPEED_SLEW_RATE_EN)},
+  { 11,  0, (SCU_CFG_MODE_FUNC2 | SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN | SCU_PIN_CFG_HIGH_SPEED_SLEW_RATE_EN)},
+  { 11,  1, (SCU_CFG_MODE_FUNC2 | SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN | SCU_PIN_CFG_HIGH_SPEED_SLEW_RATE_EN)},
+  { 11,  2, (SCU_CFG_MODE_FUNC2 | SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN | SCU_PIN_CFG_HIGH_SPEED_SLEW_RATE_EN)},
+  { 11,  3, (SCU_CFG_MODE_FUNC2 | SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN | SCU_PIN_CFG_HIGH_SPEED_SLEW_RATE_EN)},
+  { 11,  4, (SCU_CFG_MODE_FUNC2 | SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN | SCU_PIN_CFG_HIGH_SPEED_SLEW_RATE_EN)},
+  { 11,  5, (SCU_CFG_MODE_FUNC2 | SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN | SCU_PIN_CFG_HIGH_SPEED_SLEW_RATE_EN)},
+  { 11,  6, (SCU_CFG_MODE_FUNC2 | SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN | SCU_PIN_CFG_HIGH_SPEED_SLEW_RATE_EN)}
+};
+
+/* SPI Interface: SSP0
+ 
+   PINS: 
+   - CS  = PF_1 (GPIO7[16])
+   - SCK = PF_0 (SCK0)
+   - SDO = PF_2 (MISO0)
+   - SDI = PF_3 (MOSI0)
+*/
+
+/* SPI Driver */
+extern ARM_DRIVER_SPI         Driver_SPI0;
+#define ptrSPI              (&Driver_SPI0)
+
+#define SDRAM_BASE_ADDR       0x28000000
+
+/*********************** Hardware specific configuration **********************/
+
+#define SPI_START            (0x70)     /* Start byte for SPI transfer        */
+#define SPI_RD               (0x01)     /* WR bit 1 within start              */
+#define SPI_WR               (0x00)     /* WR bit 0 within start              */
+#define SPI_DATA             (0x02)     /* RS bit 1 within start byte         */
+#define SPI_INDEX            (0x00)     /* RS bit 0 within start byte         */
+
+/* SCU pin configuration definitions */
+#define LCD_PIN_SET          (SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN | SCU_PIN_CFG_HIGH_SPEED_SLEW_RATE_EN)
+#define LCD_NPR_SET          (SCU_PIN_CFG_HIGH_SPEED_SLEW_RATE_EN | SCU_PIN_CFG_PULLUP_DIS)
+
+/* Clock Control Unit register bits */
+#define CCU_CLK_CFG_RUN      (1 << 0)
+#define CCU_CLK_CFG_AUTO     (1 << 1)
+#define CCU_CLK_STAT_RUN     (1 << 0)
+
+/*---------------------------- Global variables ------------------------------*/
+
+static uint16_t   frame_buf[GLCD_WIDTH*GLCD_HEIGHT]__attribute__((at(SDRAM_BASE_ADDR)));
+static uint16_t   foreground_color = GLCD_COLOR_BLACK;
+static uint16_t   background_color = GLCD_COLOR_WHITE;
+static GLCD_FONT *active_font      = NULL;
+
+/************************ Local auxiliary functions ***************************/
+
+/**
+  \fn          void delay_ms (int ms)
+  \brief       Delay execution for a specified number of milliseconds
+  \param[in]   ms     number of while loop iterations
+*/
+static void delay_ms (int ms) {
+  ms *= (SystemCoreClock/10000);
+  while (ms--) { __nop(); __nop(); __nop(); __nop(); __nop(); __nop(); }
+}
+
+/**
+  \fn          void wr_reg (uint8_t reg, uint8_t val)
+  \brief       Write  value to LCD register
+  \param[in]   reg    register to write
+  \param[in]   val    value to write
+*/
+static void wr_reg (uint8_t reg, uint8_t val) {
+  uint8_t wr_data[2];
+
+  wr_data[0] = SPI_START | SPI_WR | SPI_INDEX;    // RS = 0, RW = 0
+  wr_data[1] = reg;
+  ptrSPI->Control(ARM_SPI_CONTROL_SS, ARM_SPI_SS_ACTIVE);
+  ptrSPI->Send   (wr_data, 2);
+  while (ptrSPI->GetStatus().busy);
+  ptrSPI->Control(ARM_SPI_CONTROL_SS, ARM_SPI_SS_INACTIVE);
+
+  wr_data[0] = SPI_START | SPI_WR | SPI_DATA;     // RS = 1, RW = 0
+  wr_data[1] = val;
+  ptrSPI->Control(ARM_SPI_CONTROL_SS, ARM_SPI_SS_ACTIVE);
+  ptrSPI->Send   (wr_data, 2);
+  while (ptrSPI->GetStatus().busy);
+  ptrSPI->Control(ARM_SPI_CONTROL_SS, ARM_SPI_SS_INACTIVE);
+}
+
+/**
+  \fn          uint8_t rd_reg (uint8_t reg)
+  \brief       Read value from LCD register
+  \param[in]   reg    register to read
+  \return      Read register value
+*/
+#if 0
+static uint8_t rd_reg (uint8_t reg) {
+  uint8_t  wr_data[2];
+  uint8_t  rd_data;
+
+  wr_data[0] = SPI_START | SPI_WR | SPI_INDEX;    // RS = 0, RW = 0
+  wr_data[1] = reg;
+  ptrSPI->Control(ARM_SPI_CONTROL_SS, ARM_SPI_SS_ACTIVE);
+  ptrSPI->Send   (wr_data, 2);
+  while (ptrSPI->GetStatus().busy);
+  ptrSPI->Control(ARM_SPI_CONTROL_SS, ARM_SPI_SS_INACTIVE);
+
+  wr_data[0] = SPI_START | SPI_RD | SPI_DATA;     // RS = 1, RW = 1
+  ptrSPI->Control(ARM_SPI_CONTROL_SS, ARM_SPI_SS_ACTIVE);
+  ptrSPI->Send   (wr_data, 1);
+  while (ptrSPI->GetStatus().busy);
+  ptrSPI->Receive  (&rd_data, 1);
+  while (ptrSPI->GetStatus().busy);
+  ptrSPI->Control(ARM_SPI_CONTROL_SS, ARM_SPI_SS_INACTIVE);
+  return (rd_data);
+}
+#endif
+
+
+/************************ Module functions ************************************/
+
+/**
+  \fn          int32_t GLCD_Initialize (void)
+  \brief       Initialize Graphic LCD
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t GLCD_Initialize (void) {
+  uint32_t i;
+
+  SystemCoreClockUpdate();
+
+  /* Initialize and configure SPI */
+  ptrSPI->Initialize  (NULL);
+  ptrSPI->PowerControl(ARM_POWER_FULL);
+  ptrSPI->Control     (ARM_SPI_MODE_MASTER | ARM_SPI_CPOL1_CPHA1 | ARM_SPI_MSB_LSB | ARM_SPI_SS_MASTER_SW | ARM_SPI_DATA_BITS(8), 10000000);
+
+  LPC_CGU->BASE_LCD_CLK  = (1    << 11) |
+                           (0x10 << 24) ; /* IDIVE is clock source            */
+
+  /* Enable LCD clock */
+  LPC_CCU1->CLK_M3_LCD_CFG   = CCU_CLK_CFG_AUTO | CCU_CLK_CFG_RUN;
+  while (!(LPC_CCU1->CLK_M3_LCD_STAT & CCU_CLK_STAT_RUN));
+ 
+  /* Enable GPIO Clock */
+  GPIO_PortClock (1);
+
+  /* Configure pins */
+  for (i = 0; i < GLCD_PIN_NUMBER; i++)
+    SCU_PinConfigure (GLCD_PIN[i].port,  GLCD_PIN[i].num,  GLCD_PIN[i].config_val);
+  /* Configure backlight pin GPIO mode */
+  GPIO_SetDir        (GLCD_GPIO[0].port, GLCD_GPIO[0].num, GPIO_DIR_OUTPUT);
+
+  /* LCD with HX8347-D LCD Controller */
+  /* Driving ability settings */
+  wr_reg(0xEA, 0x00);                   /* Power control internal used (1)    */
+  wr_reg(0xEB, 0x20);                   /* Power control internal used (2)    */
+  wr_reg(0xEC, 0x0C);                   /* Source control internal used (1)   */
+  wr_reg(0xED, 0xC7);                   /* Source control internal used (2)   */
+  wr_reg(0xE8, 0x38);                   /* Source output period Normal mode   */
+  wr_reg(0xE9, 0x10);                   /* Source output period Idle mode     */
+  wr_reg(0xF1, 0x01);                   /* RGB 18-bit interface ;0x0110       */
+  wr_reg(0xF2, 0x10);
+
+  /* Adjust Gamma Curve */
+  wr_reg(0x40, 0x01);
+  wr_reg(0x41, 0x00);
+  wr_reg(0x42, 0x00);
+  wr_reg(0x43, 0x10);
+  wr_reg(0x44, 0x0E);
+  wr_reg(0x45, 0x24);
+  wr_reg(0x46, 0x04);
+  wr_reg(0x47, 0x50);
+  wr_reg(0x48, 0x02);
+  wr_reg(0x49, 0x13);
+  wr_reg(0x4A, 0x19);
+  wr_reg(0x4B, 0x19);
+  wr_reg(0x4C, 0x16);
+
+  wr_reg(0x50, 0x1B);
+  wr_reg(0x51, 0x31);
+  wr_reg(0x52, 0x2F);
+  wr_reg(0x53, 0x3F);
+  wr_reg(0x54, 0x3F);
+  wr_reg(0x55, 0x3E);
+  wr_reg(0x56, 0x2F);
+  wr_reg(0x57, 0x7B);
+  wr_reg(0x58, 0x09);
+  wr_reg(0x59, 0x06);
+  wr_reg(0x5A, 0x06);
+  wr_reg(0x5B, 0x0C);
+  wr_reg(0x5C, 0x1D);
+  wr_reg(0x5D, 0xCC);
+
+  /* Power voltage setting */
+  wr_reg(0x1B, 0x1B);
+  wr_reg(0x1A, 0x01);
+  wr_reg(0x24, 0x2F);
+  wr_reg(0x25, 0x57);
+  wr_reg(0x23, 0x88);
+
+  /* Power on setting */
+  wr_reg(0x18, 0x36);                   /* Internal oscillator frequency adj  */
+  wr_reg(0x19, 0x01);                   /* Enable internal oscillator         */
+  wr_reg(0x01, 0x00);                   /* Normal mode, no scrool             */
+  wr_reg(0x1F, 0x88);                   /* Power control 6 - DDVDH Off        */
+  delay_ms (20);
+  wr_reg(0x1F, 0x82);                   /* Power control 6 - Step-up: 3 x VCI */
+  delay_ms (5);
+  wr_reg(0x1F, 0x92);                   /* Power control 6 - Step-up: On      */
+  delay_ms (5);
+  wr_reg(0x1F, 0xD2);                   /* Power control 6 - VCOML active     */
+  delay_ms (5);
+
+  /* Color selection */
+  wr_reg(0x17, 0x55);                   /* RGB, System interface: 16 Bit/Pixel*/
+  wr_reg(0x00, 0x00);                   /* Scrolling off, no standby          */
+
+  /* Interface config */
+  wr_reg(0x2F, 0x11);                   /* LCD Drive: 1-line inversion        */
+  wr_reg(0x31, 0x02);                   /* Value for SPI: 0x02, RBG: 0x02     */
+  wr_reg(0x32, 0x00);                   /* DPL=0, HSPL=0, VSPL=0, EPL=0       */
+
+  /* Display on setting */
+  wr_reg(0x28, 0x38);                   /* PT(0,0) active, VGL/VGL            */
+  delay_ms (20);
+  wr_reg(0x28, 0x3C);                   /* Display active, VGL/VGL            */
+
+  /* Miror and Swap:     MY           |         MX           |          MV         |    ML    |    BGR       */
+  wr_reg (0x16, ((GLCD_MIRROR_Y << 7) | (GLCD_MIRROR_X << 6) | (GLCD_SWAP_XY << 5) | (0 << 4) | (0 << 3)));
+
+  /* Display scrolling settings */
+  wr_reg(0x0E, 0x00);                   /* TFA MSB                            */
+  wr_reg(0x0F, 0x00);                   /* TFA LSB                            */
+  wr_reg(0x10, 320 >> 8);               /* VSA MSB                            */
+  wr_reg(0x11, 320 &  0xFF);            /* VSA LSB                            */
+  wr_reg(0x12, 0x00);                   /* BFA MSB                            */
+  wr_reg(0x13, 0x00);                   /* BFA LSB                            */
+
+  /* Configure LCD controller */
+  LPC_RGU->RESET_CTRL0 = (1U << 16);
+  while ((LPC_RGU->RESET_ACTIVE_STATUS0 & (1U << 16)) == 0);
+
+  LPC_LCD->CTRL &= ~(1 << 0);           /* Disable LCD                        */
+  LPC_LCD->INTMSK = 0;                  /* Disable all interrupts             */
+
+  LPC_LCD->UPBASE = SDRAM_BASE_ADDR;
+
+  LPC_LCD->TIMH  = (7    << 24) |       /* Horizontal back porch              */
+                   (3    << 16) |       /* Horizontal front porch             */
+                   (3    <<  8) |       /* Horizontal sync pulse width        */
+                   (14   <<  2) ;       /* Pixels-per-line                    */
+  LPC_LCD->TIMV  = (3    << 24) |       /* Vertical back porch                */
+                   (2    << 16) |       /* Vertical front porch               */
+                   (3    << 10) |       /* Vertical sync pulse width          */
+                   (319  <<  0) ;       /* Lines per panel                    */
+  LPC_LCD->POL   = (1    << 26) |       /* Bypass pixel clock divider         */
+                   (239  << 16) |       /* Clocks per line: num of LCDCLKs    */
+                   (1    << 13) |       /* Invert panel clock                 */
+                   (1    << 12) |       /* Invert HSYNC                       */
+                   (1    << 11) ;       /* Invert VSYNC                       */
+  LPC_LCD->LE    = (1    << 16) |       /* LCDLE Enabled: 1, Disabled: 0      */
+                   (9    <<  0) ;       /* Line-end delay: LCDCLK clocks - 1  */
+  LPC_LCD->CTRL  = (1    << 11) |       /* LCD Power Enable                   */
+                   (1    <<  5) |       /* 0 = STN display, 1: TFT display    */
+                   (6    <<  1) ;       /* Bits per pixel: 16bpp (5:6:5)      */
+
+  for (i = 0; i < 256; i++) {
+    LPC_LCD->PAL[i] = 0;                /* Clear palette                      */
+  }
+  LPC_LCD->CTRL |= (1 <<  0);           /* LCD enable                         */
+
+  /* Turn backlight on */
+  GPIO_PinWrite (GLCD_GPIO[0].port, GLCD_GPIO[0].num, 1);
+
+  return 0;
+}
+
+/**
+  \fn          int32_t GLCD_Uninitialize (void)
+  \brief       De-initialize Graphic LCD
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t GLCD_Uninitialize (void) {
+  uint32_t i;
+
+  /* Turn backlight off */
+  GPIO_PinWrite (GLCD_GPIO[0].port, GLCD_GPIO[0].num, 0);
+
+  /* Unconfigure pins */
+  for (i = 0; i < GLCD_PIN_NUMBER; i++)
+    SCU_PinConfigure (GLCD_PIN[i].port,  GLCD_PIN[i].num,  0);
+
+  return 0;
+}
+
+/**
+  \fn          int32_t GLCD_SetForegroundColor (uint32_t color)
+  \brief       Set foreground color
+  \param[in]   color  Color value
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t GLCD_SetForegroundColor (uint32_t color) {
+  foreground_color = color;
+  return 0;
+}
+
+/**
+  \fn          int32_t GLCD_SetBackgroundColor (uint32_t color)
+  \brief       Set background color
+  \param[in]   color  Color value
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t GLCD_SetBackgroundColor (uint32_t color) {
+  background_color = color;
+  return 0;
+}
+
+/**
+  \fn          int32_t GLCD_ClearScreen (void)
+  \brief       Clear screen (with active background color)
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t GLCD_ClearScreen (void) {
+  uint32_t  i;
+  uint16_t *ptr_frame_buf;
+
+  ptr_frame_buf = frame_buf;
+  for (i = 0; i < (GLCD_WIDTH * GLCD_HEIGHT); i++) {
+    *ptr_frame_buf++ = background_color;
+  }
+  return 0;
+}
+
+/**
+  \fn          int32_t GLCD_SetFont (GLCD_FONT *font)
+  \brief       Set active font
+  \param[in]   font   Pointer to font structure
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t GLCD_SetFont (GLCD_FONT *font) {
+  active_font = font;
+  return 0;
+}
+
+/**
+  \fn          int32_t GLCD_DrawPixel (uint32_t x, uint32_t y)
+  \brief       Draw pixel (in active foreground color)
+  \param[in]   x  x position in pixels (0 = left corner)
+  \param[in]   y  y position in pixels (0 = upper corner)
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t GLCD_DrawPixel (uint32_t x, uint32_t y) {
+  frame_buf[GLCD_SWAP_XY * (x * GLCD_HEIGHT + y) + (!GLCD_SWAP_XY) * (y * GLCD_WIDTH + x)] = foreground_color;
+  return 0;
+}
+
+/**
+  \fn          int32_t GLCD_DrawHLine (uint32_t x, uint32_t y, uint32_t length)
+  \brief       Draw horizontal line (in active foreground color)
+  \param[in]   x      Start x position in pixels (0 = left corner)
+  \param[in]   y      Start y position in pixels (0 = upper corner)
+  \param[in]   length Line length
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t GLCD_DrawHLine (uint32_t x, uint32_t y, uint32_t length) {
+  uint32_t dot;
+
+  dot = GLCD_SWAP_XY * (x * GLCD_HEIGHT + y) + (!GLCD_SWAP_XY) * (y * GLCD_WIDTH + x);
+  while (length--) { 
+    frame_buf[dot] = foreground_color;
+    dot += GLCD_SWAP_XY * GLCD_HEIGHT + (!GLCD_SWAP_XY);
+  }
+  return 0;
+}
+
+/**
+  \fn          int32_t GLCD_DrawVLine (uint32_t x, uint32_t y, uint32_t length)
+  \brief       Draw vertical line (in active foreground color)
+  \param[in]   x      Start x position in pixels (0 = left corner)
+  \param[in]   y      Start y position in pixels (0 = upper corner)
+  \param[in]   length Line length in pixels
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t GLCD_DrawVLine (uint32_t x, uint32_t y, uint32_t length) {
+  uint32_t dot;
+
+  dot = GLCD_SWAP_XY * (x * GLCD_HEIGHT + y) + (!GLCD_SWAP_XY) * (y * GLCD_WIDTH + x);
+  while (length--) { 
+    frame_buf[dot] = foreground_color;
+    dot += (!GLCD_SWAP_XY) * GLCD_WIDTH + (GLCD_SWAP_XY);
+  }
+  return 0;
+}
+
+/**
+  \fn          int32_t GLCD_DrawRectangle (uint32_t x, uint32_t y, uint32_t width, uint32_t height)
+  \brief       Draw rectangle (in active foreground color)
+  \param[in]   x      Start x position in pixels (0 = left corner)
+  \param[in]   y      Start y position in pixels (0 = upper corner)
+  \param[in]   width  Rectangle width in pixels
+  \param[in]   height Rectangle height in pixels
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t GLCD_DrawRectangle (uint32_t x, uint32_t y, uint32_t width, uint32_t height) {
+
+  GLCD_DrawHLine (x,         y,          width);
+  GLCD_DrawHLine (x,         y + height, width);
+  GLCD_DrawVLine (x,         y,          height);
+  GLCD_DrawVLine (x + width, y,          height);
+
+  return 0;
+}
+
+/**
+  \fn          int32_t GLCD_DrawChar (uint32_t x, uint32_t y, int32_t ch)
+  \brief       Draw character (in active foreground color)
+  \param[in]   x      x position in pixels (0 = left corner)
+  \param[in]   y      y position in pixels (0 = upper corner)
+  \param[in]   ch     Character
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t GLCD_DrawChar (uint32_t x, uint32_t y, int32_t ch) {
+  uint32_t i, j;
+  uint32_t wb, dot;
+  uint8_t *ptr_ch_bmp;
+
+  if (active_font == NULL) return -1;
+
+  ch        -= active_font->offset;
+  wb         = (active_font->width + 7)/8;
+  ptr_ch_bmp = (uint8_t *)active_font->bitmap + (ch * wb * active_font->height);
+  dot        = GLCD_SWAP_XY * (x * GLCD_HEIGHT + y) + (!GLCD_SWAP_XY) * (y * GLCD_WIDTH + x);
+
+  for (i = 0; i < active_font->height; i++) {
+    for (j = 0; j < active_font->width; j++) {
+      frame_buf[dot] = (((*ptr_ch_bmp >> (j & 7)) & 1) ? foreground_color : background_color);
+      dot += GLCD_SWAP_XY * GLCD_HEIGHT + (!GLCD_SWAP_XY);
+      if (((j & 7) == 7) && (j != (active_font->width - 1))) ptr_ch_bmp++;
+    }
+    dot = GLCD_SWAP_XY * (x * GLCD_HEIGHT + y + (i + 1)) + (!GLCD_SWAP_XY) * ((y + i + 1) * GLCD_WIDTH + x);
+    ptr_ch_bmp++;
+  }
+  return 0;
+}
+
+/**
+  \fn          int32_t GLCD_DrawString (uint32_t x, uint32_t y, const char *str)
+  \brief       Draw string (in active foreground color)
+  \param[in]   x      x position in pixels (0 = left corner)
+  \param[in]   y      y position in pixels (0 = upper corner)
+  \param[in]   str    Null-terminated String
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t GLCD_DrawString (uint32_t x, uint32_t y, const char *str) {
+
+  while (*str) { GLCD_DrawChar(x, y, *str++); x += active_font->width; }
+
+  return 0;
+}
+
+/**
+  \fn          int32_t GLCD_DrawBargraph (uint32_t x, uint32_t y, uint32_t width, uint32_t height, uint32_t val)
+  \brief       Draw bargraph (in active foreground color)
+  \param[in]   x      Start x position in pixels (0 = left corner)
+  \param[in]   y      Start y position in pixels (0 = upper corner)
+  \param[in]   width  Full bargraph width in pixels
+  \param[in]   height Full bargraph height in pixels
+  \param[in]   val    Active bargraph value (maximum value is 100)
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t GLCD_DrawBargraph (uint32_t x, uint32_t y, uint32_t width, uint32_t height, uint32_t val) {
+  int      i, j;
+  uint32_t dot;
+
+  val = (val * width) / 100;            /* Scale value                        */
+  dot = GLCD_SWAP_XY * (x * GLCD_HEIGHT + y) + (!GLCD_SWAP_XY) * (y * GLCD_WIDTH + x);
+
+  for (i = 0; i < height; i++) {
+    for (j = 0; j < width; j++) {
+      frame_buf[dot] = ((j >= val) ? background_color : foreground_color);
+      dot += GLCD_SWAP_XY * GLCD_HEIGHT + (!GLCD_SWAP_XY);
+    }
+    dot = GLCD_SWAP_XY * (x * GLCD_HEIGHT + y + (i + 1)) + (!GLCD_SWAP_XY) * ((y + i + 1) * GLCD_WIDTH + x);
+  }
+  return 0;
+}
+
+/**
+  \fn          int32_t GLCD_DrawBitmap (uint32_t x, uint32_t y, uint32_t width, uint32_t height, const uint8_t *bitmap)
+  \brief       Draw bitmap (bitmap from BMP file without header)
+  \param[in]   x      Start x position in pixels (0 = left corner)
+  \param[in]   y      Start y position in pixels (0 = upper corner)
+  \param[in]   width  Bitmap width in pixels
+  \param[in]   height Bitmap height in pixels
+  \param[in]   bitmap Bitmap data
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t GLCD_DrawBitmap (uint32_t x, uint32_t y, uint32_t width, uint32_t height, const uint8_t *bitmap) {
+  uint32_t  i, j;
+  uint32_t  dot;
+  uint16_t *ptr_bmp;
+
+  ptr_bmp = (uint16_t *)bitmap + (width * (height - 1));
+  dot     = GLCD_SWAP_XY * (x * GLCD_HEIGHT + y) + (!GLCD_SWAP_XY) * (y * GLCD_WIDTH + x);
+
+  for (i = 0; i < height; i++) {
+    for (j = 0; j < width; j++) {
+      frame_buf[dot] = *ptr_bmp++;
+      dot += GLCD_SWAP_XY * GLCD_HEIGHT + (!GLCD_SWAP_XY);
+    }
+    dot = GLCD_SWAP_XY * (x * GLCD_HEIGHT + y + (i + 1)) + (!GLCD_SWAP_XY) * ((y + i + 1) * GLCD_WIDTH + x);
+    ptr_bmp -= 2 * width;
+  }
+  return 0;
+}
+
+/**
+  \fn          int32_t GLCD_VScroll (uint32_t dy)
+  \brief       Scroll picture on display vertically
+  \param[in]   dy  Scroll size in pixels
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t GLCD_VScroll (uint32_t dy) {
+  uint32_t i, dif, len;
+
+  dif = GLCD_SWAP_XY * dy + (!GLCD_SWAP_XY) * (GLCD_WIDTH * dy);
+  len = GLCD_WIDTH * GLCD_HEIGHT - dif;
+  for (i = 0; i < len; i++) {
+    frame_buf[i] = frame_buf[i+dif];
+  }
+  for (; i < GLCD_WIDTH * GLCD_HEIGHT; i++) {
+    frame_buf[i] = background_color;
+  }
+  return 0;
+}
+
+/**
+  \fn          int32_t GLCD_FrameBufferAccess (bool enable)
+  \brief       Enable or disable direct access to FrameBuffer
+  \param[in]   enable Enable or disable request
+                - true (1): enable
+                - false(0): disable
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t  GLCD_FrameBufferAccess   (bool enable) {
+  /* Direct data access is used with direct access to frame buffer            */
+  return 0;
+}
+
+/**
+  \fn          uint32_t GLCD_FrameBufferAddress (void)
+  \brief       Retrieve FrameBuffer address
+  \returns     FrameBuffer address
+*/
+uint32_t GLCD_FrameBufferAddress (void) {
+  return ((uint32_t)frame_buf);
+}

CMSIS/Pack/Example/Boards/Keil/MCB1800/Common/Joystick_MCB1800.c

@@ -0,0 +1,110 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Name:    Joystick_MCB1800.c
+ * Purpose: Joystick interface for MCB1800 evaluation board
+ * Rev.:    1.00
+ *----------------------------------------------------------------------------*/
+
+include "LPC18xx.h"
+#include "GPIO_LPC18xx.h"
+#include "SCU_LPC18xx.h"
+#include "Board_Joystick.h"
+
+#define JOYSTICK_COUNT                 (5)
+
+/* Joystick pins:
+   - center: PC_9  = GPIO6[8]
+   - up:     PC_11 = GPIO6[10]
+   - down:   PC_12 = GPIO6[11]
+   - left:   PC_13 = GPIO6[12]
+   - right:  PC_14 = GPIO6[13] */
+
+/* Joystick GPIO definitions */
+const GPIO_ID JOYSTICK_GPIO[] = {
+  { 6,  8 },
+  { 6, 10 },
+  { 6, 11 },
+  { 6, 12 },
+  { 6, 13 }
+};
+
+/* Joystick pin definitions */
+const PIN_ID JOYSTICK_PIN[] = {
+  { 12,  9, (SCU_CFG_MODE_FUNC4 | SCU_SFS_EZI)},
+  { 12, 11, (SCU_CFG_MODE_FUNC4 | SCU_SFS_EZI)},
+  { 12, 12, (SCU_CFG_MODE_FUNC4 | SCU_SFS_EZI)},
+  { 12, 13, (SCU_CFG_MODE_FUNC4 | SCU_SFS_EZI)},
+  { 12, 14, (SCU_CFG_MODE_FUNC4 | SCU_SFS_EZI)}
+};
+
+
+/**
+  \fn          int32_t Joystick_Initialize (void)
+  \brief       Initialize joystick
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t Joystick_Initialize (void) {
+  uint32_t n;
+
+  /* Enable GPIO clock */
+  GPIO_PortClock     (1);
+
+  /* Configure pins */
+  for (n = 0; n < JOYSTICK_COUNT; n++) {
+    SCU_PinConfigure (JOYSTICK_PIN[n].port,  JOYSTICK_PIN[n].num,  JOYSTICK_PIN[n].config_val);
+    GPIO_SetDir      (JOYSTICK_GPIO[n].port, JOYSTICK_GPIO[n].num, GPIO_DIR_INPUT);
+  }
+  return 0;
+}
+
+/**
+  \fn          int32_t Joystick_Uninitialize (void)
+  \brief       De-initialize joystick
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t Joystick_Uninitialize (void) {
+  uint32_t n;
+
+  /* Unconfigure pins */
+  for (n = 0; n < JOYSTICK_COUNT; n++) {
+    SCU_PinConfigure (JOYSTICK_PIN[n].port,  JOYSTICK_PIN[n].num,  0);
+  }
+  return 0;
+}
+
+/**
+  \fn          uint32_t Joystick_GetState (void)
+  \brief       Get joystick state
+  \returns     Joystick state
+*/
+uint32_t Joystick_GetState (void) {
+  uint32_t val;
+
+  val  = 0;
+  if (!(GPIO_PinRead (JOYSTICK_GPIO[0].port, JOYSTICK_GPIO[0].num))) val |= JOYSTICK_CENTER;
+  if (!(GPIO_PinRead (JOYSTICK_GPIO[1].port, JOYSTICK_GPIO[1].num))) val |= JOYSTICK_UP;
+  if (!(GPIO_PinRead (JOYSTICK_GPIO[2].port, JOYSTICK_GPIO[2].num))) val |= JOYSTICK_DOWN;
+  if (!(GPIO_PinRead (JOYSTICK_GPIO[3].port, JOYSTICK_GPIO[3].num))) val |= JOYSTICK_LEFT;
+  if (!(GPIO_PinRead (JOYSTICK_GPIO[4].port, JOYSTICK_GPIO[4].num))) val |= JOYSTICK_RIGHT;
+
+  return val;
+}

CMSIS/Pack/Example/Boards/Keil/MCB1800/Common/LED_MCB1800.c

@@ -0,0 +1,154 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Name:    LED_MCB1800.c
+ * Purpose: LED interface for MCB1800 evaluation board
+ * Rev.:    1.00
+ *----------------------------------------------------------------------------*/
+
+#include "SCU_LPC18xx.h"
+#include "GPIO_LPC18xx.h"
+#include "Board_LED.h"
+
+#define LED_COUNT                      (8)
+
+/* LED pins:
+   - LED0: PD_10 = GPIO6[24]
+   - LED1: PD_11 = GPIO6[25]
+   - LED2: PD_12 = GPIO6[26]
+   - LED3: PD_13 = GPIO6[27]
+   - LED4: PD_14 = GPIO6[28]
+   - LED5: P9_0  = GPIO4[12]
+   - LED6: P9_1  = GPIO4[13]
+   - LED7: P9_2  = GPIO4[14] */
+
+/* LED GPIO definitions */
+const GPIO_ID LED_GPIO[] = {
+  { 6, 24 },
+  { 6, 25 },
+  { 6, 26 },
+  { 6, 27 },
+  { 6, 28 },
+  { 4, 12 },
+  { 4, 13 },
+  { 4, 14 }
+};
+
+/* LED pin definitions */
+const PIN_ID LED_PIN[] = {
+  { 13, 10, (SCU_CFG_MODE_FUNC4 | SCU_PIN_CFG_PULLDOWN_EN)},
+  { 13, 11, (SCU_CFG_MODE_FUNC4 | SCU_PIN_CFG_PULLDOWN_EN)},
+  { 13, 12, (SCU_CFG_MODE_FUNC4 | SCU_PIN_CFG_PULLDOWN_EN)},
+  { 13, 13, (SCU_CFG_MODE_FUNC4 | SCU_PIN_CFG_PULLDOWN_EN)},
+  { 13, 14, (SCU_CFG_MODE_FUNC4 | SCU_PIN_CFG_PULLDOWN_EN)},
+  {  9,  0, (SCU_CFG_MODE_FUNC0 | SCU_PIN_CFG_PULLDOWN_EN)},
+  {  9,  1, (SCU_CFG_MODE_FUNC0 | SCU_PIN_CFG_PULLDOWN_EN)},
+  {  9,  2, (SCU_CFG_MODE_FUNC0 | SCU_PIN_CFG_PULLDOWN_EN)}
+};
+
+
+/**
+  \fn          int32_t LED_Initialize (void)
+  \brief       Initialize LEDs
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t LED_Initialize (void) {
+  uint32_t n;
+
+  /* Enable GPIO clock */
+  GPIO_PortClock     (1);
+
+  /* Configure pins: Output Mode with Pull-down resistors */
+  for (n = 0; n < LED_COUNT; n++) {
+    SCU_PinConfigure (LED_PIN[n].port,  LED_PIN[n].num,  LED_PIN[n].config_val);
+    GPIO_SetDir      (LED_GPIO[n].port, LED_GPIO[n].num, GPIO_DIR_OUTPUT);
+    GPIO_PinWrite    (LED_GPIO[n].port, LED_GPIO[n].num, 0);
+  }
+  return 0;
+}
+
+/**
+  \fn          int32_t LED_Uninitialize (void)
+  \brief       De-initialize LEDs
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t LED_Uninitialize (void) {
+  uint32_t n;
+
+  /* Unconfigure pins: turn off Pull-up/down resistors */
+  for (n = 0; n < LED_COUNT; n++) {
+    SCU_PinConfigure (LED_PIN[n].port,  LED_PIN[n].num,  0);
+  }
+  return 0;
+}
+
+/**
+  \fn          int32_t LED_On (uint32_t num)
+  \brief       Turn on requested LED
+  \param[in]   num  LED number
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t LED_On (uint32_t num) {
+  GPIO_PinWrite     (LED_GPIO[num].port, LED_GPIO[num].num, 1);
+  return 0;
+}
+
+/**
+  \fn          int32_t LED_Off (uint32_t num)
+  \brief       Turn off requested LED
+  \param[in]   num  LED number
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t LED_Off (uint32_t num) {
+  GPIO_PinWrite     (LED_GPIO[num].port, LED_GPIO [num].num, 0);
+  return 0;
+}
+
+/**
+  \fn          int32_t LED_SetOut (uint32_t val)
+  \brief       Write value to LEDs
+  \param[in]   val  value to be displayed on LEDs
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t LED_SetOut (uint32_t val) {
+  uint32_t n;
+
+  for (n = 0; n < LED_COUNT; n++) {
+    if (val & (1 << n)) LED_On (n);
+    else                LED_Off(n);
+  }
+  return 0;
+}
+
+/**
+  \fn          uint32_t LED_GetCount (void)
+  \brief       Get number of LEDs
+  \return      Number of available LEDs
+*/
+uint32_t LED_GetCount (void) {
+  return LED_COUNT;
+}

CMSIS/Pack/Example/Boards/Keil/MCB1800/Common/STMPE811.h

@@ -0,0 +1,79 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Name:    STMPE811.h
+ * Purpose: STMPE811 (Touschscreen controller with IO expander) definitions
+ * Rev.:    1.00
+ *----------------------------------------------------------------------------*/
+
+#ifndef __STMPE811_H
+#define __STMPE811_H
+
+/* Register addresses */
+#define STMPE811_CHIP_ID        0x00
+#define STMPE811_ID_VER         0x02
+#define STMPE811_SYS_CTRL1      0x03
+#define STMPE811_SYS_CTRL2      0x04
+#define STMPE811_SPI_CFG        0x08
+#define STMPE811_INT_CTRL       0x09
+#define STMPE811_INT_EN         0x0A
+#define STMPE811_INT_STA        0x0B
+#define STMPE811_GPIO_EN        0x0C
+#define STMPE811_GPIO_INT_STA   0x0D
+#define STMPE811_ADC_INT_EN     0x0E
+#define STMPE811_ADC_INT_STA    0x0F
+#define STMPE811_GPIO_SET_PIN   0x10
+#define STMPE811_GPIO_CLR_PIN   0x11
+#define STMPE811_GPIO_MP_STA    0x12
+#define STMPE811_GPIO_DIR       0x13
+#define STMPE811_GPIO_ED        0x14
+#define STMPE811_GPIO_RE        0x15
+#define STMPE811_GPIO_FE        0x16
+#define STMPE811_GPIO_AF        0x17
+#define STMPE811_ADC_CTRL1      0x20
+#define STMPE811_ADC_CTRL2      0x21
+#define STMPE811_ADC_CAPT       0x22
+#define STMPE811_ADC_DATA_CH0   0x30
+#define STMPE811_ADC_DATA_CH1   0x32
+#define STMPE811_ADC_DATA_CH2   0x34
+#define STMPE811_ADC_DATA_CH3   0x36
+#define STMPE811_ADC_DATA_CH4   0x38
+#define STMPE811_ADC_DATA_CH5   0x3A
+#define STMPE811_ADC_DATA_CH6   0x3C
+#define STMPE811_ADC_DATA_CH7   0x3E
+#define STMPE811_TSC_CTRL       0x40
+#define STMPE811_TSC_CFG        0x41
+#define STMPE811_WDW_TR_X       0x42
+#define STMPE811_WDW_TR_Y       0x44
+#define STMPE811_WDW_BL_X       0x46
+#define STMPE811_WDW_BL_Y       0x48
+#define STMPE811_FIFO_TH        0x4A
+#define STMPE811_FIFO_STA       0x4B
+#define STMPE811_FIFO_SIZE      0x4C
+#define STMPE811_TSC_DATA_X     0x4D
+#define STMPE811_TSC_DATA_Y     0x4F
+#define STMPE811_TSC_DATA_Z     0x51
+#define STMPE811_TSC_FRACTION_Z 0x56
+#define STMPE811_TSC_DATA_XYZ   0x57
+#define STMPE811_TSC_DATA       0xD7
+#define STMPE811_TSC_I_DRIVE    0x58
+#define STMPE811_TSC_SHIELD     0x59
+#define STMPE811_TEMP_CTRL      0x60
+#define STMPE811_TEMP_DATA      0x61
+#define STMPE811_TEMP_TH        0x62
+
+#endif /* __STMPE811_H */

CMSIS/Pack/Example/Boards/Keil/MCB1800/Common/Thermometer_LM75.c

@@ -0,0 +1,135 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Name:    Thermometer_LM75.c
+ * Purpose: Thermometer LM75 interface
+ * Rev.:    1.00
+ *----------------------------------------------------------------------------*/
+
+#include "Driver_I2C.h"
+#include "Board_Thermometer.h"
+
+#ifndef TH_I2C_PORT
+#define TH_I2C_PORT      0              /* I2C Port number                    */
+#endif
+
+#define TH_I2C_ADDR     0x48            /* LM 75 Thermometer I2C address      */
+
+/* I2C Driver */
+#define _I2C_Driver_(n)  Driver_I2C##n
+#define  I2C_Driver_(n) _I2C_Driver_(n)
+extern ARM_DRIVER_I2C    I2C_Driver_(TH_I2C_PORT);
+#define ptrI2C         (&I2C_Driver_(TH_I2C_PORT))
+
+#define MODE_COMP   0                   /* Comparator mode                    */
+#define MODE_INT    1                   /* Interrupt mode                     */
+
+/* Register addresses */
+#define REG_TEMP        0x00
+#define REG_CONF        0x01
+#define REG_THYS        0x02
+#define REG_TOS         0x03
+
+static uint8_t DeviceAddr;
+
+/**
+  \fn          int32_t TH_Read (uint8_t reg, uint8_t *val, uint32_t size)
+  \brief       Read register value from Thermometer
+  \param[in]   reg    Register address
+  \param[in]   val    Pointer where value will be read from register
+  \param[in]   size   Number of data bytes to read
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+static int32_t TH_Read (uint8_t reg, uint8_t *val, uint32_t size) {
+  uint8_t data[1];
+
+  data[0] = reg;
+  ptrI2C->MasterTransmit (DeviceAddr, data, 1, true);
+  while (ptrI2C->GetStatus().busy);
+  ptrI2C->MasterReceive (DeviceAddr, val, size, false);
+  while (ptrI2C->GetStatus().busy);
+
+  return 0;
+}
+
+/**
+  \fn          int32_t Thermometer_Initialize (void)
+  \brief       Initialize thermometer
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t Thermometer_Initialize (void) {
+  uint8_t val[3];
+
+  ptrI2C->Initialize   (NULL);
+  ptrI2C->PowerControl (ARM_POWER_FULL);
+  ptrI2C->Control      (ARM_I2C_BUS_SPEED, ARM_I2C_BUS_SPEED_FAST);
+  ptrI2C->Control      (ARM_I2C_BUS_CLEAR, 0);
+
+  /* Init L3G4200D device */
+  DeviceAddr = TH_I2C_ADDR;
+  
+  /* Set default configuration */
+  val[1] = 0;
+  val[0] = REG_CONF;
+  ptrI2C->MasterTransmit (DeviceAddr, val, 2, false);
+  while (ptrI2C->GetStatus().busy);
+
+  /* Set Hysteresis */
+  val[2] = 75;
+  val[1] =  0;
+  val[0] =  REG_THYS;
+  ptrI2C->MasterTransmit (DeviceAddr, val, 3, false);
+  while (ptrI2C->GetStatus().busy);
+
+  /* Set Tos */
+  val[2] = 80;
+  val[1] =  0;
+  val[0] =  REG_TOS;
+  ptrI2C->MasterTransmit (DeviceAddr, val, 3, false);
+  while (ptrI2C->GetStatus().busy);
+
+  return 0;
+}
+
+/**
+  \fn          int32_t Thermometer_Uninitialize (void)
+  \brief       De-initialize thermometer
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t Thermometer_Uninitialize (void) {
+  return 0;
+}
+
+/**
+  \fn          int32_t Thermometer_GetTemperature (void)
+  \brief       Get last temperature measurement
+  \returns     Temperature in 0.1C, or TEMPERATURE_INVALID in case of error
+*/
+int32_t Thermometer_GetTemperature (void) {
+  uint8_t val[2];
+
+  if (TH_Read(REG_TEMP, val, 2) == 0) {
+    return (((val[0] << 1) | (val[1]) >> 7) * 5);
+  }
+  return TEMPERATURE_INVALID;
+}

CMSIS/Pack/Example/Boards/Keil/MCB1800/Common/Touch_STMPE811.c

@@ -0,0 +1,174 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Name:    Touch_STMPE811.c
+ * Purpose: Touchscreen STMPE811 interface
+ * Rev.:    1.00
+ *----------------------------------------------------------------------------*/
+
+#include "cmsis_os.h"
+#include "STMPE811.h"
+#include "Driver_I2C.h"
+#include "Board_Touch.h"
+
+#ifndef TSC_I2C_PORT
+#define TSC_I2C_PORT    0               /* I2C Port number                    */
+#endif
+
+#define TSC_I2C_ADDR    0x41            /* 7-bit I2C address                  */
+
+/* I2C Driver */
+#define _I2C_Driver_(n)  Driver_I2C##n
+#define  I2C_Driver_(n) _I2C_Driver_(n)
+extern ARM_DRIVER_I2C    I2C_Driver_(TSC_I2C_PORT);
+#define ptrI2C         (&I2C_Driver_(TSC_I2C_PORT))
+
+
+/**
+  \fn          int32_t Touch_ReadRegister (uint32_t reg, uint8_t *val)
+  \brief       Read register value from Touchscreen controller
+  \param[in]   reg    Register address
+  \param[out]  val    Pointer where data will be read from register
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+static bool Touch_Read (uint8_t reg, uint8_t *val) {
+  uint8_t data[1];
+
+  data[0] = reg;
+  ptrI2C->MasterTransmit (TSC_I2C_ADDR, data, 1, true);
+  while (ptrI2C->GetStatus().busy);
+  ptrI2C->MasterReceive (TSC_I2C_ADDR, val, 1, false);
+  while (ptrI2C->GetStatus().busy);
+
+  return 0;
+}
+
+/**
+  \fn          int32_t Touch_WriteData (uint32_t reg, const uint8_t *val)
+  \brief       Write value to Touchscreen controller register
+  \param[in]   reg    Register address
+  \param[in]   val    Pointer with data to write to register
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+static bool Touch_Write (uint8_t reg, uint8_t val) {
+  uint8_t data[2];
+
+  data[0] = reg;
+  data[1] = val;
+  ptrI2C->MasterTransmit (TSC_I2C_ADDR, data, 2, false);
+  while (ptrI2C->GetStatus().busy);
+
+  return 0;
+}
+
+/**
+  \fn          int32_t Touch_Initialize (void)
+  \brief       Initialize touchscreen
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t Touch_Initialize (void) {
+  uint32_t tick;
+  
+  ptrI2C->Initialize   (NULL);
+  ptrI2C->PowerControl (ARM_POWER_FULL);
+  ptrI2C->Control      (ARM_I2C_BUS_SPEED, ARM_I2C_BUS_SPEED_FAST);
+  ptrI2C->Control      (ARM_I2C_BUS_CLEAR, 0);
+
+  Touch_Write(STMPE811_SYS_CTRL1,      0x02); /* Reset Touch-screen controller */
+  tick = osKernelSysTick();                   /* Wait 10ms                     */
+  while ((osKernelSysTick() - tick) < osKernelSysTickMicroSec(10000));
+
+  Touch_Write(STMPE811_SYS_CTRL2,      0x0C); /* Enable TSC and ADC            */
+  Touch_Write(STMPE811_INT_EN,         0x07); /* Enable Touch detect, FIFO     */
+  Touch_Write(STMPE811_ADC_CTRL1,      0x68); /* Set sample time , 12-bit mode */
+  tick = osKernelSysTick();                   /* Wait 500us                    */
+  while ((osKernelSysTick() - tick) < osKernelSysTickMicroSec(500));
+
+  Touch_Write(STMPE811_ADC_CTRL2,      0x01); /* ADC frequency 3.25 MHz        */
+  Touch_Write(STMPE811_TSC_CFG,        0xC2); /* Detect delay 10us,
+                                                 Settle time 500us             */
+  Touch_Write(STMPE811_FIFO_TH,        0x01); /* Threshold for FIFO            */
+  Touch_Write(STMPE811_FIFO_STA,       0x01); /* FIFO reset                    */
+  Touch_Write(STMPE811_FIFO_STA,       0x00); /* FIFO not reset                */
+  Touch_Write(STMPE811_TSC_FRACTION_Z, 0x07); /* Fraction z                    */
+  Touch_Write(STMPE811_TSC_I_DRIVE,    0x01); /* Drive 50 mA typical           */
+  Touch_Write(STMPE811_GPIO_AF,        0x00); /* Pins are used for touchscreen */
+  Touch_Write(STMPE811_TSC_CTRL,       0x01); /* Enable TSC                    */
+  Touch_Write(STMPE811_INT_STA,        0xFF); /* Clear interrupt status        */
+
+  return 0;
+}
+
+/**
+  \fn          int32_t Touch_Uninitialize (void)
+  \brief       De-initialize touchscreen
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t Touch_Uninitialize (void) {
+  Touch_Write(STMPE811_SYS_CTRL1, 0x02);  /* Reset Touch-screen controller    */
+  return 0;
+}
+
+/**
+  \fn          int32_t Touch_GetState (TOUCH_STATE *pState)
+  \brief       Get touchscreen state
+  \param[out]  pState  pointer to TOUCH_STATE structure
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t Touch_GetState (TOUCH_STATE *pState) {
+  uint8_t val;
+  uint8_t num;
+  uint8_t xyz[4];
+  int32_t res;
+
+  /* Read touch status */
+  res = Touch_Read(STMPE811_TSC_CTRL, &val);
+  if (res < 0) return -1;
+  pState->pressed = (val & (1 << 7)) ? 1 : 0;
+  
+  if (pState->pressed) {
+    val = STMPE811_TSC_DATA;
+
+    /* If FIFO overflow, discard all samples except the last one */
+    res = Touch_Read(STMPE811_FIFO_SIZE, &num);
+    if (res < 0 || num == 0) return -1;
+
+    while (num--) {
+      ptrI2C->MasterTransmit (TSC_I2C_ADDR, &val, 1, true);
+      while (ptrI2C->GetStatus().busy);
+      ptrI2C->MasterReceive (TSC_I2C_ADDR, xyz, 4, false);
+      while (ptrI2C->GetStatus().busy);
+    }
+    pState->x =  (xyz[0] << 4) | ((xyz[1] & 0xF0) >> 4);
+    pState->y =   xyz[2]       | ((xyz[1] & 0x0F) << 8);
+  }
+
+  /* Clear interrupt flags */
+  Touch_Write(STMPE811_INT_STA, 0x1F);
+
+  return 0;
+}

CMSIS/Pack/Example/Boards/Keil/MCB1800/RTX_Blinky/Abstract.txt

@@ -0,0 +1,32 @@
+The RTX_Blinky project is a simple RTX Kernel based example
+for the NXP 'LPC1857' microcontroller using Keil 'MCB1800'
+Evaluation Board, compliant to Cortex Microcontroller
+Software Interface Standard (CMSIS V2.0).
+
+Example functionality:
+ - Clock Settings:
+   - XTAL    =  12 MHz
+   - CPU     = 180 MHz
+
+The simple RTX Kernel based example simulates the step-motor 
+driver. Four LEDs are blinking simulating the activation of 
+the four output driver stages:
+
+- phase A
+- phase B
+- phase C
+- phase D
+
+This example simulates Half step driver mode and
+CW rotation direction.
+
+
+The BLINKY example program is available for several targets:
+
+  LPC1857 Flash:       configured for on-chip Flash
+                       Valid Flash Signature is created with ElfDwT tool.
+                       See "Options for Target" - "User"
+
+
+  LPC1857 RAM:         runs from Internal RAM located on chip
+                       (may be used for target debugging)

CMSIS/Pack/Example/Boards/Keil/MCB1800/RTX_Blinky/Blinky.c

@@ -0,0 +1,152 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ *      Name:    BLinky.c
+ *      Purpose: RTX example program
+ *
+ *---------------------------------------------------------------------------*/
+
+#include "cmsis_os.h"
+#include "LPC18xx.h"
+#include "Board_LED.h"
+
+osThreadId tid_phaseA;                  /* Thread id of thread: phase_a      */
+osThreadId tid_phaseB;                  /* Thread id of thread: phase_b      */
+osThreadId tid_phaseC;                  /* Thread id of thread: phase_c      */
+osThreadId tid_phaseD;                  /* Thread id of thread: phase_d      */
+osThreadId tid_clock;                   /* Thread id of thread: clock        */
+osThreadId tid_lcd;                     /* Thread id of thread: lcd          */
+
+#define LED_A   0
+#define LED_B   1
+#define LED_C   2
+#define LED_D   3
+#define LED_CLK 7
+
+
+/*----------------------------------------------------------------------------
+ *      Switch LED on
+ *---------------------------------------------------------------------------*/
+void Switch_On (unsigned char led) {
+  LED_On(led);
+}
+
+/*----------------------------------------------------------------------------
+ *      Switch LED off
+ *---------------------------------------------------------------------------*/
+void Switch_Off (unsigned char led) {
+  LED_Off(led);
+}
+
+
+/*----------------------------------------------------------------------------
+ *      Function 'signal_func' called from multiple threads
+ *---------------------------------------------------------------------------*/
+void signal_func (osThreadId tid)  {
+  osSignalSet(tid_clock, 0x0100);           /* set signal to clock thread    */
+  osDelay(500);                             /* delay 500ms                   */
+  osSignalSet(tid_clock, 0x0100);           /* set signal to clock thread    */
+  osDelay(500);                             /* delay 500ms                   */
+  osSignalSet(tid, 0x0001);                 /* set signal to thread 'thread' */
+  osDelay(500);                             /* delay 500ms                   */
+}
+
+/*----------------------------------------------------------------------------
+ *      Thread 1 'phaseA': Phase A output
+ *---------------------------------------------------------------------------*/
+void phaseA (void const *argument) {
+  for (;;) {
+    osSignalWait(0x0001, osWaitForever);    /* wait for an event flag 0x0001 */
+    Switch_On (LED_A);
+    signal_func(tid_phaseB);                /* call common signal function   */
+    Switch_Off(LED_A);
+  }
+}
+
+/*----------------------------------------------------------------------------
+ *      Thread 2 'phaseB': Phase B output
+ *---------------------------------------------------------------------------*/
+void phaseB (void const *argument) {
+  for (;;) {
+    osSignalWait(0x0001, osWaitForever);    /* wait for an event flag 0x0001 */
+    Switch_On (LED_B);
+    signal_func(tid_phaseC);                /* call common signal function   */
+    Switch_Off(LED_B);
+  }
+}
+
+/*----------------------------------------------------------------------------
+ *      Thread 3 'phaseC': Phase C output
+ *---------------------------------------------------------------------------*/
+void phaseC (void const *argument) {
+  for (;;) {
+    osSignalWait(0x0001, osWaitForever);    /* wait for an event flag 0x0001 */
+    Switch_On (LED_C);
+    signal_func(tid_phaseD);                /* call common signal function   */
+    Switch_Off(LED_C);
+  }
+}
+
+/*----------------------------------------------------------------------------
+ *      Thread 4 'phaseD': Phase D output
+ *---------------------------------------------------------------------------*/
+void phaseD (void  const *argument) {
+  for (;;) {
+    osSignalWait(0x0001, osWaitForever);    /* wait for an event flag 0x0001 */
+    Switch_On (LED_D);
+    signal_func(tid_phaseA);                /* call common signal function   */
+    Switch_Off(LED_D);
+  }
+}
+
+/*----------------------------------------------------------------------------
+ *      Thread 5 'clock': Signal Clock
+ *---------------------------------------------------------------------------*/
+void clock (void  const *argument) {
+  for (;;) {
+    osSignalWait(0x0100, osWaitForever);    /* wait for an event flag 0x0100 */
+    Switch_On (LED_CLK);
+    osDelay(80);                            /* delay  80ms                   */
+    Switch_Off(LED_CLK);
+  }
+}
+
+
+
+osThreadDef(phaseA, osPriorityNormal, 1, 0);
+osThreadDef(phaseB, osPriorityNormal, 1, 0);
+osThreadDef(phaseC, osPriorityNormal, 1, 0);
+osThreadDef(phaseD, osPriorityNormal, 1, 0);
+osThreadDef(clock,  osPriorityNormal, 1, 0);
+
+/*----------------------------------------------------------------------------
+ *      Main: Initialize and start RTX Kernel
+ *---------------------------------------------------------------------------*/
+int main (void) {
+
+  LED_Initialize();                         /* Initialize the LEDs           */
+  tid_phaseA = osThreadCreate(osThread(phaseA), NULL);
+  tid_phaseB = osThreadCreate(osThread(phaseB), NULL);
+  tid_phaseC = osThreadCreate(osThread(phaseC), NULL);
+  tid_phaseD = osThreadCreate(osThread(phaseD), NULL);
+  tid_clock  = osThreadCreate(osThread(clock),  NULL);
+
+  osSignalSet(tid_phaseA, 0x0001);          /* set signal to phaseA thread   */
+
+  osDelay(osWaitForever);
+  while(1);
+}

CMSIS/Pack/Example/Boards/Keil/MCB1800/RTX_Blinky/Blinky.uvoptx

@@ -0,0 +1,424 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>LPC1857 Flash</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\Flash\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>8</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>MCB1800 Schematics (MCB1800)</Title>
+          <Path>C:\Keil\ARM\PACK\Keil\LPC1800_DFP\2.6.0-dev1\Documents\MCB1800v1-3-schematics.pdf</Path>
+        </Book>
+        <Book>
+          <Number>1</Number>
+          <Title>User Manual (MCB1800)</Title>
+          <Path>C:\Keil\ARM\PACK\Keil\LPC1800_DFP\2.6.0-dev1\Documents\mcb1800.chm</Path>
+        </Book>
+        <Book>
+          <Number>2</Number>
+          <Title>MCB1800 Evaluation Board Web Page (MCB1800)</Title>
+          <Path>http://www.keil.com/mcb1800/</Path>
+        </Book>
+      </Books>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name>(105=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-UV0510N9E -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15  -FN2 -FC1000 -FD10000000 -FF0LPC18xx43xx_512_BA -FF1LPC18xx43xx_512_BB -FL080000 -FL180000 -FS01A000000 -FS11B000000 -FP0($$Device:LPC1857$Flash\LPC18xx43xx_512_BA.flm) -FP1($$Device:LPC1857$Flash\LPC18xx43xx_512_BB.flm)</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>1</periodic>
+        <aLwin>1</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+    </TargetOption>
+  </Target>
+
+  <Target>
+    <TargetName>LPC1857 RAM</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\RAM\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>0</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>8</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>MCB1800 Schematics (MCB1800)</Title>
+          <Path>C:\Keil\ARM\PACK\Keil\LPC1800_DFP\1.99.3\Documents\MCB1800v1-3-schematics.pdf</Path>
+        </Book>
+        <Book>
+          <Number>1</Number>
+          <Title>User Manual (MCB1800)</Title>
+          <Path>C:\Keil\ARM\PACK\Keil\LPC1800_DFP\1.99.3\Documents\mcb1800.chm</Path>
+        </Book>
+        <Book>
+          <Number>2</Number>
+          <Title>MCB1800 Evaluation Board Web Page (MCB1800)</Title>
+          <Path>http://www.keil.com/mcb1800/</Path>
+        </Book>
+      </Books>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>0</tLdApp>
+        <tGomain>0</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>1</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
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+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile>.\Debug_RAM.ini</tIfile>
+        <pMon>BIN\UL2CM3.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name>(105=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>-UV0510N9E -O207 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD10000000 -FC1000 -FN0</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>1</periodic>
+        <aLwin>1</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
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+        <eProf>0</eProf>
+        <aLa>0</aLa>
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+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+    </TargetOption>
+  </Target>
+
+  <Group>
+    <GroupName>Source Files</GroupName>
+    <tvExp>1</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
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+      <Focus>0</Focus>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\Blinky.c</PathWithFileName>
+      <FilenameWithoutPath>Blinky.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>Documentation</GroupName>
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+    <cbSel>0</cbSel>
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+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>.\Abstract.txt</PathWithFileName>
+      <FilenameWithoutPath>Abstract.txt</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>::Board Support</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>1</RteFlg>
+  </Group>
+
+  <Group>
+    <GroupName>::CMSIS</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>1</RteFlg>
+  </Group>
+
+  <Group>
+    <GroupName>::Device</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>1</RteFlg>
+  </Group>
+
+</ProjectOpt>

CMSIS/Pack/Example/Boards/Keil/MCB1800/RTX_Blinky/Blinky.uvprojx

@@ -0,0 +1,985 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>LPC1857 Flash</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>5060020::V5.06 (build 20)::ARMCC</pCCUsed>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>LPC1857</Device>
+          <Vendor>NXP (founded by Philips)</Vendor>
+          <PackID>Keil.LPC1800_DFP.2.6.0-dev1</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IRAM(0x10000000,0x8000) IRAM2(0x20000000,0x10000) IROM(0x1A000000,0x80000) IROM2(0x1B000000,0x80000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD10000000 -FC1000 -FN2 -FF0LPC18xx43xx_512_BA -FS01A000000 -FL080000 -FF1LPC18xx43xx_512_BB -FS11B000000 -FL180000 -FP0($$Device:LPC1857$Flash\LPC18xx43xx_512_BA.flm))</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:LPC1857$Device\Include\LPC18xx.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:LPC1857$SVD\LPC18xx.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\Flash\</OutputDirectory>
+          <OutputName>Blinky</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\Flash\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>1</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name>$K\ARM\BIN\ElfDwT.exe !L BASEADDRESS(0x1A000000)</UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>-REMAP -MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments>-REMAP -MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+            <RestoreSysVw>1</RestoreSysVw>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>1</RestoreTracepoints>
+            <RestoreSysVw>1</RestoreSysVw>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>1</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>BIN\UL2CM3.DLL</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4097</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M3"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>1</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>1</hadIRAM2>
+            <hadIROM2>1</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x8000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x1a000000</StartAddress>
+                <Size>0x80000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x1a000000</StartAddress>
+                <Size>0x80000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x1b000000</StartAddress>
+                <Size>0x80000</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x8000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>0</uC99>
+            <useXO>0</useXO>
+            <v6Lang>0</v6Lang>
+            <v6LangP>0</v6LangP>
+            <vShortEn>0</vShortEn>
+            <vShortWch>0</vShortWch>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x1A000000</TextAddressRange>
+            <DataAddressRange>0x10000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Source Files</GroupName>
+          <Files>
+            <File>
+              <FileName>Blinky.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Blinky.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Documentation</GroupName>
+          <Files>
+            <File>
+              <FileName>Abstract.txt</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\Abstract.txt</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::Board Support</GroupName>
+        </Group>
+        <Group>
+          <GroupName>::CMSIS</GroupName>
+        </Group>
+        <Group>
+          <GroupName>::Device</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+    <Target>
+      <TargetName>LPC1857 RAM</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>LPC1857</Device>
+          <Vendor>NXP (founded by Philips)</Vendor>
+          <Cpu>IRAM(0x10000000,0x8000) IRAM2(0x20000000,0x10000) IROM(0x1A000000,0x80000) IROM2(0x1B000000,0x80000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD10000000 -FC1000 -FN2 -FF0LPC18xx43xx_512_BA -FS01A000000 -FL080000 -FF1LPC18xx43xx_512_BB -FS11B000000 -FL180000 -FP0($$Device:LPC1857$Flash\LPC18xx43xx_512_BA.flm))</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:LPC1857$Device\Include\LPC18xx.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:LPC1857$SVD\LPC18xx.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\RAM\</OutputDirectory>
+          <OutputName>Blinky</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\RAM\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>-REMAP -MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments>-REMAP -MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+            <RestoreSysVw>1</RestoreSysVw>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>0</LoadApplicationAtStartup>
+            <RunToMain>0</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>1</RestoreTracepoints>
+            <RestoreSysVw>1</RestoreSysVw>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>1</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile>.\Debug_RAM.ini</InitializationFile>
+            <Driver>BIN\UL2CM3.DLL</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M3"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>1</hadIRAM2>
+            <hadIROM2>1</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>0</Im1Chk>
+            <Im2Chk>1</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x8000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x1a000000</StartAddress>
+                <Size>0x80000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x8000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x1b000000</StartAddress>
+                <Size>0x80000</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>0</uC99>
+            <useXO>0</useXO>
+            <v6Lang>0</v6Lang>
+            <v6LangP>0</v6LangP>
+            <vShortEn>0</vShortEn>
+            <vShortWch>0</vShortWch>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x1A000000</TextAddressRange>
+            <DataAddressRange>0x10000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Source Files</GroupName>
+          <Files>
+            <File>
+              <FileName>Blinky.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Blinky.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Documentation</GroupName>
+          <Files>
+            <File>
+              <FileName>Abstract.txt</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\Abstract.txt</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::Board Support</GroupName>
+        </Group>
+        <Group>
+          <GroupName>::CMSIS</GroupName>
+        </Group>
+        <Group>
+          <GroupName>::Device</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis>
+      <api Capiversion="1.00" Cclass="Board Support" Cgroup="LED" exclusive="0">
+        <package name="MDK-Middleware" schemaVersion="1.0" url="http://www.keil.com/pack/" vendor="Keil" version="5.99.1"/>
+        <targetInfos>
+          <targetInfo name="LPC1857 Flash"/>
+          <targetInfo name="LPC1857 RAM"/>
+        </targetInfos>
+      </api>
+      <api Cclass="CMSIS" Cgroup="RTOS" exclusive="0">
+        <package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="3.20.0"/>
+        <targetInfos>
+          <targetInfo name="LPC1857 Flash"/>
+          <targetInfo name="LPC1857 RAM"/>
+        </targetInfos>
+      </api>
+    </apis>
+    <components>
+      <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="3.30.0" condition="CMSIS Core">
+        <package name="CMSIS" schemaVersion="1.0" url="http://www.keil.com/pack/" vendor="ARM" version="4.0.1"/>
+        <targetInfos>
+          <targetInfo name="LPC1857 Flash"/>
+          <targetInfo name="LPC1857 RAM"/>
+        </targetInfos>
+      </component>
+      <component Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX" Cvendor="ARM" Cversion="4.78.0" condition="Cortex-M Device Startup">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.3.0"/>
+        <targetInfos>
+          <targetInfo name="LPC1857 Flash"/>
+          <targetInfo name="LPC1857 RAM"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Board Support" Cgroup="LED" Cvendor="Keil" Cversion="1.00" condition="LPC1800 CMSIS SCU GPIO">
+        <package name="LPC1800_DFP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="Keil" version="1.99.2"/>
+        <targetInfos>
+          <targetInfo name="LPC1857 Flash"/>
+          <targetInfo name="LPC1857 RAM"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="GPIO" Cvendor="Keil" Cversion="1.00" condition="LPC1800 CMSIS">
+        <package name="LPC1800_DFP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="Keil" version="1.99.2"/>
+        <targetInfos>
+          <targetInfo name="LPC1857 Flash"/>
+          <targetInfo name="LPC1857 RAM"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="SCU" Cvendor="Keil" Cversion="1.00" condition="LPC1800 CMSIS">
+        <package name="LPC1800_DFP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="Keil" version="1.99.2"/>
+        <targetInfos>
+          <targetInfo name="LPC1857 Flash"/>
+          <targetInfo name="LPC1857 RAM"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="LPC1800 CMSIS">
+        <package name="LPC1800_DFP" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="Keil" version="2.6.0-dev1"/>
+        <targetInfos>
+          <targetInfo name="LPC1857 Flash"/>
+          <targetInfo name="LPC1857 RAM"/>
+        </targetInfos>
+      </component>
+    </components>
+    <files>
+      <file attr="config" category="source" name="CMSIS\RTOS\RTX\Templates\RTX_Conf_CM.c" version="4.70.1">
+        <instance index="0">RTE\CMSIS\RTX_Conf_CM.c</instance>
+        <component Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX" Cvendor="ARM" Cversion="4.78.0" condition="Cortex-M Device Startup"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.3.0"/>
+        <targetInfos>
+          <targetInfo name="LPC1857 Flash"/>
+          <targetInfo name="LPC1857 RAM"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="header" name="RTE_Driver\Config\RTE_Device.h">
+        <instance index="0">RTE\Device\LPC1857\RTE_Device.h</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="2.00" Dname="LPC1857" RTE_Components_h="#define RTE_DEVICE_STARTUP_LPC18XX    /* Device Startup for NXP18XX */" condition="LPC18xx CMSIS Device"/>
+        <package name="LPC18xx_DFP" url="http://www.keil.com/pack" vendor="Keil" version="0.0.1"/>
+        <targetInfos>
+          <targetInfo name="LPC1857 Flash"/>
+          <targetInfo name="LPC1857 RAM"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="source" name="Device\Source\ARM\startup_LPC18xx.s">
+        <instance index="0">RTE\Device\LPC1857\startup_LPC18xx.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" Dname="LPC1857" RTE_Components_h="#define RTE_DEVICE_STARTUP_LPC18XX    /* Device Startup for NXP18XX */" condition="LPC18xx CMSIS Device"/>
+        <package name="LPC18xx_DFP" url="http://www.keil.com/pack" vendor="Keil" version="0.0.1"/>
+        <targetInfos>
+          <targetInfo name="LPC1857 Flash"/>
+          <targetInfo name="LPC1857 RAM"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="source" name="Device\Source\system_LPC18xx.c" version="1.0.1">
+        <instance index="0">RTE\Device\LPC1857\system_LPC18xx.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="LPC1800 CMSIS"/>
+        <package name="LPC1800_DFP" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="Keil" version="2.6.0-dev1"/>
+        <targetInfos>
+          <targetInfo name="LPC1857 Flash"/>
+          <targetInfo name="LPC1857 RAM"/>
+        </targetInfos>
+      </file>
+    </files>
+  </RTE>
+
+</Project>

CMSIS/Pack/Example/Boards/Keil/MCB1800/RTX_Blinky/Debug_RAM.ini

@@ -0,0 +1,35 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Name:    Debug_RAM.ini
+ * Purpose: Initialization File for Debugging from Internal RAM on
+ *          NXP LPC18xx/LPC43xxAudio codec UDA1380 interface
+ * Rev.:    1.00
+ *----------------------------------------------------------------------------*/
+
+FUNC void Setup (void) {
+  SP = _RDWORD(0x10000000);             // Setup Stack Pointer
+  PC = _RDWORD(0x10000004);             // Setup Program Counter
+  XPSR = 0x01000000;                    // Set Thumb bit
+  _WDWORD(0xE000ED08, 0x10000000);      // Setup Vector Table Offset Register
+  _WDWORD(0x40043100, 0x10000000);      // Set shadow pointer
+}
+
+LOAD %L INCREMENTAL                     // Download to RAM
+Setup();
+
+g, main

CMSIS/Pack/Example/Boards/Keil/MCB1800/RTX_Blinky/RTE/CMSIS/RTX_Conf_CM.c

@@ -0,0 +1,311 @@
+/*----------------------------------------------------------------------------
+ *      CMSIS-RTOS  -  RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RTX_Conf_CM.C
+ *      Purpose: Configuration of CMSIS RTX Kernel for Cortex-M
+ *      Rev.:    V4.70.1
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used 
+ *    to endorse or promote products derived from this software without 
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+ 
+#include "cmsis_os.h"
+ 
+
+/*----------------------------------------------------------------------------
+ *      RTX User configuration part BEGIN
+ *---------------------------------------------------------------------------*/
+ 
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+//
+// <h>Thread Configuration
+// =======================
+//
+//   <o>Number of concurrent running user threads <1-250>
+//   <i> Defines max. number of user threads that will run at the same time.
+//   <i> Default: 6
+#ifndef OS_TASKCNT
+ #define OS_TASKCNT     6
+#endif
+ 
+//   <o>Default Thread stack size [bytes] <64-4096:8><#/4>
+//   <i> Defines default stack size for threads with osThreadDef stacksz = 0
+//   <i> Default: 200
+#ifndef OS_STKSIZE
+ #define OS_STKSIZE     50      // this stack size value is in words
+#endif
+ 
+//   <o>Main Thread stack size [bytes] <64-32768:8><#/4>
+//   <i> Defines stack size for main thread.
+//   <i> Default: 200
+#ifndef OS_MAINSTKSIZE
+ #define OS_MAINSTKSIZE 50      // this stack size value is in words
+#endif
+ 
+//   <o>Number of threads with user-provided stack size <0-250>
+//   <i> Defines the number of threads with user-provided stack size.
+//   <i> Default: 0
+#ifndef OS_PRIVCNT
+ #define OS_PRIVCNT     0
+#endif
+ 
+//   <o>Total stack size [bytes] for threads with user-provided stack size <0-1048576:8><#/4>
+//   <i> Defines the combined stack size for threads with user-provided stack size.
+//   <i> Default: 0
+#ifndef OS_PRIVSTKSIZE
+ #define OS_PRIVSTKSIZE 0       // this stack size value is in words
+#endif
+ 
+//   <q>Stack overflow checking
+//   <i> Enable stack overflow checks at thread switch.
+//   <i> Enabling this option increases slightly the execution time of a thread switch.
+#ifndef OS_STKCHECK
+ #define OS_STKCHECK    1
+#endif
+ 
+//   <q>Stack usage watermark
+//   <i> Initialize thread stack with watermark pattern for analyzing stack usage (current/maximum) in System and Thread Viewer.
+//   <i> Enabling this option increases significantly the execution time of osThreadCreate.
+#ifndef OS_STKINIT
+#define OS_STKINIT      0
+#endif
+ 
+//   <o>Processor mode for thread execution 
+//     <0=> Unprivileged mode 
+//     <1=> Privileged mode
+//   <i> Default: Privileged mode
+#ifndef OS_RUNPRIV
+ #define OS_RUNPRIV     1
+#endif
+ 
+// </h>
+ 
+// <h>RTX Kernel Timer Tick Configuration
+// ======================================
+//   <q> Use Cortex-M SysTick timer as RTX Kernel Timer
+//   <i> Cortex-M processors provide in most cases a SysTick timer that can be used as 
+//   <i> as time-base for RTX.
+#ifndef OS_SYSTICK
+ #define OS_SYSTICK     1
+#endif
+//
+//   <o>RTOS Kernel Timer input clock frequency [Hz] <1-1000000000>
+//   <i> Defines the input frequency of the RTOS Kernel Timer.  
+//   <i> When the Cortex-M SysTick timer is used, the input clock 
+//   <i> is on most systems identical with the core clock.
+#ifndef OS_CLOCK
+ #define OS_CLOCK       180000000
+#endif
+ 
+//   <o>RTX Timer tick interval value [us] <1-1000000>
+//   <i> The RTX Timer tick interval value is used to calculate timeout values.
+//   <i> When the Cortex-M SysTick timer is enabled, the value also configures the SysTick timer.
+//   <i> Default: 1000  (1ms)
+#ifndef OS_TICK
+ #define OS_TICK        1000
+#endif
+ 
+// </h>
+ 
+// <h>System Configuration
+// =======================
+//
+// <e>Round-Robin Thread switching
+// ===============================
+//
+// <i> Enables Round-Robin Thread switching.
+#ifndef OS_ROBIN
+ #define OS_ROBIN       1
+#endif
+ 
+//   <o>Round-Robin Timeout [ticks] <1-1000>
+//   <i> Defines how long a thread will execute before a thread switch.
+//   <i> Default: 5
+#ifndef OS_ROBINTOUT
+ #define OS_ROBINTOUT   5
+#endif
+ 
+// </e>
+ 
+// <e>User Timers
+// ==============
+//   <i> Enables user Timers
+#ifndef OS_TIMERS
+ #define OS_TIMERS      1
+#endif
+ 
+//   <o>Timer Thread Priority
+//                        <1=> Low
+//     <2=> Below Normal  <3=> Normal  <4=> Above Normal
+//                        <5=> High
+//                        <6=> Realtime (highest)
+//   <i> Defines priority for Timer Thread
+//   <i> Default: High
+#ifndef OS_TIMERPRIO
+ #define OS_TIMERPRIO   5
+#endif
+ 
+//   <o>Timer Thread stack size [bytes] <64-4096:8><#/4>
+//   <i> Defines stack size for Timer thread.
+//   <i> Default: 200
+#ifndef OS_TIMERSTKSZ
+ #define OS_TIMERSTKSZ  50     // this stack size value is in words
+#endif
+ 
+//   <o>Timer Callback Queue size <1-32>
+//   <i> Number of concurrent active timer callback functions.
+//   <i> Default: 4
+#ifndef OS_TIMERCBQS
+ #define OS_TIMERCBQS   4
+#endif
+ 
+// </e>
+ 
+//   <o>ISR FIFO Queue size<4=>   4 entries  <8=>   8 entries
+//                         <12=> 12 entries  <16=> 16 entries
+//                         <24=> 24 entries  <32=> 32 entries
+//                         <48=> 48 entries  <64=> 64 entries
+//                         <96=> 96 entries
+//   <i> ISR functions store requests to this buffer,
+//   <i> when they are called from the interrupt handler.
+//   <i> Default: 16 entries
+#ifndef OS_FIFOSZ
+ #define OS_FIFOSZ      16
+#endif
+ 
+// </h>
+ 
+//------------- <<< end of configuration section >>> -----------------------
+ 
+// Standard library system mutexes
+// ===============================
+//  Define max. number system mutexes that are used to protect 
+//  the arm standard runtime library. For microlib they are not used.
+#ifndef OS_MUTEXCNT
+ #define OS_MUTEXCNT    8
+#endif
+ 
+/*----------------------------------------------------------------------------
+ *      RTX User configuration part END
+ *---------------------------------------------------------------------------*/
+ 
+#define OS_TRV          ((uint32_t)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1)
+ 
+
+/*----------------------------------------------------------------------------
+ *      Global Functions
+ *---------------------------------------------------------------------------*/
+ 
+/*--------------------------- os_idle_demon ---------------------------------*/
+
+/// \brief The idle demon is running when no other thread is ready to run
+void os_idle_demon (void) {
+ 
+  for (;;) {
+    /* HERE: include optional user code to be executed when no thread runs.*/
+  }
+}
+ 
+#if (OS_SYSTICK == 0)   // Functions for alternative timer as RTX kernel timer
+ 
+/*--------------------------- os_tick_init ----------------------------------*/
+ 
+/// \brief Initializes an alternative hardware timer as RTX kernel timer
+/// \return                             IRQ number of the alternative hardware timer
+int os_tick_init (void) {
+  return (-1);  /* Return IRQ number of timer (0..239) */
+}
+ 
+/*--------------------------- os_tick_val -----------------------------------*/
+ 
+/// \brief Get alternative hardware timer's current value (0 .. OS_TRV)
+/// \return                             Current value of the alternative hardware timer
+uint32_t os_tick_val (void) {
+  return (0);
+}
+ 
+/*--------------------------- os_tick_ovf -----------------------------------*/
+ 
+/// \brief Get alternative hardware timer's  overflow flag
+/// \return                             Overflow flag\n
+///                                     - 1 : overflow
+///                                     - 0 : no overflow
+uint32_t os_tick_ovf (void) {
+  return (0);
+}
+ 
+/*--------------------------- os_tick_irqack --------------------------------*/
+ 
+/// \brief Acknowledge alternative hardware timer interrupt
+void os_tick_irqack (void) {
+  /* ... */
+}
+ 
+#endif   // (OS_SYSTICK == 0)
+ 
+/*--------------------------- os_error --------------------------------------*/
+ 
+/* OS Error Codes */
+#define OS_ERROR_STACK_OVF      1
+#define OS_ERROR_FIFO_OVF       2
+#define OS_ERROR_MBX_OVF        3
+#define OS_ERROR_TIMER_OVF      4
+ 
+extern osThreadId svcThreadGetId (void);
+ 
+/// \brief Called when a runtime error is detected
+/// \param[in]   error_code   actual error code that has been detected
+void os_error (uint32_t error_code) {
+ 
+  /* HERE: include optional code to be executed on runtime error. */
+  switch (error_code) {
+    case OS_ERROR_STACK_OVF:
+      /* Stack overflow detected for the currently running task. */
+      /* Thread can be identified by calling svcThreadGetId().   */
+      break;
+    case OS_ERROR_FIFO_OVF:
+      /* ISR FIFO Queue buffer overflow detected. */
+      break;
+    case OS_ERROR_MBX_OVF:
+      /* Mailbox overflow detected. */
+      break;
+    case OS_ERROR_TIMER_OVF:
+      /* User Timer Callback Queue overflow detected. */
+      break;
+  }
+  for (;;);
+}
+ 
+
+/*----------------------------------------------------------------------------
+ *      RTX Configuration Functions
+ *---------------------------------------------------------------------------*/
+ 
+#include "RTX_CM_lib.h"
+ 
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/

CMSIS/Pack/Example/Boards/Keil/MCB1800/RTX_Blinky/RTE/Device/LPC1857/RTE_Device.h

@@ -0,0 +1,2358 @@
+/* -----------------------------------------------------------------------------
+ * Copyright (c) 2013-2015 ARM Ltd.
+ *
+ * This software is provided 'as-is', without any express or implied warranty.
+ * In no event will the authors be held liable for any damages arising from
+ * the use of this software. Permission is granted to anyone to use this
+ * software for any purpose, including commercial applications, and to alter
+ * it and redistribute it freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software in
+ *    a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ *
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ *
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * $Date:        5. March 2015
+ * $Revision:    V2.1.1
+ *
+ * Project:      RTE Device Configuration for NXP LPC18xx
+ * -------------------------------------------------------------------------- */
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+#ifndef __RTE_DEVICE_H
+#define __RTE_DEVICE_H
+
+
+// <e> USB0 Controller [Driver_USBD0 and Driver_USBH0]
+// <i> Configuration settings for Driver_USBD0 in component ::Drivers:USB Device
+// <i> Configuration settings for Driver_USBH0 in component ::Drivers:USB Host
+#define   RTE_USB_USB0                  0
+
+//   <h> Pin Configuration
+//     <o> USB0_PPWR (Host) <0=>Not used <1=>P1_7 <2=>P2_0 <3=>P2_3 <4=>P6_3
+//     <i> VBUS drive signal (towards external charge pump or power management unit).
+#define   RTE_USB0_PPWR_ID              4
+#if      (RTE_USB0_PPWR_ID == 0)
+  #define RTE_USB0_PPWR_PIN_EN          0
+#elif    (RTE_USB0_PPWR_ID == 1)
+  #define RTE_USB0_PPWR_PORT            1
+  #define RTE_USB0_PPWR_BIT             7
+  #define RTE_USB0_PPWR_FUNC            4
+#elif    (RTE_USB0_PPWR_ID == 2)
+  #define RTE_USB0_PPWR_PORT            2
+  #define RTE_USB0_PPWR_BIT             0
+  #define RTE_USB0_PPWR_FUNC            3
+#elif    (RTE_USB0_PPWR_ID == 3)
+  #define RTE_USB0_PPWR_PORT            2
+  #define RTE_USB0_PPWR_BIT             3
+  #define RTE_USB0_PPWR_FUNC            7
+#elif    (RTE_USB0_PPWR_ID == 4)
+  #define RTE_USB0_PPWR_PORT            6
+  #define RTE_USB0_PPWR_BIT             3
+  #define RTE_USB0_PPWR_FUNC            1
+#else
+  #error "Invalid RTE_USB0_PPWR Pin Configuration!"
+#endif
+#ifndef   RTE_USB0_PPWR_PIN_EN
+  #define RTE_USB0_PPWR_PIN_EN          1
+#endif
+//     <o> USB0_PWR_FAULT (Host) <0=>Not used <1=>P1_5 <2=>P2_1 <3=>P2_4 <4=>P6_6 <5=>P8_0
+//     <i> Port power fault signal indicating overcurrent condition.
+//     <i> This signal monitors over-current on the USB bus
+//        (external circuitry required to detect over-current condition).
+#define   RTE_USB0_PWR_FAULT_ID         4
+#if      (RTE_USB0_PWR_FAULT_ID == 0)
+  #define RTE_USB0_PWR_FAULT_PIN_EN     0
+#elif    (RTE_USB0_PWR_FAULT_ID == 1)
+  #define RTE_USB0_PWR_FAULT_PORT       1
+  #define RTE_USB0_PWR_FAULT_BIT        5
+  #define RTE_USB0_PWR_FAULT_FUNC       4
+#elif    (RTE_USB0_PWR_FAULT_ID == 2)
+  #define RTE_USB0_PWR_FAULT_PORT       2
+  #define RTE_USB0_PWR_FAULT_BIT        1
+  #define RTE_USB0_PWR_FAULT_FUNC       3
+#elif    (RTE_USB0_PWR_FAULT_ID == 3)
+  #define RTE_USB0_PWR_FAULT_PORT       2
+  #define RTE_USB0_PWR_FAULT_BIT        4
+  #define RTE_USB0_PWR_FAULT_FUNC       7
+#elif    (RTE_USB0_PWR_FAULT_ID == 4)
+  #define RTE_USB0_PWR_FAULT_PORT       6
+  #define RTE_USB0_PWR_FAULT_BIT        6
+  #define RTE_USB0_PWR_FAULT_FUNC       3
+#elif    (RTE_USB0_PWR_FAULT_ID == 5)
+  #define RTE_USB0_PWR_FAULT_PORT       8
+  #define RTE_USB0_PWR_FAULT_BIT        0
+  #define RTE_USB0_PWR_FAULT_FUNC       1
+#else
+  #error "Invalid RTE_USB0_PWR_FAULT Pin Configuration!"
+#endif
+#ifndef   RTE_USB0_PWR_FAULT_PIN_EN
+  #define RTE_USB0_PWR_FAULT_PIN_EN     1
+#endif
+//     <o> USB0_IND0 <0=>Not used <1=>P1_4 <2=>P2_5 <3=>P2_6 <4=>P6_8 <5=>P8_2
+//     <i> USB0 port indicator LED control output 0
+#define   RTE_USB0_IND0_ID              5
+#if      (RTE_USB0_IND0_ID == 0)
+  #define RTE_USB0_IND0_PIN_EN          0
+#elif    (RTE_USB0_IND0_ID == 1)
+  #define RTE_USB0_IND0_PORT            1
+  #define RTE_USB0_IND0_BIT             4
+  #define RTE_USB0_IND0_FUNC            4
+#elif    (RTE_USB0_IND0_ID == 2)
+  #define RTE_USB0_IND0_PORT            2
+  #define RTE_USB0_IND0_BIT             5
+  #define RTE_USB0_IND0_FUNC            7
+#elif    (RTE_USB0_IND0_ID == 3)
+  #define RTE_USB0_IND0_PORT            2
+  #define RTE_USB0_IND0_BIT             6
+  #define RTE_USB0_IND0_FUNC            3
+#elif    (RTE_USB0_IND0_ID == 4)
+  #define RTE_USB0_IND0_PORT            6
+  #define RTE_USB0_IND0_BIT             8
+  #define RTE_USB0_IND0_FUNC            3
+#elif    (RTE_USB0_IND0_ID == 5)
+  #define RTE_USB0_IND0_PORT            8
+  #define RTE_USB0_IND0_BIT             2
+  #define RTE_USB0_IND0_FUNC            1
+#else
+  #error "Invalid RTE_USB0_IND0 Pin Configuration!"
+#endif
+#ifndef   RTE_USB0_IND0_PIN_EN
+  #define RTE_USB0_IND0_PIN_EN          1
+#endif
+//     <o> USB0_IND1 <0=>Not used <1=>P1_3 <2=>P2_2 <3=>P6_7 <4=>P8_1
+//     <i> USB0 port indicator LED control output 1
+#define   RTE_USB0_IND1_ID              4
+#if      (RTE_USB0_IND1_ID == 0)
+  #define RTE_USB0_IND1_PIN_EN          0
+#elif    (RTE_USB0_IND1_ID == 1)
+  #define RTE_USB0_IND1_PORT            1
+  #define RTE_USB0_IND1_BIT             3
+  #define RTE_USB0_IND1_FUNC            4
+#elif    (RTE_USB0_IND1_ID == 2)
+  #define RTE_USB0_IND1_PORT            2
+  #define RTE_USB0_IND1_BIT             2
+  #define RTE_USB0_IND1_FUNC            3
+#elif    (RTE_USB0_IND1_ID == 3)
+  #define RTE_USB0_IND1_PORT            6
+  #define RTE_USB0_IND1_BIT             7
+  #define RTE_USB0_IND1_FUNC            3
+#elif    (RTE_USB0_IND1_ID == 4)
+  #define RTE_USB0_IND1_PORT            8
+  #define RTE_USB0_IND1_BIT             1
+  #define RTE_USB0_IND1_FUNC            1
+#else
+  #error "Invalid RTE_USB0_IND1 Pin Configuration!"
+#endif
+#ifndef   RTE_USB0_IND1_PIN_EN
+  #define RTE_USB0_IND1_PIN_EN          1
+#endif
+//   </h> Pin Configuration
+
+//   <h> Device [Driver_USBD0]
+//   <i> Configuration settings for Driver_USBD0 in component ::Drivers:USB Device
+//     <o.0> High-speed
+//     <i> Enable high-speed functionality
+#define   RTE_USB_USB0_HS_EN            1
+//   </h> Device [Driver_USBD0]
+// </e> USB0 Controller [Driver_USBD0 and Driver_USBH0]
+
+// <e> USB1 Controller [Driver_USBD1 and Driver_USBH1]
+// <i> Configuration settings for Driver_USBD1 in component ::Drivers:USB Device
+// <i> Configuration settings for Driver_USBH1 in component ::Drivers:USB Host
+#define   RTE_USB_USB1                  0
+
+//   <h> Pin Configuration
+//     <o> USB1_PPWR (Host) <0=>Not used <1=>P9_5
+//     <i> VBUS drive signal (towards external charge pump or power management unit).
+#define   RTE_USB1_PPWR_ID              1
+#if      (RTE_USB1_PPWR_ID == 0)
+  #define RTE_USB1_PPWR_PIN_EN          0
+#elif    (RTE_USB1_PPWR_ID == 1)
+  #define RTE_USB1_PPWR_PORT            9
+  #define RTE_USB1_PPWR_BIT             5
+  #define RTE_USB1_PPWR_FUNC            2
+#else
+  #error "Invalid RTE_USB1_PPWR Pin Configuration!"
+#endif
+#ifndef   RTE_USB1_PPWR_PIN_EN
+  #define RTE_USB1_PPWR_PIN_EN          1
+#endif
+//     <o> USB1_PWR_FAULT (Host) <0=>Not used <1=>P9_6
+//     <i> Port power fault signal indicating overcurrent condition.
+//     <i> This signal monitors over-current on the USB bus
+//        (external circuitry required to detect over-current condition).
+#define   RTE_USB1_PWR_FAULT_ID         1
+#if      (RTE_USB1_PWR_FAULT_ID == 0)
+  #define RTE_USB1_PWR_FAULT_PIN_EN     0
+#elif    (RTE_USB1_PWR_FAULT_ID == 1)
+  #define RTE_USB1_PWR_FAULT_PORT       9
+  #define RTE_USB1_PWR_FAULT_BIT        6
+  #define RTE_USB1_PWR_FAULT_FUNC       2
+#else
+  #error "Invalid RTE_USB1_PWR_FAULT Pin Configuration!"
+#endif
+#ifndef   RTE_USB1_PWR_FAULT_PIN_EN
+  #define RTE_USB1_PWR_FAULT_PIN_EN     1
+#endif
+//     <o> USB1_IND0 <0=>Not used <1=>P3_2 <2=>P9_4
+//     <i> USB1 port indicator LED control output 0
+#define   RTE_USB1_IND0_ID              2
+#if      (RTE_USB1_IND0_ID == 0)
+  #define RTE_USB1_IND0_PIN_EN          0
+#elif    (RTE_USB1_IND0_ID == 1)
+  #define RTE_USB1_IND0_PORT            3
+  #define RTE_USB1_IND0_BIT             2
+  #define RTE_USB1_IND0_FUNC            3
+#elif    (RTE_USB1_IND0_ID == 2)
+  #define RTE_USB1_IND0_PORT            9
+  #define RTE_USB1_IND0_BIT             4
+  #define RTE_USB1_IND0_FUNC            2
+#else
+  #error "Invalid RTE_USB1_IND0 Pin Configuration!"
+#endif
+#ifndef   RTE_USB1_IND0_PIN_EN
+  #define RTE_USB1_IND0_PIN_EN          1
+#endif
+//     <o> USB1_IND1 <0=>Not used <1=>P3_1 <2=>P9_3
+//     <i> USB1 port indicator LED control output 1
+#define   RTE_USB1_IND1_ID              2
+#if      (RTE_USB1_IND1_ID == 0)
+  #define RTE_USB1_IND1_PIN_EN          0
+#elif    (RTE_USB1_IND1_ID == 1)
+  #define RTE_USB1_IND1_PORT            3
+  #define RTE_USB1_IND1_BIT             1
+  #define RTE_USB1_IND1_FUNC            3
+#elif    (RTE_USB1_IND1_ID == 2)
+  #define RTE_USB1_IND1_PORT            9
+  #define RTE_USB1_IND1_BIT             3
+  #define RTE_USB1_IND1_FUNC            2
+#else
+  #error "Invalid RTE_USB1_IND1 Pin Configuration!"
+#endif
+#ifndef   RTE_USB1_IND1_PIN_EN
+  #define RTE_USB1_IND1_PIN_EN          1
+#endif
+
+//     <e> On-chip full-speed PHY
+#define   RTE_USB_USB1_FS_PHY_EN        1
+
+//       <o> USB1_VBUS (Device) <0=>Not used <1=>P2_5
+//       <i> Monitors the presence of USB1 bus power.
+#define   RTE_USB1_VBUS_ID              1
+#if      (RTE_USB1_VBUS_ID == 0)
+  #define RTE_USB1_VBUS_PIN_EN          0
+#elif    (RTE_USB1_VBUS_ID == 1)
+  #define RTE_USB1_VBUS_PORT            2
+  #define RTE_USB1_VBUS_BIT             5
+  #define RTE_USB1_VBUS_FUNC            2
+#else
+  #error "Invalid RTE_USB1_VBUS Pin Configuration!"
+#endif
+#ifndef   RTE_USB1_VBUS_PIN_EN
+  #define RTE_USB1_VBUS_PIN_EN          1
+#endif
+//     </e> On-chip full-speed PHY
+
+//     <e> External high-speed ULPI PHY (UTMI+ Low Pin Interface)
+#define   RTE_USB_USB1_HS_PHY_EN        0
+
+//       <o> USB1_ULPI_CLK <0=>P8_8 <1=>PC_0
+//       <i> USB1 ULPI link CLK signal.
+//       <i> 60 MHz clock generated by the PHY.
+#define   RTE_USB1_ULPI_CLK_ID          0
+#if      (RTE_USB1_ULPI_CLK_ID == 0)
+  #define RTE_USB1_ULPI_CLK_PORT        8
+  #define RTE_USB1_ULPI_CLK_BIT         8
+  #define RTE_USB1_ULPI_CLK_FUNC        1
+#elif    (RTE_USB1_ULPI_CLK_ID == 1)
+  #define RTE_USB1_ULPI_CLK_PORT        0xC
+  #define RTE_USB1_ULPI_CLK_BIT         0
+  #define RTE_USB1_ULPI_CLK_FUNC        1
+#else
+  #error "Invalid RTE_USB1_ULPI_CLK Pin Configuration!"
+#endif
+//       <o> USB1_ULPI_DIR <0=>PB_1 <1=>PC_11
+//       <i> USB1 ULPI link DIR signal.
+//       <i> Controls the ULPI data line direction.
+#define   RTE_USB1_ULPI_DIR_ID          0
+#if      (RTE_USB1_ULPI_DIR_ID == 0)
+  #define RTE_USB1_ULPI_DIR_PORT        0xB
+  #define RTE_USB1_ULPI_DIR_BIT         1
+  #define RTE_USB1_ULPI_DIR_FUNC        1
+#elif    (RTE_USB1_ULPI_DIR_ID == 1)
+  #define RTE_USB1_ULPI_DIR_PORT        0xC
+  #define RTE_USB1_ULPI_DIR_BIT         11
+  #define RTE_USB1_ULPI_DIR_FUNC        1
+#else
+  #error "Invalid RTE_USB1_ULPI_DIR Pin Configuration!"
+#endif
+//       <o> USB1_ULPI_STP <0=>P8_7 <1=>PC_10
+//       <i> USB1 ULPI link STP signal.
+//       <i> Asserted to end or interrupt transfers to the PHY.
+#define   RTE_USB1_ULPI_STP_ID          0
+#if      (RTE_USB1_ULPI_STP_ID == 0)
+  #define RTE_USB1_ULPI_STP_PORT        8
+  #define RTE_USB1_ULPI_STP_BIT         7
+  #define RTE_USB1_ULPI_STP_FUNC        1
+#elif    (RTE_USB1_ULPI_STP_ID == 1)
+  #define RTE_USB1_ULPI_STP_PORT        0xC
+  #define RTE_USB1_ULPI_STP_BIT         10
+  #define RTE_USB1_ULPI_STP_FUNC        1
+#else
+  #error "Invalid RTE_USB1_ULPI_STP Pin Configuration!"
+#endif
+//       <o> USB1_ULPI_NXT <0=>P8_6 <1=>PC_9
+//       <i> USB1 ULPI link NXT signal.
+//       <i> Data flow control signal from the PHY.
+#define   RTE_USB1_ULPI_NXT_ID          0
+#if      (RTE_USB1_ULPI_NXT_ID == 0)
+  #define RTE_USB1_ULPI_NXT_PORT        8
+  #define RTE_USB1_ULPI_NXT_BIT         6
+  #define RTE_USB1_ULPI_NXT_FUNC        1
+#elif    (RTE_USB1_ULPI_NXT_ID == 1)
+  #define RTE_USB1_ULPI_NXT_PORT        0xC
+  #define RTE_USB1_ULPI_NXT_BIT         9
+  #define RTE_USB1_ULPI_NXT_FUNC        1
+#else
+  #error "Invalid RTE_USB1_ULPI_NXT Pin Configuration!"
+#endif
+//       <o> USB1_ULPI_D0 <0=>P8_5 <1=>PC_8 <2=>PD_11
+//       <i> USB1 ULPI link bidirectional data line 0.
+#define   RTE_USB1_ULPI_D0_ID           0
+#if      (RTE_USB1_ULPI_D0_ID == 0)
+  #define RTE_USB1_ULPI_D0_PORT         8
+  #define RTE_USB1_ULPI_D0_BIT          5
+  #define RTE_USB1_ULPI_D0_FUNC         1
+#elif    (RTE_USB1_ULPI_D0_ID == 1)
+  #define RTE_USB1_ULPI_D0_PORT         0xC
+  #define RTE_USB1_ULPI_D0_BIT          8
+  #define RTE_USB1_ULPI_D0_FUNC         1
+#elif    (RTE_USB1_ULPI_D0_ID == 2)
+  #define RTE_USB1_ULPI_D0_PORT         0xD
+  #define RTE_USB1_ULPI_D0_BIT          11
+  #define RTE_USB1_ULPI_D0_FUNC         5
+#else
+  #error "Invalid RTE_USB1_ULPI_D0 Pin Configuration!"
+#endif
+//       <o> USB1_ULPI_D1 <0=>P8_4 <1=>PC_7
+//       <i> USB1 ULPI link bidirectional data line 1.
+#define   RTE_USB1_ULPI_D1_ID           0
+#if      (RTE_USB1_ULPI_D1_ID == 0)
+  #define RTE_USB1_ULPI_D1_PORT         8
+  #define RTE_USB1_ULPI_D1_BIT          4
+  #define RTE_USB1_ULPI_D1_FUNC         1
+#elif    (RTE_USB1_ULPI_D1_ID == 1)
+  #define RTE_USB1_ULPI_D1_PORT         0xC
+  #define RTE_USB1_ULPI_D1_BIT          7
+  #define RTE_USB1_ULPI_D1_FUNC         1
+#else
+  #error "Invalid RTE_USB1_ULPI_D1 Pin Configuration!"
+#endif
+//       <o> USB1_ULPI_D2 <0=>P8_3 <1=>PC_6
+//       <i> USB1 ULPI link bidirectional data line 2.
+#define   RTE_USB1_ULPI_D2_ID           0
+#if      (RTE_USB1_ULPI_D2_ID == 0)
+  #define RTE_USB1_ULPI_D2_PORT         8
+  #define RTE_USB1_ULPI_D2_BIT          3
+  #define RTE_USB1_ULPI_D2_FUNC         1
+#elif    (RTE_USB1_ULPI_D2_ID == 1)
+  #define RTE_USB1_ULPI_D2_PORT         0xC
+  #define RTE_USB1_ULPI_D2_BIT          6
+  #define RTE_USB1_ULPI_D2_FUNC         1
+#else
+  #error "Invalid RTE_USB1_ULPI_D2 Pin Configuration!"
+#endif
+//       <o> USB1_ULPI_D3 <0=>PB_6 <1=>PC_5
+//       <i> USB1 ULPI link bidirectional data line 3.
+#define   RTE_USB1_ULPI_D3_ID           0
+#if      (RTE_USB1_ULPI_D3_ID == 0)
+  #define RTE_USB1_ULPI_D3_PORT         0xB
+  #define RTE_USB1_ULPI_D3_BIT          6
+  #define RTE_USB1_ULPI_D3_FUNC         1
+#elif    (RTE_USB1_ULPI_D3_ID == 1)
+  #define RTE_USB1_ULPI_D3_PORT         0xC
+  #define RTE_USB1_ULPI_D3_BIT          5
+  #define RTE_USB1_ULPI_D3_FUNC         1
+#else
+  #error "Invalid RTE_USB1_ULPI_D3 Pin Configuration!"
+#endif
+//       <o> USB1_ULPI_D4 <0=>PB_5 <1=>PC_4
+//       <i> USB1 ULPI link bidirectional data line 4.
+#define   RTE_USB1_ULPI_D4_ID           0
+#if      (RTE_USB1_ULPI_D4_ID == 0)
+  #define RTE_USB1_ULPI_D4_PORT         0xB
+  #define RTE_USB1_ULPI_D4_BIT          5
+  #define RTE_USB1_ULPI_D4_FUNC         1
+#elif    (RTE_USB1_ULPI_D4_ID == 1)
+  #define RTE_USB1_ULPI_D4_PORT         0xC
+  #define RTE_USB1_ULPI_D4_BIT          4
+  #define RTE_USB1_ULPI_D4_FUNC         1
+#else
+  #error "Invalid RTE_USB1_ULPI_D4 Pin Configuration!"
+#endif
+//       <o> USB1_ULPI_D5 <0=>PB_4 <1=>PC_3
+//       <i> USB1 ULPI link bidirectional data line 5.
+#define   RTE_USB1_ULPI_D5_ID           0
+#if      (RTE_USB1_ULPI_D5_ID == 0)
+  #define RTE_USB1_ULPI_D5_PORT         0xB
+  #define RTE_USB1_ULPI_D5_BIT          4
+  #define RTE_USB1_ULPI_D5_FUNC         1
+#elif    (RTE_USB1_ULPI_D5_ID == 1)
+  #define RTE_USB1_ULPI_D5_PORT         0xC
+  #define RTE_USB1_ULPI_D5_BIT          3
+  #define RTE_USB1_ULPI_D5_FUNC         0
+#else
+  #error "Invalid RTE_USB1_ULPI_D5 Pin Configuration!"
+#endif
+//       <o> USB1_ULPI_D6 <0=>PB_3 <1=>PC_2
+//       <i> USB1 ULPI link bidirectional data line 6.
+#define   RTE_USB1_ULPI_D6_ID           0
+#if      (RTE_USB1_ULPI_D6_ID == 0)
+  #define RTE_USB1_ULPI_D6_PORT         0xB
+  #define RTE_USB1_ULPI_D6_BIT          3
+  #define RTE_USB1_ULPI_D6_FUNC         1
+#elif    (RTE_USB1_ULPI_D6_ID == 1)
+  #define RTE_USB1_ULPI_D6_PORT         0xC
+  #define RTE_USB1_ULPI_D6_BIT          2
+  #define RTE_USB1_ULPI_D6_FUNC         0
+#else
+  #error "Invalid RTE_USB1_ULPI_D6 Pin Configuration!"
+#endif
+//       <o> USB1_ULPI_D7 <0=>PB_2 <1=>PC_1
+//       <i> USB1 ULPI link bidirectional data line 7.
+#define   RTE_USB1_ULPI_D7_ID           0
+#if      (RTE_USB1_ULPI_D7_ID == 0)
+  #define RTE_USB1_ULPI_D7_PORT         0xB
+  #define RTE_USB1_ULPI_D7_BIT          2
+  #define RTE_USB1_ULPI_D7_FUNC         1
+#elif    (RTE_USB1_ULPI_D7_ID == 1)
+  #define RTE_USB1_ULPI_D7_PORT         0xC
+  #define RTE_USB1_ULPI_D7_BIT          1
+  #define RTE_USB1_ULPI_D7_FUNC         0
+#else
+  #error "Invalid RTE_USB1_ULPI_D7 Pin Configuration!"
+#endif
+//     </e> External high-speed ULPI PHY (UTMI+ Low Pin Interface)
+//   </h> Pin Configuration
+// </e> USB1 Controller [Driver_USBD1 and Driver_USBH1]
+
+// <e> ENET (Ethernet Interface) [Driver_ETH_MAC0]
+// <i> Configuration settings for Driver_ETH_MAC0 in component ::Drivers:Ethernet MAC
+#define   RTE_ENET                      0
+
+//   <e> MII (Media Independent Interface)
+#define   RTE_ENET_MII                  0
+
+//     <o> ENET_TXD0 Pin <0=>P1_18
+#define   RTE_ENET_MII_TXD0_PORT_ID     0
+#if      (RTE_ENET_MII_TXD0_PORT_ID == 0)
+  #define RTE_ENET_MII_TXD0_PORT        1
+  #define RTE_ENET_MII_TXD0_PIN         18
+  #define RTE_ENET_MII_TXD0_FUNC        3
+#else
+  #error "Invalid ENET_TXD0 Pin Configuration!"
+#endif
+//     <o> ENET_TXD1 Pin <0=>P1_20
+#define   RTE_ENET_MII_TXD1_PORT_ID     0
+#if      (RTE_ENET_MII_TXD1_PORT_ID == 0)
+  #define RTE_ENET_MII_TXD1_PORT        1
+  #define RTE_ENET_MII_TXD1_PIN         20
+  #define RTE_ENET_MII_TXD1_FUNC        3
+#else
+  #error "Invalid ENET_TXD1 Pin Configuration!"
+#endif
+//     <o> ENET_TXD2 Pin <0=>P9_4 <1=>PC_2
+#define   RTE_ENET_MII_TXD2_PORT_ID     0
+#if      (RTE_ENET_MII_TXD2_PORT_ID == 0)
+  #define RTE_ENET_MII_TXD2_PORT        9
+  #define RTE_ENET_MII_TXD2_PIN         4
+  #define RTE_ENET_MII_TXD2_FUNC        5
+#elif    (RTE_ENET_MII_TXD2_PORT_ID == 1)
+  #define RTE_ENET_MII_TXD2_PORT        0xC
+  #define RTE_ENET_MII_TXD2_PIN         2
+  #define RTE_ENET_MII_TXD2_FUNC        3
+#else
+  #error "Invalid ENET_TXD2 Pin Configuration!"
+#endif
+//     <o> ENET_TXD3 Pin <0=>P9_5 <1=>PC_3
+#define   RTE_ENET_MII_TXD3_PORT_ID     0
+#if      (RTE_ENET_MII_TXD3_PORT_ID == 0)
+  #define RTE_ENET_MII_TXD3_PORT        9
+  #define RTE_ENET_MII_TXD3_PIN         5
+  #define RTE_ENET_MII_TXD3_FUNC        5
+#elif    (RTE_ENET_MII_TXD3_PORT_ID == 1)
+  #define RTE_ENET_MII_TXD3_PORT        0xC
+  #define RTE_ENET_MII_TXD3_PIN         3
+  #define RTE_ENET_MII_TXD3_FUNC        3
+#else
+  #error "Invalid ENET_TXD3 Pin Configuration!"
+#endif
+//     <o> ENET_TX_EN Pin <0=>P0_1 <1=>PC_4
+#define   RTE_ENET_MII_TX_EN_PORT_ID    0
+#if      (RTE_ENET_MII_TX_EN_PORT_ID == 0)
+  #define RTE_ENET_MII_TX_EN_PORT       0
+  #define RTE_ENET_MII_TX_EN_PIN        1
+  #define RTE_ENET_MII_TX_EN_FUNC       6
+#elif    (RTE_ENET_MII_TX_EN_PORT_ID == 1)
+  #define RTE_ENET_MII_TX_EN_PORT       0xC
+  #define RTE_ENET_MII_TX_EN_PIN        4
+  #define RTE_ENET_MII_TX_EN_FUNC       3
+#else
+  #error "Invalid ENET_TX_EN Pin Configuration!"
+#endif
+//     <o> ENET_TX_CLK Pin <0=>P1_19 <1=>CLK0
+#define   RTE_ENET_MII_TX_CLK_PORT_ID   0
+#if      (RTE_ENET_MII_TX_CLK_PORT_ID == 0)
+  #define RTE_ENET_MII_TX_CLK_PORT      1
+  #define RTE_ENET_MII_TX_CLK_PIN       19
+  #define RTE_ENET_MII_TX_CLK_FUNC      0
+#elif    (RTE_ENET_MII_TX_CLK_PORT_ID == 1)
+  #define RTE_ENET_MII_TX_CLK_PORT      0x10
+  #define RTE_ENET_MII_TX_CLK_PIN       0
+  #define RTE_ENET_MII_TX_CLK_FUNC      7
+#else
+  #error "Invalid ENET_TX_CLK Pin Configuration!"
+#endif
+//     <o> ENET_TX_ER Pin <0=>Not used <1=>PC_5 <2=>PC_14
+//     <i> Optional signal, rarely used
+#define   RTE_ENET_MII_TX_ER_PORT_ID    0
+#if      (RTE_ENET_MII_TX_ER_PORT_ID == 0)
+  #define RTE_ENET_MII_TX_ER_PIN_EN     0
+#elif    (RTE_ENET_MII_TX_ER_PORT_ID == 1)
+  #define RTE_ENET_MII_TX_ER_PORT       0xC
+  #define RTE_ENET_MII_TX_ER_PIN        5
+  #define RTE_ENET_MII_TX_ER_FUNC       3
+#elif    (RTE_ENET_MII_TX_ER_PORT_ID == 2)
+  #define RTE_ENET_MII_TX_ER_PORT       0xC
+  #define RTE_ENET_MII_TX_ER_PIN        14
+  #define RTE_ENET_MII_TX_ER_FUNC       6
+#else
+  #error "Invalid ENET_TX_ER Pin Configuration!"
+#endif
+#ifndef   RTE_ENET_MII_TX_ER_PIN_EN
+  #define RTE_ENET_MII_TX_ER_PIN_EN     1
+#endif
+//     <o> ENET_RXD0 Pin <0=>P1_15
+#define   RTE_ENET_MII_RXD0_PORT_ID     0
+#if      (RTE_ENET_MII_RXD0_PORT_ID == 0)
+  #define RTE_ENET_MII_RXD0_PORT        1
+  #define RTE_ENET_MII_RXD0_PIN         15
+  #define RTE_ENET_MII_RXD0_FUNC        3
+#else
+  #error "Invalid ENET_RXD0 Pin Configuration!"
+#endif
+//     <o> ENET_RXD1 Pin <0=>P0_0
+#define   RTE_ENET_MII_RXD1_PORT_ID     0
+#if      (RTE_ENET_MII_RXD1_PORT_ID == 0)
+  #define RTE_ENET_MII_RXD1_PORT        0
+  #define RTE_ENET_MII_RXD1_PIN         0
+  #define RTE_ENET_MII_RXD1_FUNC        2
+#else
+  #error "Invalid ENET_RXD1 Pin Configuration!"
+#endif
+//     <o> ENET_RXD2 Pin <0=>P9_3 <1=>PC_6
+#define   RTE_ENET_MII_RXD2_PORT_ID     0
+#if      (RTE_ENET_MII_RXD2_PORT_ID == 0)
+  #define RTE_ENET_MII_RXD2_PORT        9
+  #define RTE_ENET_MII_RXD2_PIN         3
+  #define RTE_ENET_MII_RXD2_FUNC        5
+#elif    (RTE_ENET_MII_RXD2_PORT_ID == 1)
+  #define RTE_ENET_MII_RXD2_PORT        0xC
+  #define RTE_ENET_MII_RXD2_PIN         6
+  #define RTE_ENET_MII_RXD2_FUNC        3
+#else
+  #error "Invalid ENET_RXD2 Pin Configuration!"
+#endif
+//     <o> ENET_RXD3 Pin <0=>P9_2 <1=>PC_7
+#define   RTE_ENET_MII_RXD3_PORT_ID     0
+#if      (RTE_ENET_MII_RXD3_PORT_ID == 0)
+  #define RTE_ENET_MII_RXD3_PORT        9
+  #define RTE_ENET_MII_RXD3_PIN         2
+  #define RTE_ENET_MII_RXD3_FUNC        5
+#elif    (RTE_ENET_MII_RXD3_PORT_ID == 1)
+  #define RTE_ENET_MII_RXD3_PORT        0xC
+  #define RTE_ENET_MII_RXD3_PIN         7
+  #define RTE_ENET_MII_RXD3_FUNC        3
+#else
+  #error "Invalid ENET_RXD3 Pin Configuration!"
+#endif
+//     <o> ENET_RX_DV Pin <0=>P1_16 <1=>PC_8
+#define   RTE_ENET_MII_RX_DV_PORT_ID    0
+#if      (RTE_ENET_MII_RX_DV_PORT_ID == 0)
+  #define RTE_ENET_MII_RX_DV_PORT       1
+  #define RTE_ENET_MII_RX_DV_PIN        16
+  #define RTE_ENET_MII_RX_DV_FUNC       7
+#elif    (RTE_ENET_MII_RX_DV_PORT_ID == 1)
+  #define RTE_ENET_MII_RX_DV_PORT       0xC
+  #define RTE_ENET_MII_RX_DV_PIN        8
+  #define RTE_ENET_MII_RX_DV_FUNC       3
+#else
+  #error "Invalid ENET_RX_DV Pin Configuration!"
+#endif
+//     <o> ENET_RX_CLK Pin <0=>PC_0
+#define   RTE_ENET_MII_RX_CLK_PORT_ID   0
+#if      (RTE_ENET_MII_RX_CLK_PORT_ID == 0)
+  #define RTE_ENET_MII_RX_CLK_PORT      0xC
+  #define RTE_ENET_MII_RX_CLK_PIN       0
+  #define RTE_ENET_MII_RX_CLK_FUNC      3
+#else
+  #error "Invalid ENET_RX_CLK Pin Configuration!"
+#endif
+//     <o> ENET_RX_ER Pin <0=>P9_1 <1=>PC_9
+#define   RTE_ENET_MII_RX_ER_PORT_ID    0
+#if      (RTE_ENET_MII_RX_ER_PORT_ID == 0)
+  #define RTE_ENET_MII_RX_ER_PORT       9
+  #define RTE_ENET_MII_RX_ER_PIN        1
+  #define RTE_ENET_MII_RX_ER_FUNC       5
+#elif    (RTE_ENET_MII_RX_ER_PORT_ID == 1)
+  #define RTE_ENET_MII_RX_ER_PORT       0xC
+  #define RTE_ENET_MII_RX_ER_PIN        9
+  #define RTE_ENET_MII_RX_ER_FUNC       3
+#else
+  #error "Invalid ENET_RX_ER Pin Configuration!"
+#endif
+//     <o> ENET_COL Pin <0=>P0_1 <1=>P4_1 <2=>P9_6
+#define   RTE_ENET_MII_COL_PORT_ID      0
+#if      (RTE_ENET_MII_COL_PORT_ID == 0)
+  #define RTE_ENET_MII_COL_PORT         0
+  #define RTE_ENET_MII_COL_PIN          1
+  #define RTE_ENET_MII_COL_FUNC         2
+#elif    (RTE_ENET_MII_COL_PORT_ID == 1)
+  #define RTE_ENET_MII_COL_PORT         4
+  #define RTE_ENET_MII_COL_PIN          1
+  #define RTE_ENET_MII_COL_FUNC         7
+#elif    (RTE_ENET_MII_COL_PORT_ID == 2)
+  #define RTE_ENET_MII_COL_PORT         9
+  #define RTE_ENET_MII_COL_PIN          6
+  #define RTE_ENET_MII_COL_FUNC         5
+#else
+  #error "Invalid ENET_COL Pin Configuration!"
+#endif
+//     <o> ENET_CRS Pin <0=>P1_16 <1=>P9_0
+#define   RTE_ENET_MII_CRS_PORT_ID      0
+#if      (RTE_ENET_MII_CRS_PORT_ID == 0)
+  #define RTE_ENET_MII_CRS_PORT         1
+  #define RTE_ENET_MII_CRS_PIN          16
+  #define RTE_ENET_MII_CRS_FUNC         3
+#elif    (RTE_ENET_MII_CRS_PORT_ID == 1)
+  #define RTE_ENET_MII_CRS_PORT         9
+  #define RTE_ENET_MII_CRS_PIN          0
+  #define RTE_ENET_MII_CRS_FUNC         5
+#else
+  #error "Invalid ENET_CRS Pin Configuration!"
+#endif
+//   </e> MII (Media Independent Interface)
+
+//   <e> RMII (Reduced Media Independent Interface)
+#define   RTE_ENET_RMII                 1
+
+//     <o> ENET_TXD0 Pin <0=>P1_18
+#define   RTE_ENET_RMII_TXD0_PORT_ID    0
+#if      (RTE_ENET_RMII_TXD0_PORT_ID == 0)
+  #define RTE_ENET_RMII_TXD0_PORT       1
+  #define RTE_ENET_RMII_TXD0_PIN        18
+  #define RTE_ENET_RMII_TXD0_FUNC       3
+#else
+  #error "Invalid ENET_TXD0 Pin Configuration!"
+#endif
+//     <o> ENET_TXD1 Pin <0=>P1_20
+#define   RTE_ENET_RMII_TXD1_PORT_ID    0
+#if      (RTE_ENET_RMII_TXD1_PORT_ID == 0)
+  #define RTE_ENET_RMII_TXD1_PORT       1
+  #define RTE_ENET_RMII_TXD1_PIN        20
+  #define RTE_ENET_RMII_TXD1_FUNC       3
+#else
+  #error "Invalid ENET_TXD1 Pin Configuration!"
+#endif
+//     <o> ENET_TX_EN Pin <0=>P0_1 <1=>PC_4
+#define   RTE_ENET_RMII_TX_EN_PORT_ID   0
+#if      (RTE_ENET_RMII_TX_EN_PORT_ID == 0)
+  #define RTE_ENET_RMII_TX_EN_PORT      0
+  #define RTE_ENET_RMII_TX_EN_PIN       1
+  #define RTE_ENET_RMII_TX_EN_FUNC      6
+#elif    (RTE_ENET_RMII_TX_EN_PORT_ID == 1)
+  #define RTE_ENET_RMII_TX_EN_PORT      0xC
+  #define RTE_ENET_RMII_TX_EN_PIN       4
+  #define RTE_ENET_RMII_TX_EN_FUNC      3
+#else
+  #error "Invalid ENET_TX_EN Pin Configuration!"
+#endif
+//     <o> ENET_REF_CLK Pin <0=>P1_19 <1=>CLK0
+#define   RTE_ENET_RMII_REF_CLK_PORT_ID 0
+#if      (RTE_ENET_RMII_REF_CLK_PORT_ID == 0)
+  #define RTE_ENET_RMII_REF_CLK_PORT    1
+  #define RTE_ENET_RMII_REF_CLK_PIN     19
+  #define RTE_ENET_RMII_REF_CLK_FUNC    0
+#elif    (RTE_ENET_RMII_REF_CLK_PORT_ID == 1)
+  #define RTE_ENET_RMII_REF_CLK_PORT    0x10
+  #define RTE_ENET_RMII_REF_CLK_PIN     0
+  #define RTE_ENET_RMII_REF_CLK_FUNC    7
+#else
+  #error "Invalid ENET_REF_CLK Pin Configuration!"
+#endif
+//     <o> ENET_RXD0 Pin <0=>P1_15
+#define   RTE_ENET_RMII_RXD0_PORT_ID    0
+#if      (RTE_ENET_RMII_RXD0_PORT_ID == 0)
+  #define RTE_ENET_RMII_RXD0_PORT       1
+  #define RTE_ENET_RMII_RXD0_PIN        15
+  #define RTE_ENET_RMII_RXD0_FUNC       3
+#else
+  #error "Invalid ENET_RXD0 Pin Configuration!"
+#endif
+//     <o> ENET_RXD1 Pin <0=>P0_0
+#define   RTE_ENET_RMII_RXD1_PORT_ID    0
+#if      (RTE_ENET_RMII_RXD1_PORT_ID == 0)
+  #define RTE_ENET_RMII_RXD1_PORT       0
+  #define RTE_ENET_RMII_RXD1_PIN        0
+  #define RTE_ENET_RMII_RXD1_FUNC       2
+#else
+  #error "Invalid ENET_RXD1 Pin Configuration!"
+#endif
+//     <o> ENET_RX_DV Pin <0=>P1_16 <1=>PC_8
+#define   RTE_ENET_RMII_RX_DV_PORT_ID   0
+#if      (RTE_ENET_RMII_RX_DV_PORT_ID == 0)
+  #define RTE_ENET_RMII_RX_DV_PORT      1
+  #define RTE_ENET_RMII_RX_DV_PIN       16
+  #define RTE_ENET_RMII_RX_DV_FUNC      7
+#elif    (RTE_ENET_RMII_RX_DV_PORT_ID == 1)
+  #define RTE_ENET_RMII_RX_DV_PORT      0xC
+  #define RTE_ENET_RMII_RX_DV_PIN       8
+  #define RTE_ENET_RMII_RX_DV_FUNC      3
+#else
+  #error "Invalid ENET_RX_DV Pin Configuration!"
+#endif
+//   </e> RMII (Reduced Media Independent Interface)
+
+//   <h> MIIM (Management Data Interface)
+//     <o> ENET_MDIO Pin <0=>P1_17
+#define   RTE_ENET_MDI_MDIO_PORT_ID     0
+#if      (RTE_ENET_MDI_MDIO_PORT_ID == 0)
+  #define RTE_ENET_MDI_MDIO_PORT        1
+  #define RTE_ENET_MDI_MDIO_PIN         17
+  #define RTE_ENET_MDI_MDIO_FUNC        3
+#else
+  #error "Invalid ENET_MDIO Pin Configuration!"
+#endif
+//     <o> ENET_MDC Pin <0=>P2_0 <1=>P7_7 <2=>PC_1
+#define   RTE_ENET_MDI_MDC_PORT_ID      2
+#if      (RTE_ENET_MDI_MDC_PORT_ID == 0)
+  #define RTE_ENET_MDI_MDC_PORT         2
+  #define RTE_ENET_MDI_MDC_PIN          0
+  #define RTE_ENET_MDI_MDC_FUNC         7
+#elif    (RTE_ENET_MDI_MDC_PORT_ID == 1)
+  #define RTE_ENET_MDI_MDC_PORT         7
+  #define RTE_ENET_MDI_MDC_PIN          7
+  #define RTE_ENET_MDI_MDC_FUNC         6
+#elif    (RTE_ENET_MDI_MDC_PORT_ID == 2)
+  #define RTE_ENET_MDI_MDC_PORT         0xC
+  #define RTE_ENET_MDI_MDC_PIN          1
+  #define RTE_ENET_MDI_MDC_FUNC         3
+#else
+  #error "Invalid ENET_MDC Pin Configuration!"
+#endif
+//   </h> MIIM (Management Data Interface)
+// </e> ENET (Ethernet Interface) [Driver_ETH_MAC0]
+
+// <e> SD/MMC Interface [Driver_MCI0]
+// <i> Configuration settings for Driver_MCI0 in component ::Drivers:MCI
+#define RTE_SDMMC                       0
+
+//   <h> SD/MMC Peripheral Bus
+//     <o> SD_CLK Pin <0=>PC_0 <1=>CLK0 <2=>CLK2
+#define   RTE_SD_CLK_PORT_ID            0
+#if      (RTE_SD_CLK_PORT_ID == 0)
+  #define RTE_SD_CLK_PORT               0xC
+  #define RTE_SD_CLK_PIN                0
+  #define RTE_SD_CLK_FUNC               7
+#elif    (RTE_SD_CLK_PORT_ID == 1)
+  #define RTE_SD_CLK_PORT               0x10
+  #define RTE_SD_CLK_PIN                0
+  #define RTE_SD_CLK_FUNC               4
+#elif    (RTE_SD_CLK_PORT_ID == 2)
+  #define RTE_SD_CLK_PORT               0x10
+  #define RTE_SD_CLK_PIN                2
+  #define RTE_SD_CLK_FUNC               4
+#else
+  #error "Invalid SD_CLK Pin Configuration!"
+#endif
+//     <o> SD_CMD Pin <0=>P1_6 <1=>PC_10
+#define   RTE_SD_CMD_PORT_ID            1
+#if      (RTE_SD_CMD_PORT_ID == 0)
+  #define RTE_SD_CMD_PORT               1
+  #define RTE_SD_CMD_PIN                6
+  #define RTE_SD_CMD_FUNC               7
+#elif    (RTE_SD_CMD_PORT_ID == 1)
+  #define RTE_SD_CMD_PORT               0xC
+  #define RTE_SD_CMD_PIN                10
+  #define RTE_SD_CMD_FUNC               7
+#else
+  #error "Invalid SD_CMD Pin Configuration!"
+#endif
+//     <o> SD_DAT0 Pin <0=>P1_9 <1=>PC_4
+#define   RTE_SD_DAT0_PORT_ID           1
+#if      (RTE_SD_DAT0_PORT_ID == 0)
+  #define RTE_SD_DAT0_PORT              1
+  #define RTE_SD_DAT0_PIN               9
+  #define RTE_SD_DAT0_FUNC              7
+#elif    (RTE_SD_DAT0_PORT_ID == 1)
+  #define RTE_SD_DAT0_PORT              0xC
+  #define RTE_SD_DAT0_PIN               4
+  #define RTE_SD_DAT0_FUNC              7
+#else
+  #error "Invalid SD_DAT0 Pin Configuration!"
+#endif
+//     <e> SD_DAT[1 .. 3]
+#define   RTE_SDMMC_BUS_WIDTH_4         1
+//       <o> SD_DAT1 Pin <0=>P1_10 <1=>PC_5
+#define   RTE_SD_DAT1_PORT_ID           1
+#if      (RTE_SD_DAT1_PORT_ID == 0)
+  #define RTE_SD_DAT1_PORT              1
+  #define RTE_SD_DAT1_PIN               10
+  #define RTE_SD_DAT1_FUNC              7
+#elif    (RTE_SD_DAT1_PORT_ID == 1)
+  #define RTE_SD_DAT1_PORT              0xC
+  #define RTE_SD_DAT1_PIN               5
+  #define RTE_SD_DAT1_FUNC              7
+#else
+  #error "Invalid SD_DAT1 Pin Configuration!"
+#endif
+//       <o> SD_DAT2 Pin <0=>P1_11 <1=>PC_6
+#define   RTE_SD_DAT2_PORT_ID           1
+#if      (RTE_SD_DAT2_PORT_ID == 0)
+  #define RTE_SD_DAT2_PORT              1
+  #define RTE_SD_DAT2_PIN               11
+  #define RTE_SD_DAT2_FUNC              7
+#elif    (RTE_SD_DAT2_PORT_ID == 1)
+  #define RTE_SD_DAT2_PORT              0xC
+  #define RTE_SD_DAT2_PIN               6
+  #define RTE_SD_DAT2_FUNC              7
+#else
+  #error "Invalid SD_DAT2 Pin Configuration!"
+#endif
+//       <o> SD_DAT3 Pin <0=>P1_12 <1=>PC_7
+#define   RTE_SD_DAT3_PORT_ID           1
+#if      (RTE_SD_DAT3_PORT_ID == 0)
+  #define RTE_SD_DAT3_PORT              1
+  #define RTE_SD_DAT3_PIN               12
+  #define RTE_SD_DAT3_FUNC              7
+#elif    (RTE_SD_DAT3_PORT_ID == 1)
+  #define RTE_SD_DAT3_PORT              0xC
+  #define RTE_SD_DAT3_PIN               7
+  #define RTE_SD_DAT3_FUNC              7
+#else
+  #error "Invalid SD_DAT3 Pin Configuration!"
+#endif
+//     </e> SD_DAT[1 .. 3]
+//     <e> SD_DAT[4 .. 7]
+#define   RTE_SDMMC_BUS_WIDTH_8         0
+//       <o> SD_DAT4 Pin <0=>PC_11
+#define   RTE_SD_DAT4_PORT_ID           0
+#if      (RTE_SD_DAT4_PORT_ID == 0)
+  #define RTE_SD_DAT4_PORT              0xC
+  #define RTE_SD_DAT4_PIN               11
+  #define RTE_SD_DAT4_FUNC              7
+#else
+  #error "Invalid SD_DAT4 Pin Configuration!"
+#endif
+//       <o> SD_DAT5 Pin <0=>PC_12
+#define   RTE_SD_DAT5_PORT_ID           0
+#if      (RTE_SD_DAT5_PORT_ID == 0)
+  #define RTE_SD_DAT5_PORT              0xC
+  #define RTE_SD_DAT5_PIN               12
+  #define RTE_SD_DAT5_FUNC              7
+#else
+  #error "Invalid SD_DAT5 Pin Configuration!"
+#endif
+//       <o> SD_DAT6 Pin <0=>PC_13
+#define   RTE_SD_DAT6_PORT_ID           0
+#if      (RTE_SD_DAT6_PORT_ID == 0)
+  #define RTE_SD_DAT6_PORT              0xC
+  #define RTE_SD_DAT6_PIN               13
+  #define RTE_SD_DAT6_FUNC              7
+#else
+  #error "Invalid SD_DAT6 Pin Configuration!"
+#endif
+//       <o> SD_DAT7 Pin <0=>PC_14
+#define   RTE_SD_DAT7_PORT_ID           0
+#if      (RTE_SD_DAT7_PORT_ID == 0)
+  #define RTE_SD_DAT7_PORT              0xC
+  #define RTE_SD_DAT7_PIN               14
+  #define RTE_SD_DAT7_FUNC              7
+#else
+  #error "Invalid SD_DAT7 Pin Configuration!"
+#endif
+//     </e> SD_DAT[4 .. 7]
+//   </h> SD/MMC Peripheral Bus
+
+//   <o> SD_CD (Card Detect) Pin <0=>Not used <1=>P1_13 <2=>PC_8
+//   <i> Configure Pin if exists
+#define   RTE_SD_CD_PORT_ID             2
+#if      (RTE_SD_CD_PORT_ID == 0)
+  #define RTE_SD_CD_PIN_EN              0
+#elif    (RTE_SD_CD_PORT_ID == 1)
+  #define RTE_SD_CD_PORT                1
+  #define RTE_SD_CD_PIN                 13
+  #define RTE_SD_CD_FUNC                7
+#elif    (RTE_SD_CD_PORT_ID == 2)
+  #define RTE_SD_CD_PORT                0xC
+  #define RTE_SD_CD_PIN                 8
+  #define RTE_SD_CD_FUNC                7
+#else
+  #error "Invalid SD_CD Pin Configuration!"
+#endif
+#ifndef   RTE_SD_CD_PIN_EN
+  #define RTE_SD_CD_PIN_EN              1
+#endif
+//   <o> SD_WP (Write Protect) Pin <0=>Not used <1=>PD_15 <2=>PF_10
+//   <i> Configure Pin if exists
+#define   RTE_SD_WP_PORT_ID             0
+#if      (RTE_SD_WP_PORT_ID == 0)
+  #define RTE_SD_WP_PIN_EN              0
+#elif    (RTE_SD_WP_PORT_ID == 1)
+  #define RTE_SD_WP_PORT                0xD
+  #define RTE_SD_WP_PIN                 15
+  #define RTE_SD_WP_FUNC                5
+#elif    (RTE_SD_WP_PORT_ID == 2)
+  #define RTE_SD_WP_PORT                0xF
+  #define RTE_SD_WP_PIN                 10
+  #define RTE_SD_WP_FUNC                6
+#else
+  #error "Invalid SD_WP Pin Configuration!"
+#endif
+#ifndef   RTE_SD_WP_PIN_EN
+  #define RTE_SD_WP_PIN_EN              1
+#endif
+//   <o> SD_POW (Power) Pin <0=>Not used <1=>P1_5 <2=>PC_9 <3=>PD_1
+//   <i> Configure Pin if exists
+#define   RTE_SD_POW_PORT_ID            0
+#if      (RTE_SD_POW_PORT_ID == 0)
+  #define RTE_SD_POW_PIN_EN             0
+#elif    (RTE_SD_POW_PORT_ID == 1)
+  #define RTE_SD_POW_PORT               1
+  #define RTE_SD_POW_PIN                5
+  #define RTE_SD_POW_FUNC               7
+#elif    (RTE_SD_POW_PORT_ID == 2)
+  #define RTE_SD_POW_PORT               0xC
+  #define RTE_SD_POW_PIN                9
+  #define RTE_SD_POW_FUNC               7
+#elif    (RTE_SD_POW_PORT_ID == 3)
+  #define RTE_SD_POW_PORT               0xD
+  #define RTE_SD_POW_PIN                1
+  #define RTE_SD_POW_FUNC               5
+#else
+  #error "Invalid SD_POW Pin Configuration!"
+#endif
+#ifndef   RTE_SD_POW_PIN_EN
+  #define RTE_SD_POW_PIN_EN             1
+#endif
+//   <o> SD_RST (Card Reset for MMC4.4) Pin <0=>Not used <1=>P1_3 <2=>PC_2
+//   <i> Configure Pin if exists
+#define   RTE_SD_RST_PORT_ID            0
+#if      (RTE_SD_RST_PORT_ID == 0)
+  #define RTE_SD_RST_PIN_EN             0
+#elif    (RTE_SD_RST_PORT_ID == 1)
+  #define RTE_SD_RST_PORT               1
+  #define RTE_SD_RST_PIN                3
+  #define RTE_SD_RST_FUNC               7
+#elif    (RTE_SD_RST_PORT_ID == 2)
+  #define RTE_SD_RST_PORT               0xC
+  #define RTE_SD_RST_PIN                2
+  #define RTE_SD_RST_FUNC               7
+#else
+  #error "Invalid SD_RST Pin Configuration!"
+#endif
+#ifndef   RTE_SD_RST_PIN_EN
+  #define RTE_SD_RST_PIN_EN             1
+#endif
+// </e> SD/MMC Interface [Driver_MCI0]
+
+// <e> I2C0 (Inter-integrated Circuit Interface 0) [Driver_I2C0]
+// <i> Configuration settings for Driver_I2C0 in component ::Drivers:I2C
+// </e> I2C0 (Inter-integrated Circuit Interface 0) [Driver_I2C0]
+#define   RTE_I2C0                      0
+
+// <e> I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1]
+// <i> Configuration settings for Driver_I2C1 in component ::Drivers:I2C
+#define   RTE_I2C1                      0
+
+//   <o> I2C1_SCL Pin <0=>P2_4 <1=>PE_15
+#define   RTE_I2C1_SCL_PORT_ID          0
+#if      (RTE_I2C1_SCL_PORT_ID == 0)
+  #define RTE_I2C1_SCL_PORT             2
+  #define RTE_I2C1_SCL_PIN              4
+  #define RTE_I2C1_SCL_FUNC             1
+#elif    (RTE_I2C1_SCL_PORT_ID == 1)
+  #define RTE_I2C1_SCL_PORT             0xE
+  #define RTE_I2C1_SCL_PIN              15
+  #define RTE_I2C1_SCL_FUNC             2
+#else
+  #error "Invalid I2C1_SCL Pin Configuration!"
+#endif
+//   <o> I2C1_SDA Pin <0=>P2_3 <1=>PE_13
+#define   RTE_I2C1_SDA_PORT_ID          0
+#if      (RTE_I2C1_SDA_PORT_ID == 0)
+  #define RTE_I2C1_SDA_PORT             2
+  #define RTE_I2C1_SDA_PIN              3
+  #define RTE_I2C1_SDA_FUNC             1
+#elif    (RTE_I2C1_SDA_PORT_ID == 1)
+  #define RTE_I2C1_SDA_PORT             0xE
+  #define RTE_I2C1_SDA_PIN              13
+  #define RTE_I2C1_SDA_FUNC             2
+#else
+  #error "Invalid I2C1_SDA Pin Configuration!"
+#endif
+// </e> I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1]
+
+// <e> USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0]
+#define   RTE_USART0                    0
+
+//   <h> Pin Configuration
+//     <o> TX <0=>P2_0 <1=>P6_4 <2=>P9_5 <3=>PF_10
+//     <i> USART0 Serial Output pin
+#define   RTE_USART0_TX_ID              0
+#if      (RTE_USART0_TX_ID == 0)
+  #define RTE_USART0_TX_PORT            2
+  #define RTE_USART0_TX_BIT             0
+  #define RTE_USART0_TX_FUNC            1
+#elif    (RTE_USART0_TX_ID == 1)
+  #define RTE_USART0_TX_PORT            6
+  #define RTE_USART0_TX_BIT             4
+  #define RTE_USART0_TX_FUNC            2
+#elif    (RTE_USART0_TX_ID == 2)
+  #define RTE_USART0_TX_PORT            9
+  #define RTE_USART0_TX_BIT             5
+  #define RTE_USART0_TX_FUNC            7
+#elif    (RTE_USART0_TX_ID == 3)
+  #define RTE_USART0_TX_PORT            0xF
+  #define RTE_USART0_TX_BIT             10
+  #define RTE_USART0_TX_FUNC            1
+#else
+  #error "Invalid USART0_TX Pin Configuration!"
+#endif
+//     <o> RX <0=>P2_1 <1=>P6_5 <2=>P9_6 <3=>PF_11
+//     <i> USART0 Serial Input pin
+#define   RTE_USART0_RX_ID              0
+#if      (RTE_USART0_RX_ID == 0)
+  #define RTE_USART0_RX_PORT            2
+  #define RTE_USART0_RX_BIT             1
+  #define RTE_USART0_RX_FUNC            1
+#elif    (RTE_USART0_RX_ID == 1)
+  #define RTE_USART0_RX_PORT            6
+  #define RTE_USART0_RX_BIT             5
+  #define RTE_USART0_RX_FUNC            2
+#elif    (RTE_USART0_RX_ID == 2)
+  #define RTE_USART0_RX_PORT            9
+  #define RTE_USART0_RX_BIT             6
+  #define RTE_USART0_RX_FUNC            7
+#elif    (RTE_USART0_RX_ID == 3)
+  #define RTE_USART0_RX_PORT            0xF
+  #define RTE_USART0_RX_BIT             11
+  #define RTE_USART0_RX_FUNC            1
+#else
+  #error "Invalid USART0_RX Pin Configuration!"
+#endif
+//     <o> UCLK (Synchronous and SmartCard mode) <0=>Not used <1=>P2_2 <2=>P6_1 <3=>PF_8
+//     <i> USART0 Serial Clock input/output synchronous mode
+#define   RTE_USART0_UCLK_ID            0
+#if      (RTE_USART0_UCLK_ID == 0)
+  #define RTE_USART0_UCLK_PIN_EN        0
+#elif    (RTE_USART0_UCLK_ID == 1)
+  #define RTE_USART0_UCLK_PORT          2
+  #define RTE_USART0_UCLK_BIT           2
+  #define RTE_USART0_UCLK_FUNC          1
+#elif    (RTE_USART0_UCLK_ID == 2)
+  #define RTE_USART0_UCLK_PORT          6
+  #define RTE_USART0_UCLK_BIT           1
+  #define RTE_USART0_UCLK_FUNC          2
+#elif    (RTE_USART0_UCLK_ID == 3)
+  #define RTE_USART0_UCLK_PORT          0xF
+  #define RTE_USART0_UCLK_BIT           8
+  #define RTE_USART0_UCLK_FUNC          1
+#else
+  #error "Invalid USART0_UCLK Pin Configuration!"
+#endif
+#ifndef   RTE_USART0_UCLK_PIN_EN
+  #define RTE_USART0_UCLK_PIN_EN        1
+#endif
+//   </h> Pin Configuration
+
+//   <h> DMA
+//     <e> Tx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>1 (DMAMUXPER1)  <1=>11 (DMAMUXPER11)
+//     </e>
+#define   RTE_USART0_DMA_TX_EN          0
+#define   RTE_USART0_DMA_TX_CH          0
+#define   RTE_USART0_DMA_TX_PERI_ID     0
+#if      (RTE_USART0_DMA_TX_PERI_ID == 0)
+  #define RTE_USART0_DMA_TX_PERI        1
+  #define RTE_USART0_DMA_TX_PERI_SEL    1
+#elif    (RTE_USART0_DMA_TX_PERI_ID == 1)
+  #define RTE_USART0_DMA_TX_PERI        11
+  #define RTE_USART0_DMA_TX_PERI_SEL    2
+#endif
+//     <e> Rx
+//       <o1> Channel    <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral <0=>2 (DMAMUXPER2)  <1=>12 (DMAMUXPER12)
+//     </e>
+#define   RTE_USART0_DMA_RX_EN          0
+#define   RTE_USART0_DMA_RX_CH          1
+#define   RTE_USART0_DMA_RX_PERI_ID     0
+#if      (RTE_USART0_DMA_RX_PERI_ID == 0)
+  #define RTE_USART0_DMA_RX_PERI        2
+  #define RTE_USART0_DMA_RX_PERI_SEL    1
+#elif    (RTE_USART0_DMA_RX_PERI_ID == 1)
+  #define RTE_USART0_DMA_RX_PERI        12
+  #define RTE_USART0_DMA_RX_PERI_SEL    2
+#endif
+//   </h> DMA
+// </e> USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0]
+
+// <e> UART1 (Universal asynchronous receiver transmitter) [Driver_USART1]
+#define   RTE_UART1                     0
+
+//   <h> Pin Configuration
+//     <o> TX <0=>P1_13 <1=>P3_4 <2=>P5_6 <3=>PC_13 <4=>PE_11
+//     <i> UART0 Serial Output pin
+#define   RTE_UART1_TX_ID               2
+#if      (RTE_UART1_TX_ID == 0)
+  #define RTE_UART1_TX_PORT             1
+  #define RTE_UART1_TX_BIT              13
+  #define RTE_UART1_TX_FUNC             1
+#elif    (RTE_UART1_TX_ID == 1)
+  #define RTE_UART1_TX_PORT             3
+  #define RTE_UART1_TX_BIT              4
+  #define RTE_UART1_TX_FUNC             4
+#elif    (RTE_UART1_TX_ID == 2)
+  #define RTE_UART1_TX_PORT             5
+  #define RTE_UART1_TX_BIT              6
+  #define RTE_UART1_TX_FUNC             4
+#elif    (RTE_UART1_TX_ID == 3)
+  #define RTE_UART1_TX_PORT             0xC
+  #define RTE_UART1_TX_BIT              13
+  #define RTE_UART1_TX_FUNC             2
+#elif    (RTE_UART1_TX_ID == 4)
+  #define RTE_UART1_TX_PORT             0xE
+  #define RTE_UART1_TX_BIT              11
+  #define RTE_UART1_TX_FUNC             2
+#else
+  #error "Invalid UART1_TX Pin Configuration!"
+#endif
+//   <o> RX <0=>P1_14 <1=>P3_5 <2=>P5_7 <3=>PC_14 <4=>PE_12
+//   <i> UART1 Serial Input pin
+#define   RTE_UART1_RX_ID               0
+#if      (RTE_UART1_RX_ID == 0)
+  #define RTE_UART1_RX_PORT             1
+  #define RTE_UART1_RX_BIT              14
+  #define RTE_UART1_RX_FUNC             1
+#elif    (RTE_UART1_RX_ID == 1)
+  #define RTE_UART1_RX_PORT             3
+  #define RTE_UART1_RX_BIT              5
+  #define RTE_UART1_RX_FUNC             4
+#elif    (RTE_UART1_RX_ID == 2)
+  #define RTE_UART1_RX_PORT             5
+  #define RTE_UART1_RX_BIT              7
+  #define RTE_UART1_RX_FUNC             4
+#elif    (RTE_UART1_RX_ID == 3)
+  #define RTE_UART1_RX_PORT             0xC
+  #define RTE_UART1_RX_BIT              14
+  #define RTE_UART1_RX_FUNC             2
+#elif    (RTE_UART1_RX_ID == 4)
+  #define RTE_UART1_RX_PORT             0xE
+  #define RTE_UART1_RX_BIT              12
+  #define RTE_UART1_RX_FUNC             2
+#else
+  #error "Invalid UART1_RX Pin Configuration!"
+#endif
+
+//     <h> Modem Lines
+//       <o> CTS <0=>Not used <1=>P1_11 <2=>P5_4 <3=>PC_2 <4=>PE_7
+#define   RTE_UART1_CTS_ID              1
+#if      (RTE_UART1_CTS_ID == 0)
+  #define RTE_UART1_CTS_PIN_EN          0
+#elif    (RTE_UART1_CTS_ID == 1)
+  #define RTE_UART1_CTS_PORT            1
+  #define RTE_UART1_CTS_BIT             11
+  #define RTE_UART1_CTS_FUNC            1
+#elif    (RTE_UART1_CTS_ID == 2)
+  #define RTE_UART1_CTS_PORT            5
+  #define RTE_UART1_CTS_BIT             4
+  #define RTE_UART1_CTS_FUNC            4
+#elif    (RTE_UART1_CTS_ID == 3)
+  #define RTE_UART1_CTS_PORT            0xC
+  #define RTE_UART1_CTS_BIT             2
+  #define RTE_UART1_CTS_FUNC            2
+#elif    (RTE_UART1_CTS_ID == 4)
+  #define RTE_UART1_CTS_PORT            0xE
+  #define RTE_UART1_CTS_BIT             7
+  #define RTE_UART1_CTS_FUNC            2
+#else
+  #error "Invalid UART1_CTS Pin Configuration!"
+#endif
+#ifndef   RTE_UART1_CTS_PIN_EN
+  #define RTE_UART1_CTS_PIN_EN          1
+#endif
+//       <o> RTS <0=>Not used <1=>P1_9  <2=>P5_2 <3=>PC_3 <4=>PE_5
+#define   RTE_UART1_RTS_ID              1
+#if      (RTE_UART1_RTS_ID == 0)
+  #define RTE_UART1_RTS_PIN_EN          0
+#elif    (RTE_UART1_RTS_ID == 1)
+  #define RTE_UART1_RTS_PORT            1
+  #define RTE_UART1_RTS_BIT             9
+  #define RTE_UART1_RTS_FUNC            1
+#elif    (RTE_UART1_RTS_ID == 2)
+  #define RTE_UART1_RTS_PORT            5
+  #define RTE_UART1_RTS_BIT             2
+  #define RTE_UART1_RTS_FUNC            4
+#elif    (RTE_UART1_RTS_ID == 3)
+  #define RTE_UART1_RTS_PORT            0xC
+  #define RTE_UART1_RTS_BIT             3
+  #define RTE_UART1_RTS_FUNC            2
+#elif    (RTE_UART1_RTS_ID == 4)
+  #define RTE_UART1_RTS_PORT            0xE
+  #define RTE_UART1_RTS_BIT             5
+  #define RTE_UART1_RTS_FUNC            2
+#else
+  #error "Invalid UART1_RTS Pin Configuration!"
+#endif
+#ifndef   RTE_UART1_RTS_PIN_EN
+  #define RTE_UART1_RTS_PIN_EN          1
+#endif
+//       <o> DCD <0=>Not used <1=>P1_12 <2=>P5_5 <3=>PC_11 <4=>PE_9
+#define   RTE_UART1_DCD_ID              1
+#if      (RTE_UART1_DCD_ID == 0)
+  #define RTE_UART1_DCD_PIN_EN          0
+#elif    (RTE_UART1_DCD_ID == 1)
+  #define RTE_UART1_DCD_PORT            1
+  #define RTE_UART1_DCD_BIT             12
+  #define RTE_UART1_DCD_FUNC            1
+#elif    (RTE_UART1_DCD_ID == 2)
+  #define RTE_UART1_DCD_PORT            5
+  #define RTE_UART1_DCD_BIT             5
+  #define RTE_UART1_DCD_FUNC            4
+#elif    (RTE_UART1_DCD_ID == 3)
+  #define RTE_UART1_DCD_PORT            0xC
+  #define RTE_UART1_DCD_BIT             11
+  #define RTE_UART1_DCD_FUNC            2
+#elif    (RTE_UART1_DCD_ID == 4)
+  #define RTE_UART1_DCD_PORT            0xE
+  #define RTE_UART1_DCD_BIT             9
+  #define RTE_UART1_DCD_FUNC            2
+#else
+  #error "Invalid UART1_DCD Pin Configuration!"
+#endif
+#ifndef   RTE_UART1_DCD_PIN_EN
+  #define RTE_UART1_DCD_PIN_EN          1
+#endif
+//       <o> DSR <0=>Not used <1=>P1_7 <2=>P5_0 <3=>PC_10 <4=>PE_8
+#define   RTE_UART1_DSR_ID              1
+#if      (RTE_UART1_DSR_ID == 0)
+  #define RTE_UART1_DSR_PIN_EN          0
+#elif    (RTE_UART1_DSR_ID == 1)
+  #define RTE_UART1_DSR_PORT            1
+  #define RTE_UART1_DSR_BIT             7
+  #define RTE_UART1_DSR_FUNC            1
+#elif    (RTE_UART1_DSR_ID == 2)
+  #define RTE_UART1_DSR_PORT            5
+  #define RTE_UART1_DSR_BIT             0
+  #define RTE_UART1_DSR_FUNC            4
+#elif    (RTE_UART1_DSR_ID == 3)
+  #define RTE_UART1_DSR_PORT            0xC
+  #define RTE_UART1_DSR_BIT             10
+  #define RTE_UART1_DSR_FUNC            2
+#elif    (RTE_UART1_DSR_ID == 4)
+  #define RTE_UART1_DSR_PORT            0xE
+  #define RTE_UART1_DSR_BIT             8
+  #define RTE_UART1_DSR_FUNC            2
+#else
+  #error "Invalid UART1_DSR Pin Configuration!"
+#endif
+#ifndef   RTE_UART1_DSR_PIN_EN
+  #define RTE_UART1_DSR_PIN_EN          1
+#endif
+//       <o> DTR <0=>Not used <1=>P1_8  <2=>P5_1 <3=>PC_12 <4=>PE_10
+#define   RTE_UART1_DTR_ID              1
+#if      (RTE_UART1_DTR_ID == 0)
+  #define RTE_UART1_DTR_PIN_EN          0
+#elif    (RTE_UART1_DTR_ID == 1)
+  #define RTE_UART1_DTR_PORT            1
+  #define RTE_UART1_DTR_BIT             8
+  #define RTE_UART1_DTR_FUNC            1
+#elif    (RTE_UART1_DTR_ID == 2)
+  #define RTE_UART1_DTR_PORT            5
+  #define RTE_UART1_DTR_BIT             1
+  #define RTE_UART1_DTR_FUNC            4
+#elif    (RTE_UART1_DTR_ID == 3)
+  #define RTE_UART1_DTR_PORT            0xC
+  #define RTE_UART1_DTR_BIT             12
+  #define RTE_UART1_DTR_FUNC            2
+#elif    (RTE_UART1_DTR_ID == 4)
+  #define RTE_UART1_DTR_PORT            0xE
+  #define RTE_UART1_DTR_BIT             10
+  #define RTE_UART1_DTR_FUNC            2
+#else
+  #error "Invalid UART1_DTR Pin Configuration!"
+#endif
+#ifndef   RTE_UART1_DTR_PIN_EN
+  #define RTE_UART1_DTR_PIN_EN          1
+#endif
+//       <o> RI <0=>Not used <1=>P1_10 <2=>P5_3 <3=>PC_1 <4=>PE_6
+#define   RTE_UART1_RI_ID               1
+#if      (RTE_UART1_RI_ID == 0)
+  #define RTE_UART1_RI_PIN_EN           0
+#elif    (RTE_UART1_RI_ID == 1)
+  #define RTE_UART1_RI_PORT             1
+  #define RTE_UART1_RI_BIT              10
+  #define RTE_UART1_RI_FUNC             1
+#elif    (RTE_UART1_RI_ID == 2)
+  #define RTE_UART1_RI_PORT             5
+  #define RTE_UART1_RI_BIT              3
+  #define RTE_UART1_RI_FUNC             4
+#elif    (RTE_UART1_RI_ID == 3)
+  #define RTE_UART1_RI_PORT             0xC
+  #define RTE_UART1_RI_BIT              1
+  #define RTE_UART1_RI_FUNC             2
+#elif    (RTE_UART1_RI_ID == 4)
+  #define RTE_UART1_RI_PORT             0xE
+  #define RTE_UART1_RI_BIT              6
+  #define RTE_UART1_RI_FUNC             2
+#else
+  #error "Invalid UART1_RI Pin Configuration!"
+#endif
+#ifndef   RTE_UART1_RI_PIN_EN
+  #define RTE_UART1_RI_PIN_EN           1
+#endif
+//     </h> Modem Lines
+//   </h> Pin Configuration
+
+//   <h> DMA
+//     <e> Tx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>3 (DMAMUXPER3)
+//     </e>
+#define   RTE_UART1_DMA_TX_EN           0
+#define   RTE_UART1_DMA_TX_CH           0
+#define   RTE_UART1_DMA_TX_PERI_ID      0
+#if      (RTE_UART1_DMA_TX_PERI_ID == 0)
+  #define RTE_UART1_DMA_TX_PERI         3
+  #define RTE_UART1_DMA_TX_PERI_SEL     1
+#endif
+//     <e> Rx
+//       <o1> Channel    <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral <0=>4 (DMAMUXPER4)
+//     </e>
+#define   RTE_UART1_DMA_RX_EN           0
+#define   RTE_UART1_DMA_RX_CH           1
+#define   RTE_UART1_DMA_RX_PERI_ID      0
+#if      (RTE_UART1_DMA_RX_PERI_ID == 0)
+  #define RTE_UART1_DMA_RX_PERI         4
+  #define RTE_UART1_DMA_RX_PERI_SEL     1
+#endif
+//   </h> DMA
+// </e> UART1 (Universal asynchronous receiver transmitter) [Driver_USART1]
+
+// <e> USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2]
+#define   RTE_USART2                    0
+
+//   <h> Pin Configuration
+//     <o> TX <0=>P1_15 <1=>P2_10 <2=>P7_1 <3=>PA_1
+//     <i> USART2 Serial Output pin
+#define   RTE_USART2_TX_ID              0
+#if      (RTE_USART2_TX_ID == 0)
+  #define RTE_USART2_TX_PORT            1
+  #define RTE_USART2_TX_BIT             15
+  #define RTE_USART2_TX_FUNC            1
+#elif    (RTE_USART2_TX_ID == 1)
+  #define RTE_USART2_TX_PORT            2
+  #define RTE_USART2_TX_BIT             10
+  #define RTE_USART2_TX_FUNC            2
+#elif    (RTE_USART2_TX_ID == 2)
+  #define RTE_USART2_TX_PORT            7
+  #define RTE_USART2_TX_BIT             1
+  #define RTE_USART2_TX_FUNC            6
+#elif    (RTE_USART2_TX_ID == 3)
+  #define RTE_USART2_TX_PORT            0xA
+  #define RTE_USART2_TX_BIT             1
+  #define RTE_USART2_TX_FUNC            3
+#else
+  #error "Invalid USART2_TX Pin Configuration!"
+#endif
+//     <o> RX <0=>P1_16 <1=>P2_11 <2=>P7_2 <3=>PA_2
+//     <i> USART2 Serial Input pin
+#define   RTE_USART2_RX_ID              0
+#if      (RTE_USART2_RX_ID == 0)
+  #define RTE_USART2_RX_PORT            1
+  #define RTE_USART2_RX_BIT             16
+  #define RTE_USART2_RX_FUNC            1
+#elif    (RTE_USART2_RX_ID == 1)
+  #define RTE_USART2_RX_PORT            2
+  #define RTE_USART2_RX_BIT             11
+  #define RTE_USART2_RX_FUNC            2
+#elif    (RTE_USART2_RX_ID == 2)
+  #define RTE_USART2_RX_PORT            7
+  #define RTE_USART2_RX_BIT             2
+  #define RTE_USART2_RX_FUNC            6
+#elif    (RTE_USART2_RX_ID == 3)
+  #define RTE_USART2_RX_PORT            0xA
+  #define RTE_USART2_RX_BIT             2
+  #define RTE_USART2_RX_FUNC            3
+#else
+  #error "Invalid USART2_RX Pin Configuration!"
+#endif
+//       <o> UCLK (Synchronous and SmartCard mode) <0=>Not used <1=>P1_17 <2=>P2_12
+//       <i> USART2 Serial Clock input/output synchronous mode
+#define   RTE_USART2_UCLK_ID            0
+#if      (RTE_USART2_UCLK_ID == 0)
+  #define RTE_USART2_UCLK_PIN_EN        0
+#elif    (RTE_USART2_UCLK_ID == 1)
+  #define RTE_USART2_UCLK_PORT          1
+  #define RTE_USART2_UCLK_BIT           17
+  #define RTE_USART2_UCLK_FUNC          1
+#elif    (RTE_USART2_UCLK_ID == 1)
+  #define RTE_USART2_UCLK_PORT          2
+  #define RTE_USART2_UCLK_BIT           12
+  #define RTE_USART2_UCLK_FUNC          7
+#else
+  #error "Invalid USART2_UCLK Pin Configuration!"
+#endif
+#ifndef   RTE_USART2_UCLK_PIN_EN
+  #define RTE_USART2_UCLK_PIN_EN        1
+#endif
+//   </h> Pin Configuration
+
+//   <h> DMA
+//     <e> Tx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>5 (DMAMUXPER5)
+//     </e>
+#define   RTE_USART2_DMA_TX_EN          0
+#define   RTE_USART2_DMA_TX_CH          0
+#define   RTE_USART2_DMA_TX_PERI_ID     0
+#if      (RTE_USART2_DMA_TX_PERI_ID == 0)
+  #define RTE_USART2_DMA_TX_PERI        5
+  #define RTE_USART2_DMA_TX_PERI_SEL    1
+#endif
+//     <e> Rx
+//       <o1> Channel    <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral <0=>6 (DMAMUXPER6)
+//     </e>
+#define   RTE_USART2_DMA_RX_EN          0
+#define   RTE_USART2_DMA_RX_CH          1
+#define   RTE_USART2_DMA_RX_PERI_ID     0
+#if      (RTE_USART2_DMA_RX_PERI_ID == 0)
+  #define RTE_USART2_DMA_RX_PERI        6
+  #define RTE_USART2_DMA_RX_PERI_SEL    1
+#endif
+//   </h> DMA
+// </e> USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2]
+
+// <e> USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3]
+#define   RTE_USART3                    0
+
+//   <h> Pin Configuration
+//     <o> TX <0=>P2_3 <1=>P4_1 <2=>P9_3 <3=>PF_2
+//     <i> USART3 Serial Output pin
+#define   RTE_USART3_TX_ID              0
+#if      (RTE_USART3_TX_ID == 0)
+  #define RTE_USART3_TX_PORT            2
+  #define RTE_USART3_TX_BIT             3
+  #define RTE_USART3_TX_FUNC            2
+#elif    (RTE_USART3_TX_ID == 1)
+  #define RTE_USART3_TX_PORT            4
+  #define RTE_USART3_TX_BIT             1
+  #define RTE_USART3_TX_FUNC            6
+#elif    (RTE_USART3_TX_ID == 2)
+  #define RTE_USART3_TX_PORT            9
+  #define RTE_USART3_TX_BIT             3
+  #define RTE_USART3_TX_FUNC            7
+#elif    (RTE_USART3_TX_ID == 3)
+  #define RTE_USART3_TX_PORT            0xF
+  #define RTE_USART3_TX_BIT             2
+  #define RTE_USART3_TX_FUNC            1
+#else
+  #error "Invalid USART3_TX Pin Configuration!"
+#endif
+//     <o> RX <0=>P2_4 <1=>P4_2 <2=>P9_4 <3=>PF_3
+//     <i> USART3 Serial Input pin
+#define   RTE_USART3_RX_ID              0
+#if      (RTE_USART3_RX_ID == 0)
+  #define RTE_USART3_RX_PORT            2
+  #define RTE_USART3_RX_BIT             4
+  #define RTE_USART3_RX_FUNC            2
+#elif    (RTE_USART3_RX_ID == 1)
+  #define RTE_USART3_RX_PORT            4
+  #define RTE_USART3_RX_BIT             2
+  #define RTE_USART3_RX_FUNC            6
+#elif    (RTE_USART3_RX_ID == 2)
+  #define RTE_USART3_RX_PORT            9
+  #define RTE_USART3_RX_BIT             4
+  #define RTE_USART3_RX_FUNC            7
+#elif    (RTE_USART3_RX_ID == 3)
+  #define RTE_USART3_RX_PORT            0xF
+  #define RTE_USART3_RX_BIT             3
+  #define RTE_USART3_RX_FUNC            1
+#else
+  #error "Invalid USART3_RX Pin Configuration!"
+#endif
+//     <o> UCLK (Synchronous and SmartCard mode) <0=>Not used <1=>P2_7 <2=>P4_0 <3=>PF_5
+//     <i> USART3 Serial Clock input/output synchronous mode
+#define   RTE_USART3_UCLK_ID            0
+#if      (RTE_USART3_UCLK_ID == 0)
+  #define RTE_USART3_UCLK_PIN_EN        0
+#elif    (RTE_USART3_UCLK_ID == 1)
+  #define RTE_USART3_UCLK_PORT          2
+  #define RTE_USART3_UCLK_BIT           7
+  #define RTE_USART3_UCLK_FUNC          2
+#elif    (RTE_USART3_UCLK_ID == 2)
+  #define RTE_USART3_UCLK_PORT          4
+  #define RTE_USART3_UCLK_BIT           0
+  #define RTE_USART3_UCLK_FUNC          6
+#elif    (RTE_USART3_UCLK_ID == 3)
+  #define RTE_USART3_UCLK_PORT          0xF
+  #define RTE_USART3_UCLK_BIT           5
+  #define RTE_USART3_UCLK_FUNC          1
+#else
+  #error "Invalid USART3_UCLK Pin Configuration!"
+#endif
+#ifndef   RTE_USART3_UCLK_PIN_EN
+  #define RTE_USART3_UCLK_PIN_EN        1
+#endif
+//   </h> Pin Configuration
+
+//   <h> DMA
+//     <e> Tx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>7 (DMAMUXPER7)  <1=>14 (DMAMUXPER14)
+//     </e>
+#define   RTE_USART3_DMA_TX_EN          0
+#define   RTE_USART3_DMA_TX_CH          0
+#define   RTE_USART3_DMA_TX_PERI_ID     0
+#if      (RTE_USART3_DMA_TX_PERI_ID == 0)
+  #define RTE_USART3_DMA_TX_PERI        7
+  #define RTE_USART3_DMA_TX_PERI_SEL    1
+#elif    (RTE_USART3_DMA_TX_PERI_ID == 1)
+  #define RTE_USART3_DMA_TX_PERI        14
+  #define RTE_USART3_DMA_TX_PERI_SEL    3
+#endif
+//     <e> Rx
+//       <o1> Channel    <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral <0=>8 (DMAMUXPER8)  <1=>13 (DMAMUXPER13)
+//     </e>
+#define   RTE_USART3_DMA_RX_EN          0
+#define   RTE_USART3_DMA_RX_CH          1
+#define   RTE_USART3_DMA_RX_PERI_ID     0
+#if      (RTE_USART3_DMA_RX_PERI_ID == 0)
+  #define RTE_USART3_DMA_RX_PERI        8
+  #define RTE_USART3_DMA_RX_PERI_SEL    1
+#elif    (RTE_USART3_DMA_RX_PERI_ID == 1)
+  #define RTE_USART3_DMA_RX_PERI        13
+  #define RTE_USART3_DMA_RX_PERI_SEL    3
+#endif
+//   </h> DMA
+// </e> USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3]
+
+// <e> SSP0 (Synchronous Serial Port 0) [Driver_SPI0]
+// <i> Configuration settings for Driver_SPI0 in component ::Drivers:SPI
+#define   RTE_SSP0                      0
+
+//   <h> Pin Configuration
+//     <o> SSP0_SSEL <0=>Not used <1=>P1_0 <2=>P3_6 <3=>P3_8 <4=>P9_0 <5=>PF_1
+//     <i> Slave Select for SSP0
+#define   RTE_SSP0_SSEL_PIN_SEL         5
+#if      (RTE_SSP0_SSEL_PIN_SEL == 0)
+#define   RTE_SSP0_SSEL_PIN_EN          0
+#elif    (RTE_SSP0_SSEL_PIN_SEL == 1)
+  #define RTE_SSP0_SSEL_PORT            1
+  #define RTE_SSP0_SSEL_BIT             0
+  #define RTE_SSP0_SSEL_FUNC            5
+  #define RTE_SSP0_SSEL_GPIO_FUNC       0
+  #define RTE_SSP0_SSEL_GPIO_PORT       0
+  #define RTE_SSP0_SSEL_GPIO_BIT        4
+#elif    (RTE_SSP0_SSEL_PIN_SEL == 2)
+  #define RTE_SSP0_SSEL_PORT            3
+  #define RTE_SSP0_SSEL_BIT             6
+  #define RTE_SSP0_SSEL_FUNC            2
+  #define RTE_SSP0_SSEL_GPIO_FUNC       0
+  #define RTE_SSP0_SSEL_GPIO_PORT       0
+  #define RTE_SSP0_SSEL_GPIO_BIT        6
+#elif    (RTE_SSP0_SSEL_PIN_SEL == 3)
+  #define RTE_SSP0_SSEL_PORT            3
+  #define RTE_SSP0_SSEL_BIT             8
+  #define RTE_SSP0_SSEL_FUNC            5
+  #define RTE_SSP0_SSEL_GPIO_FUNC       4
+  #define RTE_SSP0_SSEL_GPIO_PORT       5
+  #define RTE_SSP0_SSEL_GPIO_BIT        11
+#elif    (RTE_SSP0_SSEL_PIN_SEL == 4)
+  #define RTE_SSP0_SSEL_PORT            9
+  #define RTE_SSP0_SSEL_BIT             0
+  #define RTE_SSP0_SSEL_FUNC            7
+  #define RTE_SSP0_SSEL_GPIO_FUNC       0
+  #define RTE_SSP0_SSEL_GPIO_PORT       4
+  #define RTE_SSP0_SSEL_GPIO_BIT        12
+#elif    (RTE_SSP0_SSEL_PIN_SEL == 5)
+  #define RTE_SSP0_SSEL_PORT            0xF
+  #define RTE_SSP0_SSEL_BIT             1
+  #define RTE_SSP0_SSEL_FUNC            2
+  #define RTE_SSP0_SSEL_GPIO_FUNC       4
+  #define RTE_SSP0_SSEL_GPIO_PORT       7
+  #define RTE_SSP0_SSEL_GPIO_BIT        16
+#else
+  #error "Invalid SSP0 SSP0_SSEL Pin Configuration!"
+#endif
+#ifndef   RTE_SSP0_SSEL_PIN_EN
+#define   RTE_SSP0_SSEL_PIN_EN          1
+#endif
+//     <o> SSP0_SCK <0=>P3_0 <1=>P3_3 <2=>PF_0
+//     <i> Serial clock for SSP0
+#define   RTE_SSP0_SCK_PIN_SEL          2
+#if      (RTE_SSP0_SCK_PIN_SEL == 0)
+  #define RTE_SSP0_SCK_PORT             3
+  #define RTE_SSP0_SCK_BIT              0
+  #define RTE_SSP0_SCK_FUNC             4
+#elif    (RTE_SSP0_SCK_PIN_SEL == 1)
+  #define RTE_SSP0_SCK_PORT             3
+  #define RTE_SSP0_SCK_BIT              3
+  #define RTE_SSP0_SCK_FUNC             2
+#elif    (RTE_SSP0_SCK_PIN_SEL == 2)
+  #define RTE_SSP0_SCK_PORT             0xF
+  #define RTE_SSP0_SCK_BIT              0
+  #define RTE_SSP0_SCK_FUNC             0
+#else
+  #error "Invalid SSP0 SSP0_SCK Pin Configuration!"
+#endif
+//     <o> SSP0_MISO <0=>P1_1 <1=>P3_6 <2=>P3_7 <3=>P9_1 <4=>PF_2
+//     <i> Master In Slave Out for SSP0
+#define   RTE_SSP0_MISO_PIN_SEL         4
+#if      (RTE_SSP0_MISO_PIN_SEL == 0)
+  #define RTE_SSP0_MISO_PORT            1
+  #define RTE_SSP0_MISO_BIT             1
+  #define RTE_SSP0_MISO_FUNC            5
+#elif    (RTE_SSP0_MISO_PIN_SEL == 1)
+  #define RTE_SSP0_MISO_PORT            3
+  #define RTE_SSP0_MISO_BIT             6
+  #define RTE_SSP0_MISO_FUNC            5
+#elif    (RTE_SSP0_MISO_PIN_SEL == 2)
+  #define RTE_SSP0_MISO_PORT            3
+  #define RTE_SSP0_MISO_BIT             7
+  #define RTE_SSP0_MISO_FUNC            2
+#elif    (RTE_SSP0_MISO_PIN_SEL == 3)
+  #define RTE_SSP0_MISO_PORT            9
+  #define RTE_SSP0_MISO_BIT             1
+  #define RTE_SSP0_MISO_FUNC            7
+#elif    (RTE_SSP0_MISO_PIN_SEL == 4)
+  #define RTE_SSP0_MISO_PORT            0xF
+  #define RTE_SSP0_MISO_BIT             2
+  #define RTE_SSP0_MISO_FUNC            2
+#else
+  #error "Invalid SSP0 SSP0_MISO Pin Configuration!"
+#endif
+//     <o> SSP0_MOSI <0=>P1_2 <1=>P3_7 <2=>P3_8 <3=>P9_2 <4=>PF_3
+//     <i> Master Out Slave In for SSP0
+#define   RTE_SSP0_MOSI_PIN_SEL         4
+#if      (RTE_SSP0_MOSI_PIN_SEL == 0)
+  #define RTE_SSP0_MOSI_PORT            1
+  #define RTE_SSP0_MOSI_BIT             2
+  #define RTE_SSP0_MOSI_FUNC            5
+#elif    (RTE_SSP0_MOSI_PIN_SEL == 1)
+  #define RTE_SSP0_MOSI_PORT            3
+  #define RTE_SSP0_MOSI_BIT             7
+  #define RTE_SSP0_MOSI_FUNC            5
+#elif    (RTE_SSP0_MOSI_PIN_SEL == 2)
+  #define RTE_SSP0_MOSI_PORT            3
+  #define RTE_SSP0_MOSI_BIT             8
+  #define RTE_SSP0_MOSI_FUNC            2
+#elif    (RTE_SSP0_MOSI_PIN_SEL == 3)
+  #define RTE_SSP0_MOSI_PORT            9
+  #define RTE_SSP0_MOSI_BIT             2
+  #define RTE_SSP0_MOSI_FUNC            7
+#elif    (RTE_SSP0_MOSI_PIN_SEL == 4)
+  #define RTE_SSP0_MOSI_PORT            0xF
+  #define RTE_SSP0_MOSI_BIT             3
+  #define RTE_SSP0_MOSI_FUNC            2
+#else
+  #error "Invalid SSP0 SSP0_MOSI Pin Configuration!"
+#endif
+//   </h> Pin Configuration
+
+//   <h> DMA
+//     <e> Tx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>10 (DMAMUXPER10)
+//     </e>
+#define   RTE_SSP0_DMA_TX_EN            0
+#define   RTE_SSP0_DMA_TX_CH            0
+#define   RTE_SSP0_DMA_TX_PERI_ID       0
+#if      (RTE_SSP0_DMA_TX_PERI_ID == 0)
+  #define RTE_SSP0_DMA_TX_PERI          10
+  #define RTE_SSP0_DMA_TX_PERI_SEL      0
+#endif
+//     <e> Rx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>9 (DMAMUXPER9)
+//     </e>
+#define   RTE_SSP0_DMA_RX_EN            0
+#define   RTE_SSP0_DMA_RX_CH            1
+#define   RTE_SSP0_DMA_RX_PERI_ID       0
+#if      (RTE_SSP0_DMA_RX_PERI_ID == 0)
+  #define RTE_SSP0_DMA_RX_PERI          9
+  #define RTE_SSP0_DMA_RX_PERI_SEL      0
+#endif
+//   </h> DMA
+// </e> SSP0 (Synchronous Serial Port 0) [Driver_SPI0]
+
+// <e> SSP1 (Synchronous Serial Port 1) [Driver_SPI1]
+// <i> Configuration settings for Driver_SPI1 in component ::Drivers:SPI
+#define   RTE_SSP1                      0
+
+//   <h> Pin Configuration
+//     <o> SSP1_SSEL <0=>Not used <1=>P1_5 <2=>P1_20 <3=>PF_5
+//     <i> Slave Select for SSP1
+#define   RTE_SSP1_SSEL_PIN_SEL         1
+#if      (RTE_SSP1_SSEL_PIN_SEL == 0)
+  #define RTE_SSP1_SSEL_PIN_EN          0
+#elif    (RTE_SSP1_SSEL_PIN_SEL == 1)
+  #define RTE_SSP1_SSEL_PORT            1
+  #define RTE_SSP1_SSEL_BIT             5
+  #define RTE_SSP1_SSEL_FUNC            5
+  #define RTE_SSP1_SSEL_GPIO_FUNC       0
+  #define RTE_SSP1_SSEL_GPIO_PORT       1
+  #define RTE_SSP1_SSEL_GPIO_BIT        8
+#elif    (RTE_SSP1_SSEL_PIN_SEL == 2)
+  #define RTE_SSP1_SSEL_PORT            1
+  #define RTE_SSP1_SSEL_BIT             20
+  #define RTE_SSP1_SSEL_FUNC            1
+  #define RTE_SSP1_SSEL_GPIO_FUNC       0
+  #define RTE_SSP1_SSEL_GPIO_PORT       0
+  #define RTE_SSP1_SSEL_GPIO_BIT        15
+#elif    (RTE_SSP1_SSEL_PIN_SEL == 3)
+  #define RTE_SSP1_SSEL_PORT            0xF
+  #define RTE_SSP1_SSEL_BIT             5
+  #define RTE_SSP1_SSEL_FUNC            2
+  #define RTE_SSP1_SSEL_GPIO_FUNC       4
+  #define RTE_SSP1_SSEL_GPIO_PORT       7
+  #define RTE_SSP1_SSEL_GPIO_BIT        19
+#else
+  #error "Invalid SSP1 SSP1_SSEL Pin Configuration!"
+#endif
+#ifndef   RTE_SSP1_SSEL_PIN_EN
+#define   RTE_SSP1_SSEL_PIN_EN          1
+#endif
+//     <o> SSP1_SCK <0=>P1_19 <1=>PF_4 <2=>CLK0
+//     <i> Serial clock for SSP1
+#define   RTE_SSP1_SCK_PIN_SEL          0
+#if      (RTE_SSP1_SCK_PIN_SEL == 0)
+  #define RTE_SSP1_SCK_PORT             1
+  #define RTE_SSP1_SCK_BIT              19
+  #define RTE_SSP1_SCK_FUNC             1
+#elif    (RTE_SSP1_SCK_PIN_SEL == 1)
+  #define RTE_SSP1_SCK_PORT             0xF
+  #define RTE_SSP1_SCK_BIT              4
+  #define RTE_SSP1_SCK_FUNC             0
+#elif    (RTE_SSP1_SCK_PIN_SEL == 2)
+  #define RTE_SSP1_SCK_PORT             0x10
+  #define RTE_SSP1_SCK_BIT              0
+  #define RTE_SSP1_SCK_FUNC             6
+#else
+  #error "Invalid SSP1 SSP1_SCK Pin Configuration!"
+#endif
+//     <o> SSP1_MISO <0=>P0_0 <1=>P1_3 <2=>PF_6
+//     <i> Master In Slave Out for SSP1
+#define   RTE_SSP1_MISO_PIN_SEL         0
+#if      (RTE_SSP1_MISO_PIN_SEL == 0)
+  #define RTE_SSP1_MISO_PORT            0
+  #define RTE_SSP1_MISO_BIT             0
+  #define RTE_SSP1_MISO_FUNC            1
+#elif    (RTE_SSP1_MISO_PIN_SEL == 1)
+  #define RTE_SSP1_MISO_PORT            1
+  #define RTE_SSP1_MISO_BIT             3
+  #define RTE_SSP1_MISO_FUNC            5
+#elif    (RTE_SSP1_MISO_PIN_SEL == 2)
+  #define RTE_SSP1_MISO_PORT            0xF
+  #define RTE_SSP1_MISO_BIT             6
+  #define RTE_SSP1_MISO_FUNC            2
+#else
+  #error "Invalid SSP1 SSP1_MISO Pin Configuration!"
+#endif
+//     <o> SSP1_MOSI <0=>P0_1 <1=>P1_4 <2=>PF_7
+//     <i> Master Out Slave In for SSP1
+#define   RTE_SSP1_MOSI_PIN_SEL         0
+#if      (RTE_SSP1_MOSI_PIN_SEL == 0)
+  #define RTE_SSP1_MOSI_PORT            0
+  #define RTE_SSP1_MOSI_BIT             1
+  #define RTE_SSP1_MOSI_FUNC            1
+#elif    (RTE_SSP1_MOSI_PIN_SEL == 1)
+  #define RTE_SSP1_MOSI_PORT            1
+  #define RTE_SSP1_MOSI_BIT             4
+  #define RTE_SSP1_MOSI_FUNC            5
+#elif    (RTE_SSP1_MOSI_PIN_SEL == 2)
+  #define RTE_SSP1_MOSI_PORT            0xF
+  #define RTE_SSP1_MOSI_BIT             7
+  #define RTE_SSP1_MOSI_FUNC            2
+#else
+  #error "Invalid SSP1 SSP1_MOSI Pin Configuration!"
+#endif
+//   </h> Pin Configuration
+
+//   <h> DMA
+//     <e> Tx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>3 (DMAMUXPER3) <1=>5 (DMAMUXPER5) <2=>12 (DMAMUXPER12) <3=>14 (DMAMUXPER14)
+//     </e>
+#define   RTE_SSP1_DMA_TX_EN            0
+#define   RTE_SSP1_DMA_TX_CH            0
+#define   RTE_SSP1_DMA_TX_PERI_ID       0
+#if      (RTE_SSP1_DMA_TX_PERI_ID == 0)
+  #define RTE_SSP1_DMA_TX_PERI          3
+  #define RTE_SSP1_DMA_TX_PERI_SEL      3
+#elif    (RTE_SSP1_DMA_TX_PERI_ID == 1)
+  #define RTE_SSP1_DMA_TX_PERI          5
+  #define RTE_SSP1_DMA_TX_PERI_SEL      2
+#elif    (RTE_SSP1_DMA_TX_PERI_ID == 2)
+  #define RTE_SSP1_DMA_TX_PERI          12
+  #define RTE_SSP1_DMA_TX_PERI_SEL      0
+#elif    (RTE_SSP1_DMA_TX_PERI_ID == 3)
+  #define RTE_SSP1_DMA_TX_PERI          14
+  #define RTE_SSP1_DMA_TX_PERI_SEL      2
+#endif
+//     <e> Rx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>4 (DMAMUXPER4) <1=>6 (DMAMUXPER6) <2=>11 (DMAMUXPER11) <3=>13 (DMAMUXPER13)
+//     </e>
+#define   RTE_SSP1_DMA_RX_EN            0
+#define   RTE_SSP1_DMA_RX_CH            1
+#define   RTE_SSP1_DMA_RX_PERI_ID       0
+#if      (RTE_SSP1_DMA_RX_PERI_ID == 0)
+  #define RTE_SSP1_DMA_RX_PERI          4
+  #define RTE_SSP1_DMA_RX_PERI_SEL      3
+#elif    (RTE_SSP1_DMA_RX_PERI_ID == 1)
+  #define RTE_SSP1_DMA_RX_PERI          6
+  #define RTE_SSP1_DMA_RX_PERI_SEL      2
+#elif    (RTE_SSP1_DMA_RX_PERI_ID == 2)
+  #define RTE_SSP1_DMA_RX_PERI          11
+  #define RTE_SSP1_DMA_RX_PERI_SEL      0
+#elif    (RTE_SSP1_DMA_RX_PERI_ID == 3)
+  #define RTE_SSP1_DMA_RX_PERI          13
+  #define RTE_SSP1_DMA_RX_PERI_SEL      2
+#endif
+//   </h> DMA
+// </e> SSP1 (Synchronous Serial Port 1) [Driver_SPI1]
+
+// <e> I2S0 (Integrated Interchip Sound 0) [Driver_SAI0]
+// <i> Configuration settings for Driver_SAI0 in component ::Drivers:SAI
+#define   RTE_I2S0                      0
+
+//   <h> Pin Configuration
+//     <o> I2S0_RX_SCK <0=>Not used <1=>P3_0 <2=>P6_0 <3=>PF_4
+//     <i> Receive clock for I2S0
+#define   RTE_I2S0_RX_SCK_PIN_SEL       2
+#if      (RTE_I2S0_RX_SCK_PIN_SEL == 0)
+#define   RTE_I2S0_RX_SCK_PIN_EN        0
+#elif    (RTE_I2S0_RX_SCK_PIN_SEL == 1)
+  #define RTE_I2S0_RX_SCK_PORT          3
+  #define RTE_I2S0_RX_SCK_BIT           0
+  #define RTE_I2S0_RX_SCK_FUNC          0
+#elif    (RTE_I2S0_RX_SCK_PIN_SEL == 2)
+  #define RTE_I2S0_RX_SCK_PORT          6
+  #define RTE_I2S0_RX_SCK_BIT           0
+  #define RTE_I2S0_RX_SCK_FUNC          4
+#elif    (RTE_I2S0_RX_SCK_PIN_SEL == 3)
+  #define RTE_I2S0_RX_SCK_PORT          0xF
+  #define RTE_I2S0_RX_SCK_BIT           4
+  #define RTE_I2S0_RX_SCK_FUNC          7
+#else
+  #error "Invalid I2S0 I2S0_RX_SCK Pin Configuration!"
+#endif
+#ifndef   RTE_I2S0_RX_SCK_PIN_EN
+#define   RTE_I2S0_RX_SCK_PIN_EN        1
+#endif
+//     <o> I2S0_RX_WS <0=>Not used <1=>P3_1 <2=>P6_1
+//     <i> Receive word select for I2S0
+#define   RTE_I2S0_RX_WS_PIN_SEL        2
+#if      (RTE_I2S0_RX_WS_PIN_SEL == 0)
+#define   RTE_I2S0_RX_WS_PIN_EN         0
+#elif    (RTE_I2S0_RX_WS_PIN_SEL == 1)
+  #define RTE_I2S0_RX_WS_PORT           3
+  #define RTE_I2S0_RX_WS_BIT            1
+  #define RTE_I2S0_RX_WS_FUNC           1
+#elif    (RTE_I2S0_RX_WS_PIN_SEL == 2)
+  #define RTE_I2S0_RX_WS_PORT           6
+  #define RTE_I2S0_RX_WS_BIT            1
+  #define RTE_I2S0_RX_WS_FUNC           3
+#else
+  #error "Invalid I2S0 I2S0_RX_WS Pin Configuration!"
+#endif
+#ifndef   RTE_I2S0_RX_WS_PIN_EN
+#define   RTE_I2S0_RX_WS_PIN_EN         1
+#endif
+//     <o> I2S0_RX_SDA <0=>Not used <1=>P3_2 <2=>P6_2
+//     <i> Receive master clock for I2S0
+#define   RTE_I2S0_RX_SDA_PIN_SEL       2
+#if      (RTE_I2S0_RX_SDA_PIN_SEL == 0)
+#define   RTE_I2S0_RX_SDA_PIN_EN        0
+#elif    (RTE_I2S0_RX_SDA_PIN_SEL == 1)
+  #define RTE_I2S0_RX_SDA_PORT          3
+  #define RTE_I2S0_RX_SDA_BIT           2
+  #define RTE_I2S0_RX_SDA_FUNC          1
+#elif    (RTE_I2S0_RX_SDA_PIN_SEL == 2)
+  #define RTE_I2S0_RX_SDA_PORT          6
+  #define RTE_I2S0_RX_SDA_BIT           2
+  #define RTE_I2S0_RX_SDA_FUNC          3
+#else
+  #error "Invalid I2S0 I2S0_RX_SDA Pin Configuration!"
+#endif
+#ifndef   RTE_I2S0_RX_SDA_PIN_EN
+#define   RTE_I2S0_RX_SDA_PIN_EN       1
+#endif
+//     <o> I2S0_RX_MCLK <0=>Not used <1=>P1_19 <2=>P3_0 <3=>P6_0
+//     <i> Receive master clock for I2S0
+#define   RTE_I2S0_RX_MCLK_PIN_SEL      0
+#if      (RTE_I2S0_RX_MCLK_PIN_SEL == 0)
+#define   RTE_I2S0_RX_MCLK_PIN_EN       0
+#elif    (RTE_I2S0_RX_MCLK_PIN_SEL == 1)
+  #define RTE_I2S0_RX_MCLK_PORT         1
+  #define RTE_I2S0_RX_MCLK_BIT          19
+  #define RTE_I2S0_RX_MCLK_FUNC         6
+#elif    (RTE_I2S0_RX_MCLK_PIN_SEL == 2)
+  #define RTE_I2S0_RX_MCLK_PORT         3
+  #define RTE_I2S0_RX_MCLK_BIT          0
+  #define RTE_I2S0_RX_MCLK_FUNC         1
+#elif    (RTE_I2S0_RX_MCLK_PIN_SEL == 3)
+  #define RTE_I2S0_RX_MCLK_PORT         6
+  #define RTE_I2S0_RX_MCLK_BIT          0
+  #define RTE_I2S0_RX_MCLK_FUNC         1
+#else
+  #error "Invalid I2S0 I2S0_RX_MCLK Pin Configuration!"
+#endif
+#ifndef   RTE_I2S0_RX_MCLK_PIN_EN
+#define   RTE_I2S0_RX_MCLK_PIN_EN       1
+#endif
+//     <o> I2S0_TX_SCK <0=>Not used <1=>P3_0 <2=>P4_7
+//     <i> Transmit clock for I2S0
+#define   RTE_I2S0_TX_SCK_PIN_SEL       1
+#if      (RTE_I2S0_TX_SCK_PIN_SEL == 0)
+#define   RTE_I2S0_TX_SCK_PIN_EN        0
+#elif    (RTE_I2S0_TX_SCK_PIN_SEL == 1)
+  #define RTE_I2S0_TX_SCK_PORT          3
+  #define RTE_I2S0_TX_SCK_BIT           0
+  #define RTE_I2S0_TX_SCK_FUNC          2
+#elif    (RTE_I2S0_TX_SCK_PIN_SEL == 2)
+  #define RTE_I2S0_TX_SCK_PORT          4
+  #define RTE_I2S0_TX_SCK_BIT           7
+  #define RTE_I2S0_TX_SCK_FUNC          7
+#else
+  #error "Invalid I2S0 I2S0_TX_SCK Pin Configuration!"
+#endif
+#ifndef   RTE_I2S0_TX_SCK_PIN_EN
+#define   RTE_I2S0_TX_SCK_PIN_EN        1
+#endif
+//     <o> I2S0_TX_WS <0=>Not used <1=>P0_0 <2=>P3_1 <3=>P3_4 <4=>P7_1 <5=>P9_1 <6=>PC_13
+//     <i> Transmit word select for I2S0
+#define   RTE_I2S0_TX_WS_PIN_SEL        4
+#if      (RTE_I2S0_TX_WS_PIN_SEL == 0)
+#define   RTE_I2S0_TX_WS_PIN_EN         0
+#elif    (RTE_I2S0_TX_WS_PIN_SEL == 1)
+  #define RTE_I2S0_TX_WS_PORT           0
+  #define RTE_I2S0_TX_WS_BIT            0
+  #define RTE_I2S0_TX_WS_FUNC           6
+#elif    (RTE_I2S0_TX_WS_PIN_SEL == 2)
+  #define RTE_I2S0_TX_WS_PORT           3
+  #define RTE_I2S0_TX_WS_BIT            1
+  #define RTE_I2S0_TX_WS_FUNC           0
+#elif    (RTE_I2S0_TX_WS_PIN_SEL == 3)
+  #define RTE_I2S0_TX_WS_PORT           3
+  #define RTE_I2S0_TX_WS_BIT            4
+  #define RTE_I2S0_TX_WS_FUNC           5
+#elif    (RTE_I2S0_TX_WS_PIN_SEL == 4)
+  #define RTE_I2S0_TX_WS_PORT           7
+  #define RTE_I2S0_TX_WS_BIT            1
+  #define RTE_I2S0_TX_WS_FUNC           2
+#elif    (RTE_I2S0_TX_WS_PIN_SEL == 5)
+  #define RTE_I2S0_TX_WS_PORT           9
+  #define RTE_I2S0_TX_WS_BIT            1
+  #define RTE_I2S0_TX_WS_FUNC           4
+#elif    (RTE_I2S0_TX_WS_PIN_SEL == 6)
+  #define RTE_I2S0_TX_WS_PORT           0xC
+  #define RTE_I2S0_TX_WS_BIT            13
+  #define RTE_I2S0_TX_WS_FUNC           6
+#else
+  #error "Invalid I2S0 I2S0_TX_WS Pin Configuration!"
+#endif
+#ifndef   RTE_I2S0_TX_WS_PIN_EN
+#define   RTE_I2S0_TX_WS_PIN_EN         1
+#endif
+//     <o> I2S0_TX_SDA <0=>Not used <1=>P3_2 <2=>P3_5 <3=>P7_2 <4=>P9_2  <5=>PC_12
+//     <i> Transmit data for I2S0
+#define   RTE_I2S0_TX_SDA_PIN_SEL       3
+#if      (RTE_I2S0_TX_SDA_PIN_SEL == 0)
+#define   RTE_I2S0_TX_SDA_PIN_EN        0
+#elif    (RTE_I2S0_TX_SDA_PIN_SEL == 1)
+  #define RTE_I2S0_TX_SDA_PORT          3
+  #define RTE_I2S0_TX_SDA_BIT           2
+  #define RTE_I2S0_TX_SDA_FUNC          0
+#elif    (RTE_I2S0_TX_SDA_PIN_SEL == 2)
+  #define RTE_I2S0_TX_SDA_PORT          3
+  #define RTE_I2S0_TX_SDA_BIT           5
+  #define RTE_I2S0_TX_SDA_FUNC          5
+#elif    (RTE_I2S0_TX_SDA_PIN_SEL == 3)
+  #define RTE_I2S0_TX_SDA_PORT          7
+  #define RTE_I2S0_TX_SDA_BIT           2
+  #define RTE_I2S0_TX_SDA_FUNC          2
+#elif    (RTE_I2S0_TX_SDA_PIN_SEL == 4)
+  #define RTE_I2S0_TX_SDA_PORT          9
+  #define RTE_I2S0_TX_SDA_BIT           2
+  #define RTE_I2S0_TX_SDA_FUNC          4
+#elif    (RTE_I2S0_TX_SDA_PIN_SEL == 5)
+  #define RTE_I2S0_TX_SDA_PORT          0xC
+  #define RTE_I2S0_TX_SDA_BIT           12
+  #define RTE_I2S0_TX_SDA_FUNC          6
+#else
+  #error "Invalid I2S0 I2S0_TX_SDA Pin Configuration!"
+#endif
+#ifndef   RTE_I2S0_TX_SDA_PIN_EN
+#define   RTE_I2S0_TX_SDA_PIN_EN        1
+#endif
+//     <o> I2S0_TX_MCLK <0=>Not used <1=>P3_0 <2=>P3_3 <3=>PF_4 <4=>CLK2
+//     <i> Transmit master clock for I2S0
+#define   RTE_I2S0_TX_MCLK_PIN_SEL      2
+#if      (RTE_I2S0_TX_MCLK_PIN_SEL == 0)
+#define   RTE_I2S0_TX_MCLK_PIN_EN       0
+#elif    (RTE_I2S0_TX_MCLK_PIN_SEL == 1)
+  #define RTE_I2S0_TX_MCLK_PORT         3
+  #define RTE_I2S0_TX_MCLK_BIT          0
+  #define RTE_I2S0_TX_MCLK_FUNC         3
+#elif    (RTE_I2S0_TX_MCLK_PIN_SEL == 2)
+  #define RTE_I2S0_TX_MCLK_PORT         3
+  #define RTE_I2S0_TX_MCLK_BIT          3
+  #define RTE_I2S0_TX_MCLK_FUNC         6
+#elif    (RTE_I2S0_TX_MCLK_PIN_SEL == 3)
+  #define RTE_I2S0_TX_MCLK_PORT         0xf
+  #define RTE_I2S0_TX_MCLK_BIT          4
+  #define RTE_I2S0_TX_MCLK_FUNC         6
+#elif    (RTE_I2S0_TX_MCLK_PIN_SEL == 4)
+  #define RTE_I2S0_TX_MCLK_PORT         0x10
+  #define RTE_I2S0_TX_MCLK_BIT          2
+  #define RTE_I2S0_TX_MCLK_FUNC         6
+#else
+  #error "Invalid I2S0 I2S0_TX_MCLK Pin Configuration!"
+#endif
+#ifndef   RTE_I2S0_TX_MCLK_PIN_EN
+#define   RTE_I2S0_TX_MCLK_PIN_EN       1
+#endif
+//   </h> Pin Configuration
+
+//   <h> DMA
+//     <e> Tx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>9 (DMAMUXPER9)
+//     </e>
+#define   RTE_I2S0_DMA_TX_EN            0
+#define   RTE_I2S0_DMA_TX_CH            0
+#define   RTE_I2S0_DMA_TX_PERI_ID       0
+#if      (RTE_I2S0_DMA_TX_PERI_ID == 0)
+  #define RTE_I2S0_DMA_TX_PERI          9
+  #define RTE_I2S0_DMA_TX_PERI_SEL      1
+#endif
+//     <e> Rx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>10 (DMAMUXPER10)
+//     </e>
+#define   RTE_I2S0_DMA_RX_EN            0
+#define   RTE_I2S0_DMA_RX_CH            1
+#define   RTE_I2S0_DMA_RX_PERI_ID       0
+#if      (RTE_I2S0_DMA_RX_PERI_ID == 0)
+  #define RTE_I2S0_DMA_RX_PERI          10
+  #define RTE_I2S0_DMA_RX_PERI_SEL      1
+#endif
+//   </h> DMA
+// </e> I2S0 (Integrated Interchip Sound 0) [Driver_SAI0]
+
+// <e> I2S1 (Integrated Interchip Sound 1) [Driver_SAI1]
+// <i> Configuration settings for Driver_I2S1 in component ::Drivers:SAI
+#define   RTE_I2S1                      0
+
+//   <h> Pin Configuration
+//     <o> I2S1_RX_SCK <0=>Not used <1=>CLK2 <2=>CLK3
+//     <i> Receive clock for I2S1
+#define   RTE_I2S1_RX_SCK_PIN_SEL       0
+#if      (RTE_I2S1_RX_SCK_PIN_SEL == 0)
+#define   RTE_I2S1_RX_SCK_PIN_EN        0
+#elif    (RTE_I2S1_RX_SCK_PIN_SEL == 1)
+  #define RTE_I2S1_RX_SCK_PORT          0x10
+  #define RTE_I2S1_RX_SCK_BIT           2
+  #define RTE_I2S1_RX_SCK_FUNC          7
+#elif    (RTE_I2S1_RX_SCK_PIN_SEL == 2)
+  #define RTE_I2S1_RX_SCK_PORT          0x10
+  #define RTE_I2S1_RX_SCK_BIT           3
+  #define RTE_I2S1_RX_SCK_FUNC          7
+#else
+  #error "Invalid I2S1 I2S1_RX_SCK Pin Configuration!"
+#endif
+#ifndef   RTE_I2S1_RX_SCK_PIN_EN
+#define   RTE_I2S1_RX_SCK_PIN_EN        1
+#endif
+//     <o> I2S1_RX_WS <0=>Not used <1=>P3_5
+//     <i> Receive word select for I2S1
+#define   RTE_I2S1_RX_WS_PIN_SEL        0
+#if      (RTE_I2S1_RX_WS_PIN_SEL == 0)
+#define   RTE_I2S1_RX_WS_PIN_EN         0
+#elif    (RTE_I2S1_RX_WS_PIN_SEL == 1)
+  #define RTE_I2S1_RX_WS_PORT           3
+  #define RTE_I2S1_RX_WS_BIT            5
+  #define RTE_I2S1_RX_WS_FUNC           6
+#else
+  #error "Invalid I2S1 I2S1_RX_WS Pin Configuration!"
+#endif
+#ifndef   RTE_I2S1_RX_WS_PIN_EN
+#define   RTE_I2S1_RX_WS_PIN_EN         1
+#endif
+//     <o> I2S1_RX_SDA <0=>Not used <1=>P3_4
+//     <i> Receive master clock for I2S1
+#define   RTE_I2S1_RX_SDA_PIN_SEL       0
+#if      (RTE_I2S1_RX_SDA_PIN_SEL == 0)
+#define   RTE_I2S1_RX_SDA_PIN_EN        0
+#elif    (RTE_I2S1_RX_SDA_PIN_SEL == 1)
+  #define RTE_I2S1_RX_SDA_PORT          3
+  #define RTE_I2S1_RX_SDA_BIT           4
+  #define RTE_I2S1_RX_SDA_FUNC          6
+#else
+  #error "Invalid I2S1 I2S1_RX_SDA Pin Configuration!"
+#endif
+#ifndef   RTE_I2S1_RX_SDA_PIN_EN
+#define   RTE_I2S1_RX_SDA_PIN_EN       1
+#endif
+//     <o> I2S1_RX_MCLK <0=>Not used <1=>PA_0
+//     <i> Receive master clock for I2S1
+#define   RTE_I2S1_RX_MCLK_PIN_SEL      0
+#if      (RTE_I2S1_RX_MCLK_PIN_SEL == 0)
+#define   RTE_I2S1_RX_MCLK_PIN_EN       0
+#elif    (RTE_I2S1_RX_MCLK_PIN_SEL == 1)
+  #define RTE_I2S1_RX_MCLK_PORT         0x0A
+  #define RTE_I2S1_RX_MCLK_BIT          0
+  #define RTE_I2S1_RX_MCLK_FUNC         5
+#else
+  #error "Invalid I2S1 I2S1_RX_MCLK Pin Configuration!"
+#endif
+#ifndef   RTE_I2S1_RX_MCLK_PIN_EN
+#define   RTE_I2S1_RX_MCLK_PIN_EN       1
+#endif
+//     <o> I2S1_TX_SCK <0=>Not used <1=>P1_19 <2=>P3_3 <3=>P4_7
+//     <i> Transmit clock for I2S1
+#define   RTE_I2S1_TX_SCK_PIN_SEL       0
+#if      (RTE_I2S1_TX_SCK_PIN_SEL == 0)
+#define   RTE_I2S1_TX_SCK_PIN_EN        0
+#elif    (RTE_I2S1_TX_SCK_PIN_SEL == 1)
+  #define RTE_I2S1_TX_SCK_PORT          1
+  #define RTE_I2S1_TX_SCK_BIT           19
+  #define RTE_I2S1_TX_SCK_FUNC          7
+#elif    (RTE_I2S1_TX_SCK_PIN_SEL == 2)
+  #define RTE_I2S1_TX_SCK_PORT          3
+  #define RTE_I2S1_TX_SCK_BIT           3
+  #define RTE_I2S1_TX_SCK_FUNC          7
+#elif    (RTE_I2S1_TX_SCK_PIN_SEL == 3)
+  #define RTE_I2S1_TX_SCK_PORT          4
+  #define RTE_I2S1_TX_SCK_BIT           7
+  #define RTE_I2S1_TX_SCK_FUNC          6
+#else
+  #error "Invalid I2S1 I2S1_TX_SCK Pin Configuration!"
+#endif
+#ifndef   RTE_I2S1_TX_SCK_PIN_EN
+#define   RTE_I2S1_TX_SCK_PIN_EN        1
+#endif
+//     <o> I2S1_TX_WS <0=>Not used <1=>P0_0 <2=>PF_7
+//     <i> Transmit word select for I2S1
+#define   RTE_I2S1_TX_WS_PIN_SEL        0
+#if      (RTE_I2S1_TX_WS_PIN_SEL == 0)
+#define   RTE_I2S1_TX_WS_PIN_EN         0
+#elif    (RTE_I2S1_TX_WS_PIN_SEL == 1)
+  #define RTE_I2S1_TX_WS_PORT           0
+  #define RTE_I2S1_TX_WS_BIT            0
+  #define RTE_I2S1_TX_WS_FUNC           7
+#elif    (RTE_I2S1_TX_WS_PIN_SEL == 2)
+  #define RTE_I2S1_TX_WS_PORT           0x0F
+  #define RTE_I2S1_TX_WS_BIT            7
+  #define RTE_I2S1_TX_WS_FUNC           7
+#else
+  #error "Invalid I2S1 I2S1_TX_WS Pin Configuration!"
+#endif
+#ifndef   RTE_I2S1_TX_WS_PIN_EN
+#define   RTE_I2S1_TX_WS_PIN_EN         1
+#endif
+//     <o> I2S1_TX_SDA <0=>Not used <1=>P0_1 <2=>PF_6
+//     <i> Transmit data for I2S
+#define   RTE_I2S1_TX_SDA_PIN_SEL       0
+#if      (RTE_I2S1_TX_SDA_PIN_SEL == 0)
+#define   RTE_I2S1_TX_SDA_PIN_EN        0
+#elif    (RTE_I2S1_TX_SDA_PIN_SEL == 1)
+  #define RTE_I2S1_TX_SDA_PORT          0
+  #define RTE_I2S1_TX_SDA_BIT           1
+  #define RTE_I2S1_TX_SDA_FUNC          7
+#elif    (RTE_I2S1_TX_SDA_PIN_SEL == 2)
+  #define RTE_I2S1_TX_SDA_PORT          0x0F
+  #define RTE_I2S1_TX_SDA_BIT           6
+  #define RTE_I2S1_TX_SDA_FUNC          7
+#else
+  #error "Invalid I2S1 I2S1_TX_SDA Pin Configuration!"
+#endif
+#ifndef   RTE_I2S1_TX_SDA_PIN_EN
+#define   RTE_I2S1_TX_SDA_PIN_EN        1
+#endif
+//     <o> I2S1_TX_MCLK <0=>Not used <1=>P8_8 <2=>PF_0 <3=>CLK1
+//     <i> Transmit master clock for I2S1
+#define   RTE_I2S1_TX_MCLK_PIN_SEL      0
+#if      (RTE_I2S1_TX_MCLK_PIN_SEL == 0)
+#define   RTE_I2S1_TX_MCLK_PIN_EN       0
+#elif    (RTE_I2S1_TX_MCLK_PIN_SEL == 1)
+  #define RTE_I2S1_TX_MCLK_PORT         8
+  #define RTE_I2S1_TX_MCLK_BIT          8
+  #define RTE_I2S1_TX_MCLK_FUNC         7
+#elif    (RTE_I2S1_TX_MCLK_PIN_SEL == 2)
+  #define RTE_I2S1_TX_MCLK_PORT         0x0F
+  #define RTE_I2S1_TX_MCLK_BIT          0
+  #define RTE_I2S1_TX_MCLK_FUNC         7
+#elif    (RTE_I2S1_TX_MCLK_PIN_SEL == 3)
+  #define RTE_I2S1_TX_MCLK_PORT         0x10
+  #define RTE_I2S1_TX_MCLK_BIT          1
+  #define RTE_I2S1_TX_MCLK_FUNC         7
+#else
+  #error "Invalid I2S1 I2S1_TX_MCLK Pin Configuration!"
+#endif
+#ifndef   RTE_I2S1_TX_MCLK_PIN_EN
+#define   RTE_I2S1_TX_MCLK_PIN_EN       1
+#endif
+//   </h> Pin Configuration
+
+//   <h> DMA
+//     <e> Tx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>3 (DMAMUXPER3)
+//     </e>
+#define   RTE_I2S1_DMA_TX_EN            0
+#define   RTE_I2S1_DMA_TX_CH            0
+#define   RTE_I2S1_DMA_TX_PERI_ID       0
+#if      (RTE_I2S1_DMA_TX_PERI_ID == 0)
+  #define RTE_I2S1_DMA_TX_PERI          3
+  #define RTE_I2S1_DMA_TX_PERI_SEL      2
+#endif
+//     <e> Rx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>4 (DMAMUXPER4)
+//     </e>
+#define   RTE_I2S1_DMA_RX_EN            0
+#define   RTE_I2S1_DMA_RX_CH            1
+#define   RTE_I2S1_DMA_RX_PERI_ID       0
+#if      (RTE_I2S1_DMA_RX_PERI_ID == 0)
+  #define RTE_I2S1_DMA_RX_PERI          4
+  #define RTE_I2S1_DMA_RX_PERI_SEL      2
+#endif
+//   </h> DMA
+// </e> I2S1 (Integrated Interchip Sound 1) [Driver_SAI1]
+
+// <e> CAN0 Controller [Driver_CAN0]
+// <i> Configuration settings for Driver_CAN0 in component ::Drivers:CAN
+#define   RTE_CAN_CAN0                  0
+
+//   <h> Pin Configuration
+//     <o> CAN0_RD <0=>Not used <1=>P3_1 <2=>PE_2
+//     <i> CAN0 receiver input.
+#define   RTE_CAN0_RD_ID                0
+#if      (RTE_CAN0_RD_ID == 0)
+  #define RTE_CAN0_RD_PIN_EN            0
+#elif    (RTE_CAN0_RD_ID == 1)
+  #define RTE_CAN0_RD_PORT              3
+  #define RTE_CAN0_RD_BIT               1
+  #define RTE_CAN0_RD_FUNC              2
+#elif    (RTE_CAN0_RD_ID == 2)
+  #define RTE_CAN0_RD_PORT              0xE
+  #define RTE_CAN0_RD_BIT               2
+  #define RTE_CAN0_RD_FUNC              1
+#else
+  #error "Invalid RTE_CAN0_RD Pin Configuration!"
+#endif
+#ifndef   RTE_CAN0_RD_PIN_EN
+  #define RTE_CAN0_RD_PIN_EN            1
+#endif
+//     <o> CAN0_TD <0=>Not used <1=>P3_2 <2=>PE_3
+//     <i> CAN0 transmitter output.
+#define   RTE_CAN0_TD_ID                0
+#if      (RTE_CAN0_TD_ID == 0)
+  #define RTE_CAN0_TD_PIN_EN            0
+#elif    (RTE_CAN0_TD_ID == 1)
+  #define RTE_CAN0_TD_PORT              3
+  #define RTE_CAN0_TD_BIT               2
+  #define RTE_CAN0_TD_FUNC              2
+#elif    (RTE_CAN0_TD_ID == 2)
+  #define RTE_CAN0_TD_PORT              0xE
+  #define RTE_CAN0_TD_BIT               3
+  #define RTE_CAN0_TD_FUNC              1
+#else
+  #error "Invalid RTE_CAN0_TD Pin Configuration!"
+#endif
+#ifndef   RTE_CAN0_TD_PIN_EN
+  #define RTE_CAN0_TD_PIN_EN            1
+#endif
+//   </h> Pin Configuration
+// </e> CAN0 Controller [Driver_CAN0]
+
+// <e> CAN1 Controller [Driver_CAN1]
+// <i> Configuration settings for Driver_CAN1 in component ::Drivers:CAN
+#define   RTE_CAN_CAN1                  0
+
+//   <h> Pin Configuration
+//     <o> CAN1_RD <0=>Not used <1=>P1_18 <2=>P4_9 <3=>PE_1
+//     <i> CAN1 receiver input.
+#define   RTE_CAN1_RD_ID                0
+#if      (RTE_CAN1_RD_ID == 0)
+  #define RTE_CAN1_RD_PIN_EN            0
+#elif    (RTE_CAN1_RD_ID == 1)
+  #define RTE_CAN1_RD_PORT              1
+  #define RTE_CAN1_RD_BIT               18
+  #define RTE_CAN1_RD_FUNC              5
+#elif    (RTE_CAN1_RD_ID == 2)
+  #define RTE_CAN1_RD_PORT              4
+  #define RTE_CAN1_RD_BIT               9
+  #define RTE_CAN1_RD_FUNC              6
+#elif    (RTE_CAN1_RD_ID == 3)
+  #define RTE_CAN1_RD_PORT              0xE
+  #define RTE_CAN1_RD_BIT               1
+  #define RTE_CAN1_RD_FUNC              5
+#else
+  #error "Invalid RTE_CAN1_RD Pin Configuration!"
+#endif
+#ifndef   RTE_CAN1_RD_PIN_EN
+  #define RTE_CAN1_RD_PIN_EN            1
+#endif
+//     <o> CAN1_TD <0=>Not used <1=>P1_17 <2=>P4_8 <3=>PE_0
+//     <i> CAN1 transmitter output.
+#define   RTE_CAN1_TD_ID                0
+#if      (RTE_CAN1_TD_ID == 0)
+  #define RTE_CAN1_TD_PIN_EN            0
+#elif    (RTE_CAN1_TD_ID == 1)
+  #define RTE_CAN1_TD_PORT              1
+  #define RTE_CAN1_TD_BIT               17
+  #define RTE_CAN1_TD_FUNC              5
+#elif    (RTE_CAN1_TD_ID == 2)
+  #define RTE_CAN1_TD_PORT              4
+  #define RTE_CAN1_TD_BIT               8
+  #define RTE_CAN1_TD_FUNC              6
+#elif    (RTE_CAN1_TD_ID == 3)
+  #define RTE_CAN1_TD_PORT              0xE
+  #define RTE_CAN1_TD_BIT               0
+  #define RTE_CAN1_TD_FUNC              5
+#else
+  #error "Invalid RTE_CAN1_TD Pin Configuration!"
+#endif
+#ifndef   RTE_CAN1_TD_PIN_EN
+  #define RTE_CAN1_TD_PIN_EN            1
+#endif
+//   </h> Pin Configuration
+// </e> CAN1 Controller [Driver_CAN1]
+
+
+#endif  /* __RTE_DEVICE_H */

CMSIS/Pack/Example/Boards/Keil/MCB1800/RTX_Blinky/RTE/Device/LPC1857/startup_LPC18xx.s

@@ -0,0 +1,324 @@
+;/***********************************************************************
+; * $Id: startup_LPC18xx.s 6471 2011-02-16 17:13:35Z nxp27266 $
+; *
+; * Project: LPC18xx CMSIS Package
+; *
+; * Description: Cortex-M3 Core Device Startup File for the NXP LPC18xx
+; *              Device Series.
+; *
+; * Copyright(C) 2011, NXP Semiconductor
+; * All rights reserved.
+; *
+; *                                                      modified by KEIL
+; ***********************************************************************
+; * Software that is described herein is for illustrative purposes only
+; * which provides customers with programming information regarding the
+; * products. This software is supplied "AS IS" without any warranties.
+; * NXP Semiconductors assumes no responsibility or liability for the
+; * use of the software, conveys no license or title under any patent,
+; * copyright, or mask work right to the product. NXP Semiconductors
+; * reserves the right to make changes in the software without
+; * notification. NXP Semiconductors also make no representation or
+; * warranty that such application will be suitable for the specified
+; * use without further testing or modification.
+; **********************************************************************/
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+
+Sign_Value      EQU     0x5A5A5A5A
+
+__Vectors       DCD     __initial_sp              ; 0 Top of Stack
+                DCD     Reset_Handler             ; 1 Reset Handler
+                DCD     NMI_Handler               ; 2 NMI Handler
+                DCD     HardFault_Handler         ; 3 Hard Fault Handler
+                DCD     MemManage_Handler         ; 4 MPU Fault Handler
+                DCD     BusFault_Handler          ; 5 Bus Fault Handler
+                DCD     UsageFault_Handler        ; 6 Usage Fault Handler
+                DCD     Sign_Value                ; 7 Reserved
+                DCD     0                         ; 8 Reserved
+                DCD     0                         ; 9 Reserved
+                DCD     0                         ; 10 Reserved
+                DCD     SVC_Handler               ; 11 SVCall Handler
+                DCD     DebugMon_Handler          ; 12 Debug Monitor Handler
+                DCD     0                         ; 13 Reserved
+                DCD     PendSV_Handler            ; 14 PendSV Handler
+                DCD     SysTick_Handler           ; 15 SysTick Handler
+
+                ; External Interrupts
+                DCD     DAC_IRQHandler            ; 16 D/A Converter
+                DCD     0                         ; 17 Reserved
+                DCD     DMA_IRQHandler            ; 18 General Purpose DMA
+                DCD     0                         ; 19 Reserved
+                DCD     FLASHEEPROM_IRQHandler    ; 20 ORed flash bank A, flash bank B, EEPROM interrupt
+                DCD     ETH_IRQHandler            ; 21 Ethernet
+                DCD     SDIO_IRQHandler           ; 22 SD/MMC
+                DCD     LCD_IRQHandler            ; 23 LCD
+                DCD     USB0_IRQHandler           ; 24 USB0
+                DCD     USB1_IRQHandler           ; 25 USB1
+                DCD     SCT_IRQHandler            ; 26 State Configurable Timer
+                DCD     RIT_IRQHandler            ; 27 Repetitive Interrupt Timer
+                DCD     TIMER0_IRQHandler         ; 28 Timer0
+                DCD     TIMER1_IRQHandler         ; 29 Timer1
+                DCD     TIMER2_IRQHandler         ; 30 Timer2
+                DCD     TIMER3_IRQHandler         ; 31 Timer3
+                DCD     MCPWM_IRQHandler          ; 32 Motor Control PWM
+                DCD     ADC0_IRQHandler           ; 33 A/D Converter 0
+                DCD     I2C0_IRQHandler           ; 34 I2C0
+                DCD     I2C1_IRQHandler           ; 35 I2C1
+                DCD     0                         ; 36 Reserved
+                DCD     ADC1_IRQHandler           ; 37 A/D Converter 1
+                DCD     SSP0_IRQHandler           ; 38 SSP0
+                DCD     SSP1_IRQHandler           ; 39 SSP1
+                DCD     UART0_IRQHandler          ; 40 UART0
+                DCD     UART1_IRQHandler          ; 41 UART1
+                DCD     UART2_IRQHandler          ; 42 UART2
+                DCD     UART3_IRQHandler          ; 43 UART3
+                DCD     I2S0_IRQHandler           ; 44 I2S0
+                DCD     I2S1_IRQHandler           ; 45 I2S1
+                DCD     0                         ; 46 Reserved
+                DCD     0                         ; 47 Reserved
+                DCD     GPIO0_IRQHandler          ; 48 GPIO0
+                DCD     GPIO1_IRQHandler          ; 49 GPIO1
+                DCD     GPIO2_IRQHandler          ; 50 GPIO2
+                DCD     GPIO3_IRQHandler          ; 51 GPIO3
+                DCD     GPIO4_IRQHandler          ; 52 GPIO4
+                DCD     GPIO5_IRQHandler          ; 53 GPIO5
+                DCD     GPIO6_IRQHandler          ; 54 GPIO6
+                DCD     GPIO7_IRQHandler          ; 55 GPIO7
+                DCD     GINT0_IRQHandler          ; 56 GINT0
+                DCD     GINT1_IRQHandler          ; 57 GINT1
+                DCD     EVRT_IRQHandler           ; 58 Event Router
+                DCD     CAN1_IRQHandler           ; 59 C_CAN1
+                DCD     0                         ; 60 Reserved
+                DCD     0                         ; 61 Reserved
+                DCD     ATIMER_IRQHandler         ; 62 ATIMER
+                DCD     RTC_IRQHandler            ; 63 RTC
+                DCD     0                         ; 64 Reserved
+                DCD     WDT_IRQHandler            ; 65 WDT
+                DCD     0                         ; 66 Reserved
+                DCD     CAN0_IRQHandler           ; 67 C_CAN0
+                DCD     QEI_IRQHandler            ; 68 QEI
+
+
+;CRP address at offset 0x2FC relative to the BOOT Bank address
+                IF      :LNOT::DEF:NO_CRP
+                SPACE   (0x2FC - (. - __Vectors))
+;                EXPORT  CRP_Key
+CRP_Key         DCD     0xFFFFFFFF
+;                       0xFFFFFFFF => CRP Disabled
+;                       0x12345678 => CRP Level 1
+;                       0x87654321 => CRP Level 2
+;                       0x43218765 => CRP Level 3 (ARE YOU SURE?)
+;                       0x4E697370 => NO ISP      (ARE YOU SURE?)
+                ENDIF
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler           [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler             [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler       [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler       [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler        [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler      [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler             [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler        [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler          [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler         [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  DAC_IRQHandler          [WEAK]
+                EXPORT  DMA_IRQHandler          [WEAK]
+                EXPORT  FLASHEEPROM_IRQHandler  [WEAK]
+                EXPORT  ETH_IRQHandler          [WEAK]
+                EXPORT  SDIO_IRQHandler         [WEAK]
+                EXPORT  LCD_IRQHandler          [WEAK]
+                EXPORT  USB0_IRQHandler         [WEAK]
+                EXPORT  USB1_IRQHandler         [WEAK]
+                EXPORT  SCT_IRQHandler          [WEAK]
+                EXPORT  RIT_IRQHandler          [WEAK]
+                EXPORT  TIMER0_IRQHandler       [WEAK]
+                EXPORT  TIMER1_IRQHandler       [WEAK]
+                EXPORT  TIMER2_IRQHandler       [WEAK]
+                EXPORT  TIMER3_IRQHandler       [WEAK]
+                EXPORT  MCPWM_IRQHandler        [WEAK]
+                EXPORT  ADC0_IRQHandler         [WEAK]
+                EXPORT  I2C0_IRQHandler         [WEAK]
+                EXPORT  I2C1_IRQHandler         [WEAK]
+                EXPORT  ADC1_IRQHandler         [WEAK]
+                EXPORT  SSP0_IRQHandler         [WEAK]
+                EXPORT  SSP1_IRQHandler         [WEAK]
+                EXPORT  UART0_IRQHandler        [WEAK]
+                EXPORT  UART1_IRQHandler        [WEAK]
+                EXPORT  UART2_IRQHandler        [WEAK]
+                EXPORT  UART3_IRQHandler        [WEAK]
+                EXPORT  I2S0_IRQHandler         [WEAK]
+                EXPORT  I2S1_IRQHandler         [WEAK]
+                EXPORT  GPIO0_IRQHandler        [WEAK]
+                EXPORT  GPIO1_IRQHandler        [WEAK]
+                EXPORT  GPIO2_IRQHandler        [WEAK]
+                EXPORT  GPIO3_IRQHandler        [WEAK]
+                EXPORT  GPIO4_IRQHandler        [WEAK]
+                EXPORT  GPIO5_IRQHandler        [WEAK]
+                EXPORT  GPIO6_IRQHandler        [WEAK]
+                EXPORT  GPIO7_IRQHandler        [WEAK]
+                EXPORT  GINT0_IRQHandler        [WEAK]
+                EXPORT  GINT1_IRQHandler        [WEAK]
+                EXPORT  EVRT_IRQHandler         [WEAK]
+                EXPORT  CAN1_IRQHandler         [WEAK]
+                EXPORT  ATIMER_IRQHandler       [WEAK]
+                EXPORT  RTC_IRQHandler          [WEAK]
+                EXPORT  WDT_IRQHandler          [WEAK]
+                EXPORT  CAN0_IRQHandler         [WEAK]
+                EXPORT  QEI_IRQHandler          [WEAK]
+
+DAC_IRQHandler
+DMA_IRQHandler
+FLASHEEPROM_IRQHandler
+ETH_IRQHandler
+SDIO_IRQHandler
+LCD_IRQHandler
+USB0_IRQHandler
+USB1_IRQHandler
+SCT_IRQHandler
+RIT_IRQHandler
+TIMER0_IRQHandler
+TIMER1_IRQHandler
+TIMER2_IRQHandler
+TIMER3_IRQHandler
+MCPWM_IRQHandler
+ADC0_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+ADC1_IRQHandler
+SSP0_IRQHandler
+SSP1_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+I2S0_IRQHandler
+I2S1_IRQHandler
+GPIO0_IRQHandler
+GPIO1_IRQHandler
+GPIO2_IRQHandler
+GPIO3_IRQHandler
+GPIO4_IRQHandler
+GPIO5_IRQHandler
+GPIO6_IRQHandler
+GPIO7_IRQHandler
+GINT0_IRQHandler
+GINT1_IRQHandler
+EVRT_IRQHandler
+CAN1_IRQHandler
+ATIMER_IRQHandler
+RTC_IRQHandler
+WDT_IRQHandler
+CAN0_IRQHandler
+QEI_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END

CMSIS/Pack/Example/Boards/Keil/MCB1800/RTX_Blinky/RTE/Device/LPC1857/system_LPC18xx.c

@@ -0,0 +1,901 @@
+/* -----------------------------------------------------------------------------
+ * Copyright (c) 2013 - 2015 ARM Ltd.
+ *
+ * This software is provided 'as-is', without any express or implied warranty.
+ * In no event will the authors be held liable for any damages arising from
+ * the use of this software. Permission is granted to anyone to use this
+ * software for any purpose, including commercial applications, and to alter
+ * it and redistribute it freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not
+ *    claim that you wrote the original software. If you use this software in
+ *    a product, an acknowledgment in the product documentation would be
+ *    appreciated but is not required.
+ *
+ * 2. Altered source versions must be plainly marked as such, and must not be
+ *    misrepresented as being the original software.
+ *
+ * 3. This notice may not be removed or altered from any source distribution.
+ *
+ * $Date:        26. August 2015
+ * $Revision:    V5.0.1
+ *
+ * Project:      NXP LPC18xx System initialization
+ * -------------------------------------------------------------------------- */
+
+#include "LPC18xx.h"
+
+/*----------------------------------------------------------------------------
+  This file configures the clocks as follows:
+ -----------------------------------------------------------------------------
+ Clock Unit  |  Output clock  |  Source clock  |          Note
+ -----------------------------------------------------------------------------
+   PLL0USB   |    480 MHz     |      XTAL      | External crystal @ 12 MHz
+ -----------------------------------------------------------------------------
+    PLL1     |    180 MHz     |      XTAL      | External crystal @ 12 MHz
+ -----------------------------------------------------------------------------
+    CPU      |    180 MHz     |      PLL1      | CPU Clock ==  BASE_M4_CLK
+ -----------------------------------------------------------------------------
+   IDIV A    |     60 MHz     |      PLL1      | To the USB1 peripheral
+ -----------------------------------------------------------------------------
+   IDIV B    |     25 MHz     |   ENET_TX_CLK  | ENET_TX_CLK @ 50MHz
+ -----------------------------------------------------------------------------
+   IDIV C    |     12 MHz     |      IRC       | Internal oscillator @ 12 MHz
+ -----------------------------------------------------------------------------
+   IDIV D    |     12 MHz     |      IRC       | Internal oscillator @ 12 MHz
+ -----------------------------------------------------------------------------
+   IDIV E    |    5.3 MHz     |      PLL1      | To the LCD controller
+ -----------------------------------------------------------------------------*/
+
+
+/*----------------------------------------------------------------------------
+  Clock source selection definitions (do not change)
+ *----------------------------------------------------------------------------*/
+#define CLK_SRC_32KHZ       0x00
+#define CLK_SRC_IRC         0x01
+#define CLK_SRC_ENET_RX     0x02
+#define CLK_SRC_ENET_TX     0x03
+#define CLK_SRC_GP_CLKIN    0x04
+#define CLK_SRC_XTAL        0x06
+#define CLK_SRC_PLL0U       0x07
+#define CLK_SRC_PLL0A       0x08
+#define CLK_SRC_PLL1        0x09
+#define CLK_SRC_IDIVA       0x0C
+#define CLK_SRC_IDIVB       0x0D
+#define CLK_SRC_IDIVC       0x0E
+#define CLK_SRC_IDIVD       0x0F
+#define CLK_SRC_IDIVE       0x10
+
+
+/*----------------------------------------------------------------------------
+  Define external input frequency values
+ *----------------------------------------------------------------------------*/
+#define CLK_32KHZ            32768UL    /* 32 kHz oscillator frequency        */
+#define CLK_IRC           12000000UL    /* Internal oscillator frequency      */
+#define CLK_ENET_RX       50000000UL    /* Ethernet Rx frequency              */
+#define CLK_ENET_TX       50000000UL    /* Ethernet Tx frequency              */
+#define CLK_GP_CLKIN      12000000UL    /* General purpose clock input freq.  */
+#define CLK_XTAL          12000000UL    /* Crystal oscilator frequency        */
+
+
+/*----------------------------------------------------------------------------
+  Define clock sources
+ *----------------------------------------------------------------------------*/
+#define PLL1_CLK_SEL      CLK_SRC_XTAL    /* PLL1 input clock: XTAL           */
+#define PLL0USB_CLK_SEL   CLK_SRC_XTAL    /* PLL0USB input clock: XTAL        */
+#define IDIVA_CLK_SEL     CLK_SRC_PLL1    /* IDIVA input clock: PLL1          */
+#define IDIVB_CLK_SEL     CLK_SRC_ENET_TX /* IDIVB input clock: ENET TX       */
+#define IDIVC_CLK_SEL     CLK_SRC_IRC     /* IDIVC input clock: IRC           */
+#define IDIVD_CLK_SEL     CLK_SRC_IRC     /* IDIVD input clock: IRC           */
+#define IDIVE_CLK_SEL     CLK_SRC_PLL1    /* IDIVD input clock: PLL1          */
+
+
+/*----------------------------------------------------------------------------
+  Configure integer divider values
+ *----------------------------------------------------------------------------*/
+#define IDIVA_IDIV        2             /* Divide input clock by 3            */
+#define IDIVB_IDIV        1             /* Divide input clock by 2            */
+#define IDIVC_IDIV        0             /* Divide input clock by 1            */
+#define IDIVD_IDIV        0             /* Divide input clock by 1            */
+#define IDIVE_IDIV       33             /* Divide input clock by 34           */
+
+
+/*----------------------------------------------------------------------------
+  Define CPU clock input
+ *----------------------------------------------------------------------------*/
+#define CPU_CLK_SEL       CLK_SRC_PLL1  /* Default CPU clock source is PLL1   */
+
+
+/*----------------------------------------------------------------------------
+  Configure external memory controller options
+ *----------------------------------------------------------------------------*/
+#define USE_EXT_STAT_MEM_CS0 1          /* Use ext. static  memory with CS0   */
+#define USE_EXT_DYN_MEM_CS0  1          /* Use ext. dynamic memory with CS0   */
+
+
+/*----------------------------------------------------------------------------
+ * Configure PLL1
+ *----------------------------------------------------------------------------
+ * Integer mode:
+ *    - PLL1_DIRECT = 0 (Post divider enabled)
+ *    - PLL1_FBSEL  = 1 (Feedback divider runs from PLL output)
+ *    - Output frequency:
+ *                        FCLKOUT = (FCLKIN / N) * M
+ *                        FCCO    = FCLKOUT * 2 * P
+ *
+ * Non-integer:
+ *    - PLL1_DIRECT = 0 (Post divider enabled)
+ *    - PLL1_FBSEL  = 0 (Feedback divider runs from CCO clock)
+ *    - Output frequency:
+ *                        FCLKOUT = (FCLKIN / N) * M / (2 * P)
+ *                        FCCO    = FCLKOUT * 2 * P
+ *
+ * Direct mode:
+ *    - PLL1_DIRECT = 1         (Post divider disabled)
+ *    - PLL1_FBSEL  = dont care (Feedback divider runs from CCO clock)
+ *    - Output frequency:
+ *                        FCLKOUT = (FCLKIN / N) * M
+ *                        FCCO    = FCLKOUT
+ *
+ *----------------------------------------------------------------------------
+ * PLL1 requirements:
+ * | Frequency |  Minimum  |  Maximum  |               Note                   |
+ * |  FCLKIN   |    1MHz   |   25MHz   |   Clock source is external crystal   |
+ * |  FCLKIN   |    1MHz   |   50MHz   |                                      |
+ * |   FCCO    |  156MHz   |  320MHz   |                                      |
+ * |  FCLKOUT  | 9.75MHz   |  320MHz   |                                      |
+ *----------------------------------------------------------------------------
+ * Configuration examples:
+ * | Fclkout |  Fcco  |  N  |  M  |  P  | DIRECT | FBSEL | BYPASS |
+ * |  36MHz | 288MHz |  1  |  24 |  4  |   0    |   0   |    0   |
+ * |  72MHz | 288MHz |  1  |  24 |  2  |   0    |   0   |    0   |
+ * | 100MHz | 200MHz |  3  |  50 |  1  |   0    |   0   |    0   |
+ * | 120MHz | 240MHz |  1  |  20 |  1  |   0    |   0   |    0   |
+ * | 160MHz | 160MHz |  3  |  40 |  x  |   1    |   0   |    0   |
+ * | 180MHz | 180MHz |  1  |  15 |  x  |   1    |   0   |    0   |
+ *----------------------------------------------------------------------------
+ * Relations beetwen PLL dividers and definitions:
+ * N = PLL1_NSEL + 1,     M = PLL1_MSEL + 1,     P = 2 ^ PLL1_PSEL
+ *----------------------------------------------------------------------------*/
+
+/* PLL1 output clock: 180MHz, Fcco: 180MHz, N = 1, M = 15, P = x              */
+#define PLL1_NSEL   0           /* Range [0 -   3]: Pre-divider ratio N       */
+#define PLL1_MSEL  14           /* Range [0 - 255]: Feedback-divider ratio M  */
+#define PLL1_PSEL   0           /* Range [0 -   3]: Post-divider ratio P      */
+
+#define PLL1_BYPASS 0           /* 0: Use PLL, 1: PLL is bypassed             */
+#define PLL1_DIRECT 1           /* 0: Use PSEL, 1: Don't use PSEL             */
+#define PLL1_FBSEL  0           /* 0: FCCO is used as PLL feedback            */
+                                /* 1: FCLKOUT is used as PLL feedback         */
+
+
+/*----------------------------------------------------------------------------
+ * Configure PLL0USB
+ *----------------------------------------------------------------------------
+ *
+ *   Normal operating mode without post-divider and without pre-divider
+ *    - PLL0USB_DIRECTI = 1
+ *    - PLL0USB_DIRECTO = 1
+ *    - PLL0USB_BYPASS  = 0
+ *    - Output frequency:
+ *                        FOUT = FIN * 2 * M
+ *                        FCCO = FOUT
+ *
+ *   Normal operating mode with post-divider and without pre-divider
+ *    - PLL0USB_DIRECTI = 1
+ *    - PLL0USB_DIRECTO = 0
+ *    - PLL0USB_BYPASS  = 0
+ *    - Output frequency:
+ *                        FOUT = FIN * (M / P)
+ *                        FCCO = FOUT * 2 * P
+ *
+ *   Normal operating mode without post-divider and with pre-divider
+ *    - PLL0USB_DIRECTI = 0
+ *    - PLL0USB_DIRECTO = 1
+ *    - PLL0USB_BYPASS  = 0
+ *    - Output frequency:
+ *                        FOUT = FIN * 2 * M / N
+ *                        FCCO = FOUT
+ *
+ *   Normal operating mode with post-divider and with pre-divider
+ *    - PLL0USB_DIRECTI = 0
+ *    - PLL0USB_DIRECTO = 0
+ *    - PLL0USB_BYPASS  = 0
+ *    - Output frequency:
+ *                        FOUT = FIN * M / (P * N)
+ *                        FCCO = FOUT * 2 * P
+ *----------------------------------------------------------------------------
+ * PLL0 requirements:
+ * | Frequency |  Minimum  |  Maximum  |               Note                   |
+ * |  FCLKIN   |   14kHz   |   25MHz   |   Clock source is external crystal   |
+ * |  FCLKIN   |   14kHz   |  150MHz   |                                      |
+ * |   FCCO    |  275MHz   |  550MHz   |                                      |
+ * |  FCLKOUT  |  4.3MHz   |  550MHz   |                                      |
+ *----------------------------------------------------------------------------
+ * Configuration examples:
+ * | Fclkout |  Fcco  |  N  |  M  |  P  | DIRECTI | DIRECTO | BYPASS |
+ * | 120MHz | 480MHz |  x  |  20 |  2  |    1    |    0    |    0   |
+ * | 480MHz | 480MHz |  1  |  20 |  1  |    1    |    1    |    0   |
+ *----------------------------------------------------------------------------*/
+
+/* PLL0USB output clock: 480MHz, Fcco: 480MHz, N = 1, M = 20, P = 1           */
+#define PLL0USB_N       1       /* Range [1 -  256]: Pre-divider              */
+#define PLL0USB_M      20       /* Range [1 - 2^15]: Feedback-divider         */
+#define PLL0USB_P       1       /* Range [1 -   32]: Post-divider             */
+
+#define PLL0USB_DIRECTI 1       /* 0: Use N_DIV, 1: Don't use N_DIV           */
+#define PLL0USB_DIRECTO 1       /* 0: Use P_DIV, 1: Don't use P_DIV           */
+#define PLL0USB_BYPASS  0       /* 0: Use PLL, 1: PLL is bypassed             */
+
+
+/*----------------------------------------------------------------------------
+  End of configuration
+ *----------------------------------------------------------------------------*/
+
+/* PLL0 Setting Check */
+#if (PLL0USB_BYPASS == 0)
+ #if (PLL0USB_CLK_SEL == CLK_SRC_XTAL)
+  #define PLL0USB_CLKIN CLK_XTAL
+ #else
+  #define PLL0USB_CLKIN CLK_IRC
+ #endif
+
+ #if   ((PLL0USB_DIRECTI == 1) && (PLL0USB_DIRECTO == 1)) /* Mode 1a          */
+  #define PLL0USB_FOUT (PLL0USB_CLKIN * 2 * PLL0USB_M)
+  #define PLL0USB_FCCO (PLL0USB_FOUT)
+ #elif ((PLL0USB_DIRECTI == 1) && (PLL0USB_DIRECTO == 0)) /* Mode 1b          */
+  #define PLL0USB_FOUT (PLL0USB_CLKIN * PLL0USB_M / PLL0USB_P)
+  #define PLL0USB_FCCO (PLL0USB_FOUT * 2 * PLL0USB_P)
+ #elif ((PLL0USB_DIRECTI == 0) && (PLL0USB_DIRECTO == 1)) /* Mode 1c          */
+  #define PLL0USB_FOUT (PLL0USB_CLKIN * 2 * PLL0USB_M / PLL0USB_N)
+  #define PLL0USB_FCCO (PLL0USB_FOUT)
+ #else                                                    /* Mode 1d          */
+  #define PLL0USB_FOUT (PLL0USB_CLKIN * PLL0USB_M / (PLL0USB_P * PLL0USB_N))
+  #define PLL0USB_FCCO (PLL0USB_FOUT * 2 * PLL0USB_P)
+ #endif
+
+ #if (PLL0USB_FCCO < 275000000UL || PLL0USB_FCCO > 550000000UL)
+  #error "PLL0USB Fcco frequency out of range! (275MHz >= Fcco <= 550MHz)"
+ #endif
+ #if (PLL0USB_FOUT < 4300000UL || PLL0USB_FOUT > 550000000UL)
+  #error "PLL0USB output frequency out of range! (4.3MHz >= Fclkout <= 550MHz)"
+ #endif
+#endif
+
+/* PLL1 Setting Check */
+#if (PLL1_BYPASS == 0)
+ #if (PLL1_CLK_SEL == CLK_SRC_XTAL)
+  #define PLL1_CLKIN CLK_XTAL
+ #else
+  #define PLL1_CLKIN CLK_IRC
+ #endif
+
+ #if   (PLL1_DIRECT == 1)               /* Direct Mode                        */
+  #define PLL1_FCCO ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
+  #define PLL1_FOUT ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
+ #elif (PLL1_FBSEL  == 1)               /* Integer Mode                       */
+  #define PLL1_FCCO ((2 * (1 << PLL1_PSEL)) * (PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
+  #define PLL1_FOUT ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
+ #else                                  /* Noninteger Mode                    */
+  #define PLL1_FCCO ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
+  #define PLL1_FOUT (PLL1_FCCO / (2 * (1 << PLL1_PSEL)))
+ #endif
+ #if (PLL1_FCCO < 156000000UL || PLL1_FCCO > 320000000UL)
+  #error "PLL1 Fcco frequency out of range! (156MHz >= Fcco <= 320MHz)"
+ #endif
+ #if (PLL1_FOUT < 9750000UL || PLL1_FOUT > 204000000UL)
+  #error "PLL1 output frequency out of range! (9.75MHz >= Fclkout <= 204MHz)"
+ #endif
+#endif
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = CLK_IRC;    /* System Clock Frequency (Core Clock) */
+
+
+/******************************************************************************
+ * SetClock
+ ******************************************************************************/
+void SetClock (void) {
+  uint32_t x, i;
+  uint32_t selp, seli;
+
+  /* Set flash wait states to maximum                                         */
+  LPC_EMC->STATICWAITRD0  = 0x1F;
+
+  /* Switch BASE_M3_CLOCK to IRC                                              */
+  LPC_CGU->BASE_M3_CLK = (0x01        << 11) |  /* Autoblock En               */
+                         (CLK_SRC_IRC << 24) ;  /* Set clock source           */
+
+  /* Configure input to crystal oscilator                                     */
+  LPC_CGU->XTAL_OSC_CTRL = (0 << 0) |   /* Enable oscillator-pad              */
+                           (0 << 1) |   /* Operation with crystal connected   */
+                           (0 << 2) ;   /* Low-frequency mode                 */
+
+  /* Wait ~250us @ 12MHz */
+  for (i = 1500; i; i--);
+
+#if (USE_SPIFI)
+/* configure SPIFI clk to IRC via IDIVA (later IDIVA is configured to PLL1/3) */
+  LPC_CGU->IDIVA_CTRL     = (0              <<  0) |  /* Disable Power-down   */
+                            (0              <<  2) |  /* IDIV                 */
+                            (1              << 11) |  /* Autoblock En         */
+                            (CLK_SRC_IRC    << 24) ;  /* Clock source         */
+
+  LPC_CGU->BASE_SPIFI_CLK = (0              <<  0) |  /* Disable Power-down   */
+                            (0              <<  2) |  /* IDIV                 */
+                            (1              << 11) |  /* Autoblock En         */
+                            (CLK_SRC_IDIVA  << 24) ;  /* Clock source         */
+#endif
+
+/*----------------------------------------------------------------------------
+  PLL1 Setup
+ *----------------------------------------------------------------------------*/
+  /* Power down PLL                                                           */
+  LPC_CGU->PLL1_CTRL |= 1;
+
+#if ((PLL1_FOUT > 110000000UL) && (CPU_CLK_SEL == CLK_SRC_PLL1))
+  /* To run at full speed, CPU must first run at an intermediate speed        */
+  LPC_CGU->PLL1_CTRL = (0            << 0) | /* PLL1 Enabled                  */
+                       (PLL1_BYPASS  << 1) | /* CCO out sent to post-dividers */
+                       (PLL1_FBSEL   << 6) | /* PLL output used as feedback   */
+                       (0            << 7) | /* Direct on/off                 */
+                       (PLL1_PSEL    << 8) | /* PSEL                          */
+                       (0            << 11)| /* Autoblock Disabled            */
+                       (PLL1_NSEL    << 12)| /* NSEL                          */
+                       (PLL1_MSEL    << 16)| /* MSEL                          */
+                       (PLL1_CLK_SEL << 24); /* Clock source                  */
+  /* Wait for lock                                                            */
+  while (!(LPC_CGU->PLL1_STAT & 1));
+
+  /* CPU base clock is in the mid frequency range before final clock set      */
+  LPC_CGU->BASE_M3_CLK     = (0x01 << 11) |  /* Autoblock En                  */
+                             (0x09 << 24) ;  /* Clock source: PLL1            */
+
+  /* Max. BASE_M3_CLK frequency here is 102MHz, wait at least 20us */
+  for (i = 1050; i; i--);                    /* Wait minimum 2100 cycles      */
+#endif
+  /* Configure PLL1                                                           */
+  LPC_CGU->PLL1_CTRL = (0            << 0) | /* PLL1 Enabled                  */
+                       (PLL1_BYPASS  << 1) | /* CCO out sent to post-dividers */
+                       (PLL1_FBSEL   << 6) | /* PLL output used as feedback   */
+                       (PLL1_DIRECT  << 7) | /* Direct on/off                 */
+                       (PLL1_PSEL    << 8) | /* PSEL                          */
+                       (1            << 11)| /* Autoblock En                  */
+                       (PLL1_NSEL    << 12)| /* NSEL                          */
+                       (PLL1_MSEL    << 16)| /* MSEL                          */
+                       (PLL1_CLK_SEL << 24); /* Clock source                  */
+
+  /* Wait for lock                                                            */
+  while (!(LPC_CGU->PLL1_STAT & 1));
+
+  /* Set CPU base clock source                                                */
+  LPC_CGU->BASE_M3_CLK = (0x01        << 11) |  /* Autoblock En               */
+                         (CPU_CLK_SEL << 24) ;  /* Set clock source           */
+
+/*----------------------------------------------------------------------------
+  PLL0USB Setup
+ *----------------------------------------------------------------------------*/
+
+  /* Power down PLL0USB                                                       */
+  LPC_CGU->PLL0USB_CTRL  |= 1;
+
+  /* M divider                                                                */
+  x = 0x00004000;
+  switch (PLL0USB_M) {
+    case 0:  x = 0xFFFFFFFF;
+      break;
+    case 1:  x = 0x00018003;
+      break;
+    case 2:  x = 0x00010003;
+      break;
+    default:
+      for (i = PLL0USB_M; i <= 0x8000; i++) {
+        x = (((x ^ (x >> 1)) & 1) << 14) | ((x >> 1) & 0x3FFF);
+      }
+  }
+
+  if (PLL0USB_M < 60) selp = (PLL0USB_M >> 1) + 1;
+  else        selp = 31;
+
+  if      (PLL0USB_M > 16384) seli = 1;
+  else if (PLL0USB_M >  8192) seli = 2;
+  else if (PLL0USB_M >  2048) seli = 4;
+  else if (PLL0USB_M >=  501) seli = 8;
+  else if (PLL0USB_M >=   60) seli = 4 * (1024 / (PLL0USB_M + 9));
+  else                        seli = (PLL0USB_M & 0x3C) + 4;
+  LPC_CGU->PLL0USB_MDIV   =  (selp   << 17) |
+                             (seli   << 22) |
+                             (x      <<  0);
+
+  /* N divider                                                                */
+  x = 0x80;
+  switch (PLL0USB_N) {
+    case 0:  x = 0xFFFFFFFF;
+      break;
+    case 1:  x = 0x00000302;
+      break;
+    case 2:  x = 0x00000202;
+      break;
+    default:
+      for (i = PLL0USB_N; i <= 0x0100; i++) {
+        x =(((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F);
+      }
+  }
+  LPC_CGU->PLL0USB_NP_DIV = (x << 12);
+
+  /* P divider                                                                */
+  x = 0x10;
+  switch (PLL0USB_P) {
+    case 0:  x = 0xFFFFFFFF;
+      break;
+    case 1:  x = 0x00000062;
+      break;
+    case 2:  x = 0x00000042;
+      break;
+    default:
+      for (i = PLL0USB_P; i <= 0x200; i++) {
+        x = (((x ^ (x >> 2)) & 1) << 4) | ((x >> 1) &0x0F);
+      }
+  }
+  LPC_CGU->PLL0USB_NP_DIV |= x;
+
+  LPC_CGU->PLL0USB_CTRL  = (PLL0USB_CLK_SEL   << 24) | /* Clock source sel    */
+                           (1                 << 11) | /* Autoblock En        */
+                           (1                 << 4 ) | /* PLL0USB clock en    */
+                           (PLL0USB_DIRECTO   << 3 ) | /* Direct output       */
+                           (PLL0USB_DIRECTI   << 2 ) | /* Direct input        */
+                           (PLL0USB_BYPASS    << 1 ) | /* PLL bypass          */
+                           (0                 << 0 ) ; /* PLL0USB Enabled     */
+  while (!(LPC_CGU->PLL0USB_STAT & 1));
+
+
+/*----------------------------------------------------------------------------
+  Integer divider Setup
+ *----------------------------------------------------------------------------*/
+
+  /* Configure integer dividers                                               */
+  LPC_CGU->IDIVA_CTRL = (0              <<  0) |  /* Disable Power-down       */
+                        (IDIVA_IDIV     <<  2) |  /* IDIV                     */
+                        (1              << 11) |  /* Autoblock En             */
+                        (IDIVA_CLK_SEL  << 24) ;  /* Clock source             */
+
+  LPC_CGU->IDIVB_CTRL = (0              <<  0) |  /* Disable Power-down       */
+                        (IDIVB_IDIV     <<  2) |  /* IDIV                     */
+                        (1              << 11) |  /* Autoblock En             */
+                        (IDIVB_CLK_SEL  << 24) ;  /* Clock source             */
+
+  LPC_CGU->IDIVC_CTRL = (0              <<  0) |  /* Disable Power-down       */
+                        (IDIVC_IDIV     <<  2) |  /* IDIV                     */
+                        (1              << 11) |  /* Autoblock En             */
+                        (IDIVC_CLK_SEL  << 24) ;  /* Clock source             */
+
+  LPC_CGU->IDIVD_CTRL = (0              <<  0) |  /* Disable Power-down       */
+                        (IDIVD_IDIV     <<  2) |  /* IDIV                     */
+                        (1              << 11) |  /* Autoblock En             */
+                        (IDIVD_CLK_SEL  << 24) ;  /* Clock source             */
+
+  LPC_CGU->IDIVE_CTRL = (0              <<  0) |  /* Disable Power-down       */
+                        (IDIVE_IDIV     <<  2) |  /* IDIV                     */
+                        (1              << 11) |  /* Autoblock En             */
+                        (IDIVE_CLK_SEL  << 24) ;  /* Clock source             */
+}
+
+
+/*----------------------------------------------------------------------------
+  Approximate delay function (must be used after SystemCoreClockUpdate() call)
+ *----------------------------------------------------------------------------*/
+#define CPU_NANOSEC(x) (((uint64_t)(x) * SystemCoreClock)/1000000000)
+
+static void WaitUs (uint32_t us) {
+  uint32_t cyc = us * CPU_NANOSEC(1000)/4;
+  while(cyc--);
+}
+
+
+/*----------------------------------------------------------------------------
+  External Memory Controller Definitions
+ *----------------------------------------------------------------------------*/
+#define SDRAM_ADDR_BASE 0x28000000      /* SDRAM base address                 */
+/* Write Mode register macro                                                  */
+#define WR_MODE(x) (*((volatile uint32_t *)(SDRAM_ADDR_BASE | (x))))
+
+/* Pin Settings: Glith filter DIS, Input buffer EN, Fast Slew Rate, No Pullup */
+#define EMC_PIN_SET ((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4))
+#define EMC_NANOSEC(ns, freq, div) (((uint64_t)(ns) * ((freq)/((div)+1)))/1000000000)
+
+#define EMC_CLK_DLY_TIM_2  (0x7777)     /* 3.5 ns delay for the EMC clock out */
+#define EMC_CLK_DLY_TIM_0  (0x0000)     /* No delay for the EMC clock out     */
+
+typedef void (*emcdivby2) (volatile uint32_t *creg6, volatile uint32_t *emcdiv, uint32_t cfg);
+
+const uint16_t emcdivby2_opc[] =  {
+  0x6803,        /*      LDR  R3,[R0,#0]      ; Load CREG6          */
+  0xF443,0x3380, /*      ORR  R3,R3,#0x10000  ; Set Divided by 2    */
+  0x6003,        /*      STR  R3,[R0,#0]      ; Store CREG6         */
+  0x600A,        /*      STR  R2,[R1,#0]      ; EMCDIV_CFG = cfg    */
+  0x684B,        /* loop LDR  R3,[R1,#4]      ; Load EMCDIV_STAT    */
+  0x07DB,        /*      LSLS R3,R3,#31       ; Check EMCDIV_STAT.0 */
+  0xD0FC,        /*      BEQ  loop            ; Jump if 0           */
+  0x4770,        /*      BX   LR              ; Exit                */
+  0,
+};
+
+#define        emcdivby2_szw ((sizeof(emcdivby2_opc)+3)/4)
+#define        emcdivby2_ram 0x10000000
+
+/*----------------------------------------------------------------------------
+  Initialize external memory controller
+ *----------------------------------------------------------------------------*/
+
+void SystemInit_ExtMemCtl (void) {
+  uint32_t emcdivby2_buf[emcdivby2_szw];
+  uint32_t div, n;
+
+  /* Select and enable EMC branch clock */
+  LPC_CCU1->CLK_M3_EMC_CFG = (1 << 2) | (1 << 1) | 1;
+  while (!(LPC_CCU1->CLK_M3_EMC_STAT & 1));
+
+  /* Set EMC clock output delay */
+  if (SystemCoreClock < 80000000UL) {
+    LPC_SCU->EMCDELAYCLK = EMC_CLK_DLY_TIM_0; /* No EMC clock out delay       */
+  }
+  else {
+    LPC_SCU->EMCDELAYCLK = EMC_CLK_DLY_TIM_2; /* 2.0 ns EMC clock out delay   */
+  }
+
+  /* Configure EMC port pins */
+  LPC_SCU->SFSP1_0  = EMC_PIN_SET | 2;  /* P1_0:  A5                          */
+  LPC_SCU->SFSP1_1  = EMC_PIN_SET | 2;  /* P1_1:  A6                          */
+  LPC_SCU->SFSP1_2  = EMC_PIN_SET | 2;  /* P1_2:  A7                          */
+  LPC_SCU->SFSP1_3  = EMC_PIN_SET | 3;  /* P1_3:  OE                          */
+  LPC_SCU->SFSP1_4  = EMC_PIN_SET | 3;  /* P1_4:  BLS0                        */
+  LPC_SCU->SFSP1_5  = EMC_PIN_SET | 3;  /* P1_5:  CS0                         */
+  LPC_SCU->SFSP1_6  = EMC_PIN_SET | 3;  /* P1_6:  WE                          */
+  LPC_SCU->SFSP1_7  = EMC_PIN_SET | 3;  /* P1_7:  D0                          */
+  LPC_SCU->SFSP1_8  = EMC_PIN_SET | 3;  /* P1_8:  D1                          */
+  LPC_SCU->SFSP1_9  = EMC_PIN_SET | 3;  /* P1_9:  D2                          */
+  LPC_SCU->SFSP1_10 = EMC_PIN_SET | 3;  /* P1_10: D3                          */
+  LPC_SCU->SFSP1_11 = EMC_PIN_SET | 3;  /* P1_11: D4                          */
+  LPC_SCU->SFSP1_12 = EMC_PIN_SET | 3;  /* P1_12: D5                          */
+  LPC_SCU->SFSP1_13 = EMC_PIN_SET | 3;  /* P1_13: D6                          */
+  LPC_SCU->SFSP1_14 = EMC_PIN_SET | 3;  /* P1_14: D7                          */
+
+  LPC_SCU->SFSP2_0  = EMC_PIN_SET | 2;  /* P2_0:  A13                         */
+  LPC_SCU->SFSP2_1  = EMC_PIN_SET | 2;  /* P2_1:  A12                         */
+  LPC_SCU->SFSP2_2  = EMC_PIN_SET | 2;  /* P2_2:  A11                         */
+  LPC_SCU->SFSP2_6  = EMC_PIN_SET | 2;  /* P2_6:  A10                         */
+  LPC_SCU->SFSP2_7  = EMC_PIN_SET | 3;  /* P2_7:  A9                          */
+  LPC_SCU->SFSP2_8  = EMC_PIN_SET | 3;  /* P2_8:  A8                          */
+  LPC_SCU->SFSP2_9  = EMC_PIN_SET | 3;  /* P2_9:  A0                          */
+  LPC_SCU->SFSP2_10 = EMC_PIN_SET | 3;  /* P2_10: A1                          */
+  LPC_SCU->SFSP2_11 = EMC_PIN_SET | 3;  /* P2_11: A2                          */
+  LPC_SCU->SFSP2_12 = EMC_PIN_SET | 3;  /* P2_12: A3                          */
+  LPC_SCU->SFSP2_13 = EMC_PIN_SET | 3;  /* P2_13: A4                          */
+
+  LPC_SCU->SFSP5_0  = EMC_PIN_SET | 2;  /* P5_0:  D12                         */
+  LPC_SCU->SFSP5_1  = EMC_PIN_SET | 2;  /* P5_1:  D13                         */
+  LPC_SCU->SFSP5_2  = EMC_PIN_SET | 2;  /* P5_2:  D14                         */
+  LPC_SCU->SFSP5_3  = EMC_PIN_SET | 2;  /* P5_3:  D15                         */
+  LPC_SCU->SFSP5_4  = EMC_PIN_SET | 2;  /* P5_4:  D8                          */
+  LPC_SCU->SFSP5_5  = EMC_PIN_SET | 2;  /* P5_5:  D9                          */
+  LPC_SCU->SFSP5_6  = EMC_PIN_SET | 2;  /* P5_6:  D10                         */
+  LPC_SCU->SFSP5_7  = EMC_PIN_SET | 2;  /* P5_7:  D11                         */
+
+  LPC_SCU->SFSP6_1  = EMC_PIN_SET | 1;  /* P6_1:  DYCS1                       */
+  LPC_SCU->SFSP6_2  = EMC_PIN_SET | 1;  /* P6_3:  CKEOUT1                     */
+  LPC_SCU->SFSP6_3  = EMC_PIN_SET | 3;  /* P6_3:  CS1                         */
+  LPC_SCU->SFSP6_4  = EMC_PIN_SET | 3;  /* P6_4:  CAS                         */
+  LPC_SCU->SFSP6_5  = EMC_PIN_SET | 3;  /* P6_5:  RAS                         */
+  LPC_SCU->SFSP6_6  = EMC_PIN_SET | 1;  /* P6_6:  BLS1                        */
+  LPC_SCU->SFSP6_7  = EMC_PIN_SET | 1;  /* P6_7:  A15                         */
+  LPC_SCU->SFSP6_8  = EMC_PIN_SET | 1;  /* P6_8:  A14                         */
+  LPC_SCU->SFSP6_9  = EMC_PIN_SET | 3;  /* P6_9:  DYCS0                       */
+  LPC_SCU->SFSP6_10 = EMC_PIN_SET | 3;  /* P6_10: DQMOUT1                     */
+  LPC_SCU->SFSP6_11 = EMC_PIN_SET | 3;  /* P6_11: CKEOUT0                     */
+  LPC_SCU->SFSP6_12 = EMC_PIN_SET | 3;  /* P6_12: DQMOUT0                     */
+
+  LPC_SCU->SFSPA_4  = EMC_PIN_SET | 3;  /* PA_4:  A23                         */
+
+  LPC_SCU->SFSPD_0  = EMC_PIN_SET | 2;  /* PD_0:  DQMOUT2                     */
+  LPC_SCU->SFSPD_1  = EMC_PIN_SET | 2;  /* PD_1:  CKEOUT2                     */
+  LPC_SCU->SFSPD_2  = EMC_PIN_SET | 2;  /* PD_2:  D16                         */
+  LPC_SCU->SFSPD_3  = EMC_PIN_SET | 2;  /* PD_3:  D17                         */
+  LPC_SCU->SFSPD_4  = EMC_PIN_SET | 2;  /* PD_4:  D18                         */
+  LPC_SCU->SFSPD_5  = EMC_PIN_SET | 2;  /* PD_5:  D19                         */
+  LPC_SCU->SFSPD_6  = EMC_PIN_SET | 2;  /* PD_6:  D20                         */
+  LPC_SCU->SFSPD_7  = EMC_PIN_SET | 2;  /* PD_7:  D21                         */
+  LPC_SCU->SFSPD_8  = EMC_PIN_SET | 2;  /* PD_8:  D22                         */
+  LPC_SCU->SFSPD_9  = EMC_PIN_SET | 2;  /* PD_9:  D23                         */
+  LPC_SCU->SFSPD_10 = EMC_PIN_SET | 2;  /* PD_10: BLS3                        */
+  LPC_SCU->SFSPD_11 = EMC_PIN_SET | 2;  /* PD_11: CS3                         */
+  LPC_SCU->SFSPD_12 = EMC_PIN_SET | 2;  /* PD_12: CS2                         */
+  LPC_SCU->SFSPD_13 = EMC_PIN_SET | 2;  /* PD_13: BLS2                        */
+  LPC_SCU->SFSPD_14 = EMC_PIN_SET | 2;  /* PD_14: DYCS2                       */
+  LPC_SCU->SFSPD_15 = EMC_PIN_SET | 2;  /* PD_15: A17                         */
+  LPC_SCU->SFSPD_16 = EMC_PIN_SET | 2;  /* PD_16: A16                         */
+
+  LPC_SCU->SFSPE_0  = EMC_PIN_SET | 3;  /* PE_0:  A18                         */
+  LPC_SCU->SFSPE_1  = EMC_PIN_SET | 3;  /* PE_1:  A19                         */
+  LPC_SCU->SFSPE_2  = EMC_PIN_SET | 3;  /* PE_2:  A20                         */
+  LPC_SCU->SFSPE_3  = EMC_PIN_SET | 3;  /* PE_3:  A21                         */
+  LPC_SCU->SFSPE_4  = EMC_PIN_SET | 3;  /* PE_4:  A22                         */
+  LPC_SCU->SFSPE_5  = EMC_PIN_SET | 3;  /* PE_5:  D24                         */
+  LPC_SCU->SFSPE_6  = EMC_PIN_SET | 3;  /* PE_6:  D25                         */
+  LPC_SCU->SFSPE_7  = EMC_PIN_SET | 3;  /* PE_7:  D26                         */
+  LPC_SCU->SFSPE_8  = EMC_PIN_SET | 3;  /* PE_8:  D27                         */
+  LPC_SCU->SFSPE_9  = EMC_PIN_SET | 3;  /* PE_9:  D28                         */
+  LPC_SCU->SFSPE_10 = EMC_PIN_SET | 3;  /* PE_10: D29                         */
+  LPC_SCU->SFSPE_11 = EMC_PIN_SET | 3;  /* PE_11: D30                         */
+  LPC_SCU->SFSPE_12 = EMC_PIN_SET | 3;  /* PE_12: D31                         */
+  LPC_SCU->SFSPE_13 = EMC_PIN_SET | 3;  /* PE_13: DQMOUT3                     */
+  LPC_SCU->SFSPE_14 = EMC_PIN_SET | 3;  /* PE_14: DYCS3                       */
+  LPC_SCU->SFSPE_15 = EMC_PIN_SET | 3;  /* PE_15: CKEOUT3                     */
+
+  LPC_EMC->CONTROL  = 0x00000001;       /* EMC Enable                         */
+  LPC_EMC->CONFIG   = 0x00000000;       /* Little-endian, Clock Ratio 1:1     */
+
+  div = 0;
+  if (SystemCoreClock > 120000000UL) {
+    /* Use EMC clock divider and EMC clock output delay */
+    div = 1;
+    /* Following code must be executed in RAM to ensure stable operation      */
+    /* LPC_CCU1->CLK_M3_EMCDIV_CFG = (1 << 5) | (1 << 2) | (1 << 1) | 1;      */
+    /* LPC_CREG->CREG6 |= (1 << 16);       // EMC_CLK_DIV divided by 2        */
+    /* while (!(LPC_CCU1->CLK_M3_EMCDIV_STAT & 1));                           */
+
+    /* This code configures EMC clock divider and is executed in RAM          */
+    for (n = 0; n < emcdivby2_szw; n++) {
+      emcdivby2_buf[n] =  *((uint32_t *)emcdivby2_ram + n);
+      *((uint32_t *)emcdivby2_ram + n) = *((uint32_t *)emcdivby2_opc + n);
+    }
+    __ISB();
+    ((emcdivby2 )(emcdivby2_ram+1))(&LPC_CREG->CREG6, &LPC_CCU1->CLK_M3_EMCDIV_CFG, (1 << 5) | (1 << 2) | (1 << 1) | 1);
+    for (n = 0; n < emcdivby2_szw; n++) {
+      *((uint32_t *)emcdivby2_ram + n) = emcdivby2_buf[n];
+    }
+  }
+
+  /* Configure EMC clock-out pins                                             */
+  LPC_SCU->SFSCLK_0 = EMC_PIN_SET | 0;  /* CLK0                               */
+  LPC_SCU->SFSCLK_1 = EMC_PIN_SET | 0;  /* CLK1                               */
+  LPC_SCU->SFSCLK_2 = EMC_PIN_SET | 0;  /* CLK2                               */
+  LPC_SCU->SFSCLK_3 = EMC_PIN_SET | 0;  /* CLK3                               */
+
+  /* Static memory configuration (chip select 0)                              */
+#if (USE_EXT_STAT_MEM_CS0)
+  LPC_EMC->STATICCONFIG0  = (1 <<  7) | /* Byte lane state: use WE signal     */
+                            (2 <<  0) | /* Memory width 32-bit                */
+                            (1 <<  3);  /* Async page mode enable             */
+
+  LPC_EMC->STATICWAITOEN0 = (0 <<  0) ; /* Wait output enable: No delay       */
+
+  LPC_EMC->STATICWAITPAG0 = 2;
+
+  /* Set Static Memory Read Delay for 90ns External NOR Flash                 */
+  LPC_EMC->STATICWAITRD0  = 1 + EMC_NANOSEC(90, SystemCoreClock, div);
+  LPC_EMC->STATICCONFIG0 |= (1 << 19) ; /* Enable buffer                      */
+#endif
+
+  /* Dynamic memory configuration (chip select 0)                             */
+#if (USE_EXT_DYN_MEM_CS0)
+
+  /* Set Address mapping: 128Mb(4Mx32), 4 banks, row len = 12, column len = 8 */
+  LPC_EMC->DYNAMICCONFIG0    = (1 << 14) |  /* AM[14]   = 1                   */
+                               (0 << 12) |  /* AM[12]   = 0                   */
+                               (2 <<  9) |  /* AM[11:9] = 2                   */
+                               (2 <<  7) ;  /* AM[8:7]  = 2                   */
+
+  LPC_EMC->DYNAMICRASCAS0    = 0x00000303;  /* Latency: RAS 3, CAS 3 CCLK cyc.*/
+  LPC_EMC->DYNAMICREADCONFIG = 0x00000001;  /* Command delayed by 1/2 CCLK    */
+
+  LPC_EMC->DYNAMICRP         = EMC_NANOSEC (20, SystemCoreClock, div);
+  LPC_EMC->DYNAMICRAS        = EMC_NANOSEC (42, SystemCoreClock, div);
+  LPC_EMC->DYNAMICSREX       = EMC_NANOSEC (63, SystemCoreClock, div);
+  LPC_EMC->DYNAMICAPR        = EMC_NANOSEC (70, SystemCoreClock, div);
+  LPC_EMC->DYNAMICDAL        = EMC_NANOSEC (70, SystemCoreClock, div);
+  LPC_EMC->DYNAMICWR         = EMC_NANOSEC (30, SystemCoreClock, div);
+  LPC_EMC->DYNAMICRC         = EMC_NANOSEC (63, SystemCoreClock, div);
+  LPC_EMC->DYNAMICRFC        = EMC_NANOSEC (63, SystemCoreClock, div);
+  LPC_EMC->DYNAMICXSR        = EMC_NANOSEC (63, SystemCoreClock, div);
+  LPC_EMC->DYNAMICRRD        = EMC_NANOSEC (14, SystemCoreClock, div);
+  LPC_EMC->DYNAMICMRD        = EMC_NANOSEC (30, SystemCoreClock, div);
+
+  WaitUs (100);
+  LPC_EMC->DYNAMICCONTROL    = 0x00000183;  /* Issue NOP command              */
+  WaitUs (10);
+  LPC_EMC->DYNAMICCONTROL    = 0x00000103;  /* Issue PALL command             */
+  WaitUs (1);
+  LPC_EMC->DYNAMICCONTROL    = 0x00000183;  /* Issue NOP command              */
+  WaitUs (1);
+  LPC_EMC->DYNAMICREFRESH    = EMC_NANOSEC(  200, SystemCoreClock, div) / 16 + 1;
+  WaitUs (10);
+  LPC_EMC->DYNAMICREFRESH    = EMC_NANOSEC(15625, SystemCoreClock, div) / 16 + 1;
+  WaitUs (10);
+  LPC_EMC->DYNAMICCONTROL    = 0x00000083;  /* Issue MODE command             */
+
+  /* Mode register: Burst Length: 4, Burst Type: Sequential, CAS Latency: 3   */
+  WR_MODE(((3 << 4) | 2) << 12);
+
+  WaitUs (10);
+  LPC_EMC->DYNAMICCONTROL    = 0x00000002;  /* Issue NORMAL command           */
+  LPC_EMC->DYNAMICCONFIG0   |= (1 << 19);   /* Enable buffer                  */
+#endif
+}
+
+
+/*----------------------------------------------------------------------------
+  Measure frequency using frequency monitor
+ *----------------------------------------------------------------------------*/
+uint32_t MeasureFreq (uint32_t clk_sel) {
+  uint32_t fcnt, rcnt, fout;
+
+  /* Set register values */
+  LPC_CGU->FREQ_MON &= ~(1 << 23);                /* Stop frequency counters  */
+  LPC_CGU->FREQ_MON  = (clk_sel << 24) | 511;     /* RCNT == 511              */
+  LPC_CGU->FREQ_MON |= (1 << 23);                 /* Start RCNT and FCNT      */
+  while (LPC_CGU->FREQ_MON & (1 << 23)) {
+    fcnt = (LPC_CGU->FREQ_MON >> 9) & 0x3FFF;
+    rcnt = (LPC_CGU->FREQ_MON     ) & 0x01FF;
+    if (fcnt == 0 && rcnt == 0) {
+      return (0);                                 /* No input clock present   */
+    }
+  }
+  fcnt = (LPC_CGU->FREQ_MON >> 9) & 0x3FFF;
+  fout = fcnt * (12000000U/511U);                 /* FCNT * (IRC_CLK / RCNT)  */
+
+  return (fout);
+}
+
+
+/*----------------------------------------------------------------------------
+  Get PLL1 (divider and multiplier) parameters
+ *----------------------------------------------------------------------------*/
+static __inline uint32_t GetPLL1Param (void) {
+  uint32_t ctrl;
+  uint32_t p;
+  uint32_t div, mul;
+
+  ctrl = LPC_CGU->PLL1_CTRL;
+  div = ((ctrl >> 12) & 0x03) + 1;
+  mul = ((ctrl >> 16) & 0xFF) + 1;
+  p = 1 << ((ctrl >>  8) & 0x03);
+
+  if (ctrl & (1 << 1)) {
+    /* Bypass = 1, PLL1 input clock sent to post-dividers */
+    if (ctrl & (1 << 7)) {
+      div *= (2*p);
+    }
+  }
+  else {
+    /* Direct and integer mode */
+    if (((ctrl & (1 << 7)) == 0) && ((ctrl & (1 << 6)) == 0)) {
+      /* Non-integer mode */
+      div *= (2*p);
+    }
+  }
+  return ((div << 8) | (mul));
+}
+
+
+/*----------------------------------------------------------------------------
+  Get input clock source for specified clock generation block
+ *----------------------------------------------------------------------------*/
+int32_t GetClkSel (uint32_t clk_src) {
+  uint32_t reg;
+  int32_t clk_sel = -1;
+
+  switch (clk_src) {
+    case CLK_SRC_IRC:
+    case CLK_SRC_ENET_RX:
+    case CLK_SRC_ENET_TX:
+    case CLK_SRC_GP_CLKIN:
+      return (clk_src);
+
+    case CLK_SRC_32KHZ:
+      return ((LPC_CREG->CREG0 & 0x0A) != 0x02) ? (-1) : (CLK_SRC_32KHZ);
+    case CLK_SRC_XTAL:
+     return  (LPC_CGU->XTAL_OSC_CTRL & 1)       ? (-1) : (CLK_SRC_XTAL);
+
+    case CLK_SRC_PLL0U: reg = LPC_CGU->PLL0USB_CTRL;    break;
+    case CLK_SRC_PLL0A: reg = LPC_CGU->PLL0AUDIO_CTRL;  break;
+    case CLK_SRC_PLL1:  reg = (LPC_CGU->PLL1_STAT & 1) ? (LPC_CGU->PLL1_CTRL) : (0); break;
+
+    case CLK_SRC_IDIVA: reg = LPC_CGU->IDIVA_CTRL;      break;
+    case CLK_SRC_IDIVB: reg = LPC_CGU->IDIVB_CTRL;      break;
+    case CLK_SRC_IDIVC: reg = LPC_CGU->IDIVC_CTRL;      break;
+    case CLK_SRC_IDIVD: reg = LPC_CGU->IDIVD_CTRL;      break;
+    case CLK_SRC_IDIVE: reg = LPC_CGU->IDIVE_CTRL;      break;
+
+    default:
+      return (clk_sel);
+  }
+  if (!(reg & 1)) {
+    clk_sel = (reg >> 24) & 0x1F;
+  }
+  return (clk_sel);
+}
+
+
+/*----------------------------------------------------------------------------
+  Get clock frequency for specified clock source
+ *----------------------------------------------------------------------------*/
+uint32_t GetClockFreq (uint32_t clk_src) {
+  uint32_t tmp;
+  uint32_t mul        =  1;
+  uint32_t div        =  1;
+  uint32_t main_freq  =  0;
+  int32_t  clk_sel    = clk_src;
+
+  do {
+    switch (clk_sel) {
+      case CLK_SRC_32KHZ:    main_freq = CLK_32KHZ;     break;
+      case CLK_SRC_IRC:      main_freq = CLK_IRC;       break;
+      case CLK_SRC_ENET_RX:  main_freq = CLK_ENET_RX;   break;
+      case CLK_SRC_ENET_TX:  main_freq = CLK_ENET_TX;   break;
+      case CLK_SRC_GP_CLKIN: main_freq = CLK_GP_CLKIN;  break;
+      case CLK_SRC_XTAL:     main_freq = CLK_XTAL;      break;
+
+      case CLK_SRC_IDIVA: div *= ((LPC_CGU->IDIVA_CTRL >> 2) & 0x3) + 1; break;
+      case CLK_SRC_IDIVB: div *= ((LPC_CGU->IDIVB_CTRL >> 2) & 0x3) + 1; break;
+      case CLK_SRC_IDIVC: div *= ((LPC_CGU->IDIVC_CTRL >> 2) & 0x3) + 1; break;
+      case CLK_SRC_IDIVD: div *= ((LPC_CGU->IDIVD_CTRL >> 2) & 0x3) + 1; break;
+      case CLK_SRC_IDIVE: div *= ((LPC_CGU->IDIVE_CTRL >> 2) & 0x3) + 1; break;
+
+      case CLK_SRC_PLL0U: /* Not implemented */  break;
+      case CLK_SRC_PLL0A: /* Not implemented */  break;
+
+      case CLK_SRC_PLL1:
+        tmp = GetPLL1Param ();
+        mul *= (tmp     ) & 0xFF;       /* PLL input clock multiplier         */
+        div *= (tmp >> 8) & 0xFF;       /* PLL input clock divider            */
+        break;
+
+      default:
+        return (0);                     /* Clock not running or not supported */
+    }
+    if (main_freq == 0) {
+      clk_sel = GetClkSel (clk_sel);
+    }
+  }
+  while (main_freq == 0);
+
+  return ((main_freq * mul) / div);
+}
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock update
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void) {
+  /* Check BASE_M3_CLK connection */
+  uint32_t base_src = (LPC_CGU->BASE_M3_CLK >> 24) & 0x1F;
+
+  /* Update core clock frequency */
+  SystemCoreClock = GetClockFreq (base_src);
+}
+
+
+extern uint32_t __Vectors;                         /* see startup_LPC18xx.s   */
+
+/*----------------------------------------------------------------------------
+  Initialize the system
+ *----------------------------------------------------------------------------*/
+void SystemInit (void) {
+  /* Disable SysTick timer                                                    */
+  SysTick->CTRL &= ~(SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk);
+
+  /* Set vector table pointer */
+  SCB->VTOR = ((uint32_t)(&__Vectors)) & 0xFFF00000UL;
+
+  /* Configure PLL0 and PLL1, connect CPU clock to selected clock source */
+  SetClock();
+
+  /* Update SystemCoreClock variable */
+  SystemCoreClockUpdate();
+
+  /* Configure External Memory Controller */
+  SystemInit_ExtMemCtl ();
+}

CMSIS/Pack/Example/Boards/Keil/MCB1800/RTX_Blinky/RTE/RTE_Components.h

@@ -0,0 +1,17 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'Blinky' 
+ * Target:  'LPC1857 Flash' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+#define RTE_CMSIS_RTOS                  /* CMSIS-RTOS */
+        #define RTE_CMSIS_RTOS_RTX              /* CMSIS-RTOS Keil RTX */
+#define RTE_DEVICE_STARTUP_LPC18XX      /* Device Startup for NXP18XX */
+
+#endif /* RTE_COMPONENTS_H */

CMSIS/Pack/Example/CMSIS_Driver/CAN_LPC18xx.c

@@ -0,0 +1,1230 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        20. April 2016
+ * $Revision:    V1.4
+ *
+ * Driver:       Driver_CAN0/1
+ * Configured:   via RTE_Device.h configuration file
+ * Project:      CAN Driver for NXP LPC18xx
+ * --------------------------------------------------------------------------
+ * Use the following configuration settings in the middleware component
+ * to connect to this driver.
+ *
+ *   Configuration Setting                 Value   CAN Interface
+ *   ---------------------                 -----   -------------
+ *   Connect to hardware via Driver_CAN# = 0       use CAN0
+ *   Connect to hardware via Driver_CAN# = 1       use CAN1
+ * --------------------------------------------------------------------------
+ * Defines used for driver configuration (at compile time):
+ *
+ *   CAN_CLOCK_TOLERANCE:  defines maximum allowed clock tolerance in 1/1024 steps
+ *     - default value:    15 (approx. 1.5 %)
+ *   CAN0_OBJ_NUM:         number of message objects used by CAN0 controller
+ *                         this value can be reduced to save some RAM space
+ *     - default value:    32 (also this is maximum value)
+ *   CAN1_OBJ_NUM:         number of message objects used by CAN1 controller
+ *                         this value can be reduced to save some RAM space
+ *     - default value:    32 (also this is maximum value)
+ * -------------------------------------------------------------------------- */
+
+/* History:
+ *  Version 1.4
+ *    Corrected receive overrun clearing and signaling
+ *  Version 1.3
+ *    Corrected interrupt routine (status interrupt could case lockup)
+ *  Version 1.2
+ *    Corrected functionality when NULL pointer is provided for one or both 
+ *    signal callbacks in Initialize function call
+ *  Version 1.1
+ *    Corrected CAN1 IRQ routine
+ *    Corrected MessageSend function to return busy if transmission is in progress
+ *  Version 1.0
+ *    Initial release
+ */
+
+#include "CAN_LPC18xx.h"
+
+// Externally overridable configuration definitions
+
+// Maximum allowed clock tolerance in 1/1024 steps
+#ifndef CAN_CLOCK_TOLERANCE
+#define CAN_CLOCK_TOLERANCE             (15U)   // 15/1024 approx. 1.5 %
+#endif
+
+// Maximum number of Message Objects used for CAN0 controller
+#ifndef CAN0_OBJ_NUM
+#define CAN0_OBJ_NUM                    (32U)
+#endif
+#if    (CAN0_OBJ_NUM > 32U)
+#error  Too many Message Objects defined for CAN0, maximum number of Message Objects is 32 !!!
+#endif
+
+// Maximum number of Message Objects used for CAN1 controller
+#ifndef CAN1_OBJ_NUM
+#define CAN1_OBJ_NUM                    (32U)
+#endif
+#if    (CAN1_OBJ_NUM > 32U)
+#error  Too many Message Objects defined for CAN1, maximum number of Message Objects is 32 !!!
+#endif
+
+
+// External Functions
+extern uint32_t GetClockFreq (uint32_t clk_src);
+
+
+// CAN Driver ******************************************************************
+
+#define ARM_CAN_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,4) // CAN driver version
+
+// Driver Version
+static const ARM_DRIVER_VERSION can_driver_version = { ARM_CAN_API_VERSION, ARM_CAN_DRV_VERSION };
+
+// Driver Capabilities
+static const ARM_CAN_CAPABILITIES can_driver_capabilities[2] = {
+{                       // CAN0 driver capabilities
+  CAN0_OBJ_NUM,         // Number of CAN Objects available
+  0U,                   // Does not support reentrant calls to ARM_CAN_MessageSend, ARM_CAN_MessageRead, ARM_CAN_ObjectConfigure and abort message sending used by ARM_CAN_Control.
+  0U,                   // Does not support CAN with flexible data-rate mode (CAN_FD)
+  0U,                   // Does not support restricted operation mode
+  1U,                   // Supports bus monitoring mode
+  1U,                   // Supports internal loopback mode
+  1U,                   // Supports external loopback mode
+}, 
+{                       // CAN1 driver capabilities
+  CAN1_OBJ_NUM,         // Number of CAN Objects available
+  0U,                   // Does not support reentrant calls to ARM_CAN_MessageSend, ARM_CAN_MessageRead, ARM_CAN_ObjectConfigure and abort message sending used by ARM_CAN_Control.
+  0U,                   // Does not support CAN with flexible data-rate mode (CAN_FD)
+  0U,                   // Does not support restricted operation mode
+  1U,                   // Supports bus monitoring mode
+  1U,                   // Supports internal loopback mode
+  1U,                   // Supports external loopback mode
+}
+};
+
+// Object Capabilities
+static const ARM_CAN_OBJ_CAPABILITIES can_object_capabilities = {
+  1U,                   // Object supports transmission
+  1U,                   // Object supports reception
+  1U,                   // Object supports RTR reception and automatic Data transmission
+  1U,                   // Object supports RTR transmission and automatic Data reception
+  0U,                   // Object does not allow assignment of multiple filters to it
+  1U,                   // Object supports exact identifier filtering
+  0U,                   // Object does not support range identifier filtering
+  1U,                   // Object supports mask identifier filtering
+  1U                    // Object can buffer 1 message
+};
+
+static LPC_C_CANn_Type * const ptr_CANx[2] = { (LPC_C_CANn_Type *)LPC_C_CAN0_BASE, (LPC_C_CANn_Type *)LPC_C_CAN1_BASE };
+
+// Local variables and structures
+static uint8_t                     can_driver_powered    [CAN_CTRL_NUM];
+static uint8_t                     can_driver_initialized[CAN_CTRL_NUM];
+static uint8_t                     can_obj_cfg           [CAN_CTRL_NUM][(CAN0_OBJ_NUM > CAN1_OBJ_NUM) ? CAN0_OBJ_NUM : CAN1_OBJ_NUM];
+static uint8_t                     can_stat_last         [CAN_CTRL_NUM];
+static ARM_CAN_SignalUnitEvent_t   CAN_SignalUnitEvent   [CAN_CTRL_NUM];
+static ARM_CAN_SignalObjectEvent_t CAN_SignalObjectEvent [CAN_CTRL_NUM];
+
+
+// Helper Functions
+
+/**
+  \fn          void CANx_HW_Reset (uint8_t x)
+  \brief       Reset CAN hardware (reset message objects and clear interrupts).
+  \param[in]   x      Controller number (0..1)
+*/
+static void CANx_HW_Reset (uint8_t x) {
+  LPC_C_CANn_Type *ptr_CAN;
+  uint8_t          obj, obj_end;
+
+  ptr_CAN = ptr_CANx[x];
+
+  can_stat_last[x] = 0U;
+
+  ptr_CAN->CNTL = 1U;                                   // Initialization
+
+  obj_end = ((x) ? CAN1_OBJ_NUM : CAN0_OBJ_NUM);
+  for (obj = 0U; obj < obj_end; obj++) {
+    while ((ptr_CAN->IF1_CMDREQ & IF_CMDREQ_BUSY_Msk) != 0U);
+    ptr_CAN->IF1_CMDMSK_W = IF_CMDMSK_ARB_Msk | IF_CMDMSK_WR_RD_Msk;
+    ptr_CAN->IF1_ARB2     = 0U;                         // Invalidate message object (MSGVAL = 0)
+    ptr_CAN->IF1_CMDREQ   = obj + 1U;
+    while ((ptr_CAN->IF1_CMDREQ & IF_CMDREQ_BUSY_Msk) != 0U);
+
+    ptr_CAN->IF1_CMDMSK_R = IF_CMDMSK_CLRINTPND_Msk;    // Clear interrupt pending
+    ptr_CAN->IF1_CMDREQ   = obj + 1U;
+    while ((ptr_CAN->IF1_CMDREQ & IF_CMDREQ_BUSY_Msk) != 0U);
+
+    can_obj_cfg[x][obj]    = ARM_CAN_OBJ_INACTIVE;
+  }
+
+  ptr_CAN->STAT = 0U;                                   // Clear interrupt status
+}
+
+/**
+  \fn          void CANx_AbortSendMessage (uint32_t obj, uint8_t x)
+  \brief       Abort send message.
+  \param[in]   obj    Message object index
+  \param[in]   x      Controller number (0..1)
+*/
+static void CANx_AbortSendMessage (uint32_t obj, uint8_t x) {
+  LPC_C_CANn_Type *ptr_CAN;
+
+  ptr_CAN = ptr_CANx[x];
+
+  while ((ptr_CAN->IF1_CMDREQ & IF_CMDREQ_BUSY_Msk) != 0U);
+  ptr_CAN->IF1_CMDMSK_R =  IF_CMDMSK_CTRL_Msk;
+  ptr_CAN->IF1_CMDREQ   =  obj + 1U;
+  while ((ptr_CAN->IF1_CMDREQ & IF_CMDREQ_BUSY_Msk) != 0U);
+
+  ptr_CAN->IF1_MCTRL   &= ~IF_MCTRL_TXRQST_Msk;         // Clear TXRQST bit
+
+  ptr_CAN->IF1_CMDMSK_W =  IF_CMDMSK_CTRL_Msk |
+                           IF_CMDMSK_WR_RD_Msk;
+  ptr_CAN->IF1_CMDREQ   =  obj + 1U;
+  while ((ptr_CAN->IF1_CMDREQ & IF_CMDREQ_BUSY_Msk) != 0U);
+}
+
+
+// CAN Driver Functions
+
+/**
+  \fn          ARM_DRIVER_VERSION CAN_GetVersion (void)
+  \brief       Get driver version.
+  \return      ARM_DRIVER_VERSION
+*/
+static ARM_DRIVER_VERSION CAN_GetVersion (void) { return can_driver_version; }
+
+/**
+  \fn          ARM_CAN_CAPABILITIES CAN0_GetCapabilities (void)
+  \fn          ARM_CAN_CAPABILITIES CAN1_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      ARM_CAN_CAPABILITIES
+*/
+#if (RTE_CAN_CAN0 == 1U)
+static ARM_CAN_CAPABILITIES CAN0_GetCapabilities (void) { return can_driver_capabilities[0U]; }
+#endif
+#if (RTE_CAN_CAN1 == 1U)
+static ARM_CAN_CAPABILITIES CAN1_GetCapabilities (void) { return can_driver_capabilities[1U]; }
+#endif
+/**
+  \fn          int32_t CANx_Initialize (ARM_CAN_SignalUnitEvent_t   cb_unit_event,
+                                        ARM_CAN_SignalObjectEvent_t cb_object_event,
+                                        uint8_t                     x)
+  \brief       Initialize CAN interface and register signal (callback) functions.
+  \param[in]   cb_unit_event   Pointer to ARM_CAN_SignalUnitEvent callback function
+  \param[in]   cb_object_event Pointer to ARM_CAN_SignalObjectEvent callback function
+  \param[in]   x               Controller number (0..1)
+  \return      execution status
+*/
+static int32_t CANx_Initialize (ARM_CAN_SignalUnitEvent_t   cb_unit_event,
+                                ARM_CAN_SignalObjectEvent_t cb_object_event,
+                                uint8_t                     x) {
+
+  if (x >= CAN_CTRL_NUM)               { return ARM_DRIVER_ERROR; }
+  if (can_driver_initialized[x] != 0U) { return ARM_DRIVER_OK;    }
+
+  CAN_SignalUnitEvent  [x] = cb_unit_event;
+  CAN_SignalObjectEvent[x] = cb_object_event;
+
+  if (x == 0U) {
+#if (RTE_CAN0_RD_PIN_EN == 1)
+    SCU_PinConfigure (RTE_CAN0_RD_PORT, RTE_CAN0_RD_BIT, RTE_CAN0_RD_FUNC | SCU_PIN_CFG_PULLUP_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN);
+#endif
+#if (RTE_CAN0_TD_PIN_EN == 1)
+    SCU_PinConfigure (RTE_CAN0_TD_PORT, RTE_CAN0_TD_BIT, RTE_CAN0_TD_FUNC | SCU_PIN_CFG_PULLUP_DIS);
+#endif
+  } else {
+#if (RTE_CAN1_RD_PIN_EN == 1)
+    SCU_PinConfigure (RTE_CAN1_RD_PORT, RTE_CAN1_RD_BIT, RTE_CAN1_RD_FUNC | SCU_PIN_CFG_PULLUP_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN);
+#endif
+#if (RTE_CAN1_TD_PIN_EN == 1)
+    SCU_PinConfigure (RTE_CAN1_TD_PORT, RTE_CAN1_TD_BIT, RTE_CAN1_TD_FUNC | SCU_PIN_CFG_PULLUP_DIS);
+#endif
+  }
+
+  can_driver_initialized[x] = 1U;
+
+  return ARM_DRIVER_OK;
+}
+#if (RTE_CAN_CAN0 == 1U)
+static int32_t CAN0_Initialize (ARM_CAN_SignalUnitEvent_t cb_unit_event, ARM_CAN_SignalObjectEvent_t cb_object_event) { return CANx_Initialize (cb_unit_event, cb_object_event, 0U); }
+#endif
+#if (RTE_CAN_CAN1 == 1U)
+static int32_t CAN1_Initialize (ARM_CAN_SignalUnitEvent_t cb_unit_event, ARM_CAN_SignalObjectEvent_t cb_object_event) { return CANx_Initialize (cb_unit_event, cb_object_event, 1U); }
+#endif
+
+/**
+  \fn          int32_t CANx_Uninitialize (uint8_t x)
+  \brief       De-initialize CAN interface.
+  \param[in]   x      Controller number (0..1)
+  \return      execution status
+*/
+static int32_t CANx_Uninitialize (uint8_t x) {
+
+  if (x >= CAN_CTRL_NUM) { return ARM_DRIVER_ERROR; }
+
+  if (x == 0U) {
+#if (RTE_CAN0_RD_PIN_EN == 1)
+    SCU_PinConfigure (RTE_CAN0_RD_PORT, RTE_CAN0_RD_BIT, 0U);
+#endif
+#if (RTE_CAN0_TD_PIN_EN == 1)
+    SCU_PinConfigure (RTE_CAN0_TD_PORT, RTE_CAN0_TD_BIT, 0U);
+#endif
+  } else {
+#if (RTE_CAN1_RD_PIN_EN == 1)
+    SCU_PinConfigure (RTE_CAN1_RD_PORT, RTE_CAN1_RD_BIT, 0U);
+#endif
+#if (RTE_CAN1_TD_PIN_EN == 1)
+    SCU_PinConfigure (RTE_CAN1_TD_PORT, RTE_CAN1_TD_BIT, 0U);
+#endif
+  }
+
+  can_driver_initialized[x] = 0U;
+
+  return ARM_DRIVER_OK;
+}
+#if (RTE_CAN_CAN0 == 1U)
+static int32_t CAN0_Uninitialize (void) { return CANx_Uninitialize (0U); }
+#endif
+#if (RTE_CAN_CAN1 == 1U)
+static int32_t CAN1_Uninitialize (void) { return CANx_Uninitialize (1U); }
+#endif
+
+/**
+  \fn          int32_t CANx_PowerControl (ARM_POWER_STATE state, uint8_t x)
+  \brief       Control CAN interface power.
+  \param[in]   state  Power state
+                 - ARM_POWER_OFF :  power off: no operation possible
+                 - ARM_POWER_LOW :  low power mode: retain state, detect and signal wake-up events
+                 - ARM_POWER_FULL : power on: full operation at maximum performance
+  \param[in]   x      Controller number (0..1)
+  \return      execution status
+*/
+static int32_t CANx_PowerControl (ARM_POWER_STATE state, uint8_t x) {
+
+  if (x >= CAN_CTRL_NUM) { return ARM_DRIVER_ERROR; }
+
+  switch (state) {
+    case ARM_POWER_OFF:
+      can_driver_powered[x] = 0U;
+      if (x == 0U) {
+        NVIC_DisableIRQ (C_CAN0_IRQn);
+
+        LPC_CGU->BASE_APB3_CLK = (1U << 11) |   // Auto-block enable
+                                 (9U << 24) ;   // Clock source: PLL1
+        LPC_CCU1->CLK_APB3_CAN0_CFG |=  1U;     // Enable C_CAN0 Base Clock
+        while ((LPC_CCU1->CLK_APB3_CAN0_CFG & 1U) == 0U);
+      } else {
+        NVIC_DisableIRQ (C_CAN1_IRQn);
+
+        LPC_CGU->BASE_APB1_CLK = (1U << 11) |   // Auto-block enable
+                                 (9U << 24) ;   // Clock source: PLL1
+        LPC_CCU1->CLK_APB1_CAN1_CFG |=  1U;     // Enable C_CAN1 Base Clock
+        while ((LPC_CCU1->CLK_APB1_CAN1_CFG & 1U) == 0U);
+      }
+
+      CANx_HW_Reset(x);
+
+      if (x == 0U) {
+        LPC_CCU1->CLK_APB3_CAN0_CFG &= ~1U;     // Disable C_CAN0 Base Clock
+        while ((LPC_CCU1->CLK_APB3_CAN0_CFG & 1U) != 0U);
+      } else {
+        LPC_CCU1->CLK_APB1_CAN1_CFG &= ~1U;     // Disable C_CAN1 Base Clock
+        while ((LPC_CCU1->CLK_APB1_CAN1_CFG & 1U) != 0U);
+      }
+      break;
+
+    case ARM_POWER_FULL:
+      if (can_driver_initialized[x] == 0U) { return ARM_DRIVER_ERROR; }
+      if (can_driver_powered[x]     != 0U) { return ARM_DRIVER_OK;    }
+
+      if (x == 0U) {
+        LPC_CGU->BASE_APB3_CLK = (1U << 11) |   // Auto-block enable
+                                 (9U << 24) ;   // Clock source: PLL1
+        LPC_CCU1->CLK_APB3_CAN0_CFG |=  1U;     // Enable C_CAN0 Base Clock
+        while ((LPC_CCU1->CLK_APB3_CAN0_CFG & 1U) == 0U);
+      } else {
+        LPC_CGU->BASE_APB1_CLK = (1U << 11) |   // Auto-block enable
+                                 (9U << 24) ;   // Clock source: PLL1
+        LPC_CCU1->CLK_APB1_CAN1_CFG |=  1U;     // Enable C_CAN1 Base Clock
+        while ((LPC_CCU1->CLK_APB1_CAN1_CFG & 1U) == 0U);
+      }
+
+      CANx_HW_Reset(x);
+
+      can_driver_powered[x] = 1U;
+
+      if (x == 0U) {
+        NVIC_ClearPendingIRQ (C_CAN0_IRQn);
+        NVIC_EnableIRQ       (C_CAN0_IRQn);
+      } else {
+        NVIC_ClearPendingIRQ (C_CAN1_IRQn);
+        NVIC_EnableIRQ       (C_CAN1_IRQn);
+      }
+      break;
+
+    default:
+      return ARM_DRIVER_ERROR_UNSUPPORTED;
+  }
+
+  return ARM_DRIVER_OK;
+}
+#if (RTE_CAN_CAN0 == 1U)
+static int32_t CAN0_PowerControl (ARM_POWER_STATE state) { return CANx_PowerControl (state, 0U); }
+#endif
+#if (RTE_CAN_CAN1 == 1U)
+static int32_t CAN1_PowerControl (ARM_POWER_STATE state) { return CANx_PowerControl (state, 1U); }
+#endif
+
+/**
+  \fn          uint32_t CAN_GetClock (void)
+  \brief       Retrieve CAN base clock frequency.
+  \return      base clock frequency
+*/
+uint32_t CAN_GetClock (void) {
+  return GetClockFreq(9U);
+}
+
+/**
+  \fn          int32_t CANx_SetBitrate (ARM_CAN_BITRATE_SELECT select, uint32_t bitrate, uint32_t bit_segments, uint8_t x)
+  \brief       Set bitrate for CAN interface.
+  \param[in]   select       Bitrate selection
+                 - ARM_CAN_BITRATE_NOMINAL : nominal (flexible data-rate arbitration) bitrate
+                 - ARM_CAN_BITRATE_FD_DATA : flexible data-rate data bitrate
+  \param[in]   bitrate      Bitrate
+  \param[in]   bit_segments Bit segments settings
+  \param[in]   x            Controller number (0..1)
+  \return      execution status
+*/
+static int32_t CANx_SetBitrate (ARM_CAN_BITRATE_SELECT select, uint32_t bitrate, uint32_t bit_segments, uint8_t x) {
+  LPC_C_CANn_Type *ptr_CAN;
+  uint32_t         cntl, clkdiv, sjw, prop_seg, phase_seg1, phase_seg2, pclk, brp, tq_num;
+
+  if (x >= CAN_CTRL_NUM)                 { return ARM_DRIVER_ERROR;               }
+  if (select != ARM_CAN_BITRATE_NOMINAL) { return ARM_CAN_INVALID_BITRATE_SELECT; }
+  if (can_driver_powered[x] == 0U)       { return ARM_DRIVER_ERROR;               }
+
+  prop_seg   = (bit_segments & ARM_CAN_BIT_PROP_SEG_Msk  ) >> ARM_CAN_BIT_PROP_SEG_Pos;
+  phase_seg1 = (bit_segments & ARM_CAN_BIT_PHASE_SEG1_Msk) >> ARM_CAN_BIT_PHASE_SEG1_Pos;
+  phase_seg2 = (bit_segments & ARM_CAN_BIT_PHASE_SEG2_Msk) >> ARM_CAN_BIT_PHASE_SEG2_Pos;
+  sjw        = (bit_segments & ARM_CAN_BIT_SJW_Msk       ) >> ARM_CAN_BIT_SJW_Pos;
+
+  if (((prop_seg + phase_seg1) < 2U) || ((prop_seg + phase_seg1) > 16U)) { return ARM_CAN_INVALID_BIT_PROP_SEG;   }
+  if (( phase_seg2             < 1U) || ( phase_seg2             >  8U)) { return ARM_CAN_INVALID_BIT_PHASE_SEG2; }
+  if (( sjw                    < 1U) || ( sjw                    >  4U)) { return ARM_CAN_INVALID_BIT_SJW;        }
+
+  ptr_CAN = ptr_CANx[x];
+
+  tq_num = 1U + prop_seg + phase_seg1 + phase_seg2;
+  pclk   = GetClockFreq(9U);
+  clkdiv = 1U;
+  while (1U) {
+    if (clkdiv == 16U)  { return ARM_DRIVER_ERROR; }
+    if (((pclk / clkdiv) <= 50000000U) && (((pclk / clkdiv) % (tq_num * bitrate)) == 0U)) { break; }
+    clkdiv++;
+  }
+  brp    = pclk / (tq_num * bitrate * clkdiv);
+  if (brp > 1024U) { return ARM_CAN_INVALID_BITRATE; }
+  if (pclk >= (brp * tq_num * bitrate * clkdiv)) {
+    if (((pclk - (brp * tq_num * bitrate * clkdiv)) * 1024U) > CAN_CLOCK_TOLERANCE) { return ARM_CAN_INVALID_BITRATE; }
+  } else {
+    if ((((brp * tq_num * bitrate * clkdiv) - pclk) * 1024U) > CAN_CLOCK_TOLERANCE) { return ARM_CAN_INVALID_BITRATE; }
+  }
+
+  cntl = ptr_CAN->CNTL;
+  if ((cntl & (CNTL_CCE_Msk | CNTL_INIT_Msk)) != (CNTL_CCE_Msk | CNTL_INIT_Msk)) {
+    ptr_CAN->CNTL = CNTL_CCE_Msk  |             // Configuration change enable
+                    CNTL_INIT_Msk ;             // Initialization
+  }
+
+  ptr_CAN->BT     = ((brp - 1U) & BT_BRP_Msk) | ((sjw - 1U) << 6) | (((prop_seg + phase_seg1) - 1U) << 8) | ((phase_seg2 - 1U) << 12);
+  ptr_CAN->BRPE   = ((brp - 1U) >> 6);
+  ptr_CAN->CLKDIV =  clkdiv - 1U;
+  ptr_CAN->CNTL   =  cntl;
+
+  return ARM_DRIVER_OK;
+}
+#if (RTE_CAN_CAN0 == 1U)
+static int32_t CAN0_SetBitrate (ARM_CAN_BITRATE_SELECT select, uint32_t bitrate, uint32_t bit_segments) { return CANx_SetBitrate (select, bitrate, bit_segments, 0U); }
+#endif
+#if (RTE_CAN_CAN1 == 1U)
+static int32_t CAN1_SetBitrate (ARM_CAN_BITRATE_SELECT select, uint32_t bitrate, uint32_t bit_segments) { return CANx_SetBitrate (select, bitrate, bit_segments, 1U); }
+#endif
+
+/**
+  \fn          int32_t CANx_SetMode (ARM_CAN_MODE mode, uint8_t x)
+  \brief       Set operating mode for CAN interface.
+  \param[in]   mode   Operating mode
+                 - ARM_CAN_MODE_INITIALIZATION :    initialization mode
+                 - ARM_CAN_MODE_NORMAL :            normal operation mode
+                 - ARM_CAN_MODE_RESTRICTED :        restricted operation mode
+                 - ARM_CAN_MODE_MONITOR :           bus monitoring mode
+                 - ARM_CAN_MODE_LOOPBACK_INTERNAL : loopback internal mode
+                 - ARM_CAN_MODE_LOOPBACK_EXTERNAL : loopback external mode
+  \param[in]   x      Controller number (0..1)
+  \return      execution status
+*/
+static int32_t CANx_SetMode (ARM_CAN_MODE mode, uint8_t x) {
+  LPC_C_CANn_Type *ptr_CAN;
+  uint32_t         event;
+
+  if (x >= CAN_CTRL_NUM)           { return ARM_DRIVER_ERROR; }
+  if (can_driver_powered[x] == 0U) { return ARM_DRIVER_ERROR; }
+
+  ptr_CAN = ptr_CANx[x];
+
+  event = 0U;
+  switch (mode) {
+    case ARM_CAN_MODE_INITIALIZATION:
+      ptr_CAN->CNTL = CNTL_INIT_Msk;
+      event = ARM_CAN_EVENT_UNIT_BUS_OFF;
+      break;
+    case ARM_CAN_MODE_NORMAL:
+      ptr_CAN->CNTL = CNTL_IE_Msk;
+      if (CAN_SignalUnitEvent[x] != NULL) { ptr_CAN->CNTL |= CNTL_SIE_Msk | CNTL_EIE_Msk; }
+      event = ARM_CAN_EVENT_UNIT_ACTIVE;
+      break;
+    case ARM_CAN_MODE_RESTRICTED:
+      return ARM_DRIVER_ERROR_UNSUPPORTED;
+    case ARM_CAN_MODE_MONITOR:
+      ptr_CAN->CNTL = CNTL_IE_Msk | CNTL_TEST_Msk;
+      if (CAN_SignalUnitEvent[x] != NULL) { ptr_CAN->CNTL |= CNTL_SIE_Msk | CNTL_EIE_Msk; }
+      ptr_CAN->TEST  = TEST_SILENT_Msk;
+      event = ARM_CAN_EVENT_UNIT_PASSIVE;
+      break;
+    case ARM_CAN_MODE_LOOPBACK_INTERNAL:
+      ptr_CAN->CNTL = CNTL_IE_Msk | CNTL_TEST_Msk;
+      if (CAN_SignalUnitEvent[x] != NULL) { ptr_CAN->CNTL |= CNTL_SIE_Msk | CNTL_EIE_Msk; }
+      ptr_CAN->TEST  = TEST_LBACK_Msk | TEST_SILENT_Msk;
+      event = ARM_CAN_EVENT_UNIT_PASSIVE;
+      break;
+    case ARM_CAN_MODE_LOOPBACK_EXTERNAL:
+      ptr_CAN->CNTL = CNTL_IE_Msk | CNTL_TEST_Msk;
+      if (CAN_SignalUnitEvent[x] != NULL) { ptr_CAN->CNTL |= CNTL_SIE_Msk | CNTL_EIE_Msk; }
+      ptr_CAN->TEST  = TEST_LBACK_Msk;
+      event = ARM_CAN_EVENT_UNIT_ACTIVE;
+      break;
+    default:
+      return ARM_DRIVER_ERROR_PARAMETER;
+  }
+  if ((CAN_SignalUnitEvent[x] != NULL) && (event != 0U)) { CAN_SignalUnitEvent[x](event); }
+
+  return ARM_DRIVER_OK;
+}
+#if (RTE_CAN_CAN0 == 1U)
+static int32_t CAN0_SetMode (ARM_CAN_MODE mode) { return CANx_SetMode (mode, 0U); }
+#endif
+#if (RTE_CAN_CAN1 == 1U)
+static int32_t CAN1_SetMode (ARM_CAN_MODE mode) { return CANx_SetMode (mode, 1U); }
+#endif
+
+/**
+  \fn          ARM_CAN_OBJ_CAPABILITIES CANx_ObjectGetCapabilities (uint32_t obj_idx, uint8_t x)
+  \brief       Retrieve capabilities of an object.
+  \param[in]   obj_idx  Object index
+  \param[in]   x        Controller number (0..1)
+  \return      ARM_CAN_OBJ_CAPABILITIES
+*/
+ARM_CAN_OBJ_CAPABILITIES CANx_ObjectGetCapabilities (uint32_t obj_idx, uint8_t x) {
+  ARM_CAN_OBJ_CAPABILITIES obj_cap_null;
+
+  if ((x >= CAN_CTRL_NUM) || (obj_idx >= ((x) ? CAN1_OBJ_NUM : CAN0_OBJ_NUM))) {
+    memset (&obj_cap_null, 0U, sizeof(ARM_CAN_OBJ_CAPABILITIES));
+    return obj_cap_null;
+  }
+
+  return can_object_capabilities;
+}
+#if (RTE_CAN_CAN0 == 1U)
+ARM_CAN_OBJ_CAPABILITIES CAN0_ObjectGetCapabilities (uint32_t obj_idx) { return CANx_ObjectGetCapabilities (obj_idx, 0U); }
+#endif
+#if (RTE_CAN_CAN1 == 1U)
+ARM_CAN_OBJ_CAPABILITIES CAN1_ObjectGetCapabilities (uint32_t obj_idx) { return CANx_ObjectGetCapabilities (obj_idx, 1U); }
+#endif
+
+/**
+  \fn          int32_t CANx_ObjectSetFilter (uint32_t obj_idx, ARM_CAN_FILTER_OPERATION operation, uint32_t id, uint32_t arg, uint8_t x)
+  \brief       Add or remove filter for message reception.
+  \param[in]   obj_idx      Object index of object that filter should be or is assigned to
+  \param[in]   operation    Operation on filter
+                 - ARM_CAN_FILTER_ID_EXACT_ADD :       add    exact id filter
+                 - ARM_CAN_FILTER_ID_EXACT_REMOVE :    remove exact id filter
+                 - ARM_CAN_FILTER_ID_RANGE_ADD :       add    range id filter
+                 - ARM_CAN_FILTER_ID_RANGE_REMOVE :    remove range id filter
+                 - ARM_CAN_FILTER_ID_MASKABLE_ADD :    add    maskable id filter
+                 - ARM_CAN_FILTER_ID_MASKABLE_REMOVE : remove maskable id filter
+  \param[in]   id           ID or start of ID range (depending on filter type)
+  \param[in]   arg          Mask or end of ID range (depending on filter type)
+  \param[in]   x            Controller number (0..1)
+  \return      execution status
+*/
+static int32_t CANx_ObjectSetFilter (uint32_t obj_idx, ARM_CAN_FILTER_OPERATION operation, uint32_t id, uint32_t arg, uint8_t x) {
+  LPC_C_CANn_Type *ptr_CAN;
+
+  if (x >= CAN_CTRL_NUM)                              { return ARM_DRIVER_ERROR;           }
+  if (obj_idx >= ((x) ? CAN1_OBJ_NUM : CAN0_OBJ_NUM)) { return ARM_DRIVER_ERROR_PARAMETER; }
+  if (can_driver_powered[x] == 0U)                    { return ARM_DRIVER_ERROR;           }
+
+  ptr_CAN = ptr_CANx[x];
+  if ((ptr_CAN->IF1_CMDREQ&IF_CMDREQ_BUSY_Msk)!=0U)   { return ARM_DRIVER_ERROR_BUSY;      }
+
+  ptr_CAN->IF1_CMDMSK_R =                               // Read
+                           IF_CMDMSK_ARB_Msk   ;        // Access arbitration
+  ptr_CAN->IF1_CMDREQ   =  obj_idx + 1U;                // Read from message object
+  while ((ptr_CAN->IF1_CMDREQ&IF_CMDREQ_BUSY_Msk)!=0U); // Wait for read to finish
+                                                        // If arbitration in non-zero means filter is already set
+  switch (operation) {
+    case ARM_CAN_FILTER_ID_EXACT_ADD:
+    case ARM_CAN_FILTER_ID_MASKABLE_ADD:
+      if ((ptr_CAN->IF1_ARB1 != 0U) || (ptr_CAN->IF1_ARB2 != 0U)) { return ARM_DRIVER_ERROR; }
+      break;
+    case ARM_CAN_FILTER_ID_EXACT_REMOVE:
+    case ARM_CAN_FILTER_ID_MASKABLE_REMOVE:
+      if ((ptr_CAN->IF1_ARB1 == 0U) && (ptr_CAN->IF1_ARB2 == 0U)) { return ARM_DRIVER_OK;    }
+      break;
+    case ARM_CAN_FILTER_ID_RANGE_ADD:
+    case ARM_CAN_FILTER_ID_RANGE_REMOVE:
+    default:
+      return ARM_DRIVER_ERROR_UNSUPPORTED;
+  }
+
+  ptr_CAN->IF1_CMDMSK_W =  IF_CMDMSK_WR_RD_Msk |        // Write
+                           IF_CMDMSK_ARB_Msk   ;        // Access arbitration
+  ptr_CAN->IF1_ARB2     =  0U;                          // Invalidate message object (MSGVAL = 0)
+  ptr_CAN->IF1_CMDREQ   =  obj_idx + 1U;                // Write to message object
+  while ((ptr_CAN->IF1_CMDREQ&IF_CMDREQ_BUSY_Msk)!=0U); // Wait for write to finish
+
+  ptr_CAN->IF1_CMDMSK_W =  IF_CMDMSK_WR_RD_Msk |        // Write
+                           IF_CMDMSK_MASK_Msk  |        // Access mask
+                           IF_CMDMSK_ARB_Msk   |        // Access arbitration
+                           IF_CMDMSK_CTRL_Msk  ;        // Access control bits
+
+  switch (operation) {
+    case ARM_CAN_FILTER_ID_EXACT_ADD:
+      if ((id & ARM_CAN_ID_IDE_Msk) != 0U) {            // Extended Identifier
+        ptr_CAN->IF1_MSK1 =   0xFFFFU;
+        ptr_CAN->IF1_MSK2 =   0xBFFFU;
+        ptr_CAN->IF1_ARB1 =   id         & IF_ARB1_ID15_0_Msk;
+        ptr_CAN->IF1_ARB2 = ((id  >> 16) & IF_ARB2_ID28_16_Msk) | IF_ARB2_XTD_Msk;
+      } else {                                          // Standard Identifier
+        ptr_CAN->IF1_MSK1 =   0U;
+        ptr_CAN->IF1_MSK2 =   0xBFFCU;
+        ptr_CAN->IF1_ARB1 =   0U;
+        ptr_CAN->IF1_ARB2 =  (id  <<  2) & IF_ARB2_ID28_16_Msk;
+      }
+      break;
+    case ARM_CAN_FILTER_ID_MASKABLE_ADD:
+      if ((id & ARM_CAN_ID_IDE_Msk) != 0U) {            // Extended Identifier
+        ptr_CAN->IF1_MSK1 =   arg        & IF_MSK1_MSK15_0_Msk;
+        ptr_CAN->IF1_MSK2 = ((arg >> 16) & IF_MSK2_MSK28_16_Msk) | IF_MSK2_MXTD_Msk;
+        ptr_CAN->IF1_ARB1 =   id         & IF_ARB1_ID15_0_Msk;
+        ptr_CAN->IF1_ARB2 = ((id  >> 16) & IF_ARB2_ID28_16_Msk)  | IF_ARB2_XTD_Msk;
+      } else {                                          // Standard Identifier
+        ptr_CAN->IF1_MSK1 =   0U;
+        ptr_CAN->IF1_MSK2 = ((arg <<  2) & IF_MSK2_MSK28_16_Msk) | IF_MSK2_MXTD_Msk;
+        ptr_CAN->IF1_ARB1 =   0U;
+        ptr_CAN->IF1_ARB2 =  (id  <<  2) & IF_ARB2_ID28_16_Msk;
+      }
+      break;
+    case ARM_CAN_FILTER_ID_EXACT_REMOVE:
+    case ARM_CAN_FILTER_ID_MASKABLE_REMOVE:
+      ptr_CAN->IF1_MSK1 = 0U;
+      ptr_CAN->IF1_MSK2 = 0U;
+      ptr_CAN->IF1_ARB1 = 0U;
+      ptr_CAN->IF1_ARB2 = 0U;
+      break;
+    case ARM_CAN_FILTER_ID_RANGE_ADD:
+    case ARM_CAN_FILTER_ID_RANGE_REMOVE:
+    default:
+      return ARM_DRIVER_ERROR_UNSUPPORTED;
+  }
+
+  ptr_CAN->IF1_CMDREQ   =  obj_idx + 1U;                // Write to message object
+  while ((ptr_CAN->IF1_CMDREQ&IF_CMDREQ_BUSY_Msk)!=0U); // Wait for write to finish
+
+  return ARM_DRIVER_OK;
+}
+#if (RTE_CAN_CAN0 == 1U)
+static int32_t CAN0_ObjectSetFilter (uint32_t obj_idx, ARM_CAN_FILTER_OPERATION operation, uint32_t id, uint32_t arg) { return CANx_ObjectSetFilter (obj_idx, operation, id, arg, 0U); }
+#endif
+#if (RTE_CAN_CAN1 == 1U)
+static int32_t CAN1_ObjectSetFilter (uint32_t obj_idx, ARM_CAN_FILTER_OPERATION operation, uint32_t id, uint32_t arg) { return CANx_ObjectSetFilter (obj_idx, operation, id, arg, 1U); }
+#endif
+
+/**
+  \fn          int32_t CANx_ObjectConfigure (uint32_t obj_idx, ARM_CAN_OBJ_CONFIG obj_cfg, uint8_t x)
+  \brief       Configure object.
+  \param[in]   obj_idx  Object index
+  \param[in]   obj_cfg  Object configuration state
+                 - ARM_CAN_OBJ_INACTIVE :       deactivate object
+                 - ARM_CAN_OBJ_RX :             configure object for reception
+                 - ARM_CAN_OBJ_TX :             configure object for transmission
+                 - ARM_CAN_OBJ_RX_RTR_TX_DATA : configure object that on RTR reception automatically transmits Data Frame
+                 - ARM_CAN_OBJ_TX_RTR_RX_DATA : configure object that transmits RTR and automatically receives Data Frame
+  \param[in]   x        Controller number (0..1)
+  \return      execution status
+*/
+static int32_t CANx_ObjectConfigure (uint32_t obj_idx, ARM_CAN_OBJ_CONFIG obj_cfg, uint8_t x) {
+  LPC_C_CANn_Type *ptr_CAN;
+
+  if (x >= CAN_CTRL_NUM)                              { return ARM_DRIVER_ERROR;           }
+  if (obj_idx >= ((x) ? CAN1_OBJ_NUM : CAN0_OBJ_NUM)) { return ARM_DRIVER_ERROR_PARAMETER; }
+  if (can_driver_powered[x] == 0U)                    { return ARM_DRIVER_ERROR;           }
+
+  ptr_CAN = ptr_CANx[x];
+  if ((ptr_CAN->IF1_CMDREQ&IF_CMDREQ_BUSY_Msk)!=0U)   { return ARM_DRIVER_ERROR_BUSY;      }
+
+  ptr_CAN->IF1_CMDMSK_R =                               // Read
+                           IF_CMDMSK_MASK_Msk  |        // Access mask
+                           IF_CMDMSK_ARB_Msk   |        // Access arbitration
+                           IF_CMDMSK_CTRL_Msk  ;        // Access control bits
+  ptr_CAN->IF1_CMDREQ   =  obj_idx + 1U;                // Write to message object
+  while ((ptr_CAN->IF1_CMDREQ&IF_CMDREQ_BUSY_Msk)!=0U); // Wait for read to finish
+
+  ptr_CAN->IF1_CMDMSK_W =  IF_CMDMSK_WR_RD_Msk |        // Write
+                           IF_CMDMSK_MASK_Msk  |        // Access mask
+                           IF_CMDMSK_ARB_Msk   |        // Access arbitration
+                           IF_CMDMSK_CTRL_Msk  ;        // Access control bits
+
+  switch (obj_cfg) {
+    case ARM_CAN_OBJ_INACTIVE:
+      ptr_CAN->IF1_ARB2   =  0U;                        // Invalidate message object (MSGVAL = 0)
+      ptr_CAN->IF1_MCTRL  =  0U;                        // Clear control register
+      break;
+    case ARM_CAN_OBJ_TX:
+      ptr_CAN->IF1_MSK2  |=  IF_MSK2_MDIR_Msk   ;       // Use DIR for acceptance filtering
+      ptr_CAN->IF1_ARB2  |=  IF_ARB2_DIR_Msk    |       // Tx object
+                             IF_ARB2_MSGVAL_Msk ;       // Message is Valid
+      ptr_CAN->IF1_MCTRL  =  IF_MCTRL_EOB_Msk   |       // End of Buffer
+                             IF_MCTRL_TXIE_Msk  ;       // Tx Interrupt Enable
+      break;
+    case ARM_CAN_OBJ_RX:
+      ptr_CAN->IF1_MSK2  |=  IF_MSK2_MDIR_Msk   ;       // Use DIR for acceptance filtering
+      ptr_CAN->IF1_ARB2  &= ~IF_ARB2_DIR_Msk    ;       // Rx object
+      ptr_CAN->IF1_ARB2  |=  IF_ARB2_MSGVAL_Msk ;       // Message is Valid
+      ptr_CAN->IF1_MCTRL  =  IF_MCTRL_UMASK_Msk |       // Use mask for acceptance filtering
+                             IF_MCTRL_EOB_Msk   |       // End of Buffer
+                             IF_MCTRL_RXIE_Msk  |       // Rx Interrupt Enable
+                             8U                 ;       // Receive 8 bytes
+      break;
+    case ARM_CAN_OBJ_RX_RTR_TX_DATA:
+      ptr_CAN->IF1_MSK2  &= ~IF_MSK2_MDIR_Msk   ;       // Do not use DIR for acceptance filtering
+      ptr_CAN->IF1_ARB2  |=  IF_ARB2_DIR_Msk    |       // Tx object
+                             IF_ARB2_MSGVAL_Msk ;       // Message is Valid
+      ptr_CAN->IF1_MCTRL  =  IF_MCTRL_UMASK_Msk |       // Use mask for acceptance filtering
+                             IF_MCTRL_EOB_Msk   |       // End of Buffer
+                             IF_MCTRL_TXIE_Msk  |       // Tx Interrupt Enable
+                             IF_MCTRL_RMTEN_Msk ;       // Remote Enable
+      break;
+    case ARM_CAN_OBJ_TX_RTR_RX_DATA:
+      ptr_CAN->IF1_MSK2  &= ~IF_MSK2_MDIR_Msk   ;       // Do not use DIR for acceptance filtering
+      ptr_CAN->IF1_ARB2  &= ~IF_ARB2_DIR_Msk    ;       // Rx object
+      ptr_CAN->IF1_ARB2  |=  IF_ARB2_MSGVAL_Msk ;       // Message is Valid
+      ptr_CAN->IF1_MCTRL  =  IF_MCTRL_UMASK_Msk |       // Use mask for acceptance filtering
+                             IF_MCTRL_EOB_Msk   |       // End of Buffer
+                             IF_MCTRL_RXIE_Msk  ;       // Rx Interrupt Enable
+      break;
+    default:
+      return ARM_DRIVER_ERROR;
+  }
+  can_obj_cfg[x][obj_idx] = obj_cfg;
+
+  ptr_CAN->IF1_CMDREQ = obj_idx + 1U;                   // Write to message object
+  while ((ptr_CAN->IF1_CMDREQ&IF_CMDREQ_BUSY_Msk)!=0U); // Wait for write to finish
+
+  return ARM_DRIVER_OK;
+}
+#if (RTE_CAN_CAN0 == 1U)
+static int32_t CAN0_ObjectConfigure (uint32_t obj_idx, ARM_CAN_OBJ_CONFIG obj_cfg) { return CANx_ObjectConfigure (obj_idx, obj_cfg, 0U); }
+#endif
+#if (RTE_CAN_CAN1 == 1U)
+static int32_t CAN1_ObjectConfigure (uint32_t obj_idx, ARM_CAN_OBJ_CONFIG obj_cfg) { return CANx_ObjectConfigure (obj_idx, obj_cfg, 1U); }
+#endif
+
+/**
+  \fn          int32_t CANx_MessageSend (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, const uint8_t *data, uint8_t size, uint8_t x)
+  \brief       Send message on CAN bus.
+  \param[in]   obj_idx  Object index
+  \param[in]   msg_info Pointer to CAN message information
+  \param[in]   data     Pointer to data buffer
+  \param[in]   size     Number of data bytes to send
+  \param[in]   x        Controller number (0..1)
+  \return      value >= 0  number of data bytes accepted to send
+  \return      value < 0   execution status
+*/
+static int32_t CANx_MessageSend (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, const uint8_t *data, uint8_t size, uint8_t x) {
+  LPC_C_CANn_Type *ptr_CAN;
+  uint32_t         arb1, arb2, mctrl;
+
+  if (x >= CAN_CTRL_NUM)                              { return ARM_DRIVER_ERROR;           }
+  if (obj_idx >= ((x) ? CAN1_OBJ_NUM : CAN0_OBJ_NUM)) { return ARM_DRIVER_ERROR_PARAMETER; }
+  if (can_driver_powered[x]   == 0U)                  { return ARM_DRIVER_ERROR;           }
+  if (can_obj_cfg[x][obj_idx] == ARM_CAN_OBJ_RX)      { return ARM_DRIVER_ERROR;           }
+
+  ptr_CAN = ptr_CANx[x];
+
+  if ((((ptr_CAN->TXREQ2 << 16) | (ptr_CAN->TXREQ1 & 0xFFFFU)) & (1U << obj_idx)) != 0U) {
+    return ARM_DRIVER_ERROR_BUSY;
+  }
+  if ((ptr_CAN->IF1_CMDREQ&IF_CMDREQ_BUSY_Msk)!=0U)   { return ARM_DRIVER_ERROR_BUSY;      }
+
+  ptr_CAN->IF1_CMDMSK_R =                               // Read
+                           IF_CMDMSK_ARB_Msk   |        // Access arbitration
+                           IF_CMDMSK_CTRL_Msk  |        // Access control bits
+                           IF_CMDMSK_NEWDAT_Msk;        // Clear NEWDAT bit
+  ptr_CAN->IF1_CMDREQ   =  obj_idx + 1U;                // Read from message object
+  while ((ptr_CAN->IF1_CMDREQ&IF_CMDREQ_BUSY_Msk)!=0U); // Wait for read to finish
+
+  mctrl = ptr_CAN->IF1_MCTRL;                           // Store current value of MCTRL register
+  arb1  = ptr_CAN->IF1_ARB1;                            // Store current value of ARB1 register
+  arb2  = ptr_CAN->IF1_ARB2;                            // Store current value of ARB2 register
+
+  // Prepare arb1..2
+  if (can_obj_cfg[x][obj_idx] == ARM_CAN_OBJ_TX) {      // For Tx object id is prepared here
+    if (msg_info->id & ARM_CAN_ID_IDE_Msk) {            // Extended Identifier
+      arb1 =   msg_info->id        & IF_ARB1_ID15_0_Msk;
+      arb2 = ((msg_info->id >> 16) & IF_ARB2_ID28_16_Msk)  | IF_ARB2_XTD_Msk | IF_ARB2_MSGVAL_Msk;
+    } else {                                            // Standard Identifier
+      arb1 =   0U;
+      arb2 = ((msg_info->id <<  2) & IF_ARB2_ID28_16_Msk)                    | IF_ARB2_MSGVAL_Msk;
+    }
+  }
+
+  switch (can_obj_cfg[x][obj_idx]) {
+    case ARM_CAN_OBJ_INACTIVE:
+    case ARM_CAN_OBJ_RX:
+      return ARM_DRIVER_ERROR;
+    case ARM_CAN_OBJ_TX:
+      if (msg_info->rtr == 0U) {                        // If Data frame transmit requested
+        arb2 |=  IF_ARB2_DIR_Msk;                       // Tx object
+      } else {                                          // else if Remote Transmission Request frame transmit requested
+        size     =  msg_info->dlc;                      // Prepare number of data bytes to request
+      }
+      if (size > 8U) { size = 8U; }
+      mctrl      = (mctrl & ~0xFU)      |
+                    IF_MCTRL_TXRQST_Msk |               // Set Tx Request
+                    size                ;               // Number of bytes to transmit or requested by RTR
+      break;
+    case ARM_CAN_OBJ_RX_RTR_TX_DATA:
+      mctrl      = (mctrl & ~0xFU)      |
+                    size                ;               // Number of bytes to transmit or requested by RTR
+      break;
+    case ARM_CAN_OBJ_TX_RTR_RX_DATA:
+      if (msg_info->rtr) {                              // If Remote Transmission Request frame transmit requested
+        size     =  msg_info->dlc;                      // Prepare number of data bytes to request
+      }
+      if (size > 8U) { size = 8U; }
+      mctrl      = (mctrl & ~0xFU)      |
+                    IF_MCTRL_TXRQST_Msk |               // Set Tx Request
+                    size                ;               // Number of bytes requested by RTR
+      break;
+    default:
+      return ARM_DRIVER_ERROR;
+  }                                                     // Store object type information
+
+  ptr_CAN->IF1_CMDMSK_W =  IF_CMDMSK_WR_RD_Msk |        // Write
+                           IF_CMDMSK_ARB_Msk   |        // Access arbitration
+                           IF_CMDMSK_CTRL_Msk  ;        // Access control bits
+  ptr_CAN->IF1_ARB1  = arb1;
+  ptr_CAN->IF1_ARB2  = arb2;
+  ptr_CAN->IF1_MCTRL = mctrl;
+
+  if (can_obj_cfg[x][obj_idx] != ARM_CAN_OBJ_TX_RTR_RX_DATA) {
+    ptr_CAN->IF1_DA1   = (((uint16_t)(data[1])) << 8) | data[0];
+    ptr_CAN->IF1_DA2   = (((uint16_t)(data[3])) << 8) | data[2];
+    ptr_CAN->IF1_CMDMSK_W |= IF_CMDMSK_DATA_A_Msk;      // Access data bytes 0..3
+    if (size > 4) {
+      ptr_CAN->IF1_DB1 = (((uint16_t)(data[5])) << 8) | data[4];
+      ptr_CAN->IF1_DB2 = (((uint16_t)(data[7])) << 8) | data[6];
+      ptr_CAN->IF1_CMDMSK_W |= IF_CMDMSK_DATA_B_Msk;    // Access data bytes 4..7
+    }
+  }
+
+  ptr_CAN->IF1_CMDREQ   =  obj_idx + 1U;                // Write to message object
+  while ((ptr_CAN->IF1_CMDREQ&IF_CMDREQ_BUSY_Msk)!=0U); // Wait for write to finish
+
+  return ((int32_t)size);
+}
+#if (RTE_CAN_CAN0 == 1U)
+static int32_t CAN0_MessageSend (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, const uint8_t *data, uint8_t size) { return CANx_MessageSend (obj_idx, msg_info, data, size, 0U); }
+#endif
+#if (RTE_CAN_CAN1 == 1U)
+static int32_t CAN1_MessageSend (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, const uint8_t *data, uint8_t size) { return CANx_MessageSend (obj_idx, msg_info, data, size, 1U); }
+#endif
+
+/**
+  \fn          int32_t CANx_MessageRead (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, uint8_t *data, uint8_t size, uint8_t x)
+  \brief       Read message received on CAN bus.
+  \param[in]   obj_idx  Object index
+  \param[out]  msg_info Pointer to read CAN message information
+  \param[out]  data     Pointer to data buffer for read data
+  \param[in]   size     Maximum number of data bytes to read
+  \param[in]   x        Controller number (0..1)
+  \return      value >= 0  number of data bytes read
+  \return      value < 0   execution status
+*/
+static int32_t CANx_MessageRead (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, uint8_t *data, uint8_t size, uint8_t x) {
+  LPC_C_CANn_Type *ptr_CAN;
+
+  if (x >= CAN_CTRL_NUM)                                     { return ARM_DRIVER_ERROR;           }
+  if (obj_idx >= ((x) ? CAN1_OBJ_NUM : CAN0_OBJ_NUM))        { return ARM_DRIVER_ERROR_PARAMETER; }
+  if (can_driver_powered[x]   == 0U)                         { return ARM_DRIVER_ERROR;           }
+  if (can_obj_cfg[x][obj_idx] == ARM_CAN_OBJ_TX)             { return ARM_DRIVER_ERROR;           }
+  if (can_obj_cfg[x][obj_idx] == ARM_CAN_OBJ_RX_RTR_TX_DATA) { return ARM_DRIVER_ERROR;           }
+
+  ptr_CAN = ptr_CANx[x];
+
+  if (size > 8U) { size = 8U; }
+
+  ptr_CAN->IF1_CMDMSK_R =                               // Read
+                           IF_CMDMSK_ARB_Msk    |       // Access arbitration
+                           IF_CMDMSK_CTRL_Msk   |       // Access control bits
+                           IF_CMDMSK_NEWDAT_Msk |       // Access New Data bit (clear it)
+                           IF_CMDMSK_DATA_B_Msk |       // Access data bytes 4..7
+                           IF_CMDMSK_DATA_A_Msk ;       // Access data bytes 0..3
+  ptr_CAN->IF1_CMDREQ   =  obj_idx + 1U;                // Read from message object
+  while ((ptr_CAN->IF1_CMDREQ&IF_CMDREQ_BUSY_Msk)!=0U); // Wait for read to finish
+
+  if ((ptr_CAN->IF1_ARB2 & IF_ARB2_XTD_Msk) != 0U) {    // Extended Identifier
+    msg_info->id = (0x1FFFFFFFU & (((ptr_CAN->IF1_ARB2 & IF_ARB2_ID28_16_Msk) << 16) | (ptr_CAN->IF1_ARB1 & IF_ARB1_ID15_0_Msk))) | ARM_CAN_ID_IDE_Msk;
+  } else {                                              // Standard Identifier
+    msg_info->id = (0x000007FFU &  ((ptr_CAN->IF1_ARB2 & IF_ARB2_ID28_16_Msk) >>  2));
+  }
+  msg_info->rtr = 0U;
+  msg_info->dlc = ptr_CAN->IF1_MCTRL & IF_MCTRL_DLC3_0_Msk;
+
+  if (size > msg_info->dlc) { size = msg_info->dlc; }
+
+  if (size > 0U) {               data[0] = (ptr_CAN->IF1_DA1);
+    if (size > 1U) {             data[1] = (ptr_CAN->IF1_DA1 >> 8);
+      if (size > 2U) {           data[2] = (ptr_CAN->IF1_DA2);
+        if (size > 3U) {         data[3] = (ptr_CAN->IF1_DA2 >> 8);
+          if (size > 4U) {       data[4] = (ptr_CAN->IF1_DB1);
+            if (size > 5U) {     data[5] = (ptr_CAN->IF1_DB1 >> 8);
+              if (size > 6U) {   data[6] = (ptr_CAN->IF1_DB2);
+                if (size > 7U) { data[7] = (ptr_CAN->IF1_DB2 >> 8); }
+              }
+            }
+          }
+        }
+      }
+    }
+  }
+
+  if (ptr_CAN->IF1_MCTRL & IF_MCTRL_MSGLST_Msk) {
+    // If message was lost (MSGLST=1), clear this bit for new reception as now
+    // the message was read-out and is free for new reception
+    ptr_CAN->IF1_MCTRL   &= ~(IF_MCTRL_MSGLST_Msk | IF_MCTRL_NEWDAT_Msk | IF_MCTRL_INTPND_Msk);
+    ptr_CAN->IF1_CMDMSK_W =   IF_CMDMSK_CTRL_Msk |
+                              IF_CMDMSK_WR_RD_Msk;
+    ptr_CAN->IF1_CMDREQ   =   obj_idx + 1U;
+    while ((ptr_CAN->IF1_CMDREQ&IF_CMDREQ_BUSY_Msk)!=0U);       // Wait for read to finish
+  }
+
+  return ((int32_t)size);
+}
+#if (RTE_CAN_CAN0 == 1U)
+static int32_t CAN0_MessageRead (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, uint8_t *data, uint8_t size) { return CANx_MessageRead (obj_idx, msg_info, data, size, 0U); }
+#endif
+#if (RTE_CAN_CAN1 == 1U)
+static int32_t CAN1_MessageRead (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, uint8_t *data, uint8_t size) { return CANx_MessageRead (obj_idx, msg_info, data, size, 1U); }
+#endif
+
+/**
+  \fn          int32_t CANx_Control (uint32_t control, uint32_t arg, uint8_t x)
+  \brief       Control CAN interface.
+  \param[in]   control  Operation
+                 - ARM_CAN_SET_FD_MODE :            set FD operation mode
+                 - ARM_CAN_ABORT_MESSAGE_SEND :     abort sending of CAN message
+                 - ARM_CAN_CONTROL_RETRANSMISSION : enable/disable automatic retransmission
+                 - ARM_CAN_SET_TRANSCEIVER_DELAY :  set transceiver delay
+  \param[in]   arg      Argument of operation
+  \param[in]   x        Controller number (0..1)
+  \return      execution status
+*/
+static int32_t CANx_Control (uint32_t control, uint32_t arg, uint8_t x) {
+  LPC_C_CANn_Type *ptr_CAN;
+
+  if (x >= CAN_CTRL_NUM)           { return ARM_DRIVER_ERROR; }
+  if (can_driver_powered[x] == 0U) { return ARM_DRIVER_ERROR; }
+
+  ptr_CAN = ptr_CANx[x];
+
+  switch (control & ARM_CAN_CONTROL_Msk) {
+    case ARM_CAN_ABORT_MESSAGE_SEND:
+      if (arg >= ((x) ? CAN1_OBJ_NUM : CAN0_OBJ_NUM)) { return ARM_DRIVER_ERROR_PARAMETER; }
+      if (can_obj_cfg[x][arg] != ARM_CAN_OBJ_TX)      { return ARM_DRIVER_ERROR;           }
+      CANx_AbortSendMessage (arg, x);
+      break;
+    case ARM_CAN_CONTROL_RETRANSMISSION:
+      switch (arg) {
+        case 0:
+          ptr_CAN->CNTL |=  CNTL_DAR_Msk;       // Disable automatic retransmission
+          break;
+        case 1:
+          ptr_CAN->CNTL &= ~CNTL_DAR_Msk;       // Enable automatic retransmission
+          break;
+        default:
+          return ARM_DRIVER_ERROR_PARAMETER;
+      }
+      break;
+    case ARM_CAN_SET_FD_MODE:
+    case ARM_CAN_SET_TRANSCEIVER_DELAY:
+    default:
+      return ARM_DRIVER_ERROR_UNSUPPORTED;
+  }
+
+  return ARM_DRIVER_OK;
+}
+#if (RTE_CAN_CAN0 == 1U)
+static int32_t CAN0_Control (uint32_t control, uint32_t arg) { return CANx_Control (control, arg, 0U); }
+#endif
+#if (RTE_CAN_CAN1 == 1U)
+static int32_t CAN1_Control (uint32_t control, uint32_t arg) { return CANx_Control (control, arg, 1U); }
+#endif
+
+/**
+  \fn          ARM_CAN_STATUS CANx_GetStatus (uint8_t x)
+  \brief       Get CAN status.
+  \param[in]   x      Controller number (0..1)
+  \return      CAN status ARM_CAN_STATUS
+*/
+static ARM_CAN_STATUS CANx_GetStatus (uint8_t x) {
+  LPC_C_CANn_Type *ptr_CAN;
+  ARM_CAN_STATUS   can_status;
+  uint32_t         stat, ec;
+
+  if ((x >= CAN_CTRL_NUM) || (can_driver_powered[x] == 0U)) {
+    memset(&can_status, 0U, sizeof(ARM_CAN_STATUS));
+    return can_status;
+  }
+
+  ptr_CAN = ptr_CANx[x];
+  stat    = ptr_CAN->STAT;
+  ec      = ptr_CAN->EC;
+
+  if       ((ptr_CAN->CNTL & CNTL_INIT_Msk)    != 0U)  { can_status.unit_state = ARM_CAN_UNIT_STATE_INACTIVE; }
+  else if  (((ptr_CAN->CNTL & CNTL_TEST_Msk)   != 0U) &&
+            ((ptr_CAN->TEST & TEST_SILENT_Msk) != 0U)) { can_status.unit_state = ARM_CAN_UNIT_STATE_PASSIVE;  }
+  else if  ((stat & STAT_BOFF_Msk)  != 0U)             { can_status.unit_state = ARM_CAN_UNIT_STATE_INACTIVE; }
+  else if  ((stat & STAT_EPASS_Msk) != 0U)             { can_status.unit_state = ARM_CAN_UNIT_STATE_PASSIVE;  }
+  else                                                 { can_status.unit_state = ARM_CAN_UNIT_STATE_ACTIVE;   }
+
+  switch (stat & STAT_LEC_Msk) {
+    case 0:
+      can_status.last_error_code = ARM_CAN_LEC_NO_ERROR;
+      break;
+    case 1:
+      can_status.last_error_code = ARM_CAN_LEC_STUFF_ERROR;
+      break;
+    case 2:
+      can_status.last_error_code = ARM_CAN_LEC_FORM_ERROR;
+      break;
+    case 3:
+      can_status.last_error_code = ARM_CAN_LEC_ACK_ERROR;
+      break;
+    case 4:
+    case 5:
+      can_status.last_error_code = ARM_CAN_LEC_BIT_ERROR;
+      break;
+    case 6:
+      can_status.last_error_code = ARM_CAN_LEC_CRC_ERROR;
+      break;
+    case 7:
+      can_status.last_error_code = ARM_CAN_LEC_NO_ERROR;
+      break;
+  }
+
+  can_status.tx_error_count = (uint8_t)((ec & EC_TEC_7_0_Msk));
+  if ((ec & EC_RP_Msk) != 0U) {
+    can_status.rx_error_count = 128U;
+  } else {
+    can_status.rx_error_count = (uint8_t)((ec & EC_REC_6_0_Msk) >> 8);
+  }
+
+  return can_status;
+}
+#if (RTE_CAN_CAN0 == 1U)
+static ARM_CAN_STATUS CAN0_GetStatus (void) { return CANx_GetStatus (0U); }
+#endif
+#if (RTE_CAN_CAN1 == 1U)
+static ARM_CAN_STATUS CAN1_GetStatus (void) { return CANx_GetStatus (1U); }
+#endif
+
+/**
+  \fn          void CAN0_IRQHandler (void)
+  \brief       CAN0 Interrupt Routine (IRQ).
+*/
+#if (RTE_CAN_CAN0 == 1U)
+void CAN0_IRQHandler (void) {
+  uint32_t       obj_idx, stat;
+
+  while (1) {
+    obj_idx = LPC_C_CAN0->INT; if (obj_idx == 0U) { break; }
+    if (obj_idx && (obj_idx <= 0x20U)) {        // Message Object Interrupt
+      LPC_C_CAN0->IF2_CMDMSK_R = IF_CMDMSK_CTRL_Msk | IF_CMDMSK_CLRINTPND_Msk;
+      LPC_C_CAN0->IF2_CMDREQ   = obj_idx;
+      while (LPC_C_CAN0->IF2_CMDREQ & IF_CMDREQ_BUSY_Msk);
+      obj_idx --;
+      if (CAN_SignalObjectEvent[0] != NULL) {
+        switch (can_obj_cfg[0][obj_idx]) {
+          case ARM_CAN_OBJ_INACTIVE:
+            break;
+          case ARM_CAN_OBJ_TX:
+            CAN_SignalObjectEvent[0](obj_idx, ARM_CAN_EVENT_SEND_COMPLETE);
+            break;
+          case ARM_CAN_OBJ_RX:
+            if (LPC_C_CAN0->IF2_MCTRL & IF_MCTRL_MSGLST_Msk) {
+              CAN_SignalObjectEvent[0](obj_idx, ARM_CAN_EVENT_RECEIVE | ARM_CAN_EVENT_RECEIVE_OVERRUN);
+            } else {
+              CAN_SignalObjectEvent[0](obj_idx, ARM_CAN_EVENT_RECEIVE);
+            }
+            break;
+          case ARM_CAN_OBJ_RX_RTR_TX_DATA:
+            CAN_SignalObjectEvent[0](obj_idx, ARM_CAN_EVENT_SEND_COMPLETE);
+            break;
+          case ARM_CAN_OBJ_TX_RTR_RX_DATA:
+            if (LPC_C_CAN0->IF2_MCTRL & IF_MCTRL_NEWDAT_Msk) {
+              if (LPC_C_CAN0->IF2_MCTRL & IF_MCTRL_MSGLST_Msk) {
+                CAN_SignalObjectEvent[0](obj_idx, ARM_CAN_EVENT_RECEIVE | ARM_CAN_EVENT_RECEIVE_OVERRUN);
+              } else {
+                CAN_SignalObjectEvent[0](obj_idx, ARM_CAN_EVENT_RECEIVE);
+              }
+          }
+          break;
+        default:
+          break;
+      }
+    }
+    } else if (obj_idx == 0x8000U) {            // Status interrupt
+      stat = LPC_C_CAN0->STAT;
+      if (CAN_SignalUnitEvent[0] != NULL) { 
+        if ((stat ^ can_stat_last[0]) & (STAT_BOFF_Msk | STAT_EPASS_Msk | STAT_EWARN_Msk)) {
+          if      (stat & (stat ^ can_stat_last[0]) & STAT_BOFF_Msk )        { CAN_SignalUnitEvent[0](ARM_CAN_EVENT_UNIT_BUS_OFF); }
+          else if (stat & (stat ^ can_stat_last[0]) & STAT_EPASS_Msk)        { CAN_SignalUnitEvent[0](ARM_CAN_EVENT_UNIT_PASSIVE); }
+          else if (stat & (stat ^ can_stat_last[0]) & STAT_EWARN_Msk)        { CAN_SignalUnitEvent[0](ARM_CAN_EVENT_UNIT_WARNING); }
+          else if (stat & (STAT_BOFF_Msk | STAT_EPASS_Msk | STAT_EWARN_Msk)) { CAN_SignalUnitEvent[0](ARM_CAN_EVENT_UNIT_ACTIVE);  }
+        }
+        can_stat_last[0] = stat;
+      }
+    }
+  }
+}
+#endif
+
+/**
+  \fn          void CAN1_IRQHandler (void)
+  \brief       CAN1 Interrupt Routine (IRQ).
+*/
+#if (RTE_CAN_CAN1 == 1U)
+void CAN1_IRQHandler (void) {
+  uint32_t       obj_idx, stat;
+
+  while (1) {
+    obj_idx = LPC_C_CAN1->INT; if (obj_idx == 0U) { break; }
+    if (obj_idx && (obj_idx <= 0x20U)) {        // Message Object Interrupt
+      LPC_C_CAN1->IF2_CMDMSK_R = IF_CMDMSK_CTRL_Msk | IF_CMDMSK_CLRINTPND_Msk;
+      LPC_C_CAN1->IF2_CMDREQ   = obj_idx;
+      while (LPC_C_CAN1->IF2_CMDREQ & IF_CMDREQ_BUSY_Msk);
+      obj_idx --;
+      if (CAN_SignalObjectEvent[1] != NULL) {
+        switch (can_obj_cfg[1][obj_idx]) {
+          case ARM_CAN_OBJ_INACTIVE:
+            break;
+          case ARM_CAN_OBJ_TX:
+            CAN_SignalObjectEvent[1](obj_idx, ARM_CAN_EVENT_SEND_COMPLETE);
+            break;
+          case ARM_CAN_OBJ_RX:
+            if (LPC_C_CAN1->IF2_MCTRL & IF_MCTRL_MSGLST_Msk) {
+              CAN_SignalObjectEvent[1](obj_idx, ARM_CAN_EVENT_RECEIVE | ARM_CAN_EVENT_RECEIVE_OVERRUN);
+            } else {
+              CAN_SignalObjectEvent[1](obj_idx, ARM_CAN_EVENT_RECEIVE);
+            }
+            break;
+          case ARM_CAN_OBJ_RX_RTR_TX_DATA:
+            CAN_SignalObjectEvent[1](obj_idx, ARM_CAN_EVENT_SEND_COMPLETE);
+            break;
+          case ARM_CAN_OBJ_TX_RTR_RX_DATA:
+            if (LPC_C_CAN1->IF2_MCTRL & IF_MCTRL_NEWDAT_Msk) {
+              if (LPC_C_CAN1->IF2_MCTRL & IF_MCTRL_MSGLST_Msk) {
+                CAN_SignalObjectEvent[1](obj_idx, ARM_CAN_EVENT_RECEIVE | ARM_CAN_EVENT_RECEIVE_OVERRUN);
+              } else {
+                CAN_SignalObjectEvent[1](obj_idx, ARM_CAN_EVENT_RECEIVE);
+              }
+          }
+          break;
+        default:
+          break;
+      }
+    }
+    } else if (obj_idx == 0x8000U) {            // Status interrupt
+      stat = LPC_C_CAN1->STAT;
+      if (CAN_SignalUnitEvent[1] != NULL) { 
+        if ((stat ^ can_stat_last[1]) & (STAT_BOFF_Msk | STAT_EPASS_Msk | STAT_EWARN_Msk)) {
+          if      (stat & (stat ^ can_stat_last[1]) & STAT_BOFF_Msk )        { CAN_SignalUnitEvent[1](ARM_CAN_EVENT_UNIT_BUS_OFF); }
+          else if (stat & (stat ^ can_stat_last[1]) & STAT_EPASS_Msk)        { CAN_SignalUnitEvent[1](ARM_CAN_EVENT_UNIT_PASSIVE); }
+          else if (stat & (stat ^ can_stat_last[1]) & STAT_EWARN_Msk)        { CAN_SignalUnitEvent[1](ARM_CAN_EVENT_UNIT_WARNING); }
+          else if (stat & (STAT_BOFF_Msk | STAT_EPASS_Msk | STAT_EWARN_Msk)) { CAN_SignalUnitEvent[1](ARM_CAN_EVENT_UNIT_ACTIVE);  }
+          can_stat_last[1] = stat;
+        }
+}
+    }
+  }
+}
+#endif
+
+
+#if (RTE_CAN_CAN0 == 1U)
+ARM_DRIVER_CAN Driver_CAN0 = {
+  CAN_GetVersion,
+  CAN0_GetCapabilities,
+  CAN0_Initialize,
+  CAN0_Uninitialize,
+  CAN0_PowerControl,
+  CAN_GetClock,
+  CAN0_SetBitrate,
+  CAN0_SetMode,
+  CAN0_ObjectGetCapabilities,
+  CAN0_ObjectSetFilter,
+  CAN0_ObjectConfigure,
+  CAN0_MessageSend,
+  CAN0_MessageRead,
+  CAN0_Control,
+  CAN0_GetStatus
+};
+#endif
+
+#if (RTE_CAN_CAN1 == 1U)
+ARM_DRIVER_CAN Driver_CAN1 = {
+  CAN_GetVersion,
+  CAN1_GetCapabilities,
+  CAN1_Initialize,
+  CAN1_Uninitialize,
+  CAN1_PowerControl,
+  CAN_GetClock,
+  CAN1_SetBitrate,
+  CAN1_SetMode,
+  CAN1_ObjectGetCapabilities,
+  CAN1_ObjectSetFilter,
+  CAN1_ObjectConfigure,
+  CAN1_MessageSend,
+  CAN1_MessageRead,
+  CAN1_Control,
+  CAN1_GetStatus
+};
+#endif

CMSIS/Pack/Example/CMSIS_Driver/CAN_LPC18xx.h

@@ -0,0 +1,137 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        02. March 2016
+ * $Revision:    V1.0
+ *
+ * Project:      CAN Driver Definitions for NXP LPC18xx
+ * -------------------------------------------------------------------------- */
+
+#ifndef __CAN_LPC18XX_H
+#define __CAN_LPC18XX_H
+
+#include <stdint.h>
+#include <string.h>
+
+#include "Driver_CAN.h"
+
+#include "LPC18xx.h"
+#include "SCU_LPC18xx.h"
+
+#include "RTE_Device.h"
+#include "RTE_Components.h"
+
+#ifndef RTE_CAN_CAN0
+#define RTE_CAN_CAN0                   (0U)
+#endif
+#ifndef RTE_CAN_CAN1
+#define RTE_CAN_CAN1                   (0U)
+#endif
+
+#if   ((RTE_CAN_CAN0 == 0U) && (RTE_CAN_CAN1 == 0U))
+#error "No CAN is enabled in the RTE_Device.h!"
+#endif
+
+#if    (RTE_CAN_CAN1 == 1U)
+#define CAN_CTRL_NUM                   (2U)
+#else
+#define CAN_CTRL_NUM                   (1U)
+#endif
+
+// CNTL register bit definitions
+#define CNTL_INIT_Msk                  (1U      <<  0)
+#define CNTL_IE_Msk                    (1U      <<  1)
+#define CNTL_SIE_Msk                   (1U      <<  2)
+#define CNTL_EIE_Msk                   (1U      <<  3)
+#define CNTL_DAR_Msk                   (1U      <<  5)
+#define CNTL_CCE_Msk                   (1U      <<  6)
+#define CNTL_TEST_Msk                  (1U      <<  7)
+
+// STAT register bit definitions
+#define STAT_LEC_Msk                   (7U      <<  0)
+#define STAT_TXOK_Msk                  (1U      <<  3)
+#define STAT_RXOK_Msk                  (1U      <<  4)
+#define STAT_EPASS_Msk                 (1U      <<  5)
+#define STAT_EWARN_Msk                 (1U      <<  6)
+#define STAT_BOFF_Msk                  (1U      <<  7)
+
+// EC register bit definitions
+#define EC_TEC_7_0_Msk                 (0xFFU   <<  0)
+#define EC_REC_6_0_Msk                 (0x7FU   <<  8)
+#define EC_RP_Msk                      (1U      << 15)
+
+// BT register bit definitions
+#define BT_BRP_Msk                     (0x3FU   <<  0)
+#define BT_SJW_Msk                     (3U      <<  6)
+#define BT_TSEG1_Msk                   (0x0FU   <<  8)
+#define BT_TSEG2_Msk                   (0x07U   << 12)
+
+// TEST register bit definitions
+#define TEST_BASIC_Msk                 (1U      <<  2)
+#define TEST_SILENT_Msk                (1U      <<  3)
+#define TEST_LBACK_Msk                 (1U      <<  4)
+#define TEST_TX1_0_Msk                 (3U      <<  5)
+#define TEST_RX_Msk                    (1U      <<  7)
+
+// BRPE register bit definitions
+#define BRPE_BRPE_Msk                  (0x0FU   <<  0)
+
+// CMDREQ register bit definitions
+#define IF_CMDREQ_MESSABE_NUMBER_Msk   (0x3FU   <<  0)
+#define IF_CMDREQ_BUSY_Msk             (1U      << 15)
+
+// CMDMSK_W/R register bit definitions
+#define IF_CMDMSK_DATA_B_Msk           (1U      <<  0)
+#define IF_CMDMSK_DATA_A_Msk           (1U      <<  1)
+#define IF_CMDMSK_TXRQST_Msk           (1U      <<  2)
+#define IF_CMDMSK_NEWDAT_Msk           (1U      <<  2)
+#define IF_CMDMSK_CLRINTPND_Msk        (1U      <<  3)
+#define IF_CMDMSK_CTRL_Msk             (1U      <<  4)
+#define IF_CMDMSK_ARB_Msk              (1U      <<  5)
+#define IF_CMDMSK_MASK_Msk             (1U      <<  6)
+#define IF_CMDMSK_WR_RD_Msk            (1U      <<  7)
+
+// MSK1 register bit definitions
+#define IF_MSK1_MSK15_0_Msk            (0xFFFFU <<  0)
+
+// MSK2 register bit definitions
+#define IF_MSK2_MSK28_16_Msk           (0x1FFFU <<  0)
+#define IF_MSK2_MDIR_Msk               (1U      << 14)
+#define IF_MSK2_MXTD_Msk               (1U      << 15)
+
+// ARB1 register bit definitions
+#define IF_ARB1_ID15_0_Msk             (0xFFFFU <<  0)
+
+// ARB2 register bit definitions
+#define IF_ARB2_ID28_16_Msk            (0x1FFFU <<  0)
+#define IF_ARB2_DIR_Msk                (1U      << 13)
+#define IF_ARB2_XTD_Msk                (1U      << 14)
+#define IF_ARB2_MSGVAL_Msk             (1U      << 15)
+
+// MCTRL register bit definitions
+#define IF_MCTRL_DLC3_0_Msk            (0x0FU   <<  0)
+#define IF_MCTRL_EOB_Msk               (1U      <<  7)
+#define IF_MCTRL_TXRQST_Msk            (1U      <<  8)
+#define IF_MCTRL_RMTEN_Msk             (1U      <<  9)
+#define IF_MCTRL_RXIE_Msk              (1U      << 10)
+#define IF_MCTRL_TXIE_Msk              (1U      << 11)
+#define IF_MCTRL_UMASK_Msk             (1U      << 12)
+#define IF_MCTRL_INTPND_Msk            (1U      << 13)
+#define IF_MCTRL_MSGLST_Msk            (1U      << 14)
+#define IF_MCTRL_NEWDAT_Msk            (1U      << 15)
+
+#endif // __CAN_LPC18XX_H

CMSIS/Pack/Example/CMSIS_Driver/Config/RTE_Device.h

@@ -0,0 +1,2356 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        02. March 2016
+ * $Revision:    V2.2.0
+ *
+ * Project:      RTE Device Configuration for NXP LPC18xx
+ * -------------------------------------------------------------------------- */
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+#ifndef __RTE_DEVICE_H
+#define __RTE_DEVICE_H
+
+
+// <e> USB0 Controller [Driver_USBD0 and Driver_USBH0]
+// <i> Configuration settings for Driver_USBD0 in component ::Drivers:USB Device
+// <i> Configuration settings for Driver_USBH0 in component ::Drivers:USB Host
+#define   RTE_USB_USB0                  0
+
+//   <h> Pin Configuration
+//     <o> USB0_PPWR (Host) <0=>Not used <1=>P1_7 <2=>P2_0 <3=>P2_3 <4=>P6_3
+//     <i> VBUS drive signal (towards external charge pump or power management unit).
+#define   RTE_USB0_PPWR_ID              1
+#if      (RTE_USB0_PPWR_ID == 0)
+  #define RTE_USB0_PPWR_PIN_EN          0
+#elif    (RTE_USB0_PPWR_ID == 1)
+  #define RTE_USB0_PPWR_PORT            1
+  #define RTE_USB0_PPWR_BIT             7
+  #define RTE_USB0_PPWR_FUNC            4
+#elif    (RTE_USB0_PPWR_ID == 2)
+  #define RTE_USB0_PPWR_PORT            2
+  #define RTE_USB0_PPWR_BIT             0
+  #define RTE_USB0_PPWR_FUNC            3
+#elif    (RTE_USB0_PPWR_ID == 3)
+  #define RTE_USB0_PPWR_PORT            2
+  #define RTE_USB0_PPWR_BIT             3
+  #define RTE_USB0_PPWR_FUNC            7
+#elif    (RTE_USB0_PPWR_ID == 4)
+  #define RTE_USB0_PPWR_PORT            6
+  #define RTE_USB0_PPWR_BIT             3
+  #define RTE_USB0_PPWR_FUNC            1
+#else
+  #error "Invalid RTE_USB0_PPWR Pin Configuration!"
+#endif
+#ifndef   RTE_USB0_PPWR_PIN_EN
+  #define RTE_USB0_PPWR_PIN_EN          1
+#endif
+//     <o> USB0_PWR_FAULT (Host) <0=>Not used <1=>P1_5 <2=>P2_1 <3=>P2_4 <4=>P6_6 <5=>P8_0
+//     <i> Port power fault signal indicating overcurrent condition.
+//     <i> This signal monitors over-current on the USB bus
+//        (external circuitry required to detect over-current condition).
+#define   RTE_USB0_PWR_FAULT_ID         1
+#if      (RTE_USB0_PWR_FAULT_ID == 0)
+  #define RTE_USB0_PWR_FAULT_PIN_EN     0
+#elif    (RTE_USB0_PWR_FAULT_ID == 1)
+  #define RTE_USB0_PWR_FAULT_PORT       1
+  #define RTE_USB0_PWR_FAULT_BIT        5
+  #define RTE_USB0_PWR_FAULT_FUNC       4
+#elif    (RTE_USB0_PWR_FAULT_ID == 2)
+  #define RTE_USB0_PWR_FAULT_PORT       2
+  #define RTE_USB0_PWR_FAULT_BIT        1
+  #define RTE_USB0_PWR_FAULT_FUNC       3
+#elif    (RTE_USB0_PWR_FAULT_ID == 3)
+  #define RTE_USB0_PWR_FAULT_PORT       2
+  #define RTE_USB0_PWR_FAULT_BIT        4
+  #define RTE_USB0_PWR_FAULT_FUNC       7
+#elif    (RTE_USB0_PWR_FAULT_ID == 4)
+  #define RTE_USB0_PWR_FAULT_PORT       6
+  #define RTE_USB0_PWR_FAULT_BIT        6
+  #define RTE_USB0_PWR_FAULT_FUNC       3
+#elif    (RTE_USB0_PWR_FAULT_ID == 5)
+  #define RTE_USB0_PWR_FAULT_PORT       8
+  #define RTE_USB0_PWR_FAULT_BIT        0
+  #define RTE_USB0_PWR_FAULT_FUNC       1
+#else
+  #error "Invalid RTE_USB0_PWR_FAULT Pin Configuration!"
+#endif
+#ifndef   RTE_USB0_PWR_FAULT_PIN_EN
+  #define RTE_USB0_PWR_FAULT_PIN_EN     1
+#endif
+//     <o> USB0_IND0 <0=>Not used <1=>P1_4 <2=>P2_5 <3=>P2_6 <4=>P6_8 <5=>P8_2
+//     <i> USB0 port indicator LED control output 0
+#define   RTE_USB0_IND0_ID              1
+#if      (RTE_USB0_IND0_ID == 0)
+  #define RTE_USB0_IND0_PIN_EN          0
+#elif    (RTE_USB0_IND0_ID == 1)
+  #define RTE_USB0_IND0_PORT            1
+  #define RTE_USB0_IND0_BIT             4
+  #define RTE_USB0_IND0_FUNC            4
+#elif    (RTE_USB0_IND0_ID == 2)
+  #define RTE_USB0_IND0_PORT            2
+  #define RTE_USB0_IND0_BIT             5
+  #define RTE_USB0_IND0_FUNC            7
+#elif    (RTE_USB0_IND0_ID == 3)
+  #define RTE_USB0_IND0_PORT            2
+  #define RTE_USB0_IND0_BIT             6
+  #define RTE_USB0_IND0_FUNC            3
+#elif    (RTE_USB0_IND0_ID == 4)
+  #define RTE_USB0_IND0_PORT            6
+  #define RTE_USB0_IND0_BIT             8
+  #define RTE_USB0_IND0_FUNC            3
+#elif    (RTE_USB0_IND0_ID == 5)
+  #define RTE_USB0_IND0_PORT            8
+  #define RTE_USB0_IND0_BIT             2
+  #define RTE_USB0_IND0_FUNC            1
+#else
+  #error "Invalid RTE_USB0_IND0 Pin Configuration!"
+#endif
+#ifndef   RTE_USB0_IND0_PIN_EN
+  #define RTE_USB0_IND0_PIN_EN          1
+#endif
+//     <o> USB0_IND1 <0=>Not used <1=>P1_3 <2=>P2_2 <3=>P6_7 <4=>P8_1
+//     <i> USB0 port indicator LED control output 1
+#define   RTE_USB0_IND1_ID              1
+#if      (RTE_USB0_IND1_ID == 0)
+  #define RTE_USB0_IND1_PIN_EN          0
+#elif    (RTE_USB0_IND1_ID == 1)
+  #define RTE_USB0_IND1_PORT            1
+  #define RTE_USB0_IND1_BIT             3
+  #define RTE_USB0_IND1_FUNC            4
+#elif    (RTE_USB0_IND1_ID == 2)
+  #define RTE_USB0_IND1_PORT            2
+  #define RTE_USB0_IND1_BIT             2
+  #define RTE_USB0_IND1_FUNC            3
+#elif    (RTE_USB0_IND1_ID == 3)
+  #define RTE_USB0_IND1_PORT            6
+  #define RTE_USB0_IND1_BIT             7
+  #define RTE_USB0_IND1_FUNC            3
+#elif    (RTE_USB0_IND1_ID == 4)
+  #define RTE_USB0_IND1_PORT            8
+  #define RTE_USB0_IND1_BIT             1
+  #define RTE_USB0_IND1_FUNC            1
+#else
+  #error "Invalid RTE_USB0_IND1 Pin Configuration!"
+#endif
+#ifndef   RTE_USB0_IND1_PIN_EN
+  #define RTE_USB0_IND1_PIN_EN          1
+#endif
+//   </h> Pin Configuration
+
+//   <h> Device [Driver_USBD0]
+//   <i> Configuration settings for Driver_USBD0 in component ::Drivers:USB Device
+//     <o.0> High-speed
+//     <i> Enable high-speed functionality
+#define   RTE_USB_USB0_HS_EN            0
+//   </h> Device [Driver_USBD0]
+// </e> USB0 Controller [Driver_USBD0 and Driver_USBH0]
+
+// <e> USB1 Controller [Driver_USBD1 and Driver_USBH1]
+// <i> Configuration settings for Driver_USBD1 in component ::Drivers:USB Device
+// <i> Configuration settings for Driver_USBH1 in component ::Drivers:USB Host
+#define   RTE_USB_USB1                  0
+
+//   <h> Pin Configuration
+//     <o> USB1_PPWR (Host) <0=>Not used <1=>P9_5
+//     <i> VBUS drive signal (towards external charge pump or power management unit).
+#define   RTE_USB1_PPWR_ID              1
+#if      (RTE_USB1_PPWR_ID == 0)
+  #define RTE_USB1_PPWR_PIN_EN          0
+#elif    (RTE_USB1_PPWR_ID == 1)
+  #define RTE_USB1_PPWR_PORT            9
+  #define RTE_USB1_PPWR_BIT             5
+  #define RTE_USB1_PPWR_FUNC            2
+#else
+  #error "Invalid RTE_USB1_PPWR Pin Configuration!"
+#endif
+#ifndef   RTE_USB1_PPWR_PIN_EN
+  #define RTE_USB1_PPWR_PIN_EN          1
+#endif
+//     <o> USB1_PWR_FAULT (Host) <0=>Not used <1=>P9_6
+//     <i> Port power fault signal indicating overcurrent condition.
+//     <i> This signal monitors over-current on the USB bus
+//        (external circuitry required to detect over-current condition).
+#define   RTE_USB1_PWR_FAULT_ID         1
+#if      (RTE_USB1_PWR_FAULT_ID == 0)
+  #define RTE_USB1_PWR_FAULT_PIN_EN     0
+#elif    (RTE_USB1_PWR_FAULT_ID == 1)
+  #define RTE_USB1_PWR_FAULT_PORT       9
+  #define RTE_USB1_PWR_FAULT_BIT        6
+  #define RTE_USB1_PWR_FAULT_FUNC       2
+#else
+  #error "Invalid RTE_USB1_PWR_FAULT Pin Configuration!"
+#endif
+#ifndef   RTE_USB1_PWR_FAULT_PIN_EN
+  #define RTE_USB1_PWR_FAULT_PIN_EN     1
+#endif
+//     <o> USB1_IND0 <0=>Not used <1=>P3_2 <2=>P9_4
+//     <i> USB1 port indicator LED control output 0
+#define   RTE_USB1_IND0_ID              1
+#if      (RTE_USB1_IND0_ID == 0)
+  #define RTE_USB1_IND0_PIN_EN          0
+#elif    (RTE_USB1_IND0_ID == 1)
+  #define RTE_USB1_IND0_PORT            3
+  #define RTE_USB1_IND0_BIT             2
+  #define RTE_USB1_IND0_FUNC            3
+#elif    (RTE_USB1_IND0_ID == 2)
+  #define RTE_USB1_IND0_PORT            9
+  #define RTE_USB1_IND0_BIT             4
+  #define RTE_USB1_IND0_FUNC            2
+#else
+  #error "Invalid RTE_USB1_IND0 Pin Configuration!"
+#endif
+#ifndef   RTE_USB1_IND0_PIN_EN
+  #define RTE_USB1_IND0_PIN_EN          1
+#endif
+//     <o> USB1_IND1 <0=>Not used <1=>P3_1 <2=>P9_3
+//     <i> USB1 port indicator LED control output 1
+#define   RTE_USB1_IND1_ID              1
+#if      (RTE_USB1_IND1_ID == 0)
+  #define RTE_USB1_IND1_PIN_EN          0
+#elif    (RTE_USB1_IND1_ID == 1)
+  #define RTE_USB1_IND1_PORT            3
+  #define RTE_USB1_IND1_BIT             1
+  #define RTE_USB1_IND1_FUNC            3
+#elif    (RTE_USB1_IND1_ID == 2)
+  #define RTE_USB1_IND1_PORT            9
+  #define RTE_USB1_IND1_BIT             3
+  #define RTE_USB1_IND1_FUNC            2
+#else
+  #error "Invalid RTE_USB1_IND1 Pin Configuration!"
+#endif
+#ifndef   RTE_USB1_IND1_PIN_EN
+  #define RTE_USB1_IND1_PIN_EN          1
+#endif
+
+//     <e> On-chip full-speed PHY
+#define   RTE_USB_USB1_FS_PHY_EN        1
+
+//       <o> USB1_VBUS (Device) <0=>Not used <1=>P2_5
+//       <i> Monitors the presence of USB1 bus power.
+#define   RTE_USB1_VBUS_ID              1
+#if      (RTE_USB1_VBUS_ID == 0)
+  #define RTE_USB1_VBUS_PIN_EN          0
+#elif    (RTE_USB1_VBUS_ID == 1)
+  #define RTE_USB1_VBUS_PORT            2
+  #define RTE_USB1_VBUS_BIT             5
+  #define RTE_USB1_VBUS_FUNC            2
+#else
+  #error "Invalid RTE_USB1_VBUS Pin Configuration!"
+#endif
+#ifndef   RTE_USB1_VBUS_PIN_EN
+  #define RTE_USB1_VBUS_PIN_EN          1
+#endif
+//     </e> On-chip full-speed PHY
+
+//     <e> External high-speed ULPI PHY (UTMI+ Low Pin Interface)
+#define   RTE_USB_USB1_HS_PHY_EN        0
+
+//       <o> USB1_ULPI_CLK <0=>P8_8 <1=>PC_0
+//       <i> USB1 ULPI link CLK signal.
+//       <i> 60 MHz clock generated by the PHY.
+#define   RTE_USB1_ULPI_CLK_ID          0
+#if      (RTE_USB1_ULPI_CLK_ID == 0)
+  #define RTE_USB1_ULPI_CLK_PORT        8
+  #define RTE_USB1_ULPI_CLK_BIT         8
+  #define RTE_USB1_ULPI_CLK_FUNC        1
+#elif    (RTE_USB1_ULPI_CLK_ID == 1)
+  #define RTE_USB1_ULPI_CLK_PORT        0xC
+  #define RTE_USB1_ULPI_CLK_BIT         0
+  #define RTE_USB1_ULPI_CLK_FUNC        1
+#else
+  #error "Invalid RTE_USB1_ULPI_CLK Pin Configuration!"
+#endif
+//       <o> USB1_ULPI_DIR <0=>PB_1 <1=>PC_11
+//       <i> USB1 ULPI link DIR signal.
+//       <i> Controls the ULPI data line direction.
+#define   RTE_USB1_ULPI_DIR_ID          0
+#if      (RTE_USB1_ULPI_DIR_ID == 0)
+  #define RTE_USB1_ULPI_DIR_PORT        0xB
+  #define RTE_USB1_ULPI_DIR_BIT         1
+  #define RTE_USB1_ULPI_DIR_FUNC        1
+#elif    (RTE_USB1_ULPI_DIR_ID == 1)
+  #define RTE_USB1_ULPI_DIR_PORT        0xC
+  #define RTE_USB1_ULPI_DIR_BIT         11
+  #define RTE_USB1_ULPI_DIR_FUNC        1
+#else
+  #error "Invalid RTE_USB1_ULPI_DIR Pin Configuration!"
+#endif
+//       <o> USB1_ULPI_STP <0=>P8_7 <1=>PC_10
+//       <i> USB1 ULPI link STP signal.
+//       <i> Asserted to end or interrupt transfers to the PHY.
+#define   RTE_USB1_ULPI_STP_ID          0
+#if      (RTE_USB1_ULPI_STP_ID == 0)
+  #define RTE_USB1_ULPI_STP_PORT        8
+  #define RTE_USB1_ULPI_STP_BIT         7
+  #define RTE_USB1_ULPI_STP_FUNC        1
+#elif    (RTE_USB1_ULPI_STP_ID == 1)
+  #define RTE_USB1_ULPI_STP_PORT        0xC
+  #define RTE_USB1_ULPI_STP_BIT         10
+  #define RTE_USB1_ULPI_STP_FUNC        1
+#else
+  #error "Invalid RTE_USB1_ULPI_STP Pin Configuration!"
+#endif
+//       <o> USB1_ULPI_NXT <0=>P8_6 <1=>PC_9
+//       <i> USB1 ULPI link NXT signal.
+//       <i> Data flow control signal from the PHY.
+#define   RTE_USB1_ULPI_NXT_ID          0
+#if      (RTE_USB1_ULPI_NXT_ID == 0)
+  #define RTE_USB1_ULPI_NXT_PORT        8
+  #define RTE_USB1_ULPI_NXT_BIT         6
+  #define RTE_USB1_ULPI_NXT_FUNC        1
+#elif    (RTE_USB1_ULPI_NXT_ID == 1)
+  #define RTE_USB1_ULPI_NXT_PORT        0xC
+  #define RTE_USB1_ULPI_NXT_BIT         9
+  #define RTE_USB1_ULPI_NXT_FUNC        1
+#else
+  #error "Invalid RTE_USB1_ULPI_NXT Pin Configuration!"
+#endif
+//       <o> USB1_ULPI_D0 <0=>P8_5 <1=>PC_8 <2=>PD_11
+//       <i> USB1 ULPI link bidirectional data line 0.
+#define   RTE_USB1_ULPI_D0_ID           0
+#if      (RTE_USB1_ULPI_D0_ID == 0)
+  #define RTE_USB1_ULPI_D0_PORT         8
+  #define RTE_USB1_ULPI_D0_BIT          5
+  #define RTE_USB1_ULPI_D0_FUNC         1
+#elif    (RTE_USB1_ULPI_D0_ID == 1)
+  #define RTE_USB1_ULPI_D0_PORT         0xC
+  #define RTE_USB1_ULPI_D0_BIT          8
+  #define RTE_USB1_ULPI_D0_FUNC         1
+#elif    (RTE_USB1_ULPI_D0_ID == 2)
+  #define RTE_USB1_ULPI_D0_PORT         0xD
+  #define RTE_USB1_ULPI_D0_BIT          11
+  #define RTE_USB1_ULPI_D0_FUNC         5
+#else
+  #error "Invalid RTE_USB1_ULPI_D0 Pin Configuration!"
+#endif
+//       <o> USB1_ULPI_D1 <0=>P8_4 <1=>PC_7
+//       <i> USB1 ULPI link bidirectional data line 1.
+#define   RTE_USB1_ULPI_D1_ID           0
+#if      (RTE_USB1_ULPI_D1_ID == 0)
+  #define RTE_USB1_ULPI_D1_PORT         8
+  #define RTE_USB1_ULPI_D1_BIT          4
+  #define RTE_USB1_ULPI_D1_FUNC         1
+#elif    (RTE_USB1_ULPI_D1_ID == 1)
+  #define RTE_USB1_ULPI_D1_PORT         0xC
+  #define RTE_USB1_ULPI_D1_BIT          7
+  #define RTE_USB1_ULPI_D1_FUNC         1
+#else
+  #error "Invalid RTE_USB1_ULPI_D1 Pin Configuration!"
+#endif
+//       <o> USB1_ULPI_D2 <0=>P8_3 <1=>PC_6
+//       <i> USB1 ULPI link bidirectional data line 2.
+#define   RTE_USB1_ULPI_D2_ID           0
+#if      (RTE_USB1_ULPI_D2_ID == 0)
+  #define RTE_USB1_ULPI_D2_PORT         8
+  #define RTE_USB1_ULPI_D2_BIT          3
+  #define RTE_USB1_ULPI_D2_FUNC         1
+#elif    (RTE_USB1_ULPI_D2_ID == 1)
+  #define RTE_USB1_ULPI_D2_PORT         0xC
+  #define RTE_USB1_ULPI_D2_BIT          6
+  #define RTE_USB1_ULPI_D2_FUNC         1
+#else
+  #error "Invalid RTE_USB1_ULPI_D2 Pin Configuration!"
+#endif
+//       <o> USB1_ULPI_D3 <0=>PB_6 <1=>PC_5
+//       <i> USB1 ULPI link bidirectional data line 3.
+#define   RTE_USB1_ULPI_D3_ID           0
+#if      (RTE_USB1_ULPI_D3_ID == 0)
+  #define RTE_USB1_ULPI_D3_PORT         0xB
+  #define RTE_USB1_ULPI_D3_BIT          6
+  #define RTE_USB1_ULPI_D3_FUNC         1
+#elif    (RTE_USB1_ULPI_D3_ID == 1)
+  #define RTE_USB1_ULPI_D3_PORT         0xC
+  #define RTE_USB1_ULPI_D3_BIT          5
+  #define RTE_USB1_ULPI_D3_FUNC         1
+#else
+  #error "Invalid RTE_USB1_ULPI_D3 Pin Configuration!"
+#endif
+//       <o> USB1_ULPI_D4 <0=>PB_5 <1=>PC_4
+//       <i> USB1 ULPI link bidirectional data line 4.
+#define   RTE_USB1_ULPI_D4_ID           0
+#if      (RTE_USB1_ULPI_D4_ID == 0)
+  #define RTE_USB1_ULPI_D4_PORT         0xB
+  #define RTE_USB1_ULPI_D4_BIT          5
+  #define RTE_USB1_ULPI_D4_FUNC         1
+#elif    (RTE_USB1_ULPI_D4_ID == 1)
+  #define RTE_USB1_ULPI_D4_PORT         0xC
+  #define RTE_USB1_ULPI_D4_BIT          4
+  #define RTE_USB1_ULPI_D4_FUNC         1
+#else
+  #error "Invalid RTE_USB1_ULPI_D4 Pin Configuration!"
+#endif
+//       <o> USB1_ULPI_D5 <0=>PB_4 <1=>PC_3
+//       <i> USB1 ULPI link bidirectional data line 5.
+#define   RTE_USB1_ULPI_D5_ID           0
+#if      (RTE_USB1_ULPI_D5_ID == 0)
+  #define RTE_USB1_ULPI_D5_PORT         0xB
+  #define RTE_USB1_ULPI_D5_BIT          4
+  #define RTE_USB1_ULPI_D5_FUNC         1
+#elif    (RTE_USB1_ULPI_D5_ID == 1)
+  #define RTE_USB1_ULPI_D5_PORT         0xC
+  #define RTE_USB1_ULPI_D5_BIT          3
+  #define RTE_USB1_ULPI_D5_FUNC         0
+#else
+  #error "Invalid RTE_USB1_ULPI_D5 Pin Configuration!"
+#endif
+//       <o> USB1_ULPI_D6 <0=>PB_3 <1=>PC_2
+//       <i> USB1 ULPI link bidirectional data line 6.
+#define   RTE_USB1_ULPI_D6_ID           0
+#if      (RTE_USB1_ULPI_D6_ID == 0)
+  #define RTE_USB1_ULPI_D6_PORT         0xB
+  #define RTE_USB1_ULPI_D6_BIT          3
+  #define RTE_USB1_ULPI_D6_FUNC         1
+#elif    (RTE_USB1_ULPI_D6_ID == 1)
+  #define RTE_USB1_ULPI_D6_PORT         0xC
+  #define RTE_USB1_ULPI_D6_BIT          2
+  #define RTE_USB1_ULPI_D6_FUNC         0
+#else
+  #error "Invalid RTE_USB1_ULPI_D6 Pin Configuration!"
+#endif
+//       <o> USB1_ULPI_D7 <0=>PB_2 <1=>PC_1
+//       <i> USB1 ULPI link bidirectional data line 7.
+#define   RTE_USB1_ULPI_D7_ID           0
+#if      (RTE_USB1_ULPI_D7_ID == 0)
+  #define RTE_USB1_ULPI_D7_PORT         0xB
+  #define RTE_USB1_ULPI_D7_BIT          2
+  #define RTE_USB1_ULPI_D7_FUNC         1
+#elif    (RTE_USB1_ULPI_D7_ID == 1)
+  #define RTE_USB1_ULPI_D7_PORT         0xC
+  #define RTE_USB1_ULPI_D7_BIT          1
+  #define RTE_USB1_ULPI_D7_FUNC         0
+#else
+  #error "Invalid RTE_USB1_ULPI_D7 Pin Configuration!"
+#endif
+//     </e> External high-speed ULPI PHY (UTMI+ Low Pin Interface)
+//   </h> Pin Configuration
+// </e> USB1 Controller [Driver_USBD1 and Driver_USBH1]
+
+// <e> ENET (Ethernet Interface) [Driver_ETH_MAC0]
+// <i> Configuration settings for Driver_ETH_MAC0 in component ::Drivers:Ethernet MAC
+#define   RTE_ENET                      0
+
+//   <e> MII (Media Independent Interface)
+#define   RTE_ENET_MII                  0
+
+//     <o> ENET_TXD0 Pin <0=>P1_18
+#define   RTE_ENET_MII_TXD0_PORT_ID     0
+#if      (RTE_ENET_MII_TXD0_PORT_ID == 0)
+  #define RTE_ENET_MII_TXD0_PORT        1
+  #define RTE_ENET_MII_TXD0_PIN         18
+  #define RTE_ENET_MII_TXD0_FUNC        3
+#else
+  #error "Invalid ENET_TXD0 Pin Configuration!"
+#endif
+//     <o> ENET_TXD1 Pin <0=>P1_20
+#define   RTE_ENET_MII_TXD1_PORT_ID     0
+#if      (RTE_ENET_MII_TXD1_PORT_ID == 0)
+  #define RTE_ENET_MII_TXD1_PORT        1
+  #define RTE_ENET_MII_TXD1_PIN         20
+  #define RTE_ENET_MII_TXD1_FUNC        3
+#else
+  #error "Invalid ENET_TXD1 Pin Configuration!"
+#endif
+//     <o> ENET_TXD2 Pin <0=>P9_4 <1=>PC_2
+#define   RTE_ENET_MII_TXD2_PORT_ID     0
+#if      (RTE_ENET_MII_TXD2_PORT_ID == 0)
+  #define RTE_ENET_MII_TXD2_PORT        9
+  #define RTE_ENET_MII_TXD2_PIN         4
+  #define RTE_ENET_MII_TXD2_FUNC        5
+#elif    (RTE_ENET_MII_TXD2_PORT_ID == 1)
+  #define RTE_ENET_MII_TXD2_PORT        0xC
+  #define RTE_ENET_MII_TXD2_PIN         2
+  #define RTE_ENET_MII_TXD2_FUNC        3
+#else
+  #error "Invalid ENET_TXD2 Pin Configuration!"
+#endif
+//     <o> ENET_TXD3 Pin <0=>P9_5 <1=>PC_3
+#define   RTE_ENET_MII_TXD3_PORT_ID     0
+#if      (RTE_ENET_MII_TXD3_PORT_ID == 0)
+  #define RTE_ENET_MII_TXD3_PORT        9
+  #define RTE_ENET_MII_TXD3_PIN         5
+  #define RTE_ENET_MII_TXD3_FUNC        5
+#elif    (RTE_ENET_MII_TXD3_PORT_ID == 1)
+  #define RTE_ENET_MII_TXD3_PORT        0xC
+  #define RTE_ENET_MII_TXD3_PIN         3
+  #define RTE_ENET_MII_TXD3_FUNC        3
+#else
+  #error "Invalid ENET_TXD3 Pin Configuration!"
+#endif
+//     <o> ENET_TX_EN Pin <0=>P0_1 <1=>PC_4
+#define   RTE_ENET_MII_TX_EN_PORT_ID    0
+#if      (RTE_ENET_MII_TX_EN_PORT_ID == 0)
+  #define RTE_ENET_MII_TX_EN_PORT       0
+  #define RTE_ENET_MII_TX_EN_PIN        1
+  #define RTE_ENET_MII_TX_EN_FUNC       6
+#elif    (RTE_ENET_MII_TX_EN_PORT_ID == 1)
+  #define RTE_ENET_MII_TX_EN_PORT       0xC
+  #define RTE_ENET_MII_TX_EN_PIN        4
+  #define RTE_ENET_MII_TX_EN_FUNC       3
+#else
+  #error "Invalid ENET_TX_EN Pin Configuration!"
+#endif
+//     <o> ENET_TX_CLK Pin <0=>P1_19 <1=>CLK0
+#define   RTE_ENET_MII_TX_CLK_PORT_ID   0
+#if      (RTE_ENET_MII_TX_CLK_PORT_ID == 0)
+  #define RTE_ENET_MII_TX_CLK_PORT      1
+  #define RTE_ENET_MII_TX_CLK_PIN       19
+  #define RTE_ENET_MII_TX_CLK_FUNC      0
+#elif    (RTE_ENET_MII_TX_CLK_PORT_ID == 1)
+  #define RTE_ENET_MII_TX_CLK_PORT      0x10
+  #define RTE_ENET_MII_TX_CLK_PIN       0
+  #define RTE_ENET_MII_TX_CLK_FUNC      7
+#else
+  #error "Invalid ENET_TX_CLK Pin Configuration!"
+#endif
+//     <o> ENET_TX_ER Pin <0=>Not used <1=>PC_5 <2=>PC_14
+//     <i> Optional signal, rarely used
+#define   RTE_ENET_MII_TX_ER_PORT_ID    0
+#if      (RTE_ENET_MII_TX_ER_PORT_ID == 0)
+  #define RTE_ENET_MII_TX_ER_PIN_EN     0
+#elif    (RTE_ENET_MII_TX_ER_PORT_ID == 1)
+  #define RTE_ENET_MII_TX_ER_PORT       0xC
+  #define RTE_ENET_MII_TX_ER_PIN        5
+  #define RTE_ENET_MII_TX_ER_FUNC       3
+#elif    (RTE_ENET_MII_TX_ER_PORT_ID == 2)
+  #define RTE_ENET_MII_TX_ER_PORT       0xC
+  #define RTE_ENET_MII_TX_ER_PIN        14
+  #define RTE_ENET_MII_TX_ER_FUNC       6
+#else
+  #error "Invalid ENET_TX_ER Pin Configuration!"
+#endif
+#ifndef   RTE_ENET_MII_TX_ER_PIN_EN
+  #define RTE_ENET_MII_TX_ER_PIN_EN     1
+#endif
+//     <o> ENET_RXD0 Pin <0=>P1_15
+#define   RTE_ENET_MII_RXD0_PORT_ID     0
+#if      (RTE_ENET_MII_RXD0_PORT_ID == 0)
+  #define RTE_ENET_MII_RXD0_PORT        1
+  #define RTE_ENET_MII_RXD0_PIN         15
+  #define RTE_ENET_MII_RXD0_FUNC        3
+#else
+  #error "Invalid ENET_RXD0 Pin Configuration!"
+#endif
+//     <o> ENET_RXD1 Pin <0=>P0_0
+#define   RTE_ENET_MII_RXD1_PORT_ID     0
+#if      (RTE_ENET_MII_RXD1_PORT_ID == 0)
+  #define RTE_ENET_MII_RXD1_PORT        0
+  #define RTE_ENET_MII_RXD1_PIN         0
+  #define RTE_ENET_MII_RXD1_FUNC        2
+#else
+  #error "Invalid ENET_RXD1 Pin Configuration!"
+#endif
+//     <o> ENET_RXD2 Pin <0=>P9_3 <1=>PC_6
+#define   RTE_ENET_MII_RXD2_PORT_ID     0
+#if      (RTE_ENET_MII_RXD2_PORT_ID == 0)
+  #define RTE_ENET_MII_RXD2_PORT        9
+  #define RTE_ENET_MII_RXD2_PIN         3
+  #define RTE_ENET_MII_RXD2_FUNC        5
+#elif    (RTE_ENET_MII_RXD2_PORT_ID == 1)
+  #define RTE_ENET_MII_RXD2_PORT        0xC
+  #define RTE_ENET_MII_RXD2_PIN         6
+  #define RTE_ENET_MII_RXD2_FUNC        3
+#else
+  #error "Invalid ENET_RXD2 Pin Configuration!"
+#endif
+//     <o> ENET_RXD3 Pin <0=>P9_2 <1=>PC_7
+#define   RTE_ENET_MII_RXD3_PORT_ID     0
+#if      (RTE_ENET_MII_RXD3_PORT_ID == 0)
+  #define RTE_ENET_MII_RXD3_PORT        9
+  #define RTE_ENET_MII_RXD3_PIN         2
+  #define RTE_ENET_MII_RXD3_FUNC        5
+#elif    (RTE_ENET_MII_RXD3_PORT_ID == 1)
+  #define RTE_ENET_MII_RXD3_PORT        0xC
+  #define RTE_ENET_MII_RXD3_PIN         7
+  #define RTE_ENET_MII_RXD3_FUNC        3
+#else
+  #error "Invalid ENET_RXD3 Pin Configuration!"
+#endif
+//     <o> ENET_RX_DV Pin <0=>P1_16 <1=>PC_8
+#define   RTE_ENET_MII_RX_DV_PORT_ID    0
+#if      (RTE_ENET_MII_RX_DV_PORT_ID == 0)
+  #define RTE_ENET_MII_RX_DV_PORT       1
+  #define RTE_ENET_MII_RX_DV_PIN        16
+  #define RTE_ENET_MII_RX_DV_FUNC       7
+#elif    (RTE_ENET_MII_RX_DV_PORT_ID == 1)
+  #define RTE_ENET_MII_RX_DV_PORT       0xC
+  #define RTE_ENET_MII_RX_DV_PIN        8
+  #define RTE_ENET_MII_RX_DV_FUNC       3
+#else
+  #error "Invalid ENET_RX_DV Pin Configuration!"
+#endif
+//     <o> ENET_RX_CLK Pin <0=>PC_0
+#define   RTE_ENET_MII_RX_CLK_PORT_ID   0
+#if      (RTE_ENET_MII_RX_CLK_PORT_ID == 0)
+  #define RTE_ENET_MII_RX_CLK_PORT      0xC
+  #define RTE_ENET_MII_RX_CLK_PIN       0
+  #define RTE_ENET_MII_RX_CLK_FUNC      3
+#else
+  #error "Invalid ENET_RX_CLK Pin Configuration!"
+#endif
+//     <o> ENET_RX_ER Pin <0=>P9_1 <1=>PC_9
+#define   RTE_ENET_MII_RX_ER_PORT_ID    0
+#if      (RTE_ENET_MII_RX_ER_PORT_ID == 0)
+  #define RTE_ENET_MII_RX_ER_PORT       9
+  #define RTE_ENET_MII_RX_ER_PIN        1
+  #define RTE_ENET_MII_RX_ER_FUNC       5
+#elif    (RTE_ENET_MII_RX_ER_PORT_ID == 1)
+  #define RTE_ENET_MII_RX_ER_PORT       0xC
+  #define RTE_ENET_MII_RX_ER_PIN        9
+  #define RTE_ENET_MII_RX_ER_FUNC       3
+#else
+  #error "Invalid ENET_RX_ER Pin Configuration!"
+#endif
+//     <o> ENET_COL Pin <0=>P0_1 <1=>P4_1 <2=>P9_6
+#define   RTE_ENET_MII_COL_PORT_ID      0
+#if      (RTE_ENET_MII_COL_PORT_ID == 0)
+  #define RTE_ENET_MII_COL_PORT         0
+  #define RTE_ENET_MII_COL_PIN          1
+  #define RTE_ENET_MII_COL_FUNC         2
+#elif    (RTE_ENET_MII_COL_PORT_ID == 1)
+  #define RTE_ENET_MII_COL_PORT         4
+  #define RTE_ENET_MII_COL_PIN          1
+  #define RTE_ENET_MII_COL_FUNC         7
+#elif    (RTE_ENET_MII_COL_PORT_ID == 2)
+  #define RTE_ENET_MII_COL_PORT         9
+  #define RTE_ENET_MII_COL_PIN          6
+  #define RTE_ENET_MII_COL_FUNC         5
+#else
+  #error "Invalid ENET_COL Pin Configuration!"
+#endif
+//     <o> ENET_CRS Pin <0=>P1_16 <1=>P9_0
+#define   RTE_ENET_MII_CRS_PORT_ID      0
+#if      (RTE_ENET_MII_CRS_PORT_ID == 0)
+  #define RTE_ENET_MII_CRS_PORT         1
+  #define RTE_ENET_MII_CRS_PIN          16
+  #define RTE_ENET_MII_CRS_FUNC         3
+#elif    (RTE_ENET_MII_CRS_PORT_ID == 1)
+  #define RTE_ENET_MII_CRS_PORT         9
+  #define RTE_ENET_MII_CRS_PIN          0
+  #define RTE_ENET_MII_CRS_FUNC         5
+#else
+  #error "Invalid ENET_CRS Pin Configuration!"
+#endif
+//   </e> MII (Media Independent Interface)
+
+//   <e> RMII (Reduced Media Independent Interface)
+#define   RTE_ENET_RMII                 0
+
+//     <o> ENET_TXD0 Pin <0=>P1_18
+#define   RTE_ENET_RMII_TXD0_PORT_ID    0
+#if      (RTE_ENET_RMII_TXD0_PORT_ID == 0)
+  #define RTE_ENET_RMII_TXD0_PORT       1
+  #define RTE_ENET_RMII_TXD0_PIN        18
+  #define RTE_ENET_RMII_TXD0_FUNC       3
+#else
+  #error "Invalid ENET_TXD0 Pin Configuration!"
+#endif
+//     <o> ENET_TXD1 Pin <0=>P1_20
+#define   RTE_ENET_RMII_TXD1_PORT_ID    0
+#if      (RTE_ENET_RMII_TXD1_PORT_ID == 0)
+  #define RTE_ENET_RMII_TXD1_PORT       1
+  #define RTE_ENET_RMII_TXD1_PIN        20
+  #define RTE_ENET_RMII_TXD1_FUNC       3
+#else
+  #error "Invalid ENET_TXD1 Pin Configuration!"
+#endif
+//     <o> ENET_TX_EN Pin <0=>P0_1 <1=>PC_4
+#define   RTE_ENET_RMII_TX_EN_PORT_ID   0
+#if      (RTE_ENET_RMII_TX_EN_PORT_ID == 0)
+  #define RTE_ENET_RMII_TX_EN_PORT      0
+  #define RTE_ENET_RMII_TX_EN_PIN       1
+  #define RTE_ENET_RMII_TX_EN_FUNC      6
+#elif    (RTE_ENET_RMII_TX_EN_PORT_ID == 1)
+  #define RTE_ENET_RMII_TX_EN_PORT      0xC
+  #define RTE_ENET_RMII_TX_EN_PIN       4
+  #define RTE_ENET_RMII_TX_EN_FUNC      3
+#else
+  #error "Invalid ENET_TX_EN Pin Configuration!"
+#endif
+//     <o> ENET_REF_CLK Pin <0=>P1_19 <1=>CLK0
+#define   RTE_ENET_RMII_REF_CLK_PORT_ID 0
+#if      (RTE_ENET_RMII_REF_CLK_PORT_ID == 0)
+  #define RTE_ENET_RMII_REF_CLK_PORT    1
+  #define RTE_ENET_RMII_REF_CLK_PIN     19
+  #define RTE_ENET_RMII_REF_CLK_FUNC    0
+#elif    (RTE_ENET_RMII_REF_CLK_PORT_ID == 1)
+  #define RTE_ENET_RMII_REF_CLK_PORT    0x10
+  #define RTE_ENET_RMII_REF_CLK_PIN     0
+  #define RTE_ENET_RMII_REF_CLK_FUNC    7
+#else
+  #error "Invalid ENET_REF_CLK Pin Configuration!"
+#endif
+//     <o> ENET_RXD0 Pin <0=>P1_15
+#define   RTE_ENET_RMII_RXD0_PORT_ID    0
+#if      (RTE_ENET_RMII_RXD0_PORT_ID == 0)
+  #define RTE_ENET_RMII_RXD0_PORT       1
+  #define RTE_ENET_RMII_RXD0_PIN        15
+  #define RTE_ENET_RMII_RXD0_FUNC       3
+#else
+  #error "Invalid ENET_RXD0 Pin Configuration!"
+#endif
+//     <o> ENET_RXD1 Pin <0=>P0_0
+#define   RTE_ENET_RMII_RXD1_PORT_ID    0
+#if      (RTE_ENET_RMII_RXD1_PORT_ID == 0)
+  #define RTE_ENET_RMII_RXD1_PORT       0
+  #define RTE_ENET_RMII_RXD1_PIN        0
+  #define RTE_ENET_RMII_RXD1_FUNC       2
+#else
+  #error "Invalid ENET_RXD1 Pin Configuration!"
+#endif
+//     <o> ENET_RX_DV Pin <0=>P1_16 <1=>PC_8
+#define   RTE_ENET_RMII_RX_DV_PORT_ID   0
+#if      (RTE_ENET_RMII_RX_DV_PORT_ID == 0)
+  #define RTE_ENET_RMII_RX_DV_PORT      1
+  #define RTE_ENET_RMII_RX_DV_PIN       16
+  #define RTE_ENET_RMII_RX_DV_FUNC      7
+#elif    (RTE_ENET_RMII_RX_DV_PORT_ID == 1)
+  #define RTE_ENET_RMII_RX_DV_PORT      0xC
+  #define RTE_ENET_RMII_RX_DV_PIN       8
+  #define RTE_ENET_RMII_RX_DV_FUNC      3
+#else
+  #error "Invalid ENET_RX_DV Pin Configuration!"
+#endif
+//   </e> RMII (Reduced Media Independent Interface)
+
+//   <h> MIIM (Management Data Interface)
+//     <o> ENET_MDIO Pin <0=>P1_17
+#define   RTE_ENET_MDI_MDIO_PORT_ID     0
+#if      (RTE_ENET_MDI_MDIO_PORT_ID == 0)
+  #define RTE_ENET_MDI_MDIO_PORT        1
+  #define RTE_ENET_MDI_MDIO_PIN         17
+  #define RTE_ENET_MDI_MDIO_FUNC        3
+#else
+  #error "Invalid ENET_MDIO Pin Configuration!"
+#endif
+//     <o> ENET_MDC Pin <0=>P2_0 <1=>P7_7 <2=>PC_1
+#define   RTE_ENET_MDI_MDC_PORT_ID      2
+#if      (RTE_ENET_MDI_MDC_PORT_ID == 0)
+  #define RTE_ENET_MDI_MDC_PORT         2
+  #define RTE_ENET_MDI_MDC_PIN          0
+  #define RTE_ENET_MDI_MDC_FUNC         7
+#elif    (RTE_ENET_MDI_MDC_PORT_ID == 1)
+  #define RTE_ENET_MDI_MDC_PORT         7
+  #define RTE_ENET_MDI_MDC_PIN          7
+  #define RTE_ENET_MDI_MDC_FUNC         6
+#elif    (RTE_ENET_MDI_MDC_PORT_ID == 2)
+  #define RTE_ENET_MDI_MDC_PORT         0xC
+  #define RTE_ENET_MDI_MDC_PIN          1
+  #define RTE_ENET_MDI_MDC_FUNC         3
+#else
+  #error "Invalid ENET_MDC Pin Configuration!"
+#endif
+//   </h> MIIM (Management Data Interface)
+// </e> ENET (Ethernet Interface) [Driver_ETH_MAC0]
+
+// <e> SD/MMC Interface [Driver_MCI0]
+// <i> Configuration settings for Driver_MCI0 in component ::Drivers:MCI
+#define RTE_SDMMC                       0
+
+//   <h> SD/MMC Peripheral Bus
+//     <o> SD_CLK Pin <0=>PC_0 <1=>CLK0 <2=>CLK2
+#define   RTE_SD_CLK_PORT_ID            0
+#if      (RTE_SD_CLK_PORT_ID == 0)
+  #define RTE_SD_CLK_PORT               0xC
+  #define RTE_SD_CLK_PIN                0
+  #define RTE_SD_CLK_FUNC               7
+#elif    (RTE_SD_CLK_PORT_ID == 1)
+  #define RTE_SD_CLK_PORT               0x10
+  #define RTE_SD_CLK_PIN                0
+  #define RTE_SD_CLK_FUNC               4
+#elif    (RTE_SD_CLK_PORT_ID == 2)
+  #define RTE_SD_CLK_PORT               0x10
+  #define RTE_SD_CLK_PIN                2
+  #define RTE_SD_CLK_FUNC               4
+#else
+  #error "Invalid SD_CLK Pin Configuration!"
+#endif
+//     <o> SD_CMD Pin <0=>P1_6 <1=>PC_10
+#define   RTE_SD_CMD_PORT_ID            0
+#if      (RTE_SD_CMD_PORT_ID == 0)
+  #define RTE_SD_CMD_PORT               1
+  #define RTE_SD_CMD_PIN                6
+  #define RTE_SD_CMD_FUNC               7
+#elif    (RTE_SD_CMD_PORT_ID == 1)
+  #define RTE_SD_CMD_PORT               0xC
+  #define RTE_SD_CMD_PIN                10
+  #define RTE_SD_CMD_FUNC               7
+#else
+  #error "Invalid SD_CMD Pin Configuration!"
+#endif
+//     <o> SD_DAT0 Pin <0=>P1_9 <1=>PC_4
+#define   RTE_SD_DAT0_PORT_ID           0
+#if      (RTE_SD_DAT0_PORT_ID == 0)
+  #define RTE_SD_DAT0_PORT              1
+  #define RTE_SD_DAT0_PIN               9
+  #define RTE_SD_DAT0_FUNC              7
+#elif    (RTE_SD_DAT0_PORT_ID == 1)
+  #define RTE_SD_DAT0_PORT              0xC
+  #define RTE_SD_DAT0_PIN               4
+  #define RTE_SD_DAT0_FUNC              7
+#else
+  #error "Invalid SD_DAT0 Pin Configuration!"
+#endif
+//     <e> SD_DAT[1 .. 3]
+#define   RTE_SDMMC_BUS_WIDTH_4         0
+//       <o> SD_DAT1 Pin <0=>P1_10 <1=>PC_5
+#define   RTE_SD_DAT1_PORT_ID           0
+#if      (RTE_SD_DAT1_PORT_ID == 0)
+  #define RTE_SD_DAT1_PORT              1
+  #define RTE_SD_DAT1_PIN               10
+  #define RTE_SD_DAT1_FUNC              7
+#elif    (RTE_SD_DAT1_PORT_ID == 1)
+  #define RTE_SD_DAT1_PORT              0xC
+  #define RTE_SD_DAT1_PIN               5
+  #define RTE_SD_DAT1_FUNC              7
+#else
+  #error "Invalid SD_DAT1 Pin Configuration!"
+#endif
+//       <o> SD_DAT2 Pin <0=>P1_11 <1=>PC_6
+#define   RTE_SD_DAT2_PORT_ID           0
+#if      (RTE_SD_DAT2_PORT_ID == 0)
+  #define RTE_SD_DAT2_PORT              1
+  #define RTE_SD_DAT2_PIN               11
+  #define RTE_SD_DAT2_FUNC              7
+#elif    (RTE_SD_DAT2_PORT_ID == 1)
+  #define RTE_SD_DAT2_PORT              0xC
+  #define RTE_SD_DAT2_PIN               6
+  #define RTE_SD_DAT2_FUNC              7
+#else
+  #error "Invalid SD_DAT2 Pin Configuration!"
+#endif
+//       <o> SD_DAT3 Pin <0=>P1_12 <1=>PC_7
+#define   RTE_SD_DAT3_PORT_ID           0
+#if      (RTE_SD_DAT3_PORT_ID == 0)
+  #define RTE_SD_DAT3_PORT              1
+  #define RTE_SD_DAT3_PIN               12
+  #define RTE_SD_DAT3_FUNC              7
+#elif    (RTE_SD_DAT3_PORT_ID == 1)
+  #define RTE_SD_DAT3_PORT              0xC
+  #define RTE_SD_DAT3_PIN               7
+  #define RTE_SD_DAT3_FUNC              7
+#else
+  #error "Invalid SD_DAT3 Pin Configuration!"
+#endif
+//     </e> SD_DAT[1 .. 3]
+//     <e> SD_DAT[4 .. 7]
+#define   RTE_SDMMC_BUS_WIDTH_8         0
+//       <o> SD_DAT4 Pin <0=>PC_11
+#define   RTE_SD_DAT4_PORT_ID           0
+#if      (RTE_SD_DAT4_PORT_ID == 0)
+  #define RTE_SD_DAT4_PORT              0xC
+  #define RTE_SD_DAT4_PIN               11
+  #define RTE_SD_DAT4_FUNC              7
+#else
+  #error "Invalid SD_DAT4 Pin Configuration!"
+#endif
+//       <o> SD_DAT5 Pin <0=>PC_12
+#define   RTE_SD_DAT5_PORT_ID           0
+#if      (RTE_SD_DAT5_PORT_ID == 0)
+  #define RTE_SD_DAT5_PORT              0xC
+  #define RTE_SD_DAT5_PIN               12
+  #define RTE_SD_DAT5_FUNC              7
+#else
+  #error "Invalid SD_DAT5 Pin Configuration!"
+#endif
+//       <o> SD_DAT6 Pin <0=>PC_13
+#define   RTE_SD_DAT6_PORT_ID           0
+#if      (RTE_SD_DAT6_PORT_ID == 0)
+  #define RTE_SD_DAT6_PORT              0xC
+  #define RTE_SD_DAT6_PIN               13
+  #define RTE_SD_DAT6_FUNC              7
+#else
+  #error "Invalid SD_DAT6 Pin Configuration!"
+#endif
+//       <o> SD_DAT7 Pin <0=>PC_14
+#define   RTE_SD_DAT7_PORT_ID           0
+#if      (RTE_SD_DAT7_PORT_ID == 0)
+  #define RTE_SD_DAT7_PORT              0xC
+  #define RTE_SD_DAT7_PIN               14
+  #define RTE_SD_DAT7_FUNC              7
+#else
+  #error "Invalid SD_DAT7 Pin Configuration!"
+#endif
+//     </e> SD_DAT[4 .. 7]
+//   </h> SD/MMC Peripheral Bus
+
+//   <o> SD_CD (Card Detect) Pin <0=>Not used <1=>P1_13 <2=>PC_8
+//   <i> Configure Pin if exists
+#define   RTE_SD_CD_PORT_ID             0
+#if      (RTE_SD_CD_PORT_ID == 0)
+  #define RTE_SD_CD_PIN_EN              0
+#elif    (RTE_SD_CD_PORT_ID == 1)
+  #define RTE_SD_CD_PORT                1
+  #define RTE_SD_CD_PIN                 13
+  #define RTE_SD_CD_FUNC                7
+#elif    (RTE_SD_CD_PORT_ID == 2)
+  #define RTE_SD_CD_PORT                0xC
+  #define RTE_SD_CD_PIN                 8
+  #define RTE_SD_CD_FUNC                7
+#else
+  #error "Invalid SD_CD Pin Configuration!"
+#endif
+#ifndef   RTE_SD_CD_PIN_EN
+  #define RTE_SD_CD_PIN_EN              1
+#endif
+//   <o> SD_WP (Write Protect) Pin <0=>Not used <1=>PD_15 <2=>PF_10
+//   <i> Configure Pin if exists
+#define   RTE_SD_WP_PORT_ID             0
+#if      (RTE_SD_WP_PORT_ID == 0)
+  #define RTE_SD_WP_PIN_EN              0
+#elif    (RTE_SD_WP_PORT_ID == 1)
+  #define RTE_SD_WP_PORT                0xD
+  #define RTE_SD_WP_PIN                 15
+  #define RTE_SD_WP_FUNC                5
+#elif    (RTE_SD_WP_PORT_ID == 2)
+  #define RTE_SD_WP_PORT                0xF
+  #define RTE_SD_WP_PIN                 10
+  #define RTE_SD_WP_FUNC                6
+#else
+  #error "Invalid SD_WP Pin Configuration!"
+#endif
+#ifndef   RTE_SD_WP_PIN_EN
+  #define RTE_SD_WP_PIN_EN              1
+#endif
+//   <o> SD_POW (Power) Pin <0=>Not used <1=>P1_5 <2=>PC_9 <3=>PD_1
+//   <i> Configure Pin if exists
+#define   RTE_SD_POW_PORT_ID            0
+#if      (RTE_SD_POW_PORT_ID == 0)
+  #define RTE_SD_POW_PIN_EN             0
+#elif    (RTE_SD_POW_PORT_ID == 1)
+  #define RTE_SD_POW_PORT               1
+  #define RTE_SD_POW_PIN                5
+  #define RTE_SD_POW_FUNC               7
+#elif    (RTE_SD_POW_PORT_ID == 2)
+  #define RTE_SD_POW_PORT               0xC
+  #define RTE_SD_POW_PIN                9
+  #define RTE_SD_POW_FUNC               7
+#elif    (RTE_SD_POW_PORT_ID == 3)
+  #define RTE_SD_POW_PORT               0xD
+  #define RTE_SD_POW_PIN                1
+  #define RTE_SD_POW_FUNC               5
+#else
+  #error "Invalid SD_POW Pin Configuration!"
+#endif
+#ifndef   RTE_SD_POW_PIN_EN
+  #define RTE_SD_POW_PIN_EN             1
+#endif
+//   <o> SD_RST (Card Reset for MMC4.4) Pin <0=>Not used <1=>P1_3 <2=>PC_2
+//   <i> Configure Pin if exists
+#define   RTE_SD_RST_PORT_ID            0
+#if      (RTE_SD_RST_PORT_ID == 0)
+  #define RTE_SD_RST_PIN_EN             0
+#elif    (RTE_SD_RST_PORT_ID == 1)
+  #define RTE_SD_RST_PORT               1
+  #define RTE_SD_RST_PIN                3
+  #define RTE_SD_RST_FUNC               7
+#elif    (RTE_SD_RST_PORT_ID == 2)
+  #define RTE_SD_RST_PORT               0xC
+  #define RTE_SD_RST_PIN                2
+  #define RTE_SD_RST_FUNC               7
+#else
+  #error "Invalid SD_RST Pin Configuration!"
+#endif
+#ifndef   RTE_SD_RST_PIN_EN
+  #define RTE_SD_RST_PIN_EN             1
+#endif
+// </e> SD/MMC Interface [Driver_MCI0]
+
+// <e> I2C0 (Inter-integrated Circuit Interface 0) [Driver_I2C0]
+// <i> Configuration settings for Driver_I2C0 in component ::Drivers:I2C
+// </e> I2C0 (Inter-integrated Circuit Interface 0) [Driver_I2C0]
+#define   RTE_I2C0                      0
+
+// <e> I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1]
+// <i> Configuration settings for Driver_I2C1 in component ::Drivers:I2C
+#define   RTE_I2C1                      0
+
+//   <o> I2C1_SCL Pin <0=>P2_4 <1=>PE_15
+#define   RTE_I2C1_SCL_PORT_ID          0
+#if      (RTE_I2C1_SCL_PORT_ID == 0)
+  #define RTE_I2C1_SCL_PORT             2
+  #define RTE_I2C1_SCL_PIN              4
+  #define RTE_I2C1_SCL_FUNC             1
+#elif    (RTE_I2C1_SCL_PORT_ID == 1)
+  #define RTE_I2C1_SCL_PORT             0xE
+  #define RTE_I2C1_SCL_PIN              15
+  #define RTE_I2C1_SCL_FUNC             2
+#else
+  #error "Invalid I2C1_SCL Pin Configuration!"
+#endif
+//   <o> I2C1_SDA Pin <0=>P2_3 <1=>PE_13
+#define   RTE_I2C1_SDA_PORT_ID          0
+#if      (RTE_I2C1_SDA_PORT_ID == 0)
+  #define RTE_I2C1_SDA_PORT             2
+  #define RTE_I2C1_SDA_PIN              3
+  #define RTE_I2C1_SDA_FUNC             1
+#elif    (RTE_I2C1_SDA_PORT_ID == 1)
+  #define RTE_I2C1_SDA_PORT             0xE
+  #define RTE_I2C1_SDA_PIN              13
+  #define RTE_I2C1_SDA_FUNC             2
+#else
+  #error "Invalid I2C1_SDA Pin Configuration!"
+#endif
+// </e> I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1]
+
+// <e> USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0]
+#define   RTE_USART0                    0
+
+//   <h> Pin Configuration
+//     <o> TX <0=>P2_0 <1=>P6_4 <2=>P9_5 <3=>PF_10
+//     <i> USART0 Serial Output pin
+#define   RTE_USART0_TX_ID              0
+#if      (RTE_USART0_TX_ID == 0)
+  #define RTE_USART0_TX_PORT            2
+  #define RTE_USART0_TX_BIT             0
+  #define RTE_USART0_TX_FUNC            1
+#elif    (RTE_USART0_TX_ID == 1)
+  #define RTE_USART0_TX_PORT            6
+  #define RTE_USART0_TX_BIT             4
+  #define RTE_USART0_TX_FUNC            2
+#elif    (RTE_USART0_TX_ID == 2)
+  #define RTE_USART0_TX_PORT            9
+  #define RTE_USART0_TX_BIT             5
+  #define RTE_USART0_TX_FUNC            7
+#elif    (RTE_USART0_TX_ID == 3)
+  #define RTE_USART0_TX_PORT            0xF
+  #define RTE_USART0_TX_BIT             10
+  #define RTE_USART0_TX_FUNC            1
+#else
+  #error "Invalid USART0_TX Pin Configuration!"
+#endif
+//     <o> RX <0=>P2_1 <1=>P6_5 <2=>P9_6 <3=>PF_11
+//     <i> USART0 Serial Input pin
+#define   RTE_USART0_RX_ID              0
+#if      (RTE_USART0_RX_ID == 0)
+  #define RTE_USART0_RX_PORT            2
+  #define RTE_USART0_RX_BIT             1
+  #define RTE_USART0_RX_FUNC            1
+#elif    (RTE_USART0_RX_ID == 1)
+  #define RTE_USART0_RX_PORT            6
+  #define RTE_USART0_RX_BIT             5
+  #define RTE_USART0_RX_FUNC            2
+#elif    (RTE_USART0_RX_ID == 2)
+  #define RTE_USART0_RX_PORT            9
+  #define RTE_USART0_RX_BIT             6
+  #define RTE_USART0_RX_FUNC            7
+#elif    (RTE_USART0_RX_ID == 3)
+  #define RTE_USART0_RX_PORT            0xF
+  #define RTE_USART0_RX_BIT             11
+  #define RTE_USART0_RX_FUNC            1
+#else
+  #error "Invalid USART0_RX Pin Configuration!"
+#endif
+//     <o> UCLK (Synchronous and SmartCard mode) <0=>Not used <1=>P2_2 <2=>P6_1 <3=>PF_8
+//     <i> USART0 Serial Clock input/output synchronous mode
+#define   RTE_USART0_UCLK_ID            0
+#if      (RTE_USART0_UCLK_ID == 0)
+  #define RTE_USART0_UCLK_PIN_EN        0
+#elif    (RTE_USART0_UCLK_ID == 1)
+  #define RTE_USART0_UCLK_PORT          2
+  #define RTE_USART0_UCLK_BIT           2
+  #define RTE_USART0_UCLK_FUNC          1
+#elif    (RTE_USART0_UCLK_ID == 2)
+  #define RTE_USART0_UCLK_PORT          6
+  #define RTE_USART0_UCLK_BIT           1
+  #define RTE_USART0_UCLK_FUNC          2
+#elif    (RTE_USART0_UCLK_ID == 3)
+  #define RTE_USART0_UCLK_PORT          0xF
+  #define RTE_USART0_UCLK_BIT           8
+  #define RTE_USART0_UCLK_FUNC          1
+#else
+  #error "Invalid USART0_UCLK Pin Configuration!"
+#endif
+#ifndef   RTE_USART0_UCLK_PIN_EN
+  #define RTE_USART0_UCLK_PIN_EN        1
+#endif
+//   </h> Pin Configuration
+
+//   <h> DMA
+//     <e> Tx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>1 (DMAMUXPER1)  <1=>11 (DMAMUXPER11)
+//     </e>
+#define   RTE_USART0_DMA_TX_EN          0
+#define   RTE_USART0_DMA_TX_CH          0
+#define   RTE_USART0_DMA_TX_PERI_ID     0
+#if      (RTE_USART0_DMA_TX_PERI_ID == 0)
+  #define RTE_USART0_DMA_TX_PERI        1
+  #define RTE_USART0_DMA_TX_PERI_SEL    1
+#elif    (RTE_USART0_DMA_TX_PERI_ID == 1)
+  #define RTE_USART0_DMA_TX_PERI        11
+  #define RTE_USART0_DMA_TX_PERI_SEL    2
+#endif
+//     <e> Rx
+//       <o1> Channel    <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral <0=>2 (DMAMUXPER2)  <1=>12 (DMAMUXPER12)
+//     </e>
+#define   RTE_USART0_DMA_RX_EN          0
+#define   RTE_USART0_DMA_RX_CH          1
+#define   RTE_USART0_DMA_RX_PERI_ID     0
+#if      (RTE_USART0_DMA_RX_PERI_ID == 0)
+  #define RTE_USART0_DMA_RX_PERI        2
+  #define RTE_USART0_DMA_RX_PERI_SEL    1
+#elif    (RTE_USART0_DMA_RX_PERI_ID == 1)
+  #define RTE_USART0_DMA_RX_PERI        12
+  #define RTE_USART0_DMA_RX_PERI_SEL    2
+#endif
+//   </h> DMA
+// </e> USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0]
+
+// <e> UART1 (Universal asynchronous receiver transmitter) [Driver_USART1]
+#define   RTE_UART1                     0
+
+//   <h> Pin Configuration
+//     <o> TX <0=>P1_13 <1=>P3_4 <2=>P5_6 <3=>PC_13 <4=>PE_11
+//     <i> UART0 Serial Output pin
+#define   RTE_UART1_TX_ID               2
+#if      (RTE_UART1_TX_ID == 0)
+  #define RTE_UART1_TX_PORT             1
+  #define RTE_UART1_TX_BIT              13
+  #define RTE_UART1_TX_FUNC             1
+#elif    (RTE_UART1_TX_ID == 1)
+  #define RTE_UART1_TX_PORT             3
+  #define RTE_UART1_TX_BIT              4
+  #define RTE_UART1_TX_FUNC             4
+#elif    (RTE_UART1_TX_ID == 2)
+  #define RTE_UART1_TX_PORT             5
+  #define RTE_UART1_TX_BIT              6
+  #define RTE_UART1_TX_FUNC             4
+#elif    (RTE_UART1_TX_ID == 3)
+  #define RTE_UART1_TX_PORT             0xC
+  #define RTE_UART1_TX_BIT              13
+  #define RTE_UART1_TX_FUNC             2
+#elif    (RTE_UART1_TX_ID == 4)
+  #define RTE_UART1_TX_PORT             0xE
+  #define RTE_UART1_TX_BIT              11
+  #define RTE_UART1_TX_FUNC             2
+#else
+  #error "Invalid UART1_TX Pin Configuration!"
+#endif
+//   <o> RX <0=>P1_14 <1=>P3_5 <2=>P5_7 <3=>PC_14 <4=>PE_12
+//   <i> UART1 Serial Input pin
+#define   RTE_UART1_RX_ID               0
+#if      (RTE_UART1_RX_ID == 0)
+  #define RTE_UART1_RX_PORT             1
+  #define RTE_UART1_RX_BIT              14
+  #define RTE_UART1_RX_FUNC             1
+#elif    (RTE_UART1_RX_ID == 1)
+  #define RTE_UART1_RX_PORT             3
+  #define RTE_UART1_RX_BIT              5
+  #define RTE_UART1_RX_FUNC             4
+#elif    (RTE_UART1_RX_ID == 2)
+  #define RTE_UART1_RX_PORT             5
+  #define RTE_UART1_RX_BIT              7
+  #define RTE_UART1_RX_FUNC             4
+#elif    (RTE_UART1_RX_ID == 3)
+  #define RTE_UART1_RX_PORT             0xC
+  #define RTE_UART1_RX_BIT              14
+  #define RTE_UART1_RX_FUNC             2
+#elif    (RTE_UART1_RX_ID == 4)
+  #define RTE_UART1_RX_PORT             0xE
+  #define RTE_UART1_RX_BIT              12
+  #define RTE_UART1_RX_FUNC             2
+#else
+  #error "Invalid UART1_RX Pin Configuration!"
+#endif
+
+//     <h> Modem Lines
+//       <o> CTS <0=>Not used <1=>P1_11 <2=>P5_4 <3=>PC_2 <4=>PE_7
+#define   RTE_UART1_CTS_ID              1
+#if      (RTE_UART1_CTS_ID == 0)
+  #define RTE_UART1_CTS_PIN_EN          0
+#elif    (RTE_UART1_CTS_ID == 1)
+  #define RTE_UART1_CTS_PORT            1
+  #define RTE_UART1_CTS_BIT             11
+  #define RTE_UART1_CTS_FUNC            1
+#elif    (RTE_UART1_CTS_ID == 2)
+  #define RTE_UART1_CTS_PORT            5
+  #define RTE_UART1_CTS_BIT             4
+  #define RTE_UART1_CTS_FUNC            4
+#elif    (RTE_UART1_CTS_ID == 3)
+  #define RTE_UART1_CTS_PORT            0xC
+  #define RTE_UART1_CTS_BIT             2
+  #define RTE_UART1_CTS_FUNC            2
+#elif    (RTE_UART1_CTS_ID == 4)
+  #define RTE_UART1_CTS_PORT            0xE
+  #define RTE_UART1_CTS_BIT             7
+  #define RTE_UART1_CTS_FUNC            2
+#else
+  #error "Invalid UART1_CTS Pin Configuration!"
+#endif
+#ifndef   RTE_UART1_CTS_PIN_EN
+  #define RTE_UART1_CTS_PIN_EN          1
+#endif
+//       <o> RTS <0=>Not used <1=>P1_9  <2=>P5_2 <3=>PC_3 <4=>PE_5
+#define   RTE_UART1_RTS_ID              1
+#if      (RTE_UART1_RTS_ID == 0)
+  #define RTE_UART1_RTS_PIN_EN          0
+#elif    (RTE_UART1_RTS_ID == 1)
+  #define RTE_UART1_RTS_PORT            1
+  #define RTE_UART1_RTS_BIT             9
+  #define RTE_UART1_RTS_FUNC            1
+#elif    (RTE_UART1_RTS_ID == 2)
+  #define RTE_UART1_RTS_PORT            5
+  #define RTE_UART1_RTS_BIT             2
+  #define RTE_UART1_RTS_FUNC            4
+#elif    (RTE_UART1_RTS_ID == 3)
+  #define RTE_UART1_RTS_PORT            0xC
+  #define RTE_UART1_RTS_BIT             3
+  #define RTE_UART1_RTS_FUNC            2
+#elif    (RTE_UART1_RTS_ID == 4)
+  #define RTE_UART1_RTS_PORT            0xE
+  #define RTE_UART1_RTS_BIT             5
+  #define RTE_UART1_RTS_FUNC            2
+#else
+  #error "Invalid UART1_RTS Pin Configuration!"
+#endif
+#ifndef   RTE_UART1_RTS_PIN_EN
+  #define RTE_UART1_RTS_PIN_EN          1
+#endif
+//       <o> DCD <0=>Not used <1=>P1_12 <2=>P5_5 <3=>PC_11 <4=>PE_9
+#define   RTE_UART1_DCD_ID              1
+#if      (RTE_UART1_DCD_ID == 0)
+  #define RTE_UART1_DCD_PIN_EN          0
+#elif    (RTE_UART1_DCD_ID == 1)
+  #define RTE_UART1_DCD_PORT            1
+  #define RTE_UART1_DCD_BIT             12
+  #define RTE_UART1_DCD_FUNC            1
+#elif    (RTE_UART1_DCD_ID == 2)
+  #define RTE_UART1_DCD_PORT            5
+  #define RTE_UART1_DCD_BIT             5
+  #define RTE_UART1_DCD_FUNC            4
+#elif    (RTE_UART1_DCD_ID == 3)
+  #define RTE_UART1_DCD_PORT            0xC
+  #define RTE_UART1_DCD_BIT             11
+  #define RTE_UART1_DCD_FUNC            2
+#elif    (RTE_UART1_DCD_ID == 4)
+  #define RTE_UART1_DCD_PORT            0xE
+  #define RTE_UART1_DCD_BIT             9
+  #define RTE_UART1_DCD_FUNC            2
+#else
+  #error "Invalid UART1_DCD Pin Configuration!"
+#endif
+#ifndef   RTE_UART1_DCD_PIN_EN
+  #define RTE_UART1_DCD_PIN_EN          1
+#endif
+//       <o> DSR <0=>Not used <1=>P1_7 <2=>P5_0 <3=>PC_10 <4=>PE_8
+#define   RTE_UART1_DSR_ID              1
+#if      (RTE_UART1_DSR_ID == 0)
+  #define RTE_UART1_DSR_PIN_EN          0
+#elif    (RTE_UART1_DSR_ID == 1)
+  #define RTE_UART1_DSR_PORT            1
+  #define RTE_UART1_DSR_BIT             7
+  #define RTE_UART1_DSR_FUNC            1
+#elif    (RTE_UART1_DSR_ID == 2)
+  #define RTE_UART1_DSR_PORT            5
+  #define RTE_UART1_DSR_BIT             0
+  #define RTE_UART1_DSR_FUNC            4
+#elif    (RTE_UART1_DSR_ID == 3)
+  #define RTE_UART1_DSR_PORT            0xC
+  #define RTE_UART1_DSR_BIT             10
+  #define RTE_UART1_DSR_FUNC            2
+#elif    (RTE_UART1_DSR_ID == 4)
+  #define RTE_UART1_DSR_PORT            0xE
+  #define RTE_UART1_DSR_BIT             8
+  #define RTE_UART1_DSR_FUNC            2
+#else
+  #error "Invalid UART1_DSR Pin Configuration!"
+#endif
+#ifndef   RTE_UART1_DSR_PIN_EN
+  #define RTE_UART1_DSR_PIN_EN          1
+#endif
+//       <o> DTR <0=>Not used <1=>P1_8  <2=>P5_1 <3=>PC_12 <4=>PE_10
+#define   RTE_UART1_DTR_ID              1
+#if      (RTE_UART1_DTR_ID == 0)
+  #define RTE_UART1_DTR_PIN_EN          0
+#elif    (RTE_UART1_DTR_ID == 1)
+  #define RTE_UART1_DTR_PORT            1
+  #define RTE_UART1_DTR_BIT             8
+  #define RTE_UART1_DTR_FUNC            1
+#elif    (RTE_UART1_DTR_ID == 2)
+  #define RTE_UART1_DTR_PORT            5
+  #define RTE_UART1_DTR_BIT             1
+  #define RTE_UART1_DTR_FUNC            4
+#elif    (RTE_UART1_DTR_ID == 3)
+  #define RTE_UART1_DTR_PORT            0xC
+  #define RTE_UART1_DTR_BIT             12
+  #define RTE_UART1_DTR_FUNC            2
+#elif    (RTE_UART1_DTR_ID == 4)
+  #define RTE_UART1_DTR_PORT            0xE
+  #define RTE_UART1_DTR_BIT             10
+  #define RTE_UART1_DTR_FUNC            2
+#else
+  #error "Invalid UART1_DTR Pin Configuration!"
+#endif
+#ifndef   RTE_UART1_DTR_PIN_EN
+  #define RTE_UART1_DTR_PIN_EN          1
+#endif
+//       <o> RI <0=>Not used <1=>P1_10 <2=>P5_3 <3=>PC_1 <4=>PE_6
+#define   RTE_UART1_RI_ID               1
+#if      (RTE_UART1_RI_ID == 0)
+  #define RTE_UART1_RI_PIN_EN           0
+#elif    (RTE_UART1_RI_ID == 1)
+  #define RTE_UART1_RI_PORT             1
+  #define RTE_UART1_RI_BIT              10
+  #define RTE_UART1_RI_FUNC             1
+#elif    (RTE_UART1_RI_ID == 2)
+  #define RTE_UART1_RI_PORT             5
+  #define RTE_UART1_RI_BIT              3
+  #define RTE_UART1_RI_FUNC             4
+#elif    (RTE_UART1_RI_ID == 3)
+  #define RTE_UART1_RI_PORT             0xC
+  #define RTE_UART1_RI_BIT              1
+  #define RTE_UART1_RI_FUNC             2
+#elif    (RTE_UART1_RI_ID == 4)
+  #define RTE_UART1_RI_PORT             0xE
+  #define RTE_UART1_RI_BIT              6
+  #define RTE_UART1_RI_FUNC             2
+#else
+  #error "Invalid UART1_RI Pin Configuration!"
+#endif
+#ifndef   RTE_UART1_RI_PIN_EN
+  #define RTE_UART1_RI_PIN_EN           1
+#endif
+//     </h> Modem Lines
+//   </h> Pin Configuration
+
+//   <h> DMA
+//     <e> Tx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>3 (DMAMUXPER3)
+//     </e>
+#define   RTE_UART1_DMA_TX_EN           0
+#define   RTE_UART1_DMA_TX_CH           0
+#define   RTE_UART1_DMA_TX_PERI_ID      0
+#if      (RTE_UART1_DMA_TX_PERI_ID == 0)
+  #define RTE_UART1_DMA_TX_PERI         3
+  #define RTE_UART1_DMA_TX_PERI_SEL     1
+#endif
+//     <e> Rx
+//       <o1> Channel    <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral <0=>4 (DMAMUXPER4)
+//     </e>
+#define   RTE_UART1_DMA_RX_EN           0
+#define   RTE_UART1_DMA_RX_CH           1
+#define   RTE_UART1_DMA_RX_PERI_ID      0
+#if      (RTE_UART1_DMA_RX_PERI_ID == 0)
+  #define RTE_UART1_DMA_RX_PERI         4
+  #define RTE_UART1_DMA_RX_PERI_SEL     1
+#endif
+//   </h> DMA
+// </e> UART1 (Universal asynchronous receiver transmitter) [Driver_USART1]
+
+// <e> USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2]
+#define   RTE_USART2                    0
+
+//   <h> Pin Configuration
+//     <o> TX <0=>P1_15 <1=>P2_10 <2=>P7_1 <3=>PA_1
+//     <i> USART2 Serial Output pin
+#define   RTE_USART2_TX_ID              0
+#if      (RTE_USART2_TX_ID == 0)
+  #define RTE_USART2_TX_PORT            1
+  #define RTE_USART2_TX_BIT             15
+  #define RTE_USART2_TX_FUNC            1
+#elif    (RTE_USART2_TX_ID == 1)
+  #define RTE_USART2_TX_PORT            2
+  #define RTE_USART2_TX_BIT             10
+  #define RTE_USART2_TX_FUNC            2
+#elif    (RTE_USART2_TX_ID == 2)
+  #define RTE_USART2_TX_PORT            7
+  #define RTE_USART2_TX_BIT             1
+  #define RTE_USART2_TX_FUNC            6
+#elif    (RTE_USART2_TX_ID == 3)
+  #define RTE_USART2_TX_PORT            0xA
+  #define RTE_USART2_TX_BIT             1
+  #define RTE_USART2_TX_FUNC            3
+#else
+  #error "Invalid USART2_TX Pin Configuration!"
+#endif
+//     <o> RX <0=>P1_16 <1=>P2_11 <2=>P7_2 <3=>PA_2
+//     <i> USART2 Serial Input pin
+#define   RTE_USART2_RX_ID              0
+#if      (RTE_USART2_RX_ID == 0)
+  #define RTE_USART2_RX_PORT            1
+  #define RTE_USART2_RX_BIT             16
+  #define RTE_USART2_RX_FUNC            1
+#elif    (RTE_USART2_RX_ID == 1)
+  #define RTE_USART2_RX_PORT            2
+  #define RTE_USART2_RX_BIT             11
+  #define RTE_USART2_RX_FUNC            2
+#elif    (RTE_USART2_RX_ID == 2)
+  #define RTE_USART2_RX_PORT            7
+  #define RTE_USART2_RX_BIT             2
+  #define RTE_USART2_RX_FUNC            6
+#elif    (RTE_USART2_RX_ID == 3)
+  #define RTE_USART2_RX_PORT            0xA
+  #define RTE_USART2_RX_BIT             2
+  #define RTE_USART2_RX_FUNC            3
+#else
+  #error "Invalid USART2_RX Pin Configuration!"
+#endif
+//       <o> UCLK (Synchronous and SmartCard mode) <0=>Not used <1=>P1_17 <2=>P2_12
+//       <i> USART2 Serial Clock input/output synchronous mode
+#define   RTE_USART2_UCLK_ID            0
+#if      (RTE_USART2_UCLK_ID == 0)
+  #define RTE_USART2_UCLK_PIN_EN        0
+#elif    (RTE_USART2_UCLK_ID == 1)
+  #define RTE_USART2_UCLK_PORT          1
+  #define RTE_USART2_UCLK_BIT           17
+  #define RTE_USART2_UCLK_FUNC          1
+#elif    (RTE_USART2_UCLK_ID == 1)
+  #define RTE_USART2_UCLK_PORT          2
+  #define RTE_USART2_UCLK_BIT           12
+  #define RTE_USART2_UCLK_FUNC          7
+#else
+  #error "Invalid USART2_UCLK Pin Configuration!"
+#endif
+#ifndef   RTE_USART2_UCLK_PIN_EN
+  #define RTE_USART2_UCLK_PIN_EN        1
+#endif
+//   </h> Pin Configuration
+
+//   <h> DMA
+//     <e> Tx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>5 (DMAMUXPER5)
+//     </e>
+#define   RTE_USART2_DMA_TX_EN          0
+#define   RTE_USART2_DMA_TX_CH          0
+#define   RTE_USART2_DMA_TX_PERI_ID     0
+#if      (RTE_USART2_DMA_TX_PERI_ID == 0)
+  #define RTE_USART2_DMA_TX_PERI        5
+  #define RTE_USART2_DMA_TX_PERI_SEL    1
+#endif
+//     <e> Rx
+//       <o1> Channel    <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral <0=>6 (DMAMUXPER6)
+//     </e>
+#define   RTE_USART2_DMA_RX_EN          0
+#define   RTE_USART2_DMA_RX_CH          1
+#define   RTE_USART2_DMA_RX_PERI_ID     0
+#if      (RTE_USART2_DMA_RX_PERI_ID == 0)
+  #define RTE_USART2_DMA_RX_PERI        6
+  #define RTE_USART2_DMA_RX_PERI_SEL    1
+#endif
+//   </h> DMA
+// </e> USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2]
+
+// <e> USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3]
+#define   RTE_USART3                    0
+
+//   <h> Pin Configuration
+//     <o> TX <0=>P2_3 <1=>P4_1 <2=>P9_3 <3=>PF_2
+//     <i> USART3 Serial Output pin
+#define   RTE_USART3_TX_ID              0
+#if      (RTE_USART3_TX_ID == 0)
+  #define RTE_USART3_TX_PORT            2
+  #define RTE_USART3_TX_BIT             3
+  #define RTE_USART3_TX_FUNC            2
+#elif    (RTE_USART3_TX_ID == 1)
+  #define RTE_USART3_TX_PORT            4
+  #define RTE_USART3_TX_BIT             1
+  #define RTE_USART3_TX_FUNC            6
+#elif    (RTE_USART3_TX_ID == 2)
+  #define RTE_USART3_TX_PORT            9
+  #define RTE_USART3_TX_BIT             3
+  #define RTE_USART3_TX_FUNC            7
+#elif    (RTE_USART3_TX_ID == 3)
+  #define RTE_USART3_TX_PORT            0xF
+  #define RTE_USART3_TX_BIT             2
+  #define RTE_USART3_TX_FUNC            1
+#else
+  #error "Invalid USART3_TX Pin Configuration!"
+#endif
+//     <o> RX <0=>P2_4 <1=>P4_2 <2=>P9_4 <3=>PF_3
+//     <i> USART3 Serial Input pin
+#define   RTE_USART3_RX_ID              0
+#if      (RTE_USART3_RX_ID == 0)
+  #define RTE_USART3_RX_PORT            2
+  #define RTE_USART3_RX_BIT             4
+  #define RTE_USART3_RX_FUNC            2
+#elif    (RTE_USART3_RX_ID == 1)
+  #define RTE_USART3_RX_PORT            4
+  #define RTE_USART3_RX_BIT             2
+  #define RTE_USART3_RX_FUNC            6
+#elif    (RTE_USART3_RX_ID == 2)
+  #define RTE_USART3_RX_PORT            9
+  #define RTE_USART3_RX_BIT             4
+  #define RTE_USART3_RX_FUNC            7
+#elif    (RTE_USART3_RX_ID == 3)
+  #define RTE_USART3_RX_PORT            0xF
+  #define RTE_USART3_RX_BIT             3
+  #define RTE_USART3_RX_FUNC            1
+#else
+  #error "Invalid USART3_RX Pin Configuration!"
+#endif
+//     <o> UCLK (Synchronous and SmartCard mode) <0=>Not used <1=>P2_7 <2=>P4_0 <3=>PF_5
+//     <i> USART3 Serial Clock input/output synchronous mode
+#define   RTE_USART3_UCLK_ID            0
+#if      (RTE_USART3_UCLK_ID == 0)
+  #define RTE_USART3_UCLK_PIN_EN        0
+#elif    (RTE_USART3_UCLK_ID == 1)
+  #define RTE_USART3_UCLK_PORT          2
+  #define RTE_USART3_UCLK_BIT           7
+  #define RTE_USART3_UCLK_FUNC          2
+#elif    (RTE_USART3_UCLK_ID == 2)
+  #define RTE_USART3_UCLK_PORT          4
+  #define RTE_USART3_UCLK_BIT           0
+  #define RTE_USART3_UCLK_FUNC          6
+#elif    (RTE_USART3_UCLK_ID == 3)
+  #define RTE_USART3_UCLK_PORT          0xF
+  #define RTE_USART3_UCLK_BIT           5
+  #define RTE_USART3_UCLK_FUNC          1
+#else
+  #error "Invalid USART3_UCLK Pin Configuration!"
+#endif
+#ifndef   RTE_USART3_UCLK_PIN_EN
+  #define RTE_USART3_UCLK_PIN_EN        1
+#endif
+//   </h> Pin Configuration
+
+//   <h> DMA
+//     <e> Tx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>7 (DMAMUXPER7)  <1=>14 (DMAMUXPER14)
+//     </e>
+#define   RTE_USART3_DMA_TX_EN          0
+#define   RTE_USART3_DMA_TX_CH          0
+#define   RTE_USART3_DMA_TX_PERI_ID     0
+#if      (RTE_USART3_DMA_TX_PERI_ID == 0)
+  #define RTE_USART3_DMA_TX_PERI        7
+  #define RTE_USART3_DMA_TX_PERI_SEL    1
+#elif    (RTE_USART3_DMA_TX_PERI_ID == 1)
+  #define RTE_USART3_DMA_TX_PERI        14
+  #define RTE_USART3_DMA_TX_PERI_SEL    3
+#endif
+//     <e> Rx
+//       <o1> Channel    <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral <0=>8 (DMAMUXPER8)  <1=>13 (DMAMUXPER13)
+//     </e>
+#define   RTE_USART3_DMA_RX_EN          0
+#define   RTE_USART3_DMA_RX_CH          1
+#define   RTE_USART3_DMA_RX_PERI_ID     0
+#if      (RTE_USART3_DMA_RX_PERI_ID == 0)
+  #define RTE_USART3_DMA_RX_PERI        8
+  #define RTE_USART3_DMA_RX_PERI_SEL    1
+#elif    (RTE_USART3_DMA_RX_PERI_ID == 1)
+  #define RTE_USART3_DMA_RX_PERI        13
+  #define RTE_USART3_DMA_RX_PERI_SEL    3
+#endif
+//   </h> DMA
+// </e> USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3]
+
+// <e> SSP0 (Synchronous Serial Port 0) [Driver_SPI0]
+// <i> Configuration settings for Driver_SPI0 in component ::Drivers:SPI
+#define   RTE_SSP0                      0
+
+//   <h> Pin Configuration
+//     <o> SSP0_SSEL <0=>Not used <1=>P1_0 <2=>P3_6 <3=>P3_8 <4=>P9_0 <5=>PF_1
+//     <i> Slave Select for SSP0
+#define   RTE_SSP0_SSEL_PIN_SEL         1
+#if      (RTE_SSP0_SSEL_PIN_SEL == 0)
+#define   RTE_SSP0_SSEL_PIN_EN          0
+#elif    (RTE_SSP0_SSEL_PIN_SEL == 1)
+  #define RTE_SSP0_SSEL_PORT            1
+  #define RTE_SSP0_SSEL_BIT             0
+  #define RTE_SSP0_SSEL_FUNC            5
+  #define RTE_SSP0_SSEL_GPIO_FUNC       0
+  #define RTE_SSP0_SSEL_GPIO_PORT       0
+  #define RTE_SSP0_SSEL_GPIO_BIT        4
+#elif    (RTE_SSP0_SSEL_PIN_SEL == 2)
+  #define RTE_SSP0_SSEL_PORT            3
+  #define RTE_SSP0_SSEL_BIT             6
+  #define RTE_SSP0_SSEL_FUNC            2
+  #define RTE_SSP0_SSEL_GPIO_FUNC       0
+  #define RTE_SSP0_SSEL_GPIO_PORT       0
+  #define RTE_SSP0_SSEL_GPIO_BIT        6
+#elif    (RTE_SSP0_SSEL_PIN_SEL == 3)
+  #define RTE_SSP0_SSEL_PORT            3
+  #define RTE_SSP0_SSEL_BIT             8
+  #define RTE_SSP0_SSEL_FUNC            5
+  #define RTE_SSP0_SSEL_GPIO_FUNC       4
+  #define RTE_SSP0_SSEL_GPIO_PORT       5
+  #define RTE_SSP0_SSEL_GPIO_BIT        11
+#elif    (RTE_SSP0_SSEL_PIN_SEL == 4)
+  #define RTE_SSP0_SSEL_PORT            9
+  #define RTE_SSP0_SSEL_BIT             0
+  #define RTE_SSP0_SSEL_FUNC            7
+  #define RTE_SSP0_SSEL_GPIO_FUNC       0
+  #define RTE_SSP0_SSEL_GPIO_PORT       4
+  #define RTE_SSP0_SSEL_GPIO_BIT        12
+#elif    (RTE_SSP0_SSEL_PIN_SEL == 5)
+  #define RTE_SSP0_SSEL_PORT            0xF
+  #define RTE_SSP0_SSEL_BIT             1
+  #define RTE_SSP0_SSEL_FUNC            2
+  #define RTE_SSP0_SSEL_GPIO_FUNC       4
+  #define RTE_SSP0_SSEL_GPIO_PORT       7
+  #define RTE_SSP0_SSEL_GPIO_BIT        16
+#else
+  #error "Invalid SSP0 SSP0_SSEL Pin Configuration!"
+#endif
+#ifndef   RTE_SSP0_SSEL_PIN_EN
+#define   RTE_SSP0_SSEL_PIN_EN          1
+#endif
+//     <o> SSP0_SCK <0=>P3_0 <1=>P3_3 <2=>PF_0
+//     <i> Serial clock for SSP0
+#define   RTE_SSP0_SCK_PIN_SEL          0
+#if      (RTE_SSP0_SCK_PIN_SEL == 0)
+  #define RTE_SSP0_SCK_PORT             3
+  #define RTE_SSP0_SCK_BIT              0
+  #define RTE_SSP0_SCK_FUNC             4
+#elif    (RTE_SSP0_SCK_PIN_SEL == 1)
+  #define RTE_SSP0_SCK_PORT             3
+  #define RTE_SSP0_SCK_BIT              3
+  #define RTE_SSP0_SCK_FUNC             2
+#elif    (RTE_SSP0_SCK_PIN_SEL == 2)
+  #define RTE_SSP0_SCK_PORT             0xF
+  #define RTE_SSP0_SCK_BIT              0
+  #define RTE_SSP0_SCK_FUNC             0
+#else
+  #error "Invalid SSP0 SSP0_SCK Pin Configuration!"
+#endif
+//     <o> SSP0_MISO <0=>P1_1 <1=>P3_6 <2=>P3_7 <3=>P9_1 <4=>PF_2
+//     <i> Master In Slave Out for SSP0
+#define   RTE_SSP0_MISO_PIN_SEL         0
+#if      (RTE_SSP0_MISO_PIN_SEL == 0)
+  #define RTE_SSP0_MISO_PORT            1
+  #define RTE_SSP0_MISO_BIT             1
+  #define RTE_SSP0_MISO_FUNC            5
+#elif    (RTE_SSP0_MISO_PIN_SEL == 1)
+  #define RTE_SSP0_MISO_PORT            3
+  #define RTE_SSP0_MISO_BIT             6
+  #define RTE_SSP0_MISO_FUNC            5
+#elif    (RTE_SSP0_MISO_PIN_SEL == 2)
+  #define RTE_SSP0_MISO_PORT            3
+  #define RTE_SSP0_MISO_BIT             7
+  #define RTE_SSP0_MISO_FUNC            2
+#elif    (RTE_SSP0_MISO_PIN_SEL == 3)
+  #define RTE_SSP0_MISO_PORT            9
+  #define RTE_SSP0_MISO_BIT             1
+  #define RTE_SSP0_MISO_FUNC            7
+#elif    (RTE_SSP0_MISO_PIN_SEL == 4)
+  #define RTE_SSP0_MISO_PORT            0xF
+  #define RTE_SSP0_MISO_BIT             2
+  #define RTE_SSP0_MISO_FUNC            2
+#else
+  #error "Invalid SSP0 SSP0_MISO Pin Configuration!"
+#endif
+//     <o> SSP0_MOSI <0=>P1_2 <1=>P3_7 <2=>P3_8 <3=>P9_2 <4=>PF_3
+//     <i> Master Out Slave In for SSP0
+#define   RTE_SSP0_MOSI_PIN_SEL         0
+#if      (RTE_SSP0_MOSI_PIN_SEL == 0)
+  #define RTE_SSP0_MOSI_PORT            1
+  #define RTE_SSP0_MOSI_BIT             2
+  #define RTE_SSP0_MOSI_FUNC            5
+#elif    (RTE_SSP0_MOSI_PIN_SEL == 1)
+  #define RTE_SSP0_MOSI_PORT            3
+  #define RTE_SSP0_MOSI_BIT             7
+  #define RTE_SSP0_MOSI_FUNC            5
+#elif    (RTE_SSP0_MOSI_PIN_SEL == 2)
+  #define RTE_SSP0_MOSI_PORT            3
+  #define RTE_SSP0_MOSI_BIT             8
+  #define RTE_SSP0_MOSI_FUNC            2
+#elif    (RTE_SSP0_MOSI_PIN_SEL == 3)
+  #define RTE_SSP0_MOSI_PORT            9
+  #define RTE_SSP0_MOSI_BIT             2
+  #define RTE_SSP0_MOSI_FUNC            7
+#elif    (RTE_SSP0_MOSI_PIN_SEL == 4)
+  #define RTE_SSP0_MOSI_PORT            0xF
+  #define RTE_SSP0_MOSI_BIT             3
+  #define RTE_SSP0_MOSI_FUNC            2
+#else
+  #error "Invalid SSP0 SSP0_MOSI Pin Configuration!"
+#endif
+//   </h> Pin Configuration
+
+//   <h> DMA
+//     <e> Tx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>10 (DMAMUXPER10)
+//     </e>
+#define   RTE_SSP0_DMA_TX_EN            0
+#define   RTE_SSP0_DMA_TX_CH            0
+#define   RTE_SSP0_DMA_TX_PERI_ID       0
+#if      (RTE_SSP0_DMA_TX_PERI_ID == 0)
+  #define RTE_SSP0_DMA_TX_PERI          10
+  #define RTE_SSP0_DMA_TX_PERI_SEL      0
+#endif
+//     <e> Rx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>9 (DMAMUXPER9)
+//     </e>
+#define   RTE_SSP0_DMA_RX_EN            0
+#define   RTE_SSP0_DMA_RX_CH            1
+#define   RTE_SSP0_DMA_RX_PERI_ID       0
+#if      (RTE_SSP0_DMA_RX_PERI_ID == 0)
+  #define RTE_SSP0_DMA_RX_PERI          9
+  #define RTE_SSP0_DMA_RX_PERI_SEL      0
+#endif
+//   </h> DMA
+// </e> SSP0 (Synchronous Serial Port 0) [Driver_SPI0]
+
+// <e> SSP1 (Synchronous Serial Port 1) [Driver_SPI1]
+// <i> Configuration settings for Driver_SPI1 in component ::Drivers:SPI
+#define   RTE_SSP1                      0
+
+//   <h> Pin Configuration
+//     <o> SSP1_SSEL <0=>Not used <1=>P1_5 <2=>P1_20 <3=>PF_5
+//     <i> Slave Select for SSP1
+#define   RTE_SSP1_SSEL_PIN_SEL         1
+#if      (RTE_SSP1_SSEL_PIN_SEL == 0)
+  #define RTE_SSP1_SSEL_PIN_EN          0
+#elif    (RTE_SSP1_SSEL_PIN_SEL == 1)
+  #define RTE_SSP1_SSEL_PORT            1
+  #define RTE_SSP1_SSEL_BIT             5
+  #define RTE_SSP1_SSEL_FUNC            5
+  #define RTE_SSP1_SSEL_GPIO_FUNC       0
+  #define RTE_SSP1_SSEL_GPIO_PORT       1
+  #define RTE_SSP1_SSEL_GPIO_BIT        8
+#elif    (RTE_SSP1_SSEL_PIN_SEL == 2)
+  #define RTE_SSP1_SSEL_PORT            1
+  #define RTE_SSP1_SSEL_BIT             20
+  #define RTE_SSP1_SSEL_FUNC            1
+  #define RTE_SSP1_SSEL_GPIO_FUNC       0
+  #define RTE_SSP1_SSEL_GPIO_PORT       0
+  #define RTE_SSP1_SSEL_GPIO_BIT        15
+#elif    (RTE_SSP1_SSEL_PIN_SEL == 3)
+  #define RTE_SSP1_SSEL_PORT            0xF
+  #define RTE_SSP1_SSEL_BIT             5
+  #define RTE_SSP1_SSEL_FUNC            2
+  #define RTE_SSP1_SSEL_GPIO_FUNC       4
+  #define RTE_SSP1_SSEL_GPIO_PORT       7
+  #define RTE_SSP1_SSEL_GPIO_BIT        19
+#else
+  #error "Invalid SSP1 SSP1_SSEL Pin Configuration!"
+#endif
+#ifndef   RTE_SSP1_SSEL_PIN_EN
+#define   RTE_SSP1_SSEL_PIN_EN          1
+#endif
+//     <o> SSP1_SCK <0=>P1_19 <1=>PF_4 <2=>CLK0
+//     <i> Serial clock for SSP1
+#define   RTE_SSP1_SCK_PIN_SEL          0
+#if      (RTE_SSP1_SCK_PIN_SEL == 0)
+  #define RTE_SSP1_SCK_PORT             1
+  #define RTE_SSP1_SCK_BIT              19
+  #define RTE_SSP1_SCK_FUNC             1
+#elif    (RTE_SSP1_SCK_PIN_SEL == 1)
+  #define RTE_SSP1_SCK_PORT             0xF
+  #define RTE_SSP1_SCK_BIT              4
+  #define RTE_SSP1_SCK_FUNC             0
+#elif    (RTE_SSP1_SCK_PIN_SEL == 2)
+  #define RTE_SSP1_SCK_PORT             0x10
+  #define RTE_SSP1_SCK_BIT              0
+  #define RTE_SSP1_SCK_FUNC             6
+#else
+  #error "Invalid SSP1 SSP1_SCK Pin Configuration!"
+#endif
+//     <o> SSP1_MISO <0=>P0_0 <1=>P1_3 <2=>PF_6
+//     <i> Master In Slave Out for SSP1
+#define   RTE_SSP1_MISO_PIN_SEL         0
+#if      (RTE_SSP1_MISO_PIN_SEL == 0)
+  #define RTE_SSP1_MISO_PORT            0
+  #define RTE_SSP1_MISO_BIT             0
+  #define RTE_SSP1_MISO_FUNC            1
+#elif    (RTE_SSP1_MISO_PIN_SEL == 1)
+  #define RTE_SSP1_MISO_PORT            1
+  #define RTE_SSP1_MISO_BIT             3
+  #define RTE_SSP1_MISO_FUNC            5
+#elif    (RTE_SSP1_MISO_PIN_SEL == 2)
+  #define RTE_SSP1_MISO_PORT            0xF
+  #define RTE_SSP1_MISO_BIT             6
+  #define RTE_SSP1_MISO_FUNC            2
+#else
+  #error "Invalid SSP1 SSP1_MISO Pin Configuration!"
+#endif
+//     <o> SSP1_MOSI <0=>P0_1 <1=>P1_4 <2=>PF_7
+//     <i> Master Out Slave In for SSP1
+#define   RTE_SSP1_MOSI_PIN_SEL         0
+#if      (RTE_SSP1_MOSI_PIN_SEL == 0)
+  #define RTE_SSP1_MOSI_PORT            0
+  #define RTE_SSP1_MOSI_BIT             1
+  #define RTE_SSP1_MOSI_FUNC            1
+#elif    (RTE_SSP1_MOSI_PIN_SEL == 1)
+  #define RTE_SSP1_MOSI_PORT            1
+  #define RTE_SSP1_MOSI_BIT             4
+  #define RTE_SSP1_MOSI_FUNC            5
+#elif    (RTE_SSP1_MOSI_PIN_SEL == 2)
+  #define RTE_SSP1_MOSI_PORT            0xF
+  #define RTE_SSP1_MOSI_BIT             7
+  #define RTE_SSP1_MOSI_FUNC            2
+#else
+  #error "Invalid SSP1 SSP1_MOSI Pin Configuration!"
+#endif
+//   </h> Pin Configuration
+
+//   <h> DMA
+//     <e> Tx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>3 (DMAMUXPER3) <1=>5 (DMAMUXPER5) <2=>12 (DMAMUXPER12) <3=>14 (DMAMUXPER14)
+//     </e>
+#define   RTE_SSP1_DMA_TX_EN            0
+#define   RTE_SSP1_DMA_TX_CH            0
+#define   RTE_SSP1_DMA_TX_PERI_ID       0
+#if      (RTE_SSP1_DMA_TX_PERI_ID == 0)
+  #define RTE_SSP1_DMA_TX_PERI          3
+  #define RTE_SSP1_DMA_TX_PERI_SEL      3
+#elif    (RTE_SSP1_DMA_TX_PERI_ID == 1)
+  #define RTE_SSP1_DMA_TX_PERI          5
+  #define RTE_SSP1_DMA_TX_PERI_SEL      2
+#elif    (RTE_SSP1_DMA_TX_PERI_ID == 2)
+  #define RTE_SSP1_DMA_TX_PERI          12
+  #define RTE_SSP1_DMA_TX_PERI_SEL      0
+#elif    (RTE_SSP1_DMA_TX_PERI_ID == 3)
+  #define RTE_SSP1_DMA_TX_PERI          14
+  #define RTE_SSP1_DMA_TX_PERI_SEL      2
+#endif
+//     <e> Rx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>4 (DMAMUXPER4) <1=>6 (DMAMUXPER6) <2=>11 (DMAMUXPER11) <3=>13 (DMAMUXPER13)
+//     </e>
+#define   RTE_SSP1_DMA_RX_EN            0
+#define   RTE_SSP1_DMA_RX_CH            1
+#define   RTE_SSP1_DMA_RX_PERI_ID       0
+#if      (RTE_SSP1_DMA_RX_PERI_ID == 0)
+  #define RTE_SSP1_DMA_RX_PERI          4
+  #define RTE_SSP1_DMA_RX_PERI_SEL      3
+#elif    (RTE_SSP1_DMA_RX_PERI_ID == 1)
+  #define RTE_SSP1_DMA_RX_PERI          6
+  #define RTE_SSP1_DMA_RX_PERI_SEL      2
+#elif    (RTE_SSP1_DMA_RX_PERI_ID == 2)
+  #define RTE_SSP1_DMA_RX_PERI          11
+  #define RTE_SSP1_DMA_RX_PERI_SEL      0
+#elif    (RTE_SSP1_DMA_RX_PERI_ID == 3)
+  #define RTE_SSP1_DMA_RX_PERI          13
+  #define RTE_SSP1_DMA_RX_PERI_SEL      2
+#endif
+//   </h> DMA
+// </e> SSP1 (Synchronous Serial Port 1) [Driver_SPI1]
+
+// <e> I2S0 (Integrated Interchip Sound 0) [Driver_SAI0]
+// <i> Configuration settings for Driver_SAI0 in component ::Drivers:SAI
+#define   RTE_I2S0                      0
+
+//   <h> Pin Configuration
+//     <o> I2S0_RX_SCK <0=>Not used <1=>P3_0 <2=>P6_0 <3=>PF_4
+//     <i> Receive clock for I2S0
+#define   RTE_I2S0_RX_SCK_PIN_SEL       2
+#if      (RTE_I2S0_RX_SCK_PIN_SEL == 0)
+#define   RTE_I2S0_RX_SCK_PIN_EN        0
+#elif    (RTE_I2S0_RX_SCK_PIN_SEL == 1)
+  #define RTE_I2S0_RX_SCK_PORT          3
+  #define RTE_I2S0_RX_SCK_BIT           0
+  #define RTE_I2S0_RX_SCK_FUNC          0
+#elif    (RTE_I2S0_RX_SCK_PIN_SEL == 2)
+  #define RTE_I2S0_RX_SCK_PORT          6
+  #define RTE_I2S0_RX_SCK_BIT           0
+  #define RTE_I2S0_RX_SCK_FUNC          4
+#elif    (RTE_I2S0_RX_SCK_PIN_SEL == 3)
+  #define RTE_I2S0_RX_SCK_PORT          0xF
+  #define RTE_I2S0_RX_SCK_BIT           4
+  #define RTE_I2S0_RX_SCK_FUNC          7
+#else
+  #error "Invalid I2S0 I2S0_RX_SCK Pin Configuration!"
+#endif
+#ifndef   RTE_I2S0_RX_SCK_PIN_EN
+#define   RTE_I2S0_RX_SCK_PIN_EN        1
+#endif
+//     <o> I2S0_RX_WS <0=>Not used <1=>P3_1 <2=>P6_1
+//     <i> Receive word select for I2S0
+#define   RTE_I2S0_RX_WS_PIN_SEL        2
+#if      (RTE_I2S0_RX_WS_PIN_SEL == 0)
+#define   RTE_I2S0_RX_WS_PIN_EN         0
+#elif    (RTE_I2S0_RX_WS_PIN_SEL == 1)
+  #define RTE_I2S0_RX_WS_PORT           3
+  #define RTE_I2S0_RX_WS_BIT            1
+  #define RTE_I2S0_RX_WS_FUNC           1
+#elif    (RTE_I2S0_RX_WS_PIN_SEL == 2)
+  #define RTE_I2S0_RX_WS_PORT           6
+  #define RTE_I2S0_RX_WS_BIT            1
+  #define RTE_I2S0_RX_WS_FUNC           3
+#else
+  #error "Invalid I2S0 I2S0_RX_WS Pin Configuration!"
+#endif
+#ifndef   RTE_I2S0_RX_WS_PIN_EN
+#define   RTE_I2S0_RX_WS_PIN_EN         1
+#endif
+//     <o> I2S0_RX_SDA <0=>Not used <1=>P3_2 <2=>P6_2
+//     <i> Receive master clock for I2S0
+#define   RTE_I2S0_RX_SDA_PIN_SEL       2
+#if      (RTE_I2S0_RX_SDA_PIN_SEL == 0)
+#define   RTE_I2S0_RX_SDA_PIN_EN        0
+#elif    (RTE_I2S0_RX_SDA_PIN_SEL == 1)
+  #define RTE_I2S0_RX_SDA_PORT          3
+  #define RTE_I2S0_RX_SDA_BIT           2
+  #define RTE_I2S0_RX_SDA_FUNC          1
+#elif    (RTE_I2S0_RX_SDA_PIN_SEL == 2)
+  #define RTE_I2S0_RX_SDA_PORT          6
+  #define RTE_I2S0_RX_SDA_BIT           2
+  #define RTE_I2S0_RX_SDA_FUNC          3
+#else
+  #error "Invalid I2S0 I2S0_RX_SDA Pin Configuration!"
+#endif
+#ifndef   RTE_I2S0_RX_SDA_PIN_EN
+#define   RTE_I2S0_RX_SDA_PIN_EN       1
+#endif
+//     <o> I2S0_RX_MCLK <0=>Not used <1=>P1_19 <2=>P3_0 <3=>P6_0
+//     <i> Receive master clock for I2S0
+#define   RTE_I2S0_RX_MCLK_PIN_SEL      0
+#if      (RTE_I2S0_RX_MCLK_PIN_SEL == 0)
+#define   RTE_I2S0_RX_MCLK_PIN_EN       0
+#elif    (RTE_I2S0_RX_MCLK_PIN_SEL == 1)
+  #define RTE_I2S0_RX_MCLK_PORT         1
+  #define RTE_I2S0_RX_MCLK_BIT          19
+  #define RTE_I2S0_RX_MCLK_FUNC         6
+#elif    (RTE_I2S0_RX_MCLK_PIN_SEL == 2)
+  #define RTE_I2S0_RX_MCLK_PORT         3
+  #define RTE_I2S0_RX_MCLK_BIT          0
+  #define RTE_I2S0_RX_MCLK_FUNC         1
+#elif    (RTE_I2S0_RX_MCLK_PIN_SEL == 3)
+  #define RTE_I2S0_RX_MCLK_PORT         6
+  #define RTE_I2S0_RX_MCLK_BIT          0
+  #define RTE_I2S0_RX_MCLK_FUNC         1
+#else
+  #error "Invalid I2S0 I2S0_RX_MCLK Pin Configuration!"
+#endif
+#ifndef   RTE_I2S0_RX_MCLK_PIN_EN
+#define   RTE_I2S0_RX_MCLK_PIN_EN       1
+#endif
+//     <o> I2S0_TX_SCK <0=>Not used <1=>P3_0 <2=>P4_7
+//     <i> Transmit clock for I2S0
+#define   RTE_I2S0_TX_SCK_PIN_SEL       1
+#if      (RTE_I2S0_TX_SCK_PIN_SEL == 0)
+#define   RTE_I2S0_TX_SCK_PIN_EN        0
+#elif    (RTE_I2S0_TX_SCK_PIN_SEL == 1)
+  #define RTE_I2S0_TX_SCK_PORT          3
+  #define RTE_I2S0_TX_SCK_BIT           0
+  #define RTE_I2S0_TX_SCK_FUNC          2
+#elif    (RTE_I2S0_TX_SCK_PIN_SEL == 2)
+  #define RTE_I2S0_TX_SCK_PORT          4
+  #define RTE_I2S0_TX_SCK_BIT           7
+  #define RTE_I2S0_TX_SCK_FUNC          7
+#else
+  #error "Invalid I2S0 I2S0_TX_SCK Pin Configuration!"
+#endif
+#ifndef   RTE_I2S0_TX_SCK_PIN_EN
+#define   RTE_I2S0_TX_SCK_PIN_EN        1
+#endif
+//     <o> I2S0_TX_WS <0=>Not used <1=>P0_0 <2=>P3_1 <3=>P3_4 <4=>P7_1 <5=>P9_1 <6=>PC_13
+//     <i> Transmit word select for I2S0
+#define   RTE_I2S0_TX_WS_PIN_SEL        4
+#if      (RTE_I2S0_TX_WS_PIN_SEL == 0)
+#define   RTE_I2S0_TX_WS_PIN_EN         0
+#elif    (RTE_I2S0_TX_WS_PIN_SEL == 1)
+  #define RTE_I2S0_TX_WS_PORT           0
+  #define RTE_I2S0_TX_WS_BIT            0
+  #define RTE_I2S0_TX_WS_FUNC           6
+#elif    (RTE_I2S0_TX_WS_PIN_SEL == 2)
+  #define RTE_I2S0_TX_WS_PORT           3
+  #define RTE_I2S0_TX_WS_BIT            1
+  #define RTE_I2S0_TX_WS_FUNC           0
+#elif    (RTE_I2S0_TX_WS_PIN_SEL == 3)
+  #define RTE_I2S0_TX_WS_PORT           3
+  #define RTE_I2S0_TX_WS_BIT            4
+  #define RTE_I2S0_TX_WS_FUNC           5
+#elif    (RTE_I2S0_TX_WS_PIN_SEL == 4)
+  #define RTE_I2S0_TX_WS_PORT           7
+  #define RTE_I2S0_TX_WS_BIT            1
+  #define RTE_I2S0_TX_WS_FUNC           2
+#elif    (RTE_I2S0_TX_WS_PIN_SEL == 5)
+  #define RTE_I2S0_TX_WS_PORT           9
+  #define RTE_I2S0_TX_WS_BIT            1
+  #define RTE_I2S0_TX_WS_FUNC           4
+#elif    (RTE_I2S0_TX_WS_PIN_SEL == 6)
+  #define RTE_I2S0_TX_WS_PORT           0xC
+  #define RTE_I2S0_TX_WS_BIT            13
+  #define RTE_I2S0_TX_WS_FUNC           6
+#else
+  #error "Invalid I2S0 I2S0_TX_WS Pin Configuration!"
+#endif
+#ifndef   RTE_I2S0_TX_WS_PIN_EN
+#define   RTE_I2S0_TX_WS_PIN_EN         1
+#endif
+//     <o> I2S0_TX_SDA <0=>Not used <1=>P3_2 <2=>P3_5 <3=>P7_2 <4=>P9_2  <5=>PC_12
+//     <i> Transmit data for I2S0
+#define   RTE_I2S0_TX_SDA_PIN_SEL       3
+#if      (RTE_I2S0_TX_SDA_PIN_SEL == 0)
+#define   RTE_I2S0_TX_SDA_PIN_EN        0
+#elif    (RTE_I2S0_TX_SDA_PIN_SEL == 1)
+  #define RTE_I2S0_TX_SDA_PORT          3
+  #define RTE_I2S0_TX_SDA_BIT           2
+  #define RTE_I2S0_TX_SDA_FUNC          0
+#elif    (RTE_I2S0_TX_SDA_PIN_SEL == 2)
+  #define RTE_I2S0_TX_SDA_PORT          3
+  #define RTE_I2S0_TX_SDA_BIT           5
+  #define RTE_I2S0_TX_SDA_FUNC          5
+#elif    (RTE_I2S0_TX_SDA_PIN_SEL == 3)
+  #define RTE_I2S0_TX_SDA_PORT          7
+  #define RTE_I2S0_TX_SDA_BIT           2
+  #define RTE_I2S0_TX_SDA_FUNC          2
+#elif    (RTE_I2S0_TX_SDA_PIN_SEL == 4)
+  #define RTE_I2S0_TX_SDA_PORT          9
+  #define RTE_I2S0_TX_SDA_BIT           2
+  #define RTE_I2S0_TX_SDA_FUNC          4
+#elif    (RTE_I2S0_TX_SDA_PIN_SEL == 5)
+  #define RTE_I2S0_TX_SDA_PORT          0xC
+  #define RTE_I2S0_TX_SDA_BIT           12
+  #define RTE_I2S0_TX_SDA_FUNC          6
+#else
+  #error "Invalid I2S0 I2S0_TX_SDA Pin Configuration!"
+#endif
+#ifndef   RTE_I2S0_TX_SDA_PIN_EN
+#define   RTE_I2S0_TX_SDA_PIN_EN        1
+#endif
+//     <o> I2S0_TX_MCLK <0=>Not used <1=>P3_0 <2=>P3_3 <3=>PF_4 <4=>CLK2
+//     <i> Transmit master clock for I2S0
+#define   RTE_I2S0_TX_MCLK_PIN_SEL      2
+#if      (RTE_I2S0_TX_MCLK_PIN_SEL == 0)
+#define   RTE_I2S0_TX_MCLK_PIN_EN       0
+#elif    (RTE_I2S0_TX_MCLK_PIN_SEL == 1)
+  #define RTE_I2S0_TX_MCLK_PORT         3
+  #define RTE_I2S0_TX_MCLK_BIT          0
+  #define RTE_I2S0_TX_MCLK_FUNC         3
+#elif    (RTE_I2S0_TX_MCLK_PIN_SEL == 2)
+  #define RTE_I2S0_TX_MCLK_PORT         3
+  #define RTE_I2S0_TX_MCLK_BIT          3
+  #define RTE_I2S0_TX_MCLK_FUNC         6
+#elif    (RTE_I2S0_TX_MCLK_PIN_SEL == 3)
+  #define RTE_I2S0_TX_MCLK_PORT         0xf
+  #define RTE_I2S0_TX_MCLK_BIT          4
+  #define RTE_I2S0_TX_MCLK_FUNC         6
+#elif    (RTE_I2S0_TX_MCLK_PIN_SEL == 4)
+  #define RTE_I2S0_TX_MCLK_PORT         0x10
+  #define RTE_I2S0_TX_MCLK_BIT          2
+  #define RTE_I2S0_TX_MCLK_FUNC         6
+#else
+  #error "Invalid I2S0 I2S0_TX_MCLK Pin Configuration!"
+#endif
+#ifndef   RTE_I2S0_TX_MCLK_PIN_EN
+#define   RTE_I2S0_TX_MCLK_PIN_EN       1
+#endif
+//   </h> Pin Configuration
+
+//   <h> DMA
+//     <e> Tx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>9 (DMAMUXPER9)
+//     </e>
+#define   RTE_I2S0_DMA_TX_EN            0
+#define   RTE_I2S0_DMA_TX_CH            0
+#define   RTE_I2S0_DMA_TX_PERI_ID       0
+#if      (RTE_I2S0_DMA_TX_PERI_ID == 0)
+  #define RTE_I2S0_DMA_TX_PERI          9
+  #define RTE_I2S0_DMA_TX_PERI_SEL      1
+#endif
+//     <e> Rx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>10 (DMAMUXPER10)
+//     </e>
+#define   RTE_I2S0_DMA_RX_EN            0
+#define   RTE_I2S0_DMA_RX_CH            1
+#define   RTE_I2S0_DMA_RX_PERI_ID       0
+#if      (RTE_I2S0_DMA_RX_PERI_ID == 0)
+  #define RTE_I2S0_DMA_RX_PERI          10
+  #define RTE_I2S0_DMA_RX_PERI_SEL      1
+#endif
+//   </h> DMA
+// </e> I2S0 (Integrated Interchip Sound 0) [Driver_SAI0]
+
+// <e> I2S1 (Integrated Interchip Sound 1) [Driver_SAI1]
+// <i> Configuration settings for Driver_I2S1 in component ::Drivers:SAI
+#define   RTE_I2S1                      0
+
+//   <h> Pin Configuration
+//     <o> I2S1_RX_SCK <0=>Not used <1=>CLK2 <2=>CLK3
+//     <i> Receive clock for I2S1
+#define   RTE_I2S1_RX_SCK_PIN_SEL       0
+#if      (RTE_I2S1_RX_SCK_PIN_SEL == 0)
+#define   RTE_I2S1_RX_SCK_PIN_EN        0
+#elif    (RTE_I2S1_RX_SCK_PIN_SEL == 1)
+  #define RTE_I2S1_RX_SCK_PORT          0x10
+  #define RTE_I2S1_RX_SCK_BIT           2
+  #define RTE_I2S1_RX_SCK_FUNC          7
+#elif    (RTE_I2S1_RX_SCK_PIN_SEL == 2)
+  #define RTE_I2S1_RX_SCK_PORT          0x10
+  #define RTE_I2S1_RX_SCK_BIT           3
+  #define RTE_I2S1_RX_SCK_FUNC          7
+#else
+  #error "Invalid I2S1 I2S1_RX_SCK Pin Configuration!"
+#endif
+#ifndef   RTE_I2S1_RX_SCK_PIN_EN
+#define   RTE_I2S1_RX_SCK_PIN_EN        1
+#endif
+//     <o> I2S1_RX_WS <0=>Not used <1=>P3_5
+//     <i> Receive word select for I2S1
+#define   RTE_I2S1_RX_WS_PIN_SEL        0
+#if      (RTE_I2S1_RX_WS_PIN_SEL == 0)
+#define   RTE_I2S1_RX_WS_PIN_EN         0
+#elif    (RTE_I2S1_RX_WS_PIN_SEL == 1)
+  #define RTE_I2S1_RX_WS_PORT           3
+  #define RTE_I2S1_RX_WS_BIT            5
+  #define RTE_I2S1_RX_WS_FUNC           6
+#else
+  #error "Invalid I2S1 I2S1_RX_WS Pin Configuration!"
+#endif
+#ifndef   RTE_I2S1_RX_WS_PIN_EN
+#define   RTE_I2S1_RX_WS_PIN_EN         1
+#endif
+//     <o> I2S1_RX_SDA <0=>Not used <1=>P3_4
+//     <i> Receive master clock for I2S1
+#define   RTE_I2S1_RX_SDA_PIN_SEL       0
+#if      (RTE_I2S1_RX_SDA_PIN_SEL == 0)
+#define   RTE_I2S1_RX_SDA_PIN_EN        0
+#elif    (RTE_I2S1_RX_SDA_PIN_SEL == 1)
+  #define RTE_I2S1_RX_SDA_PORT          3
+  #define RTE_I2S1_RX_SDA_BIT           4
+  #define RTE_I2S1_RX_SDA_FUNC          6
+#else
+  #error "Invalid I2S1 I2S1_RX_SDA Pin Configuration!"
+#endif
+#ifndef   RTE_I2S1_RX_SDA_PIN_EN
+#define   RTE_I2S1_RX_SDA_PIN_EN       1
+#endif
+//     <o> I2S1_RX_MCLK <0=>Not used <1=>PA_0
+//     <i> Receive master clock for I2S1
+#define   RTE_I2S1_RX_MCLK_PIN_SEL      0
+#if      (RTE_I2S1_RX_MCLK_PIN_SEL == 0)
+#define   RTE_I2S1_RX_MCLK_PIN_EN       0
+#elif    (RTE_I2S1_RX_MCLK_PIN_SEL == 1)
+  #define RTE_I2S1_RX_MCLK_PORT         0x0A
+  #define RTE_I2S1_RX_MCLK_BIT          0
+  #define RTE_I2S1_RX_MCLK_FUNC         5
+#else
+  #error "Invalid I2S1 I2S1_RX_MCLK Pin Configuration!"
+#endif
+#ifndef   RTE_I2S1_RX_MCLK_PIN_EN
+#define   RTE_I2S1_RX_MCLK_PIN_EN       1
+#endif
+//     <o> I2S1_TX_SCK <0=>Not used <1=>P1_19 <2=>P3_3 <3=>P4_7
+//     <i> Transmit clock for I2S1
+#define   RTE_I2S1_TX_SCK_PIN_SEL       0
+#if      (RTE_I2S1_TX_SCK_PIN_SEL == 0)
+#define   RTE_I2S1_TX_SCK_PIN_EN        0
+#elif    (RTE_I2S1_TX_SCK_PIN_SEL == 1)
+  #define RTE_I2S1_TX_SCK_PORT          1
+  #define RTE_I2S1_TX_SCK_BIT           19
+  #define RTE_I2S1_TX_SCK_FUNC          7
+#elif    (RTE_I2S1_TX_SCK_PIN_SEL == 2)
+  #define RTE_I2S1_TX_SCK_PORT          3
+  #define RTE_I2S1_TX_SCK_BIT           3
+  #define RTE_I2S1_TX_SCK_FUNC          7
+#elif    (RTE_I2S1_TX_SCK_PIN_SEL == 3)
+  #define RTE_I2S1_TX_SCK_PORT          4
+  #define RTE_I2S1_TX_SCK_BIT           7
+  #define RTE_I2S1_TX_SCK_FUNC          6
+#else
+  #error "Invalid I2S1 I2S1_TX_SCK Pin Configuration!"
+#endif
+#ifndef   RTE_I2S1_TX_SCK_PIN_EN
+#define   RTE_I2S1_TX_SCK_PIN_EN        1
+#endif
+//     <o> I2S1_TX_WS <0=>Not used <1=>P0_0 <2=>PF_7
+//     <i> Transmit word select for I2S1
+#define   RTE_I2S1_TX_WS_PIN_SEL        0
+#if      (RTE_I2S1_TX_WS_PIN_SEL == 0)
+#define   RTE_I2S1_TX_WS_PIN_EN         0
+#elif    (RTE_I2S1_TX_WS_PIN_SEL == 1)
+  #define RTE_I2S1_TX_WS_PORT           0
+  #define RTE_I2S1_TX_WS_BIT            0
+  #define RTE_I2S1_TX_WS_FUNC           7
+#elif    (RTE_I2S1_TX_WS_PIN_SEL == 2)
+  #define RTE_I2S1_TX_WS_PORT           0x0F
+  #define RTE_I2S1_TX_WS_BIT            7
+  #define RTE_I2S1_TX_WS_FUNC           7
+#else
+  #error "Invalid I2S1 I2S1_TX_WS Pin Configuration!"
+#endif
+#ifndef   RTE_I2S1_TX_WS_PIN_EN
+#define   RTE_I2S1_TX_WS_PIN_EN         1
+#endif
+//     <o> I2S1_TX_SDA <0=>Not used <1=>P0_1 <2=>PF_6
+//     <i> Transmit data for I2S
+#define   RTE_I2S1_TX_SDA_PIN_SEL       0
+#if      (RTE_I2S1_TX_SDA_PIN_SEL == 0)
+#define   RTE_I2S1_TX_SDA_PIN_EN        0
+#elif    (RTE_I2S1_TX_SDA_PIN_SEL == 1)
+  #define RTE_I2S1_TX_SDA_PORT          0
+  #define RTE_I2S1_TX_SDA_BIT           1
+  #define RTE_I2S1_TX_SDA_FUNC          7
+#elif    (RTE_I2S1_TX_SDA_PIN_SEL == 2)
+  #define RTE_I2S1_TX_SDA_PORT          0x0F
+  #define RTE_I2S1_TX_SDA_BIT           6
+  #define RTE_I2S1_TX_SDA_FUNC          7
+#else
+  #error "Invalid I2S1 I2S1_TX_SDA Pin Configuration!"
+#endif
+#ifndef   RTE_I2S1_TX_SDA_PIN_EN
+#define   RTE_I2S1_TX_SDA_PIN_EN        1
+#endif
+//     <o> I2S1_TX_MCLK <0=>Not used <1=>P8_8 <2=>PF_0 <3=>CLK1
+//     <i> Transmit master clock for I2S1
+#define   RTE_I2S1_TX_MCLK_PIN_SEL      0
+#if      (RTE_I2S1_TX_MCLK_PIN_SEL == 0)
+#define   RTE_I2S1_TX_MCLK_PIN_EN       0
+#elif    (RTE_I2S1_TX_MCLK_PIN_SEL == 1)
+  #define RTE_I2S1_TX_MCLK_PORT         8
+  #define RTE_I2S1_TX_MCLK_BIT          8
+  #define RTE_I2S1_TX_MCLK_FUNC         7
+#elif    (RTE_I2S1_TX_MCLK_PIN_SEL == 2)
+  #define RTE_I2S1_TX_MCLK_PORT         0x0F
+  #define RTE_I2S1_TX_MCLK_BIT          0
+  #define RTE_I2S1_TX_MCLK_FUNC         7
+#elif    (RTE_I2S1_TX_MCLK_PIN_SEL == 3)
+  #define RTE_I2S1_TX_MCLK_PORT         0x10
+  #define RTE_I2S1_TX_MCLK_BIT          1
+  #define RTE_I2S1_TX_MCLK_FUNC         7
+#else
+  #error "Invalid I2S1 I2S1_TX_MCLK Pin Configuration!"
+#endif
+#ifndef   RTE_I2S1_TX_MCLK_PIN_EN
+#define   RTE_I2S1_TX_MCLK_PIN_EN       1
+#endif
+//   </h> Pin Configuration
+
+//   <h> DMA
+//     <e> Tx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>3 (DMAMUXPER3)
+//     </e>
+#define   RTE_I2S1_DMA_TX_EN            0
+#define   RTE_I2S1_DMA_TX_CH            0
+#define   RTE_I2S1_DMA_TX_PERI_ID       0
+#if      (RTE_I2S1_DMA_TX_PERI_ID == 0)
+  #define RTE_I2S1_DMA_TX_PERI          3
+  #define RTE_I2S1_DMA_TX_PERI_SEL      2
+#endif
+//     <e> Rx
+//       <o1> Channel     <0=>0 <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
+//       <o2> Peripheral  <0=>4 (DMAMUXPER4)
+//     </e>
+#define   RTE_I2S1_DMA_RX_EN            0
+#define   RTE_I2S1_DMA_RX_CH            1
+#define   RTE_I2S1_DMA_RX_PERI_ID       0
+#if      (RTE_I2S1_DMA_RX_PERI_ID == 0)
+  #define RTE_I2S1_DMA_RX_PERI          4
+  #define RTE_I2S1_DMA_RX_PERI_SEL      2
+#endif
+//   </h> DMA
+// </e> I2S1 (Integrated Interchip Sound 1) [Driver_SAI1]
+
+// <e> CAN0 Controller [Driver_CAN0]
+// <i> Configuration settings for Driver_CAN0 in component ::Drivers:CAN
+#define   RTE_CAN_CAN0                  0
+
+//   <h> Pin Configuration
+//     <o> CAN0_RD <0=>Not used <1=>P3_1 <2=>PE_2
+//     <i> CAN0 receiver input.
+#define   RTE_CAN0_RD_ID                0
+#if      (RTE_CAN0_RD_ID == 0)
+  #define RTE_CAN0_RD_PIN_EN            0
+#elif    (RTE_CAN0_RD_ID == 1)
+  #define RTE_CAN0_RD_PORT              3
+  #define RTE_CAN0_RD_BIT               1
+  #define RTE_CAN0_RD_FUNC              2
+#elif    (RTE_CAN0_RD_ID == 2)
+  #define RTE_CAN0_RD_PORT              0xE
+  #define RTE_CAN0_RD_BIT               2
+  #define RTE_CAN0_RD_FUNC              1
+#else
+  #error "Invalid RTE_CAN0_RD Pin Configuration!"
+#endif
+#ifndef   RTE_CAN0_RD_PIN_EN
+  #define RTE_CAN0_RD_PIN_EN            1
+#endif
+//     <o> CAN0_TD <0=>Not used <1=>P3_2 <2=>PE_3
+//     <i> CAN0 transmitter output.
+#define   RTE_CAN0_TD_ID                0
+#if      (RTE_CAN0_TD_ID == 0)
+  #define RTE_CAN0_TD_PIN_EN            0
+#elif    (RTE_CAN0_TD_ID == 1)
+  #define RTE_CAN0_TD_PORT              3
+  #define RTE_CAN0_TD_BIT               2
+  #define RTE_CAN0_TD_FUNC              2
+#elif    (RTE_CAN0_TD_ID == 2)
+  #define RTE_CAN0_TD_PORT              0xE
+  #define RTE_CAN0_TD_BIT               3
+  #define RTE_CAN0_TD_FUNC              1
+#else
+  #error "Invalid RTE_CAN0_TD Pin Configuration!"
+#endif
+#ifndef   RTE_CAN0_TD_PIN_EN
+  #define RTE_CAN0_TD_PIN_EN            1
+#endif
+//   </h> Pin Configuration
+// </e> CAN0 Controller [Driver_CAN0]
+
+// <e> CAN1 Controller [Driver_CAN1]
+// <i> Configuration settings for Driver_CAN1 in component ::Drivers:CAN
+#define   RTE_CAN_CAN1                  0
+
+//   <h> Pin Configuration
+//     <o> CAN1_RD <0=>Not used <1=>P1_18 <2=>P4_9 <3=>PE_1
+//     <i> CAN1 receiver input.
+#define   RTE_CAN1_RD_ID                0
+#if      (RTE_CAN1_RD_ID == 0)
+  #define RTE_CAN1_RD_PIN_EN            0
+#elif    (RTE_CAN1_RD_ID == 1)
+  #define RTE_CAN1_RD_PORT              1
+  #define RTE_CAN1_RD_BIT               18
+  #define RTE_CAN1_RD_FUNC              5
+#elif    (RTE_CAN1_RD_ID == 2)
+  #define RTE_CAN1_RD_PORT              4
+  #define RTE_CAN1_RD_BIT               9
+  #define RTE_CAN1_RD_FUNC              6
+#elif    (RTE_CAN1_RD_ID == 3)
+  #define RTE_CAN1_RD_PORT              0xE
+  #define RTE_CAN1_RD_BIT               1
+  #define RTE_CAN1_RD_FUNC              5
+#else
+  #error "Invalid RTE_CAN1_RD Pin Configuration!"
+#endif
+#ifndef   RTE_CAN1_RD_PIN_EN
+  #define RTE_CAN1_RD_PIN_EN            1
+#endif
+//     <o> CAN1_TD <0=>Not used <1=>P1_17 <2=>P4_8 <3=>PE_0
+//     <i> CAN1 transmitter output.
+#define   RTE_CAN1_TD_ID                0
+#if      (RTE_CAN1_TD_ID == 0)
+  #define RTE_CAN1_TD_PIN_EN            0
+#elif    (RTE_CAN1_TD_ID == 1)
+  #define RTE_CAN1_TD_PORT              1
+  #define RTE_CAN1_TD_BIT               17
+  #define RTE_CAN1_TD_FUNC              5
+#elif    (RTE_CAN1_TD_ID == 2)
+  #define RTE_CAN1_TD_PORT              4
+  #define RTE_CAN1_TD_BIT               8
+  #define RTE_CAN1_TD_FUNC              6
+#elif    (RTE_CAN1_TD_ID == 3)
+  #define RTE_CAN1_TD_PORT              0xE
+  #define RTE_CAN1_TD_BIT               0
+  #define RTE_CAN1_TD_FUNC              5
+#else
+  #error "Invalid RTE_CAN1_TD Pin Configuration!"
+#endif
+#ifndef   RTE_CAN1_TD_PIN_EN
+  #define RTE_CAN1_TD_PIN_EN            1
+#endif
+//   </h> Pin Configuration
+// </e> CAN1 Controller [Driver_CAN1]
+
+
+#endif  /* __RTE_DEVICE_H */

CMSIS/Pack/Example/CMSIS_Driver/EMAC_LPC18xx.c

@@ -0,0 +1,1087 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        02. March 2016
+ * $Revision:    V2.6
+ *
+ * Driver:       Driver_ETH_MAC0
+ * Configured:   via RTE_Device.h configuration file
+ * Project:      Ethernet Media Access (MAC) Driver for NXP LPC18xx
+ * --------------------------------------------------------------------------
+ * Use the following configuration settings in the middleware component
+ * to connect to this driver.
+ *
+ *   Configuration Setting                     Value
+ *   ---------------------                     -----
+ *   Connect to hardware via Driver_ETH_MAC# = 0
+ * -------------------------------------------------------------------------- */
+
+/* History:
+ *  Version 2.6
+ *    - Corrected PowerControl function for conditional Power full (driver must be initialized)
+ *  Version 2.5
+ *    - Corrected return value of the ReadFrame function
+ *  Version 2.4
+ *    - Updated initialization, uninitialization and power procedures
+ *  Version 2.3
+ *    - Corrected return value of PHY_Read and PHY_Write functions on timeout
+ *  Version 2.2
+ *    - GetMacAddress function implemented in Ethernet driver
+ *  Version 2.1
+ *    - Added Sleep mode and Wake-up on Magic Packet 
+ *    - Improved robustness and error control
+ *    - Added CLK0 pin option support
+ *  Version 2.0
+ *    - Based on API V2.00
+ *    - Added multicast MAC address filtering
+ *  Version 1.1
+ *    - Based on API V1.10 (namespace prefix ARM_ added)
+ *  Version 1.0
+ *    - Initial release
+ */
+
+/* IEEE 1588 time stamping enable (PTP) */
+#ifndef EMAC_TIME_STAMP
+#define EMAC_TIME_STAMP         0
+#endif
+
+#include "EMAC_LPC18xx.h"
+
+#define ARM_ETH_MAC_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,6) /* driver version */
+
+/* Timeouts */
+#define PHY_TIMEOUT         200         /* PHY Register access timeout in us  */
+
+/* EMAC Memory Buffer configuration */
+#define NUM_RX_BUF          4           /* 0x1800 for Rx (4*1536=6K)          */
+#define NUM_TX_BUF          2           /* 0x0C00 for Tx (2*1536=3K)          */
+#define ETH_BUF_SIZE        1536        /* ETH Receive/Transmit buffer size   */
+
+/* EMAC core clock (system_LPC43xx.c) */
+extern uint32_t GetClockFreq (uint32_t clk_src);
+
+/* Ethernet Pin definitions */
+static const PIN_ID eth_pins[] = {
+  { RTE_ENET_MDI_MDC_PORT,     RTE_ENET_MDI_MDC_PIN,                   SCU_SFS_EZI | RTE_ENET_MDI_MDC_FUNC       },
+  { RTE_ENET_MDI_MDIO_PORT,    RTE_ENET_MDI_MDIO_PIN,    SCU_SFS_EHS | SCU_SFS_EZI | RTE_ENET_MDI_MDIO_FUNC      },
+#if (RTE_ENET_RMII)
+  { RTE_ENET_RMII_TXD0_PORT,   RTE_ENET_RMII_TXD0_PIN,   SCU_SFS_EHS | SCU_SFS_EZI | RTE_ENET_RMII_TXD0_FUNC     },
+  { RTE_ENET_RMII_TXD1_PORT,   RTE_ENET_RMII_TXD1_PIN,   SCU_SFS_EHS | SCU_SFS_EZI | RTE_ENET_RMII_TXD1_FUNC     },
+  { RTE_ENET_RMII_TX_EN_PORT,  RTE_ENET_RMII_TX_EN_PIN,  SCU_SFS_EHS | SCU_SFS_EZI | RTE_ENET_RMII_TX_EN_FUNC    },
+  { RTE_ENET_RMII_REF_CLK_PORT,RTE_ENET_RMII_REF_CLK_PIN,SCU_SFS_EHS | SCU_SFS_EZI | RTE_ENET_RMII_REF_CLK_FUNC  },
+  { RTE_ENET_RMII_RXD0_PORT,   RTE_ENET_RMII_RXD0_PIN,   SCU_SFS_EHS | SCU_SFS_EZI | RTE_ENET_RMII_RXD0_FUNC     },
+  { RTE_ENET_RMII_RXD1_PORT,   RTE_ENET_RMII_RXD1_PIN,   SCU_SFS_EHS | SCU_SFS_EZI | RTE_ENET_RMII_RXD1_FUNC     },
+  { RTE_ENET_RMII_RX_DV_PORT,  RTE_ENET_RMII_RX_DV_PIN,  SCU_SFS_EHS | SCU_SFS_EZI | RTE_ENET_RMII_RX_DV_FUNC    }
+#endif
+#if (RTE_ENET_MII)
+  { RTE_ENET_MII_TXD0_PORT,    RTE_ENET_MII_TXD0_PIN,    SCU_SFS_EHS | SCU_SFS_EZI | RTE_ENET_MII_TXD0_FUNC      },
+  { RTE_ENET_MII_TXD1_PORT,    RTE_ENET_MII_TXD1_PIN,    SCU_SFS_EHS | SCU_SFS_EZI | RTE_ENET_MII_TXD1_FUNC      },
+  { RTE_ENET_MII_TXD2_PORT,    RTE_ENET_MII_TXD2_PIN,    SCU_SFS_EHS | SCU_SFS_EZI | RTE_ENET_MII_TXD2_FUNC      },
+  { RTE_ENET_MII_TXD3_PORT,    RTE_ENET_MII_TXD3_PIN,    SCU_SFS_EHS | SCU_SFS_EZI | RTE_ENET_MII_TXD3_FUNC      },
+  { RTE_ENET_MII_TX_EN_PORT,   RTE_ENET_MII_TX_EN_PIN,   SCU_SFS_EHS | SCU_SFS_EZI | RTE_ENET_MII_TX_EN_FUNC     },
+  { RTE_ENET_MII_TX_CLK_PORT,  RTE_ENET_MII_TX_CLK_PIN,  SCU_SFS_EHS | SCU_SFS_EZI | RTE_ENET_MII_TX_CLK_FUNC    },
+#if (RTE_ENET_MII_TX_ER_PIN_EN)
+  { RTE_ENET_MII_TX_ER_PORT,   RTE_ENET_MII_TX_ER_PIN,   SCU_SFS_EHS | SCU_SFS_EZI | RTE_ENET_MII_TX_ER_FUNC     },
+#endif
+  { RTE_ENET_MII_RXD0_PORT,    RTE_ENET_MII_RXD0_PIN,    SCU_SFS_EHS | SCU_SFS_EZI | RTE_ENET_MII_RXD0_FUNC      },
+  { RTE_ENET_MII_RXD1_PORT,    RTE_ENET_MII_RXD1_PIN,    SCU_SFS_EHS | SCU_SFS_EZI | RTE_ENET_MII_RXD1_FUNC      },
+  { RTE_ENET_MII_RXD2_PORT,    RTE_ENET_MII_RXD2_PIN,    SCU_SFS_EHS | SCU_SFS_EZI | RTE_ENET_MII_RXD2_FUNC      },
+  { RTE_ENET_MII_RXD3_PORT,    RTE_ENET_MII_RXD3_PIN,    SCU_SFS_EHS | SCU_SFS_EZI | RTE_ENET_MII_RXD3_FUNC      },
+  { RTE_ENET_MII_RX_DV_PORT,   RTE_ENET_MII_RX_DV_PIN,   SCU_SFS_EHS | SCU_SFS_EZI | RTE_ENET_MII_RX_DV_FUNC     },
+  { RTE_ENET_MII_RX_CLK_PORT,  RTE_ENET_MII_RX_CLK_PIN,  SCU_SFS_EHS | SCU_SFS_EZI | RTE_ENET_MII_RX_CLK_FUNC    },
+  { RTE_ENET_MII_RX_ER_PORT,   RTE_ENET_MII_RX_ER_PIN,   SCU_SFS_EHS | SCU_SFS_EZI | RTE_ENET_MII_RX_ER_FUNC     },
+  { RTE_ENET_MII_COL_PORT,     RTE_ENET_MII_COL_PIN,     SCU_SFS_EHS | SCU_SFS_EZI | RTE_ENET_MII_COL_FUNC       },
+  { RTE_ENET_MII_CRS_PORT,     RTE_ENET_MII_CRS_PIN,     SCU_SFS_EHS | SCU_SFS_EZI | RTE_ENET_MII_CRS_FUNC       },
+#endif
+};
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = {
+  ARM_ETH_MAC_API_VERSION,
+  ARM_ETH_MAC_DRV_VERSION
+};
+
+/* Driver Capabilities */
+static const ARM_ETH_MAC_CAPABILITIES DriverCapabilities = {
+  0,                                /* checksum_offload_rx_ip4  */
+  0,                                /* checksum_offload_rx_ip6  */
+  0,                                /* checksum_offload_rx_udp  */
+  0,                                /* checksum_offload_rx_tcp  */
+  0,                                /* checksum_offload_rx_icmp */
+  0,                                /* checksum_offload_tx_ip4  */
+  0,                                /* checksum_offload_tx_ip6  */
+  0,                                /* checksum_offload_tx_udp  */
+  0,                                /* checksum_offload_tx_tcp  */
+  0,                                /* checksum_offload_tx_icmp */
+  (RTE_ENET_RMII) ?
+  ARM_ETH_INTERFACE_RMII :
+  ARM_ETH_INTERFACE_MII,            /* media_interface          */
+  0,                                /* mac_address              */
+  1,                                /* event_rx_frame           */
+  1,                                /* event_tx_frame           */
+  1,                                /* event_wakeup             */
+  (EMAC_TIME_STAMP) ? 1 : 0         /* precision_timer          */
+};
+
+/* Local variables */
+static EMAC_CTRL  emac_control = { 0 };
+#define emac     (emac_control)
+static RX_Desc   rx_desc[NUM_RX_BUF];
+static TX_Desc   tx_desc[NUM_TX_BUF];
+static uint32_t  rx_buf [NUM_RX_BUF][ETH_BUF_SIZE>>2];
+static uint32_t  tx_buf [NUM_TX_BUF][ETH_BUF_SIZE>>2];
+
+/* Local functions */
+static void init_rx_desc (void);
+static void init_tx_desc (void);
+static uint32_t crc32_8bit_rev (uint32_t crc32, uint8_t val);
+static uint32_t crc32_data (const uint8_t *data, uint32_t len);
+
+/**
+  \fn          void init_rx_desc (void)
+  \brief       Initialize Rx DMA descriptors.
+  \return      none.
+*/
+static void init_rx_desc (void) {
+  uint32_t i,next;
+
+  for (i = 0; i < NUM_RX_BUF; i++) {
+    rx_desc[i].Stat = EMAC_RDES0_OWN;
+    rx_desc[i].Ctrl = EMAC_RDES1_RCH | ETH_BUF_SIZE;
+    rx_desc[i].Addr = (uint8_t *)&rx_buf[i];
+    next = i + 1;
+    if (next == NUM_RX_BUF) next = 0;
+    rx_desc[i].Next = &rx_desc[next];
+  }
+  ENET->DMA_REC_DES_ADDR = (uint32_t)&rx_desc[0];
+  emac.rx_index = 0;
+}
+
+/**
+  \fn          void init_tx_desc (void)
+  \brief       Initialize Tx DMA descriptors.
+  \return      none.
+*/
+static void init_tx_desc (void) {
+  uint32_t i,next;
+
+  for (i = 0; i < NUM_TX_BUF; i++) {
+    tx_desc[i].CtrlStat = EMAC_TDES0_TCH | EMAC_TDES0_LS | EMAC_TDES0_FS;
+    tx_desc[i].Addr     = (uint8_t *)&tx_buf[i];
+    next = i + 1;
+    if (next == NUM_TX_BUF) next = 0;
+    tx_desc[i].Next     = &tx_desc[next];
+  }
+  ENET->DMA_TRANS_DES_ADDR = (uint32_t)&tx_desc[0];
+  emac.tx_index = 0;
+}
+
+/**
+  \fn          uint32_t crc32_8bit_rev (uint32_t crc32, uint8_t val)
+  \brief       Calculate 32-bit CRC (Polynom: 0x04C11DB7, data bit-reversed).
+  \param[in]   crc32  CRC initial value
+  \param[in]   val    Input value
+  \return      Calculated CRC value
+*/
+static uint32_t crc32_8bit_rev (uint32_t crc32, uint8_t val) {
+  uint32_t n;
+
+  crc32 ^= __RBIT (val);
+  for (n = 8; n; n--) {
+    if (crc32 & 0x80000000) {
+      crc32 <<= 1;
+      crc32  ^= 0x04C11DB7;
+    } else {
+      crc32 <<= 1;
+    }
+  }
+  return (crc32);
+}
+
+/**
+  \fn          uint32_t crc32_data (const uint8_t *data, uint32_t len)
+  \brief       Calculate standard 32-bit Ethernet CRC.
+  \param[in]   data  Pointer to buffer containing the data
+  \param[in]   len   Data length in bytes
+  \return      Calculated CRC value
+*/
+static uint32_t crc32_data (const uint8_t *data, uint32_t len) {
+  uint32_t crc;
+
+  for (crc = 0xFFFFFFFF; len; len--) {
+    crc = crc32_8bit_rev (crc, *data++);
+  }
+  return (crc ^ 0xFFFFFFFF);
+}
+
+
+/* Ethernet Driver functions */
+
+/**
+  \fn          ARM_DRIVER_VERSION GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+*/
+static ARM_DRIVER_VERSION GetVersion (void) {
+  return DriverVersion;
+}
+
+
+/**
+  \fn          ARM_ETH_MAC_CAPABILITIES GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_ETH_MAC_CAPABILITIES
+*/
+static ARM_ETH_MAC_CAPABILITIES GetCapabilities (void) {
+  return DriverCapabilities;
+}
+
+
+/**
+  \fn          int32_t Initialize (ARM_ETH_MAC_SignalEvent_t cb_event)
+  \brief       Initialize Ethernet MAC Device.
+  \param[in]   cb_event  Pointer to \ref ARM_ETH_MAC_SignalEvent
+  \return      \ref execution_status
+*/
+static int32_t Initialize (ARM_ETH_MAC_SignalEvent_t cb_event) {
+  const PIN_ID *pin;
+
+  if (emac.flags & EMAC_FLAG_INIT) { return ARM_DRIVER_OK; }
+
+  /* Configure EMAC pins */
+  for (pin = eth_pins; pin != &eth_pins[sizeof(eth_pins)/sizeof(PIN_ID)]; pin++) {
+    if (pin->port == 0x10) {
+      SCU_CLK_PinConfigure (pin->num, pin->config_val);
+      continue;
+    }
+    SCU_PinConfigure(pin->port, pin->num, pin->config_val);
+  }
+  
+  /* Clear control structure */
+  memset (&emac, 0, sizeof (EMAC_CTRL));
+
+  emac.cb_event = cb_event;
+  emac.flags    = EMAC_FLAG_INIT;
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t Uninitialize (void)
+  \brief       De-initialize Ethernet MAC Device.
+  \return      \ref execution_status
+*/
+static int32_t Uninitialize (void) {
+  const PIN_ID *pin;
+
+  emac.flags = 0;
+
+  /* Unconfigure ethernet pins */
+  for (pin = eth_pins; pin != &eth_pins[sizeof(eth_pins)/sizeof(PIN_ID)]; pin++) {
+    if (pin->port == 0x10) {
+      SCU_CLK_PinConfigure (pin->num, 0);
+      continue;
+    }
+    SCU_PinConfigure(pin->port, pin->num, 0);
+  }
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t PowerControl (ARM_POWER_STATE state)
+  \brief       Control Ethernet MAC Device Power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+*/
+static int32_t PowerControl (ARM_POWER_STATE state) {
+  uint32_t clk;
+
+  switch (state) {
+    case ARM_POWER_OFF:
+      /* Disable EMAC interrupts */
+      NVIC_DisableIRQ(ETHERNET_IRQn);
+
+      /* Reset EMAC peripheral */
+      LPC_RGU->RESET_CTRL0 = RGU_RESET_EMAC;
+      while (!(LPC_RGU->RESET_ACTIVE_STATUS0 & RGU_RESET_EMAC));
+
+      /* Disable EMAC peripheral clock */
+      LPC_CCU1->CLK_M3_ETHERNET_CFG &= ~CCU_CLK_CFG_RUN;
+
+      emac.flags &= ~EMAC_FLAG_POWER;
+      break;
+
+    case ARM_POWER_LOW:
+      return ARM_DRIVER_ERROR_UNSUPPORTED;
+
+    case ARM_POWER_FULL:
+      if ((emac.flags & EMAC_FLAG_INIT)  == 0) { return ARM_DRIVER_ERROR; }
+      if ((emac.flags & EMAC_FLAG_POWER) != 0) { return ARM_DRIVER_OK; }
+
+      /* Enable EMAC peripheral clock */
+      LPC_CCU1->CLK_M3_ETHERNET_CFG |=  CCU_CLK_CFG_AUTO | CCU_CLK_CFG_RUN;
+      while (!(LPC_CCU1->CLK_M3_ETHERNET_STAT & CCU_CLK_STAT_RUN));
+
+      /* Configure Ethernet PHY interface mode (MII/RMII) */
+      /* EMAC must be reset after changing PHY interface! */
+      #if (RTE_ENET_RMII)
+        LPC_CREG->CREG6 = (LPC_CREG->CREG6 & ~EMAC_CREG6_ETH_MASK) | EMAC_CREG6_ETH_RMII;
+      #else
+        LPC_CREG->CREG6 = (LPC_CREG->CREG6 & ~EMAC_CREG6_ETH_MASK) | EMAC_CREG6_ETH_MII;
+      #endif
+
+      /* Reset EMAC peripheral */
+      LPC_RGU->RESET_CTRL0 = RGU_RESET_EMAC;
+      while (!(LPC_RGU->RESET_ACTIVE_STATUS0 & RGU_RESET_EMAC));
+
+      /* Soft reset EMAC DMA controller */
+      ENET->DMA_BUS_MODE |= EMAC_DBMR_SWR;
+      while (ENET->DMA_BUS_MODE & EMAC_DBMR_SWR);
+
+      /* MDC clock range selection */
+      clk = GetClockFreq (CLK_SRC_PLL1);
+      if      (clk >= 150000000) emac.mmar_cr_val = EMAC_MMAR_CR_Div102;
+      else if (clk >= 100000000) emac.mmar_cr_val = EMAC_MMAR_CR_Div62;
+      else if (clk >= 60000000)  emac.mmar_cr_val = EMAC_MMAR_CR_Div42;
+      else if (clk >= 35000000)  emac.mmar_cr_val = EMAC_MMAR_CR_Div26;
+      else if (clk >= 25000000)  emac.mmar_cr_val = EMAC_MMAR_CR_Div16;
+      else                       return ARM_DRIVER_ERROR_UNSUPPORTED;
+      ENET->MAC_MII_ADDR = emac.mmar_cr_val;
+
+      #if (EMAC_TIME_STAMP)
+        /* Enhanced DMA descriptor enable */
+        ENET->DMA_BUS_MODE |= EMAC_DBMR_ATDS;
+
+        /* Set clock accuracy to 20ns (50MHz) or 50ns (20MHz) */
+        if (clk >= 51000000) {
+          ENET->SUBSECOND_INCR = 20;
+          ENET->ADDEND         = (50000000ull << 32) / clk;
+        }
+        else {
+          ENET->SUBSECOND_INCR = 50;
+          ENET->ADDEND         = (20000000ull << 32) / clk;
+        }
+
+        /* Enable timestamp fine update */
+        ENET->MAC_TIMESTP_CTRL = EMAC_MTCR_TSIPV4E | EMAC_MTCR_TSIPV6E |
+                                 EMAC_MTCR_TSCTRL  | EMAC_MTCR_TSADDR  |
+                                 EMAC_MTCR_TSCFUP  | EMAC_MTCR_TSENA;
+        emac.tx_ts_index = 0;
+      #endif
+
+      /* Initialize MAC configuration */
+      ENET->MAC_CONFIG = EMAC_MCR_DO | EMAC_MCR_PS;
+
+      /* Initialize Filter registers */
+      ENET->MAC_FRAME_FILTER = EMAC_MFFR_DBF;
+      ENET->MAC_FLOW_CTRL    = EMAC_MFCR_DZPQ;
+
+      /* Initialize Address register */
+      ENET->MAC_ADDR0_HIGH = 0x00000000;
+      ENET->MAC_ADDR0_LOW  = 0x00000000;
+
+      /* Disable MAC interrupts */
+      ENET->MAC_INTR_MASK  = EMAC_MIMR_PMTIM | EMAC_MIMR_TSIM;
+
+      /* Initialize DMA Descriptors */
+      init_rx_desc ();
+      init_tx_desc ();
+
+      /* Enable DMA interrupts */
+      ENET->DMA_STAT   = 0xFFFFFFFF;
+      ENET->DMA_INT_EN = EMAC_DIER_NIE | EMAC_DIER_RIE | EMAC_DIER_TIE;
+
+      /* Enable ethernet interrupts */
+      NVIC_ClearPendingIRQ(ETHERNET_IRQn);
+      NVIC_EnableIRQ(ETHERNET_IRQn);
+
+      emac.frame_end = NULL;
+      emac.flags    |= EMAC_FLAG_POWER;
+      break;
+
+    default:
+      return ARM_DRIVER_ERROR_UNSUPPORTED;
+  }
+  
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t GetMacAddress (ARM_ETH_MAC_ADDR *ptr_addr)
+  \brief       Get Ethernet MAC Address.
+  \param[in]   ptr_addr  Pointer to address
+  \return      \ref execution_status
+*/
+static int32_t GetMacAddress (ARM_ETH_MAC_ADDR *ptr_addr) {
+  uint32_t val;
+
+  if (!ptr_addr) {
+    /* Invalid parameters */
+    return ARM_DRIVER_ERROR_PARAMETER;
+  }
+
+  if (!(emac.flags & EMAC_FLAG_POWER)) {
+    /* Driver not yet powered */
+    return ARM_DRIVER_ERROR;
+  }
+
+  val = ENET->MAC_ADDR0_HIGH;
+  ptr_addr->b[5] = (uint8_t)(val >> 8);
+  ptr_addr->b[4] = (uint8_t)(val);
+  val = ENET->MAC_ADDR0_LOW;
+  ptr_addr->b[3] = (uint8_t)(val >> 24);
+  ptr_addr->b[2] = (uint8_t)(val >> 16);
+  ptr_addr->b[1] = (uint8_t)(val >>  8);
+  ptr_addr->b[0] = (uint8_t)(val);
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t SetMacAddress (const ARM_ETH_MAC_ADDR *ptr_addr)
+  \brief       Set Ethernet MAC Address.
+  \param[in]   ptr_addr  Pointer to address
+  \return      \ref execution_status
+*/
+static int32_t SetMacAddress (const ARM_ETH_MAC_ADDR *ptr_addr) {
+
+  if (!ptr_addr) {
+    /* Invalid parameters */
+    return ARM_DRIVER_ERROR_PARAMETER;
+  }
+
+  if (!(emac.flags & EMAC_FLAG_POWER)) {
+    /* Driver not yet powered */
+    return ARM_DRIVER_ERROR;
+  }
+
+  /* Set Ethernet MAC Address registers */
+  ENET->MAC_ADDR0_HIGH = (ptr_addr->b[5] <<  8) |  ptr_addr->b[4];
+  ENET->MAC_ADDR0_LOW  = (ptr_addr->b[3] << 24) | (ptr_addr->b[2] << 16) |
+                         (ptr_addr->b[1] <<  8) |  ptr_addr->b[0];
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t SetAddressFilter (const ARM_ETH_MAC_ADDR *ptr_addr,
+                                               uint32_t          num_addr)
+  \brief       Configure Address Filter.
+  \param[in]   ptr_addr  Pointer to addresses
+  \param[in]   num_addr  Number of addresses to configure
+  \return      \ref execution_status
+*/
+static int32_t SetAddressFilter (const ARM_ETH_MAC_ADDR *ptr_addr, uint32_t num_addr) {
+  uint32_t crc;
+
+  if (!ptr_addr && num_addr) {
+    /* Invalid parameters */
+    return ARM_DRIVER_ERROR_PARAMETER;
+  }
+
+  if (!(emac.flags & EMAC_FLAG_POWER)) {
+    /* Driver not yet powered */
+    return ARM_DRIVER_ERROR;
+  }
+
+  ENET->MAC_FRAME_FILTER &= ~(EMAC_MFFR_HPF | EMAC_MFFR_HMC);
+  ENET->MAC_HASHTABLE_HIGH = 0x00000000;
+  ENET->MAC_HASHTABLE_LOW  = 0x00000000;
+
+  if (num_addr == 0) {
+    return ARM_DRIVER_OK;
+  }
+
+  /* Calculate 64-bit Hash table for MAC addresses */
+  for ( ; num_addr; ptr_addr++, num_addr--) {
+    crc = crc32_data (&ptr_addr->b[0], 6) >> 26;
+    if (crc & 0x20) {
+      ENET->MAC_HASHTABLE_HIGH |= (1 << (crc & 0x1F));
+    }
+    else {
+      ENET->MAC_HASHTABLE_LOW  |= (1 << crc);
+    }
+  }
+  /* Enable both, unicast and hash address filtering */
+  ENET->MAC_FRAME_FILTER |= EMAC_MFFR_HPF | EMAC_MFFR_HMC;
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t SendFrame (const uint8_t *frame, uint32_t len, uint32_t flags)
+  \brief       Send Ethernet frame.
+  \param[in]   frame  Pointer to frame buffer with data to send
+  \param[in]   len    Frame buffer length in bytes
+  \param[in]   flags  Frame transmit flags (see ARM_ETH_MAC_TX_FRAME_...)
+  \return      \ref execution_status
+*/
+static int32_t SendFrame (const uint8_t *frame, uint32_t len, uint32_t flags) {
+  uint8_t *dst;
+  uint32_t ctrl;
+
+  if (!frame || !len) {
+    /* Invalid parameters */
+    return ARM_DRIVER_ERROR_PARAMETER;
+  }
+
+  if (!(emac.flags & EMAC_FLAG_POWER)) {
+    /* Driver not yet powered */
+    return ARM_DRIVER_ERROR;
+  }
+
+  dst = emac.frame_end;
+  if (dst == NULL) {
+    /* Start of a new transmit frame */
+    if (tx_desc[emac.tx_index].CtrlStat & EMAC_TDES0_OWN) {
+      /* Transmitter is busy, wait */
+      return ARM_DRIVER_ERROR_BUSY;
+    }
+    dst = tx_desc[emac.tx_index].Addr;
+    tx_desc[emac.tx_index].Size = len;
+  }
+  else {
+    /* Sending data fragments in progress */
+    tx_desc[emac.tx_index].Size += len;
+  }
+  /* Fast-copy data fragments to EMAC-DMA buffer */
+  for ( ; len > 7; dst += 8, frame += 8, len -= 8) {
+    ((__packed uint32_t *)dst)[0] = ((__packed uint32_t *)frame)[0];
+    ((__packed uint32_t *)dst)[1] = ((__packed uint32_t *)frame)[1];
+  }
+  /* Copy remaining 7 bytes */
+  for ( ; len > 1; dst += 2, frame += 2, len -= 2) {
+    ((__packed uint16_t *)dst)[0] = ((__packed uint16_t *)frame)[0];
+  }
+  if (len > 0) dst++[0] = frame++[0];
+
+  if (flags & ARM_ETH_MAC_TX_FRAME_FRAGMENT) {
+    /* More data to come, remember current write position */
+    emac.frame_end = dst;
+    return ARM_DRIVER_OK;
+  }
+
+  /* Frame is now ready, send it to DMA */
+  ctrl = tx_desc[emac.tx_index].CtrlStat & ~(EMAC_TDES0_IC | EMAC_TDES0_TTSE);
+  if (flags & ARM_ETH_MAC_TX_FRAME_EVENT)     ctrl |= EMAC_TDES0_IC;
+#if (EMAC_TIME_STAMP)
+  if (flags & ARM_ETH_MAC_TX_FRAME_TIMESTAMP) ctrl |= EMAC_TDES0_TTSE;
+  emac.tx_ts_index = emac.tx_index;
+#endif
+  tx_desc[emac.tx_index].CtrlStat = ctrl | EMAC_TDES0_OWN;
+
+  if (++emac.tx_index == NUM_TX_BUF) emac.tx_index = 0;
+  emac.frame_end = NULL;
+
+  /* Start frame transmission */
+  ENET->DMA_STAT = EMAC_DSR_TPS;
+  ENET->DMA_TRANS_POLL_DEMAND = 0;
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t ReadFrame (uint8_t *frame, uint32_t len)
+  \brief       Read data of received Ethernet frame.
+  \param[in]   frame  Pointer to frame buffer for data to read into
+  \param[in]   len    Frame buffer length in bytes
+  \return      number of data bytes read or execution status
+                 - value >= 0: number of data bytes read
+                 - value < 0: error occurred, value is execution status as defined with \ref execution_status 
+*/
+static int32_t ReadFrame (uint8_t *frame, uint32_t len) {
+  uint8_t const *src;
+  int32_t cnt = (int32_t)len;
+
+  if (!frame && len) {
+    /* Invalid parameters */
+    return ARM_DRIVER_ERROR_PARAMETER;
+  }
+
+  if (!(emac.flags & EMAC_FLAG_POWER)) {
+    /* Driver not yet powered */
+    return ARM_DRIVER_ERROR;
+  }
+
+  /* Fast-copy data to packet buffer */
+  src = rx_desc[emac.rx_index].Addr;
+  for ( ; len > 7; frame += 8, src += 8, len -= 8) {
+    ((__packed uint32_t *)frame)[0] = ((uint32_t *)src)[0];
+    ((__packed uint32_t *)frame)[1] = ((uint32_t *)src)[1];
+  }
+  /* Copy remaining 7 bytes */
+  for ( ; len > 1; frame += 2, src += 2, len -= 2) {
+    ((__packed uint16_t *)frame)[0] = ((uint16_t *)src)[0];
+  }
+  if (len > 0) frame[0] = src[0];
+
+  /* Return this block back to EMAC-DMA */
+  rx_desc[emac.rx_index].Stat = EMAC_RDES0_OWN;
+
+  if (++emac.rx_index == NUM_RX_BUF) emac.rx_index = 0;
+
+  if (ENET->DMA_STAT & EMAC_DSR_RU) {
+    /* Receive buffer unavailable, resume DMA */
+    ENET->DMA_STAT = EMAC_DSR_RU;
+    ENET->DMA_REC_POLL_DEMAND = 0;
+  }
+  return (cnt);
+}
+
+/**
+  \fn          uint32_t GetRxFrameSize (void)
+  \brief       Get size of received Ethernet frame.
+  \return      number of bytes in received frame
+*/
+static uint32_t GetRxFrameSize (void) {
+  uint32_t stat;
+
+  if (!(emac.flags & EMAC_FLAG_POWER)) {
+    /* Driver not yet powered */
+    return (0);
+  }
+
+  stat = rx_desc[emac.rx_index].Stat;
+  if (stat & EMAC_RDES0_OWN) {
+    /* Owned by DMA */
+    return (0);
+  }
+
+  if ((stat & EMAC_RDES0_ES) || !(stat & EMAC_RDES0_FS) || !(stat & EMAC_RDES0_LS)) {
+    /* Error, this block is invalid */
+    return (0xFFFFFFFF);
+  }
+  return (((stat & EMAC_RDES0_FL) >> 16) - 4);
+}
+
+/**
+  \fn          int32_t GetRxFrameTime (ARM_ETH_MAC_TIME *time)
+  \brief       Get time of received Ethernet frame.
+  \param[in]   time  Pointer to time structure for data to read into
+  \return      \ref execution_status
+*/
+static int32_t GetRxFrameTime (ARM_ETH_MAC_TIME *time) {
+#if (EMAC_TIME_STAMP)
+  RX_Desc *rxd;
+
+  if (!time) {
+    /* Invalid parameters */
+    return ARM_DRIVER_ERROR_PARAMETER;
+  }
+
+  rxd = &rx_desc[emac.rx_index];
+  if (rxd->Stat & EMAC_RDES0_OWN) {
+    /* Owned by DMA */
+    return ARM_DRIVER_ERROR_BUSY;
+  }
+  time->ns  = rxd->TimeLo;
+  time->sec = rxd->TimeHi;
+
+  return ARM_DRIVER_OK;
+#else
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+#endif
+}
+
+/**
+  \fn          int32_t GetTxFrameTime (ARM_ETH_MAC_TIME *time)
+  \brief       Get time of transmitted Ethernet frame.
+  \param[in]   time  Pointer to time structure for data to read into
+  \return      \ref execution_status
+*/
+static int32_t GetTxFrameTime (ARM_ETH_MAC_TIME *time) {
+#if (EMAC_TIME_STAMP)
+  TX_Desc *txd;
+
+  if (!time) {
+    /* Invalid parameters */
+    return ARM_DRIVER_ERROR_PARAMETER;
+  }
+
+  txd = &tx_desc[emac.tx_ts_index];
+  if (txd->CtrlStat & EMAC_TDES0_OWN) {
+    /* Owned by DMA */
+    return ARM_DRIVER_ERROR_BUSY;
+  }
+  if (!(txd->CtrlStat & EMAC_TDES0_TTSS)) {
+    /* No transmit time stamp available */
+    return ARM_DRIVER_ERROR;
+  }
+  time->ns  = txd->TimeLo;
+  time->sec = txd->TimeHi;
+  return ARM_DRIVER_OK;
+#else
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+#endif
+}
+
+/**
+  \fn          int32_t Control (uint32_t control, uint32_t arg)
+  \brief       Control Ethernet Interface.
+  \param[in]   control  Operation
+  \param[in]   arg      Argument of operation (optional)
+  \return      \ref execution_status
+*/
+static int32_t Control (uint32_t control, uint32_t arg) {
+  uint32_t maccr;
+  uint32_t macffr;
+
+  if (!(emac.flags & EMAC_FLAG_POWER)) {
+    /* Driver not powered */
+    return ARM_DRIVER_ERROR;
+  }
+
+  switch (control) {
+    case ARM_ETH_MAC_CONFIGURE:
+      maccr = ENET->MAC_CONFIG & ~(EMAC_MCR_FES | EMAC_MCR_DM | EMAC_MCR_LM);
+
+      /* Configure 100MBit/10MBit mode */
+      switch (arg & ARM_ETH_MAC_SPEED_Msk) {
+        case ARM_ETH_MAC_SPEED_10M:
+#if (RTE_ENET_RMII)
+          /* RMII Half Duplex Collision detection does not work */
+          maccr |= EMAC_MCR_DM;
+#endif
+          break;
+        case ARM_ETH_SPEED_100M:
+          maccr |= EMAC_MCR_FES;
+          break;
+        default:
+          return ARM_DRIVER_ERROR_UNSUPPORTED;
+      }
+
+      /* Configure Half/Full duplex mode */
+      switch (arg & ARM_ETH_MAC_DUPLEX_Msk) {
+        case ARM_ETH_MAC_DUPLEX_FULL:
+          maccr |= EMAC_MCR_DM;
+          break;
+      }
+
+      /* Configure loopback mode */
+      if (arg & ARM_ETH_MAC_LOOPBACK) {
+        maccr |= EMAC_MCR_LM;
+      }
+
+      if ((arg & ARM_ETH_MAC_CHECKSUM_OFFLOAD_RX) ||
+          (arg & ARM_ETH_MAC_CHECKSUM_OFFLOAD_TX)) {
+        /* Checksum offload is disabled in the driver */
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+      }
+
+      ENET->MAC_CONFIG = maccr;
+
+      macffr = ENET->MAC_FRAME_FILTER & ~(EMAC_MFFR_PR | EMAC_MFFR_PAM | EMAC_MFFR_DBF);
+      /* Enable broadcast frame receive */
+      if (!(arg & ARM_ETH_MAC_ADDRESS_BROADCAST)) {
+        macffr |= EMAC_MFFR_DBF;
+      }
+
+      /* Enable all multicast frame receive */
+      if (arg & ARM_ETH_MAC_ADDRESS_MULTICAST) {
+        macffr |= EMAC_MFFR_PAM;
+      }
+
+      /* Enable promiscuous mode (no filtering) */
+      if (arg & ARM_ETH_MAC_ADDRESS_ALL) {
+        macffr |= EMAC_MFFR_PR;
+      }
+      ENET->MAC_FRAME_FILTER = macffr;
+
+      break;
+
+    case ARM_ETH_MAC_CONTROL_TX:
+      /* Enable/disable MAC transmitter */
+      if (arg != 0) {
+        ENET->MAC_CONFIG  |= EMAC_MCR_TE;
+        ENET->DMA_OP_MODE |= EMAC_DOMR_ST;
+      }
+      else {
+        ENET->DMA_OP_MODE &= ~EMAC_DOMR_ST;
+        ENET->MAC_CONFIG  &= ~EMAC_MCR_TE;
+      }
+      break;
+
+    case ARM_ETH_MAC_CONTROL_RX:
+      /* Enable/disable MAC receiver */
+      if (arg != 0) {
+        ENET->MAC_CONFIG  |= EMAC_MCR_RE;
+        ENET->DMA_OP_MODE |= EMAC_DOMR_SR;
+      }
+      else {
+        ENET->DMA_OP_MODE &= ~EMAC_DOMR_SR;
+        ENET->MAC_CONFIG  &= ~EMAC_MCR_RE;
+      }
+      break;
+
+    case ARM_ETH_MAC_FLUSH:
+      /* Flush Tx and Rx buffers */
+      if (arg & ARM_ETH_MAC_FLUSH_RX) {
+        /* Stop/Start DMA Receive */
+        uint32_t domr = ENET->DMA_OP_MODE;
+        ENET->DMA_OP_MODE &= ~EMAC_DOMR_SR;
+        init_rx_desc ();
+        ENET->DMA_OP_MODE = domr;
+      }
+      if (arg & ARM_ETH_MAC_FLUSH_TX) {
+        /* Stop/Start DMA Transmit */
+        uint32_t domr = ENET->DMA_OP_MODE;
+        ENET->DMA_OP_MODE &= ~EMAC_DOMR_ST;
+        /* Flush transmit FIFO */
+        ENET->DMA_OP_MODE |= EMAC_DOMR_FTF;
+        init_tx_desc ();
+        ENET->DMA_OP_MODE = domr;
+      }
+      break;
+
+    case ARM_ETH_MAC_SLEEP:
+      /* Enable/disable Sleep mode */
+      if (arg != 0) {
+        /* Enable Power Management interrupts */
+        ENET->MAC_INTR_MASK    &= ~EMAC_MIMR_PMTIM;
+        /* Enter Power-down, Magic packet enable */
+        ENET->MAC_PMT_CTRL_STAT = EMAC_PMTR_MPE | EMAC_PMTR_PD;
+      }
+      else {
+        /* Disable Power Management interrupts */
+        ENET->MAC_INTR_MASK    |= EMAC_MIMR_PMTIM;
+        ENET->MAC_PMT_CTRL_STAT = 0x00000000;
+      }
+      break;
+
+    case ARM_ETH_MAC_VLAN_FILTER:
+      /* Configure VLAN filter */
+      ENET->MAC_VLAN_TAG = arg;
+      break;
+
+    default:
+      return ARM_DRIVER_ERROR_UNSUPPORTED;
+  }
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t ControlTimer (uint32_t control, ARM_ETH_MAC_TIME *time)
+  \brief       Control Precision Timer.
+  \param[in]   control  Operation
+  \param[in]   time     Pointer to time structure
+  \return      \ref execution_status
+*/
+static int32_t ControlTimer (uint32_t control, ARM_ETH_MAC_TIME *time) {
+
+#if (EMAC_TIME_STAMP)
+  if (!(emac.flags & EMAC_FLAG_POWER)) {
+    /* Driver not powered */
+    return ARM_DRIVER_ERROR;
+  }
+
+  switch (control) {
+    case ARM_ETH_MAC_TIMER_GET_TIME:
+      /* Get current time */
+      time->sec = ENET->SECONDS;
+      time->ns  = ENET->NANOSECONDS;
+      break;
+
+    case ARM_ETH_MAC_TIMER_SET_TIME:
+      /* Set new time */
+      ENET->SECONDSUPDATE     = time->sec;
+      ENET->NANOSECONDSUPDATE = time->ns;
+      /* Initialize precision timer */
+      ENET->MAC_TIMESTP_CTRL |= EMAC_MTCR_TSINIT;
+      break;
+
+    case ARM_ETH_MAC_TIMER_INC_TIME:
+      /* Increment current time */
+      ENET->SECONDSUPDATE     = time->sec;
+      ENET->NANOSECONDSUPDATE = time->ns;
+      /* Update precision timer */
+      ENET->MAC_TIMESTP_CTRL |=  EMAC_MTCR_TSUPDT;
+      break;
+
+    case ARM_ETH_MAC_TIMER_DEC_TIME:
+      /* Decrement current time */
+      ENET->SECONDSUPDATE     = time->sec;
+      ENET->NANOSECONDSUPDATE = time->ns | 0x80000000;
+      /* Update precision timer */
+      ENET->MAC_TIMESTP_CTRL |=  EMAC_MTCR_TSUPDT;
+      break;
+
+    case ARM_ETH_MAC_TIMER_SET_ALARM:
+      /* Set alarm time */
+      ENET->TARGETSECONDS     = time->sec;
+      ENET->TARGETNANOSECONDS = time->ns;
+      /* Enable timestamp interrupt trigger */
+      ENET->MAC_TIMESTP_CTRL |= EMAC_MTCR_TSTRIG;
+      if (time->sec || time->ns) {
+        /* Enable timestamp interrupts */
+        ENET->MAC_INTR_MASK &= ~EMAC_MIMR_TSIM;
+        break;
+      }
+      /* Disable timestamp interrupts */
+      ENET->MAC_INTR_MASK |= EMAC_MIMR_TSIM;
+      break;
+
+    case ARM_ETH_MAC_TIMER_ADJUST_CLOCK:
+      /* Adjust current time, fine correction */
+      /* Correction factor is Q31 (0x80000000 = 1.000000000) */
+      ENET->ADDEND = ((uint64_t)time->ns * ENET->ADDEND) >> 31;
+      /* Update addend register */
+      ENET->MAC_TIMESTP_CTRL |= EMAC_MTCR_TSADDR;
+      break;
+
+    default:
+      return ARM_DRIVER_ERROR_UNSUPPORTED;
+  }
+  return ARM_DRIVER_OK;
+#else
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+#endif
+}
+
+/**
+  \fn          int32_t PHY_Read (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data)
+  \brief       Read Ethernet PHY Register through Management Interface.
+  \param[in]   phy_addr  5-bit device address
+  \param[in]   reg_addr  5-bit register address
+  \param[out]  data      Pointer where the result is written to
+  \return      \ref execution_status
+*/
+static int32_t PHY_Read (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data) {
+  uint32_t tick;
+
+  if (!data) {
+    /* Invalid parameter */
+    return ARM_DRIVER_ERROR_PARAMETER;
+  }
+
+  if (!(emac.flags & EMAC_FLAG_POWER)) {
+    /* Driver not powered */
+    return ARM_DRIVER_ERROR;
+  }
+
+  ENET->MAC_MII_ADDR  = emac.mmar_cr_val | EMAC_MMAR_GB |
+                        (phy_addr << 11) | (reg_addr << 6);
+
+  /* Wait until operation completed */
+  tick = osKernelSysTick();
+  do {
+    if (!(ENET->MAC_MII_ADDR & EMAC_MMAR_GB)) {
+      *data = ENET->MAC_MII_DATA & EMAC_MMDR_GD;
+      return ARM_DRIVER_OK;
+    }
+  } while ((osKernelSysTick() - tick) < osKernelSysTickMicroSec(PHY_TIMEOUT));
+
+  if (!(ENET->MAC_MII_ADDR & EMAC_MMAR_GB)) {
+    *data = ENET->MAC_MII_DATA & EMAC_MMDR_GD;
+    return ARM_DRIVER_OK;
+  }
+  return ARM_DRIVER_ERROR_TIMEOUT;
+}
+
+/**
+  \fn          int32_t PHY_Write (uint8_t phy_addr, uint8_t reg_addr, uint16_t data)
+  \brief       Write Ethernet PHY Register through Management Interface.
+  \param[in]   phy_addr  5-bit device address
+  \param[in]   reg_addr  5-bit register address
+  \param[in]   data      16-bit data to write
+  \return      \ref execution_status
+*/
+static int32_t PHY_Write (uint8_t phy_addr, uint8_t reg_addr, uint16_t data) {
+  uint32_t tick;
+
+  if (!(emac.flags & EMAC_FLAG_POWER)) {
+    /* Driver not powered */
+    return ARM_DRIVER_ERROR;
+  }
+
+  ENET->MAC_MII_DATA  = data;
+  ENET->MAC_MII_ADDR  = emac.mmar_cr_val | EMAC_MMAR_GB | EMAC_MMAR_W |
+                        (phy_addr << 11) | (reg_addr << 6);
+
+  /* Wait until operation completed */
+  tick = osKernelSysTick();
+  do {
+    if (!(ENET->MAC_MII_ADDR & EMAC_MMAR_GB)) {
+      return ARM_DRIVER_OK;
+    }
+  } while ((osKernelSysTick() - tick) < osKernelSysTickMicroSec(PHY_TIMEOUT));
+
+  if (!(ENET->MAC_MII_ADDR & EMAC_MMAR_GB)) {
+    return ARM_DRIVER_OK;
+  }
+  return ARM_DRIVER_ERROR_TIMEOUT;
+}
+
+/**
+  \fn          void ETH_IRQHandler (void)
+  \brief       Ethernet Interrupt handler.
+*/
+void ETH_IRQHandler (void) {
+  uint32_t stat,event = 0;
+
+  stat = ENET->DMA_STAT;
+  ENET->DMA_STAT = stat & (EMAC_DSR_NIS | EMAC_DSR_RI | EMAC_DSR_TI);
+  if (stat & EMAC_DSR_TI) {
+    /* Transmit interrupt */
+    event |= ARM_ETH_MAC_EVENT_TX_FRAME;
+  }
+  if (stat & EMAC_DSR_RI) {
+    /* Receive interrupt */
+    event |= ARM_ETH_MAC_EVENT_RX_FRAME;
+  }
+  stat = ENET->MAC_INTR;
+#if (EMAC_TIME_STAMP)
+  if (stat & EMAC_MISR_TS) {
+    /* Timestamp interrupt */
+    if (ENET->TIMESTAMPSTAT & EMAC_MTSR_TSTARGT) {
+      /* Alarm trigger interrupt */
+      event |= ARM_ETH_MAC_EVENT_TIMER_ALARM;
+    }
+  }
+#endif
+  if (stat & EMAC_MISR_PMT) {
+    /* Power management interrupt */
+    if (ENET->MAC_PMT_CTRL_STAT & EMAC_PMTR_MPR) {
+      /* Magic packet received */
+      event |= ARM_ETH_MAC_EVENT_WAKEUP;
+    }
+  }
+  /* Callback event notification */
+  if (event && emac.cb_event) {
+    emac.cb_event (event);
+  }
+}
+
+/* MAC Driver Control Block */
+ARM_DRIVER_ETH_MAC Driver_ETH_MAC0 = {
+  GetVersion,
+  GetCapabilities,
+  Initialize,
+  Uninitialize,
+  PowerControl,
+  GetMacAddress,
+  SetMacAddress,
+  SetAddressFilter,
+  SendFrame,
+  ReadFrame,
+  GetRxFrameSize,
+  GetRxFrameTime,
+  GetTxFrameTime,
+  ControlTimer,
+  Control,
+  PHY_Read,
+  PHY_Write
+};

CMSIS/Pack/Example/CMSIS_Driver/EMAC_LPC18xx.h

@@ -0,0 +1,324 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        02. March 2016
+ * $Revision:    V2.6
+ *
+ * Project:      Ethernet Media Access (MAC) Definitions for NXP LPC18xx
+ * -------------------------------------------------------------------------- */
+
+#ifndef __EMAC_LPC18XX_H
+#define __EMAC_LPC18XX_H
+
+#include <string.h>
+
+#include "Driver_ETH_MAC.h"
+
+#include "RTE_Device.h"
+#include "RTE_Components.h"
+
+#include "cmsis_os.h"
+#include "LPC18xx.h"
+
+#include "SCU_LPC18xx.h"
+
+#if (defined(RTE_Drivers_ETH_MAC0) && !RTE_ENET)
+#error "Ethernet not configured in RTE_Device.h!"
+#endif
+
+#if (RTE_ENET_MII && RTE_ENET_RMII)
+#error "Ethernet interface configuration in RTE_Device.h is invalid!"
+#endif
+
+#define ENET                LPC_ETHERNET
+
+/* Clock Control Unit register */
+#define CCU_CLK_CFG_RUN     (1 << 0)
+#define CCU_CLK_CFG_AUTO    (1 << 1)
+#define CCU_CLK_STAT_RUN    (1 << 0)
+
+#define CLK_SRC_PLL1        0x09            // EMAC clock source
+
+/* CREG6 Control Register */
+#define EMAC_CREG6_ETH_MASK 0x00000007      // EMAC mode mask
+#define EMAC_CREG6_ETH_MII  (0x0 << 0)      // EMAC mode MII
+#define EMAC_CREG6_ETH_RMII (0x4 << 0)      // EMAC mode RMII
+
+/* EMAC reset value for RGU */
+#define RGU_RESET_EMAC      (1 << 22)       // EMAC reset
+
+/* EMAC Driver state flags */
+#define EMAC_FLAG_INIT      (1 << 0)        // Driver initialized
+#define EMAC_FLAG_POWER     (1 << 1)        // Driver power on
+
+/* TDES0 Descriptor TX Packet Control/Status */
+#define EMAC_TDES0_OWN      0x80000000      // Own bit 1=DMA, 0=CPU
+#define EMAC_TDES0_IC       0x40000000      // Interrupt on completition
+#define EMAC_TDES0_LS       0x20000000      // Last segment
+#define EMAC_TDES0_FS       0x10000000      // First segment
+#define EMAC_TDES0_DC       0x08000000      // Disable CRC
+#define EMAC_TDES0_DP       0x04000000      // Disable pad
+#define EMAC_TDES0_TTSE     0x02000000      // Transmit time stamp enable
+#define EMAC_TDES0_TER      0x00200000      // Transmit end of ring
+#define EMAC_TDES0_TCH      0x00100000      // Second address chained
+#define EMAC_TDES0_TTSS     0x00020000      // Transmit time stamp status
+#define EMAC_TDES0_IHE      0x00010000      // IP header error
+#define EMAC_TDES0_ES       0x00008000      // Error summary
+#define EMAC_TDES0_JT       0x00004000      // Jabber timeout
+#define EMAC_TDES0_FF       0x00002000      // Frame flushed
+#define EMAC_TDES0_IPE      0x00001000      // IP payload error
+#define EMAC_TDES0_LOC      0x00000800      // Loss of carrier
+#define EMAC_TDES0_NC       0x00000400      // No carrier
+#define EMAC_TDES0_LC       0x00000200      // Late collision
+#define EMAC_TDES0_EC       0x00000100      // Excessive collision
+#define EMAC_TDES0_VF       0x00000080      // VLAN frame
+#define EMAC_TDES0_CC       0x00000078      // Collision count
+#define EMAC_TDES0_ED       0x00000004      // Excessive deferral
+#define EMAC_TDES0_UF       0x00000002      // Underflow error
+#define EMAC_TDES0_DB       0x00000001      // Deferred bit
+
+/* TDES1 Descriptor TX Packet Control */
+#define EMAC_TDES1_TBS2     0x1FFF0000      // Transmit buffer 2 size
+#define EMAC_TDES1_TBS1     0x00001FFF      // Transmit buffer 1 size
+
+/* RDES0 Descriptor RX Packet Status */
+#define EMAC_RDES0_OWN      0x80000000      // Own bit 1=DMA, 0=CPU
+#define EMAC_RDES0_AFM      0x40000000      // Destination address filter fail
+#define EMAC_RDES0_FL       0x3FFF0000      // Frame length mask
+#define EMAC_RDES0_ES       0x00008000      // Error summary
+#define EMAC_RDES0_DE       0x00004000      // Descriptor error
+#define EMAC_RDES0_SAF      0x00002000      // Source address filter fail
+#define EMAC_RDES0_LE       0x00001000      // Length error
+#define EMAC_RDES0_OE       0x00000800      // Overflow error
+#define EMAC_RDES0_VLAN     0x00000400      // VLAN tag
+#define EMAC_RDES0_FS       0x00000200      // First descriptor
+#define EMAC_RDES0_LS       0x00000100      // Last descriptor
+#define EMAC_RDES0_TSA      0x00000080      // Timestamp available
+#define EMAC_RDES0_LC       0x00000040      // Late collision
+#define EMAC_RDES0_FT       0x00000020      // Frame type
+#define EMAC_RDES0_RWT      0x00000010      // Receive watchdog timeout
+#define EMAC_RDES0_RE       0x00000008      // Receive error
+#define EMAC_RDES0_DBE      0x00000004      // Dribble bit error
+#define EMAC_RDES0_CE       0x00000002      // CRC error
+#define EMAC_RDES0_ESA      0x00000001      // Extended Status/Rx MAC address
+
+/* RDES1 Descriptor RX Packet Control */
+#define EMAC_RDES1_RBS2     0x1FFF0000      // Receive buffer 2 size
+#define EMAC_RDES1_RER      0x00008000      // Receive end of ring
+#define EMAC_RDES1_RCH      0x00004000      // Second address chained
+#define EMAC_RDES1_RBS1     0x00001FFF      // Receive buffer 1 size
+
+/* MAC Configuration Register */
+#define EMAC_MCR_WD         0x00800000      // Watchdog disable
+#define EMAC_MCR_JD         0x00400000      // Jabber disable
+#define EMAC_MCR_JE         0x00100000      // Jumbo frame enable
+#define EMAC_MCR_IFG        0x000E0000      // Inter-frame gap mask
+#define EMAC_MCR_DCRS       0x00010000      // Disable carrier sense during Tx
+#define EMAC_MCR_PS         0x00008000      // Port select
+#define EMAC_MCR_FES        0x00004000      // Speed
+#define EMAC_MCR_DO         0x00002000      // Disable receive own
+#define EMAC_MCR_LM         0x00001000      // Loopback mode
+#define EMAC_MCR_DM         0x00000800      // Duplex mode
+#define EMAC_MCR_DR         0x00000200      // Disable Retry
+#define EMAC_MCR_ACS        0x00000080      // Automatic pad/CRC stripping
+#define EMAC_MCR_BL         0x00000060      // Back-off limit mask
+#define EMAC_MCR_DF         0x00000010      // Deferral check
+#define EMAC_MCR_TE         0x00000008      // Transmitter enable
+#define EMAC_MCR_RE         0x00000004      // Receiver enable
+
+/* MAC Frame Filter Register */
+#define EMAC_MFFR_RA        0x80000000      // Receive all
+#define EMAC_MFFR_HPF       0x00000400      // Hash or perfect filter
+#define EMAC_MFFR_PCF       0x000000C0      // Pass control frames mask
+#define EMAC_MFFR_DBF       0x00000020      // Disable broadcast frames
+#define EMAC_MFFR_PAM       0x00000010      // Pass all multicast
+#define EMAC_MFFR_DAIF      0x00000008      // Dest. address inverse filtering
+#define EMAC_MFFR_HMC       0x00000004      // Hash multicast
+#define EMAC_MFFR_HUC       0x00000002      // Hash unicast
+#define EMAC_MFFR_PR        0x00000001      // Promiscuous mode
+
+/* MAC MII Address Register */
+#define EMAC_MMAR_PA        0x0000F800      // PHY address mask
+#define EMAC_MMAR_GR        0x000007C0      // MII register address mask
+#define EMAC_MMAR_CR        0x0000003C      // Clock range mask
+#define EMAC_MMAR_W         0x00000002      // MII write
+#define EMAC_MMAR_GB        0x00000001      // MII busy
+
+/* MAC MII Address Register Clock Range */
+#define EMAC_MMAR_CR_Div102 (0x4 << 2)      // Clk_M3_Ethernet: 150-250 MHz
+#define EMAC_MMAR_CR_Div62  (0x1 << 2)      // Clk_M3_Ethernet: 100-150 MHz
+#define EMAC_MMAR_CR_Div42  (0x0 << 2)      // Clk_M3_Ethernet:  60-100 MHz
+#define EMAC_MMAR_CR_Div26  (0x3 << 2)      // Clk_M3_Ethernet:  35- 60 MHz
+#define EMAC_MMAR_CR_Div16  (0x2 << 2)      // Clk_M3_Ethernet:  20- 35 MHz
+
+/* MAC MII Data Register */
+#define EMAC_MMDR_GD        0x0000FFFF      // MII 16-bit rw data
+
+/* MAC Flow Control Register */
+#define EMAC_MFCR_PT        0xFFFF0000      // Pause time mask
+#define EMAC_MFCR_DZPQ      0x00000080      // Disable zero-quanta pause
+#define EMAC_MFCR_PLT       0x00000030      // Pause low threshold
+#define EMAC_MFCR_UP        0x00000008      // Unicaste pause frame detect
+#define EMAC_MFCR_RFE       0x00000004      // Receive flow control enable
+#define EMAC_MFCR_TFE       0x00000002      // Transmit flow control enable
+#define EMAC_MFCR_FCB       0x00000001      // Flow ctrl busy/backpressure activate
+
+/* MAC Power Management Control and Status Register */
+#define EMAC_PMTR_WFFRPR    0x80000000      // Wake-up frame filter register pointer reset
+#define EMAC_PMTR_GU        0x00000200      // Global unicast wake-up enable
+#define EMAC_PMTR_WFR       0x00000040      // Wake-up frame received status
+#define EMAC_PMTR_MPR       0x00000020      // Magic packet received status
+#define EMAC_PMTR_WFE       0x00000004      // Wake-up frame enable
+#define EMAC_PMTR_MPE       0x00000002      // Magic packet enable
+#define EMAC_PMTR_PD        0x00000001      // Power-down
+
+/* MAC Interrupt Status Register */
+#define EMAC_MISR_TS        0x00000200      // Timestamp interrupt status
+#define EMAC_MISR_PMT       0x00000008      // PMT interrupt status
+
+/* MAC Interrupt Mask Register */
+#define EMAC_MIMR_TSIM      0x00000200      // Timestamp interrupt mask
+#define EMAC_MIMR_PMTIM     0x00000008      // PMT interrupt mask
+
+/* MAC Timestamp Control Register */
+#define EMAC_MTCR_TSENMA    0x00040000      // Enable MAC address for PTP frame filtering
+#define EMAC_MTCR_TSCLKT    0x00030000      // Select the type of clock node, see manual
+#define EMAC_MTCR_TSMSTR    0x00008000      // Enable Snapshot for messages relevant to master
+#define EMAC_MTCR_TSEVNT    0x00004000      // Enable TS snapshot for event messages
+#define EMAC_MTCR_TSIPV4E   0x00002000      // Enable TS snapshot for IPv4 frames
+#define EMAC_MTCR_TSIPV6E   0x00001000      // Enable TS snapshot for IPv6 frames
+#define EMAC_MTCR_TSIPENA   0x00000800      // Enable TS snapshot for PTP over ethernet frames
+#define EMAC_MTCR_TSVER2    0x00000400      // PTP packet snooping for version 2 format
+#define EMAC_MTCR_TSCTRL    0x00000200      // Timestamp digital or binary rollover control
+#define EMAC_MTCR_TSENAL    0x00000100      // Enable timestamp for all frames
+#define EMAC_MTCR_TSADDR    0x00000020      // Addend register update
+#define EMAC_MTCR_TSTRIG    0x00000010      // Timestamp interrupt trigger enable
+#define EMAC_MTCR_TSUPDT    0x00000008      // Timestamp update
+#define EMAC_MTCR_TSINIT    0x00000004      // Timestamp initialize
+#define EMAC_MTCR_TSCFUP    0x00000002      // Timestamp fine or coarse update
+#define EMAC_MTCR_TSENA     0x00000001      // Timestamp enable
+
+/* MAC Timestamp Status Register */
+#define EMAC_MTSR_TSTARGT   0x00000002      // Timestamp target/alarm reached
+#define EMAC_MTSR_TSSOVF    0x00000001      // Timestamp seconds overflow
+
+/* DMA Status Register */
+#define EMAC_DSR_EB3        0x02000000      // Error bit 3
+#define EMAC_DSR_EB2        0x01000000      // Error bit 2
+#define EMAC_DSR_EB1        0x00800000      // Error bit 1
+#define EMAC_DSR_TS         0x00700000      // Transmit process state
+#define EMAC_DSR_RS         0x000E0000      // Receive process state
+#define EMAC_DSR_NIS        0x00010000      // Normal interrupt summary
+#define EMAC_DSR_AIS        0x00008000      // Abnormal interrupt summary
+#define EMAC_DSR_ERI        0x00004000      // Early receive interrupt
+#define EMAC_DSR_FBI        0x00002000      // Fatal bus error interrupt
+#define EMAC_DSR_ETI        0x00000400      // Early transmit interrupt
+#define EMAC_DSR_RWT        0x00000200      // Receive watchdog timeout
+#define EMAC_DSR_RPS        0x00000100      // Receive process stopped
+#define EMAC_DSR_RU         0x00000080      // Receive buffer unavailable
+#define EMAC_DSR_RI         0x00000040      // Receive interrupt
+#define EMAC_DSR_UNF        0x00000020      // Transmit underflow
+#define EMAC_DSR_OVF        0x00000010      // Receive overflow
+#define EMAC_DSR_TJT        0x00000008      // Transmit jabber timeout
+#define EMAC_DSR_TU         0x00000004      // Transmit buffer unavailable
+#define EMAC_DSR_TPS        0x00000002      // Transmit process stopped
+#define EMAC_DSR_TI         0x00000001      // Transmit interrupt
+
+/* DMA Bus Mode Register */
+#define EMAC_DBMR_TXPR      0x08000000      // DMA Tx priority
+#define EMAC_DBMR_MB        0x04000000      // Mixed burst
+#define EMAC_DBMR_AAL       0x02000000      // Address-aligned beats
+#define EMAC_DBMR_PBL8X     0x01000000      // 8 x PBL mode
+#define EMAC_DBMR_USP       0x00800000      // Use separate PBL
+#define EMAC_DBMR_RPBL      0x007E0000      // Rx DMA PBL mask
+#define EMAC_DBMR_FB        0x00010000      // Fixed burst
+#define EMAC_DBMR_PR        0x0000C000      // Rx-to-Tx priority ratio
+#define EMAC_DBMR_PBL       0x00003F00      // Programmable burst length mask
+#define EMAC_DBMR_ATDS      0x00000080      // Alternate descriptor size
+#define EMAC_DBMR_DSL       0x0000007C      // Descriptor skip length
+#define EMAC_DBMR_DA        0x00000002      // DMA arbitration scheme
+#define EMAC_DBMR_SWR       0x00000001      // Software reset
+
+/* DMA Operation Mode Register */
+#define EMAC_DOMR_DFF       0x01000000      // Disable flushing of received frames
+#define EMAC_DOMR_FTF       0x00100000      // Flush transmit FIFO
+#define EMAC_DOMR_TTC       0x0001C000      // Transmit treshold control mask
+#define EMAC_DOMR_ST        0x00002000      // Start/stop transmission
+#define EMAC_DOMR_FEF       0x00000080      // Forward error frames
+#define EMAC_DOMR_FUF       0x00000040      // Forward undersized good frames
+#define EMAC_DOMR_RTC       0x00000018      // Receive threshold control mask
+#define EMAC_DOMR_OSF       0x00000004      // Operate on second frame
+#define EMAC_DOMR_SR        0x00000002      // Start/stop receive
+
+/* DMA Interrupt Enable Register */
+#define EMAC_DIER_NIE       0x00010000      // Normal interrupt summary enable
+#define EMAC_DIER_AIE       0x00008000      // Abnormal interrupt summary enable
+#define EMAC_DIER_ERE       0x00004000      // Early receive interrupt enable
+#define ENET_DIER_FBE       0x00002000      // Fatal bus error enable
+#define EMAC_DIER_ETE       0x00000400      // Early transmit interrupt enable
+#define EMAC_DIER_RWE       0x00000200      // Receive watchdog timeout enable
+#define EMAC_DIER_RSE       0x00000100      // Receive stopped enable
+#define EMAC_DIER_RUE       0x00000080      // Receive buffer unavailable enable
+#define EMAC_DIER_RIE       0x00000040      // Receive interrupt enable
+#define EMAC_DIER_UNE       0x00000020      // Underflow interrupt enable
+#define EMAC_DIER_OVE       0x00000010      // Overflow interrupt enable
+#define EMAC_DIER_TJE       0x00000008      // Transmit jabber timeout enable
+#define EMAC_DIER_TUE       0x00000004      // Transmit buffer unavailable enable
+#define EMAC_DIER_TSE       0x00000002      // Transmit stopped enable
+#define EMAC_DIER_TIE       0x00000001      // Transmit interrupt enable
+
+/* DMA RX Descriptor */
+typedef struct rx_desc {
+  uint32_t volatile Stat;                   // Frame status
+  uint32_t          Ctrl;                   // Frame control
+  uint8_t  const   *Addr;                   // Data buffer address
+  struct rx_desc   *Next;                   // Next Rx descriptor address
+#if (EMAC_TIME_STAMP)
+  uint32_t          ExtStat;                // Extended status
+  uint32_t          Reserved[1];            // Not used
+  uint32_t          TimeLo;                 // Receive Timestamp low
+  uint32_t          TimeHi;                 // Receive Timestamp high
+#endif
+} RX_Desc;
+
+/* DMA TX Descriptor */
+typedef struct tx_desc {
+  uint32_t volatile CtrlStat;               // Frame control and status
+  uint32_t          Size;                   // Frame size
+  uint8_t          *Addr;                   // Data buffer address
+  struct tx_desc   *Next;                   // Next Tx descriptor address
+#if (EMAC_TIME_STAMP)
+  uint32_t          Reserved[2];            // Not used
+  uint32_t          TimeLo;                 // Transmit Timestamp low
+  uint32_t          TimeHi;                 // Transmit Timestamp high
+#endif
+} TX_Desc;
+
+/* EMAC Driver Control Information */
+typedef struct {
+  ARM_ETH_MAC_SignalEvent_t cb_event;       // Event callback
+  uint8_t           flags;                  // Control and state flags
+  uint8_t           tx_index;               // Transmit descriptor index
+  uint8_t           rx_index;               // Receive descriptor index
+#if (EMAC_TIME_STAMP)
+  uint8_t           tx_ts_index;            // Transmit Timestamp descriptor index
+#endif
+  uint8_t           mmar_cr_val;            // MII Address register Clock Range 
+  uint8_t          *frame_end;              // End of assembled frame fragments
+} EMAC_CTRL;
+
+#endif /* __EMAC_LPC18XX_H */

CMSIS/Pack/Example/CMSIS_Driver/GPDMA_LPC18xx.c

@@ -0,0 +1,414 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        02. March 2016
+ * $Revision:    V1.3
+ *
+ * Project:      GPDMA Driver for NXP LPC18xx
+ * -------------------------------------------------------------------------- */
+
+/* History:
+ *  Version 1.3
+ *    - Corrected transfers bigger than 4k
+ *  Version 1.2
+ *    - Added GPDMA_ChannelGetCount function.
+ *  Version 1.1
+ *    - Updated Initialize and Uninitialize functions
+ */
+
+#include "LPC18xx.h"
+#include "GPDMA_LPC18xx.h"
+
+// GPDMA Channel register block structure
+typedef struct {
+  __IO uint32_t  SRCADDR;       // DMA Channel Source Address Register
+  __IO uint32_t  DESTADDR;      // DMA Channel Destination Address Register
+  __IO uint32_t  LLI;           // DMA Channel Linked List Item Register
+  __IO uint32_t  CONTROL;       // DMA Channel Control Register
+  __IO uint32_t  CONFIG;        // DMA Channel Configuration Register
+  __I  uint32_t  RESERVED1[3];
+} GPDMA_CHANNEL_REG;
+
+typedef struct {
+  uint32_t            SrcAddr;
+  uint32_t            DestAddr;
+  uint32_t            Size;
+  uint32_t            Cnt;
+  GPDMA_SignalEvent_t cb_event;
+} GPDMA_Channel_Info;
+
+static uint32_t Channel_active = 0U;
+static uint32_t Init_cnt       = 0U;
+
+static GPDMA_Channel_Info Channel_info[GPDMA_NUMBER_OF_CHANNELS] = { 0U };
+
+#define GPDMA_CHANNEL(n)  ((GPDMA_CHANNEL_REG *) (&(LPC_GPDMA->C0SRCADDR) + (n * 8U)))
+
+
+/**
+  \fn          int32_t Set_Channel_active_flag (uint8_t ch)
+  \brief       Protected set of channel active flag
+  \param[in]   ch        Channel number (0..7)
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+__inline static int32_t Set_Channel_active_flag (uint8_t ch) {
+  uint32_t val;
+
+  do {
+    val = __LDREXW (&Channel_active);
+    if (val & (1U << ch)) {
+      __CLREX (); 
+      return -1;
+    }
+  } while (__STREXW (val | (1U << ch), &Channel_active));
+
+  return 0;
+}
+
+/**
+  \fn          void Clear_Channel_active_flag (uint8_t ch)
+  \brief       Protected clear of channel active flag
+  \param[in]   ch        Channel number (0..7)
+*/
+__inline static void Clear_Channel_active_flag (uint8_t ch) {
+  while(__STREXW((__LDREXW(&Channel_active) & ~(1U << ch)), &Channel_active));
+}
+
+/**
+  \fn          int32_t GPDMA_Initialize (void)
+  \brief       Initialize GPDMA peripheral
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t GPDMA_Initialize (void) {
+  uint32_t ch_num;
+
+  Init_cnt++;
+
+  // Check if already initialized
+  if (Init_cnt > 1U) { return 0; }
+
+  // Enable DMA clock
+  LPC_CCU1->CLK_M3_DMA_CFG |= 1U;
+  while ((LPC_CCU1->CLK_M3_DMA_STAT & 1U) == 0U);
+
+  // Reset DMA
+  LPC_RGU->RESET_CTRL0 = (1U << 19);
+
+  // Reset all DMA channels
+  for (ch_num = 0U; ch_num < GPDMA_NUMBER_OF_CHANNELS; ch_num++) {
+    GPDMA_CHANNEL(ch_num)->CONFIG = 0U;
+    Channel_info[ch_num].SrcAddr  = 0U;
+    Channel_info[ch_num].DestAddr = 0U;
+    Channel_info[ch_num].Size     = 0U;
+    Channel_info[ch_num].Cnt      = 0U;
+  }
+
+  // Clear all DMA interrupt flags
+  LPC_GPDMA->INTTCCLEAR = 0xFF;
+  LPC_GPDMA->INTERRCLR = 0xFF;
+
+  // Clear and Enable DMA IRQ
+  NVIC_ClearPendingIRQ(DMA_IRQn);
+  NVIC_EnableIRQ(DMA_IRQn);
+
+  return 0;
+}
+
+/**
+  \fn          int32_t GPDMA_Uninitialize (void)
+  \brief       De-initialize GPDMA peripheral
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t GPDMA_Uninitialize (void) {
+
+  // Check if DMA is initialized
+  if (Init_cnt == 0U) { return -1; }
+
+  Init_cnt--;
+  if (Init_cnt != 0U) { return 0; }
+
+  // Disable DMA clock
+  LPC_CCU1->CLK_M3_DMA_CFG &= ~1U;
+
+  // Disable and Clear DMA IRQ
+  NVIC_DisableIRQ(DMA_IRQn);
+  NVIC_ClearPendingIRQ(DMA_IRQn);
+
+  return 0;
+}
+
+/**
+  \fn          int32_t GPDMA_PeripheralSelect (uint8_t peri, uint8_t sel)
+  \brief       Selects GPDMA requests
+  \param[in]   peri GPDMA peripheral
+  \param[in]   sel  Selects the DMA request for GPDMA input (0..3)
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t GPDMA_PeripheralSelect (uint8_t peri, uint8_t sel) {
+
+  if ((peri > 15U) || (sel > 3U)) { return -1; }
+
+  LPC_CREG->DMAMUX = (LPC_CREG->DMAMUX & ~(3U   << (2U * peri))) | (sel  << (2U * peri));
+
+  return 0;
+}
+
+/**
+  \fn          int32_t GPDMA_ChannelConfigure (uint8_t              ch,
+                                               uint32_t             src_addr,
+                                               uint32_t             dest_addr,
+                                               uint32_t             size,
+                                               uint32_t             control,
+                                               uint32_t             config,
+                                               GPDMA_SignalEvent_t  cb_event)
+  \brief       Configure GPDMA channel for next transfer
+  \param[in]   ch        Channel number (0..7)
+  \param[in]   src_addr  Source address
+  \param[in]   dest_addr Destination address
+  \param[in]   size      Amount of data to transfer
+  \param[in]   control   Channel control
+  \param[in]   config    Channel configuration
+  \param[in]   cb_event  Channel callback pointer
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t GPDMA_ChannelConfigure (uint8_t              ch,
+                                uint32_t             src_addr,
+                                uint32_t             dest_addr,
+                                uint32_t             size,
+                                uint32_t             control,
+                                uint32_t             config,
+                                GPDMA_SignalEvent_t  cb_event) {
+  GPDMA_CHANNEL_REG * dma_ch;
+
+  // Check if channel is valid
+  if (ch >= GPDMA_NUMBER_OF_CHANNELS)     { return -1; }
+
+  // Set Channel active flag
+  if (Set_Channel_active_flag (ch) == -1) { return -1; }
+
+  // Save callback pointer
+  Channel_info[ch].cb_event = cb_event;
+
+  dma_ch = GPDMA_CHANNEL(ch);
+
+  // Reset DMA Channel configuration
+  dma_ch->CONFIG  = 0U;
+  dma_ch->CONTROL = 0U;
+
+  // Clear DMA interrupts
+  LPC_GPDMA->INTTCCLEAR = (1U << ch);
+  LPC_GPDMA->INTERRCLR  = (1U << ch);
+
+  // Link list not supported
+  dma_ch->LLI = 0U;
+
+  // Enable DMA Channels, little endian
+  LPC_GPDMA->CONFIG = GPDMA_CONFIG_E;
+  while ((LPC_GPDMA->CONFIG & GPDMA_CONFIG_E) == 0U);
+
+  Channel_info[ch].Size = size;
+  if (size > 0x0FFFU) {
+    // Max DMA transfer size = 4k
+    size = 0x0FFFU;
+  }
+
+  control = (control & ~GPDMA_CH_CONTROL_TRANSFERSIZE_MSK) | GPDMA_CH_CONTROL_TRANSFERSIZE(size);
+
+  // Set Source and destination address
+  dma_ch->SRCADDR  = src_addr;
+  dma_ch->DESTADDR = dest_addr;
+
+  if (control & GPDMA_CH_CONTROL_SI) {
+    // Source address increment
+    src_addr += (size << ((control & GPDMA_CH_CONTROL_SWIDTH_MSK) >> GPDMA_CH_CONTROL_SWIDTH_POS));
+  }
+  if (control & GPDMA_CH_CONTROL_DI) {
+    // Destination address increment
+    dest_addr += (size << ((control & GPDMA_CH_CONTROL_DWIDTH_MSK) >> GPDMA_CH_CONTROL_DWIDTH_POS));
+  }
+
+  // Save channel information
+  Channel_info[ch].SrcAddr  = src_addr;
+  Channel_info[ch].DestAddr = dest_addr;
+  Channel_info[ch].Cnt      = size;
+
+  dma_ch->CONTROL = control;
+  dma_ch->CONFIG  = config;
+
+  if ((config & GPDMA_CONFIG_E) == 0U) {
+    // Clear Channel active flag
+    Clear_Channel_active_flag (ch);
+  }
+
+  return 0;
+}
+
+/**
+  \fn          int32_t GPDMA_ChannelEnable (uint8_t ch)
+  \brief       Enable GPDMA channel
+  \param[in]   ch Channel number (0..7)
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t GPDMA_ChannelEnable (uint8_t ch) {
+
+  // Check if channel is valid
+  if (ch >= GPDMA_NUMBER_OF_CHANNELS)     { return -1; }
+
+  // Set Channel active flag
+  if (Set_Channel_active_flag (ch) == -1) { return -1; }
+
+  GPDMA_CHANNEL(ch)->CONFIG |= GPDMA_CH_CONFIG_E;
+  return 0;
+}
+
+/**
+  \fn          int32_t GPDMA_ChannelDisable (uint8_t ch)
+  \brief       Disable GPDMA channel
+  \param[in]   ch Channel number (0..7)
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t GPDMA_ChannelDisable (uint8_t ch) {
+
+  // Check if channel is valid
+  if (ch >= GPDMA_NUMBER_OF_CHANNELS) { return -1; }
+
+  // Clear Channel active flag
+  Clear_Channel_active_flag (ch);
+
+  GPDMA_CHANNEL(ch)->CONFIG &= ~GPDMA_CH_CONFIG_E;
+
+  return 0;
+}
+
+/**
+  \fn          uint32_t GPDMA_ChannelGetStatus (uint8_t ch)
+  \brief       Check if GPDMA channel is enabled or disabled
+  \param[in]   ch Channel number (0..7)
+  \returns     Channel status
+   - \b  1: channel enabled
+   - \b  0: channel disabled
+*/
+uint32_t GPDMA_ChannelGetStatus (uint8_t ch) {
+
+  // Check if channel is valid
+  if (ch >= GPDMA_NUMBER_OF_CHANNELS) { return 0U; };
+
+  if (Channel_active & (1 << ch)) { return 1U; }
+  else                            { return 0U; }
+}
+
+/**
+  \fn          uint32_t GPDMA_ChannelGetCount (uint8_t ch)
+  \brief       Get number of transferred data
+  \param[in]   ch Channel number (0..7)
+  \returns     Number of transferred data
+*/
+uint32_t GPDMA_ChannelGetCount (uint8_t ch) {
+  // Check if channel is valid
+  if (ch >= GPDMA_NUMBER_OF_CHANNELS) return 0;
+
+  return (Channel_info[ch].Cnt - (GPDMA_CHANNEL(ch)->CONTROL & GPDMA_CH_CONTROL_TRANSFERSIZE_MSK));
+}
+
+/**
+  \fn          void DMA_IRQHandler (void)
+  \brief       DMA interrupt handler
+*/
+void DMA_IRQHandler (void) {
+  uint32_t ch, size;
+  GPDMA_CHANNEL_REG * dma_ch;
+
+  for (ch = 0; ch < GPDMA_NUMBER_OF_CHANNELS; ch++) {
+    if (LPC_GPDMA->INTSTAT & (1U << ch)) {
+      dma_ch = GPDMA_CHANNEL(ch);
+
+      // Terminal count request interrupt
+      if (LPC_GPDMA->INTTCSTAT & (1U << ch)) {
+        // Clear interrupt flag
+        LPC_GPDMA->INTTCCLEAR = (1U << ch);
+
+        if (Channel_info[ch].Cnt != Channel_info[ch].Size) {
+          // Data waiting to transfer
+
+          size = Channel_info[ch].Size - Channel_info[ch].Cnt;
+          // Max DMA transfer size = 4k
+          if (size > 0x0FFFU) { size = 0x0FFFU; }
+
+          Channel_info[ch].Cnt += size;
+
+          if (dma_ch->CONTROL & GPDMA_CH_CONTROL_SI) {
+            // Source Address Increment
+            dma_ch->SRCADDR = Channel_info[ch].SrcAddr;
+            Channel_info[ch].SrcAddr += (size << ((dma_ch->CONTROL & GPDMA_CH_CONTROL_SWIDTH_MSK) >> GPDMA_CH_CONTROL_SWIDTH_POS));
+          }
+          if (dma_ch->CONTROL & GPDMA_CH_CONTROL_DI) {
+            // Destination address increment
+            dma_ch->DESTADDR = Channel_info[ch].DestAddr;
+            Channel_info[ch].DestAddr += (size << ((dma_ch->CONTROL & GPDMA_CH_CONTROL_DWIDTH_MSK) >> GPDMA_CH_CONTROL_DWIDTH_POS));
+          }
+
+          // Set transfer size
+          dma_ch->CONTROL = (dma_ch->CONTROL & ~GPDMA_CH_CONTROL_TRANSFERSIZE_MSK) | GPDMA_CH_CONTROL_TRANSFERSIZE(size);
+
+          // Enable DMA Channel
+          dma_ch->CONFIG |= GPDMA_CH_CONFIG_E;
+        } else {
+          // All Data has been transferred
+
+          // Clear Channel active flag
+          Clear_Channel_active_flag (ch);
+
+          // Signal Event
+          if (Channel_info[ch].cb_event) {
+            Channel_info[ch].cb_event(GPDMA_EVENT_TERMINAL_COUNT_REQUEST);
+          }
+        }
+      } else {
+        // DMA error interrupt
+        if (LPC_GPDMA->INTERRSTAT & (1U << ch)) {
+          dma_ch->CONFIG  = 0U;
+          dma_ch->CONTROL = 0U;
+
+          // Clear Channel active flag
+          Clear_Channel_active_flag (ch);
+
+          // Clear interrupt flag
+          LPC_GPDMA->INTERRCLR = (1U << ch);
+
+          // Signal Event
+          if (Channel_info[ch].cb_event) {
+            Channel_info[ch].cb_event(GPDMA_EVENT_ERROR);
+          }
+        }
+      }
+    }
+  }
+}

CMSIS/Pack/Example/CMSIS_Driver/GPDMA_LPC18xx.h

@@ -0,0 +1,211 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        02. March 2016
+ * $Revision:    V1.2
+ *
+ * Project:      GPDMA Driver Definitions for NXP LPC18xx
+ * -------------------------------------------------------------------------- */
+
+#ifndef __GPDMA_LPC18XX_H
+#define __GPDMA_LPC18XX_H
+
+#include <stdint.h>
+
+// Number of GPDMA channels
+#define GPDMA_NUMBER_OF_CHANNELS           ((uint8_t) 8)
+
+// GPDMA Events
+#define GPDMA_EVENT_TERMINAL_COUNT_REQUEST (1)
+#define GPDMA_EVENT_ERROR                  (2)
+
+// GPDMA Burst size in Source and Destination definitions
+#define GPDMA_BSIZE_1                      (0)  // Burst size = 1
+#define GPDMA_BSIZE_4                      (1)  // Burst size = 4
+#define GPDMA_BSIZE_8                      (2)  // Burst size = 8
+#define GPDMA_BSIZE_16                     (3)  // Burst size = 16
+#define GPDMA_BSIZE_32                     (4)  // Burst size = 32
+#define GPDMA_BSIZE_64                     (5)  // Burst size = 64
+#define GPDMA_BSIZE_128                    (6)  // Burst size = 128
+#define GPDMA_BSIZE_256                    (7)  // Burst size = 256
+
+// Width in Source transfer width and Destination transfer width definitions
+#define GPDMA_WIDTH_BYTE                   (0)  // Width = 1 byte
+#define GPDMA_WIDTH_HALFWORD               (1)  // Width = 2 bytes
+#define GPDMA_WIDTH_WORD                   (2)  // Width = 4 bytes
+
+// GPDMA Transfer type and flow control
+#define GPDMA_TRANSFER_M2M_CTRL_DMA        (0)  // Memory to memory - DMA control
+#define GPDMA_TRANSFER_M2P_CTRL_DMA        (1)  // Memory to peripheral - DMA control
+#define GPDMA_TRANSFER_P2M_CTRL_DMA        (2)  // Peripheral to memory - DMA control
+#define GPDMA_TRANSFER_P2P_CTRL_DMA        (3)  // Source peripheral to destination peripheral - DMA control
+#define GPDMA_TRANSFER_P2P_CTRL_DEST_PERI  (4)  // Source peripheral to destination peripheral - destination peripheral control
+#define GPDMA_TRANSFER_M2P_CTRL_PERI       (5)  // Memory to peripheral - peripheral control
+#define GPDMA_TRANSFER_P2M_CTRL_PERI       (6)  // Peripheral to memory - peripheral control
+#define GPDMA_TRANSFER_P2P_CTRL_SRC_PERI   (7)  // Source peripheral to destination peripheral - source peripheral control
+
+//  GPDMA Configuration register definitions
+#define GPDMA_CONFIG_E                     (1     <<  0)
+#define GPDMA_CONFIG_M0                    (1     <<  1)
+#define GPDMA_CONFIG_M1                    (1     <<  2)
+
+// GPDMA Channel Configuration registers definitions
+#define GPDMA_CH_CONFIG_E                  (1     <<  0)
+#define GPDMA_CH_CONFIG_SRC_PERI_POS       (          1)
+#define GPDMA_CH_CONFIG_SRC_PERI_MSK       (0x1F  << GPDMA_CH_CONFIG_SRC_PERI_POS)
+#define GPDMA_CH_CONFIG_SRC_PERI(n)        (((n)  << GPDMA_CH_CONFIG_SRC_PERI_POS) & GPDMA_CH_CONFIG_SRC_PERI_MSK)
+#define GPDMA_CH_CONFIG_DEST_PERI_POS      (          6)
+#define GPDMA_CH_CONFIG_DEST_PERI_MSK      (0x1F  << GPDMA_CH_CONFIG_DEST_PERI_POS)
+#define GPDMA_CH_CONFIG_DEST_PERI(n)       (((n)  << GPDMA_CH_CONFIG_DEST_PERI_POS) & GPDMA_CH_CONFIG_DEST_PERI_MSK)
+#define GPDMA_CH_CONFIG_FLOWCNTRL_POS      (         11)
+#define GPDMA_CH_CONFIG_FLOWCNTRL_MSK      (0x03  << GPDMA_CH_CONFIG_FLOWCNTRL_POS)
+#define GPDMA_CH_CONFIG_FLOWCNTRL(n)       (((n)  << GPDMA_CH_CONFIG_FLOWCNTRL_POS) & GPDMA_CH_CONFIG_FLOWCNTRL_MSK)
+#define GPDMA_CH_CONFIG_IE                 (1     << 14)
+#define GPDMA_CH_CONFIG_ITC                (1     << 15)
+#define GPDMA_CH_CONFIG_L                  (1     << 16)
+#define GPDMA_CH_CONFIG_A                  (1     << 17)
+#define GPDMA_CH_CONFIG_H                  (1     << 18)
+
+// GPDMA Channel Control register definition
+#define GPDMA_CH_CONTROL_TRANSFERSIZE_POS  (          0)
+#define GPDMA_CH_CONTROL_TRANSFERSIZE_MSK  (0xFFF << GPDMA_CH_CONTROL_TRANSFERSIZE_POS)
+#define GPDMA_CH_CONTROL_TRANSFERSIZE(n)   (((n)  << GPDMA_CH_CONTROL_TRANSFERSIZE_POS) & GPDMA_CH_CONTROL_TRANSFERSIZE_MSK)
+#define GPDMA_CH_CONTROL_SBSIZE_POS        (         12)
+#define GPDMA_CH_CONTROL_SBSIZE_MSK        (0x03  << GPDMA_CH_CONTROL_SBSIZE_POS)
+#define GPDMA_CH_CONTROL_SBSIZE(n)         (((n)  << GPDMA_CH_CONTROL_SBSIZE_POS) & GPDMA_CH_CONTROL_SBSIZE_MSK)
+#define GPDMA_CH_CONTROL_DBSIZE_POS        (         15)
+#define GPDMA_CH_CONTROL_DBSIZE_MSK        (0x03  << GPDMA_CH_CONTROL_DBSIZE_POS)
+#define GPDMA_CH_CONTROL_DBSIZE(n)         (((n)  << GPDMA_CH_CONTROL_DBSIZE_POS) & GPDMA_CH_CONTROL_DBSIZE_MSK)
+#define GPDMA_CH_CONTROL_SWIDTH_POS        (         18)
+#define GPDMA_CH_CONTROL_SWIDTH_MSK        (0x03  << GPDMA_CH_CONTROL_SWIDTH_POS)
+#define GPDMA_CH_CONTROL_SWIDTH(n)         (((n)  << GPDMA_CH_CONTROL_SWIDTH_POS) & GPDMA_CH_CONTROL_SWIDTH_MSK)
+#define GPDMA_CH_CONTROL_DWIDTH_POS        (         21)
+#define GPDMA_CH_CONTROL_DWIDTH_MSK        (0x03  << GPDMA_CH_CONTROL_DWIDTH_POS)
+#define GPDMA_CH_CONTROL_DWIDTH(n)         (((n)  << GPDMA_CH_CONTROL_DWIDTH_POS) & GPDMA_CH_CONTROL_DWIDTH_MSK)
+#define GPDMA_CH_CONTROL_S                 (1     << 24)
+#define GPDMA_CH_CONTROL_D                 (1     << 25)
+#define GPDMA_CH_CONTROL_SI                (1     << 26)
+#define GPDMA_CH_CONTROL_DI                (1     << 27)
+#define GPDMA_CH_CONTROL_PROT1             (1     << 28)
+#define GPDMA_CH_CONTROL_PROT2             (1     << 29)
+#define GPDMA_CH_CONTROL_PROT3             (1     << 30)
+#define GPDMA_CH_CONTROL_I                 (1UL   << 31)
+
+/**
+  \fn          void GPDMA_SignalEvent_t (uint32_t event)
+  \brief       Signal GPDMA Events.
+  \param[in]   event  GPDMA Event mask
+  \return      none
+*/
+typedef void (*GPDMA_SignalEvent_t) (uint32_t event);
+
+/**
+  \fn          int32_t GPDMA_Initialize (void)
+  \brief       Initialize GPDMA peripheral
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+extern int32_t GPDMA_Initialize (void);
+
+/**
+  \fn          int32_t GPDMA_Uninitialize (void)
+  \brief       De-initialize GPDMA peripheral
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+extern int32_t GPDMA_Uninitialize (void);
+
+/**
+  \fn          int32_t GPDMA_PeripheralSelect (uint8_t peri, uint8_t sel)
+  \brief       Selects GPDMA requests
+  \param[in]   peri GPDMA peripheral (0..15)
+  \param[in]   sel  Selects the DMA request for GPDMA input (0..3)
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+extern int32_t GPDMA_PeripheralSelect (uint8_t peri, uint8_t sel);
+
+/**
+  \fn          int32_t GPDMA_ChannelConfigure (uint8_t              ch,
+                                               uint32_t             src_addr,
+                                               uint32_t             dest_addr,
+                                               uint32_t             size,
+                                               uint32_t             control,
+                                               uint32_t             config,
+                                               GPDMA_SignalEvent_t  cb_event)
+  \brief       Configure GPDMA channel for next transfer
+  \param[in]   ch        Channel number (0..7)
+  \param[in]   src_addr  Source address
+  \param[in]   dest_addr Destination address
+  \param[in]   size      Amount of data to transfer
+  \param[in]   control   Channel control
+  \param[in]   config    Channel configuration
+  \param[in]   cb_event  Channel callback pointer
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+extern int32_t GPDMA_ChannelConfigure (uint8_t              ch,
+                                       uint32_t             src_addr,
+                                       uint32_t             dest_addr,
+                                       uint32_t             size,
+                                       uint32_t             control,
+                                       uint32_t             config,
+                                       GPDMA_SignalEvent_t  cb_event);
+
+/**
+  \fn          int32_t GPDMA_ChannelEnable (uint8_t ch)
+  \brief       Enable GPDMA channel
+  \param[in]   ch Channel number (0..7)
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+extern int32_t GPDMA_ChannelEnable (uint8_t ch);
+
+/**
+  \fn          int32_t GPDMA_ChannelDisable (uint8_t ch)
+  \brief       Disable GPDMA channel
+  \param[in]   ch Channel number (0..7)
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+extern int32_t GPDMA_ChannelDisable (uint8_t ch);
+
+/**
+  \fn          uint32_t GPDMA_ChannelGetStatus (uint8_t ch)
+  \brief       Check if GPDMA channel is enabled or disabled
+  \param[in]   ch Channel number (0..7)
+  \returns     Channel status
+   - \b  1: channel enabled
+   - \b  0: channel disabled
+*/
+extern uint32_t GPDMA_ChannelGetStatus (uint8_t ch);
+
+/**
+  \fn          uint32_t GPDMA_ChannelGetCount (uint8_t ch)
+  \brief       Get number of transferred data
+  \param[in]   ch Channel number (0..7)
+  \returns     Number of transferred data
+*/
+extern uint32_t GPDMA_ChannelGetCount (uint8_t ch);
+
+#endif /* __GPDMA_LPC18XX_H */

CMSIS/Pack/Example/CMSIS_Driver/GPIO_LPC18xx.c

@@ -0,0 +1,106 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        02. March 2016
+ * $Revision:    V1.0
+ *
+ * Project:      GPIO Driver for NXP LPC18xx
+ * -------------------------------------------------------------------------- */
+
+#include "LPC18xx.h"
+#include "GPIO_LPC18xx.h"
+
+/**
+  \fn          void GPIO_PortClock (uint32_t clock)
+  \brief       Port Clock Control
+  \param[in]   clock  Enable or disable clock
+*/
+void GPIO_PortClock (uint32_t clock) {
+  if (clock) {
+    LPC_CCU1->CLK_M3_GPIO_CFG |= 3;
+    while (!(LPC_CCU1->CLK_M3_GPIO_STAT & 1));
+  }
+  else {
+    LPC_CCU1->CLK_M3_GPIO_CFG   &= ~(3);
+    while (LPC_CCU1->CLK_M3_GPIO_STAT & 1);
+  }
+}
+
+/**
+  \fn          void GPIO_SetDir (uint32_t port_num,
+                                 uint32_t pin_num,
+                                 uint32_t dir)
+  \brief       Configure GPIO pin direction
+  \param[in]   port_num   GPIO number (0..7)
+  \param[in]   pin_num    Port pin number
+  \param[in]   dir        GPIO_DIR_INPUT, GPIO_DIR_OUTPUT
+*/
+void GPIO_SetDir (uint32_t port_num, uint32_t pin_num, uint32_t dir) {
+
+  dir  ? (LPC_GPIO_PORT->DIR[port_num] |=  (1UL << pin_num)) : \
+         (LPC_GPIO_PORT->DIR[port_num] &= ~(1UL << pin_num));
+}
+
+/**
+  \fn          void GPIO_PinWrite (uint32_t port_num,
+                                   uint32_t pin_num,
+                                   uint32_t val)
+  \brief       Write port pin
+  \param[in]   port_num   GPIO number (0..7)
+  \param[in]   pin_num    Port pin number
+  \param[in]   val        Port pin value (0 or 1)
+*/
+void GPIO_PinWrite (uint32_t port_num, uint32_t pin_num, uint32_t val) {
+
+  val ? (LPC_GPIO_PORT->SET[port_num] = (1UL << pin_num)) : \
+        (LPC_GPIO_PORT->CLR[port_num] = (1UL << pin_num));
+}
+
+/**
+  \fn          uint32_t GPIO_PinRead (uint32_t port_num, uint32_t pin_num)
+  \brief       Read port pin
+  \param[in]   port_num   GPIO number (0..7)
+  \param[in]   pin_num    Port pin number
+  \return      pin value (0 or 1)
+*/
+uint32_t GPIO_PinRead (uint32_t port_num, uint32_t pin_num) {
+  return ((LPC_GPIO_PORT->PIN[port_num] & (1UL << pin_num)) ? (1) : (0));
+}
+
+/**
+  \fn          void GPIO_PortWrite (uint32_t port_num,
+                                    uint32_t mask,
+                                    uint32_t val)
+  \brief       Write port pins
+  \param[in]   port_num   GPIO number (0..7)
+  \param[in]   mask       Selected pins
+  \param[in]   val        Pin values
+*/
+void GPIO_PortWrite (uint32_t port_num, uint32_t mask, uint32_t val) {
+  LPC_GPIO_PORT->MASK[port_num] = ~mask;
+  LPC_GPIO_PORT->MPIN[port_num] =  val;
+}
+
+/**
+  \fn          uint32_t  GPIO_PortRead (uint32_t port_num)
+  \brief       Read port pins
+  \param[in]   port_num   GPIO number (0..7)
+  \return      port pin inputs
+*/
+uint32_t GPIO_PortRead (uint32_t port_num) {
+  return (LPC_GPIO_PORT->PIN[port_num]);
+}

CMSIS/Pack/Example/CMSIS_Driver/GPIO_LPC18xx.h

@@ -0,0 +1,99 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        02. March 2016
+ * $Revision:    V1.0
+ *
+ * Project:      GPIO Driver Definitions for NXP LPC18xx
+ * -------------------------------------------------------------------------- */
+
+#ifndef __GPIO_LPC18XX_H
+#define __GPIO_LPC18XX_H
+
+#include <stdint.h>
+
+// GPIO identifier
+typedef struct _GPIO_ID {
+  uint8_t       port;
+  uint8_t       num;
+} GPIO_ID;
+
+// GPIO Direction
+#define GPIO_DIR_INPUT     (0)
+#define GPIO_DIR_OUTPUT    (1)
+
+
+/**
+  \fn          void GPIO_PortClock (uint32_t clock)
+  \brief       Port Clock Control
+  \param[in]   clock  Enable or disable clock
+*/
+extern void GPIO_PortClock (uint32_t clock);
+
+/**
+  \fn          void GPIO_SetDir (uint32_t port_num,
+                                 uint32_t pin_num,
+                                 uint32_t dir)
+  \brief       Configure GPIO pin direction
+  \param[in]   port_num   GPIO number (0..7)
+  \param[in]   pin_num    Port pin number
+  \param[in]   dir        GPIO_DIR_INPUT, GPIO_DIR_OUTPUT
+*/
+extern void GPIO_SetDir (uint32_t port_num, uint32_t pin_num, uint32_t dir);
+
+/**
+  \fn          void GPIO_PinWrite (uint32_t port_num,
+                                   uint32_t pin_num,
+                                   uint32_t val)
+  \brief       Write port pin
+  \param[in]   port_num   GPIO number (0..7)
+  \param[in]   pin_num    Port pin number
+  \param[in]   val        Port pin value (0 or 1)
+*/
+extern void GPIO_PinWrite (uint32_t port_num,
+                           uint32_t pin_num,
+                           uint32_t val);
+
+/**
+  \fn          uint32_t  GPIO_PinRead (uint32_t port_num, uint32_t pin_num)
+  \brief       Read port pin
+  \param[in]   port_num   GPIO number (0..7)
+  \param[in]   pin_num    Port pin number
+  \return      pin value (0 or 1)
+*/
+extern uint32_t GPIO_PinRead (uint32_t port_num, uint32_t pin_num);
+
+/**
+  \fn          void GPIO_PortWrite (uint32_t port_num,
+                                    uint32_t mask,
+                                    uint32_t val)
+  \brief       Write port pins
+  \param[in]   port_num   GPIO number (0..7)
+  \param[in]   mask       Selected pins
+  \param[in]   val        Pin values
+*/
+extern void GPIO_PortWrite (uint32_t port_num, uint32_t mask, uint32_t val);
+
+/**
+  \fn          uint32_t  GPIO_PortRead (uint32_t port_num)
+  \brief       Read port pins
+  \param[in]   port_num   GPIO number (0..7)
+  \return      port pin inputs
+*/
+extern uint32_t GPIO_PortRead (uint32_t port_num);
+
+#endif /* __GPIO_LPC18XX_H */

CMSIS/Pack/Example/CMSIS_Driver/I2C_LPC18xx.c

@@ -0,0 +1,968 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        02. March 2016
+ * $Revision:    V2.4
+ *
+ * Driver:       Driver_I2C0, Driver_I2C1
+ * Configured:   via RTE_Device.h configuration file
+ * Project:      I2C Driver for NXP LPC18xx
+ * --------------------------------------------------------------------------
+ * Use the following configuration settings in the middleware component
+ * to connect to this driver.
+ *
+ *   Configuration Setting                 Value   I2C Interface
+ *   ---------------------                 -----   -------------
+ *   Connect to hardware via Driver_I2C# = 0       use I2C0
+ *   Connect to hardware via Driver_I2C# = 1       use I2C1
+ * -------------------------------------------------------------------------- */
+
+/* History:
+ *  Version 2.4
+ *   - Added Bus Clear Control 
+ *   - Corrected PowerControl function for conditional Power full (driver must be initialized)
+ *  Version 2.3
+ *    - Pending IRQ flag cleared after aborted transfer
+ *  Version 2.2
+ *    - Updated initialization, uninitialization and power procedures
+ *  Version 2.1
+ *    - Updated to CMSIS Driver API V2.02
+ *    - Added Multi-master support
+ *  Version 2.0
+ *    - Based on API V2.00
+ *  Version 1.1
+ *    - Based on API V1.10 (namespace prefix ARM_ added)
+ *  Version 1.0
+ *    - Initial release
+ */
+
+#include <string.h>
+
+#include "I2C_LPC18xx.h"
+#include "SCU_LPC18xx.h"
+
+#include "Driver_I2C.h"
+
+#include "RTE_Device.h"
+#include "RTE_Components.h"
+
+#define ARM_I2C_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,4) /* driver version */
+
+#if ((defined(RTE_Drivers_I2C0) || \
+      defined(RTE_Drivers_I2C1))   \
+     && !RTE_I2C0                  \
+     && !RTE_I2C1)
+#error "I2C not configured in RTE_Device.h!"
+#endif
+
+/* I2C core clock (system_LPC18xx.c) */
+extern uint32_t GetClockFreq (uint32_t clk_src);
+
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = {
+  ARM_I2C_API_VERSION,
+  ARM_I2C_DRV_VERSION
+};
+
+/* Driver Capabilities */
+static const ARM_I2C_CAPABILITIES DriverCapabilities = {
+  0            /* supports 10-bit addressing */
+};
+
+
+#if (RTE_I2C0)
+/* I2C0 Control Information */
+static I2C_CTRL I2C0_Ctrl = { 0 };
+
+/* I2C0 Resources */
+static I2C_RESOURCES I2C0_Resources = {
+  LPC_I2C0,
+  I2C0_IRQn,
+  &LPC_CGU->BASE_APB1_CLK,
+  &LPC_CCU1->CLK_APB1_I2C0_CFG,
+  &LPC_CCU1->CLK_APB1_I2C0_STAT,
+  RGU_RESET_I2C0,
+  &I2C0_Ctrl
+};
+#endif /* RTE_I2C0 */
+
+
+#if (RTE_I2C1)
+/* I2C1 Control Information */
+static I2C_CTRL I2C1_Ctrl = { 0 };
+
+/* I2C1 Resources */
+static I2C_RESOURCES I2C1_Resources = {
+  LPC_I2C1,
+  I2C1_IRQn,
+  &LPC_CGU->BASE_APB3_CLK,
+  &LPC_CCU1->CLK_APB3_I2C1_CFG,
+  &LPC_CCU1->CLK_APB3_I2C1_STAT,
+  RGU_RESET_I2C1,
+  &I2C1_Ctrl
+};
+#endif /* RTE_I2C1 */
+
+
+/**
+  \fn          ARM_DRIVER_VERSION I2C_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+*/
+static ARM_DRIVER_VERSION I2C_GetVersion (void) {
+  return DriverVersion;
+}
+
+/**
+  \fn          ARM_I2C_CAPABILITIES I2C_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_I2C_CAPABILITIES
+*/
+static ARM_I2C_CAPABILITIES I2C_GetCapabilities (void) {
+  return DriverCapabilities;
+}
+
+/**
+  \fn          int32_t I2Cx_Initialize (ARM_I2C_SignalEvent_t cb_event,
+                                        I2C_RESOURCES         *i2c)
+  \brief       Initialize I2C Interface.
+  \param[in]   cb_event  Pointer to \ref ARM_I2C_SignalEvent
+  \param[in]   i2c   Pointer to I2C resources
+  \return      \ref execution_status
+*/
+static int32_t I2Cx_Initialize (ARM_I2C_SignalEvent_t cb_event, I2C_RESOURCES *i2c) {
+
+  if (i2c->ctrl->flags & I2C_FLAG_INIT) { return ARM_DRIVER_OK; }
+
+  /* Configure I2C Pins */
+  if (i2c->reg == LPC_I2C0) {
+    SCU_I2C_PinConfigure (SCU_I2C_PIN_MODE_STANDARD_FAST);
+  }
+  else if (i2c->reg == LPC_I2C1) { 
+    SCU_PinConfigure (RTE_I2C1_SCL_PORT, RTE_I2C1_SCL_PIN, SCU_SFS_EZI | RTE_I2C1_SCL_FUNC);
+    SCU_PinConfigure (RTE_I2C1_SDA_PORT, RTE_I2C1_SDA_PIN, SCU_SFS_EZI | RTE_I2C1_SDA_FUNC);
+  }
+
+  /* Reset Run-Time information structure */
+  memset (i2c->ctrl, 0x00, sizeof (I2C_CTRL));
+
+  i2c->ctrl->cb_event = cb_event;
+  i2c->ctrl->flags    = I2C_FLAG_INIT;
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t I2Cx_Uninitialize (I2C_RESOURCES *i2c)
+  \brief       De-initialize I2C Interface.
+  \param[in]   i2c   Pointer to I2C resources
+  \return      \ref execution_status
+*/
+static int32_t I2Cx_Uninitialize (I2C_RESOURCES *i2c) {
+
+  i2c->ctrl->flags = 0;
+
+  /* Unconfigure SCL and SDA pins */
+  if (i2c->reg == LPC_I2C0) {
+    SCU_I2C_PinConfigure (0);
+  }
+  else if (i2c->reg == LPC_I2C1) { 
+    SCU_PinConfigure (RTE_I2C1_SCL_PORT, RTE_I2C1_SCL_PIN, 0);
+    SCU_PinConfigure (RTE_I2C1_SDA_PORT, RTE_I2C1_SDA_PIN, 0);
+  }
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t I2Cx_PowerControl (ARM_POWER_STATE state,
+                                          I2C_RESOURCES   *i2c)
+  \brief       Control I2C Interface Power.
+  \param[in]   state  Power state
+  \param[in]   i2c    Pointer to I2C resources
+  \return      \ref execution_status
+*/
+static int32_t I2Cx_PowerControl (ARM_POWER_STATE state, I2C_RESOURCES *i2c) {
+  uint32_t conset;
+
+  switch (state) {
+    case ARM_POWER_OFF:
+      /* Disable I2C interrupts */
+      NVIC_DisableIRQ (i2c->i2c_ev_irq);
+
+      if (i2c->ctrl->status.busy) {
+        /* Master: send STOP to I2C bus           */
+        /* Slave:  enter non-addressed Slave mode */
+        conset = I2C_CON_STO | i2c->ctrl->con_aa;
+        i2c->reg->CONSET = conset; 
+        i2c->reg->CONCLR = conset ^ I2C_CON_FLAGS;
+      }
+
+      i2c->ctrl->status.busy             = 0U;
+      i2c->ctrl->status.mode             = 0U;
+      i2c->ctrl->status.direction        = 0U;
+      i2c->ctrl->status.general_call     = 0U;
+      i2c->ctrl->status.arbitration_lost = 0U;
+      i2c->ctrl->status.bus_error        = 0U;
+
+      i2c->ctrl->stalled = 0U;
+      i2c->ctrl->snum    = 0U;
+
+      i2c->ctrl->flags  &= ~I2C_FLAG_POWER;
+
+      /* Reset I2C peripheral */
+      LPC_RGU->RESET_CTRL1 = i2c->rgu_val;
+      while (!(LPC_RGU->RESET_ACTIVE_STATUS1 & i2c->rgu_val));
+
+      /* Disable I2C peripheral clock */
+      *i2c->pclk_cfg_reg &= ~CCU_CLK_CFG_RUN;
+      break;
+
+    case ARM_POWER_FULL:
+      if ((i2c->ctrl->flags & I2C_FLAG_INIT)  == 0U) { return ARM_DRIVER_ERROR; }
+      if ((i2c->ctrl->flags & I2C_FLAG_POWER) != 0U) { return ARM_DRIVER_OK; }
+
+      /* Connect base clock */
+      *i2c->base_clk_reg = (1    << 11) |     /* Autoblock En               */
+                           (0x09 << 24) ;     /* PLL1 is APB  clock source  */
+
+      /* Enable I2C peripheral clock */
+      *i2c->pclk_cfg_reg = CCU_CLK_CFG_AUTO | CCU_CLK_CFG_RUN;
+      while (!((*i2c->pclk_stat_reg) & CCU_CLK_STAT_RUN));
+
+      /* Reset I2C peripheral */
+      LPC_RGU->RESET_CTRL1 = i2c->rgu_val;
+      while (!(LPC_RGU->RESET_ACTIVE_STATUS1 & i2c->rgu_val));
+
+      /* Enable I2C Operation */
+      i2c->reg->CONCLR = I2C_CON_FLAGS;
+      i2c->reg->CONSET = I2C_CON_I2EN;
+
+      i2c->ctrl->stalled = 0;
+      i2c->ctrl->con_aa  = 0;
+
+      /* Enable I2C interrupts */
+      NVIC_ClearPendingIRQ (i2c->i2c_ev_irq);
+      NVIC_EnableIRQ (i2c->i2c_ev_irq);
+
+      i2c->ctrl->flags |= I2C_FLAG_POWER;
+      break;
+
+    default:
+      return ARM_DRIVER_ERROR_UNSUPPORTED;
+  }
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t I2Cx_MasterTransmit (uint32_t       addr,
+                                            const uint8_t *data,
+                                            uint32_t       num,
+                                            bool           xfer_pending,
+                                            I2C_RESOURCES *i2c)
+  \brief       Start transmitting data as I2C Master.
+  \param[in]   addr          Slave address (7-bit or 10-bit)
+  \param[in]   data          Pointer to buffer with data to transmit to I2C Slave
+  \param[in]   num           Number of data bytes to transmit
+  \param[in]   xfer_pending  Transfer operation is pending - Stop condition will not be generated
+  \param[in]   i2c           Pointer to I2C resources
+  \return      \ref execution_status
+*/
+static int32_t I2Cx_MasterTransmit (uint32_t       addr,
+                                    const uint8_t *data,
+                                    uint32_t       num,
+                                    bool           xfer_pending,
+                                    I2C_RESOURCES *i2c) {
+
+  if (!data || !num || (addr > 0x7F)) {
+    /* Invalid parameters */
+    return ARM_DRIVER_ERROR_PARAMETER;
+  }
+
+  if (!(i2c->ctrl->flags & I2C_FLAG_SETUP)) {
+    /* Driver not yet configured */
+    return ARM_DRIVER_ERROR;
+  }
+
+  if (i2c->ctrl->status.busy || (i2c->ctrl->stalled & I2C_SLAVE)) {
+    /* Transfer operation in progress, or Slave stalled */
+    return ARM_DRIVER_ERROR_BUSY;
+  }
+
+  NVIC_DisableIRQ (i2c->i2c_ev_irq);
+
+  /* Set control variables */
+  i2c->ctrl->sla_rw  = addr << 1;
+  i2c->ctrl->pending = xfer_pending;
+  i2c->ctrl->data    = (uint8_t *)data;
+  i2c->ctrl->num     = num;
+  i2c->ctrl->cnt     = -1;
+
+  /* Update driver status */
+  i2c->ctrl->status.busy             = 1;
+  i2c->ctrl->status.mode             = 1;
+  i2c->ctrl->status.direction        = 0;
+  i2c->ctrl->status.arbitration_lost = 0;
+  i2c->ctrl->status.bus_error        = 0;
+  if (!i2c->ctrl->stalled) {
+    i2c->reg->CONSET = I2C_CON_STA | i2c->ctrl->con_aa;
+  }
+
+  NVIC_EnableIRQ (i2c->i2c_ev_irq);
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t I2Cx_MasterReceive (uint32_t       addr,
+                                           uint8_t       *data,
+                                           uint32_t       num,
+                                           bool           xfer_pending,
+                                           I2C_RESOURCES *i2c)
+  \brief       Start receiving data as I2C Master.
+  \param[in]   addr          Slave address (7-bit or 10-bit)
+  \param[out]  data          Pointer to buffer for data to receive from I2C Slave
+  \param[in]   num           Number of data bytes to receive
+  \param[in]   xfer_pending  Transfer operation is pending - Stop condition will not be generated
+  \param[in]   i2c           Pointer to I2C resources
+  \return      \ref execution_status
+*/
+static int32_t I2Cx_MasterReceive (uint32_t       addr,
+                                   uint8_t       *data,
+                                   uint32_t       num,
+                                   bool           xfer_pending,
+                                   I2C_RESOURCES *i2c) {
+
+  if (!data || !num || (addr > 0x7F)) {
+    /* Invalid parameters */ 
+    return ARM_DRIVER_ERROR_PARAMETER;
+  }
+
+  if (!(i2c->ctrl->flags & I2C_FLAG_SETUP)) {
+    /* Driver not yet configured */
+    return ARM_DRIVER_ERROR;
+  }
+
+  if (i2c->ctrl->status.busy || (i2c->ctrl->stalled & I2C_SLAVE)) {
+    /* Transfer operation in progress, or Slave stalled */
+    return ARM_DRIVER_ERROR_BUSY;
+  }
+
+  NVIC_DisableIRQ (i2c->i2c_ev_irq);
+
+  /* Set control variables */
+  i2c->ctrl->sla_rw  = (addr << 1) | 0x01;
+  i2c->ctrl->pending = xfer_pending;
+  i2c->ctrl->data    = data;
+  i2c->ctrl->num     = num;
+  i2c->ctrl->cnt     = -1;
+
+  /* Update driver status */
+  i2c->ctrl->status.busy             = 1;
+  i2c->ctrl->status.mode             = 1;
+  i2c->ctrl->status.direction        = 0;
+  i2c->ctrl->status.arbitration_lost = 0;
+  i2c->ctrl->status.bus_error        = 0;
+  if (!i2c->ctrl->stalled) {
+    i2c->reg->CONSET = I2C_CON_STA | i2c->ctrl->con_aa;
+  }
+
+  NVIC_EnableIRQ (i2c->i2c_ev_irq);
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t I2Cx_SlaveTransmit (const uint8_t *data,
+                                           uint32_t       num,
+                                           I2C_RESOURCES *i2c)
+  \brief       Start transmitting data as I2C Slave.
+  \param[in]   data  Pointer to buffer with data to transmit to I2C Master
+  \param[in]   num   Number of data bytes to transmit
+  \param[in]   i2c   Pointer to I2C resources
+  \return      \ref execution_status
+*/
+static int32_t I2Cx_SlaveTransmit (const uint8_t *data,
+                                   uint32_t       num,
+                                   I2C_RESOURCES *i2c) {
+
+  if (!data || !num) {
+    /* Invalid parameters */
+    return ARM_DRIVER_ERROR_PARAMETER;
+  }
+
+  if (i2c->ctrl->status.busy || (i2c->ctrl->stalled & (I2C_MASTER | I2C_SLAVE_RX))) {
+    /* Transfer operation in progress, Master stalled or Slave receive stalled */
+    return ARM_DRIVER_ERROR_BUSY;
+  }
+
+  NVIC_DisableIRQ (i2c->i2c_ev_irq);
+
+  /* Set control variables */
+  i2c->ctrl->flags &= ~I2C_FLAG_SLAVE_RX;
+  i2c->ctrl->sdata  = (uint8_t *)data;
+  i2c->ctrl->snum   = num;
+  i2c->ctrl->cnt    = -1;
+
+  /* Update driver status */
+  i2c->ctrl->status.general_call = 0;
+  i2c->ctrl->status.bus_error    = 0;
+
+  NVIC_EnableIRQ (i2c->i2c_ev_irq);
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t I2Cx_SlaveReceive (uint8_t       *data,
+                                          uint32_t       num,
+                                          I2C_RESOURCES *i2c)
+  \brief       Start receiving data as I2C Slave.
+  \param[out]  data  Pointer to buffer for data to receive from I2C Master
+  \param[in]   num   Number of data bytes to receive
+  \param[in]   i2c   Pointer to I2C resources
+  \return      \ref execution_status
+*/
+static int32_t I2Cx_SlaveReceive (uint8_t       *data,
+                                  uint32_t       num,
+                                  I2C_RESOURCES *i2c) {
+
+  if (!data || !num) {
+    /* Invalid parameters */ 
+    return ARM_DRIVER_ERROR_PARAMETER;
+  }
+
+  if (i2c->ctrl->status.busy || (i2c->ctrl->stalled & (I2C_MASTER | I2C_SLAVE_TX))) {
+    /* Transfer operation in progress, Master stalled or Slave transmit stalled */
+    return ARM_DRIVER_ERROR_BUSY;
+  }
+
+  NVIC_DisableIRQ (i2c->i2c_ev_irq);
+
+  /* Set control variables */
+  i2c->ctrl->flags |= I2C_FLAG_SLAVE_RX;
+  i2c->ctrl->sdata  = data;
+  i2c->ctrl->snum   = num;
+  i2c->ctrl->cnt    = -1;
+
+  /* Update driver status */
+  i2c->ctrl->status.general_call = 0;
+  i2c->ctrl->status.bus_error    = 0;
+
+  NVIC_EnableIRQ (i2c->i2c_ev_irq);
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t I2Cx_GetDataCount (I2C_RESOURCES *i2c)
+  \brief       Get transferred data count.
+  \return      number of data bytes transferred; -1 when Slave is not addressed by Master
+*/
+static int32_t I2Cx_GetDataCount (I2C_RESOURCES *i2c) {
+  return (i2c->ctrl->cnt);
+}
+
+/**
+  \fn          int32_t I2Cx_Control (uint32_t       control,
+                                     uint32_t       arg,
+                                     I2C_RESOURCES *i2c)
+  \brief       Control I2C Interface.
+  \param[in]   control  operation
+  \param[in]   arg      argument of operation (optional)
+  \param[in]   i2c      pointer to I2C resources
+  \return      \ref execution_status
+*/
+static int32_t I2Cx_Control (uint32_t control, uint32_t arg, I2C_RESOURCES *i2c) {
+  uint32_t val,clk,conset;
+
+  if (!(i2c->ctrl->flags & I2C_FLAG_POWER)) {
+    /* Driver not powered */
+    return ARM_DRIVER_ERROR;
+  }
+  switch (control) {
+    case ARM_I2C_OWN_ADDRESS:
+      /* Set Own Slave Address */
+      val = (arg << 1) & 0xFF;
+      if (arg & ARM_I2C_ADDRESS_GC) {
+        /* General call enable */
+        val |= 0x01;
+      }
+      i2c->reg->ADR0 = val;
+
+      /* Enable assert acknowledge */
+      if (val) val = I2C_CON_AA;
+      i2c->ctrl->con_aa = val;
+      i2c->reg->CONSET  = val;
+      break;
+
+    case ARM_I2C_BUS_SPEED:
+      /* Set Bus Speed */
+      clk = GetClockFreq (CLK_SRC_PLL1);
+      switch (arg) {
+        case ARM_I2C_BUS_SPEED_STANDARD:
+          /* Standard Speed (100kHz) */
+          clk /= 100000;
+          break;
+        case ARM_I2C_BUS_SPEED_FAST:
+          /* Fast Speed     (400kHz) */
+          clk /= 400000;
+          break;
+        case ARM_I2C_BUS_SPEED_FAST_PLUS:
+          /* Fast+ Speed    (  1MHz) */
+          if (i2c->reg == LPC_I2C0) {
+            clk /= 1000000;
+            break;
+          }
+        default:
+          return ARM_DRIVER_ERROR_UNSUPPORTED;
+      }
+      /* Improve accuracy */
+      i2c->reg->SCLH = clk / 2;
+      i2c->reg->SCLL = clk - i2c->reg->SCLH;
+
+      /* Speed configured, I2C Master active */
+      i2c->ctrl->flags |= I2C_FLAG_SETUP;
+      break;
+
+    case ARM_I2C_BUS_CLEAR:
+      /* Execute Bus clear */
+      NVIC_DisableIRQ (i2c->i2c_ev_irq);
+
+      i2c->reg->CONSET = I2C_CON_STA;
+      __NOP(); __NOP(); __NOP();
+      if ((i2c->reg->CONSET & I2C_CON_SI) == 0) {
+        for (val = 0; val < 2048; val++);
+      }
+      /* Clear start and interrupt flag */
+      i2c->reg->CONCLR = I2C_CON_STA | I2C_CON_SI;
+      /* Send STOP to end the transaction */
+      i2c->reg->CONSET = I2C_CON_STO;
+
+      NVIC_ClearPendingIRQ (i2c->i2c_ev_irq);
+      NVIC_EnableIRQ (i2c->i2c_ev_irq);
+      return ARM_DRIVER_OK;
+
+    case ARM_I2C_ABORT_TRANSFER:
+      /* Abort Master/Slave transfer */
+      NVIC_DisableIRQ (i2c->i2c_ev_irq);
+
+      i2c->ctrl->status.busy = 0;
+      i2c->ctrl->stalled = 0;
+      i2c->ctrl->snum    = 0;
+      /* Master: send STOP to I2C bus           */
+      /* Slave:  enter non-addressed Slave mode */
+      conset = I2C_CON_STO | i2c->ctrl->con_aa;
+      i2c->reg->CONSET = conset; 
+      i2c->reg->CONCLR = conset ^ I2C_CON_FLAGS;
+
+      NVIC_ClearPendingIRQ (i2c->i2c_ev_irq);
+      NVIC_EnableIRQ (i2c->i2c_ev_irq);
+      break;
+
+    default:
+      return ARM_DRIVER_ERROR_UNSUPPORTED;
+  }
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          ARM_I2C_STATUS I2Cx_GetStatus (I2C_RESOURCES *i2c)
+  \brief       Get I2C status.
+  \param[in]   i2c      pointer to I2C resources
+  \return      I2C status \ref ARM_I2C_STATUS
+*/
+static ARM_I2C_STATUS I2Cx_GetStatus (I2C_RESOURCES *i2c) {
+  return (i2c->ctrl->status);
+}
+
+/**
+  \fn          void I2Cx_MasterHandler (I2C_RESOURCES *i2c)
+  \brief       I2C Master state event handler.
+  \param[in]   i2c  Pointer to I2C resources
+  \return      I2C event notification flags
+*/
+static uint32_t I2Cx_MasterHandler (I2C_RESOURCES *i2c) {
+  uint32_t conset = i2c->ctrl->con_aa;
+  uint32_t event  = 0;
+
+  if (i2c->ctrl->stalled) {
+    /* Master resumes with repeated START here */
+    /* Stalled states: I2C_STAT_MA_DT_A        */
+    /*                 I2C_STAT_MA_DR_NA       */
+    i2c->ctrl->stalled = 0;
+    conset |= I2C_CON_STA;
+    goto write_con;
+  }
+
+  switch (i2c->reg->STAT & 0xF8) {
+    case I2C_STAT_BUSERR:
+      /* I2C Bus error */
+      i2c->ctrl->status.bus_error = 1;
+      i2c->ctrl->status.busy      = 0;
+      i2c->ctrl->status.mode      = 0;
+      event = ARM_I2C_EVENT_BUS_ERROR      |
+              ARM_I2C_EVENT_TRANSFER_DONE  |
+              ARM_I2C_EVENT_TRANSFER_INCOMPLETE;
+      conset |= I2C_CON_STO;
+      break;
+
+    case I2C_STAT_MA_START:
+      /* START transmitted */
+    case I2C_STAT_MA_RSTART:
+      /* Repeated START transmitted */
+      i2c->reg->DAT = i2c->ctrl->sla_rw;
+      break;
+
+    case I2C_STAT_MA_SLAW_NA:
+      /* SLA+W transmitted, no ACK received */
+    case I2C_STAT_MA_SLAR_NA:
+      /* SLA+R transmitted, no ACK received */
+      i2c->ctrl->status.busy = 0;
+      i2c->ctrl->status.mode = 0;
+      event = ARM_I2C_EVENT_ADDRESS_NACK   |
+              ARM_I2C_EVENT_TRANSFER_DONE  |
+              ARM_I2C_EVENT_TRANSFER_INCOMPLETE;
+      conset |= I2C_CON_STO;
+      break;
+
+    case I2C_STAT_MA_SLAW_A:
+      /* SLA+W transmitted, ACK received */
+      i2c->ctrl->cnt = 0;
+      i2c->reg->DAT  = i2c->ctrl->data[0];
+      break;
+
+    case I2C_STAT_MA_DT_A:
+      /* Data transmitted, ACK received */
+      i2c->ctrl->cnt++;
+      i2c->ctrl->num--;
+      if (!i2c->ctrl->num) {
+        goto xfer_done;
+      }
+      /* Send next byte */
+      i2c->reg->DAT = i2c->ctrl->data[i2c->ctrl->cnt];
+      break;
+
+    case I2C_STAT_MA_DT_NA:
+      /* Data transmitted, no ACK received */
+      i2c->ctrl->status.busy = 0;
+      i2c->ctrl->status.mode = 0;
+      event = ARM_I2C_EVENT_TRANSFER_DONE  |
+              ARM_I2C_EVENT_TRANSFER_INCOMPLETE;
+      conset |= I2C_CON_STO;
+      break;
+
+    case I2C_STAT_MA_ALOST:
+      /* Arbitration lost */
+      i2c->ctrl->status.arbitration_lost = 1;
+      i2c->ctrl->status.busy             = 0;
+      i2c->ctrl->status.mode             = 0;
+      event = ARM_I2C_EVENT_ARBITRATION_LOST |
+              ARM_I2C_EVENT_TRANSFER_DONE    |
+              ARM_I2C_EVENT_TRANSFER_INCOMPLETE;
+      break;
+
+    case I2C_STAT_MA_SLAR_A:
+      /* SLA+R transmitted, ACK received */
+      i2c->ctrl->cnt = 0;
+      i2c->ctrl->status.direction = 1;
+      goto upd_conset;
+
+   case I2C_STAT_MA_DR_A:
+      /* Data received, ACK returned */
+      i2c->ctrl->data[i2c->ctrl->cnt++] = i2c->reg->DAT;
+      i2c->ctrl->num--;
+upd_conset:
+      conset = 0;
+      if (i2c->ctrl->num > 1) {
+        conset = I2C_CON_AA;
+      }
+      break;
+
+    case I2C_STAT_MA_DR_NA:
+      /* Data received, no ACK returned */
+      i2c->ctrl->data[i2c->ctrl->cnt++] = i2c->reg->DAT;
+      i2c->ctrl->num--;
+xfer_done:
+      i2c->ctrl->status.busy = 0;
+      event = ARM_I2C_EVENT_TRANSFER_DONE;
+      if (i2c->ctrl->pending) {
+        /* Stall I2C transaction */
+        NVIC_DisableIRQ (i2c->i2c_ev_irq);
+        i2c->ctrl->stalled = I2C_MASTER;
+        return (event);
+      }
+      /* Generate STOP */
+      conset |= I2C_CON_STO;
+      break;
+  }
+write_con:
+  /* Set/clear control flags */
+  i2c->reg->CONSET = conset;
+  i2c->reg->CONCLR = conset ^ I2C_CON_FLAGS;
+  return (event);
+}
+
+/**
+  \fn          void I2Cx_SlaveHandler (I2C_RESOURCES *i2c)
+  \brief       I2C Slave state event handler.
+  \param[in]   i2c  Pointer to I2C resources
+  \return      I2C event notification flags
+*/
+static uint32_t I2Cx_SlaveHandler (I2C_RESOURCES *i2c) {
+  uint32_t conset = 0;
+  uint32_t event  = 0;
+
+  switch (i2c->reg->STAT & 0xF8) {
+    case I2C_STAT_SL_ALOST_GC:
+      /* Arbitration lost in General call */
+      i2c->ctrl->status.arbitration_lost = 1;
+    case I2C_STAT_SL_GCA_A:
+      /* General address recvd, ACK returned */
+      i2c->ctrl->status.general_call     = 1;
+      goto slaw_a;
+
+    case I2C_STAT_SL_ALOST_MW:
+      /* Arbitration lost SLA+W */
+      i2c->ctrl->status.arbitration_lost = 1;
+    case I2C_STAT_SL_SLAW_A:
+      /* SLA+W received, ACK returned */
+slaw_a:
+      /* Stalled Slave receiver also resumes here */
+      if (!i2c->ctrl->snum || !(i2c->ctrl->flags & I2C_FLAG_SLAVE_RX)) {
+        /* Receive buffer unavailable */
+        if (i2c->ctrl->stalled) {
+          /* Already stalled, abort transaction to prevent dead-loops */
+          event = ARM_I2C_EVENT_TRANSFER_DONE |
+                  ARM_I2C_EVENT_TRANSFER_INCOMPLETE;
+          conset = I2C_CON_STO | i2c->ctrl->con_aa;
+          break;
+        }
+        /* Stall I2C transaction */
+        NVIC_DisableIRQ (i2c->i2c_ev_irq);
+        i2c->ctrl->stalled = I2C_SLAVE_RX;
+        return (ARM_I2C_EVENT_SLAVE_RECEIVE);
+      }
+      i2c->ctrl->status.direction = 1;
+      i2c->ctrl->status.busy      = 1;
+      i2c->ctrl->cnt     = 0;
+      i2c->ctrl->stalled = 0;
+      conset = I2C_CON_AA;
+      break;
+
+    case I2C_STAT_SL_DRGC_A:
+      /* Data recvd General call, ACK returned */
+    case I2C_STAT_SL_DR_A:
+      /* Data received, ACK returned */
+      i2c->ctrl->sdata[i2c->ctrl->cnt++] = i2c->reg->DAT;
+      i2c->ctrl->snum--;
+      if (i2c->ctrl->snum) {
+        conset = I2C_CON_AA;
+      }
+      break;
+
+    case I2C_STAT_SL_ALOST_MR:
+      /* Arbitration lost SLA+R */
+      i2c->ctrl->status.arbitration_lost = 1;
+    case I2C_STAT_SL_SLAR_A:
+      /* SLA+R received, ACK returned */
+      /* Stalled Slave transmitter also resumes here */
+      if (!i2c->ctrl->snum || (i2c->ctrl->flags & I2C_FLAG_SLAVE_RX)) {
+        /* Transmit buffer unavailable */
+        if (i2c->ctrl->stalled) {
+          /* Already stalled, abort transaction to prevent dead-loops */
+          event = ARM_I2C_EVENT_TRANSFER_DONE |
+                  ARM_I2C_EVENT_TRANSFER_INCOMPLETE;
+          conset = I2C_CON_STO | i2c->ctrl->con_aa;
+          break;
+        }
+        NVIC_DisableIRQ (i2c->i2c_ev_irq);
+        i2c->ctrl->stalled = I2C_SLAVE_TX;
+        return (ARM_I2C_EVENT_SLAVE_TRANSMIT);
+      }
+      i2c->ctrl->status.direction = 0;
+      i2c->ctrl->status.busy      = 1;
+      i2c->ctrl->cnt     = 0;
+      i2c->ctrl->stalled = 0;
+    case I2C_STAT_SL_DT_A:
+      /* Data transmitted, ACK received */
+      i2c->reg->DAT = i2c->ctrl->sdata[i2c->ctrl->cnt++];
+      i2c->ctrl->snum--;
+      if (i2c->ctrl->snum) {
+        conset = I2C_CON_AA;
+      }
+      break;
+
+    case I2C_STAT_SL_DT_NA:
+      /* Data transmitted, no ACK received */
+    case I2C_STAT_SL_LDT_A:
+      /* Last data transmitted, ACK received */
+    case I2C_STAT_SL_DR_NA:
+      /* Data received, no ACK returned */
+    case I2C_STAT_SL_DRGC_NA:
+      /* Data recvd General call, no ACK returned */
+    case I2C_STAT_SL_STOP:
+      /* STOP received while addressed */
+      i2c->ctrl->status.busy = 0;
+      /* Slave operation completed, generate events */
+      event = ARM_I2C_EVENT_TRANSFER_DONE;
+      if (i2c->ctrl->status.arbitration_lost) {
+        event |= ARM_I2C_EVENT_ARBITRATION_LOST;
+      }
+      if (i2c->ctrl->status.general_call) {
+        event |= ARM_I2C_EVENT_GENERAL_CALL;
+      }
+      if (i2c->ctrl->snum) {
+        event |= ARM_I2C_EVENT_TRANSFER_INCOMPLETE;
+      }
+      conset = i2c->ctrl->con_aa;
+      break;
+  }
+  /* Set/clear control flags */
+  i2c->reg->CONSET = conset;
+  i2c->reg->CONCLR = conset ^ I2C_CON_FLAGS;
+
+  return (event);
+}
+
+/**
+  \fn          void I2Cx_IRQHandler (I2C_RESOURCES *i2c)
+  \brief       I2C Event Interrupt handler.
+  \param[in]   i2c  Pointer to I2C resources
+*/
+static void I2Cx_IRQHandler (I2C_RESOURCES *i2c) {
+  uint32_t event;
+
+  if (i2c->reg->STAT < I2C_STAT_SL_SLAW_A) {
+    event = I2Cx_MasterHandler (i2c);
+  }
+  else {
+    event = I2Cx_SlaveHandler (i2c);
+  }
+  /* Callback event notification */
+  if (event && i2c->ctrl->cb_event) {
+    i2c->ctrl->cb_event (event);
+  }
+}
+
+#if (RTE_I2C0)
+/* I2C0 Driver wrapper functions */
+static int32_t I2C0_Initialize (ARM_I2C_SignalEvent_t cb_event) {
+  return (I2Cx_Initialize (cb_event, &I2C0_Resources));
+}
+static int32_t I2C0_Uninitialize (void) {
+  return (I2Cx_Uninitialize (&I2C0_Resources));
+}
+static int32_t I2C0_PowerControl (ARM_POWER_STATE state) {
+  return (I2Cx_PowerControl (state, &I2C0_Resources));
+}
+static int32_t I2C0_MasterTransmit (uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) {
+  return (I2Cx_MasterTransmit (addr, data, num, xfer_pending, &I2C0_Resources));
+}
+static int32_t I2C0_MasterReceive (uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) {
+  return (I2Cx_MasterReceive (addr, data, num, xfer_pending, &I2C0_Resources));
+}
+static int32_t I2C0_SlaveTransmit (const uint8_t *data, uint32_t num) {
+  return (I2Cx_SlaveTransmit (data, num, &I2C0_Resources));
+}
+static int32_t I2C0_SlaveReceive (uint8_t *data, uint32_t num) {
+  return (I2Cx_SlaveReceive (data, num, &I2C0_Resources));
+}
+static int32_t I2C0_GetDataCount (void) {
+  return (I2Cx_GetDataCount (&I2C0_Resources));
+}
+static int32_t I2C0_Control (uint32_t control, uint32_t arg) {
+  return (I2Cx_Control (control, arg, &I2C0_Resources));
+}
+static ARM_I2C_STATUS I2C0_GetStatus (void) {
+  return (I2Cx_GetStatus (&I2C0_Resources));
+}
+void I2C0_IRQHandler (void) {
+  I2Cx_IRQHandler (&I2C0_Resources);
+}
+
+/* I2C0 Driver Control Block */
+ARM_DRIVER_I2C Driver_I2C0 = {
+  I2C_GetVersion,
+  I2C_GetCapabilities,
+  I2C0_Initialize,
+  I2C0_Uninitialize,
+  I2C0_PowerControl,
+  I2C0_MasterTransmit,
+  I2C0_MasterReceive,
+  I2C0_SlaveTransmit,
+  I2C0_SlaveReceive,
+  I2C0_GetDataCount,
+  I2C0_Control,
+  I2C0_GetStatus
+};
+#endif
+
+#if (RTE_I2C1)
+/* I2C1 Driver wrapper functions */
+static int32_t I2C1_Initialize (ARM_I2C_SignalEvent_t cb_event) {
+  return (I2Cx_Initialize (cb_event, &I2C1_Resources));
+}
+static int32_t I2C1_Uninitialize (void) {
+  return (I2Cx_Uninitialize (&I2C1_Resources));
+}
+static int32_t I2C1_PowerControl (ARM_POWER_STATE state) {
+  return (I2Cx_PowerControl (state, &I2C1_Resources));
+}
+static int32_t I2C1_MasterTransmit (uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) {
+  return (I2Cx_MasterTransmit (addr, data, num, xfer_pending, &I2C1_Resources));
+}
+static int32_t I2C1_MasterReceive (uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) {
+  return (I2Cx_MasterReceive (addr, data, num, xfer_pending, &I2C1_Resources));
+}
+static int32_t I2C1_SlaveTransmit (const uint8_t *data, uint32_t num) {
+  return (I2Cx_SlaveTransmit (data, num, &I2C1_Resources));
+}
+static int32_t I2C1_SlaveReceive (uint8_t *data, uint32_t num) {
+  return (I2Cx_SlaveReceive (data, num, &I2C1_Resources));
+}
+static int32_t I2C1_GetDataCount (void) {
+  return (I2Cx_GetDataCount (&I2C1_Resources));
+}
+static int32_t I2C1_Control (uint32_t control, uint32_t arg) {
+  return (I2Cx_Control (control, arg, &I2C1_Resources));
+}
+static ARM_I2C_STATUS I2C1_GetStatus (void) {
+  return (I2Cx_GetStatus (&I2C1_Resources));
+}
+void I2C1_IRQHandler (void) {
+  I2Cx_IRQHandler (&I2C1_Resources);
+}
+
+/* I2C1 Driver Control Block */
+ARM_DRIVER_I2C Driver_I2C1 = {
+  I2C_GetVersion,
+  I2C_GetCapabilities,
+  I2C1_Initialize,
+  I2C1_Uninitialize,
+  I2C1_PowerControl,
+  I2C1_MasterTransmit,
+  I2C1_MasterReceive,
+  I2C1_SlaveTransmit,
+  I2C1_SlaveReceive,
+  I2C1_GetDataCount,
+  I2C1_Control,
+  I2C1_GetStatus
+};
+#endif

CMSIS/Pack/Example/CMSIS_Driver/I2C_LPC18xx.h

@@ -0,0 +1,121 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        02. March 2016
+ * $Revision:    V2.1
+ *
+ * Project:      I2C Driver Definitions for NXP LPC18xx
+ * -------------------------------------------------------------------------- */
+
+#ifndef __I2C_LPC18XX_H
+#define __I2C_LPC18XX_H
+
+#include "LPC18xx.h"
+
+#include "Driver_I2C.h"
+
+/* Clock Control Unit register */
+#define CCU_CLK_CFG_RUN     (1 << 0)
+#define CCU_CLK_CFG_AUTO    (1 << 1)
+#define CCU_CLK_STAT_RUN    (1 << 0)
+
+#define CLK_SRC_PLL1        0x09            // I2C clock source
+
+/* I2C reset value for RGU */
+#define RGU_RESET_I2C0      (1 << 16)       // I2C0 reset
+#define RGU_RESET_I2C1      (1 << 17)       // I2C1 reset
+
+/* I2C Driver state flags */
+#define I2C_FLAG_INIT       (1 << 0)        // Driver initialized
+#define I2C_FLAG_POWER      (1 << 1)        // Driver power on
+#define I2C_FLAG_SETUP      (1 << 2)        // Master configured, clock set
+#define I2C_FLAG_SLAVE_RX   (1 << 3)        // Slave receive registered
+
+/* I2C Common Control flags */
+#define I2C_CON_AA          (1 << 2)        // Assert acknowledge bit
+#define I2C_CON_SI          (1 << 3)        // I2C interrupt bit
+#define I2C_CON_STO         (1 << 4)        // STOP bit
+#define I2C_CON_STA         (1 << 5)        // START bit
+#define I2C_CON_I2EN        (1 << 6)        // I2C interface enable
+#define I2C_CON_FLAGS       (I2C_CON_AA | I2C_CON_SI | I2C_CON_STO | I2C_CON_STA)
+
+/* I2C Stalled Status flags */
+#define I2C_MASTER          (1 << 0)        // Master stalled
+#define I2C_SLAVE_TX        (1 << 1)        // Slave stalled on transmit
+#define I2C_SLAVE_RX        (1 << 2)        // Slave stalled on receive
+#define I2C_SLAVE           (I2C_SLAVE_TX | I2C_SLAVE_RX)
+
+/* I2C Status Miscellaneous states */
+#define I2C_STAT_BUSERR      0x00           // I2C Bus error
+
+/* I2C Status Master mode */
+#define I2C_STAT_MA_START    0x08           // START transmitted
+#define I2C_STAT_MA_RSTART   0x10           // Repeated START transmitted
+#define I2C_STAT_MA_SLAW_A   0x18           // SLA+W transmitted, ACK received
+#define I2C_STAT_MA_SLAW_NA  0x20           // SLA+W transmitted, no ACK recvd
+#define I2C_STAT_MA_DT_A     0x28           // Data transmitted, ACK received
+#define I2C_STAT_MA_DT_NA    0x30           // Data transmitted, no ACK recvd
+#define I2C_STAT_MA_ALOST    0x38           // Arbitration lost SLA+W or data
+#define I2C_STAT_MA_SLAR_A   0x40           // SLA+R transmitted, ACK received
+#define I2C_STAT_MA_SLAR_NA  0x48           // SLA+R transmitted, no ACK recvd
+#define I2C_STAT_MA_DR_A     0x50           // Data received, ACK returned
+#define I2C_STAT_MA_DR_NA    0x58           // Data received, no ACK returned
+
+/* I2C Status Slave mode */
+#define I2C_STAT_SL_SLAW_A   0x60           // SLA+W received, ACK returned
+#define I2C_STAT_SL_ALOST_MW 0x68           // Arbitration lost SLA+W in Master mode
+#define I2C_STAT_SL_GCA_A    0x70           // General address recvd, ACK returned
+#define I2C_STAT_SL_ALOST_GC 0x78           // Arbitration lost in General call
+#define I2C_STAT_SL_DR_A     0x80           // Data received, ACK returned
+#define I2C_STAT_SL_DR_NA    0x88           // Data received, no ACK returned
+#define I2C_STAT_SL_DRGC_A   0x90           // Data recvd General call, ACK returned
+#define I2C_STAT_SL_DRGC_NA  0x98           // Data recvd General call, no ACK returned
+#define I2C_STAT_SL_STOP     0xA0           // STOP received while addressed
+#define I2C_STAT_SL_SLAR_A   0xA8           // SLA+R received, ACK returned
+#define I2C_STAT_SL_ALOST_MR 0xB0           // Arbitration lost SLA+R in Master mode
+#define I2C_STAT_SL_DT_A     0xB8           // Data transmitted, ACK received
+#define I2C_STAT_SL_DT_NA    0xC0           // Data transmitted, no ACK received
+#define I2C_STAT_SL_LDT_A    0xC8           // Last data transmitted, ACK received
+
+/* I2C Control Information */
+typedef struct {
+  ARM_I2C_SignalEvent_t cb_event;           // Event callback
+  ARM_I2C_STATUS        status;             // Status flags
+  uint8_t               flags;              // Control and state flags
+  uint8_t               sla_rw;             // Slave address and RW bit
+  bool                  pending;            // Transfer pending (no STOP)
+  uint8_t               stalled;            // Stall mode status flags
+  uint8_t               con_aa;             // I2C slave CON flag
+  int32_t               cnt;                // Master transfer count
+  uint8_t              *data;               // Master data to transfer
+  uint32_t              num;                // Number of bytes to transfer
+  uint8_t              *sdata;              // Slave data to transfer
+  uint32_t              snum;               // Number of bytes to transfer
+} I2C_CTRL;
+
+/* I2C Resource Configuration */
+typedef struct {
+  LPC_I2Cn_Type        *reg;                // I2C register interface
+  IRQn_Type             i2c_ev_irq;         // I2C Event IRQ Number
+  volatile uint32_t    *base_clk_reg;       // Base clock register
+  volatile uint32_t    *pclk_cfg_reg;       // Peripheral clock config register
+  const volatile uint32_t *pclk_stat_reg;   // Peripheral clock status register
+  uint32_t              rgu_val;            // Peripheral reset value
+  I2C_CTRL             *ctrl;               // Run-Time control information
+} const I2C_RESOURCES;
+
+#endif /* __I2C_LPC18XX_H */

CMSIS/Pack/Example/CMSIS_Driver/I2S_LPC18xx.c

@@ -0,0 +1,1728 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        02. March 2016
+ * $Revision:    V1.4
+ *
+ * Driver:       Driver_SAI0, Driver_SAI1
+ * Configured:   via RTE_Device.h configuration file
+ * Project:      SAI (I2S used for SAI) Driver for NXP LPC18xx
+ * --------------------------------------------------------------------------
+ * Use the following configuration settings in the middleware component
+ * to connect to this driver.
+ *
+ *   Configuration Setting                 Value   SAI Interface
+ *   ---------------------                 -----   -------------
+ *   Connect to hardware via Driver_SAI# = 0       use SAI0 (I2S0)
+ *   Connect to hardware via Driver_SAI# = 1       use SAI1 (I2S1)
+ * -------------------------------------------------------------------------- */
+
+/* History:
+ *  Version 1.4
+ *    - Driver update to work with GPDMA_LPC18xx ver.: 1.3
+ *  Version 1.3
+ *    - Corrected PowerControl function for conditional Power full (driver must be initialized)
+ *  Version 1.2
+ *    - PowerControl for Power OFF and Uninitialize functions made unconditional.
+ *    - Corrected status bit-field handling, to prevent race conditions.
+ *  Version 1.1
+ *    - Improved sampling frequency divider calculation
+ *  Version 1.0
+ *    - Initial release
+ */
+#include "GPIO_LPC18xx.h"
+#include "I2S_LPC18xx.h"
+
+#include "RTE_Device.h"
+#include "RTE_Components.h"
+
+#include <math.h>
+
+#if ((!defined(RTE_I2S0)) || (!defined(RTE_I2S1)))
+#error "I2S missing in RTE_Device.h. Please update RTE_Device.h!"
+#endif
+
+#if ((defined(RTE_Drivers_SAI0) && !RTE_I2S0) && (defined(RTE_Drivers_SAI1) && !RTE_I2S1))
+#error "I2S0/1 not configured in RTE_Device.h!"
+#endif
+
+// Definitions
+
+// Frequency tolerance in percentage
+#ifndef I2S_FREQ_TOLERANCE
+#define I2S_FREQ_TOLERANCE   (1.)
+#endif
+
+#define D2F_DOMAIN           (255UL)
+
+#if (RTE_I2S0)
+// FIFO level can have value 1 to 7
+#ifndef I2S0_TX_FIFO_LEVEL
+#define I2S0_TX_FIFO_LEVEL   ( 4U )
+#endif
+
+#ifndef I2S0_RX_FIFO_LEVEL
+#define I2S0_RX_FIFO_LEVEL   ( 4U )
+#endif
+
+#if ((I2S0_TX_FIFO_LEVEL < 1U) || (I2S0_TX_FIFO_LEVEL > 7U))
+#error "Invalid FIFO Level value. FIFO Level can be 1 to 7"
+#endif
+#if ((I2S0_RX_FIFO_LEVEL < 1U) || (I2S0_RX_FIFO_LEVEL > 7U))
+#error "Invalid FIFO Level value. FIFO Level can be 1 to 7"
+#endif
+#endif
+
+#if (RTE_I2S1)
+// FIFO level can have value 1 to 7
+#ifndef I2S1_TX_FIFO_LEVEL
+#define I2S1_TX_FIFO_LEVEL   ( 4U )
+#endif
+
+#ifndef I2S1_RX_FIFO_LEVEL
+#define I2S1_RX_FIFO_LEVEL   ( 4U )
+#endif
+
+#if ((I2S1_TX_FIFO_LEVEL < 1U) || (I2S1_TX_FIFO_LEVEL > 7U))
+#error "Invalid FIFO Level value. FIFO Level can be 1 to 7"
+#endif
+#if ((I2S1_RX_FIFO_LEVEL < 1U) || (I2S1_RX_FIFO_LEVEL > 7U))
+#error "Invalid FIFO Level value. FIFO Level can be 1 to 7"
+#endif
+#endif
+
+
+#define ARM_SAI_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,4)   // driver version
+// Driver Version
+static const ARM_DRIVER_VERSION DriverVersion = {
+  ARM_SAI_API_VERSION,
+  ARM_SAI_DRV_VERSION
+};
+
+// I2S0
+#if (RTE_I2S0)
+static I2S_INFO I2S0_Info = {0};
+
+#if (RTE_I2S0_RX_SCK_PIN_EN == 1U)
+static PIN_ID I2S0_pin_rx_sck  = { RTE_I2S0_RX_SCK_PORT,  RTE_I2S0_RX_SCK_BIT,  RTE_I2S0_RX_SCK_FUNC };
+#endif
+#if (RTE_I2S0_RX_WS_PIN_EN  == 1U)
+static PIN_ID I2S0_pin_rx_ws   = { RTE_I2S0_RX_WS_PORT,   RTE_I2S0_RX_WS_BIT,   RTE_I2S0_RX_WS_FUNC };
+#endif
+#if (RTE_I2S0_RX_SDA_PIN_EN == 1U)
+static PIN_ID I2S0_pin_rx_sda  = { RTE_I2S0_RX_SDA_PORT,  RTE_I2S0_RX_SDA_BIT,  RTE_I2S0_RX_SDA_FUNC };
+#endif
+#if (RTE_I2S0_RX_MCLK_PIN_EN == 1U)
+static PIN_ID I2S0_pin_rx_mclk = { RTE_I2S0_RX_MCLK_PORT, RTE_I2S0_RX_MCLK_BIT, RTE_I2S0_RX_MCLK_FUNC };
+#endif
+#if (RTE_I2S0_TX_SCK_PIN_EN  == 1U)
+static PIN_ID I2S0_pin_tx_sck  = { RTE_I2S0_TX_SCK_PORT,  RTE_I2S0_TX_SCK_BIT,  RTE_I2S0_TX_SCK_FUNC };
+#endif
+#if (RTE_I2S0_TX_WS_PIN_EN   == 1U)
+static PIN_ID I2S0_pin_tx_ws   = { RTE_I2S0_TX_WS_PORT,   RTE_I2S0_TX_WS_BIT,   RTE_I2S0_TX_WS_FUNC };
+#endif
+#if (RTE_I2S0_TX_SDA_PIN_EN  == 1U)
+static PIN_ID I2S0_pin_tx_sda  = { RTE_I2S0_TX_SDA_PORT,  RTE_I2S0_TX_SDA_BIT,  RTE_I2S0_TX_SDA_FUNC };
+#endif
+#if (RTE_I2S0_TX_MCLK_PIN_EN == 1U)
+static PIN_ID I2S0_pin_tx_mclk = { RTE_I2S0_TX_MCLK_PORT, RTE_I2S0_TX_MCLK_BIT, RTE_I2S0_TX_MCLK_FUNC };
+#endif
+
+#if (RTE_I2S0_DMA_TX_EN == 1U)
+void I2S0_GPDMA_Tx_Event (uint32_t event);
+static I2S_DMA I2S0_DMA_Tx = {RTE_I2S0_DMA_TX_CH,
+                              RTE_I2S0_DMA_TX_PERI,
+                              RTE_I2S0_DMA_TX_PERI_SEL,
+                              I2S0_GPDMA_Tx_Event};
+#endif
+#if (RTE_I2S0_DMA_RX_EN == 1U)
+void I2S0_GPDMA_Rx_Event (uint32_t event);
+static I2S_DMA I2S0_DMA_Rx = {RTE_I2S0_DMA_RX_CH,
+                              RTE_I2S0_DMA_RX_PERI,
+                              RTE_I2S0_DMA_RX_PERI_SEL,
+                              I2S0_GPDMA_Rx_Event};
+#endif
+
+static const I2S_RESOURCES I2S0_Resources = {
+  {  // Capabilities
+    1,   ///< supports asynchronous Transmit/Receive
+    1,   ///< supports synchronous Transmit/Receive
+    0,   ///< supports user defined Protocol
+    1,   ///< supports I2S Protocol
+    0,   ///< supports MSB/LSB justified Protocol
+    0,   ///< supports PCM short/long frame Protocol
+    0,   ///< supports AC'97 Protocol
+    1,   ///< supports Mono mode
+    0,   ///< supports Companding
+#if ((RTE_I2S0_TX_MCLK_PIN_EN == 1U) && (RTE_I2S0_RX_MCLK_PIN_EN == 1U))
+    1,   ///< supports MCLK (Master Clock) pin
+#else
+    0,   ///< supports MCLK (Master Clock) pin
+#endif
+    0,   ///< supports Frame error event: \ref ARM_SAI_EVENT_FRAME_ERROR
+  },
+  LPC_I2S0,
+  {  // I2S0 RX Pin configuration
+#if (RTE_I2S0_RX_SCK_PIN_EN  == 1U)
+    &I2S0_pin_rx_sck,
+#else
+    NULL,
+#endif
+#if (RTE_I2S0_RX_WS_PIN_EN   == 1U)
+    &I2S0_pin_rx_ws,
+#else
+    NULL,
+#endif
+#if (RTE_I2S0_RX_SDA_PIN_EN  == 1U)
+    &I2S0_pin_rx_sda,
+#else
+    NULL,
+#endif
+#if (RTE_I2S0_RX_MCLK_PIN_EN == 1U)
+    &I2S0_pin_rx_mclk,
+#else
+    NULL,
+#endif
+  },
+  {  // I2S0 RX Pin configuration
+#if (RTE_I2S0_TX_SCK_PIN_EN  == 1U)
+    &I2S0_pin_tx_sck,
+#else
+    NULL,
+#endif
+#if (RTE_I2S0_TX_WS_PIN_EN   == 1U)
+    &I2S0_pin_tx_ws,
+#else
+    NULL,
+#endif
+#if (RTE_I2S0_TX_SDA_PIN_EN  == 1U)
+    &I2S0_pin_tx_sda,
+#else
+    NULL,
+#endif
+#if (RTE_I2S0_TX_MCLK_PIN_EN == 1U)
+    &I2S0_pin_tx_mclk,
+#else
+    NULL,
+#endif
+  },
+  I2S0_IRQn,
+#if (RTE_I2S0_DMA_TX_EN == 1U)
+  &I2S0_DMA_Tx,
+#else
+  NULL,
+#endif
+#if (RTE_I2S0_DMA_RX_EN == 1U)
+  &I2S0_DMA_Rx,
+#else
+  NULL,
+#endif
+  (uint8_t) I2S0_TX_FIFO_LEVEL,
+  (uint8_t) I2S0_RX_FIFO_LEVEL,
+
+  &I2S0_Info
+};
+#endif
+
+// I2S1
+#if (RTE_I2S1)
+static I2S_INFO I2S1_Info = {0};
+
+#if (RTE_I2S1_RX_SCK_PIN_EN == 1U)
+static PIN_ID I2S1_pin_rx_sck  = { RTE_I2S1_RX_SCK_PORT,  RTE_I2S1_RX_SCK_BIT,  RTE_I2S1_RX_SCK_FUNC };
+#endif
+#if (RTE_I2S1_RX_WS_PIN_EN  == 1U)
+static PIN_ID I2S1_pin_rx_ws   = { RTE_I2S1_RX_WS_PORT,   RTE_I2S1_RX_WS_BIT,   RTE_I2S1_RX_WS_FUNC };
+#endif
+#if (RTE_I2S1_RX_SDA_PIN_EN == 1U)
+static PIN_ID I2S1_pin_rx_sda  = { RTE_I2S1_RX_SDA_PORT,  RTE_I2S1_RX_SDA_BIT,  RTE_I2S1_RX_SDA_FUNC };
+#endif
+#if (RTE_I2S1_RX_MCLK_PIN_EN == 1U)
+static PIN_ID I2S1_pin_rx_mclk = { RTE_I2S1_RX_MCLK_PORT, RTE_I2S1_RX_MCLK_BIT, RTE_I2S1_RX_MCLK_FUNC };
+#endif
+#if (RTE_I2S1_TX_SCK_PIN_EN  == 1U)
+static PIN_ID I2S1_pin_tx_sck  = { RTE_I2S1_TX_SCK_PORT,  RTE_I2S1_TX_SCK_BIT,  RTE_I2S1_TX_SCK_FUNC };
+#endif
+#if (RTE_I2S1_TX_WS_PIN_EN   == 1U)
+static PIN_ID I2S1_pin_tx_ws   = { RTE_I2S1_TX_WS_PORT,   RTE_I2S1_TX_WS_BIT,   RTE_I2S1_TX_WS_FUNC };
+#endif
+#if (RTE_I2S1_TX_SDA_PIN_EN  == 1U)
+static PIN_ID I2S1_pin_tx_sda  = { RTE_I2S1_TX_SDA_PORT,  RTE_I2S1_TX_SDA_BIT,  RTE_I2S1_TX_SDA_FUNC };
+#endif
+#if (RTE_I2S1_TX_MCLK_PIN_EN == 1U)
+static PIN_ID I2S1_pin_tx_mclk = { RTE_I2S1_TX_MCLK_PORT, RTE_I2S1_TX_MCLK_BIT, RTE_I2S1_TX_MCLK_FUNC };
+#endif
+
+#if (RTE_I2S1_DMA_TX_EN == 1U)
+void I2S1_GPDMA_Tx_Event (uint32_t event);
+static I2S_DMA I2S1_DMA_Tx = {RTE_I2S1_DMA_TX_CH,
+                              RTE_I2S1_DMA_TX_PERI,
+                              RTE_I2S1_DMA_TX_PERI_SEL,
+                              I2S1_GPDMA_Tx_Event};
+#endif
+#if (RTE_I2S1_DMA_RX_EN == 1U)
+void I2S1_GPDMA_Rx_Event (uint32_t event);
+static I2S_DMA I2S1_DMA_Rx = {RTE_I2S1_DMA_RX_CH,
+                              RTE_I2S1_DMA_RX_PERI,
+                              RTE_I2S1_DMA_RX_PERI_SEL,
+                              I2S1_GPDMA_Rx_Event};
+#endif
+
+static const I2S_RESOURCES I2S1_Resources = {
+  {  // Capabilities
+    1,   ///< supports asynchronous Transmit/Receive
+    1,   ///< supports synchronous Transmit/Receive
+    0,   ///< supports user defined Protocol
+    1,   ///< supports I2S Protocol
+    0,   ///< supports MSB/LSB justified Protocol
+    0,   ///< supports PCM short/long frame Protocol
+    0,   ///< supports AC'97 Protocol
+    1,   ///< supports Mono mode
+    0,   ///< supports Companding
+#if ((RTE_I2S1_TX_MCLK_PIN_EN == 1U) && (RTE_I2S1_RX_MCLK_PIN_EN == 1U))
+    1,   ///< supports MCLK (Master Clock) pin
+#else
+    0,   ///< supports MCLK (Master Clock) pin
+#endif
+    0,   ///< supports Frame error event: \ref ARM_SAI_EVENT_FRAME_ERROR
+  },
+  LPC_I2S1,
+  {  // I2S1 RX Pin configuration
+#if (RTE_I2S1_RX_SCK_PIN_EN  == 1U)
+    &I2S1_pin_rx_sck,
+#else
+    NULL,
+#endif
+#if (RTE_I2S1_RX_WS_PIN_EN   == 1U)
+    &I2S1_pin_rx_ws,
+#else
+    NULL,
+#endif
+#if (RTE_I2S1_RX_SDA_PIN_EN  == 1U)
+    &I2S1_pin_rx_sda,
+#else
+    NULL,
+#endif
+#if (RTE_I2S1_RX_MCLK_PIN_EN == 1U)
+    &I2S1_pin_rx_mclk,
+#else
+    NULL,
+#endif
+  },
+  {  // I2S1 RX Pin configuration
+#if (RTE_I2S1_TX_SCK_PIN_EN  == 1U)
+    &I2S1_pin_tx_sck,
+#else
+    NULL,
+#endif
+#if (RTE_I2S1_TX_WS_PIN_EN   == 1U)
+    &I2S1_pin_tx_ws,
+#else
+    NULL,
+#endif
+#if (RTE_I2S1_TX_SDA_PIN_EN  == 1U)
+    &I2S1_pin_tx_sda,
+#else
+    NULL,
+#endif
+#if (RTE_I2S1_TX_MCLK_PIN_EN == 1U)
+    &I2S1_pin_tx_mclk,
+#else
+    NULL,
+#endif
+  },
+  I2S1_IRQn,
+#if (RTE_I2S1_DMA_TX_EN == 1U)
+  &I2S1_DMA_Tx,
+#else
+  NULL,
+#endif
+#if (RTE_I2S1_DMA_RX_EN == 1U)
+  &I2S1_DMA_Rx,
+#else
+  NULL,
+#endif
+  (uint8_t) I2S1_TX_FIFO_LEVEL,
+  (uint8_t) I2S1_RX_FIFO_LEVEL,
+
+  &I2S1_Info
+};
+#endif
+
+// Extern Function
+extern uint32_t GetClockFreq (uint32_t clk_src);
+
+/*
+  \fn          static void i2s_dec2fract (double dec, uint8_t* xret, uint8_t* yret)
+  \brief       convert a decimal to a fraction for x/y baudrate factor
+  \details     Use continued fractions to find matching fraction
+               http://en.wikipedia.org/wiki/Generalized_continued_fraction
+  \param[in]   dec      Decimal fraction as floating point
+  \param[in]   xret     pointer to numerator result
+  \param[in]   yret     pointer to denominator result
+*/
+
+static void i2s_dec2fract (double dec, uint8_t* xret, uint8_t* yret) {
+  int_fast64_t a, tmp, idec;
+  int_fast64_t n = 1;
+
+  int_fast64_t f[3] = { 0, 1, 0 };
+  int_fast64_t g[3] = { 1, 0, 0 };
+  int i;
+
+  //Expand float input
+  while (dec != floor(dec)) { n <<= 1; dec *= 2; }
+  idec = dec;
+
+  //continue fraction
+  for (i = 0; i < 64; i++) {
+    a = n ? idec / n : 0;
+    if (i && !a) break;
+    tmp = idec;
+    idec = n; 
+    n = tmp % n;
+    tmp = a;
+    //check denominator
+    if (g[1] * a + g[0] >= D2F_DOMAIN) {
+      tmp = (D2F_DOMAIN - g[0]) / g[1];
+      if (tmp * 2 >= a || g[1] >= D2F_DOMAIN) { i = 65; }
+      else                                    { break;  }
+    }
+    f[2] = tmp * f[1] + f[0]; 
+    f[0] = f[1]; 
+    f[1] = f[2];
+    g[2] = tmp * g[1] + g[0]; 
+    g[0] = g[1]; 
+    g[1] = g[2];
+  }
+  *yret = g[1];
+  *xret = f[1];
+}
+
+/**
+  \fn          ARM_DRIVER_VERSION I2Sx_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+*/
+static ARM_DRIVER_VERSION I2Sx_GetVersion (void) {
+  return (DriverVersion);
+}
+
+/**
+  \fn          ARM_SAI_CAPABILITIES I2Sx_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \param[in]   i2s       Pointer to I2S resources
+  \return      \ref ARM_SAI_CAPABILITIES
+*/
+static ARM_SAI_CAPABILITIES I2S_GetCapabilities (I2S_RESOURCES *i2s) {
+  return (i2s->capabilities);
+}
+
+/**
+  \fn          int32_t I2S_Initialize (ARM_SAI_SignalEvent_t cb_event, I2S_RESOURCES *i2s)
+  \brief       Initialize I2S Interface.
+  \param[in]   cb_event  Pointer to \ref ARM_SAI_SignalEvent
+  \param[in]   i2s       Pointer to I2S resources
+  \return      \ref execution_status
+*/
+static int32_t I2S_Initialize (ARM_SAI_SignalEvent_t cb_event, I2S_RESOURCES *i2s) {
+
+  if (i2s->info->flags & I2S_FLAG_INITIALIZED) {
+    // Driver is already initialized
+    return ARM_DRIVER_OK;
+  }
+
+  // Initialize I2S Run-Time resources
+  i2s->info->cb_event             = cb_event;
+  i2s->info->status.frame_error   = 0U;
+  i2s->info->status.rx_busy       = 0U;
+  i2s->info->status.rx_overflow   = 0U;
+  i2s->info->status.tx_busy       = 0U;
+  i2s->info->status.tx_underflow  = 0U;
+
+  // Configure RX SCK pin
+  if (i2s->rx_pins.sck != NULL) {
+    if (i2s->rx_pins.sck->port == 0x10U) {
+      // CLK1, CLK2 or CLK3
+      SCU_CLK_PinConfigure (i2s->rx_pins.sck->num, SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN |
+                            SCU_PIN_CFG_PULLUP_DIS | SCU_PIN_CFG_MODE(i2s->rx_pins.sck->config_val));
+    } else {
+      SCU_PinConfigure(i2s->rx_pins.sck->port, i2s->rx_pins.sck->num,
+                       SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN |
+                       SCU_PIN_CFG_PULLUP_DIS | SCU_PIN_CFG_MODE(i2s->rx_pins.sck->config_val));
+    }
+  }
+
+  // Configure RX WS pin
+  if (i2s->rx_pins.ws != NULL) {
+    if (i2s->rx_pins.ws->port == 0x10U) {
+      // CLK1, CLK2 or CLK3
+      SCU_CLK_PinConfigure (i2s->rx_pins.ws->num, SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN |
+                            SCU_PIN_CFG_PULLUP_DIS | SCU_PIN_CFG_MODE(i2s->rx_pins.ws->config_val));
+    
+    } else {
+      SCU_PinConfigure(i2s->rx_pins.ws->port, i2s->rx_pins.ws->num,
+                       SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN |
+                       SCU_PIN_CFG_PULLUP_DIS | SCU_PIN_CFG_MODE(i2s->rx_pins.ws->config_val));
+    }
+  }
+
+  // Configure RX SDA pin
+  if (i2s->rx_pins.sda != NULL) {
+    if (i2s->rx_pins.sda->port == 0x10U) {
+      // CLK1, CLK2 or CLK3
+      SCU_CLK_PinConfigure (i2s->rx_pins.sda->num, SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN |
+                            SCU_PIN_CFG_PULLUP_DIS | SCU_PIN_CFG_MODE(i2s->rx_pins.sda->config_val));
+    
+    } else {
+      SCU_PinConfigure(i2s->rx_pins.sda->port, i2s->rx_pins.sda->num,
+                       SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN |
+                       SCU_PIN_CFG_PULLUP_DIS | SCU_PIN_CFG_MODE(i2s->rx_pins.sda->config_val));
+    }
+  }
+
+  // Configure RX MCLK pin
+  if (i2s->rx_pins.mclk != NULL) {
+    if (i2s->rx_pins.mclk->port == 0x10U) {
+      // CLK1, CLK2 or CLK3
+      SCU_CLK_PinConfigure (i2s->rx_pins.mclk->num, SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN |
+                            SCU_PIN_CFG_PULLUP_DIS | SCU_PIN_CFG_MODE(i2s->rx_pins.mclk->config_val));
+    
+    } else {
+      SCU_PinConfigure(i2s->rx_pins.mclk->port, i2s->rx_pins.mclk->num, 
+                       SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN |
+                       SCU_PIN_CFG_PULLUP_DIS | SCU_PIN_CFG_MODE(i2s->rx_pins.mclk->config_val));
+    }
+  }
+
+  // Configure TX SCK pin
+  if (i2s->tx_pins.sck != NULL) {
+    if (i2s->tx_pins.sck->port == 0x10U) {
+      // CLK1, CLK2 or CLK3
+      SCU_CLK_PinConfigure (i2s->tx_pins.sck->num, SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN |
+                            SCU_PIN_CFG_PULLUP_DIS | SCU_PIN_CFG_MODE(i2s->tx_pins.sck->config_val));
+    
+    } else {
+      SCU_PinConfigure(i2s->tx_pins.sck->port, i2s->tx_pins.sck->num,
+                       SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN |
+                       SCU_PIN_CFG_PULLUP_DIS | SCU_PIN_CFG_MODE(i2s->tx_pins.sck->config_val));
+    }
+  }
+
+  // Configure TX WS pin
+  if (i2s->tx_pins.ws != NULL) {
+    if (i2s->tx_pins.ws->port == 0x10U) {
+      // CLK1, CLK2 or CLK3
+      SCU_CLK_PinConfigure (i2s->tx_pins.ws->num, SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN |
+                           SCU_PIN_CFG_PULLUP_DIS | SCU_PIN_CFG_MODE(i2s->tx_pins.ws->config_val));
+    
+    } else {
+      SCU_PinConfigure(i2s->tx_pins.ws->port, i2s->tx_pins.ws->num,
+                       SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN |
+                       SCU_PIN_CFG_PULLUP_DIS | SCU_PIN_CFG_MODE(i2s->tx_pins.ws->config_val));
+    }
+  }
+
+  // Configure TX SDA pin
+  if (i2s->tx_pins.sda != NULL) {
+    if (i2s->tx_pins.sda->port == 0x10U) {
+      // CLK1, CLK2 or CLK3
+      SCU_CLK_PinConfigure (i2s->tx_pins.sda->num, SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN |
+                            SCU_PIN_CFG_PULLUP_DIS | SCU_PIN_CFG_MODE(i2s->tx_pins.sda->config_val));
+    
+    } else {
+      SCU_PinConfigure(i2s->tx_pins.sda->port, i2s->tx_pins.sda->num,
+                       SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN |
+                       SCU_PIN_CFG_PULLUP_DIS | SCU_PIN_CFG_MODE(i2s->tx_pins.sda->config_val));
+    }
+  }
+
+  // Configure TX MCLK pin
+  if (i2s->tx_pins.mclk != NULL) {
+    if (i2s->tx_pins.mclk->port == 0x10U) {
+      // CLK1, CLK2 or CLK3
+      SCU_CLK_PinConfigure (i2s->tx_pins.mclk->num, SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN |
+                            SCU_PIN_CFG_PULLUP_DIS | SCU_PIN_CFG_MODE(i2s->tx_pins.mclk->config_val));
+    
+    } else {
+      SCU_PinConfigure(i2s->tx_pins.mclk->port, i2s->tx_pins.mclk->num,
+                       SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN |
+                       SCU_PIN_CFG_PULLUP_DIS | SCU_PIN_CFG_MODE(i2s->tx_pins.mclk->config_val));
+    }
+  }
+
+ // DMA Initialize
+  if ((i2s->dma_tx != NULL) || (i2s->dma_rx != NULL)) {
+    GPDMA_Initialize ();
+  }
+
+  i2s->info->flags = I2S_FLAG_INITIALIZED;
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t I2S_Uninitialize (I2S_RESOURCES *i2s)
+  \brief       De-initialize I2S Interface.
+  \param[in]   i2s       Pointer to I2S resources
+  \return      \ref execution_status
+*/
+static int32_t I2S_Uninitialize (I2S_RESOURCES *i2s) {
+
+  // Reset RX SCK pin Configuration
+  if (i2s->rx_pins.sck != NULL) {
+    if (i2s->rx_pins.sck->port == 0x10U) {
+      // CLK1, CLK2 or CLK3
+      SCU_CLK_PinConfigure (i2s->rx_pins.sck->num, 0);
+    } else {
+      SCU_PinConfigure(i2s->rx_pins.sck->port, i2s->rx_pins.sck->num, 0);
+    }
+  }
+
+  // Reset RX WS pin Configuration
+  if (i2s->rx_pins.ws != NULL) {
+    if (i2s->rx_pins.ws->port == 0x10U) {
+      // CLK1, CLK2 or CLK3
+      SCU_CLK_PinConfigure (i2s->rx_pins.ws->num, 0);
+    
+    } else {
+      SCU_PinConfigure(i2s->rx_pins.ws->port, i2s->rx_pins.ws->num, 0);
+    }
+  }
+
+  // Reset RX SDA pin Configuration
+  if (i2s->rx_pins.sda != NULL) {
+    if (i2s->rx_pins.sda->port == 0x10U) {
+      // CLK1, CLK2 or CLK3
+      SCU_CLK_PinConfigure (i2s->rx_pins.sda->num, 0);
+    
+    } else {
+      SCU_PinConfigure(i2s->rx_pins.sda->port, i2s->rx_pins.sda->num, 0);
+    }
+  }
+
+  // Reset RX MCLK pin Configuration
+  if (i2s->rx_pins.mclk != NULL) {
+    if (i2s->rx_pins.mclk->port == 0x10U) {
+      // CLK1, CLK2 or CLK3
+      SCU_CLK_PinConfigure (i2s->rx_pins.mclk->num, 0);
+    
+    } else {
+      SCU_PinConfigure(i2s->rx_pins.mclk->port, i2s->rx_pins.mclk->num, 0);
+    }
+  }
+
+  // Reset TX SCK pin Configuration
+  if (i2s->tx_pins.sck != NULL) {
+    if (i2s->tx_pins.sck->port == 0x10U) {
+      // CLK1, CLK2 or CLK3
+      SCU_CLK_PinConfigure (i2s->tx_pins.sck->num, 0);
+    
+    } else {
+      SCU_PinConfigure(i2s->tx_pins.sck->port, i2s->tx_pins.sck->num, 0);
+    }
+  }
+
+  // Reset TX WS pin Configuration
+  if (i2s->tx_pins.ws != NULL) {
+    if (i2s->tx_pins.ws->port == 0x10U) {
+      // CLK1, CLK2 or CLK3
+      SCU_CLK_PinConfigure (i2s->tx_pins.ws->num, 0);
+    
+    } else {
+      SCU_PinConfigure(i2s->tx_pins.ws->port, i2s->tx_pins.ws->num, 0);
+    }
+  }
+
+  // Reset TX SDA pin Configuration
+  if (i2s->tx_pins.sda != NULL) {
+    if (i2s->tx_pins.sda->port == 0x10U) {
+      // CLK1, CLK2 or CLK3
+      SCU_CLK_PinConfigure (i2s->tx_pins.sda->num, 0);
+    
+    } else {
+      SCU_PinConfigure(i2s->tx_pins.sda->port, i2s->tx_pins.sda->num, 0);
+    }
+  }
+
+  // Reset TX MCLK pin Configuration
+  if (i2s->tx_pins.mclk != NULL) {
+    if (i2s->tx_pins.mclk->port == 0x10U) {
+      // CLK1, CLK2 or CLK3
+      SCU_CLK_PinConfigure (i2s->tx_pins.mclk->num, 0);
+    
+    } else {
+      SCU_PinConfigure(i2s->tx_pins.mclk->port, i2s->tx_pins.mclk->num, 0);
+    }
+  }
+
+  // DMA Uninitialize
+  if ((i2s->dma_tx != NULL) || (i2s->dma_rx != NULL)) { GPDMA_Uninitialize (); }
+
+  // Reset I2S status flags
+  i2s->info->flags = 0U;
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t I2S_PowerControl (ARM_POWER_STATE state, I2S_RESOURCES *i2s)
+  \brief       Control I2S Interface Power.
+  \param[in]   state  Power state
+  \param[in]   i2s       Pointer to I2S resources
+  \return      \ref execution_status
+*/
+static int32_t I2S_PowerControl (ARM_POWER_STATE state, I2S_RESOURCES *i2s) {
+
+  switch (state) {
+    case ARM_POWER_OFF:
+      // Disable I2S IRQ
+      NVIC_DisableIRQ(i2s->irq_num);
+
+      if ((i2s->dma_tx == NULL) && (i2s->info->status.tx_busy != 0U)) {
+        // Disable DMA channel
+        GPDMA_ChannelDisable (i2s->dma_tx->channel);
+      }
+      if ((i2s->dma_rx == NULL) && (i2s->info->status.rx_busy != 0U)) {
+        // Disable DMA channel
+        GPDMA_ChannelDisable (i2s->dma_rx->channel);
+      }
+
+      // Reset I2S peripheral
+      LPC_RGU->RESET_CTRL1 = (1U << 20) | (~(LPC_RGU->RESET_ACTIVE_STATUS1));
+      while ((LPC_RGU->RESET_ACTIVE_STATUS1 & (1U << 20)) == 0U);
+
+      // Disable I2S peripheral clock
+      LPC_CCU2->CLK_APLL_CFG &= ~CCU_CLK_CFG_RUN;
+
+      // Clear pending I2S interrupts in NVIC
+      NVIC_ClearPendingIRQ(i2s->irq_num);
+
+      // Clear driver variables
+      i2s->info->status.frame_error   = 0U;
+      i2s->info->status.rx_busy       = 0U;
+      i2s->info->status.rx_overflow   = 0U;
+      i2s->info->status.tx_busy       = 0U;
+      i2s->info->status.tx_underflow  = 0U;
+
+      i2s->info->flags &= ~I2S_FLAG_POWERED;
+      break;
+
+    case ARM_POWER_LOW:
+      return ARM_DRIVER_ERROR_UNSUPPORTED;
+
+    case ARM_POWER_FULL:
+      if ((i2s->info->flags & I2S_FLAG_INITIALIZED) == 0U) { return ARM_DRIVER_ERROR; }
+      if ((i2s->info->flags & I2S_FLAG_POWERED)     != 0U) { return ARM_DRIVER_OK; }
+
+      // Select PLL1 for APB1 clk source and enable autoblock
+      LPC_CGU->BASE_APB1_CLK = (9U << 24) | (1U << 11);
+
+      // Enable I2S peripheral clock
+      LPC_CCU2->CLK_APLL_CFG |=  CCU_CLK_CFG_AUTO | CCU_CLK_CFG_RUN;
+      while ((LPC_CCU2->CLK_APLL_STAT & CCU_CLK_CFG_RUN) == 0U);
+
+      // Reset I2S peripheral
+      LPC_RGU->RESET_CTRL1 = (1U << 20) | (~(LPC_RGU->RESET_ACTIVE_STATUS1));
+      while ((LPC_RGU->RESET_ACTIVE_STATUS1 & (1U << 20)) == 0U);
+
+      // I2S0 and I2S1 RX_SCK and TX_SCK are defined by RXMODE and TXMODE registers
+      LPC_CREG->CREG6 &= ~ (0x0FU << 12);
+
+      // Disable I2S interrupts
+      i2s->reg->IRQ &= ~(I2S_IRQ_RX_IRQ_ENABLE | I2S_IRQ_TX_IRQ_ENABLE);
+
+      // Stop transmitter and receiver
+      i2s->reg->DAO |= (I2S_DAO_DAI_STOP | I2S_DAO_DAI_WS_SEL);
+      i2s->reg->DAI |= (I2S_DAO_DAI_STOP | I2S_DAO_DAI_WS_SEL);
+
+      // Clear driver variables
+      i2s->info->status.frame_error   = 0U;
+      i2s->info->status.rx_busy       = 0U;
+      i2s->info->status.rx_overflow   = 0U;
+      i2s->info->status.tx_busy       = 0U;
+      i2s->info->status.tx_underflow  = 0U;
+
+      i2s->info->rx.residue_cnt       = 0U;
+      i2s->info->rx.residue_num       = 0U;
+      i2s->info->tx.residue_cnt       = 0U;
+      i2s->info->tx.residue_num       = 0U;
+
+      i2s->info->flags = I2S_FLAG_POWERED | I2S_FLAG_INITIALIZED;
+
+      // Clear and Enable SAI IRQ
+      NVIC_ClearPendingIRQ(i2s->irq_num);
+      NVIC_EnableIRQ(i2s->irq_num);
+
+      break;
+
+    default: return ARM_DRIVER_ERROR_UNSUPPORTED;
+  }
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t I2S_Send (const void *data, uint32_t num, I2S_RESOURCES *i2s)
+  \brief       Start sending data to I2S transmitter.
+  \param[in]   data  Pointer to buffer with data to send to I2S transmitter
+  \param[in]   num   Number of data items to send
+  \param[in]   i2s       Pointer to I2S resources
+  \return      \ref execution_status
+*/
+static int32_t I2S_Send (const void *data, uint32_t num, I2S_RESOURCES *i2s) {
+  uint32_t  val;
+  int32_t   stat;
+
+  if ((data == NULL) || (num == 0U)) {
+    // Invalid parameters
+    return ARM_DRIVER_ERROR_PARAMETER;
+  }
+
+  if ((i2s->info->flags & I2S_FLAG_CONFIGURED) == 0U) {
+    // I2S is not configured (mode not selected)
+    return ARM_DRIVER_ERROR;
+  }
+
+  if (i2s->info->status.tx_busy) {
+    // Send is not completed yet
+    return ARM_DRIVER_ERROR_BUSY;
+  }
+
+  // Set Send active flag
+  i2s->info->status.tx_busy = 1U;
+
+  // Clear TX underflow flag
+  i2s->info->status.tx_underflow = 0U;
+
+  // Save transmit buffer info
+  i2s->info->tx.buf = (uint8_t *)data;
+  i2s->info->tx.cnt = 0U;
+
+  // Convert from number of samples to number of bytes
+  num = num * (i2s->info->tx.data_bits / 8U);
+
+  // Only 32-bit value can be written to FIFO. If there is data left from last send,
+  // fill residue buffer to 32bits and write to TX FIFO
+  if (i2s->info->tx.residue_cnt != 0U) {
+    while ((i2s->info->tx.residue_cnt < 4U) && (i2s->info->tx.cnt < num)) {
+      i2s->info->tx.residue_buf[i2s->info->tx.residue_cnt++] = i2s->info->tx.buf[i2s->info->tx.cnt++];
+    }
+
+    if (i2s->info->tx.residue_cnt == 4U) {
+      // Write 32bits to TX FIFO
+      i2s->reg->TXFIFO = *(__packed uint32_t *)(i2s->info->tx.residue_buf);
+
+      // There is no valid data in residue buffer
+      i2s->info->tx.residue_cnt = 0U;
+    }
+  }
+
+  // Disable I2S transmitter interrupt
+  i2s->reg->IRQ &= ~I2S_IRQ_TX_IRQ_ENABLE;
+
+  i2s->info->tx.num = num;
+
+  // DMA mode
+  if (i2s->dma_tx != NULL) {
+    num -= i2s->info->tx.cnt;
+    if (num < 4U) {
+      // Enable I2S transmitter interrupt
+      i2s->reg->IRQ |= I2S_IRQ_TX_IRQ_ENABLE;
+    } else {
+
+      // Configure DMA mux
+      GPDMA_PeripheralSelect (i2s->dma_tx->peripheral, i2s->dma_tx->peripheral_sel);
+
+      // Configure DMA channel
+      stat = GPDMA_ChannelConfigure (i2s->dma_tx->channel,
+                                     (uint32_t)i2s->info->tx.buf + i2s->info->tx.cnt,
+                                     (uint32_t)(&(i2s->reg->TXFIFO)),
+                                     num / 4U,
+                                     GPDMA_CH_CONTROL_SBSIZE(GPDMA_BSIZE_1)                   |
+                                     GPDMA_CH_CONTROL_DBSIZE(GPDMA_BSIZE_1)                   |
+                                     GPDMA_CH_CONTROL_SWIDTH(GPDMA_WIDTH_WORD)                |
+                                     GPDMA_CH_CONTROL_DWIDTH(GPDMA_WIDTH_WORD)                |
+                                     GPDMA_CH_CONTROL_S                                       |
+                                     GPDMA_CH_CONTROL_D                                       |
+                                     GPDMA_CH_CONTROL_I                                       |
+                                     GPDMA_CH_CONTROL_SI,
+                                     GPDMA_CH_CONFIG_DEST_PERI(i2s->dma_tx->peripheral) |
+                                     GPDMA_CH_CONFIG_FLOWCNTRL(GPDMA_TRANSFER_M2P_CTRL_DMA)   |
+                                     GPDMA_CH_CONFIG_IE                                       |
+                                     GPDMA_CH_CONFIG_ITC                                      |
+                                     GPDMA_CH_CONFIG_E,
+                                     i2s->dma_tx->cb_event);
+      if (stat == -1) { return ARM_DRIVER_ERROR; }
+
+      // Set FIFO level and enable TX DMA
+      i2s->reg->DMA1 = (((i2s->tx_fifo_level << I2S_DMA_TX_DEPTH_DMA_POS) & I2S_DMA_TX_DEPTH_DMA_MSK) |
+                         (I2S_DMA_TX_DMA_ENABLE));
+    }
+  // Interrupt mode
+  } else {
+    // Set FIFO level, to trigger TX interrupt
+    val  = i2s->reg->IRQ & ~I2S_IRQ_TX_DEPTH_IRQ_MSK;
+    val |= (i2s->tx_fifo_level << I2S_IRQ_TX_DEPTH_IRQ_POS) & I2S_IRQ_TX_DEPTH_IRQ_MSK;
+    i2s->reg->IRQ = val;
+    // Enable I2S transmitter interrupt
+    i2s->reg->IRQ |= I2S_IRQ_TX_IRQ_ENABLE;
+  }
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t I2S_Receive (void *data, uint32_t num, I2S_RESOURCES *i2s)
+  \brief       Start receiving data from I2S receiver.
+  \param[out]  data  Pointer to buffer for data to receive from I2S receiver
+  \param[in]   num   Number of data items to receive
+  \param[in]   i2s       Pointer to I2S resources
+  \return      \ref execution_status
+*/
+static int32_t I2S_Receive (void *data, uint32_t num, I2S_RESOURCES *i2s) {
+  uint32_t val, offset;
+  int32_t  stat;
+
+  if ((data == NULL) || (num == 0U)) {
+    // Invalid parameters
+    return ARM_DRIVER_ERROR_PARAMETER;
+  }
+
+  if ((i2s->info->flags & I2S_FLAG_CONFIGURED) == 0U) {
+    // I2S is not configured (mode not selected)
+    return ARM_DRIVER_ERROR;
+  }
+
+  if (i2s->info->status.rx_busy) {
+    // Receive is not completed yet
+    return ARM_DRIVER_ERROR_BUSY;
+  }
+
+  // Set Receive active flag
+  i2s->info->status.rx_busy = 1U;
+
+  // Clear RX overflow flag
+  i2s->info->status.rx_overflow = 0U;
+
+  // Save receive buffer info
+  i2s->info->rx.buf = (uint8_t *)data;
+  i2s->info->rx.cnt = 0U;
+
+  // Convert from number of samples to number of bytes
+  num = num * (i2s->info->rx.data_bits / 8U);
+
+  while ((i2s->info->rx.cnt < num) && (i2s->info->rx.residue_cnt < i2s->info->rx.residue_num)) {
+    // RX Data available in residue buffer
+    i2s->info->rx.buf[i2s->info->rx.cnt++] = i2s->info->rx.residue_buf[i2s->info->rx.residue_cnt++];
+
+    if (i2s->info->rx.residue_cnt == i2s->info->rx.residue_num) {
+      // Residue buffer empty
+      i2s->info->rx.residue_cnt    = 0U;
+      i2s->info->rx.residue_num    = 0U;
+    }
+  }
+
+  // Disable I2S receive interrupt
+  i2s->reg->IRQ &= ~I2S_IRQ_RX_IRQ_ENABLE;
+  i2s->info->rx.num = num;
+
+  num -= i2s->info->rx.cnt;
+  // DMA mode
+  if ((i2s->dma_rx != NULL) && (num >= 4U)) {
+    // Set offset in RX Buffer for DMA transfer
+    offset = i2s->info->rx.cnt;
+
+    // Update RX count
+    num /= 4;
+    i2s->info->rx.cnt += num * 4;
+
+    // Configure DMA mux
+    GPDMA_PeripheralSelect (i2s->dma_rx->peripheral, i2s->dma_rx->peripheral_sel);
+
+    // Configure DMA channel
+    stat = GPDMA_ChannelConfigure (i2s->dma_rx->channel,
+                                   (uint32_t)(&(i2s->reg->RXFIFO)),
+                                   (uint32_t)i2s->info->rx.buf + offset,
+                                   num,
+                                   GPDMA_CH_CONTROL_SBSIZE(GPDMA_BSIZE_1)                   |
+                                   GPDMA_CH_CONTROL_DBSIZE(GPDMA_BSIZE_1)                   |
+                                   GPDMA_CH_CONTROL_SWIDTH(GPDMA_WIDTH_WORD)                |
+                                   GPDMA_CH_CONTROL_DWIDTH(GPDMA_WIDTH_WORD)                |
+                                   GPDMA_CH_CONTROL_S                                       |
+                                   GPDMA_CH_CONTROL_D                                       |
+                                   GPDMA_CH_CONTROL_I                                       |
+                                   GPDMA_CH_CONTROL_DI,
+                                   GPDMA_CH_CONFIG_SRC_PERI(i2s->dma_rx->peripheral)        |
+                                   GPDMA_CH_CONFIG_FLOWCNTRL(GPDMA_TRANSFER_P2M_CTRL_DMA)   |
+                                   GPDMA_CH_CONFIG_IE                                       |
+                                   GPDMA_CH_CONFIG_ITC                                      |
+                                   GPDMA_CH_CONFIG_E,
+                                   i2s->dma_rx->cb_event);
+    if (stat == -1) { return ARM_DRIVER_ERROR; }
+
+    // Set FIFO level and enable RX DMA
+    i2s->reg->DMA2 = (((i2s->rx_fifo_level << I2S_DMA_RX_DEPTH_DMA_POS) & I2S_DMA_RX_DEPTH_DMA_MSK) |
+                       (I2S_DMA_RX_DMA_ENABLE));
+
+  // Interrupt mode
+  } else {
+    // Set FIFO level, to trigger RX interrupt
+    val  = i2s->reg->IRQ & ~I2S_IRQ_RX_DEPTH_IRQ_MSK;
+    val |= (i2s->rx_fifo_level << I2S_IRQ_RX_DEPTH_IRQ_POS) & I2S_IRQ_RX_DEPTH_IRQ_MSK;
+    i2s->reg->IRQ = val;
+    // Enable I2S receive interrupt
+    i2s->reg->IRQ |= I2S_IRQ_RX_IRQ_ENABLE;
+  }
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          uint32_t I2S_GetTxCount (I2S_RESOURCES *i2s)
+  \brief       Get transmitted data count.
+  \param[in]   i2s       Pointer to I2S resources
+  \return      number of data items transmitted
+*/
+static uint32_t I2S_GetTxCount (I2S_RESOURCES *i2s) {
+  uint32_t cnt;
+
+  // Convert count in bytes to count of samples
+  cnt = i2s->info->tx.cnt / (i2s->info->tx.data_bits / 8U);
+
+  return (cnt);
+}
+
+/**
+  \fn          uint32_t I2S_GetRxCount (I2S_RESOURCES *i2s)
+  \brief       Get received data count.
+  \param[in]   i2s       Pointer to I2S resources
+  \return      number of data items received
+*/
+static uint32_t I2S_GetRxCount (I2S_RESOURCES *i2s) {
+  uint32_t cnt;
+
+  // Convert count in bytes to count of samples
+  cnt = i2s->info->rx.cnt / (i2s->info->rx.data_bits / 8U);
+
+  return (cnt);
+}
+
+/**
+  \fn          int32_t I2S_Control (uint32_t control, uint32_t arg1, uint32_t arg2, I2S_RESOURCES *i2s)
+  \brief       Control I2S Interface.
+  \param[in]   control  Operation
+  \param[in]   arg1     Argument 1 of operation (optional)
+  \param[in]   arg2     Argument 2 of operation (optional)
+  \param[in]   i2s      Pointer to I2S resources
+  \return      common \ref execution_status and driver specific \ref sai_execution_status
+*/
+static int32_t I2S_Control (uint32_t control, uint32_t arg1, uint32_t arg2, I2S_RESOURCES *i2s) {
+  uint32_t  val, pclk, mclk, master, data_bits;
+  uint32_t  reg_daoi, reg_rate, reg_bitrate, reg_mode;
+  uint8_t   x_best, y_best;
+  double    div_exact, div, delta;
+  I2S_PINS *pins;
+
+  if ((i2s->info->flags & I2S_FLAG_POWERED) == 0U) {
+    // I2S not powered
+    return ARM_DRIVER_ERROR;
+  }
+
+  master      = 0U;
+  data_bits   = 0U;
+
+  reg_daoi    = 0U;
+  reg_rate    = 0U;
+  reg_bitrate = 0U;
+  reg_mode    = 0U;
+
+  switch (control & ARM_SAI_CONTROL_Msk) {
+    case ARM_SAI_CONFIGURE_TX:
+      pins = &(i2s->tx_pins);
+      if (pins->sda == NULL) {
+        // No Tx_SDA pin
+        return ARM_DRIVER_ERROR;
+      }
+      break;
+      
+    case ARM_SAI_CONFIGURE_RX:
+      pins = &(i2s->rx_pins);
+      if (pins->sda == NULL) {
+        // No Rx_SDA pin
+        return ARM_DRIVER_ERROR;
+      }
+      break;
+      
+    case ARM_SAI_CONTROL_TX:
+      if ((arg1 & 1U) == 0U) {
+        i2s->reg->DAO |= (I2S_DAO_DAI_STOP | I2S_DAO_DAI_WS_SEL );
+      } else {
+        if (i2s->info->tx.master) { i2s->reg->DAO &= ~I2S_DAO_DAI_WS_SEL; }
+        else                      { i2s->reg->DAO |=  I2S_DAO_DAI_WS_SEL; }
+
+        // Set Stop
+        i2s->reg->DAO |= I2S_DAO_DAI_STOP;
+
+        if ((i2s->info->status.tx_busy == 0U) || (i2s->dma_tx)) {
+          // Set TX level to 0
+          val  = i2s->reg->IRQ & ~I2S_IRQ_TX_DEPTH_IRQ_MSK;
+          val |= (0U << I2S_IRQ_TX_DEPTH_IRQ_POS) & I2S_IRQ_TX_DEPTH_IRQ_MSK;
+          i2s->reg->IRQ = val;
+
+          if (i2s->info->status.tx_busy == 0U) {
+            // Ready to detect TX underflow
+            i2s->info->tx.num = 0U;
+          }
+        }
+
+        // Clear stop
+        i2s->reg->DAO &= ~I2S_DAO_DAI_STOP;
+
+        // Enable I2S transmit interrupt
+        i2s->reg->IRQ |= I2S_IRQ_TX_IRQ_ENABLE;
+      }
+      // Mute
+      if ((arg1 & 2U) != 0U) { i2s->reg->DAO |=  I2S_DAO_MUTE; }
+      else                   { i2s->reg->DAO &= ~I2S_DAO_MUTE; }
+      return ARM_DRIVER_OK;
+
+    case ARM_SAI_CONTROL_RX:
+      if ((arg1 & 1U) == 0U) {
+        i2s->reg->DAI |= (I2S_DAO_DAI_STOP | I2S_DAO_DAI_WS_SEL);
+      } else {
+        if (i2s->info->rx.master) { i2s->reg->DAI &= ~I2S_DAO_DAI_WS_SEL; }
+        else                      { i2s->reg->DAI |=  I2S_DAO_DAI_WS_SEL; }
+
+        // Set Stop
+        i2s->reg->DAI |= I2S_DAO_DAI_STOP;
+
+        val  = i2s->reg->IRQ & ~I2S_IRQ_RX_DEPTH_IRQ_MSK;
+        if (i2s->info->status.rx_busy == 0U) {
+          // Set FIFO level to full, to detect RX overflow
+          val |= (8U << I2S_IRQ_RX_DEPTH_IRQ_POS) & I2S_IRQ_RX_DEPTH_IRQ_MSK;
+          i2s->reg->IRQ = val;
+
+          // Ready to detect RX overflow
+          i2s->info->rx.num = 0U;
+
+          // Enable I2S receive interrupt
+          i2s->reg->IRQ |= I2S_IRQ_RX_IRQ_ENABLE;
+        } else {
+          if ((i2s->dma_rx != NULL) && ((i2s->reg->DMA2 & I2S_DMA_RX_DMA_ENABLE) == 0U)) {
+            // Set user RX FIFO level
+            val |= (i2s->rx_fifo_level  << I2S_IRQ_RX_DEPTH_IRQ_POS) & I2S_IRQ_RX_DEPTH_IRQ_MSK;
+
+            // Enable I2S receive interrupt
+            i2s->reg->IRQ |= I2S_IRQ_RX_IRQ_ENABLE;
+          }
+        }
+        // Clear stop
+        i2s->reg->DAI &= ~I2S_DAO_DAI_STOP;
+      }
+      return ARM_DRIVER_OK;
+
+    case ARM_SAI_MASK_SLOTS_TX:
+      return ARM_DRIVER_ERROR;
+
+    case ARM_SAI_MASK_SLOTS_RX:
+      return ARM_DRIVER_ERROR;
+
+    case ARM_SAI_ABORT_SEND:
+      // Disable TX interrupt
+      i2s->reg->IRQ &= ~I2S_IRQ_TX_IRQ_ENABLE;
+
+      if (i2s->dma_tx) {
+        if (i2s->info->status.tx_busy != 0U) {
+          // Disable DMA channel
+          GPDMA_ChannelDisable (i2s->dma_tx->channel);
+        }
+      }
+
+      // Reset TX FIFO
+      i2s->reg->DAO |= I2S_DAO_DAI_RESET;
+
+      // Reset counters
+      i2s->info->tx.cnt = 0U;
+      i2s->info->tx.num = 0U;
+      i2s->info->tx.residue_cnt = 0U;
+      i2s->info->tx.residue_num = 0U;
+
+      // Clear reset FIFO bit
+      i2s->reg->DAO &= ~I2S_DAO_DAI_RESET;
+
+      // Clear busy flag
+      i2s->info->status.tx_busy = 0U;
+
+      if ((i2s->reg->DAO & I2S_DAO_DAI_STOP) == 0U) {
+        // Transmitter is enabled
+      
+        // Set FIFO level to full and enable TX interrupt, to detect RX overflow
+        val  = i2s->reg->IRQ & ~I2S_IRQ_RX_DEPTH_IRQ_MSK;
+        val |= (8U << I2S_IRQ_RX_DEPTH_IRQ_POS) & I2S_IRQ_RX_DEPTH_IRQ_MSK;
+        i2s->reg->IRQ = val | I2S_IRQ_TX_IRQ_ENABLE;
+      }
+      return ARM_DRIVER_OK;
+
+    case ARM_SAI_ABORT_RECEIVE:
+      // Disable RX interrupt
+      i2s->reg->IRQ &= ~I2S_IRQ_RX_IRQ_ENABLE;
+
+      if (i2s->dma_rx) {
+        if (i2s->info->status.rx_busy != 0U) {
+          // Disable DMA channel
+          GPDMA_ChannelDisable (i2s->dma_rx->channel);
+        }
+      }
+
+      // Reset RX FIFO
+      i2s->reg->DAI |= I2S_DAO_DAI_RESET;
+
+      // Reset counters
+      i2s->info->rx.cnt = 0U;
+      i2s->info->rx.num = 0U;
+      i2s->info->rx.residue_cnt = 0U;
+      i2s->info->rx.residue_num = 0U;
+
+      // Clear reset FIFO bit
+      i2s->reg->DAI &= ~I2S_DAO_DAI_RESET;
+
+      // Clear busy flag
+      i2s->info->status.rx_busy = 0U;
+
+      if ((i2s->reg->DAI & I2S_DAO_DAI_STOP) == 0U) {
+        // Receiver is enabled
+      
+        // Set FIFO level to full and enable RX interrupt, to detect RX overflow
+        val  = i2s->reg->IRQ & ~I2S_IRQ_RX_DEPTH_IRQ_MSK;
+        val |= (8U << I2S_IRQ_RX_DEPTH_IRQ_POS) & I2S_IRQ_RX_DEPTH_IRQ_MSK;
+        i2s->reg->IRQ = val | I2S_IRQ_RX_IRQ_ENABLE;
+      }
+      return ARM_DRIVER_OK;
+
+    default: return ARM_DRIVER_ERROR;
+  }
+
+  // Mode
+  switch (control & ARM_SAI_MODE_Msk) {
+    case ARM_SAI_MODE_MASTER:
+      master = 1U;
+      break;
+    case ARM_SAI_MODE_SLAVE:
+      break;
+    default: return ARM_DRIVER_ERROR;
+  }
+
+  // Synchronization
+  switch (control & ARM_SAI_SYNCHRONIZATION_Msk) {
+    case ARM_SAI_ASYNCHRONOUS:
+      if ((pins->sck == NULL) || (pins->ws == NULL)) {
+        // Asynchronous mode requires SCK and WS pins
+        return ARM_SAI_ERROR_SYNCHRONIZATION;
+      }
+      break;
+    case ARM_SAI_SYNCHRONOUS:
+      if (master == 1U) {
+        // Only Slave can be synchronous
+        return ARM_SAI_ERROR_SYNCHRONIZATION;
+      }
+      // 4-pin mode: SCK and WS signals are shared between
+      // I2S transmit and receive blocks
+      reg_daoi |= I2S_TX_RX_MODE_4PIN;
+      break;
+    default: return ARM_SAI_ERROR_SYNCHRONIZATION;
+  }
+
+  // Protocol
+  val = (control & ARM_SAI_PROTOCOL_Msk);
+  if (val != ARM_SAI_PROTOCOL_I2S) {
+    // Only I2S protocol is supported
+    return ARM_SAI_ERROR_PROTOCOL;
+  }
+
+  // Data size
+  switch ((control & ARM_SAI_DATA_SIZE_Msk) >> ARM_SAI_DATA_SIZE_Pos) {
+    case 8-1:
+      data_bits = 8;
+      // 8-Data bit, WS_HALFPERIOD = DataBit-1 = 7
+      reg_daoi |= (7U  << I2S_DAO_DAI_WS_HALFPERIOD_POS);
+      break;
+    case 16-1:
+      data_bits = 16;
+      // 16-Data bit, WS_HALFPERIOD = DataBit-1 = 15
+      reg_daoi |= (1U  << I2S_DAO_DAI_WORDWIDTH_POS);
+      reg_daoi |= (15U << I2S_DAO_DAI_WS_HALFPERIOD_POS);
+      break;
+    case 32-1:
+      data_bits = 32;
+      // 32-Data bit, WS_HALFPERIOD = DataBit-1 = 31
+      reg_daoi |= (3U  << I2S_DAO_DAI_WORDWIDTH_POS);
+      reg_daoi |= (31U << I2S_DAO_DAI_WS_HALFPERIOD_POS);
+      break;
+    default: return ARM_SAI_ERROR_DATA_SIZE;
+  }
+
+  // Mono mode
+  if (control & ARM_SAI_MONO_MODE) {
+    reg_daoi |= I2S_DAO_DAI_MONO;
+  }
+
+  // Companding
+  val = control & ARM_SAI_COMPANDING_Msk;
+  if (val != ARM_SAI_COMPANDING_NONE)  { return ARM_SAI_ERROR_COMPANDING; }
+
+  // Clock polarity
+  val = control & ARM_SAI_CLOCK_POLARITY_Msk;
+  if (val != ARM_SAI_CLOCK_POLARITY_0) { return ARM_SAI_ERROR_CLOCK_POLARITY; }
+
+  // Master clock pin
+  switch (control & ARM_SAI_MCLK_PIN_Msk) {
+    case ARM_SAI_MCLK_PIN_INACTIVE:
+      break;
+    case ARM_SAI_MCLK_PIN_OUTPUT:
+      if (pins->mclk == NULL) {
+        // MCLK pin is not available
+        return ARM_SAI_ERROR_MCLK_PIN;
+      }
+      // Generate MCLK on MCLK pin
+      reg_mode |= I2S_TX_RX_MODE_MCENA;
+      break;
+    case ARM_SAI_MCLK_PIN_INPUT:
+      if (pins->mclk == NULL) {
+        // MCLK pin is not available
+        return ARM_SAI_ERROR_MCLK_PIN;
+      }
+      // Audio clock source is MCLK
+      reg_mode |= (1U & I2S_TX_RX_MODE_CLKSEL_MSK);
+      break;
+    default: return ARM_SAI_ERROR_MCLK_PIN;
+  }
+
+  // Frame length
+  val = ((arg1 & ARM_SAI_FRAME_LENGTH_Msk) >> ARM_SAI_FRAME_LENGTH_Pos) + 1;
+  if ((val != 0U) && (val != (data_bits * 2))) { return ARM_SAI_ERROR_FRAME_LENGHT; }
+
+  // Audio Frequency
+  if (master == 1U) {
+    // WS and SCK are generated only by master
+
+    val = ((arg2 & ARM_SAI_MCLK_PRESCALER_Msk) >> ARM_SAI_MCLK_PRESCALER_Pos) + 1;
+
+    reg_bitrate  = val / (data_bits * 2);
+    reg_bitrate--;
+    if (reg_bitrate > I2S_TX_RX_BITRATE_BITRATE_MSK) { return ARM_SAI_ERROR_MCLK_PRESCALER; }
+
+    if ((reg_mode & (1U & I2S_TX_RX_MODE_CLKSEL_MSK)) == 0U) {
+      // Clock source is not MCLK input
+
+      mclk = val * (arg2 & ARM_SAI_AUDIO_FREQ_Msk);
+      pclk = GetClockFreq (9);
+
+      // MCLK = pclk * (x/y) /2  ==> (x/y) = 2*MCLK/pclk
+      div_exact      = (2.0 * mclk) / pclk;
+      i2s_dec2fract (div_exact, &x_best, &y_best);
+      div = (double)(x_best) / (double)(y_best);
+      if (div_exact > div) { delta = div_exact - div;       }
+      else                 { delta = div       - div_exact; }
+      if (((delta * 100U) / div_exact) > I2S_FREQ_TOLERANCE) {return ARM_SAI_ERROR_AUDIO_FREQ; }
+      reg_rate = (y_best << I2S_TX_RX_RATE_Y_DIVIDER_POS) | (x_best << I2S_TX_RX_RATE_X_DIVIDER_POS);
+    }
+  }
+
+  // Save values to registers and globals
+  if ((control & ARM_SAI_CONTROL_Msk) == ARM_SAI_CONFIGURE_TX) {
+    i2s->info->tx.data_bits = data_bits;
+    i2s->info->tx.master    = master;
+    i2s->reg->TXRATE        = reg_rate;
+    i2s->reg->TXBITRATE     = reg_bitrate;
+    i2s->reg->TXMODE        = reg_mode;
+    reg_daoi |= (i2s->reg->DAO & (I2S_DAO_DAI_STOP | I2S_DAO_MUTE | I2S_DAO_DAI_WS_SEL));
+    if (master == 0U) {reg_daoi |= I2S_DAO_DAI_WS_SEL;}
+    i2s->reg->DAO           = reg_daoi;
+  } else {
+    i2s->info->rx.data_bits = data_bits;
+    i2s->info->rx.master    = master;
+    i2s->reg->RXRATE        = reg_rate;
+    i2s->reg->RXBITRATE     = reg_bitrate;
+    i2s->reg->RXMODE        = reg_mode;
+    reg_daoi |= (i2s->reg->DAI & (I2S_DAO_DAI_STOP | I2S_DAO_DAI_WS_SEL));
+    if (master == 0U) {reg_daoi |= I2S_DAO_DAI_WS_SEL;}
+    i2s->reg->DAI           = reg_daoi;
+  }
+
+  i2s->info->flags |= I2S_FLAG_CONFIGURED;
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          ARM_SAI_STATUS I2S_GetStatus (I2S_RESOURCES *i2s)
+  \brief       Get I2S status.
+  \param[in]   i2s       Pointer to I2S resources
+  \return      SAI status \ref ARM_SAI_STATUS
+*/
+static ARM_SAI_STATUS I2S_GetStatus (I2S_RESOURCES *i2s) {
+  ARM_SAI_STATUS status;
+
+  status.frame_error  = i2s->info->status.frame_error;
+  status.rx_busy      = i2s->info->status.rx_busy;
+  status.rx_overflow  = i2s->info->status.rx_overflow;
+  status.tx_busy      = i2s->info->status.tx_busy;
+  status.tx_underflow = i2s->info->status.tx_underflow;
+
+  return status;
+}
+
+/**
+  \fn          void I2S_IRQHandler (I2S_RESOURCES *i2s)
+  \brief       I2S Interrupt handler.
+  \param[in]   i2s     Pointer to I2S resources
+*/
+static void I2S_IRQHandler (I2S_RESOURCES *i2s) {
+  uint32_t  state, val, event, level;
+  uint32_t  i, j;
+  uint8_t  *ptr_buf;
+
+  state = i2s->reg->STATE;
+  event = 0U;
+
+  if (state & I2S_STATE_IRQ) {
+
+    // Fill TX FIFO if needed
+    if (i2s->reg->IRQ & I2S_IRQ_TX_IRQ_ENABLE) {
+
+      // Check for TX underflow
+      if (i2s->info->tx.num == 0U) {
+        // Set TX underflow event and flag
+        i2s->info->status.tx_underflow = 1U;
+        event |= ARM_SAI_EVENT_TX_UNDERFLOW;
+
+        // Disable TX interrupt
+        i2s->reg->IRQ &= ~I2S_IRQ_TX_IRQ_ENABLE;
+      } else {
+        // Get TX level
+        level = ((i2s->reg->STATE & I2S_STATE_TX_LEVEL_MSK) >> I2S_STATE_TX_LEVEL_POS);
+        if (level == 8U) { level = 0U; }
+        else             { level = 7U - level; }
+        
+
+        while (((i2s->info->tx.cnt + 4U) <= i2s->info->tx.num) && (level != 0U)) {
+          // Copy all available 32bit data to FIFO, until FIFO is full
+          ptr_buf = i2s->info->tx.buf + i2s->info->tx.cnt;
+          i2s->reg->TXFIFO = *(__packed uint32_t *)(ptr_buf);
+
+          // Update TX buffer info
+          i2s->info->tx.cnt += 4U;
+          level--;
+        }
+
+        if ((i2s->info->tx.cnt < i2s->info->tx.num) && (level != 0U)) {
+          while (i2s->info->tx.cnt < i2s->info->tx.num) {
+            // Copy remaining data to residue buffer (data < 32bits)
+            i2s->info->tx.residue_buf[i2s->info->tx.residue_cnt++] = i2s->info->tx.buf[i2s->info->tx.cnt++];
+          }
+        }
+
+        if (i2s->info->tx.cnt == i2s->info->tx.num) {
+          i2s->info->status.tx_busy = 0U;
+          i2s->info->tx.num = 0U;
+          event |= ARM_SAI_EVENT_SEND_COMPLETE;
+
+         // Set FIFO level to 0, to detect TX underflow
+          val  = i2s->reg->IRQ & ~I2S_IRQ_TX_DEPTH_IRQ_MSK;
+          i2s->reg->IRQ = val;
+        }
+      }
+    }
+
+    // RX interrupt
+    if (i2s->reg->IRQ & I2S_IRQ_RX_IRQ_ENABLE) {
+
+      // Check for RX overflow
+      if (i2s->info->rx.num == 0U) {
+        // Flush residue buffer
+        i2s->info->rx.residue_cnt = 0U;
+        i2s->info->rx.residue_num = 0U;
+
+        i2s->info->status.rx_overflow = 1U;
+        event |= ARM_SAI_EVENT_RX_OVERFLOW;
+        i2s->reg->IRQ &= ~I2S_IRQ_RX_IRQ_ENABLE;
+      } else {
+        // Get FIFO level
+        level = (i2s->reg->STATE & I2S_STATE_RX_LEVEL_MSK) >> I2S_STATE_RX_LEVEL_POS;
+
+        while (((i2s->info->rx.cnt + 4U) <= i2s->info->rx.num) && (level != 0U)) {
+          // Read FIFO
+          ptr_buf = i2s->info->rx.buf + i2s->info->rx.cnt;
+          *(__packed uint32_t *)(ptr_buf) = i2s->reg->RXFIFO;
+
+          i2s->info->rx.cnt += 4U;
+          level--;
+        }
+
+        if ((i2s->info->rx.cnt < i2s->info->rx.num) && (level != 0U)) {
+          // Read FIFO
+          val = i2s->reg->RXFIFO;
+
+          j = 0U;
+          for (i = 0U; i < 4U; i++) {
+            if ((i2s->info->rx.cnt < i2s->info->rx.num)) {
+              i2s->info->rx.buf[i2s->info->rx.cnt++] = (uint8_t)(val >> j);
+            } else {
+              i2s->info->rx.residue_buf[i2s->info->rx.residue_num++] = (uint8_t)(val >> j);
+            }
+            j += 8U;
+          }
+        }
+
+        if (i2s->info->rx.cnt == i2s->info->rx.num) {
+          i2s->info->status.rx_busy = 0U;
+          i2s->info->rx.num = 0U;
+          event |= ARM_SAI_EVENT_RECEIVE_COMPLETE;
+
+          // Set FIFO level to full, to detect RX overflow
+          val  = i2s->reg->IRQ & ~I2S_IRQ_RX_DEPTH_IRQ_MSK;
+          val |= (8U << I2S_IRQ_RX_DEPTH_IRQ_POS) & I2S_IRQ_RX_DEPTH_IRQ_MSK;
+          i2s->reg->IRQ = val;
+        }
+      }
+    }
+  }
+
+  if ((event != 0U) && (i2s->info->cb_event != NULL)) {
+    i2s->info->cb_event (event);
+  }
+}
+#if (((RTE_I2S0 != 0U) &&(RTE_I2S0_DMA_TX_EN == 1U)) || \
+     ((RTE_I2S1 != 0U) &&(RTE_I2S1_DMA_TX_EN == 1U)))
+static void I2S_GPDMA_Tx_Event (uint32_t event, I2S_RESOURCES *i2s) {
+  uint32_t evt = 0;
+
+  switch (event) {
+    case GPDMA_EVENT_TERMINAL_COUNT_REQUEST:
+      // Update TX buffer info
+      i2s->info->tx.cnt += (i2s->info->tx.num / 4U) * 4U;
+
+      while (i2s->info->tx.cnt < i2s->info->tx.num) {
+        // Copy remaining data to residue buffer (data < 32bits)
+        i2s->info->tx.residue_buf[i2s->info->tx.residue_cnt++] = i2s->info->tx.buf[i2s->info->tx.cnt++];
+      }
+
+      // Clear TX busy flag
+      i2s->info->status.tx_busy = 0U;
+
+      // Clear TX num and enable TX interrupt to detect TX underflow
+      i2s->info->tx.num = 0U;
+      i2s->reg->IRQ |= I2S_IRQ_TX_IRQ_ENABLE;
+
+      // Set Send complete event
+      evt = ARM_SAI_EVENT_SEND_COMPLETE;
+      break;
+    case GPDMA_EVENT_ERROR:
+      break;
+  }
+  if ((evt != 0U) && (i2s->info->cb_event != NULL)) {
+    i2s->info->cb_event (evt);
+  }
+}
+#endif
+
+#if (((RTE_I2S0 != 0U) &&(RTE_I2S0_DMA_RX_EN == 1U)) || \
+     ((RTE_I2S1 != 0U) &&(RTE_I2S1_DMA_RX_EN == 1U)))
+static void I2S_GPDMA_Rx_Event (uint32_t event, I2S_RESOURCES *i2s) {
+  uint32_t evt = 0U;
+  uint32_t val;
+
+  switch (event) {
+    case GPDMA_EVENT_TERMINAL_COUNT_REQUEST:
+      if (i2s->info->rx.cnt == i2s->info->rx.num) {
+        // Clear RX busy flag
+        i2s->info->status.rx_busy = 0U;
+
+        // Set receive complete event
+        evt = ARM_SAI_EVENT_RECEIVE_COMPLETE;
+
+        // Set FIFO level to full, to detect RX overflow
+        val  = i2s->reg->IRQ & ~I2S_IRQ_RX_DEPTH_IRQ_MSK;
+        val |= (8U << I2S_IRQ_RX_DEPTH_IRQ_POS) & I2S_IRQ_RX_DEPTH_IRQ_MSK;
+        i2s->reg->IRQ = val;
+      } else {
+        // Set user defined level, to retrieve remaining requested data
+        val  = i2s->reg->IRQ & ~I2S_IRQ_RX_DEPTH_IRQ_MSK;
+        val |= (i2s->rx_fifo_level << I2S_IRQ_RX_DEPTH_IRQ_POS) & I2S_IRQ_RX_DEPTH_IRQ_MSK;
+        i2s->reg->IRQ = val;
+      
+      }
+
+      i2s->reg->IRQ |= I2S_IRQ_RX_IRQ_ENABLE;
+      break;
+    case GPDMA_EVENT_ERROR:
+      break;
+  }
+  if ((evt != 0U) && (i2s->info->cb_event != NULL)) {
+    i2s->info->cb_event (evt);
+  }
+}
+#endif
+
+
+#if (RTE_I2S0)
+// I2S0 Driver Wrapper functions
+static ARM_SAI_CAPABILITIES I2S0_GetCapabilities (void) {
+  return I2S_GetCapabilities (&I2S0_Resources);
+}
+
+static int32_t I2S0_Initialize (ARM_SAI_SignalEvent_t cb_event) {
+  return I2S_Initialize (cb_event, &I2S0_Resources);
+}
+
+static int32_t I2S0_Uninitialize (void) {
+  return I2S_Uninitialize (&I2S0_Resources);
+}
+
+static int32_t I2S0_PowerControl (ARM_POWER_STATE state) {
+  return I2S_PowerControl (state, &I2S0_Resources);
+}
+
+static int32_t I2S0_Send (const void *data, uint32_t num) {
+  return I2S_Send (data, num, &I2S0_Resources);
+}
+
+static int32_t I2S0_Receive (void *data, uint32_t num) {
+  return I2S_Receive (data, num, &I2S0_Resources);
+}
+
+static uint32_t I2S0_GetTxCount (void) {
+  return I2S_GetTxCount (&I2S0_Resources);
+}
+
+static uint32_t I2S0_GetRxCount (void) {
+  return I2S_GetRxCount (&I2S0_Resources);
+}
+
+static int32_t I2S0_Control (uint32_t control, uint32_t arg1, uint32_t arg2) {
+  return I2S_Control (control, arg1, arg2, &I2S0_Resources);
+}
+
+static ARM_SAI_STATUS I2S0_GetStatus (void) {
+  return I2S_GetStatus (&I2S0_Resources);
+}
+
+void I2S0_IRQHandler (void) {
+  I2S_IRQHandler (&I2S0_Resources);
+}
+
+#if (RTE_I2S0_DMA_TX_EN == 1)
+void I2S0_GPDMA_Tx_Event (uint32_t event) {
+  I2S_GPDMA_Tx_Event (event, &I2S0_Resources);
+}
+#endif
+
+#if (RTE_I2S0_DMA_RX_EN == 1)
+void I2S0_GPDMA_Rx_Event (uint32_t event) {
+  I2S_GPDMA_Rx_Event (event, &I2S0_Resources);
+}
+#endif
+
+// SAI0 Driver Control Block
+ARM_DRIVER_SAI Driver_SAI0 = {
+    I2Sx_GetVersion,
+    I2S0_GetCapabilities,
+    I2S0_Initialize,
+    I2S0_Uninitialize,
+    I2S0_PowerControl,
+    I2S0_Send,
+    I2S0_Receive,
+    I2S0_GetTxCount,
+    I2S0_GetRxCount,
+    I2S0_Control,
+    I2S0_GetStatus
+};
+#endif
+
+#if (RTE_I2S1)
+// I2S1 Driver Wrapper functions
+static ARM_SAI_CAPABILITIES I2S1_GetCapabilities (void) {
+  return I2S_GetCapabilities (&I2S1_Resources);
+}
+
+static int32_t I2S1_Initialize (ARM_SAI_SignalEvent_t cb_event) {
+  return I2S_Initialize (cb_event, &I2S1_Resources);
+}
+
+static int32_t I2S1_Uninitialize (void) {
+  return I2S_Uninitialize (&I2S1_Resources);
+}
+
+static int32_t I2S1_PowerControl (ARM_POWER_STATE state) {
+  return I2S_PowerControl (state, &I2S1_Resources);
+}
+
+static int32_t I2S1_Send (const void *data, uint32_t num) {
+  return I2S_Send (data, num, &I2S1_Resources);
+}
+
+static int32_t I2S1_Receive (void *data, uint32_t num) {
+  return I2S_Receive (data, num, &I2S1_Resources);
+}
+
+static uint32_t I2S1_GetTxCount (void) {
+  return I2S_GetTxCount (&I2S1_Resources);
+}
+
+static uint32_t I2S1_GetRxCount (void) {
+  return I2S_GetRxCount (&I2S1_Resources);
+}
+
+static int32_t I2S1_Control (uint32_t control, uint32_t arg1, uint32_t arg2) {
+  return I2S_Control (control, arg1, arg2, &I2S1_Resources);
+}
+
+static ARM_SAI_STATUS I2S1_GetStatus (void) {
+  return I2S_GetStatus (&I2S1_Resources);
+}
+
+void I2S1_IRQHandler (void) {
+  I2S_IRQHandler (&I2S1_Resources);
+}
+
+#if (RTE_I2S1_DMA_TX_EN == 1)
+void I2S1_GPDMA_Tx_Event (uint32_t event) {
+  I2S_GPDMA_Tx_Event (event, &I2S1_Resources);
+}
+#endif
+
+#if (RTE_I2S1_DMA_RX_EN == 1)
+void I2S1_GPDMA_Rx_Event (uint32_t event) {
+  I2S_GPDMA_Rx_Event (event, &I2S1_Resources);
+}
+#endif
+
+// SAI1 Driver Control Block
+ARM_DRIVER_SAI Driver_SAI1 = {
+    I2Sx_GetVersion,
+    I2S1_GetCapabilities,
+    I2S1_Initialize,
+    I2S1_Uninitialize,
+    I2S1_PowerControl,
+    I2S1_Send,
+    I2S1_Receive,
+    I2S1_GetTxCount,
+    I2S1_GetRxCount,
+    I2S1_Control,
+    I2S1_GetStatus
+};
+#endif

CMSIS/Pack/Example/CMSIS_Driver/I2S_LPC18xx.h

@@ -0,0 +1,161 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        02. March 2016
+ * $Revision:    V1.1
+ *
+ * Project:      I2S Driver Definitions for NXP LPC18xx
+ * -------------------------------------------------------------------------- */
+
+#ifndef __I2S_LPC18XX_H
+#define __I2S_LPC18XX_H
+
+#include "LPC18xx.h"
+#include "Driver_SAI.h"
+
+#include "SCU_LPC18xx.h"
+#include "GPDMA_LPC18xx.h"
+
+// Clock Control Unit register
+#define CCU_CLK_CFG_RUN     (1 << 0)
+#define CCU_CLK_CFG_AUTO    (1 << 1)
+#define CCU_CLK_STAT_RUN    (1 << 0)
+
+// I2S Register interface definitions
+// I2S Digital audio output/input register
+#define I2S_DAO_DAI_WORDWIDTH_POS       (          0U)
+#define I2S_DAO_DAI_WORDWIDTH_MSK       (3U    << I2S_DAO_DAI_WORDWIDTH_POS)
+#define I2S_DAO_DAI_MONO                (1U    <<   2)
+#define I2S_DAO_DAI_STOP                (1U    <<   3)
+#define I2S_DAO_DAI_RESET               (1U    <<   4)
+#define I2S_DAO_DAI_WS_SEL              (1U    <<   5)
+#define I2S_DAO_DAI_WS_HALFPERIOD_POS   (          6U)
+#define I2S_DAO_DAI_WS_HALFPERIOD_MSK   (0x1FF << I2S_DAO_DAI_WS_HALFPERIOD_POS)
+#define I2S_DAO_MUTE                    (1U    <<  15)
+
+// I2S Transmit fifo register
+#define I2S_TXFIFO_I2STXFIFO_MSK        (0xFFFFFFFFU)
+
+// I2S Receive fifo register
+#define I2S_RXFIFO_I2SrXFIFO_MSK        (0xFFFFFFFFU)
+
+// I2S Status feedback register
+#define I2S_STATE_IRQ                   (          1U)
+#define I2S_STATE_DMAREQ1               (1U    <<   1)
+#define I2S_STATE_DMAREQ2               (1U    <<   2)
+#define I2S_STATE_RX_LEVEL_POS          (          8U)
+#define I2S_STATE_RX_LEVEL_MSK          (0xFU  << I2S_STATE_RX_LEVEL_POS)
+#define I2S_STATE_TX_LEVEL_POS          (         16U)
+#define I2S_STATE_TX_LEVEL_MSK          (0xFU  << I2S_STATE_TX_LEVEL_POS)
+
+// I2S DMA configuration register
+#define I2S_DMA_RX_DMA_ENABLE           (          1U)
+#define I2S_DMA_TX_DMA_ENABLE           (1U    <<   1)
+#define I2S_DMA_RX_DEPTH_DMA_POS        (          8U)
+#define I2S_DMA_RX_DEPTH_DMA_MSK        (0xFU  << I2S_DMA_RX_DEPTH_DMA_POS)
+#define I2S_DMA_TX_DEPTH_DMA_POS        (         16U)
+#define I2S_DMA_TX_DEPTH_DMA_MSK        (0xFU  << I2S_DMA_TX_DEPTH_DMA_POS)
+
+// I2S Interrupt request control register
+#define I2S_IRQ_RX_IRQ_ENABLE           (          1U)
+#define I2S_IRQ_TX_IRQ_ENABLE           (1U    <<   1)
+#define I2S_IRQ_RX_DEPTH_IRQ_POS        (          8U)
+#define I2S_IRQ_RX_DEPTH_IRQ_MSK        (0xFU  << I2S_IRQ_RX_DEPTH_IRQ_POS)
+#define I2S_IRQ_TX_DEPTH_IRQ_POS        (         16U)
+#define I2S_IRQ_TX_DEPTH_IRQ_MSK        (0xFU  << I2S_IRQ_TX_DEPTH_IRQ_POS)
+
+// I2S Transmit/Recevice clock rate register
+#define I2S_TX_RX_RATE_Y_DIVIDER_POS    (          0U)
+#define I2S_TX_RX_RATE_Y_DIVIDER_MSK    (0xFFU << I2S_TX_RX_RATE_Y_DIVIDER_POS)
+#define I2S_TX_RX_RATE_X_DIVIDER_POS    (          8U)
+#define I2S_TX_RX_RATE_X_DIVIDER_MSK    (0xFFU << I2S_TX_RX_RATE_X_DIVIDER_POS)
+
+// I2S Transmit/Receive clock bit rate register
+#define I2S_TX_RX_BITRATE_BITRATE_POS   (          0U)
+#define I2S_TX_RX_BITRATE_BITRATE_MSK   (0x3FU << I2S_TX_RX_BITRATE_BITRATE_POS)
+
+// I2S Transmit/Receive mode control register
+#define I2S_TX_RX_MODE_CLKSEL_POS       (          0U)
+#define I2S_TX_RX_MODE_CLKSEL_MSK       (3U    << I2S_TX_RX_MODE_CLKSEL_POS)
+#define I2S_TX_RX_MODE_4PIN             (1U    <<  2U)
+#define I2S_TX_RX_MODE_MCENA            (1U    <<  3U)
+
+// I2S flags
+#define I2S_FLAG_INITIALIZED            (     1U)
+#define I2S_FLAG_POWERED                (1U << 1)
+#define I2S_FLAG_CONFIGURED             (1U << 2)
+
+// I2S Stream Information (Run-Time)
+typedef struct _I2S_STREAM_INFO {
+  uint32_t                num;           // Total number of data to be transmited/received
+  uint8_t                *buf;           // Pointer to data buffer
+  uint32_t                cnt;           // Number of data transmited/receive
+  uint8_t                 data_bits;     // Number of data bits
+  uint8_t                 master;        // Master flag
+  uint8_t                 residue_num;
+  uint8_t                 residue_buf[4];
+  uint8_t                 residue_cnt;
+} I2S_STREAM_INFO;
+
+typedef struct _I2S_STATUS {
+  uint8_t tx_busy;                       // Transmitter busy flag
+  uint8_t rx_busy;                       // Receiver busy flag
+  uint8_t tx_underflow;                  // Transmit data underflow detected (cleared on start of next send operation)
+  uint8_t rx_overflow;                   // Receive data overflow detected (cleared on start of next receive operation)
+  uint8_t frame_error;                   // Sync Frame error detected (cleared on start of next send/receive operation)
+} I2S_STATUS;
+
+// I2S Information (Run-Time)
+typedef struct _I2S_INFO {
+  ARM_SAI_SignalEvent_t   cb_event;      // Event callback
+  I2S_STATUS              status;        // Status flags
+  I2S_STREAM_INFO         tx;            // Transmit information
+  I2S_STREAM_INFO         rx;            // Receive information
+  uint8_t                 flags;         // I2S driver flags
+} I2S_INFO;
+
+// I2S DMA
+typedef const struct _I2S_DMA {
+  uint8_t                 channel;       // DMA Channel
+  uint8_t                 peripheral;    // DMA mux
+  uint8_t                 peripheral_sel;// DMA mux selection
+  GPDMA_SignalEvent_t     cb_event;      // DMA Event callback
+} I2S_DMA;
+
+// I2S Pin Configuration
+typedef const struct _I2S_PINS {
+  PIN_ID                 *sck;           // Clock pin identifier
+  PIN_ID                 *ws;            // Word select pin identifier
+  PIN_ID                 *sda;           // Data pin identifier
+  PIN_ID                 *mclk;          // Master clock pin identifier
+} I2S_PINS;
+
+// I2S Reseurces definitions
+typedef struct {
+  ARM_SAI_CAPABILITIES    capabilities;  // Capabilities
+  LPC_I2Sn_Type          *reg;           // Pointer to I2S peripheral
+  I2S_PINS                rx_pins;       // I2S receive pins configuration
+  I2S_PINS                tx_pins;       // I2S transmit pins configuration
+  IRQn_Type               irq_num;       // I2S IRQ Number
+  I2S_DMA                *dma_tx;        // I2S TX DMA configuration
+  I2S_DMA                *dma_rx;        // I2S RX DMA configuration
+  uint8_t                 tx_fifo_level; // I2S transmit fifo level
+  uint8_t                 rx_fifo_level; // I2S receive fifo level
+  I2S_INFO               *info;          // Run-Time information
+} const I2S_RESOURCES;
+
+#endif // __I2S_LPC18XX_H

CMSIS/Pack/Example/CMSIS_Driver/MCI_LPC18xx.c

@@ -0,0 +1,1011 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        02. March 2016
+ * $Revision:    V2.5
+ *
+ * Driver:       Driver_MCI0
+ * Configured:   via RTE_Device.h configuration file
+ * Project:      MCI Driver for NXP LPC18xx
+ * --------------------------------------------------------------------------
+ * Use the following configuration settings in the middleware component
+ * to connect to this driver.
+ *
+ *   Configuration Setting                 Value
+ *   ---------------------                 -----
+ *   Connect to hardware via Driver_MCI# = 0
+ * -------------------------------------------------------------------------- */
+
+/* Note:
+    For designs that need to support legacy MMC cards in open-drain mode,
+    an external pull-up controlled with a general purpose output and FET
+    will be needed for the CMD line.
+ */
+
+/* History:
+ *  Version 2.5
+ *    - Corrected PowerControl function for conditional Power full (driver must be initialized)
+ *  Version 2.4
+ *    - Updated initialization, uninitialization and power procedures
+ *    - IRQ processing optimized
+ *    - Data timeout handling corrected
+ *    - Include file definitions moved to header file
+ *  Version 2.3
+ *    - FIFO Threshold Watermark Register values corrected
+ *  Version 2.2
+ *    - High speed enabled under capabilities
+ *    - Block size handling added to SetupTransfer function
+ *  Version 2.1
+ *    - DMA descriptor handling corrected
+ *    - Minor functional corrections
+ *    - Card Detect event handling added
+ *    - SD_RST pin handling added
+ *  Version 2.0
+ *    - Updated to CMSIS Driver API V2.01
+ *  Version 1.1
+ *    - Based on API V1.10 (namespace prefix ARM_ added)
+ *  Version 1.0
+ *    - Initial release
+ */
+
+#include "MCI_LPC18xx.h"
+
+#define ARM_MCI_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,5)  /* driver version */
+
+/* External function (system_LPC18xx.c) used to get SDMMC peripheral clock */
+extern uint32_t GetClockFreq (uint32_t clk_src);
+
+static SDMMC_DMA_DESC SDMMC_DMA_Descriptor[SDMMC_DMA_DESC_CNT];
+static MCI_INFO       MCI;
+
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = {
+  ARM_MCI_API_VERSION,
+  ARM_MCI_DRV_VERSION
+};
+
+/* Driver Capabilities */
+static const ARM_MCI_CAPABILITIES DriverCapabilities = {
+  RTE_SD_CD_PIN_EN,                               /* cd_state          */
+  RTE_SD_CD_PIN_EN,                               /* cd_event          */
+  RTE_SD_WP_PIN_EN,                               /* wp_state          */
+  RTE_SD_POW_PIN_EN,                              /* vdd               */
+  0,                                              /* vdd_1v8           */
+  0,                                              /* vccq              */
+  0,                                              /* vccq_1v8          */
+  0,                                              /* vccq_1v2          */
+  RTE_SDMMC_BUS_WIDTH_4,                          /* data_width_4      */
+  RTE_SDMMC_BUS_WIDTH_4 && RTE_SDMMC_BUS_WIDTH_8, /* data_width_8      */
+  0,                                              /* data_width_4_ddr  */
+  0,                                              /* data_width_8_ddr  */
+  1,                                              /* high_speed        */
+  0,                                              /* uhs_signaling     */
+  0,                                              /* uhs_tuning        */
+  0,                                              /* uhs_sdr50         */
+  0,                                              /* uhs_sdr104        */
+  0,                                              /* uhs_ddr50         */
+  0,                                              /* uhs_driver_type_a */
+  0,                                              /* uhs_driver_type_c */
+  0,                                              /* uhs_driver_type_d */
+  1,                                              /* sdio_interrupt    */
+  1,                                              /* read_wait         */
+  0,                                              /* suspend_resume    */
+  0,                                              /* mmc_interrupt     */
+  0,                                              /* mmc_boot          */
+  RTE_SD_RST_PIN_EN,                              /* rst_n             */
+  0,                                              /* ccs               */
+  0                                               /* ccs_timeout       */
+};
+
+/**
+  \fn            void SetupDMADescriptor (MCI_XFER *xfer)
+  \brief         Setup Internal DMA descriptors for data transfer
+*/
+static void SetupDMADescriptor (MCI_XFER *xfer, bool first) {
+  uint32_t i, n;
+
+  for (i = 0; (i < SDMMC_DMA_DESC_CNT) && (xfer->cnt); i++) {
+    n = (xfer->cnt > 7680) ? (7680) : (xfer->cnt);
+
+    SDMMC_DMA_Descriptor[i].CtrlStat = SDMMC_DMA_DESC_OWN;
+    SDMMC_DMA_Descriptor[i].BufSize  = n;
+    SDMMC_DMA_Descriptor[i].BufAddr1 = (uint32_t)xfer->buf;
+    SDMMC_DMA_Descriptor[i].BufAddr2 = (uint32_t)xfer->buf + n;
+
+    xfer->buf += n;
+    xfer->cnt -= n;
+
+    n = (xfer->cnt > 7680) ? (7680) : (xfer->cnt);
+    if (n) {
+      SDMMC_DMA_Descriptor[i].BufSize |= n << 13;
+
+      xfer->buf += n;
+      xfer->cnt -= n;
+    }
+  }
+  if (xfer->cnt == 0) {
+    SDMMC_DMA_Descriptor[i-1].CtrlStat |= SDMMC_DMA_DESC_LD;
+  }
+  if (first) {
+    SDMMC_DMA_Descriptor[0].CtrlStat |= SDMMC_DMA_DESC_FS;
+  }
+  SDMMC_DMA_Descriptor[SDMMC_DMA_DESC_CNT-1].CtrlStat |= SDMMC_DMA_DESC_ER;
+}
+
+
+/**
+  \fn            ARM_DRIVER_VERSION GetVersion (void)
+  \brief         Get driver version.
+  \return        \ref ARM_DRIVER_VERSION
+*/
+static ARM_DRIVER_VERSION GetVersion (void) {
+  return DriverVersion;
+}
+
+
+/**
+  \fn            ARM_MCI_CAPABILITIES GetCapabilities (void)
+  \brief         Get driver capabilities.
+  \return        \ref ARM_MCI_CAPABILITIES
+*/
+static ARM_MCI_CAPABILITIES GetCapabilities (void) {
+  return DriverCapabilities;
+}
+
+
+/**
+  \fn            int32_t Initialize (ARM_MCI_SignalEvent_t cb_event)
+  \brief         Initialize the Memory Card Interface
+  \param[in]     cb_event  Pointer to \ref ARM_MCI_SignalEvent
+  \return        \ref execution_status
+*/
+static int32_t Initialize (ARM_MCI_SignalEvent_t cb_event) {
+
+  if (MCI.flags & MCI_INIT)  { return ARM_DRIVER_OK; }
+
+  /* Enable GPIO register interface clock */
+  LPC_CCU1->CLK_M3_GPIO_CFG |= CCU_CLK_CFG_AUTO | CCU_CLK_CFG_RUN;
+  while (!(LPC_CCU1->CLK_M3_GPIO_STAT & CCU_CLK_STAT_RUN));
+
+  /* Configure SD_CLK, SD_CMD and SD_DAT0 */
+  if (RTE_SD_CLK_PORT == 0x10) {
+    SCU_CLK_PinConfigure (RTE_SD_CLK_PIN, RTE_SD_CLK_FUNC              |
+                                          SCU_PIN_CFG_PULLUP_DIS       |
+                                          SCU_PIN_CFG_INPUT_BUFFER_EN  |
+                                          SCU_PIN_CFG_INPUT_FILTER_DIS);
+  }
+  else {
+    SCU_PinConfigure(RTE_SD_CLK_PORT, RTE_SD_CLK_PIN, RTE_SD_CLK_FUNC              |
+                                                      SCU_PIN_CFG_PULLUP_DIS       |
+                                                      SCU_PIN_CFG_INPUT_BUFFER_EN  |
+                                                      SCU_PIN_CFG_INPUT_FILTER_DIS);
+  }
+                                                    
+  SCU_PinConfigure(RTE_SD_CMD_PORT, RTE_SD_CMD_PIN, RTE_SD_CMD_FUNC              |
+                                                    SCU_PIN_CFG_PULLUP_DIS       |
+                                                    SCU_PIN_CFG_INPUT_BUFFER_EN  |
+                                                    SCU_PIN_CFG_INPUT_FILTER_DIS);
+  SCU_PinConfigure(RTE_SD_DAT0_PORT, RTE_SD_DAT0_PIN, RTE_SD_DAT0_FUNC             |
+                                                      SCU_PIN_CFG_PULLUP_DIS       |
+                                                      SCU_PIN_CFG_INPUT_BUFFER_EN  |
+                                                      SCU_PIN_CFG_INPUT_FILTER_DIS);
+  #if (RTE_SDMMC_BUS_WIDTH_4)
+  /* SD_DAT[3..1] */
+  SCU_PinConfigure(RTE_SD_DAT3_PORT, RTE_SD_DAT3_PIN, RTE_SD_DAT3_FUNC             |
+                                                      SCU_PIN_CFG_PULLUP_DIS       |
+                                                      SCU_PIN_CFG_INPUT_BUFFER_EN  |
+                                                      SCU_PIN_CFG_INPUT_FILTER_DIS);
+  SCU_PinConfigure(RTE_SD_DAT2_PORT, RTE_SD_DAT2_PIN, RTE_SD_DAT2_FUNC             |
+                                                      SCU_PIN_CFG_PULLUP_DIS       |
+                                                      SCU_PIN_CFG_INPUT_BUFFER_EN  |
+                                                      SCU_PIN_CFG_INPUT_FILTER_DIS);
+  SCU_PinConfigure(RTE_SD_DAT1_PORT, RTE_SD_DAT1_PIN, RTE_SD_DAT1_FUNC             |
+                                                      SCU_PIN_CFG_PULLUP_DIS       |
+                                                      SCU_PIN_CFG_INPUT_BUFFER_EN  |
+                                                      SCU_PIN_CFG_INPUT_FILTER_DIS);
+
+    #if (RTE_SDMMC_BUS_WIDTH_8)
+    /* SD_DAT[7..4] */
+    SCU_PinConfigure(RTE_SD_DAT4_PORT, RTE_SD_DAT4_PIN, RTE_SD_DAT4_FUNC             |
+                                                        SCU_PIN_CFG_PULLUP_DIS       |
+                                                        SCU_PIN_CFG_INPUT_BUFFER_EN  |
+                                                        SCU_PIN_CFG_INPUT_FILTER_DIS);
+    SCU_PinConfigure(RTE_SD_DAT5_PORT, RTE_SD_DAT5_PIN, RTE_SD_DAT5_FUNC             |
+                                                        SCU_PIN_CFG_PULLUP_DIS       |
+                                                        SCU_PIN_CFG_INPUT_BUFFER_EN  |
+                                                        SCU_PIN_CFG_INPUT_FILTER_DIS);
+    SCU_PinConfigure(RTE_SD_DAT6_PORT, RTE_SD_DAT6_PIN, RTE_SD_DAT6_FUNC             |
+                                                        SCU_PIN_CFG_PULLUP_DIS       |
+                                                        SCU_PIN_CFG_INPUT_BUFFER_EN  |
+                                                        SCU_PIN_CFG_INPUT_FILTER_DIS);
+    SCU_PinConfigure(RTE_SD_DAT7_PORT, RTE_SD_DAT7_PIN, RTE_SD_DAT7_FUNC             |
+                                                        SCU_PIN_CFG_PULLUP_DIS       |
+                                                        SCU_PIN_CFG_INPUT_BUFFER_EN  |
+                                                        SCU_PIN_CFG_INPUT_FILTER_DIS);
+    #endif /* RTE_SDMMC_BUS_WIDTH_8 */
+
+  #endif /* RTE_SDMMC_BUS_WIDTH_4 */
+
+  #if (RTE_SD_CD_PIN_EN)
+  /* Configure SD_CD (Card Detect) Pin */
+  SCU_PinConfigure(RTE_SD_CD_PORT, RTE_SD_CD_PIN, RTE_SD_CD_FUNC               |
+                                                  SCU_PIN_CFG_PULLUP_DIS       |
+                                                  SCU_PIN_CFG_INPUT_BUFFER_EN  |
+                                                  SCU_PIN_CFG_INPUT_FILTER_DIS);
+  #endif
+
+  #if (RTE_SDIO_WP_PIN_EN)
+  /* Configure SD_WP (Write Protect) Pin */
+  SCU_PinConfigure(RTE_SD_WP_PORT, RTE_SD_WP_PIN, RTE_SD_WP_FUNC               |
+                                                  SCU_PIN_CFG_PULLUP_DIS       |
+                                                  SCU_PIN_CFG_INPUT_BUFFER_EN  |
+                                                  SCU_PIN_CFG_INPUT_FILTER_DIS);
+  #endif
+
+  /* Configure SD_POW Pin */
+  #if (RTE_SD_POW_PIN_EN)
+    SCU_PinConfigure(RTE_SD_POW_PORT, RTE_SD_POW_PIN, RTE_SD_POW_FUNC              |
+                                                      SCU_PIN_CFG_PULLUP_DIS       |
+                                                      SCU_PIN_CFG_INPUT_BUFFER_EN  |
+                                                      SCU_PIN_CFG_INPUT_FILTER_DIS);
+  #endif
+
+  /* Configure SD_RST Pin */
+  #if (RTE_SD_RST_PIN_EN)
+    SCU_PinConfigure(RTE_SD_RST_PORT, RTE_SD_RST_PIN, RTE_SD_RST_FUNC              |
+                                                      SCU_PIN_CFG_PULLUP_DIS       |
+                                                      SCU_PIN_CFG_INPUT_BUFFER_EN  |
+                                                      SCU_PIN_CFG_INPUT_FILTER_DIS);
+  #endif
+
+  /* Connect SDIO base clock to PLL1 */
+  LPC_CGU->BASE_SDIO_CLK  = (0x01 << 11) | (SDIO_CLK_SEL_PLL1 << 24);
+
+  /* Clear control structure */
+  memset (&MCI, 0, sizeof (MCI_INFO));
+
+  MCI.cb_event = cb_event;
+  MCI.flags    = MCI_INIT;
+
+  return ARM_DRIVER_OK;
+}
+
+
+/**
+  \fn            int32_t Uninitialize (void)
+  \brief         De-initialize Memory Card Interface.
+  \return        \ref execution_status
+*/
+static int32_t Uninitialize (void) {
+
+  /* Change SDIO base clock from PLL1 to IRC */
+  LPC_CGU->BASE_SDIO_CLK  = (0x01 << 11) | (0x01 << 24);
+
+  /* Unconfigure SD_CLK and SD_CMD and SD_DAT0 */
+  if (RTE_SD_CLK_PORT == 0x10) {
+    SCU_CLK_PinConfigure (RTE_SD_CLK_PIN, 0);
+  }
+  else {
+    SCU_PinConfigure(RTE_SD_CLK_PORT,  RTE_SD_CLK_PIN,  0);
+  }
+  SCU_PinConfigure(RTE_SD_CMD_PORT,  RTE_SD_CMD_PIN,  0);
+  SCU_PinConfigure(RTE_SD_DAT0_PORT, RTE_SD_DAT0_PIN, 0);
+  
+  #if (RTE_SDMMC_BUS_WIDTH_4)
+  /* SD_DAT[3..1] */
+  SCU_PinConfigure(RTE_SD_DAT1_PORT, RTE_SD_DAT1_PIN, 0);
+  SCU_PinConfigure(RTE_SD_DAT2_PORT, RTE_SD_DAT2_PIN, 0);
+  SCU_PinConfigure(RTE_SD_DAT3_PORT, RTE_SD_DAT3_PIN, 0);
+  
+    #if (RTE_SDMMC_BUS_WIDTH_8)
+    /* SD_DAT[7..4] */
+    SCU_PinConfigure(RTE_SD_DAT4_PORT, RTE_SD_DAT4_PIN, 0);
+    SCU_PinConfigure(RTE_SD_DAT5_PORT, RTE_SD_DAT5_PIN, 0);
+    SCU_PinConfigure(RTE_SD_DAT6_PORT, RTE_SD_DAT6_PIN, 0);
+    SCU_PinConfigure(RTE_SD_DAT7_PORT, RTE_SD_DAT7_PIN, 0);
+    #endif /* RTE_SDMMC_BUS_WIDTH_8 */
+  
+  #endif /* RTE_SDMMC_BUS_WIDTH_4 */
+
+  /* Unconfigure SD_CD (Card Detect) Pin */
+  #if (RTE_SD_CD_PIN_EN)
+    SCU_PinConfigure(RTE_SD_CD_PORT, RTE_SD_CD_PIN, 0);
+  #endif
+
+  /* Unconfigure SD_WP (Write Protect) Pin */
+  #if (RTE_SD_WP_PIN_EN)
+    SCU_PinConfigure(RTE_SD_WP_PORT, RTE_SD_WP_PIN, 0);
+  #endif
+  
+  /* Unconfigure SD_POW Pin */
+  #if (RTE_SD_POW_PIN_EN)
+    SCU_PinConfigure(RTE_SD_POW_PORT, RTE_SD_POW_PIN, 0);
+  #endif
+
+  /* Unconfigure SD_RST Pin */
+  #if (RTE_SD_RST_PIN_EN)
+    SCU_PinConfigure(RTE_SD_RST_PORT, RTE_SD_RST_PIN, 0);
+  #endif
+
+  MCI.flags = 0;
+
+  return ARM_DRIVER_OK;
+}
+
+
+/**
+  \fn            int32_t PowerControl (ARM_POWER_STATE state)
+  \brief         Control Memory Card Interface Power.
+  \param[in]     state   Power state \ref ARM_POWER_STATE
+  \return        \ref execution_status
+*/
+static int32_t PowerControl (ARM_POWER_STATE state) {
+
+  switch (state) {
+    case ARM_POWER_OFF:
+      /* Disable SDIO interrupts */
+      NVIC_DisableIRQ(SDIO_IRQn);
+
+      MCI.flags &= ~MCI_POWER;
+
+      /* Clear status */
+      MCI.status.command_active   = 0U;
+      MCI.status.command_timeout  = 0U;
+      MCI.status.command_error    = 0U;
+      MCI.status.transfer_active  = 0U;
+      MCI.status.transfer_timeout = 0U;
+      MCI.status.transfer_error   = 0U;
+      MCI.status.sdio_interrupt   = 0U;
+      MCI.status.ccs              = 0U;
+
+      /* Reset peripheral */
+      LPC_RGU->RESET_CTRL0 = RGU_RESET_CTRL0_SDIO_RST;
+      __NOP();
+
+      /* Disable SDIO interface clock */
+      LPC_CCU2->CLK_SDIO_CFG    = 0;
+      LPC_CCU1->CLK_M3_SDIO_CFG = 0;
+      break;
+
+    case ARM_POWER_FULL:
+      if ((MCI.flags & MCI_INIT)  == 0U) { return ARM_DRIVER_ERROR; }
+      if ((MCI.flags & MCI_POWER) != 0U) { return ARM_DRIVER_OK; }
+
+      /* Clear response and transfer variables */
+      MCI.response = NULL;
+      MCI.xfer.cnt = NULL;
+
+      /* Enable SDIO clocks */
+      LPC_CCU1->CLK_M3_SDIO_CFG |= CCU_CLK_CFG_AUTO | CCU_CLK_CFG_RUN;
+      while (!(LPC_CCU1->CLK_M3_SDIO_CFG & CCU_CLK_STAT_RUN));
+
+      LPC_CCU2->CLK_SDIO_CFG |= CCU_CLK_CFG_AUTO | CCU_CLK_CFG_RUN;
+      while (!(LPC_CCU2->CLK_SDIO_CFG & CCU_CLK_STAT_RUN));
+
+      /* Reset controller, FIFO and DMA and wait until reset done */
+      LPC_SDMMC->CTRL = SDMMC_CTRL_RESET_BITMASK;
+      while (LPC_SDMMC->CTRL & SDMMC_CTRL_RESET_BITMASK);
+
+      LPC_SDMMC->BMOD = SDMMC_BMOD_SWR;
+      while (LPC_SDMMC->BMOD & SDMMC_BMOD_SWR);
+
+      /* Enable internal DMAC interrupts */
+      LPC_SDMMC->IDINTEN = SDMMC_IDINTEN_FBE |
+                           SDMMC_IDINTEN_DU  ;
+
+      /* Enable SD/MMC peripheral interrupts */
+      LPC_SDMMC->INTMASK = SDMMC_INTMASK_RE    |
+                           #if (RTE_SD_CD_PIN_EN)
+                           SDMMC_INTMASK_CDET  |
+                           #endif
+                           SDMMC_INTMASK_CDONE |
+                           SDMMC_INTMASK_DTO   |
+                           SDMMC_INTMASK_RCRC  |
+                           SDMMC_INTMASK_DCRC  |
+                           SDMMC_INTMASK_RTO   |
+                           SDMMC_INTMASK_DRTO  |
+                           SDMMC_INTMASK_SBE   |
+                           SDMMC_INTMASK_EBE   ;
+      /* Enable Global Interrupt and select internal DMA for data transfer */
+      LPC_SDMMC->CTRL = SDMMC_CTRL_INT_ENABLE | SDMMC_CTRL_USE_INTERNAL_DMAC;
+
+      /* Set FIFO Threshold watermark */
+      LPC_SDMMC->FIFOTH = SDMMC_FIFOTH_DMA_MTS(0)   |
+                          SDMMC_FIFOTH_RX_WMARK(14) |
+                          SDMMC_FIFOTH_TX_WMARK(15) ;
+
+      /* Set Bus Mode */
+      LPC_SDMMC->BMOD = SDMMC_BMOD_DE;
+
+      /* Set descriptor address */
+      LPC_SDMMC->DBADDR = (uint32_t)&SDMMC_DMA_Descriptor;
+
+      /* Enable SDMMC peripheral interrupts in NVIC */
+      NVIC_ClearPendingIRQ(SDIO_IRQn);
+      NVIC_EnableIRQ(SDIO_IRQn);
+
+      MCI.flags |= MCI_POWER;
+      break;
+
+    default:
+      return ARM_DRIVER_ERROR_UNSUPPORTED;
+  }
+  return ARM_DRIVER_OK;
+}
+
+
+
+/**
+  \fn            int32_t CardPower (uint32_t voltage)
+  \brief         Set Memory Card supply voltage.
+  \param[in]     voltage  Memory Card supply voltage
+  \return        \ref execution_status
+*/
+static int32_t CardPower (uint32_t voltage) {
+
+  if (!(MCI.flags & MCI_POWER)) { return ARM_DRIVER_ERROR; }
+
+  #if (RTE_SD_POW_PIN_EN)
+  /* Power on/off is supported */
+  switch (voltage & ARM_MCI_POWER_VDD_Msk) {
+    case ARM_MCI_POWER_VDD_OFF:
+      LPC_SDMMC->PWREN &= ~SDMMC_PWREN_POWER_ENABLE;
+      return ARM_DRIVER_OK;
+
+    case ARM_MCI_POWER_VDD_3V3:
+      LPC_SDMMC->PWREN |=  SDMMC_PWREN_POWER_ENABLE;
+      return ARM_DRIVER_OK;
+    
+    default:
+      break;
+  }
+  #endif
+  return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+
+/**
+  \fn            int32_t ReadCD (void)
+  \brief         Read Card Detect (CD) state.
+  \return        1:card detected, 0:card not detected, or error
+*/
+static int32_t ReadCD (void) {
+
+  if (!(MCI.flags & MCI_POWER)) { return ARM_DRIVER_ERROR; }
+
+  #if (RTE_SD_CD_PIN_EN)
+  return !(LPC_SDMMC->CDETECT & 1);
+  #else
+  return (0);
+  #endif
+}
+
+
+/**
+  \fn            int32_t ReadWP (void)
+  \brief         Read Write Protect (WP) state.
+  \return        1:write protected, 0:not write protected, or error
+*/
+static int32_t ReadWP (void) {
+
+  if (!(MCI.flags & MCI_POWER)) { return ARM_DRIVER_ERROR; }
+
+  #if (RTE_SD_WP_PIN_EN)
+  return (LPC_SDMMC->WRTPRT & 1);
+  #else
+  return (0);
+  #endif
+}
+
+
+/**
+  \fn            int32_t SendCommand (uint32_t  cmd,
+                                      uint32_t  arg,
+                                      uint32_t  flags,
+                                      uint32_t *response)
+  \brief         Send Command to card and get the response.
+  \param[in]     cmd       Memory Card command
+  \param[in]     arg       Command argument
+  \param[in]     flags     Command flags
+  \param[out]    response  Pointer to buffer for response
+  \return        \ref execution_status
+*/
+static int32_t SendCommand (uint32_t cmd, uint32_t arg, uint32_t flags, uint32_t *response) {
+
+  if ((flags & MCI_RESPONSE_EXPECTED_Msk) && (response == NULL)) {
+    return ARM_DRIVER_ERROR_PARAMETER;
+  }
+  if (!(MCI.flags & MCI_SETUP)) {
+    return ARM_DRIVER_ERROR;
+  }
+  if (MCI.status.command_active) {
+    return ARM_DRIVER_ERROR_BUSY;
+  }
+  MCI.status.command_active = 1;
+
+  /* Set command register value */
+  cmd = SDMMC_CMD_CMD_INDEX(cmd) | SDMMC_CMD_WAIT_PRVDATA_COMPLETE | SDMMC_CMD_START_CMD;
+
+  if (flags & ARM_MCI_CARD_INITIALIZE) {
+    cmd |= SDMMC_CMD_SEND_INITIALIZATION;
+  }
+
+  MCI.response = response;
+  MCI.flags   &= ~MCI_RESP_LONG;
+
+  switch (flags & ARM_MCI_RESPONSE_Msk) {
+    case ARM_MCI_RESPONSE_NONE:
+      /* No response expected */
+      MCI.response = NULL;
+      break;
+
+    case ARM_MCI_RESPONSE_SHORT:
+    case ARM_MCI_RESPONSE_SHORT_BUSY:
+      /* Short response expected */
+      cmd |= SDMMC_CMD_RESPONSE_EXPECT;
+      break;
+
+    case ARM_MCI_RESPONSE_LONG:
+      MCI.flags |= MCI_RESP_LONG;
+      /* Long response expected */
+      cmd |= SDMMC_CMD_RESPONSE_EXPECT | SDMMC_CMD_RESPONSE_LENGTH;
+      break;
+  }
+
+  if (flags & ARM_MCI_RESPONSE_CRC) {
+    cmd |= SDMMC_CMD_CHECK_RESPONSE_CRC;
+  }
+
+  if (flags & ARM_MCI_TRANSFER_DATA) {
+    cmd |= SDMMC_CMD_DATA_EXPECTED;
+
+    if (MCI.flags & MCI_WRITE)  { cmd |= SDMMC_CMD_READ_WRITE;    }
+    if (MCI.flags & MCI_STREAM) { cmd |= SDMMC_CMD_TRANSFER_MODE; }
+
+    MCI.status.transfer_active = 1;
+  }
+
+  /* Send the command */
+  LPC_SDMMC->CMDARG = arg;
+  LPC_SDMMC->CMD    = cmd;
+
+  return ARM_DRIVER_OK;
+}
+
+
+/**
+  \fn            int32_t SetupTransfer (uint8_t *data,
+                                        uint32_t block_count,
+                                        uint32_t block_size,
+                                        uint32_t mode)
+  \brief         Setup read or write transfer operation.
+  \param[in,out] data         Pointer to data block(s) to be written or read
+  \param[in]     block_count  Number of blocks
+  \param[in]     block_size   Size of a block in bytes
+  \param[in]     mode         Transfer mode
+  \return        \ref execution_status
+*/
+static int32_t SetupTransfer (uint8_t *data, uint32_t block_count, uint32_t block_size, uint32_t mode) {
+
+  if ((data == NULL) || (block_count == 0) || (block_size == 0)) return ARM_DRIVER_ERROR_PARAMETER;
+
+  if (!(MCI.flags & MCI_SETUP)) {
+    return ARM_DRIVER_ERROR;
+  }
+  if (MCI.status.transfer_active) {
+    return ARM_DRIVER_ERROR_BUSY;
+  }
+
+  /* Remember if write or read transfer requested */
+  if (mode & ARM_MCI_TRANSFER_WRITE) { MCI.flags |=  MCI_WRITE; }
+  else                               { MCI.flags &= ~MCI_WRITE; }
+
+  /* Remember if stream or block transfer mode requested */
+  if (mode & ARM_MCI_TRANSFER_STREAM) { MCI.flags |=  MCI_STREAM; }
+  else                                { MCI.flags &= ~MCI_STREAM; }
+
+  MCI.xfer.buf = data;
+  MCI.xfer.cnt = block_count * block_size;
+
+  LPC_SDMMC->BLKSIZ = block_size;
+  LPC_SDMMC->BYTCNT = MCI.xfer.cnt;
+  
+  SetupDMADescriptor (&MCI.xfer, true);
+
+  return ARM_DRIVER_OK;
+}
+
+
+/**
+  \fn            int32_t AbortTransfer (void)
+  \brief         Abort current read/write data transfer.
+  \return        \ref execution_status
+*/
+static int32_t AbortTransfer (void) {
+
+  if (!(MCI.flags & MCI_SETUP)) { return ARM_DRIVER_ERROR; }
+
+  /* Disable global interrupt */
+  LPC_SDMMC->CTRL &= ~SDMMC_CTRL_INT_ENABLE;
+
+  /* Reset Controller, FIFO and internal DMA */
+  LPC_SDMMC->CTRL |= SDMMC_CTRL_CONTROLLER_RESET |
+                     SDMMC_CTRL_FIFO_RESET       |
+                     SDMMC_CTRL_DMA_RESET        ;
+
+  /* Clear DMA Interrupt flags */
+  LPC_SDMMC->IDSTS = SDMMC_IDSTS_TI  |
+                     SDMMC_IDSTS_RI  |
+                     SDMMC_IDSTS_FBE |
+                     SDMMC_IDSTS_DU  |
+                     SDMMC_IDSTS_CES |
+                     SDMMC_IDSTS_NIS |
+                     SDMMC_IDSTS_AIS ;
+  /* Clear RAW Interrupt flags */
+  LPC_SDMMC->RINTSTS = 0xFFFF;
+
+  MCI.status.command_active  = 0;
+  MCI.status.transfer_active = 0;
+  MCI.status.sdio_interrupt  = 0;
+  MCI.status.ccs             = 0;
+
+  /* Enable global interrupt */
+  LPC_SDMMC->CTRL |= SDMMC_CTRL_INT_ENABLE;
+
+  return ARM_DRIVER_OK;
+}
+
+
+/**
+  \fn            int32_t Control (uint32_t control, uint32_t arg)
+  \brief         Control MCI Interface.
+  \param[in]     control  Operation
+  \param[in]     arg      Argument of operation (optional)
+  \return        \ref execution_status
+*/
+static int32_t Control (uint32_t control, uint32_t arg) {
+  uint32_t div, bps, pclk;
+  
+  if (!(MCI.flags & MCI_POWER)) { return ARM_DRIVER_ERROR; }
+
+  switch (control) {
+    case ARM_MCI_BUS_SPEED:
+      /* Get peripheral clock and calculate clock divider */
+      pclk = GetClockFreq (SDIO_CLK_SEL_PLL1);
+      bps  = arg;
+
+      LPC_SDMMC->CLKENA &= ~SDMMC_CLKENA_CCLK_ENABLE;
+
+      if (bps) {
+        /* bps = pclk / (2 * div) */
+        div   = (pclk + bps - 1) / bps;
+        if (div & 1) { div += 1; }
+
+        bps = pclk / div;
+
+        LPC_SDMMC->CLKSRC  =  SDMMC_CLKSRC_CLK_SOURCE (0);
+        LPC_SDMMC->CLKDIV  =  SDMMC_CLKDIV_CLK_DIVIDER0 (div >> 1);
+        LPC_SDMMC->CLKENA |=  SDMMC_CLKENA_CCLK_ENABLE   |
+                              SDMMC_CLKENA_CCLK_LOW_POWER;
+      }
+
+      /* Send "update clock registers" command and wait until finished */
+      LPC_SDMMC->CMD = SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY |
+                       SDMMC_CMD_WAIT_PRVDATA_COMPLETE       |
+                       SDMMC_CMD_START_CMD                   ;
+
+      while (LPC_SDMMC->CMD & SDMMC_CMD_START_CMD);
+
+      /* Bus speed configured */
+      MCI.flags |= MCI_SETUP;
+
+      return (bps);
+
+    case ARM_MCI_BUS_SPEED_MODE:
+      switch (arg) {
+        case ARM_MCI_BUS_DEFAULT_SPEED:
+          /* Speed mode up to 25/26MHz */
+        case ARM_MCI_BUS_HIGH_SPEED:
+          /* Speed mode up to 50MHz */
+          return ARM_DRIVER_OK;
+
+        default:
+          break;
+      }
+      return ARM_DRIVER_ERROR_UNSUPPORTED;
+
+    case ARM_MCI_BUS_CMD_MODE:
+      /* Implement external pull-up control to support MMC cards in open-drain mode */
+      /* Default mode is push-pull and is configured in Driver_MCI0.Initialize()    */
+      if (arg == ARM_MCI_BUS_CMD_PUSH_PULL) {
+        /* Configure external circuit to work in push-pull mode */
+      }
+      else if (arg == ARM_MCI_BUS_CMD_OPEN_DRAIN) {
+        /* Configure external circuit to work in open-drain mode */
+      }
+      else {
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+      }
+      break;
+
+    case ARM_MCI_BUS_DATA_WIDTH:
+      LPC_SDMMC->CTYPE &= ~(SDMMC_CTYPE_CARD_WIDTH0 | SDMMC_CTYPE_CARD_WIDTH1);
+
+      switch (arg) {
+        case ARM_MCI_BUS_DATA_WIDTH_1:
+          break;
+        case ARM_MCI_BUS_DATA_WIDTH_4:
+          LPC_SDMMC->CTYPE |= SDMMC_CTYPE_CARD_WIDTH0;
+          break;
+        case ARM_MCI_BUS_DATA_WIDTH_8:
+          LPC_SDMMC->CTYPE |= SDMMC_CTYPE_CARD_WIDTH1;
+          break;
+        default:
+          return ARM_DRIVER_ERROR_UNSUPPORTED;
+      }
+      break;
+
+    #if (RTE_SD_RST_PIN_EN)
+    case ARM_MCI_CONTROL_RESET:
+      if (arg) {
+        /* Assert RST_n pin */
+        LPC_SDMMC->RST_N = 0;
+      }
+      else {
+        /* Deassert RST_n pin */
+        LPC_SDMMC->RST_N = 1;
+      }
+      break;
+    #endif
+
+    case ARM_MCI_CONTROL_CLOCK_IDLE:
+      if (arg) {
+        /* Clock generation enabled when idle */
+        LPC_SDMMC->CLKENA &= ~SDMMC_CLKENA_CCLK_LOW_POWER;
+      }
+      else {
+        /* Clock generation disabled when idle */
+        LPC_SDMMC->CLKENA |=  SDMMC_CLKENA_CCLK_LOW_POWER;
+      }
+      /* Send "update clock registers" command and wait until finished */
+      LPC_SDMMC->CMD = SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY |
+                       SDMMC_CMD_WAIT_PRVDATA_COMPLETE       |
+                       SDMMC_CMD_START_CMD                   ;
+
+      while (LPC_SDMMC->CMD & SDMMC_CMD_START_CMD);
+      break;
+
+    case ARM_MCI_DATA_TIMEOUT:
+      if (arg > 0xFFFFFF) {
+        /* Max timeout @ 50MHz is ~335ms: this could cause */
+        /* data timeout issues on slow devices             */
+        arg = 0xFFFFFF;
+      }
+      LPC_SDMMC->TMOUT = (arg << 8) | 0x40;
+      break;
+    
+    case ARM_MCI_MONITOR_SDIO_INTERRUPT:
+      MCI.status.sdio_interrupt = 0;
+      LPC_SDMMC->INTMASK |= SDMMC_INTMASK_SDIO_INT_MASK;
+      break;
+    
+    case ARM_MCI_CONTROL_READ_WAIT:
+      if (arg) {
+        /* Assert read wait */
+        LPC_SDMMC->CTRL |= SDMMC_CTRL_READ_WAIT;
+      }
+      else {
+        /* Clear read wait */
+        LPC_SDMMC->CTRL &= ~SDMMC_CTRL_READ_WAIT;
+      }
+      break;
+    
+    case ARM_MCI_DRIVER_STRENGTH:
+    default: return ARM_DRIVER_ERROR_UNSUPPORTED;
+  }
+
+  return ARM_DRIVER_OK;
+}
+
+
+/**
+  \fn            ARM_MCI_STATUS GetStatus (void)
+  \brief         Get MCI status.
+  \return        MCI status \ref ARM_MCI_STATUS
+*/
+static ARM_MCI_STATUS GetStatus (void) {
+  return MCI.status;
+}
+
+
+/**
+  \fn          SDIO_IRQHandler (void)
+  \brief       Abort current read/write data transfer.
+  \return      \ref MCI_STATUS execution status
+*/
+void SDIO_IRQHandler (void) {
+  uint32_t rintsts, idsts;
+  uint32_t rintclr, idclr;
+  uint32_t event;
+
+  event   = 0;
+  rintclr = 0;
+  idclr   = 0;
+  rintsts = LPC_SDMMC->RINTSTS;
+  idsts   = LPC_SDMMC->IDSTS;
+
+  /* Abnormal Interrupt Summary */
+  if (idsts & SDMMC_IDSTS_DU) {
+    idclr |= SDMMC_IDSTS_DU;
+    /* Descriptor Unavailable Interrupt */
+    if (MCI.xfer.cnt) {
+      SetupDMADescriptor (&MCI.xfer, false);
+
+      LPC_SDMMC->PLDMND = 1;
+    }
+  }
+  if (idsts & SDMMC_IDSTS_FBE) {
+    idclr |= SDMMC_IDSTS_FBE;
+    /* Fatal Bus Error Interrupt */
+    event |= ARM_MCI_EVENT_TRANSFER_ERROR;
+  }
+  #if (RTE_SD_CD_PIN_EN)
+  if (rintsts & SDMMC_RINTSTS_CDET) {
+    rintclr |= SDMMC_RINTSTS_CDET;
+    /* Card detect */
+    if (LPC_SDMMC->CDETECT & 1) {
+      event |= ARM_MCI_EVENT_CARD_REMOVED;
+    }
+    else {
+      event |= ARM_MCI_EVENT_CARD_INSERTED;
+    }
+  }
+  #endif
+  
+  if (rintsts & SDMMC_RINT_ERR_SDIO_Msk) {
+    if (rintsts & SDMMC_RINTSTS_RE) {
+      rintclr |= SDMMC_RINTSTS_RE;
+      /* Response error */
+      event |= ARM_MCI_EVENT_COMMAND_ERROR;
+    }
+    if (rintsts & SDMMC_RINTSTS_RCRC) {
+      rintclr |= SDMMC_RINTSTS_RCRC;
+      /* Response CRC error */
+      event |= ARM_MCI_EVENT_COMMAND_ERROR;
+    }
+    if (rintsts & SDMMC_RINTSTS_DCRC) {
+      rintclr |= SDMMC_RINTSTS_DCRC;
+      /* Data CRC error */
+      event |= ARM_MCI_EVENT_TRANSFER_ERROR;
+    }
+    if (rintsts & SDMMC_RINTSTS_RTO_BAR) {
+      rintclr |= SDMMC_RINTSTS_RTO_BAR;
+      /* Response time-out/Boot Ack Received */
+      event |= ARM_MCI_EVENT_COMMAND_TIMEOUT;
+    }
+    if (rintsts & SDMMC_RINTSTS_DRTO_BDS) {
+      rintclr |= SDMMC_RINTSTS_DRTO_BDS;
+      /* Data read time-out / Boot Data Start              */
+      /* Card has not sent data within the time-out period */
+      event |= ARM_MCI_EVENT_TRANSFER_TIMEOUT;
+    }
+    if (rintsts & SDMMC_RINTSTS_HLE) {
+      rintclr |= SDMMC_RINTSTS_HLE;
+      /* Hardware locked error (command buffer full) */
+      event |= ARM_MCI_EVENT_COMMAND_ERROR;
+    }
+    if (rintsts & SDMMC_RINTSTS_SBE) {
+      rintclr |= SDMMC_RINTSTS_SBE;
+      /* Start-bit error */
+      event |= ARM_MCI_EVENT_TRANSFER_ERROR;
+    }
+    if (rintsts & SDMMC_RINTSTS_EBE) {
+      rintclr |= SDMMC_RINTSTS_EBE;
+      /* End-bit error (read)/write no CRC */
+      event |= ARM_MCI_EVENT_TRANSFER_ERROR;
+    }
+    if (rintsts & SDMMC_RINTSTS_SDIO_INTERRUPT) {
+      rintclr |= SDMMC_RINTSTS_SDIO_INTERRUPT;
+      /* Interrupt from SDIO card */
+      event |= ARM_MCI_EVENT_SDIO_INTERRUPT;
+      MCI.status.sdio_interrupt = 1;
+
+      /* Disable interrupt (must be re-enabled using Control) */
+      LPC_SDMMC->INTMASK &= ~SDMMC_INTMASK_SDIO_INT_MASK;
+    }
+  }
+  if (rintsts & SDMMC_RINTSTS_CDONE) {
+    rintclr |= SDMMC_RINTSTS_CDONE;
+    /* Command done */
+    event |= ARM_MCI_EVENT_COMMAND_COMPLETE;
+
+    if (MCI.response) {
+      /* Read response registers */
+      MCI.response[0] = LPC_SDMMC->RESP0;
+
+      if (MCI.flags & MCI_RESP_LONG) {
+        MCI.response[1] = LPC_SDMMC->RESP1;
+        MCI.response[2] = LPC_SDMMC->RESP2;
+        MCI.response[3] = LPC_SDMMC->RESP3;
+      }
+    }
+  }
+  if (rintsts & SDMMC_RINTSTS_DTO) {
+    rintclr |= SDMMC_RINTSTS_DTO;
+    /* Data transfer over */
+    event |= ARM_MCI_EVENT_TRANSFER_COMPLETE;
+  }
+
+  LPC_SDMMC->RINTSTS = rintclr;
+  LPC_SDMMC->IDSTS   = idclr;
+
+  if (event & MCI_TRANSFER_EVENT_Msk) {
+    MCI.status.transfer_active = 0;
+
+    if (MCI.cb_event) {
+      if (event & ARM_MCI_EVENT_TRANSFER_ERROR) {
+        (MCI.cb_event)(ARM_MCI_EVENT_TRANSFER_ERROR);
+      }
+      else if (event & ARM_MCI_EVENT_TRANSFER_TIMEOUT) {
+        (MCI.cb_event)(ARM_MCI_EVENT_TRANSFER_TIMEOUT);
+      }
+      else {
+        (MCI.cb_event)(ARM_MCI_EVENT_TRANSFER_COMPLETE);
+      }
+    }
+  }
+  
+  if (event & MCI_COMMAND_EVENT_Msk) {
+    MCI.status.command_active = 0;
+
+    if (MCI.cb_event) {
+      if (event & ARM_MCI_EVENT_COMMAND_ERROR) {
+        (MCI.cb_event)(ARM_MCI_EVENT_COMMAND_ERROR);
+      }
+      else if (event & ARM_MCI_EVENT_COMMAND_TIMEOUT) {
+        (MCI.cb_event)(ARM_MCI_EVENT_COMMAND_TIMEOUT);
+      }
+      else {
+        (MCI.cb_event)(ARM_MCI_EVENT_COMMAND_COMPLETE);
+      }
+    }
+  }
+
+  if (event & MCI_CONTROL_EVENT_Msk) {
+    if (MCI.cb_event) {
+      (MCI.cb_event)(event & MCI_CONTROL_EVENT_Msk);
+    }
+  }
+}
+
+/* MCI Driver Control Block */
+ARM_DRIVER_MCI Driver_MCI0 = {
+  GetVersion,
+  GetCapabilities,
+  Initialize,
+  Uninitialize,
+  PowerControl,
+  CardPower,
+  ReadCD,
+  ReadWP,
+  SendCommand,
+  SetupTransfer,
+  AbortTransfer,
+  Control,
+  GetStatus
+};

CMSIS/Pack/Example/CMSIS_Driver/MCI_LPC18xx.h

@@ -0,0 +1,307 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        02. March 2016
+ * $Revision:    V2.4
+ *
+ * Project:      MCI Driver Definitions for NXP LPC18xx
+ * -------------------------------------------------------------------------- */
+
+#ifndef __MCI_LPC18XX_H
+#define __MCI_LPC18XX_H
+
+#include "Driver_MCI.h"
+
+#include "LPC18xx.h"
+#include "SCU_LPC18xx.h"
+#include "MCI_LPC18xx.h"
+
+#include "RTE_Device.h"
+#include "RTE_Components.h"
+
+#include <string.h>
+
+#if (defined(RTE_Drivers_MCI0) && !RTE_SDMMC)
+#error "SDMMC not configured in RTE_Device.h!"
+#endif
+/* Driver flag definitions */
+#define MCI_INIT            (1 << 0)    /* MCI initialized         */
+#define MCI_POWER           (1 << 1)    /* MCI powered on          */
+#define MCI_SETUP           (1 << 2)    /* MCI configured          */
+#define MCI_WRITE           (1 << 3)    /* Write transfer          */
+#define MCI_STREAM          (1 << 4)    /* Stream stransfer        */
+#define MCI_RESP_LONG       (1 << 5)    /* Long response expected  */
+
+
+#define MCI_RESPONSE_EXPECTED_Msk (ARM_MCI_RESPONSE_SHORT      | \
+                                   ARM_MCI_RESPONSE_SHORT_BUSY | \
+                                   ARM_MCI_RESPONSE_LONG)
+
+#define MCI_TRANSFER_EVENT_Msk   (ARM_MCI_EVENT_TRANSFER_ERROR   | \
+                                  ARM_MCI_EVENT_TRANSFER_TIMEOUT | \
+                                  ARM_MCI_EVENT_TRANSFER_COMPLETE)
+
+#define MCI_COMMAND_EVENT_Msk    (ARM_MCI_EVENT_COMMAND_ERROR   | \
+                                  ARM_MCI_EVENT_COMMAND_TIMEOUT | \
+                                  ARM_MCI_EVENT_COMMAND_COMPLETE)
+
+#define MCI_CONTROL_EVENT_Msk    (ARM_MCI_EVENT_CARD_INSERTED | \
+                                  ARM_MCI_EVENT_CARD_REMOVED  | \
+                                  ARM_MCI_EVENT_SDIO_INTERRUPT)
+
+#define SDMMC_CTRL_RESET_BITMASK (SDMMC_CTRL_CONTROLLER_RESET | \
+                                  SDMMC_CTRL_FIFO_RESET       | \
+                                  SDMMC_CTRL_DMA_RESET)
+
+#define SDMMC_RINT_ERR_SDIO_Msk  (SDMMC_RINTSTS_RE            | \
+                                  SDMMC_RINTSTS_RCRC          | \
+                                  SDMMC_RINTSTS_DCRC          | \
+                                  SDMMC_RINTSTS_RTO_BAR       | \
+                                  SDMMC_RINTSTS_DRTO_BDS      | \
+                                  SDMMC_RINTSTS_HLE           | \
+                                  SDMMC_RINTSTS_SBE           | \
+                                  SDMMC_RINTSTS_EBE           | \
+                                  SDMMC_RINTSTS_SDIO_INTERRUPT)
+
+/* Clock Control Unit register bits */
+#define CCU_CLK_CFG_RUN   (1 << 0)
+#define CCU_CLK_CFG_AUTO  (1 << 1)
+#define CCU_CLK_STAT_RUN  (1 << 0)
+
+/* Reset Generation Unit register bits */
+#define RGU_RESET_CTRL0_SDIO_RST (1 << 20)
+
+/* CGU BASE_SDIO_CLK CLK_SEL definition */
+#define SDIO_CLK_SEL_PLL1 0x09
+
+/* Number of DMA descriptors */
+#define SDMMC_DMA_DESC_CNT 4
+
+/* DMA descriptor bit definitions */
+#define SDMMC_DMA_DESC_DIC (1U <<  1)   /* Disable Interrupt on Completion    */
+#define SDMMC_DMA_DESC_LD  (1U <<  2)   /* Last Descriptor                    */
+#define SDMMC_DMA_DESC_FS  (1U <<  3)   /* First Descriptor                   */
+#define SDMMC_DMA_DESC_CH  (1U <<  4)   /* Second Address Chained             */
+#define SDMMC_DMA_DESC_ER  (1U <<  5)   /* End of Ring                        */
+#define SDMMC_DMA_DESC_CES (1U << 30)   /* Card Error Summary                 */
+#define SDMMC_DMA_DESC_OWN (1U << 31)   /* Descriptor Ownership               */
+
+/* SDMMC Internal DMA Descriptor Definition */
+typedef struct {
+  uint32_t CtrlStat;                    /* Control and Status Information     */
+  uint32_t BufSize;                     /* Buffer Size                        */
+  uint32_t BufAddr1;                    /* Address pointer to data buffer 1   */
+  uint32_t BufAddr2;                    /* Address pointer to data buffer 2   */
+} SDMMC_DMA_DESC;
+
+/* MCI Transfer Information Definition */
+typedef struct _MCI_XFER {
+  uint8_t *buf;                         /* Data buffer                        */
+  uint32_t cnt;                         /* Data bytes to transfer             */
+} MCI_XFER;
+
+/* MCI Driver State Definition */
+typedef struct _MCI_INFO {
+  ARM_MCI_SignalEvent_t cb_event;       /* Driver event callback function     */
+  ARM_MCI_STATUS        status;         /* Driver status                      */
+  uint32_t             *response;       /* Pointer to response buffer         */
+  MCI_XFER              xfer;           /* Data transfer description          */
+  uint8_t               flags;          /* Driver state flags                 */
+} MCI_INFO;
+
+/* SDMMC CTRL Register Bitmask Definitions */
+#define SDMMC_CTRL_CONTROLLER_RESET               (1U <<  0)
+#define SDMMC_CTRL_FIFO_RESET                     (1U <<  1)
+#define SDMMC_CTRL_DMA_RESET                      (1U <<  2)
+#define SDMMC_CTRL_INT_ENABLE                     (1U <<  4)
+#define SDMMC_CTRL_READ_WAIT                      (1U <<  6)
+#define SDMMC_CTRL_SEND_IRQ_RESPONSE              (1U <<  7)
+#define SDMMC_CTRL_ABORT_READ_DATA                (1U <<  8)
+#define SDMMC_CTRL_SEND_CCSD                      (1U <<  9)
+#define SDMMC_CTRL_SEND_AUTO_STOP_CCSD            (1U << 10)
+#define SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS  (1U << 11)
+#define SDMMC_CTRL_USE_INTERNAL_DMAC              (1U << 25)
+
+/* SDMMC PWREN Register Bitmask Definitions */
+#define SDMMC_PWREN_POWER_ENABLE                  (1U <<  0)
+
+/* SDMMC CLKDIV Register Bitmask Definitions */
+#define SDMMC_CLKDIV_CLK_DIVIDER0(x)    (((x) & 0xFF) <<  0)
+#define SDMMC_CLKDIV_CLK_DIVIDER1(x)    (((x) & 0xFF) <<  8)
+#define SDMMC_CLKDIV_CLK_DIVIDER2(x)    (((x) & 0xFF) << 16)
+#define SDMMC_CLKDIV_CLK_DIVIDER3(x)    (((x) & 0xFF) << 24)
+
+/* SDMMC CLKSRC Register Bitmask Definitions */
+#define SDMMC_CLKSRC_CLK_SOURCE(x)      (((x) & 0x03) <<  0)
+
+/* SDMMC CLKENA Register Bitmask Definitions */
+#define SDMMC_CLKENA_CCLK_ENABLE                  (1U <<  0)
+#define SDMMC_CLKENA_CCLK_LOW_POWER               (1U << 16)
+
+/* SDMMC TMOUT Register Bitmask Definitions */
+#define SDMMC_TMOUT_RESPONSE_TIMEOUT(x) (((x) & 0xFF) <<  0)
+#define SDMMC_TMOUT_DATA_TIMEOUT(x) (((x) & 0xFFFFFF) <<  8)
+
+/* SDMMC CTYPE Register Bitmask Definitions */
+#define SDMMC_CTYPE_CARD_WIDTH0                   (1U <<  0)
+#define SDMMC_CTYPE_CARD_WIDTH1                   (1U << 16)
+
+/* SDMMC BLKSIZ Register Bitmask Definitions */
+#define SDMMC_BLKSIZ_BLOCK_SIZE(x)    (((x) & 0xFFFF) <<  0)
+
+/* SDMMC BYTCNT Register Bitmask Definitions */
+#define SDMMC_BYTCNT_BYTE_COUNT(x)               ((x) <<  0)
+
+/* SDMMC INTMASK Register Bitmask Definitions */
+#define SDMMC_INTMASK_CDET                        (1U <<  0)
+#define SDMMC_INTMASK_RE                          (1U <<  1)
+#define SDMMC_INTMASK_CDONE                       (1U <<  2)
+#define SDMMC_INTMASK_DTO                         (1U <<  3)
+#define SDMMC_INTMASK_TXDR                        (1U <<  4)
+#define SDMMC_INTMASK_RXDR                        (1U <<  5)
+#define SDMMC_INTMASK_RCRC                        (1U <<  6)
+#define SDMMC_INTMASK_DCRC                        (1U <<  7)
+#define SDMMC_INTMASK_RTO                         (1U <<  8)
+#define SDMMC_INTMASK_DRTO                        (1U <<  9)
+#define SDMMC_INTMASK_HTO                         (1U << 10)
+#define SDMMC_INTMASK_FRUN                        (1U << 11)
+#define SDMMC_INTMASK_HLE                         (1U << 12)
+#define SDMMC_INTMASK_SBE                         (1U << 13)
+#define SDMMC_INTMASK_ACD                         (1U << 14)
+#define SDMMC_INTMASK_EBE                         (1U << 15)
+#define SDMMC_INTMASK_SDIO_INT_MASK               (1U << 16)
+
+/* SDMMC CMDARG Register Bitmask Definitions */
+#define SDMMC_CMDARG_CMD_ARG(x)                  ((x) <<  0)
+
+/* SDMMC CMD Register Bitmask Definitions */
+#define SDMMC_CMD_CMD_INDEX(x)          (((x) & 0x3F) <<  0)
+#define SDMMC_CMD_RESPONSE_EXPECT                 (1U <<  6)
+#define SDMMC_CMD_RESPONSE_LENGTH                 (1U <<  7)
+#define SDMMC_CMD_CHECK_RESPONSE_CRC              (1U <<  8)
+#define SDMMC_CMD_DATA_EXPECTED                   (1U <<  9)
+#define SDMMC_CMD_READ_WRITE                      (1U << 10)
+#define SDMMC_CMD_TRANSFER_MODE                   (1U << 11)
+#define SDMMC_CMD_SEND_AUTO_STOP                  (1U << 12)
+#define SDMMC_CMD_WAIT_PRVDATA_COMPLETE           (1U << 13)
+#define SDMMC_CMD_STOP_ABORT_CMD                  (1U << 14)
+#define SDMMC_CMD_SEND_INITIALIZATION             (1U << 15)
+#define SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY     (1U << 21)
+#define SDMMC_CMD_READ_CEATA_DEVICE               (1U << 22)
+#define SDMMC_CMD_CCS_EXPECTED                    (1U << 23)
+#define SDMMC_CMD_ENABLE_BOOT                     (1U << 24)
+#define SDMMC_CMD_EXPECT_BOOT_ACK                 (1U << 25)
+#define SDMMC_CMD_DISABLE_BOOT                    (1U << 26)
+#define SDMMC_CMD_BOOT_MODE                       (1U << 27)
+#define SDMMC_CMD_VOLT_SWITCH                     (1U << 28)
+#define SDMMC_CMD_START_CMD                       (1U << 31)
+
+/* SDMMC MINTSTS Register Bitmask Definitions */
+#define SDMMC_MINTSTS_CDET                        (1U <<  0)
+#define SDMMC_MINTSTS_RE                          (1U <<  1)
+#define SDMMC_MINTSTS_CDONE                       (1U <<  2)
+#define SDMMC_MINTSTS_DTO                         (1U <<  3)
+#define SDMMC_MINTSTS_TXDR                        (1U <<  4)
+#define SDMMC_MINTSTS_RXDR                        (1U <<  5)
+#define SDMMC_MINTSTS_RCRC                        (1U <<  6)
+#define SDMMC_MINTSTS_DCRC                        (1U <<  7)
+#define SDMMC_MINTSTS_RTO                         (1U <<  8)
+#define SDMMC_MINTSTS_DRTO                        (1U <<  9)
+#define SDMMC_MINTSTS_HTO                         (1U << 10)
+#define SDMMC_MINTSTS_FRUN                        (1U << 11)
+#define SDMMC_MINTSTS_HLE                         (1U << 12)
+#define SDMMC_MINTSTS_SBE                         (1U << 13)
+#define SDMMC_MINTSTS_ACD                         (1U << 14)
+#define SDMMC_MINTSTS_EBE                         (1U << 15)
+#define SDMMC_MINTSTS_SDIO_INTERRUPT              (1U << 16)
+
+/* SDMMC RINTSTS Register Bitmask Definitions */
+#define SDMMC_RINTSTS_CDET                        (1U <<  0)
+#define SDMMC_RINTSTS_RE                          (1U <<  1)
+#define SDMMC_RINTSTS_CDONE                       (1U <<  2)
+#define SDMMC_RINTSTS_DTO                         (1U <<  3)
+#define SDMMC_RINTSTS_TXDR                        (1U <<  4)
+#define SDMMC_RINTSTS_RXDR                        (1U <<  5)
+#define SDMMC_RINTSTS_RCRC                        (1U <<  6)
+#define SDMMC_RINTSTS_DCRC                        (1U <<  7)
+#define SDMMC_RINTSTS_RTO_BAR                     (1U <<  8)
+#define SDMMC_RINTSTS_DRTO_BDS                    (1U <<  9)
+#define SDMMC_RINTSTS_HTO                         (1U << 10)
+#define SDMMC_RINTSTS_FRUN                        (1U << 11)
+#define SDMMC_RINTSTS_HLE                         (1U << 12)
+#define SDMMC_RINTSTS_SBE                         (1U << 13)
+#define SDMMC_RINTSTS_ACD                         (1U << 14)
+#define SDMMC_RINTSTS_EBE                         (1U << 15)
+#define SDMMC_RINTSTS_SDIO_INTERRUPT              (1U << 16)
+
+/* SDMMC STATUS Register Bitmask Definitions */
+#define SDMMC_STATUS_FIFO_RX_WATERMARK            (1U <<  0)
+#define SDMMC_STATUS_FIFO_TX_WATERMARK            (1U <<  1)
+#define SDMMC_STATUS_FIFO_EMPTY                   (1U <<  2)
+#define SDMMC_STATUS_FIFO_FULL                    (1U <<  3)
+#define SDMMC_STATUS_DATA_3_STATUS                (1U <<  8)
+#define SDMMC_STATUS_DATA_BUSY                    (1U <<  9)
+#define SDMMC_STATUS_DATA_STATE_MC_BUSY           (1U << 10)
+#define SDMMC_STATUS_DMA_ACK                      (1U << 30)
+#define SDMMC_STATUS_DMA_REQ                      (1U << 31)
+
+/* SDMMC FIFOTH Register Bitmask Definitions */
+#define SDMMC_FIFOTH_TX_WMARK(x)       (((x) & 0x7FF) <<  0)
+#define SDMMC_FIFOTH_RX_WMARK(x)       (((x) & 0x7FF) << 16)
+#define SDMMC_FIFOTH_DMA_MTS(x)        (((x) & 0x007) << 28)
+
+/* SDMMC CDETECT Register Bitmask Definitions */
+#define SDMMC_CDETECT_CARD_DETECT                 (1U <<  0)
+
+/* SDMMC WRTPRT Register Bitmask Definitions */
+#define SDMMC_WRTPRT_WRITE_PROTECT                (1U <<  0)
+
+/* SDMMC DEBNCE Register Bitmask Definitions */
+#define SDMMC_DEBNCE_DEBOUNCE_COUNT(x) (((x)&0xFFFFFF)<<  0)
+
+/* SDMMC RST_N Register Bitmask Definitions */
+#define SDMMC_RST_N_CARD_RESET                    (1U <<  0)
+
+/* SDMMC BMOD Register Bitmask Definitions */
+#define SDMMC_BMOD_SWR                            (1U <<  0)
+#define SDMMC_BMOD_FB                             (1U <<  1)
+#define SDMMC_BMOD_DSL(x)               (((x) & 0x1F) <<  2)
+#define SDMMC_BMOD_DE                             (1U <<  7)
+#define SDMMC_BMOD_PBL(x)               (((x) & 0x07) <<  8)
+
+/* SDMMC PLDMND Register Bitmask Definitions */
+#define SDMMC_PLDMND_PD(x)                       ((x) <<  0)
+
+/* SDMMC IDSTS Register Bitmask Definitions */
+#define SDMMC_IDSTS_TI                            (1U <<  0)
+#define SDMMC_IDSTS_RI                            (1U <<  1)
+#define SDMMC_IDSTS_FBE                           (1U <<  2)
+#define SDMMC_IDSTS_DU                            (1U <<  4)
+#define SDMMC_IDSTS_CES                           (1U <<  5)
+#define SDMMC_IDSTS_NIS                           (1U <<  8)
+#define SDMMC_IDSTS_AIS                           (1U <<  9)
+
+/* SDMMC IDSTS Register Bitmask Definitions */
+#define SDMMC_IDINTEN_TI                          (1U <<  0)
+#define SDMMC_IDINTEN_RI                          (1U <<  1)
+#define SDMMC_IDINTEN_FBE                         (1U <<  2)
+#define SDMMC_IDINTEN_DU                          (1U <<  4)
+#define SDMMC_IDINTEN_CES                         (1U <<  5)
+#define SDMMC_IDINTEN_NIS                         (1U <<  8)
+#define SDMMC_IDINTEN_AIS                         (1U <<  9)
+
+#endif /* __MCI_LPC18XX_H */

CMSIS/Pack/Example/CMSIS_Driver/ReadMe.txt

@@ -0,0 +1,16 @@
+This folder contains reference implementations of the following drivers:
+
+ CAN_LPC18xx.[ch]:        CAN driver for NXP LPC1800 series
+ EMAC_LPC18xx.[ch]:       Ethernet driver for NXP LPC1800 series
+ I2C_LPC18xx.[ch]:        I2C driver for NXP LPC1800 series
+ I2S_LPC18xx.[ch]:        I2S(SAI) driver for NXP LPC1800 series
+ MCI_LPC18xx.[ch:         MCI driver for NXP LPC1800 series
+ SSP_LPC18xx.[ch]:        SPI driver for NXP LPC1800 series
+ USART_LPC18xx.[ch]:      USART driver for NXP LPC1800 series
+ USBDn_LPC18xx.c:         USB 0/1 Device driver for NXP LPC1800 series
+ USBHn_LPC18xx.c:         USB 0/1 Host driver for NXP LPC1800 series
+ USBn_LPC18xx.[ch]:       USB 0/1 driver (common) for NXP LPC1800 series
+ USB_LPC18xx.h:           USB driver (common) header for NXP LPC1800 series
+
+Further driver reference implementations are available in 
+Device Family Packs (DFP) labelled with version 2.0.0 or higher. 

CMSIS/Pack/Example/CMSIS_Driver/SCU_LPC18xx.c

@@ -0,0 +1,159 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        02. March 2016
+ * $Revision:    V1.1
+ *
+ * Project:      SCU Driver for NXP LPC18xx
+ * -------------------------------------------------------------------------- */
+
+/* History:
+ *  Version 1.1
+ *    - Corrected SCU_SFSCLKx(clk_pin) and SCU_ENAIOx(n) macros
+ *  Version 1.0
+ *    - Initial release
+ */
+
+#include "LPC18xx.h"
+#include "SCU_LPC18xx.h"
+
+#define PORT_OFFSET          ( 0x80 )
+#define PIN_OFFSET           ( 0x04 )
+#define SCU_SFSPx(port, pin) (*((volatile uint32_t *) ((LPC_SCU_BASE + PORT_OFFSET * port + PIN_OFFSET * pin))))
+#define SCU_SFSCLKx(clk_pin) (*((volatile uint32_t *) (&(LPC_SCU->SFSCLK_0) + clk_pin)))
+#define SCU_ENAIOx(n)        (*((volatile uint32_t *) (&(LPC_SCU->ENAIO0) + n)))
+
+
+/**
+  \fn          int32_t SCU_PinConfiguare (uint8_t port, uint8_t pin, uint32_t pin_cfg)
+  \brief       Set pin function and electrical characteristics
+  \param[in]   port       Port number (0..15)
+  \param[in]   pin        Pin number (0..31)
+  \param[in]   pin_cfg    pin_cfg configuration bit mask
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t SCU_PinConfigure (uint8_t port, uint8_t pin, uint32_t pin_cfg) {
+
+  if ((port > 15) || (pin > 31)) return -1;
+  SCU_SFSPx(port, pin) = pin_cfg;
+  return 0;
+}
+
+/**
+  \fn          int32_t SCU_CLK_PinConfigure (uint8_t clk_pin, uint32_t pin_cfg)
+  \brief       Set pin function and electrical characteristics for CLK pins
+  \param[in]   clk_pin    Clock pin number should be 0..3
+  \param[in]   pin_cfg    pin_cfg
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t SCU_CLK_PinConfigure (uint8_t pin_clk, uint32_t pin_cfg) {
+
+  if (pin_clk > 3) return -1;
+  SCU_SFSCLKx(pin_clk) = pin_cfg;
+  return 0;
+}
+
+/**
+  \fn          int32_t SCU_USB1_PinConfigure (uint32_t USB1_pin_cfg)
+  \brief       Pin configuration for USB1 USB_DP/USBDM  pins
+  \param[in]   USB1_pin_cfg   USB1_pin_cfg configuration bit mask
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t SCU_USB1_PinConfigure (uint32_t USB1_pin_cfg) {
+  LPC_SCU->SFSUSB = USB1_pin_cfg;
+  return 0;
+}
+
+/**
+  \fn          int32_t SCU_I2C_PinConfigure (uint32_t I2C_mode)
+  \brief       Set I2C pin configuration
+  \param[in]   I2C_mode:  SCU_I2C_PIN_MODE_DISABLED
+                          SCU_I2C_PIN_MODE_STANDARD_FAST
+                          SCU_I2C_PIN_MODE_FAST_PLUS
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t SCU_I2C_PinConfigure (uint32_t I2C_mode) {
+
+  switch (I2C_mode) {
+    case SCU_I2C_PIN_MODE_DISABLED:      break;
+    case SCU_I2C_PIN_MODE_STANDARD_FAST: break;
+    case SCU_I2C_PIN_MODE_FAST_PLUS:     break;
+    default: return -1;
+  }
+  LPC_SCU->SFSI2C0 = I2C_mode;
+  return 0;
+}
+
+/**
+  \fn          int32_t SCU_ADC_ChannelPinConfigure (uint8_t ADC_num, uint8_t channel, uint32_t cmd)
+  \brief       ADC Channel configuration
+  \param[in]   ADC_num:  0 = ADC0, 1 = ADC1
+  \param[in]   channel:  channel number 0..7
+  \param[in]   cmd:      1 - enabled, 0 - disabled
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t SCU_ADC_ChannelPinConfigure (uint8_t ADC_num, uint8_t channel, uint32_t cmd) {
+
+  if ((ADC_num > 1) || (channel > 7) || (cmd > 1)) return -1;
+  cmd ? (SCU_ENAIOx(ADC_num) |= (1 << channel)) : (SCU_ENAIOx(ADC_num) &= ~(1 << channel));
+  return 0;
+}
+
+/**
+  \fn          int32_t SCU_DAC_PinConfigure (uint32_t cmd)
+  \brief       Analog function on P4_4
+  \param[in]   cmd:      1 - enabled, 0 - disabled
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t SCU_DAC_PinConfigure (uint32_t cmd) {
+
+  if (cmd > 1) return -1;
+  cmd ? (LPC_SCU->ENAIO2 |= SCU_ENAIO2_DAC) : (LPC_SCU->ENAIO2 &= ~SCU_ENAIO2_DAC);
+  return 0;
+}
+
+/**
+  \fn          int32_t SCU_PinInterruptSourceSelect (uint8_t pin_int, uint8_t port, uint8_t pin)
+  \brief       Select interrupt source pin
+  \param[in]   pin_int:  pin interrupt 0..7
+  \param[in]   port:     GPIO port number 0..7
+  \param[in]   pin:      GPIO pin number 0..31
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t SCU_PinInterruptSourceSelect (uint8_t pin_int, uint8_t port, uint8_t pin) {
+
+  if ((port > 7) || (pin > 31) || (pin_int > 7)) return -1;
+
+  if (pin_int < 4) {
+    LPC_SCU->PINTSEL0 &= ~(0xFF << (8 * pin_int));
+    LPC_SCU->PINTSEL0 |=  ((pin | (port << 5)) << (8 * pin_int));
+  } else {
+    pin_int -= 4;
+    LPC_SCU->PINTSEL1 &= ~(0xFF << (8 * pin_int));
+    LPC_SCU->PINTSEL1 |=  ((pin | (port << 5)) << (8 * pin_int));
+  }
+
+  return 0;
+}

CMSIS/Pack/Example/CMSIS_Driver/SCU_LPC18xx.h

@@ -0,0 +1,196 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        02. March 2016
+ * $Revision:    V1.0
+ *
+ * Project:      SCU Driver Definitions for NXP LPC18xx
+ * -------------------------------------------------------------------------- */
+
+#ifndef __SCU_LPC18XX_H
+#define __SCU_LPC18XX_H
+
+#include <stdint.h>
+
+// Pin identifier
+typedef struct _PIN_ID {
+  uint8_t       port;
+  uint8_t       num;
+  uint32_t      config_val;
+} PIN_ID;
+
+//------------------------------------------------------------------------------
+// SCU REGISTER BIT DEFINITIONS
+//------------------------------------------------------------------------------
+// SCU Pin configuration register for normal-drive pins
+#define SCU_SFS_MODE_POS              (         0 )
+#define SCU_SFS_MODE_MSK              (7    <<  SCU_SFS_MODE_POS)
+#define SCU_SFS_EPD                   (1    <<  3)
+#define SCU_SFS_EPUN                  (1    <<  4)
+#define SCU_SFS_EHS                   (1    <<  5)
+#define SCU_SFS_EZI                   (1    <<  6)
+#define SCU_SFS_ZIF                   (1    <<  7)
+
+// SCU Pin configuration register for high-drive pins
+//    P1_17
+//    P2_3 to P2_5
+//    P8_0 to P8_2
+//    PA_1 to PA_3
+#define SCU_SFS_EHD_POS               (         8 )
+#define SCU_SFS_EHD_MSK               (3    <<  SCU_SFS_EHD_POS)
+
+// SCU Pin configuration register for USB1 pins USB1_DP/USB1_DM
+#define SCU_SFSUSB_AIM                (1    <<  0)
+#define SCU_SFSUSB_ESEA               (1    <<  1)
+#define SCU_SFSUSB_EPD                (1    <<  2)
+#define SCU_SFSUSB_EPWR               (1    <<  4)
+#define SCU_SFSUSB_VBUS               (1    <<  5)
+
+// SCU Pin configuration for open-drain I2C pins
+#define SCU_SFSI2C_SCL_EFP            (1    <<  0)
+#define SCU_SFSI2C_SCL_EHD            (1    <<  2)
+#define SCU_SFSI2C_SCL_EZI            (1    <<  3)
+#define SCU_SFSI2C_SCL_ZIF            (1    <<  7)
+#define SCU_SFSI2C_SDA_EFP            (1    <<  8)
+#define SCU_SFSI2C_SDA_EHD            (1    << 10)
+#define SCU_SFSI2C_SDA_EZI            (1    << 11)
+#define SCU_SFSI2C_SDA_ZIF            (1    << 15)
+
+// SCU Analog function select register ENAIO2
+#define SCU_ENAIO2_DAC                (1    <<  0)
+#define SCU_ENAIO2_BG                 (1    <<  4)
+
+
+
+//------------------------------------------------------------------------------
+// SCU FUNCTION PARAMETER DEFINITIONS
+//------------------------------------------------------------------------------
+// SCU_PIN_CFG_MODE(mode)
+#define SCU_CFG_MODE_FUNC0                    (0)
+#define SCU_CFG_MODE_FUNC1                    (1)
+#define SCU_CFG_MODE_FUNC2                    (2)
+#define SCU_CFG_MODE_FUNC3                    (3)
+#define SCU_CFG_MODE_FUNC4                    (4)
+#define SCU_CFG_MODE_FUNC5                    (5)
+#define SCU_CFG_MODE_FUNC6                    (6)
+#define SCU_CFG_MODE_FUNC7                    (7)
+
+// SCU_PIN_CFG_DRIVER_STRENGTH(ehd) (only for high drive pins)
+#define SCU_CFG_EHD_4mA                       (0)
+#define SCU_CFG_EHD_8mA                       (1)
+#define SCU_CFG_EHD_14mA                      (2)
+#define SCU_CFG_EHD_20mA                      (3)
+
+// pin_cfg (configuration bit mask)
+#define SCU_PIN_CFG_MODE(mode)                (((mode) & SCU_SFS_MODE_MSK) << SCU_SFS_MODE_POS)
+#define SCU_PIN_CFG_PULLDOWN_EN               ( SCU_SFS_EPD )
+#define SCU_PIN_CFG_PULLUP_DIS                ( SCU_SFS_EPUN)
+#define SCU_PIN_CFG_HIGH_SPEED_SLEW_RATE_EN   ( SCU_SFS_EHS )
+#define SCU_PIN_CFG_INPUT_BUFFER_EN           ( SCU_SFS_EZI )
+#define SCU_PIN_CFG_INPUT_FILTER_DIS          ( SCU_SFS_ZIF )
+// additional pin_cfg for high-drive pins only
+#define SCU_PIN_CFG_DRIVER_STRENGTH(ehd)      ((val & SCU_SFS_EHD_MSK) << SCU_SFS_EHD_POS)
+
+// USB1_pin_cfg (configuration bit mask)
+#define SCU_USB1_PIN_CFG_AIM                  (SCU_SFSUSB_AIM )
+#define SCU_USB1_PIN_CFG_ESEA                 (SCU_SFSUSB_ESEA)
+#define SCU_USB1_PIN_CFG_EPD                  (SCU_SFSUSB_EPD )
+#define SCU_USB1_PIN_CFG_EPWR                 (SCU_SFSUSB_EPWR)
+#define SCU_USB1_PIN_CFG_VBUS                 (SCU_SFSUSB_VBUS)
+
+// I2C_mode
+#define SCU_I2C_PIN_MODE_DISABLED             (0)
+#define SCU_I2C_PIN_MODE_STANDARD_FAST        (SCU_SFSI2C_SCL_EZI | SCU_SFSI2C_SDA_EZI)
+#define SCU_I2C_PIN_MODE_FAST_PLUS            (SCU_SFSI2C_SCL_EHD | SCU_SFSI2C_SCL_EZI | \
+                                               SCU_SFSI2C_SCL_EZI | SCU_SFSI2C_SDA_EHD | \
+                                               SCU_SFSI2C_SDA_EZI)
+
+
+/**
+  \fn          int32_t SCU_PinConfiguare (uint8_t port, uint8_t pin, uint32_t pin_cfg)
+  \brief       Set pin function and electrical characteristics
+  \param[in]   port       Port number (0..15)
+  \param[in]   pin        Pin number (0..31)
+  \param[in]   pin_cfg    pin_cfg configuration bit mask
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+extern int32_t SCU_PinConfigure (uint8_t port, uint8_t pin, uint32_t pin_cfg);
+
+/**
+  \fn          int32_t SCU_CLK_PinConfigure (uint8_t clk_pin, uint32_t pin_cfg)
+  \brief       Set pin function and electrical characteristics for CLK pins
+  \param[in]   clk_pin    Clock pin number should be 0..3
+  \param[in]   pin_cfg    pin_cfg
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+extern int32_t SCU_CLK_PinConfigure (uint8_t pin_clk, uint32_t pin_cfg);
+
+/**
+  \fn          int32_t SCU_USB1_PinConfigure (uint32_t USB1_pin_cfg)
+  \brief       Pin configuration for USB1 USB_DP/USBDM  pins
+  \param[in]   USB1_pin_cfg   USB1_pin_cfg configuration bit mask
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+extern int32_t SCU_USB1_PinConfigure (uint32_t USB1_pin_cfg);
+
+/**
+  \fn          int32_t SCU_I2C_PinConfigure (uint32_t I2C_mode)
+  \brief       Set I2C pin configuration
+  \param[in]   I2C_mode:  SCU_I2C_PIN_MODE_DISABLED
+                          SCU_I2C_PIN_MODE_STANDARD_FAST
+                          SCU_I2C_PIN_MODE_FAST_PLUS
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+extern int32_t SCU_I2C_PinConfigure (uint32_t I2C_mode);
+
+/**
+  \fn          int32_t SCU_ADC_ChannelPinConfigure (uint8_t ADC_num, uint8_t channel, uint32_t cmd)
+  \brief       ADC Channel configuration
+  \param[in]   ADC_num:  0 = ADC0, 1 = ADC1
+  \param[in]   channel:  channel number 0..7
+  \param[in]   cmd:      1 - enabled, 0 - disabled
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+extern int32_t SCU_ADC_ChannelPinConfigure (uint8_t ADC_num, uint8_t channel, uint32_t cmd);
+
+/**
+  \fn          int32_t SCU_DAC_PinConfigure (uint32_t cmd)
+  \brief       Analog function on P4_4
+  \param[in]   cmd:      1 - enabled, 0 - disabled
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+extern int32_t SCU_DAC_PinConfigure (uint32_t cmd);
+
+/**
+  \fn          int32_t SCU_PinInterruptSourceSelect (uint8_t pin_int, uint8_t port, uint8_t pin)
+  \brief       Select interrupt source pin
+  \param[in]   pin_int:  pin interrupt 0..7
+  \param[in]   port:     GPIO port number 0..7
+  \param[in]   pin:      GPIO pin number 0..31
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+extern int32_t SCU_PinInterruptSourceSelect (uint8_t pin_int, uint8_t port, uint8_t pin);
+
+#endif /* __SCU_LPC18XX_H */

CMSIS/Pack/Example/CMSIS_Driver/SSP_LPC18xx.c

@@ -0,0 +1,1034 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        13. March 2016
+ * $Revision:    V2.8
+ *
+ * Driver:       Driver_SPI0, Driver_SPI1
+ * Configured:   via RTE_Device.h configuration file
+ * Project:      SPI (SSP used for SPI) Driver for NXP LPC18xx
+ * --------------------------------------------------------------------------
+ * Use the following configuration settings in the middleware component
+ * to connect to this driver.
+ *
+ *   Configuration Setting                 Value   SPI Interface
+ *   ---------------------                 -----   -------------
+ *   Connect to hardware via Driver_SPI# = 0       use SPI0 (SSP0)
+ *   Connect to hardware via Driver_SPI# = 1       use SPI1 (SSP1)
+ * -------------------------------------------------------------------------- */
+
+/* History:
+ *  Version 2.8
+ *    - Corrected Pin Configuration and Unconfiguration
+ *  Version 2.7
+ *    - Driver update to work with GPDMA_LPC18xx ver.: 1.3
+ *  Version 2.6
+ *    - Corrected Bus Speed configuration
+ *    - Corrected PowerControl function for conditional Power full (driver must be initialized)
+ *  Version 2.5
+ *    - PowerControl for Power OFF and Uninitialize functions made unconditional.
+ *    - Corrected status bit-field handling, to prevent race conditions.
+ *    - Corrected ARM_SPI_EVENT_DATA_LOST event handling in slave mode
+ *  Version 2.4
+ *    - Corrected ssp->info->mode and pin handling
+ *  Version 2.3
+ *    - Updated Control functions
+ *    - GPDMA initialization and uninitialization
+ *  Version 2.2
+ *    - Updated Send and Receive functions to avoid stack corruption
+ *  Version 2.1
+ *    - Added DMA support
+ *  Version 2.0
+ *    - Initial CMSIS Driver API V2.00 release
+ */
+
+#include <string.h>
+
+#include "SCU_LPC18xx.h"
+#include "GPIO_LPC18xx.h"
+#include "GPDMA_LPC18xx.h"
+#include "SSP_LPC18xx.h"
+
+#include "Driver_SPI.h"
+
+#include "RTE_Device.h"
+#include "RTE_Components.h"
+
+extern uint32_t GetClockFreq   (uint32_t clk_src);
+void SSP0_GPDMA_Tx_SignalEvent (uint32_t event);
+void SSP0_GPDMA_Rx_SignalEvent (uint32_t event);
+void SSP1_GPDMA_Tx_SignalEvent (uint32_t event);
+void SSP1_GPDMA_Rx_SignalEvent (uint32_t event);
+
+#define ARM_SPI_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,8)   // driver version
+
+#if ((defined(RTE_Drivers_SPI0) || defined(RTE_Drivers_SPI1)) && (!RTE_SSP0) && (!RTE_SSP1))
+#error "SSP not configured in RTE_Device.h!"
+#endif
+#if ((RTE_SSP0) &&                                  \
+    ((RTE_SSP0_DMA_TX_EN && !RTE_SSP0_DMA_RX_EN) || \
+     (RTE_SSP0_DMA_RX_EN && !RTE_SSP0_DMA_TX_EN)))
+#error "Both Tx and Rx DMA for SSP0 have to be enabled or disabled in RTE_Device.h!"
+#endif
+#if ((RTE_SSP1) &&                                  \
+    ((RTE_SSP1_DMA_TX_EN && !RTE_SSP1_DMA_RX_EN) || \
+     (RTE_SSP1_DMA_RX_EN && !RTE_SSP1_DMA_TX_EN)))
+#error "Both Tx and Rx DMA for SSP1 have to be enabled or disabled in RTE_Device.h!"
+#endif
+
+// Driver Version
+static const ARM_DRIVER_VERSION DriverVersion = {
+  ARM_SPI_API_VERSION,
+  ARM_SPI_DRV_VERSION
+};
+
+// Driver Capabilities
+static const ARM_SPI_CAPABILITIES DriverCapabilities = {
+  0,  // Simplex Mode (Master and Slave)
+  1,  // TI Synchronous Serial Interface
+  1,  // Microwire Interface
+  0   // Signal Mode Fault event: \ref ARM_SPI_EVENT_MODE_FAULT
+};
+
+#if (RTE_SSP0)
+static SSP_INFO          SSP0_Info = { 0 };
+static SSP_TRANSFER_INFO SSP0_Xfer;
+
+static PIN_ID  SSP0_pin_sck    = { RTE_SSP0_SCK_PORT,  RTE_SSP0_SCK_BIT,  RTE_SSP0_SCK_FUNC };
+static PIN_ID  SSP0_pin_miso   = { RTE_SSP0_MISO_PORT, RTE_SSP0_MISO_BIT, RTE_SSP0_MISO_FUNC};
+static PIN_ID  SSP0_pin_mosi   = { RTE_SSP0_MOSI_PORT, RTE_SSP0_MOSI_BIT, RTE_SSP0_MOSI_FUNC};
+#if (RTE_SSP0_SSEL_PIN_EN == 1U)
+static PIN_ID  SSP0_pin_ssel   = { RTE_SSP0_SSEL_PORT, RTE_SSP0_SSEL_BIT, RTE_SSP0_SSEL_FUNC };
+static GPIO_ID SSP0_gpio_ssel  = { RTE_SSP0_SSEL_GPIO_PORT, RTE_SSP0_SSEL_GPIO_BIT};
+#endif
+
+
+static SSP_RESOURCES SSP0_Resources = {
+    LPC_SSP0,
+  { &SSP0_pin_sck,
+    &SSP0_pin_miso,
+    &SSP0_pin_mosi,
+#if (RTE_SSP0_SSEL_PIN_EN == 1U)
+    &SSP0_pin_ssel,
+    &SSP0_gpio_ssel,
+    RTE_SSP0_SSEL_GPIO_FUNC,
+#else
+    NULL,
+    NULL,
+    0,
+#endif
+  },
+  { CGU_BASE_SSPx_CLK_AUTOBLOCK | ((CLK_SRC_PLL1 << 24) & CGU_BASE_SSPx_CLK_CLK_SEL),
+    &(LPC_CGU->BASE_SSP0_CLK),
+    CCU1_CLK_M3_SSPx_CFG_AUTO | CCU1_CLK_M3_SSPx_CFG_RUN,
+    &(LPC_CCU1->CLK_M3_SSP0_CFG),
+    CCU1_CLK_M3_SSPx_STAT_RUN,
+    &(LPC_CCU1->CLK_M3_SSP0_STAT) },
+  { RGU_RESET_CTRL1_SSP0_RST,
+    &(LPC_RGU->RESET_CTRL1),
+    RGU_RESET_ACTIVE_STATUS1_SSP0_RST,
+    &(LPC_RGU->RESET_ACTIVE_STATUS1) },
+  { RTE_SSP0_DMA_TX_EN,
+    RTE_SSP0_DMA_TX_CH,
+    RTE_SSP0_DMA_TX_PERI,
+    RTE_SSP0_DMA_TX_PERI_SEL,
+    SSP0_GPDMA_Tx_SignalEvent,
+    RTE_SSP0_DMA_RX_EN,
+    RTE_SSP0_DMA_RX_CH,
+    RTE_SSP0_DMA_RX_PERI,
+    RTE_SSP0_DMA_RX_PERI_SEL,
+    SSP0_GPDMA_Rx_SignalEvent },
+  SSP0_IRQn,
+ &SSP0_Info,
+ &SSP0_Xfer
+};
+#endif
+
+#if (RTE_SSP1)
+static SSP_INFO          SSP1_Info = { 0 };
+static SSP_TRANSFER_INFO SSP1_Xfer;
+
+static PIN_ID  SSP1_pin_sck    = { RTE_SSP1_SCK_PORT,  RTE_SSP1_SCK_BIT,  RTE_SSP1_SCK_FUNC };
+static PIN_ID  SSP1_pin_miso   = { RTE_SSP1_MISO_PORT, RTE_SSP1_MISO_BIT, RTE_SSP1_MISO_FUNC};
+static PIN_ID  SSP1_pin_mosi   = { RTE_SSP1_MOSI_PORT, RTE_SSP1_MOSI_BIT, RTE_SSP1_MOSI_FUNC};
+#if (RTE_SSP1_SSEL_PIN_EN == 1U)
+static PIN_ID  SSP1_pin_ssel   = { RTE_SSP1_SSEL_PORT, RTE_SSP1_SSEL_BIT, RTE_SSP1_SSEL_FUNC };
+static GPIO_ID SSP1_gpio_ssel  = { RTE_SSP1_SSEL_GPIO_PORT, RTE_SSP1_SSEL_GPIO_BIT};
+#endif
+
+static SSP_RESOURCES SSP1_Resources = {
+  LPC_SSP1,
+  { &SSP1_pin_sck,
+    &SSP1_pin_miso,
+    &SSP1_pin_mosi,
+#if (RTE_SSP1_SSEL_PIN_EN == 1U)
+    &SSP1_pin_ssel,
+    &SSP1_gpio_ssel,
+    RTE_SSP1_SSEL_GPIO_FUNC,
+#else
+    NULL,
+    NULL,
+    0,
+#endif
+  },
+  { CGU_BASE_SSPx_CLK_AUTOBLOCK | ((CLK_SRC_PLL1 << 24) & CGU_BASE_SSPx_CLK_CLK_SEL),
+    &(LPC_CGU->BASE_SSP1_CLK),
+    CCU1_CLK_M3_SSPx_CFG_AUTO | CCU1_CLK_M3_SSPx_CFG_RUN,
+    &(LPC_CCU1->CLK_M3_SSP1_CFG),
+    CCU1_CLK_M3_SSPx_STAT_RUN,
+    &(LPC_CCU1->CLK_M3_SSP1_STAT) },
+  { RGU_RESET_CTRL1_SSP1_RST,
+    &(LPC_RGU->RESET_CTRL1),
+    RGU_RESET_ACTIVE_STATUS1_SSP1_RST,
+    &(LPC_RGU->RESET_ACTIVE_STATUS1) },
+  { RTE_SSP1_DMA_TX_EN,
+    RTE_SSP1_DMA_TX_CH,
+    RTE_SSP1_DMA_TX_PERI,
+    RTE_SSP1_DMA_TX_PERI_SEL,
+    SSP1_GPDMA_Tx_SignalEvent,
+    RTE_SSP1_DMA_RX_EN,
+    RTE_SSP1_DMA_RX_CH,
+    RTE_SSP1_DMA_RX_PERI,
+    RTE_SSP1_DMA_RX_PERI_SEL,
+    SSP1_GPDMA_Rx_SignalEvent },
+  SSP1_IRQn,
+ &SSP1_Info,
+ &SSP1_Xfer
+};
+#endif
+
+
+
+/**
+  \fn          ARM_DRIVER_VERSION SSP_GetVersion (void)
+  \brief       Get SSP driver version.
+  \return      \ref ARM_DRV_VERSION
+*/
+static ARM_DRIVER_VERSION SSP_GetVersion (void) {
+  return DriverVersion;
+}
+
+/**
+  \fn          ARM_SPI_CAPABILITIES SSP_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_SPI_CAPABILITIES
+*/
+static ARM_SPI_CAPABILITIES SSP_GetCapabilities (void) {
+  return DriverCapabilities;
+}
+
+/**
+  \fn          int32_t SSPx_Initialize (ARM_SPI_SignalEvent_t cb_event, SSP_RESOURCES *ssp)
+  \brief       Initialize SSP Interface.
+  \param[in]   cb_event  Pointer to \ref ARM_SPI_SignalEvent
+  \param[in]   ssp       Pointer to SSP resources
+  \return      \ref execution_status
+*/
+static int32_t SSPx_Initialize (ARM_SPI_SignalEvent_t cb_event, SSP_RESOURCES *ssp) {
+  uint32_t val;
+
+  if (ssp->info->state & SSP_INITIALIZED) { return ARM_DRIVER_OK; }
+
+  // Initialize SSP Run-Time Resources
+  ssp->info->cb_event          = cb_event;
+  ssp->info->status.busy       = 0U;
+  ssp->info->status.data_lost  = 0U;
+  ssp->info->status.mode_fault = 0U;
+
+  // Clear transfer information
+  memset(ssp->xfer, 0, sizeof(SSP_TRANSFER_INFO));
+
+  // Configure pins
+  val = SCU_PIN_CFG_PULLUP_DIS |   SCU_PIN_CFG_HIGH_SPEED_SLEW_RATE_EN | SCU_PIN_CFG_INPUT_BUFFER_EN | SCU_PIN_CFG_INPUT_FILTER_DIS;
+                                   SCU_PinConfigure     (ssp->pin.sck->port,  ssp->pin.sck->num,  ssp->pin.sck->config_val  | val);
+  if (ssp->pin.sck->port == 16U) { SCU_CLK_PinConfigure (ssp->pin.sck->num,                       ssp->pin.sck->config_val  | val); }
+  else                           { SCU_PinConfigure     (ssp->pin.sck->port,  ssp->pin.sck->num,  ssp->pin.sck->config_val  | val); }
+                                   SCU_PinConfigure     (ssp->pin.miso->port, ssp->pin.miso->num, ssp->pin.miso->config_val | val);
+                                   SCU_PinConfigure     (ssp->pin.mosi->port, ssp->pin.mosi->num, ssp->pin.mosi->config_val | val);
+
+  // Configure DMA if it will be used
+  if (ssp->dma.tx_en || ssp->dma.rx_en) { GPDMA_Initialize (); }
+
+  if (ssp->dma.tx_en) { GPDMA_PeripheralSelect (ssp->dma.tx_peri, ssp->dma.tx_peri_sel); }
+  if (ssp->dma.rx_en) { GPDMA_PeripheralSelect (ssp->dma.rx_peri, ssp->dma.rx_peri_sel); }
+
+  ssp->info->state = SSP_INITIALIZED;   // SSP is initialized
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t SSPx_Uninitialize (SSP_RESOURCES *ssp)
+  \brief       De-initialize SSP Interface.
+  \param[in]   ssp  Pointer to SSP resources
+  \return      \ref execution_status
+*/
+static int32_t SSPx_Uninitialize (SSP_RESOURCES *ssp) {
+
+  // Unconfigure pins
+  if (ssp->pin.ssel != NULL)     { SCU_PinConfigure     (ssp->pin.ssel->port, ssp->pin.ssel->num, 0U); }
+  if (ssp->pin.sck->port == 16U) { SCU_CLK_PinConfigure (ssp->pin.sck->num,                       0U); }
+  else                           { SCU_PinConfigure     (ssp->pin.sck->port,  ssp->pin.sck->num,  0U); }
+                                   SCU_PinConfigure     (ssp->pin.miso->port, ssp->pin.miso->num, 0U);
+                                   SCU_PinConfigure     (ssp->pin.mosi->port, ssp->pin.mosi->num, 0U);
+
+  // Uninitialize DMA
+  if (ssp->dma.tx_en || ssp->dma.rx_en) { GPDMA_Uninitialize (); }
+
+  ssp->info->state = 0U;                // SSP is uninitialized
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t SSPx_PowerControl (ARM_POWER_STATE state, SSP_RESOURCES *ssp)
+  \brief       Control SSP Interface Power.
+  \param[in]   state  Power state
+  \param[in]   ssp    Pointer to SSP resources
+  \return      \ref execution_status
+*/
+static int32_t SSPx_PowerControl (ARM_POWER_STATE state, SSP_RESOURCES *ssp) {
+
+  switch (state) {
+    case ARM_POWER_OFF:
+      NVIC_DisableIRQ (ssp->irq_num);   // Disable SSP IRQ in NVIC
+
+      if (ssp->info->status.busy) {
+        // If DMA mode - disable DMA channel
+        if (ssp->dma.tx_en) { GPDMA_ChannelDisable (ssp->dma.tx_ch); } 
+        // If DMA mode - disable DMA channel
+        if (ssp->dma.rx_en) { GPDMA_ChannelDisable (ssp->dma.rx_ch); }
+      }
+
+      // Reset SSP peripheral
+      *(ssp->rst.reg_cfg)  = ssp->rst.reg_cfg_val;
+       while (!(*(ssp->rst.reg_stat) & ssp->rst.reg_stat_val));
+
+      if (*(ssp->clk.reg_cfg) == 0U) {
+         *(ssp->clk.peri_cfg) = ~1U;
+        while ( *(ssp->clk.peri_cfg) & 1U);
+
+        // Power down, clock source set to IRC
+        *(ssp->clk.reg_cfg) =  1U | (1U << 24) | (1U << 11);
+      }
+
+      // Reset SSP Run-Time Resources
+      ssp->info->status.busy       = 0U;
+      ssp->info->status.data_lost  = 0U;
+      ssp->info->status.mode_fault = 0U;
+
+      // Clear transfer information
+      memset(ssp->xfer, 0, sizeof(SSP_TRANSFER_INFO));
+
+      ssp->info->state &= ~SSP_POWERED; // SSP is not powered
+      break;
+
+    case ARM_POWER_FULL:
+      if ((ssp->info->state & SSP_INITIALIZED) == 0U) { return ARM_DRIVER_ERROR; }
+      if ((ssp->info->state & SSP_POWERED)     != 0U) { return ARM_DRIVER_OK; }
+
+      // Initialize SSP register clock
+      *(ssp->clk.reg_cfg) = ssp->clk.reg_cfg_val;
+
+      // Activate SSP peripheral clock
+      *(ssp->clk.peri_cfg) = ssp->clk.peri_cfg_val;
+      while (!(*(ssp->clk.peri_stat) & ssp->clk.peri_stat_val));
+
+      // Reset SSP peripheral
+      *(ssp->rst.reg_cfg)  = ssp->rst.reg_cfg_val;
+      while (!(*(ssp->rst.reg_stat) & ssp->rst.reg_stat_val));
+
+      ssp->reg->IMSC  = 0U;             // Disable SSP interrupts
+      ssp->reg->ICR   = 3U;             // Clear SSP interrupts
+
+      // Reset SSP Run-Time Resources
+      ssp->info->status.busy       = 0U;
+      ssp->info->status.data_lost  = 0U;
+      ssp->info->status.mode_fault = 0U;
+
+      ssp->info->state |=  SSP_POWERED; // SSP is powered
+
+      // Enable DMA
+      if (ssp->dma.tx_en) { ssp->reg->DMACR |= SSPx_DMACR_TXDMAE; }
+      if (ssp->dma.rx_en) { ssp->reg->DMACR |= SSPx_DMACR_RXDMAE; }
+
+      NVIC_ClearPendingIRQ (ssp->irq_num);
+      NVIC_EnableIRQ (ssp->irq_num);    // Enable SSP IRQ in NVIC
+      break;
+
+    default:
+      return ARM_DRIVER_ERROR_UNSUPPORTED;
+  }
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t SSPx_Send (const void *data, uint32_t num, SSP_RESOURCES *ssp)
+  \brief       Start sending data to SSP transmitter.
+  \param[in]   data  Pointer to buffer with data to send to SSP transmitter
+  \param[in]   num   Number of data items to send
+  \param[in]   ssp   Pointer to SSP resources
+  \return      \ref execution_status
+*/
+static int32_t SSPx_Send (const void *data, uint32_t num, SSP_RESOURCES *ssp) {
+  static uint32_t dummy_data;
+
+  if ((data == NULL) || (num == 0U))        { return ARM_DRIVER_ERROR_PARAMETER; }
+  if (!(ssp->info->state & SSP_CONFIGURED)) { return ARM_DRIVER_ERROR; }
+  if (  ssp->info->status.busy)             { return ARM_DRIVER_ERROR_BUSY; }
+  ssp->info->status.busy       = 1U;
+  ssp->info->status.data_lost  = 0U;
+  ssp->info->status.mode_fault = 0U;
+
+  ssp->xfer->rx_buf = NULL;
+  ssp->xfer->tx_buf = (uint8_t *)data;
+
+  ssp->xfer->num    = num;
+  ssp->xfer->rx_cnt = 0U;
+  ssp->xfer->tx_cnt = 0U;
+
+  if (ssp->dma.tx_en && ssp->dma.rx_en) {
+    if (GPDMA_ChannelConfigure (ssp->dma.rx_ch,
+                               (uint32_t)&ssp->reg->DR,
+                               (uint32_t)&dummy_data,
+                                num,
+                                GPDMA_CH_CONTROL_SBSIZE(GPDMA_BSIZE_1)                            |
+                                GPDMA_CH_CONTROL_DBSIZE(GPDMA_BSIZE_1)                            |
+                                GPDMA_CH_CONTROL_SWIDTH((ssp->reg->CR0 & SSPx_CR0_DSS) > 7)       |
+                                GPDMA_CH_CONTROL_DWIDTH((ssp->reg->CR0 & SSPx_CR0_DSS) > 7)       |
+                                GPDMA_CH_CONTROL_S                                                |
+                                GPDMA_CH_CONTROL_D                                                |
+                                GPDMA_CH_CONTROL_I,
+                                GPDMA_CH_CONFIG_SRC_PERI(ssp->dma.rx_peri)      |
+                                GPDMA_CH_CONFIG_FLOWCNTRL(GPDMA_TRANSFER_P2M_CTRL_DMA)            |
+                                GPDMA_CH_CONFIG_IE                                                |
+                                GPDMA_CH_CONFIG_ITC                                               |
+                                GPDMA_CH_CONFIG_E,
+                                ssp->dma.rx_callback) == -1) {
+      return ARM_DRIVER_ERROR;
+    }
+    if (GPDMA_ChannelConfigure (ssp->dma.tx_ch,
+                               (uint32_t)data,
+                               (uint32_t)&ssp->reg->DR,
+                                num,
+                                GPDMA_CH_CONTROL_SBSIZE(GPDMA_BSIZE_1)                            |
+                                GPDMA_CH_CONTROL_DBSIZE(GPDMA_BSIZE_1)                            |
+                                GPDMA_CH_CONTROL_SWIDTH((ssp->reg->CR0 & SSPx_CR0_DSS) > 7)       |
+                                GPDMA_CH_CONTROL_DWIDTH((ssp->reg->CR0 & SSPx_CR0_DSS) > 7)       |
+                                GPDMA_CH_CONTROL_S                                                |
+                                GPDMA_CH_CONTROL_D                                                |
+                                GPDMA_CH_CONTROL_SI                                               |
+                                GPDMA_CH_CONTROL_I,
+                                GPDMA_CH_CONFIG_DEST_PERI(ssp->dma.tx_peri)                       |
+                                GPDMA_CH_CONFIG_FLOWCNTRL(GPDMA_TRANSFER_M2P_CTRL_DMA)            |
+                                GPDMA_CH_CONFIG_IE                                                |
+                                GPDMA_CH_CONFIG_ITC                                               |
+                                GPDMA_CH_CONFIG_E,
+                                ssp->dma.tx_callback) == -1) {
+      return ARM_DRIVER_ERROR;
+    }
+  } else {
+    ssp->reg->IMSC = SSPx_IMSC_TXIM | SSPx_IMSC_RXIM | SSPx_IMSC_RTIM | SSPx_IMSC_RORIM;
+  }
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t SSPx_Receive (void *data, uint32_t num, SSP_RESOURCES *ssp)
+  \brief       Start receiving data from SSP receiver.
+  \param[out]  data  Pointer to buffer for data to receive from SSP receiver
+  \param[in]   num   Number of data items to receive
+  \param[in]   ssp   Pointer to SSP resources
+  \return      \ref execution_status
+*/
+static int32_t SSPx_Receive (void *data, uint32_t num, SSP_RESOURCES *ssp) {
+  static uint32_t dummy_data;
+
+  if ((data == NULL) || (num == 0U))        { return ARM_DRIVER_ERROR_PARAMETER; }
+  if (!(ssp->info->state & SSP_CONFIGURED)) { return ARM_DRIVER_ERROR; }
+  if (  ssp->info->status.busy)             { return ARM_DRIVER_ERROR_BUSY; }
+  ssp->info->status.busy       = 1U;
+  ssp->info->status.data_lost  = 0U;
+  ssp->info->status.mode_fault = 0U;
+
+  dummy_data        = ssp->xfer->def_val;
+
+  ssp->xfer->rx_buf = (uint8_t *)data;
+  ssp->xfer->tx_buf = NULL;
+
+  ssp->xfer->num    = num;
+  ssp->xfer->rx_cnt = 0U;
+  ssp->xfer->tx_cnt = 0U;
+
+  if (ssp->dma.tx_en && ssp->dma.rx_en) {
+    if (GPDMA_ChannelConfigure (ssp->dma.rx_ch,
+                               (uint32_t)&ssp->reg->DR,
+                               (uint32_t)data,
+                                num,
+                                GPDMA_CH_CONTROL_SBSIZE(GPDMA_BSIZE_1)                            |
+                                GPDMA_CH_CONTROL_DBSIZE(GPDMA_BSIZE_1)                            |
+                                GPDMA_CH_CONTROL_SWIDTH((ssp->reg->CR0 & SSPx_CR0_DSS) > 7)       |
+                                GPDMA_CH_CONTROL_DWIDTH((ssp->reg->CR0 & SSPx_CR0_DSS) > 7)       |
+                                GPDMA_CH_CONTROL_S                                                |
+                                GPDMA_CH_CONTROL_D                                                |
+                                GPDMA_CH_CONTROL_DI                                               |
+                                GPDMA_CH_CONTROL_I,
+                                GPDMA_CH_CONFIG_SRC_PERI(ssp->dma.rx_peri)                        |
+                                GPDMA_CH_CONFIG_FLOWCNTRL(GPDMA_TRANSFER_P2M_CTRL_DMA)            |
+                                GPDMA_CH_CONFIG_IE                                                |
+                                GPDMA_CH_CONFIG_ITC                                               |
+                                GPDMA_CH_CONFIG_E,
+                                ssp->dma.rx_callback) == -1) {
+      return ARM_DRIVER_ERROR;
+    }
+    if (GPDMA_ChannelConfigure (ssp->dma.tx_ch,
+                               (uint32_t)&dummy_data,
+                               (uint32_t)&ssp->reg->DR,
+                                num,
+                                GPDMA_CH_CONTROL_SBSIZE(GPDMA_BSIZE_1)                            |
+                                GPDMA_CH_CONTROL_DBSIZE(GPDMA_BSIZE_1)                            |
+                                GPDMA_CH_CONTROL_SWIDTH((ssp->reg->CR0 & SSPx_CR0_DSS) > 7)       |
+                                GPDMA_CH_CONTROL_DWIDTH((ssp->reg->CR0 & SSPx_CR0_DSS) > 7)       |
+                                GPDMA_CH_CONTROL_S                                                |
+                                GPDMA_CH_CONTROL_D                                                |
+                                GPDMA_CH_CONTROL_I,
+                                GPDMA_CH_CONFIG_DEST_PERI(ssp->dma.tx_peri)                       |
+                                GPDMA_CH_CONFIG_FLOWCNTRL(GPDMA_TRANSFER_M2P_CTRL_DMA)            |
+                                GPDMA_CH_CONFIG_IE                                                |
+                                GPDMA_CH_CONFIG_ITC                                               |
+                                GPDMA_CH_CONFIG_E,
+                                ssp->dma.tx_callback) == -1) {
+      return ARM_DRIVER_ERROR;
+    }
+  } else {
+    ssp->reg->IMSC = SSPx_IMSC_TXIM | SSPx_IMSC_RXIM | SSPx_IMSC_RTIM | SSPx_IMSC_RORIM;
+  }
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t SSPx_Transfer (const void          *data_out,
+                                            void          *data_in,
+                                            uint32_t       num,
+                                            SSP_RESOURCES *ssp)
+  \brief       Start sending/receiving data to/from SSP transmitter/receiver.
+  \param[in]   data_out  Pointer to buffer with data to send to SSP transmitter
+  \param[out]  data_in   Pointer to buffer for data to receive from SSP receiver
+  \param[in]   num       Number of data items to transfer
+  \param[in]   ssp       Pointer to SSP resources
+  \return      \ref execution_status
+*/
+static int32_t SSPx_Transfer (const void *data_out, void *data_in, uint32_t num, SSP_RESOURCES *ssp) {
+
+  if ((data_out == NULL) || (data_in == NULL) || (num == 0U)) { return ARM_DRIVER_ERROR_PARAMETER; }
+  if (!(ssp->info->state & SSP_CONFIGURED))                   { return ARM_DRIVER_ERROR; }
+  if (  ssp->info->status.busy)                               { return ARM_DRIVER_ERROR_BUSY; }
+  ssp->info->status.busy       = 1U;
+  ssp->info->status.data_lost  = 0U;
+  ssp->info->status.mode_fault = 0U;
+
+  ssp->xfer->rx_buf = (uint8_t *)data_in;
+  ssp->xfer->tx_buf = (uint8_t *)data_out;
+
+  ssp->xfer->num    = num;
+  ssp->xfer->rx_cnt = 0U;
+  ssp->xfer->tx_cnt = 0U;
+
+  if (ssp->dma.tx_en && ssp->dma.rx_en) {
+    if (GPDMA_ChannelConfigure (ssp->dma.rx_ch,
+                               (uint32_t)&ssp->reg->DR,
+                               (uint32_t)data_in,
+                                num,
+                                GPDMA_CH_CONTROL_SBSIZE(GPDMA_BSIZE_1)                            |
+                                GPDMA_CH_CONTROL_DBSIZE(GPDMA_BSIZE_1)                            |
+                                GPDMA_CH_CONTROL_SWIDTH((ssp->reg->CR0 & SSPx_CR0_DSS) > 7)       |
+                                GPDMA_CH_CONTROL_DWIDTH((ssp->reg->CR0 & SSPx_CR0_DSS) > 7)       |
+                                GPDMA_CH_CONTROL_S                                                |
+                                GPDMA_CH_CONTROL_D                                                |
+                                GPDMA_CH_CONTROL_DI                                               |
+                                GPDMA_CH_CONTROL_I,
+                                GPDMA_CH_CONFIG_SRC_PERI(ssp->dma.rx_peri)      |
+                                GPDMA_CH_CONFIG_FLOWCNTRL(GPDMA_TRANSFER_P2M_CTRL_DMA)            |
+                                GPDMA_CH_CONFIG_IE                                                |
+                                GPDMA_CH_CONFIG_ITC                                               |
+                                GPDMA_CH_CONFIG_E,
+                                ssp->dma.rx_callback) == -1) {
+      return ARM_DRIVER_ERROR;
+    }
+    if (GPDMA_ChannelConfigure (ssp->dma.tx_ch,
+                               (uint32_t)data_out,
+                               (uint32_t)&ssp->reg->DR,
+                                num,
+                                GPDMA_CH_CONTROL_SBSIZE(GPDMA_BSIZE_1)                            |
+                                GPDMA_CH_CONTROL_DBSIZE(GPDMA_BSIZE_1)                            |
+                                GPDMA_CH_CONTROL_SWIDTH((ssp->reg->CR0 & SSPx_CR0_DSS) > 7)       |
+                                GPDMA_CH_CONTROL_DWIDTH((ssp->reg->CR0 & SSPx_CR0_DSS) > 7)       |
+                                GPDMA_CH_CONTROL_S                                                |
+                                GPDMA_CH_CONTROL_D                                                |
+                                GPDMA_CH_CONTROL_SI                                               |
+                                GPDMA_CH_CONTROL_I,
+                                GPDMA_CH_CONFIG_DEST_PERI(ssp->dma.tx_peri)                       |
+                                GPDMA_CH_CONFIG_FLOWCNTRL(GPDMA_TRANSFER_M2P_CTRL_DMA)            |
+                                GPDMA_CH_CONFIG_IE                                                |
+                                GPDMA_CH_CONFIG_ITC                                               |
+                                GPDMA_CH_CONFIG_E,
+                                ssp->dma.tx_callback) == -1) { 
+      return ARM_DRIVER_ERROR;
+    }
+  } else {
+    ssp->reg->IMSC = SSPx_IMSC_TXIM | SSPx_IMSC_RXIM | SSPx_IMSC_RTIM | SSPx_IMSC_RORIM;
+  }
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          uint32_t SSPx_GetDataCount (SSP_RESOURCES *ssp)
+  \brief       Get transferred data count.
+  \param[in]   ssp  Pointer to SSP resources
+  \return      number of data items transferred
+*/
+static uint32_t SSPx_GetDataCount (SSP_RESOURCES *ssp) {
+  uint32_t cnt;
+
+  if (!(ssp->info->state & SSP_CONFIGURED)) { return 0U; }
+
+  if (ssp->dma.rx_en) {
+    cnt = GPDMA_ChannelGetCount (ssp->dma.rx_ch);
+  } else {
+    cnt = ssp->xfer->rx_cnt;
+  }
+
+  return cnt;
+}
+
+/**
+  \fn          int32_t SSPx_Control (uint32_t control, uint32_t arg, SSP_RESOURCES *ssp)
+  \brief       Control SSP Interface.
+  \param[in]   control  Operation
+  \param[in]   arg      Argument of operation (optional)
+  \param[in]   ssp      Pointer to SSP resources
+  \return      common \ref execution_status and driver specific \ref spi_execution_status
+*/
+static int32_t SSPx_Control (uint32_t control, uint32_t arg, SSP_RESOURCES *ssp) {
+  uint32_t cpsr, scr, bps = 0U, clk, data_bits;
+  uint32_t best_cpsr = 2U, best_scr = 0U, best_bps = 0U;
+
+  if (!(ssp->info->state & SSP_POWERED)) { return ARM_DRIVER_ERROR; }
+
+  if ((control & ARM_SPI_CONTROL_Msk) == ARM_SPI_ABORT_TRANSFER) {
+    ssp->reg->CR1 &= ~SSPx_CR1_SSE;         // Disable SSP
+    ssp->reg->IMSC =  0U;                   // Disable interrupts
+    if (ssp->info->status.busy) {
+      // If DMA mode - disable DMA channel
+      if (ssp->dma.tx_en) { GPDMA_ChannelDisable (ssp->dma.tx_ch); }
+      // If DMA mode - disable DMA channel
+      if (ssp->dma.rx_en) { GPDMA_ChannelDisable (ssp->dma.rx_ch); }
+    }
+    memset(ssp->xfer, 0, sizeof(SSP_TRANSFER_INFO));
+    ssp->info->status.busy = 0U;
+    ssp->reg->CR1 |=  SSPx_CR1_SSE;         // Enable  SSP
+    return ARM_DRIVER_OK;
+  }  
+
+  if (ssp->info->status.busy)            { return ARM_DRIVER_ERROR_BUSY; }
+
+  switch (control & ARM_SPI_CONTROL_Msk) {
+    default:
+      return ARM_DRIVER_ERROR_UNSUPPORTED;
+
+    case ARM_SPI_MODE_INACTIVE:             // SPI Inactive
+      ssp->reg->CR1    &= ~SSPx_CR1_SSE;    // Disable SSP
+      ssp->reg->IMSC    =  0U;              // Disable interrupts
+      ssp->info->mode  &= ~ARM_SPI_CONTROL_Msk;
+      ssp->info->mode  |=  ARM_SPI_MODE_INACTIVE;
+      ssp->info->state &= ~SSP_CONFIGURED;
+      return ARM_DRIVER_OK;
+
+    case ARM_SPI_MODE_MASTER:               // SPI Master (Output on MOSI, Input on MISO); arg = Bus Speed in bps
+      ssp->reg->CR1    &= ~SSPx_CR1_SSE;    // Disable SSP
+      ssp->reg->IMSC    =  0U;              // Disable interrupts
+      ssp->reg->CR1    &= ~SSPx_CR1_MS;     // Set master mode
+      ssp->info->mode  &= ~ARM_SPI_CONTROL_Msk;
+      ssp->info->mode  |=  ARM_SPI_MODE_MASTER;
+      ssp->info->state |=  SSP_CONFIGURED;
+      ssp->reg->CR1    |=  SSPx_CR1_SSE;    // Enable  SSP
+      goto set_speed;
+
+    case ARM_SPI_MODE_SLAVE:                // SPI Slave  (Output on MISO, Input on MOSI)
+      ssp->reg->CR1    &= ~SSPx_CR1_SSE;    // Disable SSP
+      ssp->reg->CR1    |=  SSPx_CR1_MS;     // Set slave mode
+      ssp->reg->IMSC    =  SSPx_IMSC_RORIM; // Enable receive overrun interrupt
+      ssp->info->mode  &= ~ARM_SPI_CONTROL_Msk;
+      ssp->info->mode  |=  ARM_SPI_MODE_SLAVE;
+      ssp->info->state |=  SSP_CONFIGURED;
+      ssp->reg->CR1    |=  SSPx_CR1_SSE;    // Enable  SSP
+      break;
+
+    case ARM_SPI_MODE_MASTER_SIMPLEX:       // SPI Master (Output/Input on MOSI); arg = Bus Speed in bps
+    case ARM_SPI_MODE_SLAVE_SIMPLEX:        // SPI Slave  (Output/Input on MISO)
+      return ARM_SPI_ERROR_MODE;
+
+    case ARM_SPI_SET_BUS_SPEED:             // Set Bus Speed in bps; arg = value
+set_speed:
+      if (arg == 0U) {
+        return ARM_DRIVER_ERROR;
+      }
+
+      clk = GetClockFreq(CLK_SRC_PLL1) << 4;
+      arg = (arg << 4);
+      for (cpsr = 2U; cpsr < 255U; cpsr+= 2U) {// Loop through clock prescaler
+        for (scr = 0U; scr < 256U; scr++) {    // Loop through bit prescaler
+          bps = clk  / (cpsr * (scr + 1U));
+          if (arg == bps) {
+            best_bps  = bps;
+            best_cpsr = cpsr;
+            best_scr  = scr;
+            goto found_best;
+          } else {
+            if (arg > bps) {
+              if ((arg - best_bps) > (arg - bps)) {
+                best_bps  = bps;
+                best_cpsr = cpsr;
+                best_scr  = scr;
+              }
+            }
+          }
+        }
+      }
+      if (best_bps == 0U) {
+        return ARM_DRIVER_ERROR;
+      }
+found_best:
+      ssp->reg->CPSR =  best_cpsr & SSPx_CPSR_CPSDVSR;
+      ssp->reg->CR0 &= ~SSPx_CR0_SCR;
+      ssp->reg->CR0 |= ((best_scr << 8) & SSPx_CR0_SCR);
+      if ((control & ARM_SPI_CONTROL_Msk) == ARM_SPI_SET_BUS_SPEED) {
+        return ARM_DRIVER_OK;
+      }
+      break;
+
+    case ARM_SPI_GET_BUS_SPEED:             // Get Bus Speed in bps
+      return (GetClockFreq(CLK_SRC_PLL1) / ((ssp->reg->CPSR & SSPx_CPSR_CPSDVSR) * (((ssp->reg->CR0 & SSPx_CR0_SCR) >> 8) + 1U)));
+
+    case ARM_SPI_SET_DEFAULT_TX_VALUE:      // Set default Transmit value; arg = value
+      ssp->xfer->def_val = (uint16_t)(arg & 0xFFFF);
+      return ARM_DRIVER_OK;
+
+    case ARM_SPI_CONTROL_SS:                // Control Slave Select; arg = 0:inactive, 1:active 
+      if (((ssp->info->mode & ARM_SPI_CONTROL_Msk)        != ARM_SPI_MODE_MASTER)  ||
+          ((ssp->info->mode & ARM_SPI_SS_MASTER_MODE_Msk) != ARM_SPI_SS_MASTER_SW)) {
+        return ARM_DRIVER_ERROR;
+      }
+      if (ssp->pin.ssel == NULL) {
+        return ARM_DRIVER_ERROR;
+      }
+      if (arg == ARM_SPI_SS_INACTIVE) {
+        GPIO_PinWrite  (ssp->pin.gpio_ssel->port, ssp->pin.gpio_ssel->num, 1U);
+      } else {
+        GPIO_PinWrite  (ssp->pin.gpio_ssel->port, ssp->pin.gpio_ssel->num, 0U);
+      }
+      return ARM_DRIVER_OK;
+  }
+
+  if ((ssp->info->mode & ARM_SPI_CONTROL_Msk) == ARM_SPI_MODE_MASTER) {
+    switch (control & ARM_SPI_SS_MASTER_MODE_Msk) {
+      case ARM_SPI_SS_MASTER_UNUSED:        // SPI Slave Select when Master: Not used (default)
+        if (ssp->pin.ssel != NULL) { SCU_PinConfigure (ssp->pin.ssel->port, ssp->pin.ssel->num, 0U); }
+        ssp->info->mode  &= ~ARM_SPI_SS_MASTER_MODE_Msk;
+        ssp->info->mode  |=  ARM_SPI_SS_MASTER_UNUSED;
+        break;
+
+      case ARM_SPI_SS_MASTER_HW_INPUT:      // SPI Slave Select when Master: Hardware monitored Input
+        ssp->info->mode  &= ~ARM_SPI_SS_MASTER_MODE_Msk;
+        return ARM_SPI_ERROR_SS_MODE;
+
+      case ARM_SPI_SS_MASTER_SW:            // SPI Slave Select when Master: Software controlled
+        ssp->info->mode  &= ~ARM_SPI_SS_MASTER_MODE_Msk;
+        if (ssp->pin.ssel != NULL) {
+          SCU_PinConfigure (ssp->pin.ssel->port, ssp->pin.ssel->num, ssp->pin.gpio_ssel_af               |
+                                                                     SCU_PIN_CFG_PULLUP_DIS              |
+                                                                     SCU_PIN_CFG_HIGH_SPEED_SLEW_RATE_EN );
+          GPIO_SetDir      (ssp->pin.gpio_ssel->port, ssp->pin.gpio_ssel->num, GPIO_DIR_OUTPUT);
+          GPIO_PinWrite    (ssp->pin.gpio_ssel->port, ssp->pin.gpio_ssel->num, 1);
+          ssp->info->mode |= ARM_SPI_SS_MASTER_SW;
+        } else {
+          return ARM_SPI_ERROR_SS_MODE;
+        }
+        break;
+
+      case ARM_SPI_SS_MASTER_HW_OUTPUT:     // SPI Slave Select when Master: Hardware controlled Output
+        ssp->info->mode  &= ~ARM_SPI_SS_MASTER_MODE_Msk;
+        if (ssp->pin.ssel != NULL) {
+          SCU_PinConfigure (ssp->pin.ssel->port, ssp->pin.ssel->num, ssp->pin.ssel->config_val           |
+                                                                     SCU_PIN_CFG_PULLUP_DIS              |
+                                                                     SCU_PIN_CFG_HIGH_SPEED_SLEW_RATE_EN );
+          ssp->info->mode |= ARM_SPI_SS_MASTER_HW_OUTPUT;
+        } else {
+          return ARM_SPI_ERROR_SS_MODE;
+        }
+      default:
+        break;
+    }
+  }
+
+  if ((ssp->info->mode & ARM_SPI_CONTROL_Msk) ==  ARM_SPI_MODE_SLAVE) {
+    switch (control & ARM_SPI_SS_SLAVE_MODE_Msk) {
+      case ARM_SPI_SS_SLAVE_HW:             // SPI Slave Select when Slave: Hardware monitored (default)
+        ssp->info->mode  &= ~ARM_SPI_SS_SLAVE_MODE_Msk;
+        if (ssp->pin.ssel != NULL) {
+          SCU_PinConfigure (ssp->pin.ssel->port, ssp->pin.ssel->num, ssp->pin.ssel->config_val           |
+                                                                     SCU_PIN_CFG_PULLUP_DIS              |
+                                                                     SCU_PIN_CFG_HIGH_SPEED_SLEW_RATE_EN |
+                                                                     SCU_PIN_CFG_INPUT_BUFFER_EN         |
+                                                                     SCU_PIN_CFG_INPUT_FILTER_DIS        );
+          ssp->info->mode |= ARM_SPI_SS_SLAVE_HW;
+        } else {
+          return ARM_SPI_ERROR_SS_MODE;
+        }
+        break;
+
+      case ARM_SPI_SS_SLAVE_SW:             // SPI Slave Select when Slave: Software controlled
+        ssp->info->mode  &= ~ARM_SPI_SS_SLAVE_MODE_Msk;
+        return ARM_SPI_ERROR_SS_MODE;
+      default: return ARM_SPI_ERROR_SS_MODE;
+    }
+  }
+
+  // Configure Frame Format
+  switch (control & ARM_SPI_FRAME_FORMAT_Msk) {
+    case ARM_SPI_CPOL0_CPHA0:
+      ssp->reg->CR0 &=  ~SSPx_CR0_FRF;
+      ssp->reg->CR0 &= ~(SSPx_CR0_CPOL | SSPx_CR0_CPHA);
+      break;
+
+    case ARM_SPI_CPOL0_CPHA1:
+      ssp->reg->CR0 &=  ~SSPx_CR0_FRF;
+      ssp->reg->CR0 &=  ~SSPx_CR0_CPOL;
+      ssp->reg->CR0 |=   SSPx_CR0_CPHA;
+      break;
+
+    case ARM_SPI_CPOL1_CPHA0:
+      ssp->reg->CR0 &=  ~SSPx_CR0_FRF;
+      ssp->reg->CR0 |=   SSPx_CR0_CPOL;
+      ssp->reg->CR0 &=  ~SSPx_CR0_CPHA;
+      break;
+
+    case ARM_SPI_CPOL1_CPHA1:
+      ssp->reg->CR0 &=  ~SSPx_CR0_FRF;
+      ssp->reg->CR0 |=  (SSPx_CR0_CPOL | SSPx_CR0_CPHA);
+      break;
+
+    case ARM_SPI_TI_SSI:
+      ssp->reg->CR0  =  (ssp->reg->CR0 & (~SSPx_CR0_FRF)) | (1U << 4);
+      break;
+
+    case ARM_SPI_MICROWIRE:
+      ssp->reg->CR0  =  (ssp->reg->CR0 & (~SSPx_CR0_FRF)) | (2U << 4);
+      break;
+
+    default:
+      return ARM_SPI_ERROR_FRAME_FORMAT;
+  }
+
+  // Configure Number of Data Bits
+  data_bits = ((control & ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos);
+  if ((data_bits >= 4U) && (data_bits <= 16U)) {
+    ssp->reg->CR0 = (ssp->reg->CR0 & (~SSPx_CR0_DSS)) | ((data_bits - 1U) << 0);
+  } else {
+    return ARM_SPI_ERROR_DATA_BITS;
+  }
+
+  // Configure Bit Order
+  if ((control & ARM_SPI_BIT_ORDER_Msk) == ARM_SPI_LSB_MSB) {
+    return ARM_SPI_ERROR_BIT_ORDER;
+  }
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          ARM_SPI_STATUS SSPx_GetStatus (SSP_RESOURCES *ssp)
+  \brief       Get SSP status.
+  \param[in]   ssp  Pointer to SSP resources
+  \return      SPI status \ref ARM_SPI_STATUS
+*/
+static ARM_SPI_STATUS SSPx_GetStatus (SSP_RESOURCES *ssp) {
+  ARM_SPI_STATUS status;
+
+  status.busy       = ssp->info->status.busy;
+  status.data_lost  = ssp->info->status.data_lost;
+  status.mode_fault = ssp->info->status.mode_fault;
+
+  return (status);
+}
+
+/**
+  \fn          void SSPx_GPDMA_Tx_SignalEvent (uint32_t event, SSP_RESOURCES *ssp)
+  \brief       SSP GPDMA Tx Event handler.
+  \param[in]   event GPDMA Tx Event
+  \param[in]   ssp   Pointer to SSP resources
+*/
+void SSPx_GPDMA_Tx_SignalEvent (uint32_t event, SSP_RESOURCES *ssp) {
+
+  switch (event) {
+    case GPDMA_EVENT_TERMINAL_COUNT_REQUEST:
+      ssp->xfer->tx_cnt = ssp->xfer->num;
+      break;
+    case GPDMA_EVENT_ERROR:
+    default:
+      break;
+  }
+}
+
+/**
+  \fn          void SSPx_GPDMA_Rx_SignalEvent (uint32_t event, SSP_RESOURCES *ssp)
+  \brief       SSP GPDMA Rx Event handler.
+  \param[in]   event GPDMA Rx Event
+  \param[in]   ssp   Pointer to SSP resources
+*/
+void SSPx_GPDMA_Rx_SignalEvent (uint32_t event, SSP_RESOURCES *ssp) {
+
+  switch (event) {
+    case GPDMA_EVENT_TERMINAL_COUNT_REQUEST:
+      ssp->xfer->rx_cnt = ssp->xfer->num;
+      ssp->info->status.busy = 0U;
+      if (ssp->info->cb_event) {
+        ssp->info->cb_event(ARM_SPI_EVENT_TRANSFER_COMPLETE);
+      }
+      break;
+    case GPDMA_EVENT_ERROR:
+    default:
+      break;
+  }
+}
+
+/**
+  \fn          void SSPx_IRQHandler (SSP_RESOURCES *ssp)
+  \brief       SSP Interrupt handler.
+  \param[in]   ssp  Pointer to SSP resources
+*/
+static void SSPx_IRQHandler (SSP_RESOURCES *ssp) {
+  uint16_t data;
+  uint32_t mis;
+
+  mis = ssp->reg->MIS;
+  ssp->reg->ICR = mis & 3U;
+
+                                                  // Handle transfer
+  if ((ssp->reg->SR & SSPx_SR_TNF) && (ssp->xfer->num > ssp->xfer->tx_cnt)) {
+    if (ssp->xfer->tx_buf) {                      // If data available
+      data = *(ssp->xfer->tx_buf++);
+      if ((ssp->reg->CR0 & SSPx_CR0_DSS) > 7U) {  // If 9..16-bit data frame format
+        data |= *(ssp->xfer->tx_buf++) << 8;
+      }
+    } else {                                      // If default data send
+      data = ssp->xfer->def_val;
+    }
+    ssp->reg->DR = data;                          // Activate send
+    ssp->xfer->tx_cnt++;
+  }
+
+  if (ssp->reg->SR & SSPx_SR_RNE) {
+    data = ssp->reg->DR;                          // Read data
+    if (ssp->xfer->num > ssp->xfer->rx_cnt) {
+      if (ssp->xfer->rx_buf) {
+        *(ssp->xfer->rx_buf++) = (uint8_t)data;    // Put data into buffer
+        if ((ssp->reg->CR0 & SSPx_CR0_DSS) > 7U) { // If 9..16-bit data frame format
+          *(ssp->xfer->rx_buf++) = (uint8_t)(data >> 8);
+        }
+      }
+      ssp->xfer->rx_cnt++;
+      if (ssp->xfer->rx_cnt == ssp->xfer->num) {  // If all data received
+        ssp->reg->IMSC   &= ~(SSPx_IMSC_TXIM | SSPx_IMSC_RXIM | SSPx_IMSC_RTIM | SSPx_IMSC_RORIM);
+        ssp->info->status.busy = 0U;
+        if (ssp->info->cb_event) { ssp->info->cb_event(ARM_SPI_EVENT_TRANSFER_COMPLETE); }
+      }
+    }
+  }
+
+  if (mis & SSPx_MIS_RORMIS) {                    // Handle errors
+    // Overrun flag is set
+    ssp->info->status.data_lost = 1U;
+    if (ssp->info->cb_event) { ssp->info->cb_event(ARM_SPI_EVENT_DATA_LOST); }
+  }
+}
+
+
+#if (RTE_SSP0)
+static int32_t        SSP0_Initialize          (ARM_SPI_SignalEvent_t pSignalEvent)                { return SSPx_Initialize   (pSignalEvent, &SSP0_Resources); }
+static int32_t        SSP0_Uninitialize        (void)                                              { return SSPx_Uninitialize (&SSP0_Resources); }
+static int32_t        SSP0_PowerControl        (ARM_POWER_STATE state)                             { return SSPx_PowerControl (state, &SSP0_Resources); }
+static int32_t        SSP0_Send                (const void *data, uint32_t num)                    { return SSPx_Send         (data, num, &SSP0_Resources); }
+static int32_t        SSP0_Receive             (void *data, uint32_t num)                          { return SSPx_Receive      (data, num, &SSP0_Resources); }
+static int32_t        SSP0_Transfer            (const void *data_out, void *data_in, uint32_t num) { return SSPx_Transfer     (data_out, data_in, num, &SSP0_Resources); }
+static uint32_t       SSP0_GetDataCount        (void)                                              { return SSPx_GetDataCount (&SSP0_Resources); }
+static int32_t        SSP0_Control             (uint32_t control, uint32_t arg)                    { return SSPx_Control      (control, arg, &SSP0_Resources); }
+static ARM_SPI_STATUS SSP0_GetStatus           (void)                                              { return SSPx_GetStatus    (&SSP0_Resources); }
+       void           SSP0_GPDMA_Tx_SignalEvent(uint32_t event)                                    { SSPx_GPDMA_Tx_SignalEvent(event, &SSP0_Resources); }
+       void           SSP0_GPDMA_Rx_SignalEvent(uint32_t event)                                    { SSPx_GPDMA_Rx_SignalEvent(event, &SSP0_Resources); }
+       void           SSP0_IRQHandler          (void)                                              { SSPx_IRQHandler          (&SSP0_Resources); }
+
+// SPI0 Driver Control Block
+ARM_DRIVER_SPI Driver_SPI0 = {
+  SSP_GetVersion,
+  SSP_GetCapabilities,
+  SSP0_Initialize,
+  SSP0_Uninitialize,
+  SSP0_PowerControl,
+  SSP0_Send,
+  SSP0_Receive,
+  SSP0_Transfer,
+  SSP0_GetDataCount,
+  SSP0_Control,
+  SSP0_GetStatus
+};
+#endif
+
+
+#if (RTE_SSP1)
+static int32_t        SSP1_Initialize          (ARM_SPI_SignalEvent_t pSignalEvent)                { return SSPx_Initialize   (pSignalEvent, &SSP1_Resources); }
+static int32_t        SSP1_Uninitialize        (void)                                              { return SSPx_Uninitialize (&SSP1_Resources); }
+static int32_t        SSP1_PowerControl        (ARM_POWER_STATE state)                             { return SSPx_PowerControl (state, &SSP1_Resources); }
+static int32_t        SSP1_Send                (const void *data, uint32_t num)                    { return SSPx_Send         (data, num, &SSP1_Resources); }
+static int32_t        SSP1_Receive             (void *data, uint32_t num)                          { return SSPx_Receive      (data, num, &SSP1_Resources); }
+static int32_t        SSP1_Transfer            (const void *data_out, void *data_in, uint32_t num) { return SSPx_Transfer     (data_out, data_in, num, &SSP1_Resources); }
+static uint32_t       SSP1_GetDataCount        (void)                                              { return SSPx_GetDataCount (&SSP1_Resources); }
+static int32_t        SSP1_Control             (uint32_t control, uint32_t arg)                    { return SSPx_Control      (control, arg, &SSP1_Resources); }
+static ARM_SPI_STATUS SSP1_GetStatus           (void)                                              { return SSPx_GetStatus    (&SSP1_Resources); }
+       void           SSP1_GPDMA_Tx_SignalEvent(uint32_t event)                                    { SSPx_GPDMA_Tx_SignalEvent(event, &SSP1_Resources); }
+       void           SSP1_GPDMA_Rx_SignalEvent(uint32_t event)                                    { SSPx_GPDMA_Rx_SignalEvent(event, &SSP1_Resources); }
+       void           SSP1_IRQHandler          (void)                                              { SSPx_IRQHandler          (&SSP1_Resources); }
+
+// SPI1 Driver Control Block
+ARM_DRIVER_SPI Driver_SPI1 = {
+  SSP_GetVersion,
+  SSP_GetCapabilities,
+  SSP1_Initialize,
+  SSP1_Uninitialize,
+  SSP1_PowerControl,
+  SSP1_Send,
+  SSP1_Receive,
+  SSP1_Transfer,
+  SSP1_GetDataCount,
+  SSP1_Control,
+  SSP1_GetStatus
+};
+#endif

CMSIS/Pack/Example/CMSIS_Driver/SSP_LPC18xx.h

@@ -0,0 +1,181 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        02. March 2016
+ * $Revision:    V2.2
+ *
+ * Project:      SSP Driver Definitions for NXP LPC18xx
+ * -------------------------------------------------------------------------- */
+
+#ifndef __SSP_LPC18XX_H
+#define __SSP_LPC18XX_H
+
+#include "LPC18xx.h"
+#include "SCU_LPC18xx.h"
+#include "GPIO_LPC18xx.h"
+#include "GPDMA_LPC18xx.h"
+
+#include "Driver_SPI.h"
+
+/* SSP Register Interface Definitions */
+#define CGU_BASE_SSPx_CLK_PD              (0x01 << 0)       /*!< CGU BASE_SSPx_CLK: PD Mask              */
+#define CGU_BASE_SSPx_CLK_AUTOBLOCK       (0x01 << 11)      /*!< CGU BASE_SSPx_CLK: AUTOBLOCK Mask       */
+#define CGU_BASE_SSPx_CLK_CLK_SEL         (0x1F << 24)      /*!< CGU BASE_SSPx_CLK: CLK_SEL Mask         */
+#define CCU1_CLK_M3_SSPx_CFG_RUN          (0x01 << 0)       /*!< CCU1 CLK_M3_SSPx_CFG: RUN Mask          */
+#define CCU1_CLK_M3_SSPx_CFG_AUTO         (0x01 << 1)       /*!< CCU1 CLK_M3_SSPx_CFG: AUTO Mask         */
+#define CCU1_CLK_M3_SSPx_CFG_WAKEUP       (0x01 << 2)       /*!< CCU1 CLK_M3_SSPx_CFG: WAKEUP Mask       */
+#define CCU1_CLK_M3_SSPx_STAT_RUN         (0x01 << 0)       /*!< CCU1 CLK_M3_SSPx_STAT: RUN Mask         */
+#define CCU1_CLK_M3_SSPx_STAT_AUTO        (0x01 << 1)       /*!< CCU1 CLK_M3_SSPx_STAT: AUTO Mask        */
+#define CCU1_CLK_M3_SSPx_STAT_WAKEUP      (0x01 << 2)       /*!< CCU1 CLK_M3_SSPx_STAT: WAKEUP Mask      */
+#define CCU2_BASE_STAT_BASE_SSP1_CLK      (0x01 << 5)       /*!< CCU2 BASE_STAT: BASE_SSP1_CLK Mask      */
+#define CCU2_BASE_STAT_BASE_SSP0_CLK      (0x01 << 6)       /*!< CCU2 BASE_STAT: BASE_SSP0_CLK Mask      */
+#define CCU2_CLK_APBn_SSPx_CFG_RUN        (0x01 << 0)       /*!< CCU2 CLK_APBn_SSPx_CFG: RUN Mask        */
+#define CCU2_CLK_APBn_SSPx_CFG_AUTO       (0x01 << 1)       /*!< CCU2 CLK_APBn_SSPx_CFG: AUTO Mask       */
+#define CCU2_CLK_APBn_SSPx_CFG_WAKEUP     (0x01 << 2)       /*!< CCU2 CLK_APBn_SSPx_CFG: WAKEUP Mask     */
+#define CCU2_CLK_APBn_SSPx_STAT_RUN       (0x01 << 0)       /*!< CCU2 CLK_APBn_SSPx_STAT: RUN Mask       */
+#define CCU2_CLK_APBn_SSPx_STAT_AUTO      (0x01 << 1)       /*!< CCU2 CLK_APBn_SSPx_STAT: AUTO Mask      */
+#define CCU2_CLK_APBn_SSPx_STAT_WAKEUP    (0x01 << 2)       /*!< CCU2 CLK_APBn_SSPx_STAT: WAKEUP Mask    */
+#define RGU_RESET_CTRL1_SSP0_RST          (0x01 << 18)      /*!< RGU RESET_CTRL1: SSP0_RST Mask          */
+#define RGU_RESET_CTRL1_SSP1_RST          (0x01 << 19)      /*!< RGU RESET_CTRL1: SSP1_RST Mask          */
+#define RGU_RESET_STATUS3_SSP0_RST        (0x03 << 4)       /*!< RGU RESET_STATUS3: SSP0_RST Mask        */
+#define RGU_RESET_STATUS3_SSP1_RST        (0x03 << 6)       /*!< RGU RESET_STATUS3: SSP1_RST Mask        */
+#define RGU_RESET_ACTIVE_STATUS1_SSP0_RST (0x01 << 18)      /*!< RGU RESET_ACTIVE_STATUS1: SSP0_RST Mask */
+#define RGU_RESET_ACTIVE_STATUS1_SSP1_RST (0x01 << 19)      /*!< RGU RESET_ACTIVE_STATUS1: SSP1_RST Mask */
+
+#define SSPx_CR0_DSS                      (0x0F << 0)       /*!< SSPx CR0: DSS Mask                      */
+#define SSPx_CR0_FRF                      (0x03 << 4)       /*!< SSPx CR0: FRF Mask                      */
+#define SSPx_CR0_CPOL                     (0x01 << 6)       /*!< SSPx CR0: CPOL Mask                     */
+#define SSPx_CR0_CPHA                     (0x01 << 7)       /*!< SSPx CR0: CPHA Mask                     */
+#define SSPx_CR0_SCR                      (0xFF << 8)       /*!< SSPx CR0: SCR Mask                      */
+#define SSPx_CR1_LBM                      (0x01 << 0)       /*!< SSPx CR1: LBM Mask                      */
+#define SSPx_CR1_SSE                      (0x01 << 1)       /*!< SSPx CR1: SSE Mask                      */
+#define SSPx_CR1_MS                       (0x01 << 2)       /*!< SSPx CR1: MS Mask                       */
+#define SSPx_CR1_SOD                      (0x01 << 3)       /*!< SSPx CR1: SOD Mask                      */
+#define SSPx_DR_DATA                      (0xFFFF<<0)       /*!< SSPx DR: DATA Mask                      */
+#define SSPx_SR_TFE                       (0x01 << 0)       /*!< SSPx SR: TFE Mask                       */
+#define SSPx_SR_TNF                       (0x01 << 1)       /*!< SSPx SR: TNF Mask                       */
+#define SSPx_SR_RNE                       (0x01 << 2)       /*!< SSPx SR: RNE Mask                       */
+#define SSPx_SR_RFF                       (0x01 << 3)       /*!< SSPx SR: RFF Mask                       */
+#define SSPx_SR_BSY                       (0x01 << 4)       /*!< SSPx SR: BSY Mask                       */
+#define SSPx_CPSR_CPSDVSR                 (0xFF << 0)       /*!< SSPx CPSR: CPSDVSR Mask                 */
+#define SSPx_IMSC_RORIM                   (0x01 << 0)       /*!< SSPx IMSC: RORIM Mask                   */
+#define SSPx_IMSC_RTIM                    (0x01 << 1)       /*!< SSPx IMSC: RTIM Mask                    */
+#define SSPx_IMSC_RXIM                    (0x01 << 2)       /*!< SSPx IMSC: RXIM Mask                    */
+#define SSPx_IMSC_TXIM                    (0x01 << 3)       /*!< SSPx IMSC: TXIM Mask                    */
+#define SSPx_RIS_RORRIS                   (0x01 << 0)       /*!< SSPx RIS: RORRIS Mask                   */
+#define SSPx_RIS_RTRIS                    (0x01 << 1)       /*!< SSPx RIS: RTRIS Mask                    */
+#define SSPx_RIS_RXRIS                    (0x01 << 2)       /*!< SSPx RIS: RXRIS Mask                    */
+#define SSPx_RIS_TXRIS                    (0x01 << 3)       /*!< SSPx RIS: TXRIS Mask                    */
+#define SSPx_MIS_RORMIS                   (0x01 << 0)       /*!< SSPx MIS: RORMIS Mask                   */
+#define SSPx_MIS_RTMIS                    (0x01 << 1)       /*!< SSPx MIS: RTMIS Mask                    */
+#define SSPx_MIS_RXMIS                    (0x01 << 2)       /*!< SSPx MIS: RXMIS Mask                    */
+#define SSPx_MIS_TXMIS                    (0x01 << 3)       /*!< SSPx MIS: TXMIS Mask                    */
+#define SSPx_ICR_RORIC                    (0x01 << 0)       /*!< SSPx ICR: RORIC Mask                    */
+#define SSPx_ICR_RTIC                     (0x01 << 1)       /*!< SSPx ICR: RTIC Mask                     */
+#define SSPx_DMACR_RXDMAE                 (0x01 << 0)       /*!< SSPx DMACR: RXDMAE Mask                 */
+#define SSPx_DMACR_TXDMAE                 (0x01 << 1)       /*!< SSPx DMACR: TXDMAE Mask                 */
+
+#define CLK_SRC_PLL1                       0x09             // SSP clock source
+
+/* Current driver status flag definition */
+#define SSP_INITIALIZED                   (1    << 0)       // SSP initialized
+#define SSP_POWERED                       (1    << 1)       // SSP powered on
+#define SSP_CONFIGURED                    (1    << 2)       // SSP configured
+#define SSP_DATA_LOST                     (1    << 3)       // SSP data lost occurred
+#define SSP_MODE_FAULT                    (1    << 4)       // SSP mode fault occurred
+
+/* SSP Pins Configuration */
+typedef const struct _SSP_PINS {
+  PIN_ID              *sck;              // SCK pin
+  PIN_ID              *miso;             // MISO pin
+  PIN_ID              *mosi;             // MOSI pin
+  PIN_ID              *ssel;             // SSEL pin
+  GPIO_ID             *gpio_ssel;        // SSEL gpio
+  uint8_t              gpio_ssel_af;     // SSEL gpio alternate function
+} SSP_PINS;
+
+/* Clocks Configuration */
+typedef const struct _SSP_CLOCK {
+  uint32_t              reg_cfg_val;    // SSP register interface clock configuration register value
+  volatile uint32_t    *reg_cfg;        // SSP register interface clock configuration register
+  uint32_t              peri_cfg_val;   // SSP peripheral clock configuration register value
+  volatile uint32_t    *peri_cfg;       // SSP peripheral clock configuration register
+  uint32_t              peri_stat_val;  // SSP peripheral clock status register value
+  const volatile uint32_t *peri_stat;   // SSP peripheral clock status register
+} SSP_CLOCKS;
+
+/* Reset Configuration */
+typedef const struct _SSP_RESET {
+  uint32_t              reg_cfg_val;    // SSP register interface clock configuration register value
+  volatile uint32_t    *reg_cfg;        // SSP register interface clock configuration register
+  uint32_t              reg_stat_val;   // SSP peripheral clock status register value
+  const volatile uint32_t *reg_stat;    // SSP peripheral clock status register
+} SSP_RESET;
+
+/* DMA Configuration */
+typedef const struct _SSP_DMA {
+  uint8_t               tx_en;          // Transmit channel enabled
+  uint8_t               tx_ch;          // Transmit channel number
+  uint8_t               tx_peri;        // Transmit peripheral
+  uint8_t               tx_peri_sel;    // Transmit peripheral mux selection
+  void                (*tx_callback)(uint32_t event); // Transmit callback
+  uint8_t               rx_en;          // Receive channel enabled
+  uint8_t               rx_ch;          // Receive channel number
+  uint8_t               rx_peri;        // Receive peripheral
+  uint8_t               rx_peri_sel;    // Receive peripheral mux selection
+  void                (*rx_callback)(uint32_t event); // Receive callback
+} SSP_DMA;
+
+/* SSP status */
+typedef struct _SSP_STATUS {
+  uint8_t busy;                         // Transmitter/Receiver busy flag
+  uint8_t data_lost;                    // Data lost: Receive overflow / Transmit underflow (cleared on start of transfer operation)
+  uint8_t mode_fault;                   // Mode fault detected; optional (cleared on start of transfer operation)
+} SSP_STATUS;
+
+/* SSP Information (Run-time) */
+typedef struct _SSP_INFO {
+  ARM_SPI_SignalEvent_t cb_event;       // Event Callback
+  SSP_STATUS            status;         // Status flags
+  uint8_t               state;          // Current SSP state
+  uint32_t              mode;           // Current SSP mode
+} SSP_INFO;
+
+/* SSP Transfer Information (Run-Time) */
+typedef struct _SSP_TRANSFER_INFO {
+  uint32_t              num;            // Total number of transfers
+  uint8_t              *rx_buf;         // Pointer to in data buffer
+  uint8_t              *tx_buf;         // Pointer to out data buffer
+  uint32_t              rx_cnt;         // Number of data received
+  uint32_t              tx_cnt;         // Number of data sent
+  uint32_t              dump_val;       // Variable for dumping DMA data
+  uint16_t              def_val;        // Default transfer value
+} SSP_TRANSFER_INFO;
+
+/* SSP Resources */
+typedef struct {
+  LPC_SSPn_Type        *reg;            // SSP peripheral register interface
+  SSP_PINS              pin;            // SSP pins configuration
+  SSP_CLOCKS            clk;            // SSP clocks configuration
+  SSP_RESET             rst;            // SSP reset configuration
+  SSP_DMA               dma;            // SSP DMA configuration
+  IRQn_Type             irq_num;        // SSP IRQ number
+  SSP_INFO             *info;           // SSP Run-time information
+  SSP_TRANSFER_INFO    *xfer;           // SSP transfer information
+} const SSP_RESOURCES;
+
+#endif /* __SSP_LPC18XX_H */

CMSIS/Pack/Example/CMSIS_Driver/USART_LPC18xx.c

@@ -0,0 +1,2629 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        02. March 2016
+ * $Revision:    V2.9
+ *
+ * Driver:       Driver_USART0, Driver_USART1, Driver_USART2, Driver_USART3
+ * Configured:   via RTE_Device.h configuration file
+ * Project:      USART Driver for NXP LPC18xx
+ * --------------------------------------------------------------------------
+ * Use the following configuration settings in the middleware component
+ * to connect to this driver.
+ *
+ *   Configuration Setting                   Value   UART Interface
+ *   ---------------------                   -----   --------------
+ *   Connect to hardware via Driver_USART# = 0       use USART0
+ *   Connect to hardware via Driver_USART# = 1       use UART1
+ *   Connect to hardware via Driver_USART# = 2       use USART2
+ *   Connect to hardware via Driver_USART# = 3       use USART3
+ * -------------------------------------------------------------------------- */
+
+/* History:
+ *  Version 2.9
+ *    - Driver update to work with GPDMA_LPC18xx ver.: 1.3
+ *  Version 2.8
+ *    - Corrected PowerControl function for conditional Power full (driver must be initialized)
+ *  Version 2.7
+ *    - PowerControl for Power OFF and Uninitialize functions made unconditional.
+ *    - Corrected status bit-field handling, to prevent race conditions.
+ *  Version 2.6
+ *    - Corrected disabling of receive DMA channel when aborting
+ *      Receive (ARM_USART_ABORT_RECEIVE) or Transfer (ARM_USART_ABORT_TRANSFER)
+ *  Version 2.5
+ *    - fract_div_lookup_table moved from USART_LPC18xx.h to USART_LPC18xx.c
+ *  Version 2.4
+ *    - Improved baudrate calculation
+ *  Version 2.3
+ *    - Corrected RX Time-Out handling
+ *    - Corrected USART clock configuration
+ *    - Updated USART_Control function
+ *    - Updated USART_Send function
+ *    - GPDMA initialization and uninitialization
+ *  Version 2.2
+ *    - Corrected modem lines handling
+ *  Version 2.1
+ *    - Added DMA support
+ *    - Other Improvements (status checking, USART_Control, ...)
+ *  Version 2.0
+ *    - Updated to CMSIS Driver API V2.00
+ *  Version 1.1
+ *    - Based on API V1.10 (namespace prefix ARM_ added)
+ *  Version 1.0
+ *    - Initial release
+ */
+#include "USART_LPC18xx.h"
+
+#include "RTE_Device.h"
+#include "RTE_Components.h"
+
+#define ARM_USART_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,9)
+
+#if ((!RTE_USART0) && (!RTE_UART1) && (!RTE_USART2) && (!RTE_USART3))
+#error "USART not enabled in RTE_Device.h!"
+#endif
+
+// Driver Version
+static const ARM_DRIVER_VERSION usart_driver_version = { ARM_USART_API_VERSION, ARM_USART_DRV_VERSION };
+
+// Trigger level definitions
+// Can be user defined by C preprocessor
+#ifndef USART0_TRIG_LVL
+#define USART0_TRIG_LVL           USART_TRIG_LVL_1
+#endif
+#ifndef USART1_TRIG_LVL
+#define USART1_TRIG_LVL           USART_TRIG_LVL_1
+#endif
+#ifndef USART2_TRIG_LVL
+#define USART2_TRIG_LVL           USART_TRIG_LVL_1
+#endif
+#ifndef USART3_TRIG_LVL
+#define USART3_TRIG_LVL           USART_TRIG_LVL_1
+#endif
+
+// SmartCard oversampling ratio
+#ifndef USART0_SC_OVERSAMPLING_RATIO
+#define USART0_SC_OVERSAMPLING_RATIO           372
+#endif
+#ifndef USART2_SC_OVERSAMPLING_RATIO
+#define USART2_SC_OVERSAMPLING_RATIO           372
+#endif
+#ifndef USART3_SC_OVERSAMPLING_RATIO
+#define USART3_SC_OVERSAMPLING_RATIO           372
+#endif
+
+// Fractional divider lookup table
+static const FRACT_DIVIDER fract_div_lookup_table[] = {
+  {(1 << 12), 0},
+  FRACT_DIV(1,  15),
+  FRACT_DIV(1,  14),
+  FRACT_DIV(1,  13),
+  FRACT_DIV(1,  12),
+  FRACT_DIV(1,  11),
+  FRACT_DIV(1,  10),
+  FRACT_DIV(1,   9),
+  FRACT_DIV(1,   8),
+  FRACT_DIV(2,  15),
+  FRACT_DIV(1,   7),
+  FRACT_DIV(2,  13),
+  FRACT_DIV(1,   6),
+  FRACT_DIV(2,  11),
+  FRACT_DIV(1,   5),
+  FRACT_DIV(3,  14),
+  FRACT_DIV(2,   9),
+  FRACT_DIV(3,  13),
+  FRACT_DIV(1,   4),
+  FRACT_DIV(4,  15),
+  FRACT_DIV(3,  11),
+  FRACT_DIV(2,   7),
+  FRACT_DIV(3,  10),
+  FRACT_DIV(4,  13),
+  FRACT_DIV(1,   3),
+  FRACT_DIV(5,  14),
+  FRACT_DIV(4,  11),
+  FRACT_DIV(3,   8),
+  FRACT_DIV(5,  13),
+  FRACT_DIV(2,   5),
+  FRACT_DIV(5,  12),
+  FRACT_DIV(3,   7),
+  FRACT_DIV(4,   9),
+  FRACT_DIV(5,  11),
+  FRACT_DIV(6,  13),
+  FRACT_DIV(7,  15),
+  FRACT_DIV(1,   2),
+  FRACT_DIV(8,  15),
+  FRACT_DIV(7,  13),
+  FRACT_DIV(6,  11),
+  FRACT_DIV(5,   9),
+  FRACT_DIV(4,   7),
+  FRACT_DIV(7,  12),
+  FRACT_DIV(3,   5),
+  FRACT_DIV(8,  13),
+  FRACT_DIV(5,   8),
+  FRACT_DIV(7,  11),
+  FRACT_DIV(9,  14),
+  FRACT_DIV(2,   3),
+  FRACT_DIV(9,  13),
+  FRACT_DIV(7,  10),
+  FRACT_DIV(5,   7),
+  FRACT_DIV(8,  11),
+  FRACT_DIV(11, 15),
+  FRACT_DIV(3,   4),
+  FRACT_DIV(10, 13),
+  FRACT_DIV(7,   9),
+  FRACT_DIV(11, 14),
+  FRACT_DIV(4,   5),
+  FRACT_DIV(9,  11),
+  FRACT_DIV(5,   6),
+  FRACT_DIV(11, 13),
+  FRACT_DIV(6,   7),
+  FRACT_DIV(13, 15),
+  FRACT_DIV(7,   8),
+  FRACT_DIV(8,   9),
+  FRACT_DIV(9,  10),
+  FRACT_DIV(10, 11),
+  FRACT_DIV(11, 12),
+  FRACT_DIV(12, 13),
+  FRACT_DIV(13, 14),
+  FRACT_DIV(14, 15)
+};
+
+// Fractional divider lookup table size
+#define FRACT_DIV_LOOKUP_TABLE_SZ  (sizeof(fract_div_lookup_table) / sizeof(fract_div_lookup_table[0]))
+
+// USART0
+#if (RTE_USART0)
+static USART_INFO USART0_Info = {0};
+static PIN_ID USART0_pin_tx  = { RTE_USART0_TX_PORT,   RTE_USART0_TX_BIT,   RTE_USART0_TX_FUNC };
+static PIN_ID USART0_pin_rx  = { RTE_USART0_RX_PORT,   RTE_USART0_RX_BIT,   RTE_USART0_RX_FUNC };
+#if (RTE_USART0_UCLK_PIN_EN == 1)
+static PIN_ID USART0_pin_clk = { RTE_USART0_UCLK_PORT, RTE_USART0_UCLK_BIT, RTE_USART0_UCLK_FUNC };
+#endif
+
+#if (RTE_USART0_DMA_TX_EN == 1)
+void USART0_GPDMA_Tx_Event (uint32_t event);
+static USART_DMA USART0_DMA_Tx = {RTE_USART0_DMA_TX_CH,
+                                  RTE_USART0_DMA_TX_PERI,
+                                  RTE_USART0_DMA_TX_PERI_SEL,
+                                  USART0_GPDMA_Tx_Event};
+#endif
+#if (RTE_USART0_DMA_RX_EN == 1)
+void USART0_GPDMA_Rx_Event (uint32_t event);
+static USART_DMA USART0_DMA_Rx = {RTE_USART0_DMA_RX_CH,
+                                  RTE_USART0_DMA_RX_PERI,
+                                  RTE_USART0_DMA_RX_PERI_SEL,
+                                  USART0_GPDMA_Rx_Event};
+#endif
+
+static const USART_RESOURCES USART0_Resources = {
+  {     // Capabilities
+    1,  // supports UART (Asynchronous) mode
+#if (RTE_USART0_UCLK_PIN_EN == 1)
+    1,  // supports Synchronous Master mode
+    1,  // supports Synchronous Slave mode
+#else
+    0,  // supports Synchronous Master mode
+    0,  // supports Synchronous Slave mode
+#endif
+    1,  // supports UART Single-wire mode
+    0,  // supports UART IrDA mode
+    1,  // supports UART Smart Card mode
+#if (RTE_USART0_UCLK_PIN_EN == 1)
+    1,  // Smart Card Clock generator
+#else
+    0,
+#endif
+    0,  // RTS Flow Control available
+    0,  // CTS Flow Control available
+    0,  // Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE
+#if ((RTE_USART0_DMA_RX_EN == 1) || (USART0_TRIG_LVL == USART_TRIG_LVL_1))
+    0,  // Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT
+#else
+    1,  // Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT
+#endif
+    0,  // RTS Line: 0=not available, 1=available
+    0,  // CTS Line: 0=not available, 1=available
+    0,  // DTR Line: 0=not available, 1=available
+    0,  // DSR Line: 0=not available, 1=available
+    0,  // DCD Line: 0=not available, 1=available
+    0,  // RI Line: 0=not available, 1=available
+    0,  // Signal CTS change event: \ref ARM_USART_EVENT_CTS
+    0,  // Signal DSR change event: \ref ARM_USART_EVENT_DSR
+    0,  // Signal DCD change event: \ref ARM_USART_EVENT_DCD
+    0,  // Signal RI change event: \ref ARM_USART_EVENT_RI
+  },
+    LPC_USART0,
+    NULL,
+  {     // USART Pin Configuration
+    &USART0_pin_tx,
+    &USART0_pin_rx,
+#if (RTE_USART0_UCLK_PIN_EN == 1)
+    &USART0_pin_clk,
+#else
+    NULL,
+#endif
+    NULL, NULL, NULL, NULL, NULL, NULL,
+  },
+  {     // USART Clocks Configuration
+    &LPC_CCU1->CLK_M3_USART0_CFG,
+    &LPC_CCU1->CLK_M3_USART0_STAT,
+    &LPC_CCU2->CLK_APB0_USART0_CFG,
+    &LPC_CCU2->CLK_APB0_USART0_STAT,
+    &LPC_CGU->BASE_UART0_CLK,
+  },
+  {    // USART Reset Configuration
+    (1 << 12),
+    &LPC_RGU->RESET_CTRL1,
+    &LPC_RGU->RESET_ACTIVE_STATUS1,
+  },
+    USART0_IRQn,
+    USART0_TRIG_LVL,
+#if (RTE_USART0_DMA_TX_EN == 1)
+    &USART0_DMA_Tx,
+#else
+    NULL,
+#endif
+#if (RTE_USART0_DMA_RX_EN == 1)
+    &USART0_DMA_Rx,
+#else
+    NULL,
+#endif
+    &USART0_Info,
+    USART0_SC_OVERSAMPLING_RATIO
+};
+#endif
+
+// UART1
+#if (RTE_UART1)
+static USART_INFO USART1_Info = {0};
+static PIN_ID USART1_pin_tx  = { RTE_UART1_TX_PORT,   RTE_UART1_TX_BIT,  RTE_UART1_TX_FUNC };
+static PIN_ID USART1_pin_rx  = { RTE_UART1_RX_PORT,   RTE_UART1_RX_BIT,  RTE_UART1_RX_FUNC };
+#if (RTE_UART1_CTS_PIN_EN == 1)
+static PIN_ID USART1_pin_cts = { RTE_UART1_CTS_PORT,  RTE_UART1_CTS_BIT, RTE_UART1_CTS_FUNC };
+#endif
+#if (RTE_UART1_RTS_PIN_EN == 1)
+static PIN_ID USART1_pin_rts = { RTE_UART1_RTS_PORT,  RTE_UART1_RTS_BIT, RTE_UART1_RTS_FUNC };
+#endif
+#if (RTE_UART1_DCD_PIN_EN == 1)
+static PIN_ID USART1_pin_dcd = { RTE_UART1_DCD_PORT,  RTE_UART1_DCD_BIT, RTE_UART1_DCD_FUNC };
+#endif
+#if (RTE_UART1_DSR_PIN_EN == 1)
+static PIN_ID USART1_pin_dsr = { RTE_UART1_DSR_PORT,  RTE_UART1_DSR_BIT, RTE_UART1_DSR_FUNC };
+#endif
+#if (RTE_UART1_DTR_PIN_EN == 1)
+static PIN_ID USART1_pin_dtr = { RTE_UART1_DTR_PORT,  RTE_UART1_DTR_BIT, RTE_UART1_DTR_FUNC };
+#endif
+#if (RTE_UART1_RI_PIN_EN == 1)
+static PIN_ID USART1_pin_ri  = { RTE_UART1_RI_PORT,   RTE_UART1_RI_BIT,  RTE_UART1_RI_FUNC };
+#endif
+
+#if (RTE_UART1_DMA_TX_EN == 1)
+void USART1_GPDMA_Tx_Event (uint32_t event);
+static USART_DMA USART1_DMA_Tx = {RTE_UART1_DMA_TX_CH,
+                                  RTE_UART1_DMA_TX_PERI,
+                                  RTE_UART1_DMA_TX_PERI_SEL,
+                                  USART1_GPDMA_Tx_Event};
+#endif
+#if (RTE_UART1_DMA_RX_EN == 1)
+void USART1_GPDMA_Rx_Event (uint32_t event);
+static USART_DMA USART1_DMA_Rx = {RTE_UART1_DMA_RX_CH,
+                                  RTE_UART1_DMA_RX_PERI,
+                                  RTE_UART1_DMA_RX_PERI_SEL,
+                                  USART1_GPDMA_Rx_Event};
+#endif
+
+static const USART_RESOURCES USART1_Resources = {
+  {     // Capabilities
+    1,  // supports UART (Asynchronous) mode 
+    0,  // supports Synchronous Master mode
+    0,  // supports Synchronous Slave mode
+    0,  // supports UART Single-wire mode
+    0,  // supports UART IrDA mode
+    0,  // supports UART Smart Card mode
+    0,  // Smart Card Clock generator
+#if (RTE_UART1_RTS_PIN_EN == 1)
+    1,  // RTS Flow Control available
+#else
+    0,  // RTS Flow Control available
+#endif
+#if (RTE_UART1_CTS_PIN_EN == 1)
+    1,  // CTS Flow Control available
+#else
+    0,  // CTS Flow Control available
+#endif
+    0,  // Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE
+#if ((RTE_UART1_DMA_RX_EN == 1) || (USART1_TRIG_LVL == USART_TRIG_LVL_1))
+    0,  // Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT
+#else
+    1,  // Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT
+#endif
+#if (RTE_UART1_RTS_PIN_EN == 1)
+    1,  // RTS Line: 0=not available, 1=available
+#else
+    0,
+#endif
+#if (RTE_UART1_CTS_PIN_EN == 1)
+    1,  // CTS Line: 0=not available, 1=available
+#else
+    0,
+#endif
+#if (RTE_UART1_DTR_PIN_EN == 1)
+    1,  // DTR Line: 0=not available, 1=available
+#else
+    0,
+#endif
+#if (RTE_UART1_DSR_PIN_EN == 1)
+    1,  // DSR Line: 0=not available, 1=available
+#else
+    0,
+#endif
+#if (RTE_UART1_DCD_PIN_EN == 1)
+    1,  // DCD Line: 0=not available, 1=available
+#else
+    0,
+#endif
+#if (RTE_UART1_RI_PIN_EN == 1)
+    1,  // RI Line: 0=not available, 1=available
+#else
+    0,
+#endif
+#if (RTE_UART1_CTS_PIN_EN == 1)
+    1,  // Signal CTS change event: \ref ARM_USART_EVENT_CTS
+#else
+    0,
+#endif
+#if (RTE_UART1_DSR_PIN_EN == 1)
+    1,  // Signal DSR change event: \ref ARM_USART_EVENT_DSR
+#else
+    0,
+#endif
+#if (RTE_UART1_DCD_PIN_EN == 1)
+    1,  // Signal DCD change event: \ref ARM_USART_EVENT_DCD
+#else
+    0,
+#endif
+#if (RTE_UART1_RI_PIN_EN == 1)
+    1,  // Signal RI change event: \ref ARM_USART_EVENT_RI
+#else
+    0,
+#endif
+  },
+    (LPC_USARTn_Type *)LPC_UART1,
+    LPC_UART1,
+  {     // USART Pin Configuration
+    &USART1_pin_tx,
+    &USART1_pin_rx,
+    NULL,
+#if (RTE_UART1_CTS_PIN_EN == 1)
+    &USART1_pin_cts,
+#else
+    NULL,
+#endif
+#if (RTE_UART1_RTS_PIN_EN == 1)
+    &USART1_pin_rts,
+#else
+    NULL,
+#endif
+#if (RTE_UART1_DCD_PIN_EN == 1)
+    &USART1_pin_dcd,
+#else
+    NULL,
+#endif
+#if (RTE_UART1_DSR_PIN_EN == 1)
+    &USART1_pin_dsr,
+#else
+    NULL,
+#endif
+#if (RTE_UART1_DTR_PIN_EN == 1)
+    &USART1_pin_dtr,
+#else
+    NULL,
+#endif
+#if (RTE_UART1_RI_PIN_EN == 1)
+    &USART1_pin_ri,
+#else
+    NULL,
+#endif
+  },
+  {     // USART Clocks Configuration
+    &LPC_CCU1->CLK_M3_UART1_CFG,
+    &LPC_CCU1->CLK_M3_UART1_STAT,
+    &LPC_CCU2->CLK_APB0_UART1_CFG,
+    &LPC_CCU2->CLK_APB0_UART1_STAT,
+    &LPC_CGU->BASE_UART1_CLK,
+  },
+  {    // USART Reset Configuration
+    (1 << 13),
+    &LPC_RGU->RESET_CTRL1,
+    &LPC_RGU->RESET_ACTIVE_STATUS1,
+  },
+    UART1_IRQn,
+    USART1_TRIG_LVL,
+#if (RTE_UART1_DMA_TX_EN == 1)
+    &USART1_DMA_Tx,
+#else
+    NULL,
+#endif
+#if (RTE_UART1_DMA_RX_EN == 1)
+    &USART1_DMA_Rx,
+#else
+    NULL,
+#endif
+    &USART1_Info,
+    0
+};
+#endif
+
+// USART2
+#if (RTE_USART2)
+static USART_INFO USART2_Info = {0};
+static PIN_ID USART2_pin_tx  = { RTE_USART2_TX_PORT,   RTE_USART2_TX_BIT,   RTE_USART2_TX_FUNC };
+static PIN_ID USART2_pin_rx  = { RTE_USART2_RX_PORT,   RTE_USART2_RX_BIT,   RTE_USART2_RX_FUNC };
+#if (RTE_USART2_UCLK_PIN_EN == 1)
+static PIN_ID USART2_pin_clk = { RTE_USART2_UCLK_PORT, RTE_USART2_UCLK_BIT, RTE_USART2_UCLK_FUNC };
+#endif
+
+#if (RTE_USART2_DMA_TX_EN == 1)
+void USART2_GPDMA_Tx_Event (uint32_t event);
+static USART_DMA USART2_DMA_Tx = {RTE_USART2_DMA_TX_CH,
+                                  RTE_USART2_DMA_TX_PERI,
+                                  RTE_USART2_DMA_TX_PERI_SEL,
+                                  USART2_GPDMA_Tx_Event};
+#endif
+#if (RTE_USART2_DMA_RX_EN == 1)
+void USART2_GPDMA_Rx_Event (uint32_t event);
+static USART_DMA USART2_DMA_Rx = {RTE_USART2_DMA_RX_CH,
+                                  RTE_USART2_DMA_RX_PERI,
+                                  RTE_USART2_DMA_RX_PERI_SEL,
+                                  USART2_GPDMA_Rx_Event};
+#endif
+
+static const USART_RESOURCES USART2_Resources = {
+  {     // Capabilities
+    1,  // supports UART (Asynchronous) mode
+#if (RTE_USART1_UCLK_PIN_EN == 1)
+    1,  // supports Synchronous Master mode
+    1,  // supports Synchronous Slave mode
+#else
+    0,  // supports Synchronous Master mode
+    0,  // supports Synchronous Slave mode
+#endif
+    1,  // supports UART Single-wire mode
+    0,  // supports UART IrDA mode
+    1,  // supports UART Smart Card mode
+#if (RTE_USART2_UCLK_PIN_EN == 1)
+    1,  // Smart Card Clock generator
+#else
+    0,
+#endif
+    0,  // RTS Flow Control available
+    0,  // CTS Flow Control available
+    0,  // Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE
+#if ((RTE_USART2_DMA_RX_EN == 1) || (USART2_TRIG_LVL == USART_TRIG_LVL_1))
+    0,  // Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT
+#else
+    1,  // Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT
+#endif
+    0,  // RTS Line: 0=not available, 1=available
+    0,  // CTS Line: 0=not available, 1=available
+    0,  // DTR Line: 0=not available, 1=available
+    0,  // DSR Line: 0=not available, 1=available
+    0,  // DCD Line: 0=not available, 1=available
+    0,  // RI Line: 0=not available, 1=available
+    0,  // Signal CTS change event: \ref ARM_USART_EVENT_CTS
+    0,  // Signal DSR change event: \ref ARM_USART_EVENT_DSR
+    0,  // Signal DCD change event: \ref ARM_USART_EVENT_DCD
+    0,  // Signal RI change event: \ref ARM_USART_EVENT_RI
+  },
+    LPC_USART2,
+    NULL,
+  {     // USART Pin Configuration
+    &USART2_pin_tx,
+    &USART2_pin_rx,
+#if (RTE_USART2_UCLK_PIN_EN == 1)
+    &USART2_pin_clk,
+#else
+    NULL,
+#endif
+    NULL, NULL, NULL, NULL, NULL, NULL,
+  },
+  {     // USART Clocks Configuration
+    &LPC_CCU1->CLK_M3_USART2_CFG,
+    &LPC_CCU1->CLK_M3_USART2_STAT,
+    &LPC_CCU2->CLK_APB2_USART2_CFG,
+    &LPC_CCU2->CLK_APB2_USART2_STAT,
+    &LPC_CGU->BASE_UART2_CLK,
+  },
+  {    // USART Reset Configuration
+    (1 << 14),
+    &LPC_RGU->RESET_CTRL1,
+    &LPC_RGU->RESET_ACTIVE_STATUS1,
+  },
+    USART2_IRQn,
+    USART2_TRIG_LVL,
+#if (RTE_USART2_DMA_TX_EN == 1)
+    &USART2_DMA_Tx,
+#else
+    NULL,
+#endif
+#if (RTE_USART2_DMA_RX_EN == 1)
+    &USART2_DMA_Rx,
+#else
+    NULL,
+#endif
+    &USART2_Info,
+    USART2_SC_OVERSAMPLING_RATIO
+};
+#endif
+
+// USART3
+#if (RTE_USART3)
+static USART_INFO USART3_Info = {0};
+static PIN_ID USART3_pin_tx  = { RTE_USART3_TX_PORT,   RTE_USART3_TX_BIT,   RTE_USART3_TX_FUNC };
+static PIN_ID USART3_pin_rx  = { RTE_USART3_RX_PORT,   RTE_USART3_RX_BIT,   RTE_USART3_RX_FUNC };
+#if (RTE_USART3_UCLK_PIN_EN == 1)
+static PIN_ID USART3_pin_clk = { RTE_USART3_UCLK_PORT, RTE_USART3_UCLK_BIT, RTE_USART3_UCLK_FUNC };
+#endif
+
+#if (RTE_USART3_DMA_TX_EN == 1)
+void USART3_GPDMA_Tx_Event (uint32_t event);
+static USART_DMA USART3_DMA_Tx = {RTE_USART3_DMA_TX_CH,
+                                  RTE_USART3_DMA_TX_PERI,
+                                  RTE_USART3_DMA_TX_PERI_SEL,
+                                  USART3_GPDMA_Tx_Event};
+#endif
+#if (RTE_USART3_DMA_RX_EN == 1)
+void USART3_GPDMA_Rx_Event (uint32_t event);
+static USART_DMA USART3_DMA_Rx = {RTE_USART3_DMA_RX_CH,
+                                  RTE_USART3_DMA_RX_PERI,
+                                  RTE_USART3_DMA_RX_PERI_SEL,
+                                  USART3_GPDMA_Rx_Event};
+#endif
+
+static const USART_RESOURCES USART3_Resources = {
+  {     // Capabilities
+    1,  // supports UART (Asynchronous) mode 
+#if (RTE_USART3_UCLK_PIN_EN == 1)
+    1,  // supports Synchronous Master mode
+    1,  // supports Synchronous Slave mode
+#else
+    0,  // supports Synchronous Master mode
+    0,  // supports Synchronous Slave mode
+#endif
+    1,  // supports UART Single-wire mode
+    1,  // supports UART IrDA mode
+    1,  // supports UART Smart Card mode
+#if (RTE_USART3_UCLK_PIN_EN == 1)
+    1,  // Smart Card Clock generator
+#else
+    0,
+#endif
+    0,  // RTS Flow Control available
+    0,  // CTS Flow Control available
+    0,  // Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE
+#if ((RTE_USART3_DMA_RX_EN == 1) || (USART3_TRIG_LVL == USART_TRIG_LVL_1))
+    0,  // Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT
+#else
+    1,  // Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT
+#endif
+    0,  // RTS Line: 0=not available, 1=available
+    0,  // CTS Line: 0=not available, 1=available
+    0,  // DTR Line: 0=not available, 1=available
+    0,  // DSR Line: 0=not available, 1=available
+    0,  // DCD Line: 0=not available, 1=available
+    0,  // RI Line: 0=not available, 1=available
+    0,  // Signal CTS change event: \ref ARM_USART_EVENT_CTS
+    0,  // Signal DSR change event: \ref ARM_USART_EVENT_DSR
+    0,  // Signal DCD change event: \ref ARM_USART_EVENT_DCD
+    0,  // Signal RI change event: \ref ARM_USART_EVENT_RI
+  },
+    LPC_USART3,
+    NULL,
+  {     // USART Pin Configuration
+    &USART3_pin_tx,
+    &USART3_pin_rx,
+#if (RTE_USART3_UCLK_PIN_EN == 1)
+    &USART3_pin_clk,
+#else
+    NULL,
+#endif
+    NULL, NULL, NULL, NULL, NULL, NULL,
+  },
+  {     // USART Clocks Configuration
+    &LPC_CCU1->CLK_M3_USART3_CFG,
+    &LPC_CCU1->CLK_M3_USART3_STAT,
+    &LPC_CCU2->CLK_APB2_USART3_CFG,
+    &LPC_CCU2->CLK_APB2_USART3_STAT,
+    &LPC_CGU->BASE_UART3_CLK,
+  },
+  {    // USART Reset Configuration
+    (1 << 15),
+    &LPC_RGU->RESET_CTRL1,
+    &LPC_RGU->RESET_ACTIVE_STATUS1,
+  },
+    USART3_IRQn,
+    USART3_TRIG_LVL,
+#if (RTE_USART3_DMA_TX_EN == 1)
+    &USART3_DMA_Tx,
+#else
+    NULL,
+#endif
+#if (RTE_USART3_DMA_RX_EN == 1)
+    &USART3_DMA_Rx,
+#else
+    NULL,
+#endif
+    &USART3_Info,
+    USART3_SC_OVERSAMPLING_RATIO
+};
+#endif
+
+
+// Extern Function
+extern uint32_t GetClockFreq (uint32_t clk_src);
+
+// Local Function
+/**
+  \fn          int32_t USART_SetBaudrate (uint32_t         baudrate,
+                                          USART_RESOURCES *usart)
+  \brief       Set baudrate dividers
+  \param[in]   baudrate  Usart baudrate
+  \param[in]   usart     Pointer to USART resources)
+  \returns
+   - \b  0: function succeeded
+   - \b -1: function failed
+*/
+int32_t USART_SetBaudrate (uint32_t         baudrate,
+                           USART_RESOURCES *usart) {
+  uint8_t  add, mul, add_mul_best, oversampling_fract_best;
+  uint16_t latch_div_best, oversampling, oversampling_best;
+  uint32_t i, j, pclk, div, tmp_div, latch_div, delta, delta_best, val;
+
+  pclk = GetClockFreq ((*usart->clk.base_clk >> 24) & 0x1FU);
+
+  // Calculate fixed point divider (12 LSBs are fractional part)
+  div       = (uint32_t)(((uint64_t)pclk << FRACT_BITS) / (uint64_t)baudrate);
+
+  delta_best              = 0xFFFFFFFFU;
+  oversampling_fract_best = 0U;
+
+  // SmartCard mode
+  if (usart->info->mode == ARM_USART_MODE_SMART_CARD) {
+    oversampling_best = usart->sc_oversamp;
+    for (i = 0; i < FRACT_DIV_LOOKUP_TABLE_SZ; i++) {
+      // Calculate latch divider (latch_div = div / (fract_div * oversampling(16)))
+      latch_div = ((div / fract_div_lookup_table[i].val) / oversampling_best);
+
+      if (latch_div > 65535U) { continue; }
+
+      for (j = 0U; j < 2U; j++) {
+        // Which latch divider value is more appropriate:
+        //    latch_div or latch_div + 1 (rounded up)
+
+        if (latch_div < 3U) { latch_div++; continue; }
+
+        // Calculate actual divider (temp_div = latch_div * fract_div * oversampling(16))
+        tmp_div   = (latch_div * fract_div_lookup_table[i].val) / oversampling_best;
+
+        // Calculate delta
+        if (div > tmp_div) { delta = div - tmp_div; }
+        else               { delta = tmp_div - div; }
+
+        // Check if delta is better than best delta
+        if (delta < delta_best) {
+          delta_best        = delta;
+          add_mul_best      = fract_div_lookup_table[i].add_mul;
+          latch_div_best    = latch_div;
+        }
+        latch_div++;
+      }
+    }
+  } else {
+
+    // Oversampling is fixed to 16
+    // divider = oversampling * latch divider * fractional divider = 16 * latch_div * fract_div
+    if (div >= FIXED_OVERSAMPLING_DIVIDER_LIMIT) {
+      latch_div = div >> (FRACT_BITS + 4U);
+      if ((div == (latch_div << (FRACT_BITS + 4U))) && ((latch_div >> 4) <= 0xFFFFU)) {
+        // Fractional part of divider is 0
+        delta_best        = 0U;
+        add_mul_best      = 0U;
+        latch_div_best    = latch_div;
+        oversampling_best = 16U;
+      } else {
+        // Divider larger than 48, can be accomplished with configurable
+        // latch and fractional divider, and fixed oversampling to 16
+
+        for (i = 0U; i < FRACT_DIV_LOOKUP_TABLE_SZ; i++) {
+          // Calculate latch divider (latch_div = div / (fract_div * oversampling(16)))
+          latch_div = ((div / fract_div_lookup_table[i].val) >> 4);
+
+          if (latch_div > 65535U) { continue; }
+
+          for (j = 0U; j < 2U; j++) {
+            // Which latch divider value is more appropriate: 
+            //    latch_div or latch_div + 1 (rounded up)
+
+            if (latch_div < 3U) { latch_div++; continue; }
+
+            // Calculate actual divider (temp_div = latch_div * fract_div * oversampling(16))
+            tmp_div   = (latch_div * fract_div_lookup_table[i].val) << 4;
+
+            // Calculate delta
+            if (div > tmp_div) { delta = div - tmp_div; }
+            else               { delta = tmp_div - div; }
+
+            // Check if delta is better than best delta
+            if (delta < delta_best) {
+              delta_best        = delta;
+              add_mul_best      = fract_div_lookup_table[i].add_mul;
+              latch_div_best    = latch_div;
+              oversampling_best = 16U;
+            }
+            latch_div++;
+          }
+        }
+      }
+    } else {
+      // Check if oversampling register is available
+      if (usart->uart_reg != NULL) {return - 1; }
+
+      if (div > INTEGER_OVERSAMPLING_DIVIDER_LIMIT) {
+        // Oversampling ratio is integer value
+
+        // Set oversampling
+        if      (div > (48U << 12)) { oversampling = 15U; }
+        else if (div > (45U << 12)) { oversampling = 14U; }
+        else if (div > (42U << 12)) { oversampling = 13U; }
+        else if (div > (38U << 12)) { oversampling = 12U; }
+        else if (div > (35U << 12)) { oversampling = 11U; }
+        else if (div > (32U << 12)) { oversampling = 10U; }
+        else if (div > (29U << 12)) { oversampling =  9U; }
+        else if (div > (26U << 12)) { oversampling =  8U; }
+        else if (div > (23U << 12)) { oversampling =  7U; }
+        else if (div > (19U << 12)) { oversampling =  6U; }
+        else if (div > (16U << 12)) { oversampling =  5U; }
+        else                        { oversampling =  4U; }
+
+        // Check if divider is integer value
+        tmp_div   = (div / oversampling);
+        if ((tmp_div & FRACT_MASK) == 0U) {
+          // Fractional part of divider is 0
+          delta_best        = 0U;
+          add_mul_best      = 0U;
+          latch_div_best    = tmp_div >> FRACT_BITS;
+          oversampling_best = oversampling;
+        } else {
+          // Fractional part of divider is not 0
+
+          latch_div = 3U;
+
+          for (i = 0U; i < FRACT_DIV_LOOKUP_TABLE_SZ; i++) {
+
+            // Calculate actual divider (temp_div = latch_div * fract_div * oversampling)
+            tmp_div   = latch_div * fract_div_lookup_table[i].val * oversampling;
+
+            // Calculate delta
+            if (div > tmp_div) { delta = div - tmp_div; }
+            else               { delta = tmp_div - div; }
+
+            // Check if delta is better than best delta
+            if (delta < delta_best) {
+              delta_best        = delta;
+              add_mul_best      = fract_div_lookup_table[i].add_mul;
+              latch_div_best    = latch_div;
+              oversampling_best = oversampling;
+            }
+          }
+        }
+
+        //tmp_div = latch_div_best * fract_best * oversampling_best;
+        add = add_mul_best & 0x0FU;
+        mul = add_mul_best >> 4;
+        tmp_div = ((latch_div_best * (mul + add) * oversampling_best) << 12) / mul;
+        if ((tmp_div & FRACT_MASK) == 0U) {
+          // If best possible divider is integer value, make sure
+          // fractional divider is 0 and max oversampling is used
+
+          oversampling = 16U;
+          do {
+            if (((tmp_div / oversampling) & FRACT_MASK) == 0U) {
+              // Fractional part of divider is 0
+
+              tmp_div /= oversampling;
+              add_mul_best      = 0U;
+              latch_div_best    = tmp_div >> FRACT_BITS;
+              oversampling_best = oversampling;
+              break;
+            }
+            oversampling--;
+          } while (oversampling >= 4U);
+        }
+      } else {
+        // Oversampling ratio can be fractional,
+        // latch divider is 1 and fractional divider is not used
+
+        // Oversampling step
+        val = (125U << FRACT_BITS) / 1000U;
+        oversampling = 13U << FRACT_BITS;
+        do {
+          // Calculate delta
+          if (div > oversampling) { delta = div - oversampling; }
+          else                    { delta = oversampling - div; }
+
+          // Check if delta is better than best delta
+          if (delta < delta_best) {
+            delta_best        = delta;
+            add_mul_best      = 0U;
+            latch_div_best    = 1U;
+            oversampling_best = oversampling;
+          }
+
+          oversampling -= val;
+        } while (oversampling >= (4U << FRACT_BITS));
+
+        oversampling_fract_best = ((oversampling_best & FRACT_MASK) << 3) >> FRACT_BITS;
+        oversampling_best       =   oversampling_best >> FRACT_BITS;
+      }
+    }
+  }
+
+  if (((delta_best * 100U) / div) > USART_MAX_BAUDRATE_ERROR) { return -1; }
+
+  usart->reg->LCR |= USART_LCR_DLAB;
+  usart->reg->DLM  = ((latch_div_best >> 8) & 0xFFU) << USART_DLM_DLMSB_POS;
+  usart->reg->DLL  = (latch_div_best & USART_DLL_DLLSB_MSK) << USART_DLL_DLLSB_POS;
+  // Reset DLAB bit
+  usart->reg->LCR &= (~USART_LCR_DLAB);
+  usart->reg->FDR  = ((add_mul_best & USART_FDR_MULVAL_MSK)  |
+                      (add_mul_best & USART_FDR_DIVADDVAL_MSK));
+
+  // Check if oversampling register is available
+  if (usart->uart_reg == NULL) {
+    usart->reg->OSR = ((oversampling_best - 1)  << USART_OSR_OSINT_POS) |
+                      ( oversampling_fract_best << USART_OSR_OSFRAC_POS);
+  }
+
+  usart->info->baudrate = baudrate;
+
+  return 0;
+}
+
+/**
+  \fn          uint32_t USART_RxLineIntHandler (USART_RESOURCES *usart)
+  \brief       Receive line interrupt handler
+  \param[in]   usart     Pointer to USART resources
+  \return      Rx Line event mask
+*/
+static uint32_t USART_RxLineIntHandler (USART_RESOURCES *usart) {
+  uint32_t lsr, event;
+
+  event = 0U;
+  lsr   = usart->reg->LSR  & USART_LSR_LINE_INT;
+
+  // OverRun error
+  if (lsr & USART_LSR_OE) {
+    usart->info->rx_status.rx_overflow = 1U;
+    event |= ARM_USART_EVENT_RX_OVERFLOW;
+
+    // Sync Slave mode: If Transmitter enabled, signal TX underflow
+    if (usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_SLAVE) {
+      if (usart->info->xfer.send_active != 0U) {
+        event |= ARM_USART_EVENT_TX_UNDERFLOW;
+      }
+    }
+  }
+
+  // Parity error
+  if (lsr & USART_LSR_PE) {
+    usart->info->rx_status.rx_parity_error = 1U;
+    event |= ARM_USART_EVENT_RX_PARITY_ERROR;
+  }
+
+  // Break detected
+  if (lsr & USART_LSR_BI) {
+    usart->info->rx_status.rx_break = 1U;
+    event |= ARM_USART_EVENT_RX_BREAK;
+  }
+
+  // Framing error
+  else {
+    if(lsr & USART_LSR_FE) {
+      usart->info->rx_status.rx_framing_error = 1U;
+      event |= ARM_USART_EVENT_RX_FRAMING_ERROR;
+    }
+  }
+
+  return event;
+}
+
+// Function Prototypes
+static int32_t USART_Receive (void            *data,
+                              uint32_t         num,
+                              USART_RESOURCES *usart);
+
+
+// USART Driver functions
+
+/**
+  \fn          ARM_DRIVER_VERSION USARTx_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+*/
+static ARM_DRIVER_VERSION USARTx_GetVersion (void) {
+  return usart_driver_version;
+}
+
+/**
+  \fn          ARM_USART_CAPABILITIES USART_GetCapabilities (USART_RESOURCES *usart)
+  \brief       Get driver capabilities
+  \param[in]   usart     Pointer to USART resources
+  \return      \ref ARM_USART_CAPABILITIES
+*/
+static ARM_USART_CAPABILITIES USART_GetCapabilities (USART_RESOURCES *usart) {
+  return usart->capabilities;
+}
+
+/**
+  \fn          int32_t USART_Initialize (ARM_USART_SignalEvent_t  cb_event
+                                         USART_RESOURCES         *usart)
+  \brief       Initialize USART Interface.
+  \param[in]   cb_event  Pointer to \ref ARM_USART_SignalEvent
+  \param[in]   usart     Pointer to USART resources
+  \return      \ref execution_status
+*/
+static int32_t USART_Initialize (ARM_USART_SignalEvent_t  cb_event,
+                                 USART_RESOURCES         *usart) {
+
+  if (usart->info->flags & USART_FLAG_INITIALIZED) {
+    // Driver is already initialized
+    return ARM_DRIVER_OK;
+  }
+
+  // Initialize USART Run-time Resources
+  usart->info->cb_event = cb_event;
+
+  usart->info->rx_status.rx_busy          = 0U;
+  usart->info->rx_status.rx_overflow      = 0U;
+  usart->info->rx_status.rx_break         = 0U;
+  usart->info->rx_status.rx_framing_error = 0U;
+  usart->info->rx_status.rx_parity_error  = 0U;
+
+  usart->info->xfer.send_active           = 0U;
+  usart->info->xfer.tx_def_val            = 0U;
+
+  // Configure CTS pin
+  if (usart->capabilities.cts) {
+    SCU_PinConfigure(usart->pins.cts->port, usart->pins.cts->num,
+                     SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN |
+                     SCU_PIN_CFG_MODE(usart->pins.cts->config_val));
+  }
+
+  // Configure RTS pin
+  if (usart->capabilities.rts) {
+    SCU_PinConfigure(usart->pins.rts->port, usart->pins.rts->num,
+                     SCU_PIN_CFG_MODE(usart->pins.rts->config_val));
+  }
+
+  // Configure DCD pin
+  if (usart->capabilities.dcd) {
+    SCU_PinConfigure(usart->pins.dcd->port, usart->pins.dcd->num,
+                     SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN |
+                     SCU_PIN_CFG_MODE(usart->pins.dcd->config_val));
+  }
+
+  // Configure DSR pin
+  if (usart->capabilities.dsr) {
+    SCU_PinConfigure(usart->pins.dsr->port, usart->pins.dsr->num,
+                     SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN |
+                     SCU_PIN_CFG_MODE(usart->pins.dsr->config_val));
+  }
+
+  // Configure DTR pin
+  if (usart->capabilities.dtr) {
+    SCU_PinConfigure(usart->pins.dtr->port, usart->pins.dtr->num,
+                     SCU_PIN_CFG_MODE(usart->pins.dtr->config_val));
+  }
+
+  // Configure RI pin
+  if (usart->capabilities.ri) {
+    SCU_PinConfigure(usart->pins.ri->port, usart->pins.ri->num,
+                     SCU_PIN_CFG_INPUT_FILTER_DIS | SCU_PIN_CFG_INPUT_BUFFER_EN |
+                     SCU_PIN_CFG_MODE(usart->pins.ri->config_val));
+  }
+
+  // DMA Initialize
+  if (usart->dma_tx || usart->dma_rx) { GPDMA_Initialize (); }
+
+  usart->info->flags = USART_FLAG_INITIALIZED;
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t USART_Uninitialize (USART_RESOURCES *usart)
+  \brief       De-initialize USART Interface.
+  \param[in]   usart     Pointer to USART resources
+  \return      \ref execution_status
+*/
+static int32_t USART_Uninitialize (USART_RESOURCES *usart) {
+
+  // Reset TX pin configuration
+  SCU_PinConfigure(usart->pins.tx->port, usart->pins.tx->num  , 0U);
+
+  // Reset RX pin configuration
+  SCU_PinConfigure(usart->pins.rx->port, usart->pins.rx->num  , 0U);
+
+  // Reset CLK pin configuration
+  if (usart->pins.clk) {
+    SCU_PinConfigure(usart->pins.clk->port, usart->pins.clk->num, 0U);
+  }
+
+  // Reset CTS pin configuration
+  if (usart->capabilities.cts) {
+    SCU_PinConfigure(usart->pins.cts->port, usart->pins.cts->num, 0U);
+  }
+
+  // Reset RTS pin configuration
+  if (usart->capabilities.rts) {
+    SCU_PinConfigure(usart->pins.rts->port, usart->pins.rts->num, 0U);
+  }
+
+  // Configure DCD pin configuration
+  if (usart->capabilities.dcd) {
+    SCU_PinConfigure(usart->pins.dcd->port, usart->pins.dcd->num, 0U);
+  }
+
+  // Reset DSR pin configuration
+  if (usart->capabilities.dsr) {
+    SCU_PinConfigure(usart->pins.dsr->port, usart->pins.dsr->num, 0U);
+  }
+
+  // Reset DTR pin configuration
+  if (usart->capabilities.dtr) {
+    SCU_PinConfigure(usart->pins.dtr->port, usart->pins.dtr->num, 0U);
+  }
+
+  // Reset RI pin configuration
+  if (usart->capabilities.ri) {
+    SCU_PinConfigure(usart->pins.ri->port, usart->pins.ri->num, 0U);
+  }
+
+  // DMA Uninitialize
+  if (usart->dma_tx || usart->dma_rx) { GPDMA_Uninitialize (); }
+
+  // Reset USART status flags
+  usart->info->flags = 0U;
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t USART_PowerControl (ARM_POWER_STATE state)
+  \brief       Control USART Interface Power.
+  \param[in]   state  Power state
+  \param[in]   usart  Pointer to USART resources
+  \return      \ref execution_status
+*/
+static int32_t USART_PowerControl (ARM_POWER_STATE  state,
+                                   USART_RESOURCES *usart) {
+  uint32_t val;
+
+  switch (state) {
+    case ARM_POWER_OFF:
+      // Disable USART IRQ
+      NVIC_DisableIRQ(usart->irq_num);
+
+      // If DMA mode - disable TX DMA channel
+      if ((usart->dma_tx) && (usart->info->xfer.send_active != 0U)) {
+        GPDMA_ChannelDisable (usart->dma_tx->channel);
+      }
+
+      // If DMA mode - disable DMA channel
+      if ((usart->dma_rx) && (usart->info->rx_status.rx_busy)) {
+        GPDMA_ChannelDisable (usart->dma_rx->channel);
+      }
+
+      // Reset USART peripheral
+      *usart->rst.reg_cfg = usart->rst.reg_cfg_val;
+      while ((*(usart->rst.reg_stat) & usart->rst.reg_cfg_val) == 0U);
+
+      // Disable USART peripheral clock
+      *usart->clk.peri_cfg &= ~1U;
+      while (*usart->clk.peri_cfg & 1U);
+        
+      // Disable USART register interface clock
+      *usart->clk.reg_cfg &= ~1U;
+      while (*usart->clk.reg_cfg & 1U);
+
+      // Clear pending USART interrupts in NVIC
+      NVIC_ClearPendingIRQ(usart->irq_num);
+
+      // Clear driver variables
+      usart->info->rx_status.rx_busy          = 0U;
+      usart->info->rx_status.rx_overflow      = 0U;
+      usart->info->rx_status.rx_break         = 0U;
+      usart->info->rx_status.rx_framing_error = 0U;
+      usart->info->rx_status.rx_parity_error  = 0U;
+      usart->info->xfer.send_active           = 0U;
+
+      usart->info->flags &= ~USART_FLAG_POWERED;
+      break;
+
+    case ARM_POWER_LOW:
+      return ARM_DRIVER_ERROR_UNSUPPORTED;
+
+    case ARM_POWER_FULL:
+      if ((usart->info->flags & USART_FLAG_INITIALIZED) == 0U) { return ARM_DRIVER_ERROR; }
+      if ((usart->info->flags & USART_FLAG_POWERED)     != 0U) { return ARM_DRIVER_OK; }
+
+      // Connect USART base clock to PLL1
+      *usart->clk.base_clk = (1U    << 11) |
+                             (0x09U << 24) ;
+
+      // Enable USART register interface clock
+      *usart->clk.reg_cfg |= CCU_CLK_CFG_AUTO | CCU_CLK_CFG_RUN;
+      while ((*usart->clk.reg_cfg & CCU_CLK_CFG_RUN) == 0U);
+
+      // Enable USART peripheral clock
+      *usart->clk.peri_cfg |= CCU_CLK_CFG_AUTO | CCU_CLK_CFG_RUN;
+      while (( *usart->clk.peri_cfg & CCU_CLK_CFG_RUN) == 0U);
+
+      // Reset USART peripheral
+      *usart->rst.reg_cfg = usart->rst.reg_cfg_val;
+      while ((*(usart->rst.reg_stat) & usart->rst.reg_cfg_val) == 0U);
+
+      // Disable transmitter
+      usart->reg->TER &= ~USART_TER_TXEN;
+
+      // Disable receiver
+      usart->reg->RS485CTRL |= USART_RS485CTRL_RXDIS;
+
+      // Disable interrupts
+      usart->reg->IER = 0U;
+
+      // Configure FIFO Control register
+      // Set trigger level
+      val = (usart->trig_lvl & USART_FCR_RXTRIGLVL_MSK) | USART_FCR_FIFOEN;
+
+      if (usart->dma_rx || usart->dma_tx) {
+        val |= USART_FCR_DMAMODE;
+      }
+
+      usart->reg->FCR = val;
+
+#if (RTE_UART1)
+      // Enable modem lines status interrupts (only UART1)
+      if (usart->uart_reg) {
+        if (usart->capabilities.cts || usart->capabilities.dcd ||
+            usart->capabilities.dsr || usart->capabilities.ri) {
+          usart->uart_reg->IER |= UART_IER_MSIE;
+        }
+      }
+#endif
+
+      // Clear driver variables
+      usart->info->rx_status.rx_busy          = 0U;
+      usart->info->rx_status.rx_overflow      = 0U;
+      usart->info->rx_status.rx_break         = 0U;
+      usart->info->rx_status.rx_framing_error = 0U;
+      usart->info->rx_status.rx_parity_error  = 0U;
+
+      usart->info->mode                       = 0U;
+      usart->info->flags                      = 0U;
+      usart->info->xfer.send_active           = 0U;
+
+      usart->info->flags = USART_FLAG_POWERED | USART_FLAG_INITIALIZED;
+
+      // Clear and Enable USART IRQ
+      NVIC_ClearPendingIRQ(usart->irq_num);
+      NVIC_EnableIRQ(usart->irq_num);
+
+      break;
+
+    default: return ARM_DRIVER_ERROR_UNSUPPORTED;
+  }
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t USART_Send (const void            *data,
+                                         uint32_t         num,
+                                         USART_RESOURCES *usart)
+  \brief       Start sending data to USART transmitter.
+  \param[in]   data  Pointer to buffer with data to send to USART transmitter
+  \param[in]   num   Number of data items to send
+  \param[in]   usart Pointer to USART resources
+  \return      \ref execution_status
+*/
+static int32_t USART_Send (const void            *data,
+                                 uint32_t         num,
+                                 USART_RESOURCES *usart) {
+  int32_t stat, source_inc, val;
+
+  if ((data == NULL) || (num == 0U)) {
+    // Invalid parameters
+    return ARM_DRIVER_ERROR_PARAMETER;
+  }
+
+  if ((usart->info->flags & USART_FLAG_CONFIGURED) == 0U) {
+    // USART is not configured (mode not selected)
+    return ARM_DRIVER_ERROR;
+  }
+
+  if (usart->info->xfer.send_active != 0U) {
+    // Send is not completed yet
+    return ARM_DRIVER_ERROR_BUSY;
+  }
+
+  // Set Send active flag
+  usart->info->xfer.send_active = 1U;
+
+  // For DMA mode: source increment
+  source_inc = GPDMA_CH_CONTROL_SI;
+
+  // Synchronous mode
+  if ((usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_MASTER) ||
+      (usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_SLAVE )) {
+    if (usart->info->xfer.sync_mode == 0U) {
+      usart->info->xfer.sync_mode = USART_SYNC_MODE_TX;
+      // Start dummy reads
+      stat = USART_Receive (&usart->info->xfer.rx_dump_val, num, usart);
+      if (stat != ARM_DRIVER_OK) { return ARM_DRIVER_ERROR; }
+
+    } else {
+      if (usart->info->xfer.sync_mode == USART_SYNC_MODE_RX) {
+        // Dummy DMA writes (do not increment source address)
+        source_inc = 0U;
+      }
+    }
+  }
+
+  // Save transmit buffer info
+  usart->info->xfer.tx_buf = (uint8_t *)data;
+  usart->info->xfer.tx_num = num;
+  usart->info->xfer.tx_cnt = 0U;
+
+  // DMA mode
+  if (usart->dma_tx) {
+
+    // Configure DMA mux
+    GPDMA_PeripheralSelect (usart->dma_tx->peripheral, usart->dma_tx->peripheral_sel);
+
+    // Configure DMA channel
+    stat = GPDMA_ChannelConfigure (usart->dma_tx->channel,
+                                   (uint32_t)data,
+                                   (uint32_t)(&(usart->reg->THR)),
+                                   num,
+                                   GPDMA_CH_CONTROL_SBSIZE(GPDMA_BSIZE_1)                   |
+                                   GPDMA_CH_CONTROL_DBSIZE(GPDMA_BSIZE_1)                   |
+                                   GPDMA_CH_CONTROL_SWIDTH(GPDMA_WIDTH_BYTE)                |
+                                   GPDMA_CH_CONTROL_DWIDTH(GPDMA_WIDTH_BYTE)                |
+                                   GPDMA_CH_CONTROL_S                                       |
+                                   GPDMA_CH_CONTROL_D                                       |
+                                   GPDMA_CH_CONTROL_I                                       |
+                                   source_inc,
+                                   GPDMA_CH_CONFIG_DEST_PERI(usart->dma_tx->peripheral) |
+                                   GPDMA_CH_CONFIG_FLOWCNTRL(GPDMA_TRANSFER_M2P_CTRL_DMA)   |
+                                   GPDMA_CH_CONFIG_IE                                       |
+                                   GPDMA_CH_CONFIG_ITC                                      |
+                                   GPDMA_CH_CONFIG_E,
+                                   usart->dma_tx->cb_event);
+  if (stat == -1) { return ARM_DRIVER_ERROR; }
+
+  // Interrupt mode
+  } else {
+    // Fill TX FIFO
+    if (usart->reg->LSR & USART_LSR_THRE) {
+      val = 16U;
+      while ((val--) && (usart->info->xfer.tx_cnt != usart->info->xfer.tx_num)) {
+        usart->reg->THR = usart->info->xfer.tx_buf[usart->info->xfer.tx_cnt++];
+      }
+    }
+
+    // Enable transmit holding register empty interrupt
+    usart->reg->IER |= USART_IER_THREIE;
+  }
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t USART_Receive (void            *data,
+                                      uint32_t         num,
+                                      USART_RESOURCES *usart)
+  \brief       Start receiving data from USART receiver.
+  \param[out]  data  Pointer to buffer for data to receive from USART receiver
+  \param[in]   num   Number of data items to receive
+  \param[in]   usart Pointer to USART resources
+  \return      \ref execution_status
+*/
+static int32_t USART_Receive (void            *data,
+                              uint32_t         num,
+                              USART_RESOURCES *usart) {
+
+  int32_t stat, dest_inc;
+
+  if ((data == NULL) || (num == 0U)) {
+    // Invalid parameters
+    return ARM_DRIVER_ERROR_PARAMETER;
+  }
+
+  if ((usart->info->flags & USART_FLAG_CONFIGURED) == 0U) {
+    // USART is not configured (mode not selected)
+    return ARM_DRIVER_ERROR;
+  }
+
+  // Check if receiver is busy
+  if (usart->info->rx_status.rx_busy == 1U) {
+    return ARM_DRIVER_ERROR_BUSY;
+  }
+
+  // Set RX busy flag
+  usart->info->rx_status.rx_busy = 1U;
+
+  dest_inc = GPDMA_CH_CONTROL_DI;
+
+  // Save number of data to be received
+  usart->info->xfer.rx_num = num;
+
+  // Clear RX statuses
+  usart->info->rx_status.rx_break          = 0U;
+  usart->info->rx_status.rx_framing_error  = 0U;
+  usart->info->rx_status.rx_overflow       = 0U;
+  usart->info->rx_status.rx_parity_error   = 0U;
+
+  // Save receive buffer info
+  usart->info->xfer.rx_buf = (uint8_t *)data;
+  usart->info->xfer.rx_cnt =                0U;
+
+  // Synchronous mode
+  if ((usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_MASTER) ||
+      (usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_SLAVE )) {
+    if (usart->info->xfer.sync_mode == USART_SYNC_MODE_TX) {
+      // Dummy DMA reads (do not increment destination address)
+      dest_inc = 0U;
+    }
+  }
+
+  // DMA mode
+  if (usart->dma_rx) {
+
+    GPDMA_PeripheralSelect (usart->dma_rx->peripheral, usart->dma_rx->peripheral_sel);
+    stat = GPDMA_ChannelConfigure (usart->dma_rx->channel,
+                                   (uint32_t)&usart->reg->RBR,
+                                   (uint32_t)data,
+                                   num,
+                                   GPDMA_CH_CONTROL_SBSIZE(GPDMA_BSIZE_1)                   |
+                                   GPDMA_CH_CONTROL_DBSIZE(GPDMA_BSIZE_1)                   |
+                                   GPDMA_CH_CONTROL_SWIDTH(GPDMA_WIDTH_BYTE)                |
+                                   GPDMA_CH_CONTROL_DWIDTH(GPDMA_WIDTH_BYTE)                |
+                                   GPDMA_CH_CONTROL_S                                       |
+                                   GPDMA_CH_CONTROL_D                                       |
+                                   GPDMA_CH_CONTROL_I                                       |
+                                   dest_inc,
+                                   GPDMA_CH_CONFIG_SRC_PERI(usart->dma_rx->peripheral)      |
+                                   GPDMA_CH_CONFIG_FLOWCNTRL(GPDMA_TRANSFER_P2M_CTRL_DMA)   |
+                                   GPDMA_CH_CONFIG_IE                                       |
+                                   GPDMA_CH_CONFIG_ITC                                      |
+                                   GPDMA_CH_CONFIG_E,
+                                   usart->dma_rx->cb_event);
+  if (stat == -1) { return ARM_DRIVER_ERROR; }
+
+  // Interrupt mode
+  } else {
+    // Enable receive data available interrupt
+    usart->reg->IER |= USART_IER_RBRIE;
+  }
+
+  // Synchronous mode
+  if ((usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_MASTER) ||
+      (usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_SLAVE )) {
+    if (usart->info->xfer.sync_mode == 0U) {
+      usart->info->xfer.sync_mode = USART_SYNC_MODE_RX;
+      // Send dummy data
+      stat = USART_Send (&usart->info->xfer.tx_def_val, num, usart);
+      if (stat != ARM_DRIVER_OK) { return ARM_DRIVER_ERROR; }
+    }
+  }
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t USART_Transfer (const void             *data_out,
+                                             void             *data_in,
+                                             uint32_t          num,
+                                             USART_RESOURCES  *usart)
+  \brief       Start sending/receiving data to/from USART transmitter/receiver.
+  \param[in]   data_out  Pointer to buffer with data to send to USART transmitter
+  \param[out]  data_in   Pointer to buffer for data to receive from USART receiver
+  \param[in]   num       Number of data items to transfer
+  \param[in]   usart     Pointer to USART resources
+  \return      \ref execution_status
+*/
+static int32_t USART_Transfer (const void             *data_out,
+                                     void             *data_in,
+                                     uint32_t          num,
+                                     USART_RESOURCES  *usart) {
+  int32_t status;
+
+  if ((data_out == NULL) || (data_in == NULL) || (num == 0U)) {
+    // Invalid parameters
+    return ARM_DRIVER_ERROR_PARAMETER;
+  }
+
+  if ((usart->info->flags & USART_FLAG_CONFIGURED) == 0U) {
+    // USART is not configured
+    return ARM_DRIVER_ERROR;
+  }
+
+  if ((usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_MASTER) ||
+      (usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_SLAVE )) {
+
+    // Set xfer mode
+    usart->info->xfer.sync_mode = USART_SYNC_MODE_TX_RX;
+
+    // Receive
+    status = USART_Receive (data_in, num, usart);
+    if (status != ARM_DRIVER_OK) { return status; }
+
+    // Send
+    status = USART_Send (data_out, num, usart);
+    if (status != ARM_DRIVER_OK) { return status; }
+
+  } else {
+    // Only in synchronous mode
+    return ARM_DRIVER_ERROR;
+  }
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          uint32_t USART_GetTxCount (USART_RESOURCES *usart)
+  \brief       Get transmitted data count.
+  \param[in]   usart     Pointer to USART resources
+  \return      number of data items transmitted
+*/
+static uint32_t USART_GetTxCount (USART_RESOURCES *usart) {
+  uint32_t cnt;
+
+  if (usart->dma_tx) {
+    cnt = GPDMA_ChannelGetCount (usart->dma_tx->channel);
+  } else {
+    cnt = usart->info->xfer.tx_cnt;
+  }
+
+  return cnt;
+}
+
+/**
+  \fn          uint32_t USART_GetRxCount (USART_RESOURCES *usart)
+  \brief       Get received data count.
+  \param[in]   usart     Pointer to USART resources
+  \return      number of data items received
+*/
+static uint32_t USART_GetRxCount (USART_RESOURCES *usart) {
+  uint32_t cnt;
+
+  if (usart->dma_rx) {
+    cnt = GPDMA_ChannelGetCount (usart->dma_rx->channel);
+  } else {
+    cnt = usart->info->xfer.rx_cnt;
+  }
+
+  return cnt;
+}
+
+/**
+  \fn          int32_t USART_Control (uint32_t          control,
+                                      uint32_t          arg,
+                                      USART_RESOURCES  *usart)
+  \brief       Control USART Interface.
+  \param[in]   control  Operation
+  \param[in]   arg      Argument of operation (optional)
+  \param[in]   usart    Pointer to USART resources
+  \return      common \ref execution_status and driver specific \ref usart_execution_status
+*/
+static int32_t USART_Control (uint32_t          control,
+                              uint32_t          arg,
+                              USART_RESOURCES  *usart) {
+  uint32_t val, mode;
+  uint32_t syncctrl, hden, icr, scictrl, lcr, mcr;
+
+  if ((usart->info->flags & USART_FLAG_POWERED) == 0U) {
+    // USART not powered
+    return ARM_DRIVER_ERROR;
+  }
+
+  syncctrl = 0U;
+  hden     = 0U;
+  icr      = 0U;
+  scictrl  = 0U;
+  lcr      = 0U;
+
+  switch (control & ARM_USART_CONTROL_Msk) {
+    // Control TX
+    case ARM_USART_CONTROL_TX:
+      // Check if TX line available
+      if (usart->pins.tx == NULL) { return ARM_DRIVER_ERROR; }
+      if (arg) {
+        if (usart->info->mode != ARM_USART_MODE_SMART_CARD) {
+          // USART TX pin function selected
+          SCU_PinConfigure(usart->pins.tx->port, usart->pins.tx->num, SCU_PIN_CFG_INPUT_FILTER_DIS |
+                           SCU_PIN_CFG_MODE(usart->pins.tx->config_val));
+        }
+        usart->info->flags |= USART_FLAG_TX_ENABLED;
+        usart->reg->TER    |= USART_TER_TXEN;
+      } else {
+        usart->info->flags &= ~USART_FLAG_TX_ENABLED;
+        usart->reg->TER &= ~USART_TER_TXEN;
+        if (usart->info->mode != ARM_USART_MODE_SMART_CARD) {
+          // GPIO pin function selected
+          SCU_PinConfigure(usart->pins.tx->port, usart->pins.tx->num, SCU_PIN_CFG_INPUT_FILTER_DIS |
+                           SCU_PIN_CFG_MODE(SCU_CFG_MODE_FUNC0));
+        }
+      }
+      return ARM_DRIVER_OK;
+
+    // Control RX
+    case ARM_USART_CONTROL_RX:
+      if (usart->pins.rx == NULL) { return ARM_DRIVER_ERROR; }
+      // RX Line interrupt enable (overrun, framing, parity error, break)
+      if (arg) {
+        if ((usart->info->mode != ARM_USART_MODE_SMART_CARD)   &&
+            (usart->info->mode != ARM_USART_MODE_SINGLE_WIRE )) {
+          // USART RX pin function selected
+          SCU_PinConfigure(usart->pins.rx->port, usart->pins.rx->num,
+                           SCU_PIN_CFG_INPUT_BUFFER_EN | SCU_PIN_CFG_INPUT_FILTER_DIS |
+                           SCU_PIN_CFG_MODE(usart->pins.rx->config_val));
+        }
+        usart->info->flags |= USART_FLAG_RX_ENABLED;
+        usart->reg->RS485CTRL &= ~USART_RS485CTRL_RXDIS;
+        usart->reg->IER |= USART_IER_RXIE;
+      } else {
+        usart->info->flags &= ~USART_FLAG_RX_ENABLED;
+        usart->reg->RS485CTRL |= USART_RS485CTRL_RXDIS;
+        usart->reg->IER &= ~USART_IER_RXIE;
+        if ((usart->info->mode != ARM_USART_MODE_SMART_CARD)   &&
+            (usart->info->mode != ARM_USART_MODE_SINGLE_WIRE )) {
+          // GPIO pin function selected
+          SCU_PinConfigure(usart->pins.rx->port, usart->pins.rx->num, SCU_PIN_CFG_INPUT_FILTER_DIS |
+                           SCU_PIN_CFG_MODE(SCU_CFG_MODE_FUNC0));
+        }
+      }
+      return ARM_DRIVER_OK;
+
+    // Control break
+    case ARM_USART_CONTROL_BREAK:
+      if (arg) {
+        if (usart->info->xfer.send_active != 0U) { return ARM_DRIVER_ERROR_BUSY; }
+
+        usart->reg->LCR |= USART_LCR_BC;
+
+        // Set Send active flag
+        usart->info->xfer.send_active = 1U;
+      }
+      else {
+        usart->reg->LCR &= ~USART_LCR_BC;
+
+        // Clear Send active flag
+        usart->info->xfer.send_active = 0U;
+      }
+      return ARM_DRIVER_OK;
+
+    // Abort Send
+    case ARM_USART_ABORT_SEND:
+      // Disable transmit holding register empty interrupt
+      usart->reg->IER &= ~USART_IER_THREIE;
+
+      // Set trigger level
+      val  = (usart->trig_lvl & USART_FCR_RXTRIGLVL_MSK) | USART_FCR_FIFOEN;
+      if (usart->dma_rx || usart->dma_tx) {
+        val |= USART_FCR_DMAMODE;
+      }
+
+      // Transmit FIFO reset
+      val |= USART_FCR_TXFIFORES;
+      usart->reg->FCR = val;
+
+      // If DMA mode - disable DMA channel
+      if ((usart->dma_tx) && (usart->info->xfer.send_active != 0U)) {
+        GPDMA_ChannelDisable (usart->dma_tx->channel);
+      }
+
+      // Clear Send active flag
+      usart->info->xfer.send_active = 0U;
+      return ARM_DRIVER_OK;
+
+    // Abort receive
+    case ARM_USART_ABORT_RECEIVE:
+      // Disable receive data available interrupt
+      usart->reg->IER &= ~USART_IER_RBRIE;
+
+      // Set trigger level
+      val  = (usart->trig_lvl & USART_FCR_RXTRIGLVL_MSK) |
+              USART_FCR_FIFOEN;
+      if (usart->dma_rx || usart->dma_tx) {
+        val |= USART_FCR_DMAMODE;
+      }
+
+      // Receive FIFO reset
+      val |= USART_FCR_RXFIFORES;
+      usart->reg->FCR = val;
+
+      // If DMA mode - disable DMA channel
+      if ((usart->dma_rx) && (usart->info->rx_status.rx_busy)) {
+        GPDMA_ChannelDisable (usart->dma_rx->channel);
+      }
+
+      // Clear RX busy status
+      usart->info->rx_status.rx_busy = 0U;
+      return ARM_DRIVER_OK;
+
+    // Abort transfer
+    case ARM_USART_ABORT_TRANSFER:
+      // Disable transmit holding register empty and 
+      // receive data available interrupts
+      usart->reg->IER &= ~(USART_IER_THREIE | USART_IER_RBRIE);
+
+      // If DMA mode - disable DMA channel
+      if ((usart->dma_tx) && (usart->info->xfer.send_active != 0U)) {
+        GPDMA_ChannelDisable (usart->dma_tx->channel);
+      }
+      if ((usart->dma_rx) && (usart->info->rx_status.rx_busy)) {
+        GPDMA_ChannelDisable (usart->dma_rx->channel);
+      }
+
+      // Set trigger level
+      val  = (usart->trig_lvl & USART_FCR_RXTRIGLVL_MSK) | USART_FCR_FIFOEN;
+      if (usart->dma_rx || usart->dma_tx) {
+        val |= USART_FCR_DMAMODE;
+      }
+
+      // Transmit and receive FIFO reset
+      val |= USART_FCR_TXFIFORES | USART_FCR_RXFIFORES;
+      usart->reg->FCR = val;
+
+      // Clear busy statuses
+      usart->info->rx_status.rx_busy = 0U;
+      usart->info->xfer.send_active  = 0U;
+      return ARM_DRIVER_OK;
+
+    default: break;
+  }
+
+  switch (control & ARM_USART_CONTROL_Msk) {
+    case ARM_USART_MODE_ASYNCHRONOUS:
+      mode = ARM_USART_MODE_ASYNCHRONOUS;
+      break;
+    case ARM_USART_MODE_SYNCHRONOUS_MASTER:
+      if (usart->capabilities.synchronous_master) {
+        // Enable synchronous master (SCLK out) mode
+        syncctrl = USART_SYNCCTRL_SYNC | USART_SYNCCTRL_CSRC;
+      } else { return ARM_USART_ERROR_MODE; }
+      mode = ARM_USART_MODE_SYNCHRONOUS_MASTER;
+      break;
+    case ARM_USART_MODE_SYNCHRONOUS_SLAVE:
+      if (usart->capabilities.synchronous_slave) {
+        // Enable synchronous slave (SCLK in) mode
+        syncctrl = USART_SYNCCTRL_SYNC;
+      } else { return ARM_USART_ERROR_MODE; }
+      mode = ARM_USART_MODE_SYNCHRONOUS_SLAVE;
+      break;
+    case ARM_USART_MODE_SINGLE_WIRE:
+      // Enable Half duplex
+      hden = USART_HDEN_HDEN;
+      mode = ARM_USART_MODE_SINGLE_WIRE;
+      break;
+    case ARM_USART_MODE_IRDA:
+      if (usart->capabilities.irda) {
+        // Enable IrDA mode
+        icr = USART_ICR_IRDAEN;
+      } else { return ARM_USART_ERROR_MODE; }
+      mode = ARM_USART_MODE_IRDA;
+      break;
+    case ARM_USART_MODE_SMART_CARD:
+      if (usart->capabilities.smart_card) {
+        // Enable Smart card mode
+        scictrl = USART_SCICTRL_SCIEN;
+      } else { return ARM_USART_ERROR_MODE; }
+      mode = ARM_USART_MODE_SMART_CARD;
+      break;
+
+    // Default TX value
+    case ARM_USART_SET_DEFAULT_TX_VALUE:
+      usart->info->xfer.tx_def_val = arg;
+      return ARM_DRIVER_OK;
+
+    // IrDA pulse
+    case ARM_USART_SET_IRDA_PULSE:
+      if (usart->capabilities.irda) {
+        if (arg == 0U) {
+          usart->reg->ICR &= ~(USART_ICR_FIXPULSEEN);
+        } else {
+          val = 1000000000U / (GetClockFreq (((*usart->clk.base_clk >> 24) & 0x1FU)));
+          icr = usart->reg->ICR & ~USART_ICR_PULSEDIV_MSK;
+          if      (arg <= (2U   * val)) { icr |= (0U << USART_ICR_PULSEDIV_POS); }
+          else if (arg <= (4U   * val)) { icr |= (1U << USART_ICR_PULSEDIV_POS); }
+          else if (arg <= (8U   * val)) { icr |= (2U << USART_ICR_PULSEDIV_POS); }
+          else if (arg <= (16U  * val)) { icr |= (3U << USART_ICR_PULSEDIV_POS); }
+          else if (arg <= (32U  * val)) { icr |= (4U << USART_ICR_PULSEDIV_POS); }
+          else if (arg <= (64U  * val)) { icr |= (5U << USART_ICR_PULSEDIV_POS); }
+          else if (arg <= (128U * val)) { icr |= (6U << USART_ICR_PULSEDIV_POS); }
+          else if (arg <= (256U * val)) { icr |= (7U << USART_ICR_PULSEDIV_POS); }
+          else { return ARM_DRIVER_ERROR; }
+          usart->reg->ICR = icr | USART_ICR_FIXPULSEEN;
+        }
+      } else { return ARM_DRIVER_ERROR; }
+      return ARM_DRIVER_OK;
+
+    // SmartCard guard time
+    case ARM_USART_SET_SMART_CARD_GUARD_TIME:
+      if (usart->capabilities.smart_card) {
+        if (arg > 0xFF) { return ARM_DRIVER_ERROR; }
+        usart->reg->SCICTRL &= ~USART_SCICTRL_GUARDTIME_MSK;
+        usart->reg->SCICTRL |= (arg << USART_SCICTRL_GUARDTIME_POS);
+      } else { return ARM_DRIVER_ERROR; }
+      return ARM_DRIVER_OK;
+
+    // SmartCard clock
+    case ARM_USART_SET_SMART_CARD_CLOCK:
+      if (usart->capabilities.smart_card == 0U) { return ARM_DRIVER_ERROR; }
+      if (arg == 0U)                            { return ARM_DRIVER_OK;    }
+      if (usart->capabilities.smart_card_clock) {
+        if ((usart->info->baudrate * usart->sc_oversamp) != arg) {
+          return ARM_DRIVER_ERROR;
+        }
+      } else { return ARM_DRIVER_ERROR; }
+      return ARM_DRIVER_OK;
+
+     // SmartCard NACK
+    case ARM_USART_CONTROL_SMART_CARD_NACK:
+      if (usart->capabilities.smart_card) {
+        if (arg) { usart->reg->SCICTRL &= ~USART_SCICTRL_NACKDIS; }
+        else     { usart->reg->SCICTRL |=  USART_SCICTRL_NACKDIS; }
+      } else return ARM_DRIVER_ERROR;
+      return ARM_DRIVER_OK;
+
+    // Unsupported command
+    default: return ARM_DRIVER_ERROR_UNSUPPORTED;
+  }
+
+  // Check if Receiver/Transmitter is busy
+  if ( usart->info->rx_status.rx_busy ||
+      (usart->info->xfer.send_active != 0U)) {
+    return ARM_DRIVER_ERROR_BUSY;
+  }
+
+  // USART Data bits
+  switch (control & ARM_USART_DATA_BITS_Msk) {
+    case ARM_USART_DATA_BITS_5: lcr |= (0U << USART_LCR_WLS_POS); break;
+    case ARM_USART_DATA_BITS_6: lcr |= (1U << USART_LCR_WLS_POS); break;
+    case ARM_USART_DATA_BITS_7: lcr |= (2U << USART_LCR_WLS_POS); break;
+    case ARM_USART_DATA_BITS_8: lcr |= (3U << USART_LCR_WLS_POS); break;
+    default: return ARM_USART_ERROR_DATA_BITS;
+  }
+
+  // USART Parity
+  switch (control & ARM_USART_PARITY_Msk) {
+    case ARM_USART_PARITY_NONE:                                  break;
+    case ARM_USART_PARITY_EVEN: lcr |= (1U << USART_LCR_PS_POS) |
+                                              USART_LCR_PE;      break;
+    case ARM_USART_PARITY_ODD:  lcr |= USART_LCR_PE;             break;
+    default: return (ARM_USART_ERROR_PARITY);
+  }
+
+  // USART Stop bits
+  switch (control & ARM_USART_STOP_BITS_Msk) {
+    case ARM_USART_STOP_BITS_1:                       break;
+    case ARM_USART_STOP_BITS_2: lcr |= USART_LCR_SBS; break;
+    default: return ARM_USART_ERROR_STOP_BITS;
+  }
+
+  // USART Flow control (RTS and CTS lines are only available on USART1)
+  if (usart->uart_reg != NULL) {
+    mcr = usart->uart_reg->MCR & ~(UART_MCR_RTSEN | UART_MCR_CTSEN);
+    switch (control & ARM_USART_FLOW_CONTROL_Msk) {
+      case ARM_USART_FLOW_CONTROL_NONE:
+        break;
+      case ARM_USART_FLOW_CONTROL_RTS:
+        if (usart->capabilities.flow_control_rts) {
+          mcr |= UART_MCR_RTSEN;
+        }
+        else  { return ARM_USART_ERROR_FLOW_CONTROL; }
+        break;
+      case ARM_USART_FLOW_CONTROL_CTS:
+        if (usart->capabilities.flow_control_cts) {
+          mcr |= UART_MCR_CTSEN;
+        } else { 
+          return ARM_USART_ERROR_FLOW_CONTROL;
+        }
+        break;
+      case ARM_USART_FLOW_CONTROL_RTS_CTS:
+        if (usart->capabilities.flow_control_rts && 
+            usart->capabilities.flow_control_cts) {
+          mcr |= (UART_MCR_RTSEN | UART_MCR_CTSEN);
+        } else {
+          return ARM_USART_ERROR_FLOW_CONTROL;
+        }
+        break;
+      default: { return ARM_USART_ERROR_FLOW_CONTROL; }
+    }
+  }
+
+  // Clock setting for synchronous mode
+  if ((mode == ARM_USART_MODE_SYNCHRONOUS_MASTER) ||
+      (mode == ARM_USART_MODE_SYNCHRONOUS_SLAVE )) {
+
+    // Only CPOL0 - CPHA1 combination available
+
+    // USART clock polarity
+    if ((control & ARM_USART_CPOL_Msk) != ARM_USART_CPOL0) {
+      return ARM_USART_ERROR_CPOL;
+    }
+
+    // USART clock phase
+    if ((control & ARM_USART_CPHA_Msk) != ARM_USART_CPHA1) {
+      return ARM_USART_ERROR_CPHA;
+    }
+  }
+
+  // USART Baudrate
+  if (USART_SetBaudrate (arg, usart) == -1) {
+    return ARM_USART_ERROR_BAUDRATE;
+  }
+
+  // Configuration is OK - Mode is valid
+  usart->info->mode = mode;
+
+  // Configure TX pin regarding mode and transmitter state
+  val = SCU_PIN_CFG_INPUT_FILTER_DIS;
+  switch (usart->info->mode) {
+    case ARM_USART_MODE_SMART_CARD:
+      // Pin function = USART TX
+      val |= SCU_PIN_CFG_MODE(usart->pins.tx->config_val);
+      break;
+    default:
+      // Synchronous master/slave, asynchronous, single-wire and IrDA mode
+      if (usart->info->flags & USART_FLAG_TX_ENABLED) {
+        // Pin function = USART TX
+        val |= SCU_PIN_CFG_MODE(usart->pins.tx->config_val);
+      } else {
+        // Pin function = GPIO
+        val |= SCU_PIN_CFG_MODE(SCU_CFG_MODE_FUNC0);
+      }
+  }
+  SCU_PinConfigure(usart->pins.tx->port, usart->pins.tx->num, val);
+
+  // Configure RX pin regarding mode and receiver state
+  val = SCU_PIN_CFG_INPUT_FILTER_DIS;
+  switch (usart->info->mode) {
+    case ARM_USART_MODE_SINGLE_WIRE:
+    case ARM_USART_MODE_SMART_CARD:
+      // Pin function = GPIO
+      val |= SCU_PIN_CFG_MODE(SCU_CFG_MODE_FUNC0);
+      break;
+    default:
+      // Synchronous master/slave, asynchronous and  IrDA mode
+      if (usart->info->flags & USART_FLAG_RX_ENABLED) {
+        // Pin function = USART RX
+        val |= SCU_PIN_CFG_INPUT_BUFFER_EN | 
+               SCU_PIN_CFG_MODE(usart->pins.rx->config_val);
+      } else {
+        // Pin function = GPIO
+        val |= SCU_PIN_CFG_MODE(SCU_CFG_MODE_FUNC0);
+      }
+      break;
+  }
+  SCU_PinConfigure(usart->pins.rx->port, usart->pins.rx->num, val);
+
+  // Configure CLK pin regarding mode
+  if (usart->pins.clk) {
+    val = SCU_PIN_CFG_INPUT_FILTER_DIS;
+    switch (usart->info->mode) {
+      case ARM_USART_MODE_SMART_CARD:
+      case ARM_USART_MODE_SYNCHRONOUS_MASTER:
+        // Pin function = USART UCLK (output)
+        val |= SCU_PIN_CFG_MODE(usart->pins.clk->config_val);
+        break;
+      case ARM_USART_MODE_SYNCHRONOUS_SLAVE:
+        // Pin function = USART UCLK (input)
+        val |= SCU_PIN_CFG_INPUT_BUFFER_EN |
+               SCU_PIN_CFG_MODE(usart->pins.clk->config_val);
+        break;
+      default:
+        // Asynchronous, Single-wire and IrDA mode
+        // Pin function = GPIO
+        val |= SCU_PIN_CFG_INPUT_BUFFER_EN |
+               SCU_PIN_CFG_MODE(SCU_CFG_MODE_FUNC0);
+    }
+    SCU_PinConfigure(usart->pins.clk->port, usart->pins.clk->num, val);
+  }
+
+  // Configure SYNCCRTL register (only in synchronous mode)
+  if (usart->capabilities.synchronous_master ||
+      usart->capabilities.synchronous_slave) {
+    usart->reg->SYNCCTRL = USART_SYNCCTRL_FES    |
+                           USART_SYNCCTRL_SSSDIS |
+                           syncctrl;
+  }
+
+  // Configure HDEN register (only in single wire mode)
+  if (usart->capabilities.single_wire) {
+    usart->reg->HDEN = hden;
+  }
+
+  // Configure ICR register (only in IrDA mode)
+  if (usart->capabilities.irda) {
+    usart->reg->ICR = (usart->reg->ICR & ~USART_ICR_IRDAEN) | icr;
+  }
+
+  // Configure SCICTRL register (only in Smart Card mode)
+  if (usart->capabilities.smart_card) {
+    usart->reg->SCICTRL = (usart->reg->SCICTRL & ~USART_SCICTRL_SCIEN) |
+                           scictrl;
+  }
+
+  // Configure MCR register (modem line for USART1)
+  if (usart->uart_reg) {
+    usart->uart_reg->MCR = ((usart->uart_reg->MCR & ~(UART_MCR_RTSEN |
+                             UART_MCR_CTSEN))) | mcr;
+  }
+
+  // Configure Line control register
+  usart->reg->LCR = ((usart->reg->LCR & (USART_LCR_BC | USART_LCR_DLAB)) | lcr);
+
+  // Set configured flag
+  usart->info->flags |= USART_FLAG_CONFIGURED;
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          ARM_USART_STATUS USART_GetStatus (USART_RESOURCES *usart)
+  \brief       Get USART status.
+  \param[in]   usart     Pointer to USART resources
+  \return      USART status \ref ARM_USART_STATUS
+*/
+static ARM_USART_STATUS USART_GetStatus (USART_RESOURCES *usart) {
+  ARM_USART_STATUS stat;
+
+  stat.tx_busy          = (usart->reg->LSR & USART_LSR_TEMT ? (0U) : (1U));
+  stat.rx_busy          = usart->info->rx_status.rx_busy;
+  stat.tx_underflow     = 0U;
+  stat.rx_overflow      = usart->info->rx_status.rx_overflow;
+  stat.rx_break         = usart->info->rx_status.rx_break;
+  stat.rx_framing_error = usart->info->rx_status.rx_framing_error;
+  stat.rx_parity_error  = usart->info->rx_status.rx_parity_error;
+  return stat;
+}
+
+/**
+  \fn          int32_t USART_SetModemControl (ARM_USART_MODEM_CONTROL  control,
+                                              USART_RESOURCES         *usart)
+  \brief       Set USART Modem Control line state.
+  \param[in]   control   \ref ARM_USART_MODEM_CONTROL
+  \param[in]   usart     Pointer to USART resources
+  \return      \ref execution_status
+*/
+static int32_t USART_SetModemControl (ARM_USART_MODEM_CONTROL  control,
+                                      USART_RESOURCES         *usart) {
+
+  if ((usart->info->flags & USART_FLAG_CONFIGURED) == 0U) {
+    // USART is not configured
+    return ARM_DRIVER_ERROR;
+  }
+
+  // Only UART1 supports modem lines
+  if (usart->uart_reg == NULL) { return ARM_DRIVER_ERROR_UNSUPPORTED; }
+
+  if (control == ARM_USART_RTS_CLEAR) {
+    if (usart->capabilities.rts) { usart->uart_reg->MCR &= ~UART_MCR_RTSCTRL; }
+    else                         { return ARM_DRIVER_ERROR_UNSUPPORTED;       }
+  }
+  if (control == ARM_USART_RTS_SET) {
+    if (usart->capabilities.rts) { usart->uart_reg->MCR |=  UART_MCR_RTSCTRL; }
+    else                         {return ARM_DRIVER_ERROR_UNSUPPORTED;        }
+  }
+  if (control == ARM_USART_DTR_CLEAR) {
+    if (usart->capabilities.dtr) { usart->uart_reg->MCR &= ~UART_MCR_DTRCTRL; }
+    else                         { return ARM_DRIVER_ERROR_UNSUPPORTED;       }
+  }
+  if (control == ARM_USART_DTR_SET) {
+    if (usart->capabilities.dtr) { usart->uart_reg->MCR |=  UART_MCR_DTRCTRL; }
+    else                         { return ARM_DRIVER_ERROR_UNSUPPORTED;       }
+  }
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          ARM_USART_MODEM_STATUS USART_GetModemStatus (USART_RESOURCES *usart)
+  \brief       Get USART Modem Status lines state.
+  \param[in]   usart     Pointer to USART resources
+  \return      modem status \ref ARM_USART_MODEM_STATUS
+*/
+static ARM_USART_MODEM_STATUS USART_GetModemStatus (USART_RESOURCES *usart) {
+  ARM_USART_MODEM_STATUS modem_status;
+  uint32_t msr;
+
+  if (usart->uart_reg &&
+     (usart->info->flags & USART_FLAG_CONFIGURED)) {
+
+    msr = usart->uart_reg->MSR;
+
+    if (usart->capabilities.cts) { modem_status.cts = (msr & UART_MSR_CTS ? (1U) : (0U)); }
+    else                         { modem_status.cts = 0U; }
+    if (usart->capabilities.dsr) { modem_status.dsr = (msr & UART_MSR_DSR ? (1U) : (0U)); }
+    else                         { modem_status.dsr = 0U; }
+    if (usart->capabilities.ri ) { modem_status.ri  = (msr & UART_MSR_RI  ? (1U) : (0U)); }
+    else                         { modem_status.ri  = 0U; }
+    if (usart->capabilities.dcd) { modem_status.dcd = (msr & UART_MSR_DCD ? (1U) : (0U)); }
+    else                         { modem_status.dcd = 0U; }
+  } else {
+     modem_status.cts = 0U;
+     modem_status.dsr = 0U;
+     modem_status.ri  = 0U;
+     modem_status.dcd = 0U;
+  }
+
+  return modem_status;
+}
+
+/**
+  \fn          void USART_IRQHandler (UART_RESOURCES *usart)
+  \brief       USART Interrupt handler.
+  \param[in]   usart     Pointer to USART resources
+*/
+static void USART_IRQHandler (USART_RESOURCES *usart) {
+  uint32_t iir, event, val, i;
+
+  event = 0U;
+  iir   = usart->reg->IIR;
+
+  if ((iir & USART_IIR_INTSTATUS) == 0U) {
+
+    // Transmit holding register empty
+    if ((iir & USART_IIR_INTID_MSK) == USART_IIR_INTID_THRE) {
+      val = 16U;
+      while ((val --) && (usart->info->xfer.tx_num != usart->info->xfer.tx_cnt)) {
+        if (((usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_MASTER)  ||
+             (usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_SLAVE )) &&
+             (usart->info->xfer.sync_mode == USART_SYNC_MODE_RX)) {
+          // Dummy write in synchronous receive only mode
+          usart->reg->THR = usart->info->xfer.tx_def_val;
+        } else {
+          // Write data to Tx FIFO
+          usart->reg->THR = usart->info->xfer.tx_buf[usart->info->xfer.tx_cnt];
+        }
+        usart->info->xfer.tx_cnt++;
+      }
+
+      // Check if all data is transmitted
+      if (usart->info->xfer.tx_num == usart->info->xfer.tx_cnt) {
+        // Disable THRE interrupt
+        usart->reg->IER &= ~USART_IER_THREIE;
+
+        // Clear TX busy flag
+        usart->info->xfer.send_active = 0U;
+
+        // Set send complete event
+        if ((usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_MASTER) ||
+            (usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_SLAVE )) {
+          if ((usart->info->xfer.sync_mode == USART_SYNC_MODE_TX)    &&
+              ((usart->info->flags & USART_FLAG_RX_ENABLED) == 0U)) {
+            event |= ARM_USART_EVENT_SEND_COMPLETE;
+          }
+        } else {
+          event |= ARM_USART_EVENT_SEND_COMPLETE;
+        }
+      }
+    }
+
+    // Receive line status
+    if ((iir & USART_IIR_INTID_MSK) == USART_IIR_INTID_RLS) {
+      event |= USART_RxLineIntHandler(usart);
+    }
+
+    // Receive data available and Character time-out indicator interrupt
+    if (((iir & USART_IIR_INTID_MSK) == USART_IIR_INTID_RDA)  ||
+        ((iir & USART_IIR_INTID_MSK) == USART_IIR_INTID_CTI)) {
+
+      switch (usart->trig_lvl) {
+        case USART_TRIG_LVL_1:  i = 1U;  break;
+        case USART_TRIG_LVL_4:  i = 3U;  break;
+        case USART_TRIG_LVL_8:  i = 7U;  break;
+        case USART_TRIG_LVL_14: i = 13U; break;
+      }
+
+      // Get available data from RX FIFO
+      while ((usart->reg->LSR & USART_LSR_RDR) && (i--)) {
+        // Check RX line interrupt for errors
+        event |= USART_RxLineIntHandler (usart);
+
+        if (((usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_MASTER)  ||
+             (usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_SLAVE )) &&
+             (usart->info->xfer.sync_mode == USART_SYNC_MODE_TX)) {
+          // Dummy read in synchronous transmit only mode
+          usart->reg->RBR;
+        } else {
+          // Read data from RX FIFO into receive buffer
+          usart->info->xfer.rx_buf[usart->info->xfer.rx_cnt] = usart->reg->RBR;
+        }
+
+        usart->info->xfer.rx_cnt++;
+
+        // Check if requested amount of data is received
+        if (usart->info->xfer.rx_cnt == usart->info->xfer.rx_num) {
+          // Disable RDA interrupt
+          usart->reg->IER &= ~USART_IER_RBRIE;
+
+          // Clear RX busy flag and set receive transfer complete event
+          usart->info->rx_status.rx_busy = 0U;
+          if ((usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_MASTER) ||
+              (usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_SLAVE )) {
+            val = usart->info->xfer.sync_mode;
+            usart->info->xfer.sync_mode = 0U;
+            switch (val) {
+              case USART_SYNC_MODE_TX:
+                event |= ARM_USART_EVENT_SEND_COMPLETE;
+                break;
+              case USART_SYNC_MODE_RX:
+                event |= ARM_USART_EVENT_RECEIVE_COMPLETE;
+                break;
+              case USART_SYNC_MODE_TX_RX:
+                event |= ARM_USART_EVENT_TRANSFER_COMPLETE;
+                break;
+              default: break;
+            }
+          } else {
+            event |= ARM_USART_EVENT_RECEIVE_COMPLETE;
+          }
+          break;
+        }
+      }
+    }
+
+    // Character time-out indicator
+    if ((iir & USART_IIR_INTID_MSK) == USART_IIR_INTID_CTI) {
+      if ((usart->info->mode != ARM_USART_MODE_SYNCHRONOUS_MASTER) &&
+          (usart->info->mode != ARM_USART_MODE_SYNCHRONOUS_SLAVE )) {
+        // Signal RX Time-out event, if not all requested data received
+        if (usart->info->xfer.rx_cnt != usart->info->xfer.rx_num) {
+          event |= ARM_USART_EVENT_RX_TIMEOUT;
+        }
+      }
+    }
+
+    // Modem interrupt (UART1 only)
+#if (RTE_UART1)
+    if (usart->uart_reg) {
+      if ((iir & USART_IIR_INTID_MSK) == UART_IIR_INTID_MS) {
+        // Save modem status register
+        val = usart->uart_reg->MSR;
+      
+        // CTS state changed
+        if ((usart->capabilities.cts) && (val & UART_MSR_DCTS)) {
+          event |= ARM_USART_EVENT_CTS;
+        }
+        // DSR state changed
+        if ((usart->capabilities.dsr) && (val & UART_MSR_DDSR)) {
+          event |= ARM_USART_EVENT_DSR;
+        }
+        // Ring indicator
+        if ((usart->capabilities.ri)  && (val & UART_MSR_TERI)) {
+          event |= ARM_USART_EVENT_RI;
+        }
+        // DCD state changed
+        if ((usart->capabilities.dcd) && (val & UART_MSR_DDCD)) {
+          event |= ARM_USART_EVENT_DCD;
+        }
+      }
+    }
+#endif
+  }
+  if ((usart->info->cb_event != NULL) && (event != 0U)) {
+    usart->info->cb_event (event);
+  }
+}
+
+#if (((RTE_USART0) && (RTE_USART0_DMA_TX_EN == 1)) || \
+     ((RTE_UART1)  && (RTE_UART1_DMA_TX_EN  == 1)) || \
+     ((RTE_USART2) && (RTE_USART2_DMA_TX_EN == 1)) || \
+     ((RTE_USART3) && (RTE_USART3_DMA_TX_EN == 1)))
+/**
+  \fn          void USART_GPDMA_Tx_Event (uint32_t event, USART_RESOURCES *usart)
+  \brief       UART Interrupt handler.
+  \param[in]   usart     Pointer to USART resources
+  \param[in]   event     GPDMA_EVENT_TERMINAL_COUNT_REQUEST / GPDMA_EVENT_ERROR
+*/
+static void USART_GPDMA_Tx_Event (uint32_t event, USART_RESOURCES *usart) {
+  switch (event) {
+    case GPDMA_EVENT_TERMINAL_COUNT_REQUEST:
+      usart->info->xfer.tx_cnt = usart->info->xfer.tx_num;
+      // Clear TX busy flag
+      usart->info->xfer.send_active = 0U;
+
+      // Set Send Complete event for asynchronous transfers
+      if ((usart->info->mode != ARM_USART_MODE_SYNCHRONOUS_MASTER) &&
+          (usart->info->mode != ARM_USART_MODE_SYNCHRONOUS_SLAVE )) {
+        if (usart->info->cb_event) {
+          usart->info->cb_event (ARM_USART_EVENT_SEND_COMPLETE);
+        }
+      }
+      break;
+    case GPDMA_EVENT_ERROR:
+    default:
+      break;
+  }
+}
+#endif
+
+#if (((RTE_USART0) && (RTE_USART0_DMA_RX_EN == 1)) || \
+     ((RTE_UART1)  && (RTE_UART1_DMA_RX_EN  == 1)) || \
+     ((RTE_USART2) && (RTE_USART2_DMA_RX_EN == 1)) || \
+     ((RTE_USART3) && (RTE_USART3_DMA_RX_EN == 1)))
+/**
+  \fn          void USART_GPDMA_Rx_Event (uint32_t event, USART_RESOURCES *usart)
+  \brief       UART Interrupt handler.
+  \param[in]   event     GPDMA_EVENT_TERMINAL_COUNT_REQUEST / GPDMA_EVENT_ERROR
+  \param[in]   usart     Pointer to USART resources
+*/
+static void USART_GPDMA_Rx_Event (uint32_t event, USART_RESOURCES *usart) {
+  uint32_t val, evt;
+
+  evt = 0U;
+
+  switch (event) {
+    case GPDMA_EVENT_TERMINAL_COUNT_REQUEST:
+      usart->info->xfer.rx_cnt    = usart->info->xfer.rx_num; 
+      usart->info->rx_status.rx_busy = 0U;
+
+      if ((usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_MASTER) ||
+          (usart->info->mode == ARM_USART_MODE_SYNCHRONOUS_SLAVE )) {
+        val = usart->info->xfer.sync_mode;
+        usart->info->xfer.sync_mode = 0U;
+        switch (val) {
+          case USART_SYNC_MODE_TX:
+            evt |= ARM_USART_EVENT_SEND_COMPLETE;
+            break;
+          case USART_SYNC_MODE_RX:
+            evt |= ARM_USART_EVENT_RECEIVE_COMPLETE;
+            break;
+          case USART_SYNC_MODE_TX_RX:
+            evt |= ARM_USART_EVENT_TRANSFER_COMPLETE;
+             break;
+          default: break;
+        }
+      } else {
+        evt |= ARM_USART_EVENT_RECEIVE_COMPLETE;
+      }
+      if ((usart->info->cb_event != NULL) && (evt != 0U)) {
+        usart->info->cb_event (evt);
+      }
+      break;
+    case GPDMA_EVENT_ERROR:
+    default:
+      break;
+  }
+}
+#endif
+
+
+#if (RTE_USART0)
+// USART0 Driver Wrapper functions
+static ARM_USART_CAPABILITIES USART0_GetCapabilities (void) {
+  return USART_GetCapabilities (&USART0_Resources);
+}
+static int32_t USART0_Initialize (ARM_USART_SignalEvent_t cb_event) {
+  return USART_Initialize (cb_event, &USART0_Resources);
+}
+static int32_t USART0_Uninitialize (void) {
+  return USART_Uninitialize(&USART0_Resources);
+}
+static int32_t USART0_PowerControl (ARM_POWER_STATE state) {
+  return USART_PowerControl (state, &USART0_Resources);
+}
+static int32_t USART0_Send (const void *data, uint32_t num) {
+  return USART_Send (data, num, &USART0_Resources);
+}
+static int32_t USART0_Receive (void *data, uint32_t num) {
+  return USART_Receive (data, num, &USART0_Resources);
+}
+static int32_t USART0_Transfer (const void      *data_out,
+                                      void      *data_in,
+                                      uint32_t   num) {
+  return USART_Transfer (data_out, data_in, num, &USART0_Resources);
+}
+static uint32_t USART0_GetTxCount (void) {
+  return USART_GetTxCount (&USART0_Resources);
+}
+static uint32_t USART0_GetRxCount (void) {
+  return USART_GetRxCount (&USART0_Resources); 
+}
+static int32_t USART0_Control (uint32_t control, uint32_t arg) {
+  return USART_Control (control, arg, &USART0_Resources);
+}
+static ARM_USART_STATUS USART0_GetStatus (void) {
+  return USART_GetStatus (&USART0_Resources);
+}
+static int32_t USART0_SetModemControl (ARM_USART_MODEM_CONTROL control) {
+  return USART_SetModemControl (control, &USART0_Resources);
+}
+static ARM_USART_MODEM_STATUS USART0_GetModemStatus (void) {
+  return USART_GetModemStatus (&USART0_Resources);
+}
+void UART0_IRQHandler (void) {
+  USART_IRQHandler (&USART0_Resources);
+}
+#if (RTE_USART0_DMA_TX_EN == 1)
+void USART0_GPDMA_Tx_Event (uint32_t event) {
+  USART_GPDMA_Tx_Event(event, &USART0_Resources);
+}
+#endif
+#if (RTE_USART0_DMA_RX_EN == 1)
+void USART0_GPDMA_Rx_Event (uint32_t event) {
+  USART_GPDMA_Rx_Event(event, &USART0_Resources);
+}
+#endif
+
+// USART0 Driver Control Block
+ARM_DRIVER_USART Driver_USART0 = {
+    USARTx_GetVersion,
+    USART0_GetCapabilities,
+    USART0_Initialize,
+    USART0_Uninitialize,
+    USART0_PowerControl,
+    USART0_Send, 
+    USART0_Receive,
+    USART0_Transfer,
+    USART0_GetTxCount,
+    USART0_GetRxCount,
+    USART0_Control,
+    USART0_GetStatus,
+    USART0_SetModemControl,
+    USART0_GetModemStatus
+};
+#endif
+
+#if (RTE_UART1)
+// USART1 Driver Wrapper functions
+static ARM_USART_CAPABILITIES USART1_GetCapabilities (void) {
+  return USART_GetCapabilities (&USART1_Resources);
+}
+static int32_t USART1_Initialize (ARM_USART_SignalEvent_t cb_event) {
+  return USART_Initialize (cb_event, &USART1_Resources);
+}
+static int32_t USART1_Uninitialize (void) {
+  return USART_Uninitialize(&USART1_Resources);
+}
+static int32_t USART1_PowerControl (ARM_POWER_STATE state) {
+  return USART_PowerControl (state, &USART1_Resources);
+}
+static int32_t USART1_Send (const void *data, uint32_t num) {
+  return USART_Send (data, num, &USART1_Resources);
+}
+static int32_t USART1_Receive (void *data, uint32_t num) {
+  return USART_Receive (data, num, &USART1_Resources);
+}
+static int32_t USART1_Transfer (const void      *data_out,
+                                      void      *data_in,
+                                      uint32_t   num) {
+  return USART_Transfer (data_out, data_in, num, &USART1_Resources);
+}
+static uint32_t USART1_GetTxCount (void) {
+  return USART_GetTxCount (&USART1_Resources);
+}
+static uint32_t USART1_GetRxCount (void) {
+  return USART_GetRxCount (&USART1_Resources); 
+}
+static int32_t USART1_Control (uint32_t control, uint32_t arg) {
+  return USART_Control (control, arg, &USART1_Resources);
+}
+static ARM_USART_STATUS USART1_GetStatus (void) {
+  return USART_GetStatus (&USART1_Resources);
+}
+static int32_t USART1_SetModemControl (ARM_USART_MODEM_CONTROL control) {
+  return USART_SetModemControl (control, &USART1_Resources);
+}
+static ARM_USART_MODEM_STATUS USART1_GetModemStatus (void) {
+  return USART_GetModemStatus (&USART1_Resources);
+}
+void UART1_IRQHandler (void) {
+  USART_IRQHandler (&USART1_Resources);
+}
+#if (RTE_UART1_DMA_TX_EN == 1)
+void USART1_GPDMA_Tx_Event (uint32_t event) {
+  USART_GPDMA_Tx_Event(event, &USART1_Resources);
+}
+#endif
+#if (RTE_UART1_DMA_RX_EN == 1)
+void USART1_GPDMA_Rx_Event (uint32_t event) {
+  USART_GPDMA_Rx_Event(event, &USART1_Resources);
+}
+#endif
+
+// USART1 Driver Control Block
+ARM_DRIVER_USART Driver_USART1 = {
+    USARTx_GetVersion,
+    USART1_GetCapabilities,
+    USART1_Initialize,
+    USART1_Uninitialize,
+    USART1_PowerControl,
+    USART1_Send, 
+    USART1_Receive,
+    USART1_Transfer,
+    USART1_GetTxCount,
+    USART1_GetRxCount,
+    USART1_Control,
+    USART1_GetStatus,
+    USART1_SetModemControl,
+    USART1_GetModemStatus
+};
+#endif
+
+#if (RTE_USART2)
+// USART2 Driver Wrapper functions
+static ARM_USART_CAPABILITIES USART2_GetCapabilities (void) {
+  return USART_GetCapabilities (&USART2_Resources);
+}
+static int32_t USART2_Initialize (ARM_USART_SignalEvent_t cb_event) {
+  return USART_Initialize (cb_event, &USART2_Resources);
+}
+static int32_t USART2_Uninitialize (void) {
+  return USART_Uninitialize(&USART2_Resources);
+}
+static int32_t USART2_PowerControl (ARM_POWER_STATE state) {
+  return USART_PowerControl (state, &USART2_Resources);
+}
+static int32_t USART2_Send (const void *data, uint32_t num) {
+  return USART_Send (data, num, &USART2_Resources);
+}
+static int32_t USART2_Receive (void *data, uint32_t num) {
+  return USART_Receive (data, num, &USART2_Resources);
+}
+static int32_t USART2_Transfer (const void      *data_out,
+                                      void      *data_in,
+                                      uint32_t   num) {
+  return USART_Transfer (data_out, data_in, num, &USART2_Resources);
+}
+static uint32_t USART2_GetTxCount (void) {
+  return USART_GetTxCount (&USART2_Resources);
+}
+static uint32_t USART2_GetRxCount (void) {
+  return USART_GetRxCount (&USART2_Resources); 
+}
+static int32_t USART2_Control (uint32_t control, uint32_t arg) {
+  return USART_Control (control, arg, &USART2_Resources);
+}
+static ARM_USART_STATUS USART2_GetStatus (void) {
+  return USART_GetStatus (&USART2_Resources);
+}
+static int32_t USART2_SetModemControl (ARM_USART_MODEM_CONTROL control) {
+  return USART_SetModemControl (control, &USART2_Resources);
+}
+static ARM_USART_MODEM_STATUS USART2_GetModemStatus (void) {
+  return USART_GetModemStatus (&USART2_Resources);
+}
+void UART2_IRQHandler (void) {
+  USART_IRQHandler (&USART2_Resources);
+}
+#if (RTE_USART2_DMA_TX_EN == 1)
+void USART2_GPDMA_Tx_Event (uint32_t event) {
+  USART_GPDMA_Tx_Event(event, &USART2_Resources);
+}
+#endif
+#if (RTE_USART2_DMA_RX_EN == 1)
+void USART2_GPDMA_Rx_Event (uint32_t event) {
+  USART_GPDMA_Rx_Event(event, &USART2_Resources);
+}
+#endif
+
+// USART2 Driver Control Block
+ARM_DRIVER_USART Driver_USART2 = {
+    USARTx_GetVersion,
+    USART2_GetCapabilities,
+    USART2_Initialize,
+    USART2_Uninitialize,
+    USART2_PowerControl,
+    USART2_Send, 
+    USART2_Receive,
+    USART2_Transfer,
+    USART2_GetTxCount,
+    USART2_GetRxCount,
+    USART2_Control,
+    USART2_GetStatus,
+    USART2_SetModemControl,
+    USART2_GetModemStatus
+};
+#endif
+
+#if (RTE_USART3)
+// USART3 Driver Wrapper functions
+static ARM_USART_CAPABILITIES USART3_GetCapabilities (void) {
+  return USART_GetCapabilities (&USART3_Resources);
+}
+static int32_t USART3_Initialize (ARM_USART_SignalEvent_t cb_event) {
+  return USART_Initialize (cb_event, &USART3_Resources);
+}
+static int32_t USART3_Uninitialize (void) {
+  return USART_Uninitialize(&USART3_Resources);
+}
+static int32_t USART3_PowerControl (ARM_POWER_STATE state) {
+  return USART_PowerControl (state, &USART3_Resources);
+}
+static int32_t USART3_Send (const void *data, uint32_t num) {
+  return USART_Send (data, num, &USART3_Resources);
+}
+static int32_t USART3_Receive (void *data, uint32_t num) {
+  return USART_Receive (data, num, &USART3_Resources);
+}
+static int32_t USART3_Transfer (const void      *data_out,
+                                      void      *data_in,
+                                      uint32_t   num) {
+  return USART_Transfer (data_out, data_in, num, &USART3_Resources);
+}
+static uint32_t USART3_GetTxCount (void) {
+  return USART_GetTxCount (&USART3_Resources);
+}
+static uint32_t USART3_GetRxCount (void) {
+  return USART_GetRxCount (&USART3_Resources); 
+}
+static int32_t USART3_Control (uint32_t control, uint32_t arg) {
+  return USART_Control (control, arg, &USART3_Resources);
+}
+static ARM_USART_STATUS USART3_GetStatus (void) {
+  return USART_GetStatus (&USART3_Resources);
+}
+static int32_t USART3_SetModemControl (ARM_USART_MODEM_CONTROL control) {
+  return USART_SetModemControl (control, &USART3_Resources);
+}
+static ARM_USART_MODEM_STATUS USART3_GetModemStatus (void) {
+  return USART_GetModemStatus (&USART3_Resources);
+}
+void UART3_IRQHandler (void) {
+  USART_IRQHandler (&USART3_Resources);
+}
+#if (RTE_USART3_DMA_TX_EN == 1)
+void USART3_GPDMA_Tx_Event (uint32_t event) {
+  USART_GPDMA_Tx_Event(event, &USART3_Resources);
+}
+#endif
+#if (RTE_USART3_DMA_RX_EN == 1)
+void USART3_GPDMA_Rx_Event (uint32_t event) {
+  USART_GPDMA_Rx_Event(event, &USART3_Resources);
+}
+#endif
+
+// USART3 Driver Control Block
+ARM_DRIVER_USART Driver_USART3 = {
+    USARTx_GetVersion,
+    USART3_GetCapabilities,
+    USART3_Initialize,
+    USART3_Uninitialize,
+    USART3_PowerControl,
+    USART3_Send, 
+    USART3_Receive,
+    USART3_Transfer,
+    USART3_GetTxCount,
+    USART3_GetRxCount,
+    USART3_Control,
+    USART3_GetStatus,
+    USART3_SetModemControl,
+    USART3_GetModemStatus
+};
+#endif

CMSIS/Pack/Example/CMSIS_Driver/USART_LPC18xx.h

@@ -0,0 +1,295 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        02. March 2016
+ * $Revision:    V2.5
+ *
+ * Project:      USART Driver Definitions for NXP LPC18xx
+ * -------------------------------------------------------------------------- */
+
+#ifndef __USART_LPC18XX_H
+#define __USART_LPC18XX_H
+
+#include "LPC18xx.h"
+#include "Driver_USART.h"
+
+#include "SCU_LPC18xx.h"
+#include "GPDMA_LPC18xx.h"
+
+// Clock Control Unit register
+#define CCU_CLK_CFG_RUN     (1 << 0)
+#define CCU_CLK_CFG_AUTO    (1 << 1)
+#define CCU_CLK_STAT_RUN    (1 << 0)
+
+// USART register interface definitions
+// USART Divisor Latch register LSB
+#define USART_DLL_DLLSB_POS          (     0U)
+#define USART_DLL_DLLSB_MSK          (0xFFU << USART_DLL_DLLSB_POS)
+
+// USART Divisor Latch register MSB
+#define USART_DLM_DLMSB_POS          (     0U)
+#define USART_DLM_DLMSB_MSK          (0xFFU << USART_DLM_DLMSB_POS)
+
+// USART Interrupt enable register
+#define USART_IER_RBRIE              (1U << 0)
+#define USART_IER_THREIE             (1U << 1)
+#define USART_IER_RXIE               (1U << 2)
+#define UART_IER_MSIE                (1U << 3) // Only for UART1 - modem status interrupt enable
+#define USART_IER_ABEOINTEN          (1U << 8)
+#define USART_IER_ABTOINTEN          (1U << 9)
+
+// USART Interrupt identification register
+#define USART_IIR_INTSTATUS          (1U << 0)
+#define USART_IIR_INTID_POS          (     1U)
+#define USART_IIR_INTID_MSK          (7U << USART_IIR_INTID_POS)
+#define USART_IIR_FIFOENABLE_POS     (     6U)
+#define USART_IIR_FIFOENABLE_MSK     (3U << USART_IIR_FIFOENABLE_POS)
+#define USART_IIR_ABEOINT            (1U << 8)
+#define USART_IIR_ABTOINT            (1U << 9)
+
+#define USART_IIR_INTID_RLS          (3U << USART_IIR_INTID_POS)
+#define USART_IIR_INTID_RDA          (2U << USART_IIR_INTID_POS)
+#define USART_IIR_INTID_CTI          (6U << USART_IIR_INTID_POS)
+#define USART_IIR_INTID_THRE         (1U << USART_IIR_INTID_POS)
+#define UART_IIR_INTID_MS            (0U << USART_IIR_INTID_POS) // UART1 only
+
+// USART FIFO control register
+#define USART_FCR_FIFOEN             (1U << 0)
+#define USART_FCR_RXFIFORES          (1U << 1)
+#define USART_FCR_TXFIFORES          (1U << 2)
+#define USART_FCR_DMAMODE            (1U << 3)
+#define USART_FCR_RXTRIGLVL_POS      (     6U)
+#define USART_FCR_RXTRIGLVL_MSK      (3U << USART_FCR_RXTRIGLVL_POS)
+
+// USART Line control register
+#define USART_LCR_WLS_POS            (     0U)
+#define USART_LCR_WLS_MSK            (3U << USART_LCR_WLS_POS)
+#define USART_LCR_SBS                (1U << 2)
+#define USART_LCR_PE                 (1U << 3)
+#define USART_LCR_PS_POS             (     4U)
+#define USART_LCR_PS_MSK             (3U << USART_LCR_PS_POS)
+#define USART_LCR_BC                 (1U << 6)
+#define USART_LCR_DLAB               (1U << 7)
+
+// USART Line status register
+#define USART_LSR_RDR                (1U << 0)
+#define USART_LSR_OE                 (1U << 1)
+#define USART_LSR_PE                 (1U << 2)
+#define USART_LSR_FE                 (1U << 3)
+#define USART_LSR_BI                 (1U << 4)
+#define USART_LSR_THRE               (1U << 5)
+#define USART_LSR_TEMT               (1U << 6)
+#define USART_LSR_RXFE               (1U << 7)
+#define USART_LSR_TXERR              (1U << 8)
+
+#define USART_LSR_LINE_INT           (USART_LSR_OE | USART_LSR_PE | USART_LSR_FE | USART_LSR_BI)
+
+// USART IrDA control register
+#define USART_ICR_IRDAEN             (1U << 0)
+#define USART_ICR_FIXPULSEEN         (1U << 1)
+#define USART_ICR_IRDAINV            (1U << 2)
+#define USART_ICR_PULSEDIV_POS       (     3U)
+#define USART_ICR_PULSEDIV_MSK       (7U << USART_ICR_PULSEDIV_POS)
+
+
+// USART Fractional divider register
+#define USART_FDR_DIVADDVAL_POS      (      0U)
+#define USART_FDR_DIVADDVAL_MSK      (0x0FU << USART_FDR_DIVADDVAL_POS)
+#define USART_FDR_MULVAL_POS         (      4U)
+#define USART_FDR_MULVAL_MSK         (0x0FU << USART_FDR_MULVAL_POS)
+
+// USART oversampling register
+#define USART_OSR_OSFRAC_POS         (      1U)
+#define USART_OSR_OSFRAC_MSK         (7U    << USART_OSR_OSFRAC_POS)
+#define USART_OSR_OSINT_POS          (      4U)
+#define USART_OSR_OSINT_MSK          (0x0FU << USART_OSR_OSINT_POS)
+#define USART_OSR_FDINT_POS          (      8U)
+#define USART_OSR_FDINT_MSK          (0x7FU << USART_OSR_FDINT_MSK)
+
+// USART Half duplex enable register
+#define USART_HDEN_HDEN              (1U << 0U)
+
+// USART SmartCard interface control register
+#define USART_SCICTRL_SCIEN          (1U << 0)
+#define USART_SCICTRL_NACKDIS        (1U << 1)
+#define USART_SCICTRL_PROTSEL        (1U << 2)
+#define USART_SCICTRL_TXRETRY_POS    (     5U)
+#define USART_SCICTRL_TXRETRY_MSK    (7U << USART_SCICTRL_TXRETRY_POS)
+#define USART_SCICTRL_GUARDTIME_POS  (     8U)
+#define USART_SCICTRL_GUARDTIME_MSK  (0xFFU << USART_SCICTRL_GUARDTIME_POS)
+
+// USART Synchronous mode control register
+#define USART_SYNCCTRL_SYNC          (1U << 0)
+#define USART_SYNCCTRL_CSRC          (1U << 1)
+#define USART_SYNCCTRL_FES           (1U << 2)
+#define USART_SYNCCTRL_TSBYPASS      (1U << 3)
+#define USART_SYNCCTRL_CSCEN         (1U << 4)
+#define USART_SYNCCTRL_SSSDIS        (1U << 5)
+#define USART_SYNCCTRL_CCCLR         (1U << 6)
+
+// UART Modem control register
+#define UART_MCR_DTRCTRL             (1U << 0)
+#define UART_MCR_RTSCTRL             (1U << 1)
+#define UART_MCR_LMS                 (1U << 4)
+#define UART_MCR_RTSEN               (1U << 6)
+#define UART_MCR_CTSEN               (1U << 7)
+
+// UART Modem status register
+#define UART_MSR_DCTS                (1U << 0)
+#define UART_MSR_DDSR                (1U << 1)
+#define UART_MSR_TERI                (1U << 2)
+#define UART_MSR_DDCD                (1U << 3)
+#define UART_MSR_CTS                 (1U << 4)
+#define UART_MSR_DSR                 (1U << 5)
+#define UART_MSR_RI                  (1U << 6)
+#define UART_MSR_DCD                 (1U << 7)
+
+// USART RS485 control register
+#define USART_RS485CTRL_NMMEN        (1U << 0)
+#define USART_RS485CTRL_RXDIS        (1U << 1)
+#define USART_RS485CTRL_AADEN        (1U << 2)
+#define USART_RS485CTRL_DCTRL        (1U << 4)
+#define USART_RS485CTRL_OINV         (1U << 5)
+
+// USART Transmitter enable register
+#define USART_TER_TXEN               (1U << 0)
+
+
+// USART flags
+#define USART_FLAG_INITIALIZED       (1U << 0)
+#define USART_FLAG_POWERED           (1U << 1)
+#define USART_FLAG_CONFIGURED        (1U << 2)
+#define USART_FLAG_TX_ENABLED        (1U << 3)
+#define USART_FLAG_RX_ENABLED        (1U << 4)
+#define USART_FLAG_SEND_ACTIVE       (1U << 5)
+
+// USART synchronous xfer modes
+#define USART_SYNC_MODE_TX           ( 1U )
+#define USART_SYNC_MODE_RX           ( 2U )
+#define USART_SYNC_MODE_TX_RX        (USART_SYNC_MODE_TX | \
+                                      USART_SYNC_MODE_RX)
+
+
+#define FRACT_BITS                   ( 12U  )
+#define FRACT_MASK                   (0XFFFU)
+
+#define FIXED_OVERSAMPLING_DIVIDER_LIMIT   (51U  << FRACT_BITS)
+#define INTEGER_OVERSAMPLING_DIVIDER_LIMIT ((12U << FRACT_BITS) + (8 << FRACT_BITS) / 10)
+
+// Baudrate accepted error
+#define USART_MAX_BAUDRATE_ERROR     ( 3U )
+#define USART_MAX_DIVIDER_ERROR      ( 3U )
+
+// USART TX FIFO trigger level
+#define USART_TRIG_LVL_1             (0x00U)
+#define USART_TRIG_LVL_4             (0x40U)
+#define USART_TRIG_LVL_8             (0x80U)
+#define USART_TRIG_LVL_14            (0xC0U)
+
+#define FRACT_DIV(add, mul)      { ((uint16_t)((1U << 12) + (((uint32_t)(add << 24) / (mul)) >> 12))), ((uint8_t) (((mul) << 4) | add)), }
+
+typedef struct _FRACT_DIV {
+  uint16_t val;
+  uint8_t  add_mul;
+} FRACT_DIVIDER;
+
+// USART Transfer Information (Run-Time)
+typedef struct _USART_TRANSFER_INFO {
+  uint32_t                rx_num;        // Total number of data to be received
+  uint32_t                tx_num;        // Total number of data to be send
+  uint8_t                *rx_buf;        // Pointer to in data buffer
+  uint8_t                *tx_buf;        // Pointer to out data buffer
+  uint32_t                rx_cnt;        // Number of data received
+  uint32_t                tx_cnt;        // Number of data sent
+  uint8_t                 tx_def_val;    // Transmit default value (used in USART_SYNC_MASTER_MODE_RX)
+  uint8_t                 rx_dump_val;   // Receive dump value (used in USART_SYNC_MASTER_MODE_TX)
+  uint8_t                 send_active;   // Send active flag
+  uint8_t                 sync_mode;     // Synchronous mode
+} USART_TRANSFER_INFO;
+
+typedef struct _USART_RX_STATUS {
+  uint8_t rx_busy;                       // Receiver busy flag
+  uint8_t rx_overflow;                   // Receive data overflow detected (cleared on start of next receive operation)
+  uint8_t rx_break;                      // Break detected on receive (cleared on start of next receive operation)
+  uint8_t rx_framing_error;              // Framing error detected on receive (cleared on start of next receive operation)
+  uint8_t rx_parity_error;               // Parity error detected on receive (cleared on start of next receive operation)
+} USART_RX_STATUS;
+
+// USART Information (Run-Time)
+typedef struct _USART_INFO {
+  ARM_USART_SignalEvent_t cb_event;      // Event callback
+  USART_RX_STATUS         rx_status;     // Receive status flags
+  USART_TRANSFER_INFO     xfer;          // Transfer information
+  uint8_t                 mode;          // USART mode
+  uint8_t                 flags;         // USART driver flags
+  uint32_t                baudrate;      // Baudrate
+} USART_INFO;
+
+// USART DMA
+typedef const struct _USART_DMA {
+  uint8_t                 channel;       // DMA Channel
+  uint8_t                 peripheral;    // DMA mux
+  uint8_t                 peripheral_sel;// DMA mux selection
+  GPDMA_SignalEvent_t     cb_event;      // DMA Event callback
+} USART_DMA;
+
+// USART Pin Configuration
+typedef const struct _USART_PINS {
+  PIN_ID                 *tx;            // TX  Pin identifier
+  PIN_ID                 *rx;            // RX  Pin identifier
+  PIN_ID                 *clk;           // CLK  Pin identifier
+  PIN_ID                 *cts;           // CTS Pin identifier
+  PIN_ID                 *rts;           // RTS Pin identifier
+  PIN_ID                 *dcd;           // DCD Pin identifier
+  PIN_ID                 *dsr;           // DSR Pin identifier
+  PIN_ID                 *dtr;           // DTR Pin identifier
+  PIN_ID                 *ri;            // RI  Pin identifier
+} USART_PINS;
+
+// USART Clocks Configuration
+typedef const struct _USART_CLOCK {
+  __IO uint32_t          *reg_cfg;       // USART register interface clock configuration register
+  __I  uint32_t          *reg_stat;      // USART register interface clock status register
+  __IO uint32_t          *peri_cfg;      // USART peripheral clock configuration register
+  __I  uint32_t          *peri_stat;     // USART peripheral clock status register
+  __IO uint32_t          *base_clk;      // USART base clock
+} USART_CLOCKS;
+
+// USART Reset Configuration
+typedef const struct _USART_RESET {
+       uint32_t           reg_cfg_val;   // USART reset bit 
+  __IO uint32_t          *reg_cfg;       // USART reset control register
+  __I  uint32_t          *reg_stat;      // USART reset active status register
+} USART_RESET;
+
+// USART Resources definitions
+typedef struct {
+  ARM_USART_CAPABILITIES  capabilities;  // Capabilities
+  LPC_USARTn_Type        *reg;           // Pointer to USART peripheral
+  LPC_UART1_Type         *uart_reg;      // Pointer to UART peripheral
+  USART_PINS              pins;          // USART pins configuration
+  USART_CLOCKS            clk;           // USART clocks configuration
+  USART_RESET             rst;           // USART reset configuration
+  IRQn_Type               irq_num;       // USART IRQ Number
+  uint32_t                trig_lvl;      // FIFO Trigger level
+  USART_DMA              *dma_tx;
+  USART_DMA              *dma_rx;
+  USART_INFO             *info;          // Run-Time Information
+  float                   sc_oversamp;   // SmartCard oversampling ratio
+} const USART_RESOURCES;
+
+#endif /* __USART_LPC18XX_H */

CMSIS/Pack/Example/CMSIS_Driver/USB0_LPC18xx.c

@@ -0,0 +1,133 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        02. March 2016
+ * $Revision:    V1.1
+ *
+ * Project:      USB common (Device and Host) module for NXP LPC18xx
+ * -------------------------------------------------------------------------- */
+
+/* History:
+ *  Version 1.1
+ *    Improved support for Host and Device
+ *  Version 1.0
+ *    Initial release
+ */
+
+#include "LPC18xx.h"
+#include "SCU_LPC18xx.h"
+
+#include "Driver_USB.h"
+
+#include "RTE_Device.h"
+#include "RTE_Components.h"
+
+volatile uint8_t USB0_role  = ARM_USB_ROLE_NONE;
+volatile uint8_t USB0_state = 0U;
+
+#ifdef RTE_Drivers_USBH0
+extern void USBH0_IRQ (void);
+#endif
+#ifdef RTE_Drivers_USBD0
+extern void USBD0_IRQ (void);
+#endif
+
+
+// Common IRQ Routine **********************************************************
+
+/**
+  \fn          void USB0_IRQHandler (void)
+  \brief       USB Interrupt Routine (IRQ).
+*/
+void USB0_IRQHandler (void) {
+#if (defined(RTE_Drivers_USBH0) && defined(RTE_Drivers_USBD0))
+  switch (USB0_role) {
+#ifdef RTE_Drivers_USBH0
+    case ARM_USB_ROLE_HOST:
+      USBH0_IRQ ();
+      break;
+#endif
+#ifdef RTE_Drivers_USBD0
+    case ARM_USB_ROLE_DEVICE:
+      USBD0_IRQ ();
+      break;
+#endif
+    default:
+      break;
+  }
+#else
+#ifdef RTE_Drivers_USBH0
+  USBH0_IRQ ();
+#else
+  USBD0_IRQ ();
+#endif
+#endif
+
+}
+
+
+// Public Functions ************************************************************
+
+/**
+  \fn          void USB0_PinsConfigure (void)
+  \brief       Configure USB pins
+*/
+void USB0_PinsConfigure (void) {
+
+  // Common (Device and Host) Pins
+#if (RTE_USB0_IND0_PIN_EN)
+  SCU_PinConfigure(RTE_USB0_IND0_PORT, RTE_USB0_IND0_BIT, RTE_USB0_IND0_FUNC);
+#endif
+#if (RTE_USB0_IND1_PIN_EN)
+  SCU_PinConfigure(RTE_USB0_IND1_PORT, RTE_USB0_IND1_BIT, RTE_USB0_IND1_FUNC);
+#endif
+
+  // Host Pins
+  if (USB0_role == ARM_USB_ROLE_HOST) {
+#if (RTE_USB0_PPWR_PIN_EN)
+    SCU_PinConfigure(RTE_USB0_PPWR_PORT,      RTE_USB0_PPWR_BIT,      RTE_USB0_PPWR_FUNC);
+#endif
+#if (RTE_USB0_PWR_FAULT_PIN_EN)
+    SCU_PinConfigure(RTE_USB0_PWR_FAULT_PORT, RTE_USB0_PWR_FAULT_BIT, RTE_USB0_PWR_FAULT_FUNC);
+#endif
+  }
+}
+
+/**
+  \fn          void USB0_PinsUnconfigure (void)
+  \brief       De-configure USB pins
+*/
+void USB0_PinsUnconfigure (void) {
+
+  // Common (Device and Host) Pins
+#if (RTE_USB0_IND0_PIN_EN)
+  SCU_PinConfigure(RTE_USB0_IND0_PORT, RTE_USB0_IND0_BIT, 0);
+#endif
+#if (RTE_USB0_IND1_PIN_EN)
+  SCU_PinConfigure(RTE_USB0_IND1_PORT, RTE_USB0_IND1_BIT, 0);
+#endif
+
+  // Host Pins
+  if (USB0_role == ARM_USB_ROLE_HOST) {
+#if (RTE_USB0_PPWR_PIN_EN)
+    SCU_PinConfigure(RTE_USB0_PPWR_PORT,      RTE_USB0_PPWR_BIT,      0);
+#endif
+#if (RTE_USB0_PWR_FAULT_PIN_EN)
+    SCU_PinConfigure(RTE_USB0_PWR_FAULT_PORT, RTE_USB0_PWR_FAULT_BIT, 0);
+#endif
+  }
+}

CMSIS/Pack/Example/CMSIS_Driver/USB1_LPC18xx.c

@@ -0,0 +1,183 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        02. March 2016
+ * $Revision:    V1.1
+ *
+ * Project:      USB common (Device and Host) module for NXP LPC18xx
+ * -------------------------------------------------------------------------- */
+
+/* History:
+ *  Version 1.1
+ *    Improved support for Host and Device
+ *  Version 1.0
+ *    Initial release
+ */
+
+#include "LPC18xx.h"
+#include "SCU_LPC18xx.h"
+
+#include "Driver_USB.h"
+
+#include "RTE_Device.h"
+#include "RTE_Components.h"
+
+volatile uint8_t USB1_role  = ARM_USB_ROLE_NONE;
+volatile uint8_t USB1_state = 0U;
+
+#ifdef RTE_Drivers_USBH1
+extern void USBH1_IRQ (void);
+#endif
+#ifdef RTE_Drivers_USBD1
+extern void USBD1_IRQ (void);
+#endif
+
+
+// Common IRQ Routine **********************************************************
+
+/**
+  \fn          void USB1_IRQHandler (void)
+  \brief       USB Interrupt Routine (IRQ).
+*/
+void USB1_IRQHandler (void) {
+#if (defined(RTE_Drivers_USBH1) && defined(RTE_Drivers_USBD1))
+  switch (USB1_role) {
+#ifdef RTE_Drivers_USBH1
+    case ARM_USB_ROLE_HOST:
+      USBH1_IRQ ();
+      break;
+#endif
+#ifdef RTE_Drivers_USBD1
+    case ARM_USB_ROLE_DEVICE:
+      USBD1_IRQ ();
+      break;
+#endif
+    default:
+      break;
+  }
+#else
+#ifdef RTE_Drivers_USBH1
+  USBH1_IRQ ();
+#else
+  USBD1_IRQ ();
+#endif
+#endif
+
+}
+
+
+// Public Functions ************************************************************
+
+/**
+  \fn          void USB1_PinsConfigure (void)
+  \brief       Configure USB pins
+*/
+void USB1_PinsConfigure (void) {
+
+  // Common (Device and Host) Pins
+#if (RTE_USB1_IND0_PIN_EN)
+  SCU_PinConfigure(RTE_USB1_IND0_PORT, RTE_USB1_IND0_BIT, RTE_USB1_IND0_FUNC);
+#endif
+#if (RTE_USB1_IND1_PIN_EN)
+  SCU_PinConfigure(RTE_USB1_IND1_PORT, RTE_USB1_IND1_BIT, RTE_USB1_IND1_FUNC);
+#endif
+
+#if (RTE_USB_USB1_FS_PHY_EN)
+#if (RTE_USB1_VBUS_PIN_EN)
+  // Device Pin
+  if (USB1_role == ARM_USB_ROLE_DEVICE) {
+    SCU_PinConfigure(RTE_USB1_VBUS_PORT, RTE_USB1_VBUS_BIT, RTE_USB1_VBUS_FUNC | SCU_SFS_EPD | SCU_SFS_EZI);
+  }
+#endif
+#endif
+
+  // Host Pins
+  if (USB1_role == ARM_USB_ROLE_HOST) {
+#if (RTE_USB1_PPWR_PIN_EN)
+    SCU_PinConfigure(RTE_USB1_PPWR_PORT,      RTE_USB1_PPWR_BIT,      RTE_USB1_PPWR_FUNC);
+#endif
+#if (RTE_USB1_PWR_FAULT_PIN_EN)
+    SCU_PinConfigure(RTE_USB1_PWR_FAULT_PORT, RTE_USB1_PWR_FAULT_BIT, RTE_USB1_PWR_FAULT_FUNC);
+#endif
+  }
+
+  // ULPI Pins
+#if (RTE_USB_USB1_HS_PHY_EN)
+  SCU_PinConfigure(RTE_USB1_ULPI_CLK_PORT, RTE_USB1_ULPI_CLK_BIT,  RTE_USB1_ULPI_CLK_FUNC);
+  SCU_PinConfigure(RTE_USB1_ULPI_DIR_PORT, RTE_USB1_ULPI_DIR_BIT,  RTE_USB1_ULPI_DIR_FUNC);
+  SCU_PinConfigure(RTE_USB1_ULPI_STP_PORT, RTE_USB1_ULPI_STP_BIT,  RTE_USB1_ULPI_STP_FUNC);
+  SCU_PinConfigure(RTE_USB1_ULPI_NXT_PORT, RTE_USB1_ULPI_NXT_BIT,  RTE_USB1_ULPI_NXT_FUNC);
+  SCU_PinConfigure(RTE_USB1_ULPI_D0_PORT,  RTE_USB1_ULPI_D0_BIT,   RTE_USB1_ULPI_D0_FUNC );
+  SCU_PinConfigure(RTE_USB1_ULPI_D1_PORT,  RTE_USB1_ULPI_D1_BIT,   RTE_USB1_ULPI_D1_FUNC );
+  SCU_PinConfigure(RTE_USB1_ULPI_D2_PORT,  RTE_USB1_ULPI_D2_BIT,   RTE_USB1_ULPI_D2_FUNC );
+  SCU_PinConfigure(RTE_USB1_ULPI_D3_PORT,  RTE_USB1_ULPI_D3_BIT,   RTE_USB1_ULPI_D3_FUNC );
+  SCU_PinConfigure(RTE_USB1_ULPI_D4_PORT,  RTE_USB1_ULPI_D4_BIT,   RTE_USB1_ULPI_D4_FUNC );
+  SCU_PinConfigure(RTE_USB1_ULPI_D5_PORT,  RTE_USB1_ULPI_D5_BIT,   RTE_USB1_ULPI_D5_FUNC );
+  SCU_PinConfigure(RTE_USB1_ULPI_D6_PORT,  RTE_USB1_ULPI_D6_BIT,   RTE_USB1_ULPI_D6_FUNC );
+  SCU_PinConfigure(RTE_USB1_ULPI_D7_PORT,  RTE_USB1_ULPI_D7_BIT,   RTE_USB1_ULPI_D7_FUNC );
+#endif
+}
+
+/**
+  \fn          void USB1_PinsUnconfigure (void)
+  \brief       De-configure USB pins
+*/
+void USB1_PinsUnconfigure (void) {
+
+  // Common (Device and Host) Pins
+#if (RTE_USB1_IND0_PIN_EN)
+  SCU_PinConfigure(RTE_USB1_IND0_PORT, RTE_USB1_IND0_BIT, 0);
+#endif
+#if (RTE_USB1_IND1_PIN_EN)
+  SCU_PinConfigure(RTE_USB1_IND1_PORT, RTE_USB1_IND1_BIT, 0);
+#endif
+
+#if (RTE_USB_USB1_FS_PHY_EN)
+#if (RTE_USB1_VBUS_PIN_EN)
+  // Device Pin
+  if (USB1_role == ARM_USB_ROLE_DEVICE) {
+    SCU_PinConfigure(RTE_USB1_VBUS_PORT, RTE_USB1_VBUS_BIT, 0);
+  }
+#endif
+#endif
+
+  // Host Pins
+  if (USB1_role == ARM_USB_ROLE_HOST) {
+#if (RTE_USB1_PPWR_PIN_EN)
+    SCU_PinConfigure(RTE_USB1_PPWR_PORT,      RTE_USB1_PPWR_BIT,      0);
+#endif
+#if (RTE_USB1_PWR_FAULT_PIN_EN)
+    SCU_PinConfigure(RTE_USB1_PWR_FAULT_PORT, RTE_USB1_PWR_FAULT_BIT, 0);
+#endif
+  }
+
+  // ULPI Pins
+#if (RTE_USB_USB1_HS_PHY_EN)
+  SCU_PinConfigure(RTE_USB1_ULPI_CLK_PORT, RTE_USB1_ULPI_CLK_BIT,  0);
+  SCU_PinConfigure(RTE_USB1_ULPI_DIR_PORT, RTE_USB1_ULPI_DIR_BIT,  0);
+  SCU_PinConfigure(RTE_USB1_ULPI_STP_PORT, RTE_USB1_ULPI_STP_BIT,  0);
+  SCU_PinConfigure(RTE_USB1_ULPI_NXT_PORT, RTE_USB1_ULPI_NXT_BIT,  0);
+  SCU_PinConfigure(RTE_USB1_ULPI_D0_PORT,  RTE_USB1_ULPI_D0_BIT,   0 );
+  SCU_PinConfigure(RTE_USB1_ULPI_D1_PORT,  RTE_USB1_ULPI_D1_BIT,   0 );
+  SCU_PinConfigure(RTE_USB1_ULPI_D2_PORT,  RTE_USB1_ULPI_D2_BIT,   0 );
+  SCU_PinConfigure(RTE_USB1_ULPI_D3_PORT,  RTE_USB1_ULPI_D3_BIT,   0 );
+  SCU_PinConfigure(RTE_USB1_ULPI_D4_PORT,  RTE_USB1_ULPI_D4_BIT,   0 );
+  SCU_PinConfigure(RTE_USB1_ULPI_D5_PORT,  RTE_USB1_ULPI_D5_BIT,   0 );
+  SCU_PinConfigure(RTE_USB1_ULPI_D6_PORT,  RTE_USB1_ULPI_D6_BIT,   0 );
+  SCU_PinConfigure(RTE_USB1_ULPI_D7_PORT,  RTE_USB1_ULPI_D7_BIT,   0 );
+#endif
+}

CMSIS/Pack/Example/CMSIS_Driver/USBD0_LPC18xx.c

@@ -0,0 +1,895 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        02. March 2016
+ * $Revision:    V2.9
+ *
+ * Driver:       Driver_USBD0
+ * Configured:   via RTE_Device.h configuration file
+ * Project:      USB Device Driver for NXP LPC18xx
+ * --------------------------------------------------------------------------
+ * Use the following configuration settings in the middleware component
+ * to connect to this driver.
+ *
+ *   Configuration Setting                  Value
+ *   ---------------------                  -----
+ *   Connect to hardware via Driver_USBD# = 0
+ * --------------------------------------------------------------------------
+ * Defines used for driver configuration (at compile time):
+ *
+ *   USBD_MAX_ENDPOINT_NUM:  defines maximum number of IN/OUT Endpoint pairs 
+ *                           that driver will support with Control Endpoint 0
+ *                           not included, this value impacts driver memory
+ *                           requirements
+ *     - default value: 5
+ *     - maximum value: 5
+ * -------------------------------------------------------------------------- */
+
+/* History:
+ *  Version 2.9
+ *    Removed unnecessary __packed specifier for structures dQH_t and dTD_t
+ *  Version 2.8
+ *    Corrected PowerControl function for conditional Power full (driver must be initialized)
+ *  Version 2.7
+ *    PowerControl for Power OFF and Uninitialize functions made unconditional
+ *  Version 2.6
+ *    Corrected isochronous endpoint configuration
+ *    Corrected transfer procedure
+ *  Version 2.5
+ *    Corrected isochronous transfer functionality
+ *  Version 2.4
+ *    Corrected CLK_M3_USB1_CFG into CLK_M3_USB0_CFG in USBD_PowerControl
+ *    function
+ *  Version 2.3
+ *    Corrected PORTSC1_D_PFSC into USB_PORTSC1_D_PFSC
+ *  Version 2.2
+ *    Corrected return value in USBD_PowerControl function.
+ *  Version 2.1
+ *    Added USB_LPC18xx_USB0.h with register bit definitions
+ *    Pin configuration moved to USB_LPC18xx.c
+ *  Version 2.0
+ *    Updated to 2.00 API
+ *  Version 1.3
+ *    Re-implementation of the driver
+ *  Version 1.2
+ *    Updated USB1 pin configurations
+ *  Version 1.1
+ *    Based on API V1.10 (namespace prefix ARM_ added)
+ *  Version 1.0
+ *    Initial release
+ */
+
+
+#include <stdint.h>
+#include <string.h>
+
+#include "Driver_USBD.h"
+
+#include "LPC18xx.h"
+#include "USB_LPC18xx.h"
+
+#include "RTE_Device.h"
+#include "RTE_Components.h"
+
+#if      (RTE_USB_USB0 == 0)
+#error   "USB0 is not enabled in the RTE_Device.h!"
+#endif
+
+#ifndef USBD_MAX_ENDPOINT_NUM
+#define USBD_MAX_ENDPOINT_NUM           5U
+#endif
+#if    (USBD_MAX_ENDPOINT_NUM > 5)
+#error  Too many Endpoints, maximum IN/OUT Endpoint pairs that this driver supports is 5 !!!
+#endif
+
+extern uint8_t USB0_role;
+extern uint8_t USB0_state;
+
+extern void USB0_PinsConfigure   (void);
+extern void USB0_PinsUnconfigure (void);
+
+
+// USBD Driver *****************************************************************
+
+#define ARM_USBD_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,9)
+
+// Driver Version
+static const ARM_DRIVER_VERSION usbd_driver_version = { ARM_USBD_API_VERSION, ARM_USBD_DRV_VERSION };
+
+// Driver Capabilities
+static const ARM_USBD_CAPABILITIES usbd_driver_capabilities = {
+  0U,   // VBUS Detection
+  0U,   // Event VBUS On
+  0U    // Event VBUS Off
+};
+
+#define LPC_USBx                        LPC_USB0
+#define ENDPTCTRL(ep_num)               (*(volatile uint32_t *)((uint32_t)(&LPC_USBx->ENDPTCTRL0) + 4U * ep_num))
+
+#define EP_NUM(ep_addr)                 (ep_addr & ARM_USB_ENDPOINT_NUMBER_MASK)
+#define EP_DIR(ep_addr)                 ((ep_addr >>  7) & 1U)
+#define EP_SLL(ep_addr)                 (EP_DIR(ep_addr) * 16U)
+#define EP_IDX(ep_addr)                 ((EP_NUM(ep_addr) * 2U) + ((ep_addr >> 7) & 1U))
+#define EP_MSK(ep_addr)                 (1UL << (EP_NUM(ep_addr) + EP_SLL(ep_addr)))
+
+typedef struct {                        // USB Device Endpoint Queue Head
+  uint32_t  cap;
+  uint32_t  curr_dTD;
+  uint32_t  next_dTD;
+  uint32_t  dTD_token;
+  uint32_t  buf[5];
+  uint32_t  reserved;
+  uint32_t  setup[2];
+                                        // Use reminder of 64 bytes for transfer information
+  uint8_t  *data;
+  uint32_t  num;
+  uint32_t  num_transferred_total;
+  uint16_t  num_transferring;
+  uint8_t   ep_type;
+  uint8_t   ep_active;
+} dQH_t;
+
+typedef struct {                        // USB Device Endpoint Transfer Descriptor
+  uint32_t  next_dTD;
+  uint32_t  dTD_token;
+  uint32_t  buf[5];
+  uint32_t  reserved;
+} dTD_t;
+
+static ARM_USBD_SignalDeviceEvent_t   SignalDeviceEvent;
+static ARM_USBD_SignalEndpointEvent_t SignalEndpointEvent;
+
+static ARM_USBD_STATE      usbd_state;
+
+static uint32_t            setup_packet[2];     // Setup packet data
+static volatile uint8_t    setup_received;      // Setup packet received
+
+static dQH_t __align(2048) dQH[(USBD_MAX_ENDPOINT_NUM + 1U) * 2U];      // Queue Heads
+static dTD_t __align(  32) dTD[(USBD_MAX_ENDPOINT_NUM + 1U) * 2U];      // Transfer Descriptors
+
+// Function prototypes
+static int32_t USBD_EndpointConfigure (uint8_t ep_addr, uint8_t ep_type, uint16_t ep_max_packet_size);
+
+
+// Auxiliary functions
+
+/**
+  \fn          void USBD_HW_EndpointFlush (uint8_t ep_addr)
+  \brief       Flush Endpoint.
+*/
+static void USBD_HW_EndpointFlush (uint8_t ep_addr) {
+  uint32_t ep_msk;
+
+  ep_msk = EP_MSK(ep_addr);
+
+  LPC_USBx->ENDPTFLUSH = ep_msk;
+  while (LPC_USBx->ENDPTFLUSH & ep_msk);
+}
+
+/**
+  \fn          void USBD_Reset (void)
+  \brief       Reset USB Endpoint settings and variables.
+*/
+static void USBD_Reset (void) {
+  uint8_t i;
+
+  // Reset global variables
+  setup_packet[0] = 0U;
+  setup_packet[1] = 0U;
+  setup_received  = 0U;
+  memset((void *)&usbd_state, 0, sizeof(usbd_state));
+  memset((void *)dQH,         0, sizeof(dQH));
+  memset((void *)dTD,         0, sizeof(dTD));
+  for (i = 1U; i <= USBD_MAX_ENDPOINT_NUM; i++) {
+    ENDPTCTRL(i) &= ~(USB_ENDPTCTRL_RXE | USB_ENDPTCTRL_TXE);
+  }
+
+  // Clear interrupts
+  LPC_USBx->ENDPTNAK       = 0xFFFFFFFFUL;
+  LPC_USBx->ENDPTNAKEN     = 0U;
+  LPC_USBx->USBSTS_D       = 0xFFFFFFFFUL;
+  LPC_USBx->ENDPTSETUPSTAT = LPC_USBx->ENDPTSETUPSTAT;
+  LPC_USBx->ENDPTCOMPLETE  = LPC_USBx->ENDPTCOMPLETE;
+
+  while (LPC_USBx->ENDPTPRIME);
+
+  // Clear all Primed buffers
+  LPC_USBx->ENDPTFLUSH = 0xFFFFFFFFUL;
+  while (LPC_USBx->ENDPTFLUSH);
+
+  // Interrupt threshold control: no threshold
+  LPC_USBx->USBCMD_D &= ~(USB_USBCMD_D_ITC(0xFFUL));
+
+  // Default Initialize Control Endpoint 0
+  if (usbd_state.speed == ARM_USB_SPEED_HIGH) { // For High-speed
+    USBD_EndpointConfigure (0x00U, ARM_USB_ENDPOINT_CONTROL, 64U);
+    USBD_EndpointConfigure (0x80U, ARM_USB_ENDPOINT_CONTROL, 64U);
+  } else {                                      // For Full/Low-speed
+    USBD_EndpointConfigure (0x00U, ARM_USB_ENDPOINT_CONTROL,  8U);
+    USBD_EndpointConfigure (0x80U, ARM_USB_ENDPOINT_CONTROL,  8U);
+  }
+
+  // Set start of endpoint list address
+  LPC_USBx->ENDPOINTLISTADDR = (uint32_t)dQH;
+
+  // Setup lockouts off
+  LPC_USBx->USBMODE_D |= USB_USBMODE_D_SLOM;
+}
+
+/**
+  \fn          void USBD_HW_ReadSetupPacket (void)
+  \brief       Read Setup Packet to buffer.
+*/
+static void USBD_HW_ReadSetupPacket (void) {
+
+  do {
+    LPC_USBx->USBCMD_D |= USB_USBCMD_D_SUTW;            // Setup trip wire
+
+    // Copy Setup Packet Data to buffer
+    setup_packet[0] = dQH[0].setup[0];
+    setup_packet[1] = dQH[0].setup[1];
+  } while (!(LPC_USBx->USBCMD_D & LPC_USBx->USBCMD_D));
+
+  LPC_USBx->USBCMD_D &= ~USB_USBCMD_D_SUTW;             // Clear Setup trip wire
+
+  LPC_USBx->ENDPTSETUPSTAT = 1U;                        // Clear Setup bit
+
+}
+
+/**
+  \fn            void USBD_HW_EndpointTransfer (uint8_t ep_addr)
+  \brief         Start transfer on Endpoint.
+  \param[in]     ep_addr  Endpoint Address
+                  - ep_addr.0..3: Address
+                  - ep_addr.7:    Direction
+*/
+static void USBD_HW_EndpointTransfer (uint8_t ep_addr) {
+  dQH_t   *ptr_dqh;
+  dTD_t   *ptr_dtd;
+  uint8_t *data;
+  uint32_t ep_msk, num;
+  uint8_t  ep_idx;
+
+  ep_idx  =  EP_IDX(ep_addr);
+  ep_msk  =  EP_MSK(ep_addr);
+  ptr_dqh = &dQH[ep_idx];
+  ptr_dtd = &dTD[ep_idx];
+
+  data    =  ptr_dqh->data + ptr_dqh->num_transferred_total;
+  num     =  ptr_dqh->num  - ptr_dqh->num_transferred_total;
+
+  if (num > 0x4000U) { num = 0x4000U; } // Maximum transfer length is 16k
+
+  while (LPC_USBx->ENDPTSTAT & ep_msk);
+
+  memset (ptr_dtd, 0, sizeof(dTD_t));
+
+  // Driver does not support linked endpoint descriptors
+  // Next link pointer is not valid
+  ptr_dtd->next_dTD = 1U;
+
+  // Configure Transfer Descriptor
+  ptr_dtd->dTD_token |=  USB_bTD_TOKEN_TOTAL_BYTES(num) |       // Bytes to transfer
+                         USB_bTD_TOKEN_IOC              |       // Interrupt on complete
+                         USB_bTD_TOKEN_STATUS_ACTIVE    ;       // Transfer Active
+
+  // Set Buffer Addresses
+  ptr_dtd->buf[0]     =  (uint32_t)(data          );
+  ptr_dtd->buf[1]     =  (uint32_t)(data + 0x1000U);
+  ptr_dtd->buf[2]     =  (uint32_t)(data + 0x2000U);
+  ptr_dtd->buf[3]     =  (uint32_t)(data + 0x3000U);
+  ptr_dtd->buf[4]     =  (uint32_t)(data + 0x4000U);
+
+  ptr_dqh->dTD_token &= ~USB_bTD_TOKEN_STATUS_MSK;              // Clear status
+  ptr_dqh->next_dTD   =  (uint32_t)(ptr_dtd);                   // Save Transfer Descriptor address to Queue Head overlay
+
+  ptr_dqh->num_transferring = num;
+
+  LPC_USBx->ENDPTPRIME |= ep_msk;       // Prime Endpoint -> Start Transfer
+}
+
+
+// USBD Driver functions
+
+/**
+  \fn          ARM_DRIVER_VERSION USBD_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+*/
+static ARM_DRIVER_VERSION USBD_GetVersion (void) { return usbd_driver_version; }
+
+/**
+  \fn          ARM_USBD_CAPABILITIES USBD_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_USBD_CAPABILITIES
+*/
+static ARM_USBD_CAPABILITIES USBD_GetCapabilities (void) { return usbd_driver_capabilities; }
+
+/**
+  \fn          int32_t USBD_Initialize (ARM_USBD_SignalDeviceEvent_t   cb_device_event,
+                                        ARM_USBD_SignalEndpointEvent_t cb_endpoint_event)
+  \brief       Initialize USB Device Interface.
+  \param[in]   cb_device_event    Pointer to \ref ARM_USBD_SignalDeviceEvent
+  \param[in]   cb_endpoint_event  Pointer to \ref ARM_USBD_SignalEndpointEvent
+  \return      \ref execution_status
+*/
+static int32_t USBD_Initialize (ARM_USBD_SignalDeviceEvent_t   cb_device_event,
+                                ARM_USBD_SignalEndpointEvent_t cb_endpoint_event) {
+
+  if ((USB0_state & USBD_DRIVER_INITIALIZED) != 0U) { return ARM_DRIVER_OK; }
+
+  SignalDeviceEvent   = cb_device_event;
+  SignalEndpointEvent = cb_endpoint_event;
+
+  USB0_role   =  ARM_USB_ROLE_DEVICE;
+  USB0_PinsConfigure ();
+
+  USB0_state  =  USBD_DRIVER_INITIALIZED;
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t USBD_Uninitialize (void)
+  \brief       De-initialize USB Device Interface.
+  \return      \ref execution_status
+*/
+static int32_t USBD_Uninitialize (void) {
+
+  USB0_PinsUnconfigure ();
+  USB0_role   =  ARM_USB_ROLE_NONE;
+  USB0_state &= ~USBD_DRIVER_INITIALIZED;
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t USBD_PowerControl (ARM_POWER_STATE state)
+  \brief       Control USB Device Interface Power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+*/
+static int32_t USBD_PowerControl (ARM_POWER_STATE state) {
+
+  switch (state) {
+    case ARM_POWER_OFF:
+      NVIC_DisableIRQ      (USB0_IRQn);                 // Disable interrupt
+      NVIC_ClearPendingIRQ (USB0_IRQn);                 // Clear pending interrupt
+      USB0_state &= ~USBD_DRIVER_POWERED;               // Clear powered flag
+                                                        // Reset variables
+      setup_received =  0U;
+      memset((void *)&usbd_state, 0, sizeof(usbd_state));
+      memset((void *)dQH,         0, sizeof(dQH));
+      memset((void *)dTD,         0, sizeof(dTD));
+
+      if ((LPC_CGU->BASE_USB0_CLK & 1U) == 0U) {
+        LPC_CREG->CREG0 |=  (1U << 5);                  // Disable USB0 PHY
+        LPC_CCU1->CLK_USB0_CFG    &= ~1U;               // Disable USB0 Base Clock
+        while (LPC_CCU1->CLK_USB0_STAT    & 1U);
+        LPC_CCU1->CLK_M3_USB0_CFG &= ~1U;               // Disable USB0 Register Interface Clock
+        while (LPC_CCU1->CLK_M3_USB0_STAT & 1U);
+        LPC_CGU->BASE_USB0_CLK     =  1U;               // Disable Base Clock
+      }
+      break;
+
+    case ARM_POWER_FULL:
+      if ((USB0_state & USBD_DRIVER_INITIALIZED) == 0U) { return ARM_DRIVER_ERROR; }
+      if ((USB0_state & USBD_DRIVER_POWERED)     != 0U) { return ARM_DRIVER_OK; }
+
+      LPC_CGU->BASE_USB0_CLK     = (0x01U << 11) |      // Auto-block Enable
+                                   (0x07U << 24) ;      // Clock source: PLL0USB
+      LPC_CCU1->CLK_M3_USB0_CFG |=  1U;                 // Enable USB0 Register Interface Clock
+      while (!(LPC_CCU1->CLK_M3_USB0_STAT & 1U));
+      LPC_CCU1->CLK_USB0_CFG    |=  1U;                 // Enable USB0 Base Clock
+      while (!(LPC_CCU1->CLK_USB0_STAT    & 1U));
+
+      // Reset USB Controller
+      LPC_USBx->USBCMD_D = USB_USBCMD_D_RST;
+      while ((LPC_USBx->USBCMD_D & (USB_USBCMD_D_RS | USB_USBCMD_D_RST)) != 0U);
+
+      // Force device mode and set Setup lockouts off
+      LPC_USBx->USBMODE_D =  USB_USBMODE_D_CM1_0(2U) | USB_USBMODE_D_SLOM;
+
+      LPC_CREG->CREG0 &= ~(1U << 5);                    // Enable USB0 PHY
+
+      USBD_Reset ();                                    // Reset variables and endpoint settings
+
+#if  (RTE_USB_USB0_HS_EN)
+      LPC_USBx->PORTSC1_D &= ~USB_PORTSC1_D_PFSC;
+#else
+      LPC_USBx->PORTSC1_D |=  USB_PORTSC1_D_PFSC;
+#endif
+      // Configure OTG Register
+      LPC_USBx->OTGSC      =  USB_OTGSC_VD |            // VBUS discharge
+                              USB_OTGSC_OT ;            // OTG termination
+
+      // Enable interrupts
+      LPC_USBx->USBINTR_D  = (USB_USBINTR_D_UE  |       // USB interrupt enable
+                              USB_USBINTR_D_PCE |       // Port change detect interrupt enable
+                              USB_USBINTR_D_SLE |       // Suspend interrupt enable
+                              USB_USBINTR_D_URE);       // Reset interrupt enable
+
+      USB0_state |=  USBD_DRIVER_POWERED;               // Set powered flag
+      NVIC_EnableIRQ   (USB0_IRQn);                     // Enable interrupt
+      break;
+
+    default:
+      return ARM_DRIVER_ERROR_UNSUPPORTED;
+  }
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t USBD_DeviceConnect (void)
+  \brief       Connect USB Device.
+  \return      \ref execution_status
+*/
+static int32_t USBD_DeviceConnect (void) {
+
+  if ((USB0_state & USBD_DRIVER_POWERED) == 0U) { return ARM_DRIVER_ERROR; }
+
+  LPC_USBx->USBCMD_D |= USB_USBCMD_D_RS;                // Attach Device
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t USBD_DeviceDisconnect (void)
+  \brief       Disconnect USB Device.
+  \return      \ref execution_status
+*/
+static int32_t USBD_DeviceDisconnect (void) {
+
+  if ((USB0_state & USBD_DRIVER_POWERED) == 0U) { return ARM_DRIVER_ERROR; }
+
+  LPC_USBx->USBCMD_D &= ~USB_USBCMD_D_RS;               // Detach Device
+
+#if (RTE_USB0_IND0_PIN_EN)
+  LPC_USBx->PORTSC1_D &= ~USB_PORTSC1_D_PIC1_0(1);      // Clear indicator LED0
+#endif
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          ARM_USBD_STATE USBD_DeviceGetState (void)
+  \brief       Get current USB Device State.
+  \return      Device State \ref ARM_USBD_STATE
+*/
+static ARM_USBD_STATE USBD_DeviceGetState (void) {
+  ARM_USBD_STATE dev_state = { 0U, 0U, 0U };
+  uint32_t       portsc1_d;
+
+  if ((USB0_state & USBD_DRIVER_POWERED) == 0U) { return dev_state; }
+
+  portsc1_d = LPC_USBx->PORTSC1_D;
+  dev_state = usbd_state;
+
+  dev_state.active = ((portsc1_d & USB_PORTSC1_D_CCS) != 0U) &&
+                     ((portsc1_d & USB_USBDSTS_D_SLI) == 0U)  ;
+
+  return dev_state;
+}
+
+/**
+  \fn          int32_t USBD_DeviceRemoteWakeup (void)
+  \brief       Trigger USB Remote Wakeup.
+  \return      \ref execution_status
+*/
+static int32_t USBD_DeviceRemoteWakeup (void) {
+
+  if ((USB0_state & USBD_DRIVER_POWERED) == 0U) { return ARM_DRIVER_ERROR; }
+
+  LPC_USBx->PORTSC1_D &= ~USB_PORTSC1_D_PHCD;           // Enable PHY Clock
+  LPC_USBx->PORTSC1_D |=  USB_PORTSC1_D_FPR;            // Force Port Resume
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t USBD_DeviceSetAddress (uint8_t dev_addr)
+  \brief       Set USB Device Address.
+  \param[in]   dev_addr  Device Address
+  \return      \ref execution_status
+*/
+static int32_t USBD_DeviceSetAddress (uint8_t dev_addr) {
+
+  if ((USB0_state & USBD_DRIVER_POWERED) == 0U) { return ARM_DRIVER_ERROR; }
+
+  LPC_USBx->DEVICEADDR  = (dev_addr << USB_DEVICEADDR_USBADR_POS) & USB_DEVICEADDR_USBADR_MSK;
+  LPC_USBx->DEVICEADDR |=  USB_DEVICEADDR_USBADRA;
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t USBD_ReadSetupPacket (uint8_t *setup)
+  \brief       Read setup packet received over Control Endpoint.
+  \param[out]  setup  Pointer to buffer for setup packet
+  \return      \ref execution_status
+*/
+static int32_t USBD_ReadSetupPacket (uint8_t *setup) {
+
+  if ((USB0_state & USBD_DRIVER_POWERED) == 0U) { return ARM_DRIVER_ERROR; }
+  if (setup_received                     == 0U) { return ARM_DRIVER_ERROR; }
+
+  setup_received = 0U;
+  memcpy(setup, setup_packet, 8);
+
+  if (setup_received != 0U) {           // If new setup packet was received while this was being read
+    return ARM_DRIVER_ERROR;
+  }
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t USBD_EndpointConfigure (uint8_t  ep_addr,
+                                               uint8_t  ep_type,
+                                               uint16_t ep_max_packet_size)
+  \brief       Configure USB Endpoint.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \param[in]   ep_type  Endpoint Type (ARM_USB_ENDPOINT_xxx)
+  \param[in]   ep_max_packet_size Endpoint Maximum Packet Size
+  \return      \ref execution_status
+*/
+static int32_t USBD_EndpointConfigure (uint8_t  ep_addr,
+                                       uint8_t  ep_type,
+                                       uint16_t ep_max_packet_size) {
+  dQH_t   *ptr_dqh;
+  uint32_t ep_mult;
+  uint32_t ep_mps;
+  uint8_t  ep_num,ep_sll;
+
+  ep_num = EP_NUM(ep_addr);
+  if (ep_num > USBD_MAX_ENDPOINT_NUM)           { return ARM_DRIVER_ERROR; }
+  if ((USB0_state & USBD_DRIVER_POWERED) == 0U) { return ARM_DRIVER_ERROR; }
+
+  ptr_dqh = &dQH[EP_IDX(ep_addr)];
+  if (ptr_dqh->ep_active != 0U)                 { return ARM_DRIVER_ERROR_BUSY; }
+
+  ep_num  =  EP_NUM(ep_addr);
+  ep_sll  =  EP_SLL(ep_addr);
+  ep_mult = (ep_max_packet_size & ARM_USB_ENDPOINT_MICROFRAME_TRANSACTIONS_MASK) >> 11;
+  ep_mps  =  ep_max_packet_size & ARM_USB_ENDPOINT_MAX_PACKET_SIZE_MASK;
+
+  // Clear Endpoint Queue Head
+  memset((void *)ptr_dqh, 0, sizeof(dQH_t));
+
+  ptr_dqh->ep_type = ep_type;
+  if (ep_type == ARM_USB_ENDPOINT_ISOCHRONOUS) {
+    // For isochronous endpoints number of transactions per microframe in high-speed (or frame in full-speed)
+    // has to be 1 more than additional transactions per microframe for high-speed (or 1 for full-speed)
+    ep_mult++;
+  }
+
+  if ((ep_mult > 1U) && (usbd_state.speed == ARM_USB_SPEED_FULL)) { ep_mult = 1U; }
+
+  ptr_dqh->cap       = ((ep_mult << USB_EPQH_CAP_MULT_POS) & USB_EPQH_CAP_MULT_MSK) |
+                        (USB_EPQH_CAP_MAX_PACKET_LEN(ep_mps))                       |
+                        (USB_EPQH_CAP_ZLT)                                          |
+                       ((ep_addr == 0U) * USB_EPQH_CAP_IOS);
+  ptr_dqh->next_dTD  = 1U;
+  ptr_dqh->dTD_token = 0U;
+
+  USBD_HW_EndpointFlush(ep_addr);
+
+  // Clear Endpoint Control Settings
+  ENDPTCTRL(ep_num) &= ~((USB_ENDPTCTRL_RXS     |
+                          USB_ENDPTCTRL_RXT_MSK |
+                          USB_ENDPTCTRL_RXI     |
+                          USB_ENDPTCTRL_RXR     |
+                          USB_ENDPTCTRL_RXE     )
+                          << ep_sll);
+
+  // Set Endpoint Control Settings
+  ENDPTCTRL(ep_num) |=   (USB_ENDPTCTRL_RXT(ep_type) |  // Endpoint Type
+                          USB_ENDPTCTRL_RXR          |  // Data Tggle Rset
+                          USB_ENDPTCTRL_RXE          )  // Endpoint Enable
+                          << ep_sll;
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t USBD_EndpointUnconfigure (uint8_t ep_addr)
+  \brief       Unconfigure USB Endpoint.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \return      \ref execution_status
+*/
+static int32_t USBD_EndpointUnconfigure (uint8_t ep_addr) {
+  dQH_t   *ptr_dqh;
+  dTD_t   *ptr_dtd;
+  uint8_t  ep_idx, ep_num, ep_sll;
+
+  ep_num = EP_NUM(ep_addr);
+  if (ep_num > USBD_MAX_ENDPOINT_NUM)           { return ARM_DRIVER_ERROR; }
+  if ((USB0_state & USBD_DRIVER_POWERED) == 0U) { return ARM_DRIVER_ERROR; }
+
+  ep_idx  =  EP_IDX(ep_addr);
+  ptr_dqh = &dQH[ep_idx];
+  if (ptr_dqh->ep_active != 0U)                 { return ARM_DRIVER_ERROR_BUSY; }
+
+  ptr_dtd = &dTD[ep_idx];
+  ep_sll  =  EP_SLL(ep_addr);
+
+  // Clear Endpoint Control Settings
+  ENDPTCTRL(ep_num) &= ~((USB_ENDPTCTRL_RXS     |
+                          USB_ENDPTCTRL_RXT_MSK |
+                          USB_ENDPTCTRL_RXI     |
+                          USB_ENDPTCTRL_RXR     |
+                          USB_ENDPTCTRL_RXE     )
+                          << ep_sll);
+
+  ENDPTCTRL(ep_num)  |=  (USB_ENDPTCTRL_RXR << ep_sll);         // Data toggle reset
+
+  // Clear Endpoint Queue Head and Endpoint Transfer Descriptor
+  memset((void *)ptr_dqh, 0, sizeof(dQH_t));
+  memset((void *)ptr_dtd, 0, sizeof(dTD_t));
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t USBD_EndpointStall (uint8_t ep_addr, bool stall)
+  \brief       Set/Clear Stall for USB Endpoint.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \param[in]   stall  Operation
+                - \b false Clear
+                - \b true Set
+  \return      \ref execution_status
+*/
+static int32_t USBD_EndpointStall (uint8_t ep_addr, bool stall) {
+  dQH_t   *ptr_dqh;
+  uint8_t  ep_num, ep_sll;
+
+  ep_num = EP_NUM(ep_addr);
+  if (ep_num > USBD_MAX_ENDPOINT_NUM)           { return ARM_DRIVER_ERROR; }
+  if ((USB0_state & USBD_DRIVER_POWERED) == 0U) { return ARM_DRIVER_ERROR; }
+
+  ptr_dqh = &dQH[EP_IDX(ep_addr)];
+  if (ptr_dqh->ep_active != 0U)                 { return ARM_DRIVER_ERROR_BUSY; }
+
+  ep_sll  =  EP_SLL(ep_addr);
+
+  if (stall != 0U) {                    // Set endpoint stall
+    ENDPTCTRL(ep_num)  |=  (USB_ENDPTCTRL_RXS << ep_sll);
+  } else {                              // Clear endpoint stall
+    ENDPTCTRL(ep_num)  &= ~(USB_ENDPTCTRL_RXS << ep_sll);
+
+    ptr_dqh->dTD_token  = 0U;
+
+    USBD_HW_EndpointFlush(ep_addr);
+
+    ENDPTCTRL(ep_num)  |=  (USB_ENDPTCTRL_RXR << ep_sll);       // Data toggle reset
+  }
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t USBD_EndpointTransfer (uint8_t ep_addr, uint8_t *data, uint32_t num)
+  \brief       Read data from or Write data to USB Endpoint.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \param[out]  data Pointer to buffer for data to read or with data to write
+  \param[in]   num  Number of data bytes to transfer
+  \return      \ref execution_status
+*/
+static int32_t USBD_EndpointTransfer (uint8_t ep_addr, uint8_t *data, uint32_t num) {
+  dQH_t   *ptr_dqh;
+
+  if (EP_NUM(ep_addr) > USBD_MAX_ENDPOINT_NUM)  { return ARM_DRIVER_ERROR; }
+  if ((USB0_state & USBD_DRIVER_POWERED) == 0U) { return ARM_DRIVER_ERROR; }
+
+  ptr_dqh = &dQH[EP_IDX(ep_addr)];
+  if (ptr_dqh->ep_active != 0U)                 { return ARM_DRIVER_ERROR_BUSY; }
+
+  ptr_dqh->ep_active = 1U;
+
+  ptr_dqh->data                  = data;
+  ptr_dqh->num                   = num;
+  ptr_dqh->num_transferred_total = 0U;
+  ptr_dqh->num_transferring      = 0U;
+
+  USBD_HW_EndpointTransfer(ep_addr);    // Start transfer
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          uint32_t USBD_EndpointTransferGetResult (uint8_t ep_addr)
+  \brief       Get result of USB Endpoint transfer.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \return      number of successfully transferred data bytes
+*/
+static uint32_t USBD_EndpointTransferGetResult (uint8_t ep_addr) {
+
+  if (EP_NUM(ep_addr) > USBD_MAX_ENDPOINT_NUM) { return 0U; }
+
+  return (dQH[EP_IDX(ep_addr)].num_transferred_total);
+}
+
+/**
+  \fn          int32_t USBD_EndpointTransferAbort (uint8_t ep_addr)
+  \brief       Abort current USB Endpoint transfer.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \return      \ref execution_status
+*/
+static int32_t USBD_EndpointTransferAbort (uint8_t ep_addr) {
+  dQH_t   *ptr_dqh;
+  uint32_t ep_msk;
+  uint8_t  ep_num, ep_sll;
+
+  ep_num = EP_NUM(ep_addr);
+  if (ep_num > USBD_MAX_ENDPOINT_NUM)           { return ARM_DRIVER_ERROR; }
+  if ((USB0_state & USBD_DRIVER_POWERED) == 0U) { return ARM_DRIVER_ERROR; }
+
+  ptr_dqh = &dQH[EP_IDX(ep_addr)];
+  ep_msk  =  EP_MSK(ep_addr);
+  ep_sll  =  EP_SLL(ep_addr);
+
+  USBD_HW_EndpointFlush(ep_addr);
+
+  LPC_USBx->ENDPTCOMPLETE = ep_msk;                     // Clear Completed Flag
+  ENDPTCTRL(ep_num)  |=  (USB_ENDPTCTRL_RXR << ep_sll); // Data toggle reset
+
+  ptr_dqh->dTD_token &= ~0xFFU;
+
+  ptr_dqh->ep_active  =  0U;
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          uint16_t USBD_GetFrameNumber (void)
+  \brief       Get current USB Frame Number.
+  \return      Frame Number
+*/
+static uint16_t USBD_GetFrameNumber (void) {
+
+  if ((USB0_state & USBD_DRIVER_POWERED) == 0U) { return 0U; }
+
+  return ((LPC_USBx->FRINDEX_D & USB_FRINDEX_D_FRINDEX13_3_MSK) >> USB_FRINDEX_D_FRINDEX13_3_POS);
+}
+
+/**
+  \fn          void USBD0_IRQ (void)
+  \brief       USB0 Device Interrupt Routine (IRQ).
+*/
+void USBD0_IRQ (void) {
+  dQH_t   *ptr_dqh;
+  uint32_t sts, cmpl;
+  uint16_t ep_mps, num_transferred;
+  uint8_t  ep_num, ep_addr;
+
+  sts  = LPC_USBx->USBSTS_D & LPC_USBx->USBINTR_D;      // Read active interrupts
+  cmpl = LPC_USBx->ENDPTCOMPLETE;                       // Read Endpoint completed status
+  LPC_USBx->USBSTS_D      = sts;                        // Clear interrupts
+  LPC_USBx->ENDPTCOMPLETE = cmpl;                       // Clear Endpoint completed status
+
+  if ((sts & USB_USBDSTS_D_URI) != 0U) {                // Reset interrupt
+    USBD_Reset();
+    SignalDeviceEvent(ARM_USBD_EVENT_RESET);
+  }
+
+  if ((sts & USB_USBDSTS_D_SLI) != 0U) {                // Suspend interrupt
+    SignalDeviceEvent(ARM_USBD_EVENT_SUSPEND);
+
+#if (RTE_USB0_IND0_PIN_EN)
+    LPC_USBx->PORTSC1_D &= ~USB_PORTSC1_D_PIC1_0(1);    // Clear indicator LED0
+#endif
+  }
+
+  if ((sts & USB_USBDSTS_D_PCI) != 0U) {                // Port change detect interrupt
+    if (((LPC_USBx->PORTSC1_D & USB_PORTSC1_D_PSPD_MSK) >> USB_PORTSC1_D_PSPD_POS) == 2U) {
+      usbd_state.speed = ARM_USB_SPEED_HIGH;
+      SignalDeviceEvent(ARM_USBD_EVENT_HIGH_SPEED);
+    } else {
+      usbd_state.speed = ARM_USB_SPEED_FULL;
+    }
+
+#if (RTE_USB0_IND0_PIN_EN)
+    LPC_USBx->PORTSC1_D |= USB_PORTSC1_D_PIC1_0(1);     // Set indicator LED0
+#endif
+    SignalDeviceEvent(ARM_USBD_EVENT_RESUME);
+  }
+
+  if ((sts & USB_USBDSTS_D_UI) != 0U) {                 // USB interrupt - completed transfer
+    if ((LPC_USBx->ENDPTSETUPSTAT) != 0U) {             // Setup Packet Received
+      USBD_HW_ReadSetupPacket();
+      setup_received = 1U;
+      SignalEndpointEvent(0, ARM_USBD_EVENT_SETUP);
+    }
+
+    if ((cmpl & USB_ENDPTCOMPLETE_ETCE_MSK) != 0U) {    // IN Data Sent
+      for (ep_num = 0U; ep_num <= USBD_MAX_ENDPOINT_NUM; ep_num++) {
+        if ((cmpl & USB_ENDPTCOMPLETE_ETCE_MSK) & (1U << (ep_num + USB_ENDPTCOMPLETE_ETCE_POS))) {
+          ep_addr =  ep_num | ARM_USB_ENDPOINT_DIRECTION_MASK;
+          ptr_dqh = &dQH[EP_IDX(ep_addr)];
+
+          ptr_dqh->num_transferred_total += ptr_dqh->num_transferring;
+
+          // Check if all required IN data was sent
+          if (ptr_dqh->num == ptr_dqh->num_transferred_total) {
+            ptr_dqh->ep_active = 0U;                            // Clear Endpoint busy flag
+            SignalEndpointEvent(ep_addr, ARM_USBD_EVENT_IN);    // Send IN event
+          } else if (ptr_dqh->ep_active != 0U) {
+            USBD_HW_EndpointTransfer (ep_addr);                 // If this was not last transfer, start next
+          }
+        }
+      }
+    }
+
+    if ((cmpl & USB_ENDPTCOMPLETE_ERCE_MSK) != 0U) {    // OUT Data Received
+      for (ep_num = 0U; ep_num <= USBD_MAX_ENDPOINT_NUM; ep_num++) {
+        if ((cmpl & USB_ENDPTCOMPLETE_ERCE_MSK) & (1 << ep_num)) {
+          ep_addr =  ep_num;
+          ptr_dqh = &dQH[EP_IDX(ep_addr)];
+          ep_mps  = (ptr_dqh->cap & USB_EPQH_CAP_MAX_PACKET_LEN_MSK) >> USB_EPQH_CAP_MAX_PACKET_LEN_POS;
+
+          num_transferred = ptr_dqh->num_transferring - 
+                           ((ptr_dqh->dTD_token & USB_bTD_TOKEN_TOTAL_BYTES_MSK) >> USB_bTD_TOKEN_TOTAL_BYTES_POS);
+          ptr_dqh->num_transferred_total += num_transferred;
+
+          // Check if all OUT data was received:
+          //  - data terminated with ZLP or short packet or
+          //  - all required data received
+          if (((num_transferred % ep_mps) != 0U) || (ptr_dqh->num == ptr_dqh->num_transferred_total)) {
+            ptr_dqh->ep_active = 0U;                            // Clear Endpoint busy flag
+            SignalEndpointEvent(ep_addr, ARM_USBD_EVENT_OUT);   // Send OUT event
+          } else if (ptr_dqh->ep_active != 0U) {
+            USBD_HW_EndpointTransfer (ep_addr);                 // If this was not last transfer, start next
+          }
+        }
+      }
+    }
+  }
+}
+
+ARM_DRIVER_USBD Driver_USBD0 = {
+  USBD_GetVersion,
+  USBD_GetCapabilities,
+  USBD_Initialize,
+  USBD_Uninitialize,
+  USBD_PowerControl,
+  USBD_DeviceConnect,
+  USBD_DeviceDisconnect,
+  USBD_DeviceGetState,
+  USBD_DeviceRemoteWakeup,
+  USBD_DeviceSetAddress,
+  USBD_ReadSetupPacket,
+  USBD_EndpointConfigure,
+  USBD_EndpointUnconfigure,
+  USBD_EndpointStall,
+  USBD_EndpointTransfer,
+  USBD_EndpointTransferGetResult,
+  USBD_EndpointTransferAbort,
+  USBD_GetFrameNumber
+};

CMSIS/Pack/Example/CMSIS_Driver/USBD1_LPC18xx.c

@@ -0,0 +1,899 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        02. March 2016
+ * $Revision:    V2.7
+ *
+ * Driver:       Driver_USBD1
+ * Configured:   via RTE_Device.h configuration file
+ * Project:      USB Device Driver for NXP LPC18xx
+ * --------------------------------------------------------------------------
+ * Use the following configuration settings in the middleware component
+ * to connect to this driver.
+ *
+ *   Configuration Setting                  Value
+ *   ---------------------                  -----
+ *   Connect to hardware via Driver_USBD# = 1
+ * --------------------------------------------------------------------------
+ * Defines used for driver configuration (at compile time):
+ *
+ *   USBD_MAX_ENDPOINT_NUM:  defines maximum number of IN/OUT Endpoint pairs 
+ *                           that driver will support with Control Endpoint 0
+ *                           not included, this value impacts driver memory
+ *                           requirements
+ *     - default value: 3
+ *     - maximum value: 3
+ * -------------------------------------------------------------------------- */
+
+/* History:
+ *  Version 2.7
+ *    Removed unnecessary __packed specifier for structures dQH_t and dTD_t
+ *  Version 2.6
+ *    Corrected PowerControl function for conditional Power full (driver must be initialized)
+ *  Version 2.5
+ *    PowerControl for Power OFF and Uninitialize functions made unconditional
+ *  Version 2.4
+ *    Corrected isochronous endpoint configuration
+ *    Corrected transfer procedure
+ *  Version 2.3
+ *    Corrected isochronous transfer functionality
+ *  Version 2.2
+ *    Corrected return value in USBD_PowerControl function.
+ *  Version 2.1
+ *    Added USB_LPC18xx_USB1.h with register bit definitions
+ *    Pin configuration moved to USB_LPC18xx.c
+ *  Version 2.0
+ *    Updated to 2.00 API
+ *  Version 1.3
+ *    Re-implementation of the driver
+ *  Version 1.2
+ *    Updated USB1 pin configurations
+ *  Version 1.1
+ *    Based on API V1.10 (namespace prefix ARM_ added)
+ *  Version 1.0
+ *    Initial release
+ */
+
+
+#include <stdint.h>
+#include <string.h>
+
+#include "Driver_USBD.h"
+
+#include "LPC18xx.h"
+#include "USB_LPC18xx.h"
+#include "SCU_LPC18xx.h"
+
+#include "RTE_Device.h"
+#include "RTE_Components.h"
+
+#if      (RTE_USB_USB1 == 0)
+#error   "USB1 is not enabled in the RTE_Device.h!"
+#endif
+#if      (RTE_USB_USB1_FS_PHY_EN && RTE_USB_USB1_HS_PHY_EN)
+#error   "Both full-speed and high-speed PHY can not be selected at the same time!"
+#endif
+
+#ifndef USBD_MAX_ENDPOINT_NUM
+#define USBD_MAX_ENDPOINT_NUM           3U
+#endif
+#if    (USBD_MAX_ENDPOINT_NUM > 3)
+#error  Too many Endpoints, maximum IN/OUT Endpoint pairs that this driver supports is 3 !!!
+#endif
+
+extern uint8_t USB1_role;
+extern uint8_t USB1_state;
+
+extern void USB1_PinsConfigure   (void);
+extern void USB1_PinsUnconfigure (void);
+
+
+// USBD Driver *****************************************************************
+
+#define ARM_USBD_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,7)
+
+// Driver Version
+static const ARM_DRIVER_VERSION usbd_driver_version = { ARM_USBD_API_VERSION, ARM_USBD_DRV_VERSION };
+
+// Driver Capabilities
+static const ARM_USBD_CAPABILITIES usbd_driver_capabilities = {
+  0U,   // VBUS Detection
+  0U,   // Event VBUS On
+  0U    // Event VBUS Off
+};
+
+#define LPC_USBx                        LPC_USB1
+#define ENDPTCTRL(ep_num)               (*(volatile uint32_t *)((uint32_t)(&LPC_USBx->ENDPTCTRL0) + 4U * ep_num))
+
+#define EP_NUM(ep_addr)                 (ep_addr & ARM_USB_ENDPOINT_NUMBER_MASK)
+#define EP_DIR(ep_addr)                 ((ep_addr >>  7) & 1U)
+#define EP_SLL(ep_addr)                 (EP_DIR(ep_addr) * 16U)
+#define EP_IDX(ep_addr)                 ((EP_NUM(ep_addr) * 2U) + ((ep_addr >> 7) & 1U))
+#define EP_MSK(ep_addr)                 (1UL << (EP_NUM(ep_addr) + EP_SLL(ep_addr)))
+
+typedef struct {                        // USB Device Endpoint Queue Head
+  uint32_t  cap;
+  uint32_t  curr_dTD;
+  uint32_t  next_dTD;
+  uint32_t  dTD_token;
+  uint32_t  buf[5];
+  uint32_t  reserved;
+  uint32_t  setup[2];
+                                        // Use reminder of 64 bytes for transfer information
+  uint8_t  *data;
+  uint32_t  num;
+  uint32_t  num_transferred_total;
+  uint16_t  num_transferring;
+  uint8_t   ep_type;
+  uint8_t   ep_active;
+} dQH_t;
+
+typedef struct {                        // USB Device Endpoint Transfer Descriptor
+  uint32_t  next_dTD;
+  uint32_t  dTD_token;
+  uint32_t  buf[5];
+  uint32_t  reserved;
+} dTD_t;
+
+static ARM_USBD_SignalDeviceEvent_t   SignalDeviceEvent;
+static ARM_USBD_SignalEndpointEvent_t SignalEndpointEvent;
+
+static ARM_USBD_STATE      usbd_state;
+
+static uint32_t            setup_packet[2];     // Setup packet data
+static volatile uint8_t    setup_received;      // Setup packet received
+
+static dQH_t __align(2048) dQH[(USBD_MAX_ENDPOINT_NUM + 1U) * 2U];      // Queue Heads
+static dTD_t __align(  32) dTD[(USBD_MAX_ENDPOINT_NUM + 1U) * 2U];      // Transfer Descriptors
+
+// Function prototypes
+static int32_t USBD_EndpointConfigure (uint8_t ep_addr, uint8_t ep_type, uint16_t ep_max_packet_size);
+
+
+// Auxiliary functions
+
+/**
+  \fn          void USBD_HW_EndpointFlush (uint8_t ep_addr)
+  \brief       Flush Endpoint.
+*/
+static void USBD_HW_EndpointFlush (uint8_t ep_addr) {
+  uint32_t ep_msk;
+
+  ep_msk = EP_MSK(ep_addr);
+
+  LPC_USBx->ENDPTFLUSH = ep_msk;
+  while (LPC_USBx->ENDPTFLUSH & ep_msk);
+}
+
+/**
+  \fn          void USBD_Reset (void)
+  \brief       Reset USB Endpoint settings and variables.
+*/
+static void USBD_Reset (void) {
+  uint8_t i;
+
+  // Reset global variables
+  setup_packet[0] = 0U;
+  setup_packet[1] = 0U;
+  setup_received  = 0U;
+  memset((void *)&usbd_state, 0, sizeof(usbd_state));
+  memset((void *)dQH,         0, sizeof(dQH));
+  memset((void *)dTD,         0, sizeof(dTD));
+  for (i = 1U; i <= USBD_MAX_ENDPOINT_NUM; i++) {
+    ENDPTCTRL(i) &= ~(USB_ENDPTCTRL_RXE | USB_ENDPTCTRL_TXE);
+  }
+
+  // Clear interrupts
+  LPC_USBx->ENDPTNAK       = 0xFFFFFFFFUL;
+  LPC_USBx->ENDPTNAKEN     = 0U;
+  LPC_USBx->USBSTS_D       = 0xFFFFFFFFUL;
+  LPC_USBx->ENDPTSETUPSTAT = LPC_USBx->ENDPTSETUPSTAT;
+  LPC_USBx->ENDPTCOMPLETE  = LPC_USBx->ENDPTCOMPLETE;
+
+  while (LPC_USBx->ENDPTPRIME);
+
+  // Clear all Primed buffers
+  LPC_USBx->ENDPTFLUSH = 0xFFFFFFFFUL;
+  while (LPC_USBx->ENDPTFLUSH);
+
+  // Interrupt threshold control: no threshold
+  LPC_USBx->USBCMD_D &= ~(USB_USBCMD_D_ITC(0xFFUL));
+
+  // Default Initialize Control Endpoint 0
+  if (usbd_state.speed == ARM_USB_SPEED_HIGH) { // For High-speed
+    USBD_EndpointConfigure (0x00U, ARM_USB_ENDPOINT_CONTROL, 64U);
+    USBD_EndpointConfigure (0x80U, ARM_USB_ENDPOINT_CONTROL, 64U);
+  } else {                                      // For Full/Low-speed
+    USBD_EndpointConfigure (0x00U, ARM_USB_ENDPOINT_CONTROL,  8U);
+    USBD_EndpointConfigure (0x80U, ARM_USB_ENDPOINT_CONTROL,  8U);
+  }
+
+  // Set start of endpoint list address
+  LPC_USBx->ENDPOINTLISTADDR = (uint32_t)dQH;
+
+  // Setup lockouts off
+  LPC_USBx->USBMODE_D |= USB_USBMODE_D_SLOM;
+}
+
+/**
+  \fn          void USBD_HW_ReadSetupPacket (void)
+  \brief       Read Setup Packet to buffer.
+*/
+static void USBD_HW_ReadSetupPacket (void) {
+
+  do {
+    LPC_USBx->USBCMD_D |= USB_USBCMD_D_SUTW;            // Setup trip wire
+
+    // Copy Setup Packet Data to buffer
+    setup_packet[0] = dQH[0].setup[0];
+    setup_packet[1] = dQH[0].setup[1];
+  } while (!(LPC_USBx->USBCMD_D & LPC_USBx->USBCMD_D));
+
+  LPC_USBx->USBCMD_D &= ~USB_USBCMD_D_SUTW;             // Clear Setup trip wire
+
+  LPC_USBx->ENDPTSETUPSTAT = 1U;                        // Clear Setup bit
+
+}
+
+/**
+  \fn            void USBD_HW_EndpointTransfer (uint8_t ep_addr)
+  \brief         Start transfer on Endpoint.
+  \param[in]     ep_addr  Endpoint Address
+                  - ep_addr.0..3: Address
+                  - ep_addr.7:    Direction
+*/
+static void USBD_HW_EndpointTransfer (uint8_t ep_addr) {
+  dQH_t   *ptr_dqh;
+  dTD_t   *ptr_dtd;
+  uint8_t *data;
+  uint32_t ep_msk, num;
+  uint8_t  ep_idx;
+
+  ep_idx  =  EP_IDX(ep_addr);
+  ep_msk  =  EP_MSK(ep_addr);
+  ptr_dqh = &dQH[ep_idx];
+  ptr_dtd = &dTD[ep_idx];
+
+  data    =  ptr_dqh->data + ptr_dqh->num_transferred_total;
+  num     =  ptr_dqh->num  - ptr_dqh->num_transferred_total;
+
+  if (num > 0x4000U) { num = 0x4000U; } // Maximum transfer length is 16k
+
+  while (LPC_USBx->ENDPTSTAT & ep_msk);
+
+  memset (ptr_dtd, 0, sizeof(dTD_t));
+
+  // Driver does not support linked endpoint descriptors
+  // Next link pointer is not valid
+  ptr_dtd->next_dTD = 1U;
+
+  // Configure Transfer Descriptor
+  ptr_dtd->dTD_token |=  USB_bTD_TOKEN_TOTAL_BYTES(num) |       // Bytes to transfer
+                         USB_bTD_TOKEN_IOC              |       // Interrupt on complete
+                         USB_bTD_TOKEN_STATUS_ACTIVE    ;       // Transfer Active
+
+  // Set Buffer Addresses
+  ptr_dtd->buf[0]     =  (uint32_t)(data          );
+  ptr_dtd->buf[1]     =  (uint32_t)(data + 0x1000U);
+  ptr_dtd->buf[2]     =  (uint32_t)(data + 0x2000U);
+  ptr_dtd->buf[3]     =  (uint32_t)(data + 0x3000U);
+  ptr_dtd->buf[4]     =  (uint32_t)(data + 0x4000U);
+
+  ptr_dqh->dTD_token &= ~USB_bTD_TOKEN_STATUS_MSK;              // Clear status
+  ptr_dqh->next_dTD   =  (uint32_t)(ptr_dtd);                   // Save Transfer Descriptor address to Queue Head overlay
+
+  ptr_dqh->num_transferring = num;
+
+  LPC_USBx->ENDPTPRIME |= ep_msk;       // Prime Endpoint -> Start Transfer
+}
+
+
+// USBD Driver functions
+
+/**
+  \fn          ARM_DRIVER_VERSION USBD_GetVersion (void)
+  \brief       Get driver version.
+  \return      \ref ARM_DRIVER_VERSION
+*/
+static ARM_DRIVER_VERSION USBD_GetVersion (void) { return usbd_driver_version; }
+
+/**
+  \fn          ARM_USBD_CAPABILITIES USBD_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_USBD_CAPABILITIES
+*/
+static ARM_USBD_CAPABILITIES USBD_GetCapabilities (void) { return usbd_driver_capabilities; }
+
+/**
+  \fn          int32_t USBD_Initialize (ARM_USBD_SignalDeviceEvent_t   cb_device_event,
+                                        ARM_USBD_SignalEndpointEvent_t cb_endpoint_event)
+  \brief       Initialize USB Device Interface.
+  \param[in]   cb_device_event    Pointer to \ref ARM_USBD_SignalDeviceEvent
+  \param[in]   cb_endpoint_event  Pointer to \ref ARM_USBD_SignalEndpointEvent
+  \return      \ref execution_status
+*/
+static int32_t USBD_Initialize (ARM_USBD_SignalDeviceEvent_t   cb_device_event,
+                                ARM_USBD_SignalEndpointEvent_t cb_endpoint_event) {
+
+  if ((USB1_state & USBD_DRIVER_INITIALIZED) != 0U) { return ARM_DRIVER_OK; }
+
+  SignalDeviceEvent   = cb_device_event;
+  SignalEndpointEvent = cb_endpoint_event;
+
+  USB1_role   =  ARM_USB_ROLE_DEVICE;
+  USB1_PinsConfigure ();
+
+  USB1_state  =  USBD_DRIVER_INITIALIZED;
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t USBD_Uninitialize (void)
+  \brief       De-initialize USB Device Interface.
+  \return      \ref execution_status
+*/
+static int32_t USBD_Uninitialize (void) {
+
+  USB1_PinsUnconfigure ();
+  USB1_role   =  ARM_USB_ROLE_NONE;
+  USB1_state &= ~USBD_DRIVER_INITIALIZED;
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t USBD_PowerControl (ARM_POWER_STATE state)
+  \brief       Control USB Device Interface Power.
+  \param[in]   state  Power state
+  \return      \ref execution_status
+*/
+static int32_t USBD_PowerControl (ARM_POWER_STATE state) {
+
+  switch (state) {
+    case ARM_POWER_OFF:
+      NVIC_DisableIRQ      (USB1_IRQn);                 // Disable interrupt
+      NVIC_ClearPendingIRQ (USB1_IRQn);                 // Clear pending interrupt
+      USB1_state &= ~USBD_DRIVER_POWERED;               // Clear powered flag
+                                                        // Reset variables
+      setup_received =  0U;
+      memset((void *)&usbd_state, 0, sizeof(usbd_state));
+      memset((void *)dQH,         0, sizeof(dQH));
+      memset((void *)dTD,         0, sizeof(dTD));
+
+#if (!RTE_USB_USB1_HS_PHY_EN)
+      SCU_USB1_PinConfigure (SCU_USB1_PIN_CFG_ESEA);    // Reset SCU Register
+#endif
+
+      if ((LPC_CGU->BASE_USB1_CLK & 1U) ==  0U) {
+        LPC_CCU1->CLK_USB1_CFG    &= ~1U;               // Disable USB1 Base Clock
+        while (LPC_CCU1->CLK_USB1_STAT    & 1U);
+        LPC_CCU1->CLK_M3_USB1_CFG &= ~1U;               // Disable USB1 Register Interface Clock
+        while (LPC_CCU1->CLK_M3_USB1_STAT & 1U);
+        LPC_CGU->BASE_USB1_CLK     =  1U;               // Disable Base Clock
+      }
+      break;
+
+    case ARM_POWER_FULL:
+      if ((USB1_state & USBD_DRIVER_INITIALIZED) == 0U) { return ARM_DRIVER_ERROR; }
+      if ((USB1_state & USBD_DRIVER_POWERED)     != 0U) { return ARM_DRIVER_OK; }
+
+      LPC_CGU->BASE_USB1_CLK     = (0x01U << 11) |      // Auto-block Enable
+                                   (0x0CU << 24) ;      // Clock source: IDIVA
+      LPC_CCU1->CLK_M3_USB1_CFG |=  1U;                 // Enable USB1 Register Interface Clock
+      while (!(LPC_CCU1->CLK_M3_USB1_STAT & 1U));
+      LPC_CCU1->CLK_USB1_CFG    |=  1U;                 // Enable USB1 Base Clock
+      while (!(LPC_CCU1->CLK_USB1_STAT    & 1U));
+
+      // Reset USB Controller
+      LPC_USBx->USBCMD_D = USB_USBCMD_D_RST;
+      while (LPC_USBx->USBCMD_D & (USB_USBCMD_D_RS | USB_USBCMD_D_RST));
+
+      // Force device mode and set Setup lockouts off
+      LPC_USBx->USBMODE_D =  USB_USBMODE_D_CM1_0(2U) | USB_USBMODE_D_SLOM;
+
+      // Clear Transceiver Selection
+      LPC_USBx->PORTSC1_D &= ~(USB_PORTSC1_D_PTS_MSK | USB_PORTSC1_D_PFSC | USB_PORTSC1_D_PHCD);
+
+      USBD_Reset ();                                    // Reset variables and endpoint settings
+
+#if  (RTE_USB_USB1_HS_PHY_EN)
+      // ULPI Selected
+      LPC_USBx->PORTSC1_D |=   USB_PORTSC1_D_PTS(2U);   // Activate ULPI
+#else
+      // Serial/1.1 PHY selected and Full-speed forced
+      LPC_USBx->PORTSC1_D |=   USB_PORTSC1_D_PTS(3UL) | USB_PORTSC1_D_PFSC;
+      SCU_USB1_PinConfigure (SCU_USB1_PIN_CFG_ESEA |
+                             SCU_USB1_PIN_CFG_EPWR);
+#endif
+
+      // Enable interrupts
+      LPC_USBx->USBINTR_D  = (USB_USBINTR_D_UE  |       // USB interrupt enable
+                              USB_USBINTR_D_PCE |       // Port change detect interrupt enable
+                              USB_USBINTR_D_SLE |       // Suspend interrupt enable
+                              USB_USBINTR_D_URE);       // Reset interrupt enable
+
+      USB1_state |=  USBD_DRIVER_POWERED;               // Set powered flag
+      NVIC_EnableIRQ   (USB1_IRQn);                     // Enable interrupt
+      break;
+
+    default:
+      return ARM_DRIVER_ERROR_UNSUPPORTED;
+  }
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t USBD_DeviceConnect (void)
+  \brief       Connect USB Device.
+  \return      \ref execution_status
+*/
+static int32_t USBD_DeviceConnect (void) {
+
+  if ((USB1_state & USBD_DRIVER_POWERED) == 0U) { return ARM_DRIVER_ERROR; }
+
+  LPC_USBx->USBCMD_D |= USB_USBCMD_D_RS;                // Attach Device
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t USBD_DeviceDisconnect (void)
+  \brief       Disconnect USB Device.
+  \return      \ref execution_status
+*/
+static int32_t USBD_DeviceDisconnect (void) {
+
+  if ((USB1_state & USBD_DRIVER_POWERED) == 0U) { return ARM_DRIVER_ERROR; }
+
+  LPC_USBx->USBCMD_D &= ~USB_USBCMD_D_RS;               // Detach Device
+
+#if (RTE_USB1_IND0_PIN_EN)
+  LPC_USBx->PORTSC1_D &= ~USB_PORTSC1_D_PIC1_0(1);      // Clear indicator LED0
+#endif
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          ARM_USBD_STATE USBD_DeviceGetState (void)
+  \brief       Get current USB Device State.
+  \return      Device State \ref ARM_USBD_STATE
+*/
+static ARM_USBD_STATE USBD_DeviceGetState (void) {
+  ARM_USBD_STATE dev_state = { 0U, 0U, 0U };
+  uint32_t       portsc1_d;
+
+  if ((USB1_state & USBD_DRIVER_POWERED) == 0U) { return dev_state; }
+
+  portsc1_d = LPC_USBx->PORTSC1_D;
+  dev_state = usbd_state;
+
+  dev_state.active = ((portsc1_d & USB_PORTSC1_D_CCS) != 0U) &&
+                     ((portsc1_d & USB_USBDSTS_D_SLI) == 0U)  ;
+
+  return dev_state;
+}
+
+/**
+  \fn          int32_t USBD_DeviceRemoteWakeup (void)
+  \brief       Trigger USB Remote Wakeup.
+  \return      \ref execution_status
+*/
+static int32_t USBD_DeviceRemoteWakeup (void) {
+
+  if ((USB1_state & USBD_DRIVER_POWERED) == 0U) { return ARM_DRIVER_ERROR; }
+
+  LPC_USBx->PORTSC1_D &= ~USB_PORTSC1_D_PHCD;           // Enable PHY Clock
+  LPC_USBx->PORTSC1_D |=  USB_PORTSC1_D_FPR;            // Force Port Resume
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t USBD_DeviceSetAddress (uint8_t dev_addr)
+  \brief       Set USB Device Address.
+  \param[in]   dev_addr  Device Address
+  \return      \ref execution_status
+*/
+static int32_t USBD_DeviceSetAddress (uint8_t dev_addr) {
+
+  if ((USB1_state & USBD_DRIVER_POWERED) == 0U) { return ARM_DRIVER_ERROR; }
+
+  LPC_USBx->DEVICEADDR  = (dev_addr << USB_DEVICEADDR_USBADR_POS) & USB_DEVICEADDR_USBADR_MSK;
+  LPC_USBx->DEVICEADDR |=  USB_DEVICEADDR_USBADRA;
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t USBD_ReadSetupPacket (uint8_t *setup)
+  \brief       Read setup packet received over Control Endpoint.
+  \param[out]  setup  Pointer to buffer for setup packet
+  \return      \ref execution_status
+*/
+static int32_t USBD_ReadSetupPacket (uint8_t *setup) {
+
+  if ((USB1_state & USBD_DRIVER_POWERED) == 0U) { return ARM_DRIVER_ERROR; }
+  if (setup_received                     == 0U) { return ARM_DRIVER_ERROR; }
+
+  setup_received = 0U;
+  memcpy(setup, setup_packet, 8);
+
+  if (setup_received != 0U) {           // If new setup packet was received while this was being read
+    return ARM_DRIVER_ERROR;
+  }
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t USBD_EndpointConfigure (uint8_t  ep_addr,
+                                               uint8_t  ep_type,
+                                               uint16_t ep_max_packet_size)
+  \brief       Configure USB Endpoint.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \param[in]   ep_type  Endpoint Type (ARM_USB_ENDPOINT_xxx)
+  \param[in]   ep_max_packet_size Endpoint Maximum Packet Size
+  \return      \ref execution_status
+*/
+static int32_t USBD_EndpointConfigure (uint8_t  ep_addr,
+                                       uint8_t  ep_type,
+                                       uint16_t ep_max_packet_size) {
+  dQH_t   *ptr_dqh;
+  uint32_t ep_mult;
+  uint32_t ep_mps;
+  uint8_t  ep_num, ep_sll;
+
+  ep_num = EP_NUM(ep_addr);
+  if (ep_num > USBD_MAX_ENDPOINT_NUM)           { return ARM_DRIVER_ERROR; }
+  if ((USB1_state & USBD_DRIVER_POWERED) == 0U) { return ARM_DRIVER_ERROR; }
+
+  ptr_dqh = &dQH[EP_IDX(ep_addr)];
+  if (ptr_dqh->ep_active != 0U)                 { return ARM_DRIVER_ERROR_BUSY; }
+
+  ep_num  =  EP_NUM(ep_addr);
+  ep_sll  =  EP_SLL(ep_addr);
+  ep_mult = (ep_max_packet_size & ARM_USB_ENDPOINT_MICROFRAME_TRANSACTIONS_MASK) >> 11;
+  ep_mps  =  ep_max_packet_size & ARM_USB_ENDPOINT_MAX_PACKET_SIZE_MASK;
+
+  // Clear Endpoint Queue Head
+  memset((void *)ptr_dqh, 0, sizeof(dQH_t));
+
+  ptr_dqh->ep_type = ep_type;
+  if (ep_type == ARM_USB_ENDPOINT_ISOCHRONOUS) {
+    // For isochronous endpoints number of transactions per microframe in high-speed (or frame in full-speed)
+    // has to be 1 more than additional transactions per microframe for high-speed (or 1 for full-speed)
+    ep_mult++;
+  }
+
+  if ((ep_mult > 1U) && (usbd_state.speed == ARM_USB_SPEED_FULL)) { ep_mult = 1U; }
+
+  ptr_dqh->cap       = ((ep_mult << USB_EPQH_CAP_MULT_POS) & USB_EPQH_CAP_MULT_MSK) |
+                        (USB_EPQH_CAP_MAX_PACKET_LEN(ep_mps))                       |
+                        (USB_EPQH_CAP_ZLT)                                          |
+                       ((ep_addr == 0U) * USB_EPQH_CAP_IOS);
+  ptr_dqh->next_dTD  = 1U;
+  ptr_dqh->dTD_token = 0U;
+
+  USBD_HW_EndpointFlush(ep_addr);
+
+  // Clear Endpoint Control Settings
+  ENDPTCTRL(ep_num) &= ~((USB_ENDPTCTRL_RXS     |
+                          USB_ENDPTCTRL_RXT_MSK |
+                          USB_ENDPTCTRL_RXI     |
+                          USB_ENDPTCTRL_RXR     |
+                          USB_ENDPTCTRL_RXE     )
+                          << ep_sll);
+
+  // Set Endpoint Control Settings
+  ENDPTCTRL(ep_num) |=   (USB_ENDPTCTRL_RXT(ep_type) |  // Endpoint Type
+                          USB_ENDPTCTRL_RXR          |  // Data Tggle Rset
+                          USB_ENDPTCTRL_RXE          )  // Endpoint Enable
+                          << ep_sll;
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t USBD_EndpointUnconfigure (uint8_t ep_addr)
+  \brief       Unconfigure USB Endpoint.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \return      \ref execution_status
+*/
+static int32_t USBD_EndpointUnconfigure (uint8_t ep_addr) {
+  dQH_t   *ptr_dqh;
+  dTD_t   *ptr_dtd;
+  uint8_t  ep_idx, ep_num, ep_sll;
+
+  ep_num = EP_NUM(ep_addr);
+  if (ep_num > USBD_MAX_ENDPOINT_NUM)           { return ARM_DRIVER_ERROR; }
+  if ((USB1_state & USBD_DRIVER_POWERED) == 0U) { return ARM_DRIVER_ERROR; }
+
+  ep_idx  =  EP_IDX(ep_addr);
+  ptr_dqh = &dQH[ep_idx];
+  if (ptr_dqh->ep_active != 0U)                 { return ARM_DRIVER_ERROR_BUSY; }
+
+  ptr_dtd = &dTD[ep_idx];
+  ep_sll  =  EP_SLL(ep_addr);
+
+  // Clear Endpoint Control Settings
+  ENDPTCTRL(ep_num) &= ~((USB_ENDPTCTRL_RXS     |
+                          USB_ENDPTCTRL_RXT_MSK |
+                          USB_ENDPTCTRL_RXI     |
+                          USB_ENDPTCTRL_RXR     |
+                          USB_ENDPTCTRL_RXE     )
+                          << ep_sll);
+
+  ENDPTCTRL(ep_num)  |=  (USB_ENDPTCTRL_RXR << ep_sll);         // Data toggle reset
+
+  // Clear Endpoint Queue Head and Endpoint Transfer Descriptor
+  memset((void *)ptr_dqh, 0, sizeof(dQH_t));
+  memset((void *)ptr_dtd, 0, sizeof(dTD_t));
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t USBD_EndpointStall (uint8_t ep_addr, bool stall)
+  \brief       Set/Clear Stall for USB Endpoint.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \param[in]   stall  Operation
+                - \b false Clear
+                - \b true Set
+  \return      \ref execution_status
+*/
+static int32_t USBD_EndpointStall (uint8_t ep_addr, bool stall) {
+  dQH_t   *ptr_dqh;
+  uint8_t  ep_num, ep_sll;
+
+  ep_num = EP_NUM(ep_addr);
+  if (ep_num > USBD_MAX_ENDPOINT_NUM)           { return ARM_DRIVER_ERROR; }
+  if ((USB1_state & USBD_DRIVER_POWERED) == 0U) { return ARM_DRIVER_ERROR; }
+
+  ptr_dqh = &dQH[EP_IDX(ep_addr)];
+  if (ptr_dqh->ep_active != 0U)                 { return ARM_DRIVER_ERROR_BUSY; }
+
+  ep_sll  =  EP_SLL(ep_addr);
+
+  if (stall != 0U) {                    // Set endpoint stall
+    ENDPTCTRL(ep_num)  |=  (USB_ENDPTCTRL_RXS << ep_sll);
+  } else {                              // Clear endpoint stall
+    ENDPTCTRL(ep_num)  &= ~(USB_ENDPTCTRL_RXS << ep_sll);
+
+    ptr_dqh->dTD_token  = 0U;
+
+    USBD_HW_EndpointFlush(ep_addr);
+
+    ENDPTCTRL(ep_num)  |=  (USB_ENDPTCTRL_RXR << ep_sll);       // Data toggle reset
+  }
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t USBD_EndpointTransfer (uint8_t ep_addr, uint8_t *data, uint32_t num)
+  \brief       Read data from or Write data to USB Endpoint.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \param[out]  data Pointer to buffer for data to read or with data to write
+  \param[in]   num  Number of data bytes to transfer
+  \return      \ref execution_status
+*/
+static int32_t USBD_EndpointTransfer (uint8_t ep_addr, uint8_t *data, uint32_t num) {
+  dQH_t   *ptr_dqh;
+
+  if (EP_NUM(ep_addr) > USBD_MAX_ENDPOINT_NUM)  { return ARM_DRIVER_ERROR; }
+  if ((USB1_state & USBD_DRIVER_POWERED) == 0U) { return ARM_DRIVER_ERROR; }
+
+  ptr_dqh = &dQH[EP_IDX(ep_addr)];
+  if (ptr_dqh->ep_active != 0U)                 { return ARM_DRIVER_ERROR_BUSY; }
+
+  ptr_dqh->ep_active = 1U;
+
+  ptr_dqh->data                  = data;
+  ptr_dqh->num                   = num;
+  ptr_dqh->num_transferred_total = 0U;
+  ptr_dqh->num_transferring      = 0U;
+
+  USBD_HW_EndpointTransfer(ep_addr);    // Start transfer
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          uint32_t USBD_EndpointTransferGetResult (uint8_t ep_addr)
+  \brief       Get result of USB Endpoint transfer.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \return      number of successfully transferred data bytes
+*/
+static uint32_t USBD_EndpointTransferGetResult (uint8_t ep_addr) {
+
+  if (EP_NUM(ep_addr) > USBD_MAX_ENDPOINT_NUM) { return 0U; }
+
+  return (dQH[EP_IDX(ep_addr)].num_transferred_total);
+}
+
+/**
+  \fn          int32_t USBD_EndpointTransferAbort (uint8_t ep_addr)
+  \brief       Abort current USB Endpoint transfer.
+  \param[in]   ep_addr  Endpoint Address
+                - ep_addr.0..3: Address
+                - ep_addr.7:    Direction
+  \return      \ref execution_status
+*/
+static int32_t USBD_EndpointTransferAbort (uint8_t ep_addr) {
+  dQH_t   *ptr_dqh;
+  uint32_t ep_msk;
+  uint8_t  ep_num, ep_sll;
+
+  ep_num = EP_NUM(ep_addr);
+  if (ep_num > USBD_MAX_ENDPOINT_NUM)           { return ARM_DRIVER_ERROR; }
+  if ((USB1_state & USBD_DRIVER_POWERED) == 0U) { return ARM_DRIVER_ERROR; }
+
+  ptr_dqh = &dQH[EP_IDX(ep_addr)];
+  ep_msk  =  EP_MSK(ep_addr);
+  ep_sll  =  EP_SLL(ep_addr);
+
+  USBD_HW_EndpointFlush(ep_addr);
+
+  LPC_USBx->ENDPTCOMPLETE = ep_msk;                     // Clear Completed Flag
+  ENDPTCTRL(ep_num)  |=  (USB_ENDPTCTRL_RXR << ep_sll); // Data toggle reset
+
+  ptr_dqh->dTD_token &= ~0xFFU;
+
+  ptr_dqh->ep_active  =  0U;
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          uint16_t USBD_GetFrameNumber (void)
+  \brief       Get current USB Frame Number.
+  \return      Frame Number
+*/
+static uint16_t USBD_GetFrameNumber (void) {
+
+  if ((USB1_state & USBD_DRIVER_POWERED) == 0U) { return 0U; }
+
+  return ((LPC_USBx->FRINDEX_D & USB_FRINDEX_D_FRINDEX13_3_MSK) >> USB_FRINDEX_D_FRINDEX13_3_POS);
+}
+
+/**
+  \fn          void USBD1_IRQ (void)
+  \brief       USB1 Device Interrupt Routine (IRQ).
+*/
+void USBD1_IRQ (void) {
+  dQH_t   *ptr_dqh;
+  uint32_t sts, cmpl;
+  uint16_t ep_mps, num_transferred;
+  uint8_t  ep_num, ep_addr;
+
+  sts  = LPC_USBx->USBSTS_D & LPC_USBx->USBINTR_D;      // Read active interrupts
+  cmpl = LPC_USBx->ENDPTCOMPLETE;                       // Read Endpoint completed status
+  LPC_USBx->USBSTS_D      = sts;                        // Clear interrupts
+  LPC_USBx->ENDPTCOMPLETE = cmpl;                       // Clear Endpoint completed status
+
+  if ((sts & USB_USBDSTS_D_URI) != 0U) {                // Reset interrupt
+    USBD_Reset();
+    SignalDeviceEvent(ARM_USBD_EVENT_RESET);
+  }
+
+  if ((sts & USB_USBDSTS_D_SLI) != 0U) {                // Suspend interrupt
+    SignalDeviceEvent(ARM_USBD_EVENT_SUSPEND);
+
+#if (RTE_USB1_IND0_PIN_EN)
+    LPC_USBx->PORTSC1_D &= ~USB_PORTSC1_D_PIC1_0(1);    // Clear indicator LED0
+#endif
+  }
+
+  if ((sts & USB_USBDSTS_D_PCI) != 0U) {                // Port change detect interrupt
+    if (((LPC_USBx->PORTSC1_D & USB_PORTSC1_D_PSPD_MSK) >> USB_PORTSC1_D_PSPD_POS) == 2U) {
+      usbd_state.speed = ARM_USB_SPEED_HIGH;
+      SignalDeviceEvent(ARM_USBD_EVENT_HIGH_SPEED);
+    } else {
+      usbd_state.speed = ARM_USB_SPEED_FULL;
+    }
+
+#if (RTE_USB1_IND0_PIN_EN)
+    LPC_USBx->PORTSC1_D |= USB_PORTSC1_D_PIC1_0(1);     // Set indicator LED0
+#endif
+    SignalDeviceEvent(ARM_USBD_EVENT_RESUME);
+  }
+
+  if ((sts & USB_USBDSTS_D_UI) != 0U) {                 // USB interrupt - completed transfer
+    if ((LPC_USBx->ENDPTSETUPSTAT) != 0U) {             // Setup Packet Received
+      USBD_HW_ReadSetupPacket();
+      setup_received = 1U;
+      SignalEndpointEvent(0, ARM_USBD_EVENT_SETUP);
+    }
+
+    if ((cmpl & USB_ENDPTCOMPLETE_ETCE_MSK) != 0U) {    // IN Data Sent
+      for (ep_num = 0U; ep_num <= USBD_MAX_ENDPOINT_NUM; ep_num++) {
+        if ((cmpl & USB_ENDPTCOMPLETE_ETCE_MSK) & (1U << (ep_num + USB_ENDPTCOMPLETE_ETCE_POS))) {
+          ep_addr =  ep_num | ARM_USB_ENDPOINT_DIRECTION_MASK;
+          ptr_dqh = &dQH[EP_IDX(ep_addr)];
+
+          ptr_dqh->num_transferred_total += ptr_dqh->num_transferring;
+
+          // Check if all required IN data was sent
+          if (ptr_dqh->num == ptr_dqh->num_transferred_total) {
+            ptr_dqh->ep_active = 0U;                            // Clear Endpoint busy flag
+            SignalEndpointEvent(ep_addr, ARM_USBD_EVENT_IN);    // Send IN event
+          } else if (ptr_dqh->ep_active != 0U) {
+            USBD_HW_EndpointTransfer (ep_addr);                 // If this was not last transfer, start next
+          }
+        }
+      }
+    }
+
+    if ((cmpl & USB_ENDPTCOMPLETE_ERCE_MSK) != 0U) {    // OUT Data Received
+      for (ep_num = 0U; ep_num <= USBD_MAX_ENDPOINT_NUM; ep_num++) {
+        if ((cmpl & USB_ENDPTCOMPLETE_ERCE_MSK) & (1 << ep_num)) {
+          ep_addr =  ep_num;
+          ptr_dqh = &dQH[EP_IDX(ep_addr)];
+          ep_mps  = (ptr_dqh->cap & USB_EPQH_CAP_MAX_PACKET_LEN_MSK) >> USB_EPQH_CAP_MAX_PACKET_LEN_POS;
+
+          num_transferred = ptr_dqh->num_transferring - 
+                           ((ptr_dqh->dTD_token & USB_bTD_TOKEN_TOTAL_BYTES_MSK) >> USB_bTD_TOKEN_TOTAL_BYTES_POS);
+          ptr_dqh->num_transferred_total += num_transferred;
+
+          // Check if all OUT data was received:
+          //  - data terminated with ZLP or short packet or
+          //  - all required data received
+          if (((num_transferred % ep_mps) != 0U) || (ptr_dqh->num == ptr_dqh->num_transferred_total)) {
+            ptr_dqh->ep_active = 0U;                            // Clear Endpoint busy flag
+            SignalEndpointEvent(ep_addr, ARM_USBD_EVENT_OUT);   // Send OUT event
+          } else if (ptr_dqh->ep_active != 0U) {
+            USBD_HW_EndpointTransfer (ep_addr);                 // If this was not last transfer, start next
+          }
+        }
+      }
+    }
+  }
+}
+
+ARM_DRIVER_USBD Driver_USBD1 = {
+  USBD_GetVersion,
+  USBD_GetCapabilities,
+  USBD_Initialize,
+  USBD_Uninitialize,
+  USBD_PowerControl,
+  USBD_DeviceConnect,
+  USBD_DeviceDisconnect,
+  USBD_DeviceGetState,
+  USBD_DeviceRemoteWakeup,
+  USBD_DeviceSetAddress,
+  USBD_ReadSetupPacket,
+  USBD_EndpointConfigure,
+  USBD_EndpointUnconfigure,
+  USBD_EndpointStall,
+  USBD_EndpointTransfer,
+  USBD_EndpointTransferGetResult,
+  USBD_EndpointTransferAbort,
+  USBD_GetFrameNumber
+};

CMSIS/Pack/Example/CMSIS_Driver/USBH0_LPC18xx.c

@@ -0,0 +1,212 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        02. March 2016
+ * $Revision:    V2.4
+ *
+ * Driver:       Driver_USBH0_HCI
+ * Configured:   via RTE_Device.h configuration file
+ * Project:      USB Host 0 HCI Controller (EHCI) Driver for NXP LPC18xx
+ * --------------------------------------------------------------------------
+ * Use the following configuration settings in the middleware component
+ * to connect to this driver.
+ *
+ *   Configuration Setting                  Value
+ *   ---------------------                  -----
+ *   Connect to hardware via Driver_USBH# = 0
+ *   USB Host controller interface        = EHCI
+ * -------------------------------------------------------------------------- */
+
+/* History:
+ *  Version 2.4
+ *    Corrected PowerControl function for conditional Power full (driver must be initialized)
+ *  Version 2.3
+ *    PowerControl for Power OFF and Uninitialize functions made unconditional
+ *  Version 2.2
+ *    Updated in accordance with USB Device Driver
+ *  Version 2.1
+ *    Moved register initialization and uninitialization to PowerControl
+ *    function and removed from Initialize/Uninitialize functions
+ *    Pin configuration moved to USB_LPC18xx_USB0.c
+ *  Version 2.0
+ *    Initial release for USB Host EHCI Driver API v2.0
+ *  Version 1.0
+ *    Initial release
+ */
+
+
+#include "Driver_USBH.h"
+
+#include "LPC18xx.h"
+#include "USB_LPC18xx.h"
+
+#include "RTE_Device.h"
+#include "RTE_Components.h"
+
+#if      (RTE_USB_USB0 == 0)
+#error   "USB0 is not enabled in the RTE_Device.h!"
+#endif
+
+extern uint8_t USB0_role;
+extern uint8_t USB0_state;
+
+extern void USB0_PinsConfigure   (void);
+extern void USB0_PinsUnconfigure (void);
+
+
+// USBH EHCI Driver ************************************************************
+
+#define ARM_USBH_EHCI_DRIVER_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,4)
+
+// Driver Version
+static const ARM_DRIVER_VERSION usbh_ehci_driver_version = { ARM_USBH_API_VERSION, ARM_USBH_EHCI_DRIVER_VERSION };
+
+// Driver Capabilities
+static const ARM_USBH_HCI_CAPABILITIES usbh_ehci_driver_capabilities = {
+  0x0001U       // Root HUB available Ports Mask
+};
+
+static ARM_USBH_HCI_Interrupt_t EHCI_IRQ;
+
+// USBH EHCI Driver functions
+
+/**
+  \fn          ARM_DRIVER_VERSION USBH_HCI_GetVersion (void)
+  \brief       Get USB Host HCI (OHCI/EHCI) driver version.
+  \return      \ref ARM_DRIVER_VERSION
+*/
+static ARM_DRIVER_VERSION USBH_HCI_GetVersion (void) { return usbh_ehci_driver_version; }
+
+/**
+  \fn          ARM_USBH_HCI_CAPABILITIES USBH_HCI_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_USBH_HCI_CAPABILITIES
+*/
+static ARM_USBH_HCI_CAPABILITIES USBH_HCI_GetCapabilities (void) { return usbh_ehci_driver_capabilities; }
+
+/**
+  \fn          int32_t USBH_HCI_Initialize (ARM_USBH_HCI_Interrupt_t *cb_interrupt)
+  \brief       Initialize USB Host HCI (OHCI/EHCI) Interface.
+  \param[in]   cb_interrupt Pointer to Interrupt Handler Routine
+  \return      \ref execution_status
+*/
+static int32_t USBH_HCI_Initialize (ARM_USBH_HCI_Interrupt_t cb_interrupt) {
+
+  if ((USB0_state & USBH_DRIVER_INITIALIZED) != 0U) { return ARM_DRIVER_OK; }
+
+  EHCI_IRQ = cb_interrupt;
+
+  USB0_role   =  ARM_USB_ROLE_HOST;
+  USB0_PinsConfigure ();
+
+  USB0_state  =  USBH_DRIVER_INITIALIZED;
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t USBH_HCI_Uninitialize (void)
+  \brief       De-initialize USB Host HCI (OHCI/EHCI) Interface.
+  \return      \ref execution_status
+*/
+static int32_t USBH_HCI_Uninitialize (void) {
+
+  USB0_PinsUnconfigure ();
+  USB0_role   =  ARM_USB_ROLE_NONE;
+  USB0_state &= ~USBH_DRIVER_INITIALIZED;
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t USBH_HCI_PowerControl (ARM_POWER_STATE state)
+  \brief       Control USB Host HCI (OHCI/EHCI) Interface Power.
+  \param[in]   state Power state
+  \return      \ref execution_status
+*/
+static int32_t USBH_HCI_PowerControl (ARM_POWER_STATE state) {
+
+  switch (state) {
+    case ARM_POWER_OFF:
+      NVIC_DisableIRQ      (USB0_IRQn);                 // Disable interrupt
+      NVIC_ClearPendingIRQ (USB0_IRQn);                 // Clear pending interrupt
+      USB0_state &= ~USBH_DRIVER_POWERED;               // Clear powered flag
+      if ((LPC_CGU->BASE_USB0_CLK & 1U) == 0U) {
+        LPC_CREG->CREG0 |=  (1U << 5);                  // Disable USB0 PHY
+        LPC_CCU1->CLK_USB0_CFG    &= ~1U;               // Disable USB0 Base Clock
+        while (LPC_CCU1->CLK_USB0_STAT    & 1U);
+        LPC_CCU1->CLK_M3_USB0_CFG &= ~1U;               // Disable USB0 Register Interface Clock
+        while (LPC_CCU1->CLK_M3_USB0_STAT & 1U);
+        LPC_CGU->BASE_USB0_CLK     =  1U;               // Disable Base Clock
+      }
+      break;
+
+    case ARM_POWER_FULL:
+      if ((USB0_state & USBH_DRIVER_INITIALIZED) == 0U) { return ARM_DRIVER_ERROR; }
+      if ((USB0_state & USBH_DRIVER_POWERED)     != 0U) { return ARM_DRIVER_OK; }
+
+      LPC_CGU->BASE_USB0_CLK     = (0x01U << 11) |      // Auto-block Enable
+                                   (0x07U << 24) ;      // Clock source: PLL0USB
+      LPC_CCU1->CLK_M3_USB0_CFG |=  1U;                 // Enable USB0 Register Interface Clock
+      while (!(LPC_CCU1->CLK_M3_USB0_STAT & 1U));
+      LPC_CCU1->CLK_USB0_CFG    |=  1U;                 // Enable USB0 Base Clock
+      while (!(LPC_CCU1->CLK_USB0_STAT    & 1U));
+      LPC_CREG->CREG0 &= ~(1U << 5);                    // Enable USB0 PHY
+
+      USB0_state |=  USBH_DRIVER_POWERED;               // Set powered flag
+      NVIC_EnableIRQ   (USB0_IRQn);                     // Enable interrupt
+      break;
+
+    default:
+      return ARM_DRIVER_ERROR_UNSUPPORTED;
+  }
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t USBH_HCI_PortVbusOnOff (uint8_t port, bool vbus)
+  \brief       USB Host HCI (OHCI/EHCI) Root HUB Port VBUS on/off.
+  \param[in]   port  Root HUB Port Number
+  \param[in]   vbus
+                - \b false VBUS off
+                - \b true  VBUS on
+  \return      \ref execution_status
+*/
+static int32_t USBH_HCI_PortVbusOnOff (uint8_t port, bool power) {
+  // No GPIO pins used for VBUS control it is controlled by EHCI Controller
+
+  if (((1U << port) & usbh_ehci_driver_capabilities.port_mask) == 0U) { return ARM_DRIVER_ERROR; }
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          void USBH0_IRQ (void)
+  \brief       USB0 Host Interrupt Routine (IRQ).
+*/
+void USBH0_IRQ (void) {
+  EHCI_IRQ();
+}
+
+ARM_DRIVER_USBH_HCI Driver_USBH0_HCI = {
+  USBH_HCI_GetVersion,
+  USBH_HCI_GetCapabilities,
+  USBH_HCI_Initialize,
+  USBH_HCI_Uninitialize,
+  USBH_HCI_PowerControl,
+  USBH_HCI_PortVbusOnOff
+};

CMSIS/Pack/Example/CMSIS_Driver/USBH1_LPC18xx.c

@@ -0,0 +1,233 @@
+/* -------------------------------------------------------------------------- /*
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        02. March 2016
+ * $Revision:    V2.4
+ *
+ * Driver:       Driver_USBH1_HCI
+ * Configured:   via RTE_Device.h configuration file
+ * Project:      USB Host 1 HCI Controller (EHCI) Driver for NXP LPC18xx
+ * --------------------------------------------------------------------------
+ * Use the following configuration settings in the middleware component
+ * to connect to this driver.
+ *
+ *   Configuration Setting                  Value
+ *   ---------------------                  -----
+ *   Connect to hardware via Driver_USBH# = 1
+ *   USB Host controller interface        = EHCI
+ * -------------------------------------------------------------------------- */
+
+/* History:
+ *  Version 2.4
+ *    Corrected PowerControl function for conditional Power full (driver must be initialized)
+ *  Version 2.3
+ *    PowerControl for Power OFF and Uninitialize functions made unconditional
+ *  Version 2.2
+ *    Updated in accordance with USB Device Driver
+ *  Version 2.1
+ *    Moved register initialization and uninitialization to PowerControl
+ *    function and removed from Initialize/Uninitialize functions
+ *    Pin configuration moved to USB_LPC18xx_USB0.c
+ *  Version 2.0
+ *    Initial release for USB Host EHCI Driver API v2.0
+ *  Version 1.0
+ *    Initial release
+ */
+
+
+#include "Driver_USBH.h"
+
+#include "LPC18xx.h"
+#include "SCU_LPC18xx.h"
+#include "USB_LPC18xx.h"
+
+#include "RTE_Device.h"
+#include "RTE_Components.h"
+
+#if      (RTE_USB_USB1 == 0)
+#error   "USB1 is not enabled in the RTE_Device.h!"
+#endif
+#if      (RTE_USB_USB1_FS_PHY_EN && RTE_USB_USB1_HS_PHY_EN)
+#error   "Both full-speed and high-speed PHY can not be selected at the same time!"
+#endif
+
+extern uint8_t USB1_role;
+extern uint8_t USB1_state;
+
+extern void USB1_PinsConfigure   (void);
+extern void USB1_PinsUnconfigure (void);
+
+
+// USBH EHCI Driver ************************************************************
+
+#define ARM_USBH_EHCI_DRIVER_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,4)
+
+// Driver Version
+static const ARM_DRIVER_VERSION usbh_ehci_driver_version = { ARM_USBH_API_VERSION, ARM_USBH_EHCI_DRIVER_VERSION };
+
+// Driver Capabilities
+static const ARM_USBH_HCI_CAPABILITIES usbh_ehci_driver_capabilities = {
+  0x0001U       // Root HUB available Ports Mask
+};
+
+static ARM_USBH_HCI_Interrupt_t EHCI_IRQ;
+
+// USBH EHCI Driver functions
+
+/**
+  \fn          ARM_DRIVER_VERSION USBH_HCI_GetVersion (void)
+  \brief       Get USB Host HCI (OHCI/EHCI) driver version.
+  \return      \ref ARM_DRIVER_VERSION
+*/
+static ARM_DRIVER_VERSION USBH_HCI_GetVersion (void) { return usbh_ehci_driver_version; }
+
+/**
+  \fn          ARM_USBH_HCI_CAPABILITIES USBH_HCI_GetCapabilities (void)
+  \brief       Get driver capabilities.
+  \return      \ref ARM_USBH_HCI_CAPABILITIES
+*/
+static ARM_USBH_HCI_CAPABILITIES USBH_HCI_GetCapabilities (void) { return usbh_ehci_driver_capabilities; }
+
+/**
+  \fn          int32_t USBH_HCI_Initialize (ARM_USBH_HCI_Interrupt_t *cb_interrupt)
+  \brief       Initialize USB Host HCI (OHCI/EHCI) Interface.
+  \param[in]   cb_interrupt Pointer to Interrupt Handler Routine
+  \return      \ref execution_status
+*/
+static int32_t USBH_HCI_Initialize (ARM_USBH_HCI_Interrupt_t cb_interrupt) {
+
+  if ((USB1_state & USBH_DRIVER_INITIALIZED) != 0U) { return ARM_DRIVER_OK; }
+
+  EHCI_IRQ = cb_interrupt;
+
+  USB1_role   =  ARM_USB_ROLE_HOST;
+
+  USB1_PinsConfigure ();
+
+  USB1_state  =  USBH_DRIVER_INITIALIZED;
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t USBH_HCI_Uninitialize (void)
+  \brief       De-initialize USB Host HCI (OHCI/EHCI) Interface.
+  \return      \ref execution_status
+*/
+static int32_t USBH_HCI_Uninitialize (void) {
+
+  USB1_PinsUnconfigure ();
+  USB1_role   =  ARM_USB_ROLE_NONE;
+  USB1_state &= ~USBH_DRIVER_INITIALIZED;
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t USBH_HCI_PowerControl (ARM_POWER_STATE state)
+  \brief       Control USB Host HCI (OHCI/EHCI) Interface Power.
+  \param[in]   state Power state
+  \return      \ref execution_status
+*/
+static int32_t USBH_HCI_PowerControl (ARM_POWER_STATE state) {
+
+  switch (state) {
+    case ARM_POWER_OFF:
+      NVIC_DisableIRQ      (USB1_IRQn);                 // Disable interrupt
+      NVIC_ClearPendingIRQ (USB1_IRQn);                 // Clear pending interrupt
+      USB1_state &= ~USBH_DRIVER_POWERED;               // Clear powered flag
+#if (!RTE_USB_USB1_HS_PHY_EN)
+      SCU_USB1_PinConfigure (SCU_USB1_PIN_CFG_ESEA);    // Reset SCU Register
+#endif
+    
+      if ((LPC_CGU->BASE_USB1_CLK & 1U) == 0U) {
+        LPC_CCU1->CLK_USB1_CFG    &= ~1U;               // Disable USB1 Base Clock
+        while (LPC_CCU1->CLK_USB1_STAT    & 1U);
+        LPC_CCU1->CLK_M3_USB1_CFG &= ~1U;               // Disable USB1 Register Interface Clock
+        while (LPC_CCU1->CLK_M3_USB1_STAT & 1U);
+        LPC_CGU->BASE_USB1_CLK     =  1U;               // Disable Base Clock
+      }
+      break;
+
+    case ARM_POWER_FULL:
+      if ((USB1_state & USBH_DRIVER_INITIALIZED) == 0U) { return ARM_DRIVER_ERROR; }
+      if ((USB1_state & USBH_DRIVER_POWERED)     != 0U) { return ARM_DRIVER_OK; }
+
+      LPC_CGU->BASE_USB1_CLK     = (0x01U << 11) |      // Auto-block Enable
+                                   (0x0CU << 24) ;      // Clock source: IDIVA
+      LPC_CCU1->CLK_M3_USB1_CFG |=  1U;                 // Enable USB1 Register Interface Clock
+      while (!(LPC_CCU1->CLK_M3_USB1_STAT & 1U));
+      LPC_CCU1->CLK_USB1_CFG    |=  1U;                 // Enable USB1 Base Clock
+      while (!(LPC_CCU1->CLK_USB1_STAT    & 1U));
+
+      // Clear Transceiver Selection
+      LPC_USB1->PORTSC1_H &= ~(USB_PORTSC1_H_PTS_MSK | USB_PORTSC1_H_PFSC | USB_PORTSC1_H_PHCD);
+#if  (RTE_USB_USB1_HS_PHY_EN)
+      // ULPI Selected
+      LPC_USB1->PORTSC1_H |=   USB_PORTSC1_H_PTS(2U);   // Activate ULPI
+#else
+      // Serial/1.1 PHY selected and Full-speed forced
+      LPC_USB1->PORTSC1_H |=   USB_PORTSC1_H_PTS(3UL);
+      SCU_USB1_PinConfigure (SCU_USB1_PIN_CFG_AIM  |
+                             SCU_USB1_PIN_CFG_ESEA |
+                             SCU_USB1_PIN_CFG_EPD  |
+                             SCU_USB1_PIN_CFG_EPWR);
+#endif
+
+      USB1_state |=  USBH_DRIVER_POWERED;               // Set powered flag
+      NVIC_EnableIRQ   (USB1_IRQn);                     // Enable interrupt
+      break;
+
+    default:
+      return ARM_DRIVER_ERROR_UNSUPPORTED;
+  }
+
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          int32_t USBH_HCI_PortVbusOnOff (uint8_t port, bool vbus)
+  \brief       USB Host HCI (OHCI/EHCI) Root HUB Port VBUS on/off.
+  \param[in]   port  Root HUB Port Number
+  \param[in]   vbus
+                - \b false VBUS off
+                - \b true  VBUS on
+  \return      \ref execution_status
+*/
+static int32_t USBH_HCI_PortVbusOnOff (uint8_t port, bool power) {
+  // No GPIO pins used for VBUS control it is controlled by EHCI Controller
+
+  if (((1U << port) & usbh_ehci_driver_capabilities.port_mask) == 0U) { return ARM_DRIVER_ERROR; }
+  return ARM_DRIVER_OK;
+}
+
+/**
+  \fn          void USBH1_IRQ (void)
+  \brief       USB1 Host Interrupt Routine (IRQ).
+*/
+void USBH1_IRQ (void) {
+  EHCI_IRQ();
+}
+
+ARM_DRIVER_USBH_HCI Driver_USBH1_HCI = {
+  USBH_HCI_GetVersion,
+  USBH_HCI_GetCapabilities,
+  USBH_HCI_Initialize,
+  USBH_HCI_Uninitialize,
+  USBH_HCI_PowerControl,
+  USBH_HCI_PortVbusOnOff
+};

CMSIS/Pack/Example/CMSIS_Driver/USB_LPC18xx.h

@@ -0,0 +1,333 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * $Date:        02. March 2016
+ * $Revision:    V2.1
+ *
+ * Project:      USB Driver Definitions for NXP LPC18xx
+ * -------------------------------------------------------------------------- */
+
+#ifndef __USB_LPC18XX_H
+#define __USB_LPC18XX_H
+
+#include <stdint.h>
+
+#ifndef USB_ENDPT_MSK
+#define USB_ENDPT_MSK                          (0x3FU)
+#endif
+
+// USB Device Command Register
+#define USB_USBCMD_D_RS                        (1U           )
+#define USB_USBCMD_D_RST                       (1U     <<  1U)
+#define USB_USBCMD_D_SUTW                      (1U     << 13U)
+#define USB_USBCMD_D_ATDTW                     (1U     << 14U)
+#define USB_USBCMD_D_ITC_POS                   (          16U)
+#define USB_USBCMD_D_ITC_MSK                   (0xFFU  << USB_USBCMD_D_ITC_POS)
+#define USB_USBCMD_D_ITC(n)                    (((n)   << USB_USBCMD_D_ITC_POS) & USB_USBCMD_D_ITC_MSK)
+
+// USB Host Command Register
+#define USB_USBCMD_H_RS                        (1U           )
+#define USB_USBCMD_H_RST                       (1U     <<  1U)
+#define USB_USBCMD_H_FS0                       (1U     <<  2U)
+#define USB_USBCMD_H_FS1                       (1U     <<  3U)
+#define USB_USBCMD_H_PSE                       (1U     <<  4U)
+#define USB_USBCMD_H_ASE                       (1U     <<  5U)
+#define USB_USBCMD_H_IAA                       (1U     <<  6U)
+#define USB_USBCMD_H_ASP1_0_POS                (           8U)
+#define USB_USBCMD_H_ASP1_0_MSK                (3U     <<  USB_USBCMD_H_ASP1_0_POS)
+#define USB_USBCMD_H_ASPE                      (1U     << 11U)
+#define USB_USBCMD_H_FS2                       (1U     << 15U)
+#define USB_USBCMD_H_ITC_POS                   (          16U)
+#define USB_USBCMD_H_ITC_MSK                   (0xFFU  << USB_USBCMD_H_ITC_POS)
+#define USB_USBCMD_H_ITC(n)                    (((n)   << USB_USBCMD_H_ITC_POS) & USB_USBCMD_H_ITC_MSK)
+
+// USB Device Status Register
+#define USB_USBDSTS_D_UI                       (1U           )
+#define USB_USBDSTS_D_UEI                      (1U     <<  1U)
+#define USB_USBDSTS_D_PCI                      (1U     <<  2U)
+#define USB_USBDSTS_D_URI                      (1U     <<  6U)
+#define USB_USBDSTS_D_SRI                      (1U     <<  7U)
+#define USB_USBDSTS_D_SLI                      (1U     <<  8U)
+#define USB_USBDSTS_D_NAKI                     (1U     << 16U)
+
+// USB Host Status Register
+#define USB_USBDSTS_H_UI                       (1U           )
+#define USB_USBDSTS_H_UEI                      (1U     <<  1U)
+#define USB_USBDSTS_H_PCI                      (1U     <<  2U)
+#define USB_USBDSTS_H_FRI                      (1U     <<  3U)
+#define USB_USBDSTS_H_AAI                      (1U     <<  5U)
+#define USB_USBDSTS_H_SRI                      (1U     <<  7U)
+#define USB_USBDSTS_H_HCH                      (1U     << 12U)
+#define USB_USBDSTS_H_RCL                      (1U     << 13U)
+#define USB_USBDSTS_H_PS                       (1U     << 14U)
+#define USB_USBDSTS_H_AS                       (1U     << 15U)
+#define USB_USBDSTS_H_UAI                      (1U     << 18U)
+#define USB_USBDSTS_H_UPI                      (1U     << 19U)
+
+// USB Device Interrupt Register
+#define USB_USBINTR_D_UE                       (1U           )
+#define USB_USBINTR_D_UEE                      (1U     <<  1U)
+#define USB_USBINTR_D_PCE                      (1U     <<  2U)
+#define USB_USBINTR_D_URE                      (1U     <<  6U)
+#define USB_USBINTR_D_SRE                      (1U     <<  7U)
+#define USB_USBINTR_D_SLE                      (1U     <<  8U)
+#define USB_USBINTR_D_NAKE                     (1U     << 16U)
+
+// USB Host Interrupt Register
+#define USB_USBINTR_H_UE                       (1U           )
+#define USB_USBINTR_H_UEE                      (1U     <<  1U)
+#define USB_USBINTR_H_PCE                      (1U     <<  2U)
+#define USB_USBINTR_H_FRE                      (1U     <<  3U)
+#define USB_USBINTR_H_AAE                      (1U     <<  5U)
+#define USB_USBINTR_H_SRE                      (1U     <<  7U)
+#define USB_USBINTR_H_UAIE                     (1U     << 18U)
+#define USB_USBINTR_H_UPIA                     (1U     << 19U)
+
+// USB Device Frame Index Register
+#define USB_FRINDEX_D_FRINDEX2_0_POS           (          0U)
+#define USB_FRINDEX_D_FRINDEX2_0_MSK           (7U          )
+#define USB_FRINDEX_D_FRINDEX13_3_POS          (          3U)
+#define USB_FRINDEX_D_FRINDEX13_3_MSK          (0x7FFU << USB_FRINDEX_D_FRINDEX13_3_POS)
+
+// USB Host Frame Index Register
+#define USB_FRINDEX_H_FRINDEX2_0_POS           (          0U)
+#define USB_FRINDEX_H_FRINDEX2_0_MSK           (7U          )
+#define USB_FRINDEX_H_FRINDEX12_3_POS          (          3U)
+#define USB_FRINDEX_H_FRINDEX12_3_MSK          (0x3FFU << USB_FRINDEX_H_FRINDEX12_3_POS)
+
+// USB Device Address Register
+#define USB_DEVICEADDR_USBADRA                 (1U     << 24U)
+#define USB_DEVICEADDR_USBADR_POS              (          25U)
+#define USB_DEVICEADDR_USBADR_MSK              (0x7FUL << USB_DEVICEADDR_USBADR_POS)
+
+// USB Endpoint List Address Register
+#define USB_ENDPOINTLISTADDR_EPBASE31_11_POS   (          11U)
+#define USB_ENDPOINTLISTADDR_EPBASE31_11_MSK   (0x1FFFFFUL << USB_ENDPOINTLISTADDR_EPBASE31_11_POS)
+
+// USB Burst Size Register
+#define USB_BURSTSIZE_RXPBURST_POS             (           0U)
+#define USB_BURSTSIZE_RXPBURST_MSK             (0xFFU        )
+#define USB_BURSTSIZE_TXPBURST_POS             (           8U)
+#define USB_BURSTSIZE_TXPBURST_MSK             (0xFFU  <<  USB_BURSTSIZE_TXPBURST_POS)
+
+// USB ULPI Viewport register (USB1 only)
+#define USB_ULPIVIEWPORT_ULPIDATWR_POS         (           0U)
+#define USB_ULPIVIEWPORT_ULPIDATRW_MSK         (0xFFU        )
+#define USB_ULPIVIEWPORT_ULPIDATRD_POS         (           8U)
+#define USB_ULPIVIEWPORT_ULPIDATRD_MSK         (0xFFU  <<  USB_ULPIVIEWPORT_ULPIDATRD_POS)
+#define USB_ULPIVIEWPORT_ULPIADDR_POS          (          16U)
+#define USB_ULPIVIEWPORT_ULPIADDR_MSK          (0xFFU  << USB_ULPIVIEWPORT_ULPIADDR_POS)
+#define USB_ULPIVIEWPORT_ULPIPORT_POS          (          24U)
+#define USB_ULPIVIEWPORT_ULPIPORT_MSK          (7U     << USB_ULPIVIEWPORT_ULPIPORT_POS)
+#define USB_ULPIVIEWPORT_ULPISS                (1U     << 27U)
+#define USB_ULPIVIEWPORT_ULPIRW                (1U     << 29U)
+#define USB_ULPIVIEWPORT_ULPIRUN               (1U     << 30U)
+#define USB_ULPIVIEWPORT_ULPIWU                (1UL    << 31U)
+
+// USB BInterval Register
+#define USB_BINTERVAL_BINT_POS                 (           0U)
+#define USB_BINTERVAL_BINT_MSK                 (0x0FU  <<  USB_BINTERVAL_BINT_POS)
+
+// USB Endpoint NAK Register
+#define USB_ENDPTNAK_EPRN_POS                  (           0U)
+#define USB_ENDPTNAK_EPRN_MSK                  (USB_ENDPT_MSK)
+#define USB_ENDPTNAK_EPTN_POS                  (          16U)
+#define USB_ENDPTNAK_EPTN_MSK                  (USB_ENDPT_MSK << USB_ENDPTNAK_EPTN_POS)
+
+// USB Endpoint NAK Enable Register
+#define USB_ENDPTNAKEN_EPRNE_POS               (           0U)
+#define USB_ENDPTNAKEN_EPRNE_MSK               (USB_ENDPT_MSK)
+#define USB_ENDPTNAKEN_EPTNE_POS               (          16U)
+#define USB_ENDPTNAKEN_EPTNE_MSK               (USB_ENDPT_MSK << USB_ENDPTNAKEN_EPTNE_POS)
+
+// USB Device Port Status and Control Register
+#define USB_PORTSC1_D_CCS                      (1U           )
+#define USB_PORTSC1_D_PE                       (1U     <<  2U)
+#define USB_PORTSC1_D_PEC                      (1U     <<  3U)
+#define USB_PORTSC1_D_FPR                      (1U     <<  6U)
+#define USB_PORTSC1_D_SUSP                     (1U     <<  7U)
+#define USB_PORTSC1_D_PR                       (1U     <<  8U)
+#define USB_PORTSC1_D_HSP                      (1U     <<  9U)
+#define USB_PORTSC1_D_PIC1_0_POS               (          14U)
+#define USB_PORTSC1_D_PIC1_0_MSK               (3U     << USB_PORTSC1_D_PIC1_0_POS)
+#define USB_PORTSC1_D_PIC1_0(n)                (((n)   << USB_PORTSC1_D_PIC1_0_POS) & USB_PORTSC1_D_PIC1_0_MSK)
+#define USB_PORTSC1_D_PTC3_0_POS               (          16U)
+#define USB_PORTSC1_D_PTC3_0_MSK               (0x0FU  << USB_PORTSC1_D_PTC3_0_POS)
+#define USB_PORTSC1_D_PHCD                     (1U     << 23U)
+#define USB_PORTSC1_D_PFSC                     (1U     << 24U)
+#define USB_PORTSC1_D_PSPD_POS                 (          26U)
+#define USB_PORTSC1_D_PSPD_MSK                 (3U     << USB_PORTSC1_D_PSPD_POS)
+#define USB_PORTSC1_D_PTS_POS                  (          30U)
+#define USB_PORTSC1_D_PTS_MSK                  (3UL    << USB_PORTSC1_D_PTS_POS)
+#define USB_PORTSC1_D_PTS(n)                   (((n)   << USB_PORTSC1_D_PTS_POS) & USB_PORTSC1_D_PTS_MSK)
+
+// USB Host Port Status and Control Register
+#define USB_PORTSC1_H_CCS                      (1U           )
+#define USB_PORTSC1_H_CSC                      (1U     <<  1U)
+#define USB_PORTSC1_H_PE                       (1U     <<  2U)
+#define USB_PORTSC1_H_PEC                      (1U     <<  3U)
+#define USB_PORTSC1_H_OCA                      (1U     <<  4U)
+#define USB_PORTSC1_H_OCC                      (1U     <<  5U)
+#define USB_PORTSC1_H_FPR                      (1U     <<  6U)
+#define USB_PORTSC1_H_SUSP                     (1U     <<  7U)
+#define USB_PORTSC1_H_PR                       (1U     <<  8U)
+#define USB_PORTSC1_H_HSP                      (1U     <<  9U)
+#define USB_PORTSC1_H_LS_POS                   (          10U)
+#define USB_PORTSC1_H_LS_MSK                   (3U     << USB_PORTSC1_H_LS_POS)
+#define USB_PORTSC1_H_PP                       (1U     << 12U)
+#define USB_PORTSC1_H_PIC1_0_POS               (          14U)
+#define USB_PORTSC1_H_PIC1_0_MSK               (3U     << USB_PORTSC1_H_PIC1_0_POS)
+#define USB_PORTSC1_H_PIC1_0(n)                (((n)   << USB_PORTSC1_H_PIC1_0_POS) & USB_PORTSC1_H_PIC1_0_MSK)
+#define USB_PORTSC1_H_PTC3_0_POS               (          16U)
+#define USB_PORTSC1_H_PTC3_0_MSK               (0x0FU  << USB_PORTSC1_H_PTC3_0_POS)
+#define USB_PORTSC1_H_WKCN                     (1U     << 20U)
+#define USB_PORTSC1_H_WKDC                     (1U     << 21U)
+#define USB_PORTSC1_H_WKOC                     (1U     << 22U)
+#define USB_PORTSC1_H_PHCD                     (1U     << 23U)
+#define USB_PORTSC1_H_PFSC                     (1U     << 24U)
+#define USB_PORTSC1_H_PSPD_POS                 (          26U)
+#define USB_PORTSC1_H_PSPD_MSK                 (3U     << USB_PORTSC1_H_PSPD_POS)
+#define USB_PORTSC1_H_PTS_POS                  (          30U)
+#define USB_PORTSC1_H_PTS_MSK                  (3UL    << USB_PORTSC1_H_PTS_POS)
+#define USB_PORTSC1_H_PTS(n)                   (((n)   << USB_PORTSC1_H_PTS_POS) & USB_PORTSC1_H_PTS_MSK)
+
+// OTG Status and Control Register (USB0 only)
+#define USB_OTGSC_VD                           (1U           )
+#define USB_OTGSC_VC                           (1U     <<  1U)
+#define USB_OTGSC_HAAR                         (1U     <<  2U)
+#define USB_OTGSC_OT                           (1U     <<  3U)
+#define USB_OTGSC_DP                           (1U     <<  4U)
+#define USB_OTGSC_IDPU                         (1U     <<  5U)
+#define USB_OTGSC_HADP                         (1U     <<  6U)
+#define USB_OTGSC_HABA                         (1U     <<  7U)
+#define USB_OTGSC_ID                           (1U     <<  8U)
+#define USB_OTGSC_AVV                          (1U     <<  9U)
+#define USB_OTGSC_ASV                          (1U     << 10U)
+#define USB_OTGSC_BSV                          (1U     << 11U)
+#define USB_OTGSC_BSE                          (1U     << 12U)
+#define USB_OTGSC_MS1T                         (1U     << 13U)
+#define USB_OTGSC_DPS                          (1U     << 14U)
+#define USB_OTGSC_IDIS                         (1U     << 16U)
+#define USB_OTGSC_AVVIS                        (1U     << 17U)
+#define USB_OTGSC_ASVIS                        (1U     << 18U)
+#define USB_OTGSC_BSVIS                        (1U     << 19U)
+#define USB_OTGSC_BSEIS                        (1U     << 20U)
+#define USB_OTGSC_MS1S                         (1U     << 21U)
+#define USB_OTGSC_DPIS                         (1U     << 22U)
+#define USB_OTGSC_IDIE                         (1U     << 24U)
+#define USB_OTGSC_AVVIE                        (1U     << 25U)
+#define USB_OTGSC_ASVIE                        (1U     << 26U)
+#define USB_OTGSC_BSVIE                        (1U     << 27U)
+#define USB_OTGSC_BSEIE                        (1U     << 28U)
+#define USB_OTGSC_MS1E                         (1U     << 29U)
+#define USB_OTGSC_DPIE                         (1U     << 30U)
+
+// USB Device Mode Register
+#define USB_USBMODE_D_CM1_0_POS                (           0U)
+#define USB_USBMODE_D_CM1_0_MSK                (3U           )
+#define USB_USBMODE_D_CM1_0(n)                 ((n)    &   USB_USBMODE_D_CM1_0_MSK)
+#define USB_USBMODE_D_ES                       (1U     <<  2U)
+#define USB_USBMODE_D_SLOM                     (1U     <<  3U)
+#define USB_USBMODE_D_SDIS                     (1U     <<  4U)
+
+// USB Device Mode Register
+#define USB_USBMODE_H_CM1_0_POS                (           0U)
+#define USB_USBMODE_H_CM1_0_MSK                (3U           )
+#define USB_USBMODE_H_CM1_0(n)                 ((n)    &   USB_USBMODE_H_CM1_0_MSK)
+#define USB_USBMODE_H_ES                       (1U     <<  2U)
+#define USB_USBMODE_H_SDIS                     (1U     <<  4U)
+#define USB_USBMODE_H_VBPS                     (1U     <<  5U)
+
+// USB Endpoint Setup Status Register
+#define USB_ENDPTSETUPSTAT_POS                 (           0U)
+#define USB_ENDPTSETUPSTAT_MSK                 (USB_ENDPT_MSK << USB_ENDPTSETUPSTAT_POS)
+
+// USB Endpoint Prime Register
+#define USB_ENDPTRPRIME_PERB_POS               (           0U)
+#define USB_ENDPTRPRIME_PERB_MSK               (USB_ENDPT_MSK)
+#define USB_ENDPTRPRIME_PETB_POS               (          16U)
+#define USB_ENDPTRPRIME_PETB_MSK               (USB_ENDPT_MSK << USB_ENDPTRPRIME_PETB_POS)
+
+// USB Endpoint Flush Register
+#define USB_ENDPTFLUSH_FERB_POS                (           0U)
+#define USB_ENDPTFLUSH_FERB_MSK                (USB_ENDPT_MSK)
+#define USB_ENDPTFLUSH_FETB_POS                (          16U)
+#define USB_ENDPTFLUSH_FETB_MSK                (USB_ENDPT_MSK << USB_ENDPTFLUSH_FETB_POS)
+
+// USB Endpoint Status Register
+#define USB_ENDPTSTAT_ERBR_POS                 (           0U)
+#define USB_ENDPTSTAT_ERBR_MSK                 (USB_ENDPT_MSK)
+#define USB_ENDPTSTAT_ETBR_POS                 (          16U)
+#define USB_ENDPTSTAT_ETBR_MSK                 (USB_ENDPT_MSK << USB_ENDPTSTAT_ETBR_POS)
+
+// USB Endpoint Complete Register
+#define USB_ENDPTCOMPLETE_ERCE_POS             (           0U)
+#define USB_ENDPTCOMPLETE_ERCE_MSK             (USB_ENDPT_MSK)
+#define USB_ENDPTCOMPLETE_ETCE_POS             (          16U)
+#define USB_ENDPTCOMPLETE_ETCE_MSK             (USB_ENDPT_MSK << USB_ENDPTCOMPLETE_ETCE_POS)
+
+// USB Endpoint Control Register
+#define USB_ENDPTCTRL_RXS                      (1U           )
+#define USB_ENDPTCTRL_RXT_POS                  (           2U)
+#define USB_ENDPTCTRL_RXT_MSK                  (3U     <<  USB_ENDPTCTRL_RXT_POS)
+#define USB_ENDPTCTRL_RXT(n)                   (((n)   <<  USB_ENDPTCTRL_RXT_POS) & USB_ENDPTCTRL_RXT_MSK)
+#define USB_ENDPTCTRL_RXI                      (1U     <<  5U)
+#define USB_ENDPTCTRL_RXR                      (1U     <<  6U)
+#define USB_ENDPTCTRL_RXE                      (1U     <<  7U)
+#define USB_ENDPTCTRL_TXS                      (1U     << 16U)
+#define USB_ENDPTCTRL_TXT_POS                  (          18U)
+#define USB_ENDPTCTRL_TXT_MSK                  (3U     << USB_ENDPTCTRL_TXT_POS)
+#define USB_ENDPTCTRL_TXT(n)                   (((n)   << USB_ENDPTCTRL_TXT_POS) & USB_ENDPTCTRL_TXT_MSK)
+#define USB_ENDPTCTRL_TXI                      (1U     << 21U)
+#define USB_ENDPTCTRL_TXR                      (1U     << 22U)
+#define USB_ENDPTCTRL_TXE                      (1U     << 23U)
+
+// Endpoint Queue Head Capabilities and Characteristics
+#define USB_EPQH_CAP_IOS                       (1U     << 15U)
+#define USB_EPQH_CAP_MAX_PACKET_LEN_POS        (          16U)
+#define USB_EPQH_CAP_MAX_PACKET_LEN_MSK        (0x7FFU << USB_EPQH_CAP_MAX_PACKET_LEN_POS)
+#define USB_EPQH_CAP_MAX_PACKET_LEN(n)         (((n)   << USB_EPQH_CAP_MAX_PACKET_LEN_POS) & USB_EPQH_CAP_MAX_PACKET_LEN_MSK)
+#define USB_EPQH_CAP_ZLT                       (1U     << 29U)
+#define USB_EPQH_CAP_MULT_POS                  (          30U)
+#define USB_EPQH_CAP_MULT_MSK                  (3UL    << USB_EPQH_CAP_MULT_POS)
+
+// Transfer Descriptor Token
+#define USB_bTD_TOKEN_STATUS_POS               (           0U)
+#define USB_bTD_TOKEN_STATUS_MSK               (0xFFU        )
+#define USB_bTD_TOKEN_STATUS(n)                (n      &  USB_bTD_TOKEN_STATUS_MSK)
+#define USB_bTD_TOKEN_STATUS_TRAN_ERROR        (0x08U  &  USB_bTD_TOKEN_STATUS_MSK)
+#define USB_bTD_TOKEN_STATUS_BUFFER_ERROR      (0x20U  &  USB_bTD_TOKEN_STATUS_MSK)
+#define USB_bTD_TOKEN_STATUS_HALTED            (0x40U  &  USB_bTD_TOKEN_STATUS_MSK)
+#define USB_bTD_TOKEN_STATUS_ACTIVE            (0x80U  &  USB_bTD_TOKEN_STATUS_MSK)
+#define USB_bTD_TOKEN_MULTO_POS                (          10U)
+#define USB_bTD_TOKEN_MULTO_MSK                (3U     << USB_bTD_TOKEN_MULTO_POS)
+#define USB_bTD_TOKEN_MULTO(n)                 (((n)   << USB_bTD_TOKEN_MULTO_POS) & USB_bTD_TOKEN_MULTO_MSK)
+#define USB_bTD_TOKEN_IOC                      (1U     << 15U)
+#define USB_bTD_TOKEN_TOTAL_BYTES_POS          (          16U)
+#define USB_bTD_TOKEN_TOTAL_BYTES_MSK          (0x7FFFU<< USB_bTD_TOKEN_TOTAL_BYTES_POS)
+#define USB_bTD_TOKEN_TOTAL_BYTES(n)           (((n)   << USB_bTD_TOKEN_TOTAL_BYTES_POS) & USB_bTD_TOKEN_TOTAL_BYTES_MSK)
+
+// USB Driver State Flags
+// Device State Flags
+#define USBD_DRIVER_INITIALIZED                (1U           )
+#define USBD_DRIVER_POWERED                    (1U     <<  1U)
+
+// Host State Flags
+#define USBH_DRIVER_INITIALIZED                (1U     <<  4U)
+#define USBH_DRIVER_POWERED                    (1U     <<  5U)
+
+#endif /* __USB_LPC18XX_H */

CMSIS/Pack/Example/Debug/LPC18xx.dbgconf

@@ -0,0 +1,31 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <h> Debug Setup
+
+// <o> Vector Reset
+//   <0=> Processor Only
+//   <1=> Processor and Peripherals
+// <i> Select if to additionally reset peripherals after a Vector Reset
+VecResetWithPeriph = 1;
+
+// </h>
+
+// <h> TPIU Pin Routing (TRACECLK fixed on PF_4)
+// <i> Configure the TPIU pin routing as used on your target platform.
+// <o.1> TRACEDATA0
+//   <0=> Pin PF_5
+//   <1=> Pin P7_4
+// <o.2> TRACEDATA1
+//   <0=> Pin PF_6
+//   <1=> Pin P7_5
+// <o.3> TRACEDATA2
+//   <0=> Pin PF_7
+//   <1=> Pin P7_6
+// <o.4> TRACEDATA3
+//   <0=> Pin PF_8
+//   <1=> Pin P7_7
+RoutingTPIU = 0x00000000;
+
+// </h>
+
+// <<< end of configuration section >>>

CMSIS/Pack/Example/Device/Include/LPC18xx.h

@@ -0,0 +1,5 @@
+/**
+  ******************************************************************************
+    PLACEHOLDER for CMSIS-CORE Device Header File for the LPC1800 Series
+  ******************************************************************************  
+  */ 

CMSIS/Pack/Example/Device/Include/system_LPC18xx.h

@@ -0,0 +1,5 @@
+/**
+  ******************************************************************************
+    PLACEHOLDER for CMSIS-CORE System Header File for the LPC1800 Series
+  ******************************************************************************  
+  */ 

CMSIS/Pack/Example/Device/Source/ARM/startup_LPC18xx.s

@@ -0,0 +1,6 @@
+/**
+  ******************************************************************************
+    PLACEHOLDER for CMSIS-CORE Startup Device Assembler File 
+    for the LPC1800 Series for the ARM Compiler Toolchain
+  ******************************************************************************  
+  */ 

CMSIS/Pack/Example/Device/Source/GCC/startup_LPC18xx.S

@@ -0,0 +1,6 @@
+/**
+  ******************************************************************************
+    PLACEHOLDER for CMSIS-CORE Startup Device Assembler File 
+    for the LPC1800 Series for the GNU GCC Compiler Toolchain
+  ******************************************************************************  
+  */ 

CMSIS/Pack/Example/Device/Source/IAR/startup_LPC18xx.s

@@ -0,0 +1,6 @@
+/**
+  ******************************************************************************
+    PLACEHOLDER for CMSIS-CORE Startup Device Assembler File 
+    for the LPC1800 Series for the IAR Compiler Toolchain
+  ******************************************************************************  
+  */ 

CMSIS/Pack/Example/Device/Source/system_LPC18xx.c

@@ -0,0 +1,5 @@
+/**
+  ******************************************************************************
+    PLACEHOLDER for CMSIS-CORE System Device Source File for the LPC1800 Series
+  ******************************************************************************  
+  */ 

CMSIS/Pack/Example/Flash/FlashOS.h

@@ -0,0 +1,84 @@
+/* -----------------------------------------------------------------------------
+ * Copyright (c) 2014 ARM Ltd.
+ *
+ * This software is provided 'as-is', without any express or implied warranty. 
+ * In no event will the authors be held liable for any damages arising from 
+ * the use of this software. Permission is granted to anyone to use this 
+ * software for any purpose, including commercial applications, and to alter 
+ * it and redistribute it freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not 
+ *    claim that you wrote the original software. If you use this software in
+ *    a product, an acknowledgment in the product documentation would be 
+ *    appreciated but is not required. 
+ * 
+ * 2. Altered source versions must be plainly marked as such, and must not be 
+ *    misrepresented as being the original software. 
+ * 
+ * 3. This notice may not be removed or altered from any source distribution.
+ *   
+ *
+ * $Date:        14. Jan 2014
+ * $Revision:    V1.00
+ *  
+ * Project:      FlashOS Headerfile for Flash drivers
+ * --------------------------------------------------------------------------- */
+
+/* History:
+ *  Version 1.00
+ *    Initial release
+ */ 
+
+#define VERS       1           // Interface Version 1.01
+
+#define UNKNOWN    0           // Unknown
+#define ONCHIP     1           // On-chip Flash Memory
+#define EXT8BIT    2           // External Flash Device on 8-bit  Bus
+#define EXT16BIT   3           // External Flash Device on 16-bit Bus
+#define EXT32BIT   4           // External Flash Device on 32-bit Bus
+#define EXTSPI     5           // External Flash Device on SPI
+
+#define SECTOR_NUM 512         // Max Number of Sector Items
+#define PAGE_MAX   65536       // Max Page Size for Programming
+
+struct FlashSectors  {
+  unsigned long   szSector;    // Sector Size in Bytes
+  unsigned long AddrSector;    // Address of Sector
+};
+
+#define SECTOR_END 0xFFFFFFFF, 0xFFFFFFFF
+
+struct FlashDevice  {
+   unsigned short     Vers;    // Version Number and Architecture
+   char       DevName[128];    // Device Name and Description
+   unsigned short  DevType;    // Device Type: ONCHIP, EXT8BIT, EXT16BIT, ...
+   unsigned long    DevAdr;    // Default Device Start Address
+   unsigned long     szDev;    // Total Size of Device
+   unsigned long    szPage;    // Programming Page Size
+   unsigned long       Res;    // Reserved for future Extension
+   unsigned char  valEmpty;    // Content of Erased Memory
+
+   unsigned long    toProg;    // Time Out of Program Page Function
+   unsigned long   toErase;    // Time Out of Erase Sector Function
+
+   struct FlashSectors sectors[SECTOR_NUM];
+};
+
+#define FLASH_DRV_VERS (0x0100+VERS)   // Driver Version, do not modify!
+
+// Flash Programming Functions (Called by FlashOS)
+extern          int  Init        (unsigned long adr,   // Initialize Flash
+                                  unsigned long clk,
+                                  unsigned long fnc);
+extern          int  UnInit      (unsigned long fnc);  // De-initialize Flash
+extern          int  BlankCheck  (unsigned long adr,   // Blank Check
+                                  unsigned long sz,
+                                  unsigned char pat);
+extern          int  EraseChip   (void);               // Erase complete Device
+extern          int  EraseSector (unsigned long adr);  // Erase Sector Function
+extern          int  ProgramPage (unsigned long adr,   // Program Page Function
+                                  unsigned long sz,
+                                  unsigned char *buf);
+extern unsigned long Verify      (unsigned long adr,   // Verify Function
+                                  unsigned long sz,
+                                  unsigned char *buf);

CMSIS/Pack/Example/Flash/LPC18xx43xx_IAP/FlashDev.c

@@ -0,0 +1,152 @@
+/* -----------------------------------------------------------------------------
+ * Copyright (c) 2004 - 2014 ARM Ltd.
+ *
+ * This software is provided 'as-is', without any express or implied warranty. 
+ * In no event will the authors be held liable for any damages arising from 
+ * the use of this software. Permission is granted to anyone to use this 
+ * software for any purpose, including commercial applications, and to alter 
+ * it and redistribute it freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not 
+ *    claim that you wrote the original software. If you use this software in
+ *    a product, an acknowledgment in the product documentation would be 
+ *    appreciated but is not required. 
+ * 
+ * 2. Altered source versions must be plainly marked as such, and must not be 
+ *    misrepresented as being the original software. 
+ * 
+ * 3. This notice may not be removed or altered from any source distribution.
+ *   
+ *
+ * $Date:        30. May 2014
+ * $Revision:    V1.00
+ *  
+ * Project:      Flash Device Description for NXP LPC18xx/43xx Flash using IAP
+ * --------------------------------------------------------------------------- */
+
+#include "..\FlashOS.H"        // FlashOS Structures
+
+
+#ifdef LPC18xx43xx
+
+#ifdef FLASH_512_BA
+struct FlashDevice const FlashDevice  =  {
+   FLASH_DRV_VERS,             // Driver Version, do not modify!
+   "LPC18xx/43xx IAP 512kB Flash Bank A",  // Device Name
+   ONCHIP,                     // Device Type
+   0x1A000000,                 // Device Start Address
+   0x00080000,                 // Device Size (512kB)
+   1024,                       // Programming Page Size
+   0,                          // Reserved, must be 0
+   0xFF,                       // Initial Content of Erased Memory
+   5000,                       // Program Page Timeout 5000 mSec
+   5000,                       // Erase Sector Timeout 5000 mSec
+
+// Specify Size and Address of Sectors
+   0x002000, 0x000000,         // Sector Size  8kB (8 Sectors)
+   0x010000, 0x010000,         // Sector Size 64kB (7 Sectors)
+   SECTOR_END
+};
+#endif
+
+#ifdef FLASH_512_BB
+struct FlashDevice const FlashDevice  =  {
+   FLASH_DRV_VERS,             // Driver Version, do not modify!
+   "LPC18xx/43xx IAP 512kB Flash Bank B",  // Device Name
+   ONCHIP,                     // Device Type
+   0x1B000000,                 // Device Start Address
+   0x00080000,                 // Device Size (512kB)
+   1024,                       // Programming Page Size
+   0,                          // Reserved, must be 0
+   0xFF,                       // Initial Content of Erased Memory
+   5000,                       // Program Page Timeout 5000 mSec
+   5000,                       // Erase Sector Timeout 5000 mSec
+
+// Specify Size and Address of Sectors
+   0x002000, 0x000000,         // Sector Size  8kB (8 Sectors)
+   0x010000, 0x010000,         // Sector Size 64kB (7 Sectors)
+   SECTOR_END
+};
+#endif
+
+#ifdef FLASH_384_BA
+struct FlashDevice const FlashDevice  =  {
+   FLASH_DRV_VERS,             // Driver Version, do not modify!
+   "LPC18xx/43xx IAP 384kB Flash Bank A",  // Device Name
+   ONCHIP,                     // Device Type
+   0x1A000000,                 // Device Start Address
+   0x00060000,                 // Device Size (384kB)
+   1024,                       // Programming Page Size
+   0,                          // Reserved, must be 0
+   0xFF,                       // Initial Content of Erased Memory
+   5000,                       // Program Page Timeout 5000 mSec
+   5000,                       // Erase Sector Timeout 5000 mSec
+
+// Specify Size and Address of Sectors
+   0x002000, 0x000000,         // Sector Size  8kB (8 Sectors)
+   0x010000, 0x010000,         // Sector Size 64kB (5 Sectors)
+   SECTOR_END
+};
+#endif
+
+#ifdef FLASH_384_BB
+struct FlashDevice const FlashDevice  =  {
+   FLASH_DRV_VERS,             // Driver Version, do not modify!
+   "LPC18xx/43xx IAP 384kB Flash Bank B",  // Device Name
+   ONCHIP,                     // Device Type
+   0x1B000000,                 // Device Start Address
+   0x00060000,                 // Device Size (384kB)
+   1024,                       // Programming Page Size
+   0,                          // Reserved, must be 0
+   0xFF,                       // Initial Content of Erased Memory
+   5000,                       // Program Page Timeout 5000 mSec
+   5000,                       // Erase Sector Timeout 5000 mSec
+
+// Specify Size and Address of Sectors
+   0x002000, 0x000000,         // Sector Size  8kB (8 Sectors)
+   0x010000, 0x010000,         // Sector Size 64kB (5 Sectors)
+   SECTOR_END
+};
+#endif
+
+#ifdef FLASH_256_BA
+struct FlashDevice const FlashDevice  =  {
+   FLASH_DRV_VERS,             // Driver Version, do not modify!
+   "LPC18xx/43xx IAP 256kB Flash Bank A",  // Device Name
+   ONCHIP,                     // Device Type
+   0x1A000000,                 // Device Start Address
+   0x00040000,                 // Device Size (256kB)
+   1024,                       // Programming Page Size
+   0,                          // Reserved, must be 0
+   0xFF,                       // Initial Content of Erased Memory
+   5000,                       // Program Page Timeout 5000 mSec
+   5000,                       // Erase Sector Timeout 5000 mSec
+
+// Specify Size and Address of Sectors
+   0x002000, 0x000000,         // Sector Size  8kB (8 Sectors)
+   0x010000, 0x010000,         // Sector Size 64kB (3 Sectors)
+   SECTOR_END
+};
+#endif
+
+#ifdef FLASH_256_BB
+struct FlashDevice const FlashDevice  =  {
+   FLASH_DRV_VERS,             // Driver Version, do not modify!
+   "LPC18xx/43xx IAP 256kB Flash Bank B",  // Device Name
+   ONCHIP,                     // Device Type
+   0x1B000000,                 // Device Start Address
+   0x00040000,                 // Device Size (256kB)
+   1024,                       // Programming Page Size
+   0,                          // Reserved, must be 0
+   0xFF,                       // Initial Content of Erased Memory
+   5000,                       // Program Page Timeout 5000 mSec
+   5000,                       // Erase Sector Timeout 5000 mSec
+
+// Specify Size and Address of Sectors
+   0x002000, 0x000000,         // Sector Size  8kB (8 Sectors)
+   0x010000, 0x010000,         // Sector Size 64kB (3 Sectors)
+   SECTOR_END
+};
+#endif
+
+#endif // LPC18xx43xx

CMSIS/Pack/Example/Flash/LPC18xx43xx_IAP/FlashPrg.c

@@ -0,0 +1,291 @@
+/* -----------------------------------------------------------------------------
+ * Copyright (c) 2004 - 2014 ARM Ltd.
+ *
+ * This software is provided 'as-is', without any express or implied warranty. 
+ * In no event will the authors be held liable for any damages arising from 
+ * the use of this software. Permission is granted to anyone to use this 
+ * software for any purpose, including commercial applications, and to alter 
+ * it and redistribute it freely, subject to the following restrictions:
+ *
+ * 1. The origin of this software must not be misrepresented; you must not 
+ *    claim that you wrote the original software. If you use this software in
+ *    a product, an acknowledgment in the product documentation would be 
+ *    appreciated but is not required. 
+ * 
+ * 2. Altered source versions must be plainly marked as such, and must not be 
+ *    misrepresented as being the original software. 
+ * 
+ * 3. This notice may not be removed or altered from any source distribution.
+ *   
+ *
+ * $Date:        17. June 2014
+ * $Revision:    V1.01
+ *  
+ * Project:      Flash Device Description for NXP LPC18xx/43xx Flash using IAP
+ * --------------------------------------------------------------------------- */
+ 
+#include "..\FlashOS.H"        // FlashOS Structures
+
+// Memory Mapping Control
+#ifdef LPC18xx43xx
+  #define BASE_Mx_CLK (*(volatile unsigned long *) (0x4005006C))
+#endif
+
+
+#define BANK_A    0x1A000000
+#define BANK_B    0x1B000000
+
+#ifdef LPC18xx43xx
+  #if defined FLASH_512_BA || FLASH_512_BB
+    #define END_SECTOR     14
+  #endif
+  #if defined FLASH_384_BA || FLASH_384_BB
+    #define END_SECTOR     12
+  #endif
+  #if defined FLASH_256_BA || FLASH_256_BB
+    #define END_SECTOR     10
+  #endif
+#endif  // LPC18xx43xx
+
+unsigned long CCLK;            // CCLK in kHz
+
+struct sIAP {                  // IAP Structure
+  unsigned long cmd;           // Command
+  unsigned long par[5];        // Parameters
+  unsigned long stat;          // Status
+  unsigned long res[4];        // Result
+} IAP;
+
+
+/* IAP Call */
+typedef void (*IAP_Entry) (unsigned long *cmd, unsigned long *stat);
+#define IAP_Call ((IAP_Entry) *((unsigned long *)0x10400100))
+
+unsigned long base_adr;
+unsigned long flash_bank;
+
+/*
+ * Get Sector Number
+ *    Parameter:      adr:  Sector Address
+ *    Return Value:   Sector Number
+ */
+
+unsigned long GetSecNum (unsigned long adr) {
+  unsigned long n;
+
+  n = (adr & 0x000FF000) >> 13;                //  8kB Sector
+  if (n >= 0x07) {
+    n = 0x07 + (n >> 3);                       // 64kB Sector
+  }
+
+  return (n);                                  // Sector Number
+}
+
+
+/*
+ *  Initialize Flash Programming Functions
+ *    Parameter:      adr:  Device Base Address
+ *                    clk:  Clock Frequency (Hz)
+ *                    fnc:  Function Code (1 - Erase, 2 - Program, 3 - Verify)
+ *    Return Value:   0 - OK,  1 - Failed
+ */
+
+int Init (unsigned long adr, unsigned long clk, unsigned long fnc) {
+
+  base_adr   = adr;                            // store Flash Base Address
+  flash_bank = (adr == BANK_A) ? 0 : 1;
+
+  BASE_Mx_CLK = (0x01 << 11) |                 // Autoblock En
+                (0x01 << 24) ;                 // Set clock source to IRC
+  CCLK  = 12000;                               // 12MHz Internal RC Oscillator
+
+  IAP.cmd  = 49;                               // IAP initialization
+  IAP_Call (&IAP.cmd, &IAP.stat);              // Call IAP Command
+
+  IAP.stat =  0;                               // Note: Some Bootloader versions don't set the status if this command is executed
+  IAP.cmd  = 54;                               // Read Part ID
+  IAP_Call (&IAP.cmd, &IAP.stat);              // Call IAP Command
+  if (IAP.stat) return (1);                    // Command Failed
+
+  return (0);
+}
+
+
+/*
+ *  De-Initialize Flash Programming Functions
+ *    Parameter:      fnc:  Function Code (1 - Erase, 2 - Program, 3 - Verify)
+ *    Return Value:   0 - OK,  1 - Failed
+ */
+
+int UnInit (unsigned long fnc) {
+  return (0);
+}
+
+
+/*
+ *  Erase complete Flash Memory
+ *    Return Value:   0 - OK,  1 - Failed
+ */
+
+int EraseChip (void) {
+
+  IAP.cmd    = 50;                             // Prepare Sector for Erase
+  IAP.par[0] = 0;                              // Start Sector
+  IAP.par[1] = END_SECTOR;                     // End Sector
+  IAP.par[2] = flash_bank;                     // Flashbank
+  IAP_Call (&IAP.cmd, &IAP.stat);              // Call IAP Command
+  if (IAP.stat) return (1);                    // Command Failed
+
+  IAP.cmd    = 52;                             // Erase Sector
+  IAP.par[0] = 0;                              // Start Sector
+  IAP.par[1] = END_SECTOR;                     // End Sector
+  IAP.par[2] = CCLK;                           // CCLK in kHz
+  IAP.par[3] = flash_bank;                     // Flashbank
+  IAP_Call (&IAP.cmd, &IAP.stat);              // Call IAP Command
+  if (IAP.stat) return (1);                    // Command Failed
+
+  return (0);                                  // Finished without Errors
+}
+
+
+/*
+ *  Erase Sector in Flash Memory
+ *    Parameter:      adr:  Sector Address
+ *    Return Value:   0 - OK,  1 - Failed
+ */
+
+int EraseSector (unsigned long adr) {
+  unsigned long n;
+
+  n = GetSecNum(adr);                          // Get Sector Number
+
+  IAP.cmd    = 50;                             // Prepare Sector for Erase
+  IAP.par[0] = n;                              // Start Sector
+  IAP.par[1] = n;                              // End Sector
+  IAP.par[2] = flash_bank;                     // Flashbank
+  IAP_Call (&IAP.cmd, &IAP.stat);              // Call IAP Command
+  if (IAP.stat) return (1);                    // Command Failed
+
+  IAP.cmd    = 52;                             // Erase Sector
+  IAP.par[0] = n;                              // Start Sector
+  IAP.par[1] = n;                              // End Sector
+  IAP.par[2] = CCLK;                           // CCLK in kHz
+  IAP.par[3] = flash_bank;                     // Flashbank
+  IAP_Call (&IAP.cmd, &IAP.stat);              // Call IAP Command
+  if (IAP.stat) return (1);                    // Command Failed
+
+  return (0);                                  // Finished without Errors
+}
+
+
+/*
+ *  Program Page in Flash Memory
+ *    Parameter:      adr:  Page Start Address
+ *                    sz:   Page Size
+ *                    buf:  Page Data
+ *    Return Value:   0 - OK,  1 - Failed
+ */
+int ProgramPage (unsigned long adr, unsigned long sz, unsigned char *buf) {
+  unsigned long n;
+  unsigned long sig;
+
+  n = GetSecNum(adr);                          // Get Sector Number
+
+  IAP.cmd    = 50;                             // Prepare Sector for Write
+  IAP.par[0] = n;                              // Start Sector
+  IAP.par[1] = n;                              // End Sector
+  IAP.par[2] = flash_bank;                     // Flashbank
+  IAP_Call (&IAP.cmd, &IAP.stat);              // Call IAP Command
+  if (IAP.stat) return (1);                    // Command Failed
+
+  IAP.cmd    = 51;                             // Copy RAM to Flash
+  IAP.par[0] = adr;                            // Destination Flash Address
+  IAP.par[1] = (unsigned long)buf;             // Source RAM Address
+  IAP.par[2] = 1024;                           // Fixed Page Size
+  IAP.par[3] = CCLK;                           // CCLK in kHz
+  IAP.par[4] = flash_bank;                     // Flashbank
+  IAP_Call (&IAP.cmd, &IAP.stat);              // Call IAP Command
+  if (IAP.stat) return (1);                    // Command Failed
+
+/* calculates vectore checksum and more
+   It is not used because it erases the signature in th eother bank!
+   This could cause trouble if we want to have valid code or data in the other bank.
+   Utility ElfDwt.exe must be used to calculate Signatute and stote it in AXF file.
+ */
+//  if (adr == base_adr) {                       // Set active partition to FLASH_BANK if vectors are written
+//    IAP.cmd    = 60;                           // Set active partition
+//    IAP.par[0] = FLASH_BANK;                   // Flashbank
+//    IAP.par[1] = CCLK;                         // CCLK in kHz
+//    IAP_Call (&IAP.cmd, &IAP.stat);            // Call IAP Command
+//    if (IAP.stat) return (1);                  // Command Failed
+//  }
+#if 0
+  we also removed all special handling about the vector checksum because
+	it causes more trouble than solving problems. The user must now take 
+	care that only on valid checksum is in the application.
+
+  if (adr == BANK_B) {
+    sig = *((unsigned long *)(BANK_B + 0x00)) +
+          *((unsigned long *)(BANK_B + 0x04)) +
+          *((unsigned long *)(BANK_B + 0x08)) +
+          *((unsigned long *)(BANK_B + 0x0C)) +
+          *((unsigned long *)(BANK_B + 0x10)) +
+          *((unsigned long *)(BANK_B + 0x14)) +
+          *((unsigned long *)(BANK_B + 0x18));
+
+    if (*((unsigned long *)(BANK_B + 0x1C)) == (0 - sig)) {
+    /* we have just written a valid signature to BankB. We assume that we must boot from BankB
+       check if a valid signature is in BankA. If so delete it. */
+
+      sig = *((unsigned long *)(BANK_A + 0x00)) +
+            *((unsigned long *)(BANK_A + 0x04)) +
+            *((unsigned long *)(BANK_A + 0x08)) +
+            *((unsigned long *)(BANK_A + 0x0C)) +
+            *((unsigned long *)(BANK_A + 0x10)) +
+            *((unsigned long *)(BANK_A + 0x14)) +
+            *((unsigned long *)(BANK_A + 0x18));
+
+      /* delete signature if a valid signature is found */
+      if (*((unsigned long *)(BANK_A + 0x1C)) == (0 - sig)) {
+
+        for (n = 0; n < (512); n++) {
+          *(buf + n) = *((unsigned char *)(BANK_A + n)); // copy page to RAM
+        }
+
+        *((unsigned long *)(buf + 0x1C)) = 0;          // invalid Signature at Reserved Vector
+
+        IAP.cmd    = 50;                               // Prepare Sector for Write
+        IAP.par[0] = 0;                                // Start Sector
+        IAP.par[1] = 0;                                // End Sector
+        IAP.par[2] = 0;                                // Flashbank
+        IAP_Call (&IAP.cmd, &IAP.stat);                // Call IAP Command
+        if (IAP.stat) return (1);                      // Command Failed
+
+        IAP.cmd    = 59;                               // Erase Page
+        IAP.par[0] = BANK_A;                           // Start Page Address
+        IAP.par[1] = BANK_A;                           // End Page Address
+        IAP.par[2] = CCLK;                             // CCLK in kHz
+        IAP_Call (&IAP.cmd, &IAP.stat);                // Call IAP Command
+        if (IAP.stat) return (1);                      // Command Failed
+
+        IAP.cmd    = 50;                               // Prepare Sector for Write
+        IAP.par[0] = 0;                                // Start Sector
+        IAP.par[1] = 0;                                // End Sector
+        IAP.par[2] = 0;                                // Flashbank
+        IAP_Call (&IAP.cmd, &IAP.stat);                // Call IAP Command
+        if (IAP.stat) return (1);                      // Command Failed
+
+        IAP.cmd    = 51;                               // Copy RAM to Flash
+        IAP.par[0] = BANK_A;                           // Destination Flash Address
+        IAP.par[1] = (unsigned long)buf;               // Source RAM Address
+        IAP.par[2] = 512;                              // Fixed Page Size
+        IAP.par[3] = CCLK;                             // CCLK in kHz
+        IAP.par[4] = 0;                                // Flashbank
+        IAP_Call (&IAP.cmd, &IAP.stat);                // Call IAP Command
+        if (IAP.stat) return (1);                      // Command Failed
+      }
+    }
+  }
+#endif
+  return (0);                                          // Finished without Errors
+}