CMSIS-NN: Remove unused Examples folder

The pre-TFLu examples are removed.

Change-Id: I057350c0da241af2a85b086d73de0ee35a6d1f14

ARM.CMSIS.pdsc

@@ -23,6 +23,7 @@
         - Improved MVE performance for fully Connected and max pool operator
         - NULL bias support for fully connected operator in non-MVE case(Can affect performance)
         - Expanded existing unit test suite along with support for FVP
+        - Removed Examples folder
       CMSIS-RTOS2:
         - RTX 5.5.3 (see revision history for details)
       CMSIS-Pack: 1.7.2 (see revision history for details)
@@ -3774,66 +3775,6 @@ and 8-bit Java bytecodes in Jazelle state.
       </attributes>
     </example>
 
-    <example name="NN Library CIFAR10" doc="readme.txt" folder="CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10">
-      <description>Neural Network CIFAR10 example</description>
-      <board name="uVision Simulator" vendor="Keil"/>
-      <project>
-        <environment name="uv" load="arm_nnexamples_cifar10.uvprojx"/>
-      </project>
-      <attributes>
-        <component Cclass="CMSIS" Cgroup="CORE"/>
-        <component Cclass="CMSIS" Cgroup="DSP"/>
-        <component Cclass="CMSIS" Cgroup="NN Lib"/>
-        <component Cclass="Device" Cgroup="Startup"/>
-        <category>Getting Started</category>
-      </attributes>
-    </example>
-
-    <example name="NN-example-cifar10" doc="readme_iar.txt" folder="CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-cifar10">
-      <description>Neural Network CIFAR10 example</description>
-      <board name="EWARM Simulator" vendor="IAR"/>
-      <project>
-        <environment name="iar" load="NN-example-cifar10.ewp"/>
-      </project>
-      <attributes>
-        <component Cclass="CMSIS" Cgroup="CORE"/>
-        <component Cclass="CMSIS" Cgroup="DSP"/>
-        <component Cclass="CMSIS" Cgroup="NN Lib"/>
-        <component Cclass="Device" Cgroup="Startup"/>
-        <category>Getting Started</category>
-      </attributes>
-    </example>
-
-    <example name="NN Library GRU" doc="readme.txt" folder="CMSIS/NN/Examples/ARM/arm_nn_examples/gru">
-      <description>Neural Network GRU example</description>
-      <board name="uVision Simulator" vendor="Keil"/>
-      <project>
-        <environment name="uv" load="arm_nnexamples_gru.uvprojx"/>
-      </project>
-      <attributes>
-        <component Cclass="CMSIS" Cgroup="CORE"/>
-        <component Cclass="CMSIS" Cgroup="DSP"/>
-        <component Cclass="CMSIS" Cgroup="NN Lib"/>
-        <component Cclass="Device" Cgroup="Startup"/>
-        <category>Getting Started</category>
-      </attributes>
-    </example>
-
-    <example name="NN-example-gru" doc="readme_iar.txt" folder="CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-gru">
-      <description>Neural Network GRU example</description>
-      <board name="EWARM Simulator" vendor="IAR"/>
-      <project>
-        <environment name="iar" load="NN-example-gru.ewp"/>
-      </project>
-      <attributes>
-        <component Cclass="CMSIS" Cgroup="CORE"/>
-        <component Cclass="CMSIS" Cgroup="DSP"/>
-        <component Cclass="CMSIS" Cgroup="NN Lib"/>
-        <component Cclass="Device" Cgroup="Startup"/>
-        <category>Getting Started</category>
-      </attributes>
-    </example>
-
     <example name="CMSIS-RTOS2 Blinky" doc="Abstract.txt" folder="CMSIS/RTOS2/RTX/Examples/Blinky">
       <description>CMSIS-RTOS2 Blinky example</description>
       <board name="uVision Simulator" vendor="Keil"/>

CMSIS/DoxyGen/NN/nn.dxy

@@ -750,7 +750,6 @@ WARN_LOGFILE           =
 # Note: If this tag is empty the current directory is searched.
 
 INPUT                  = ./src/history.txt      \
-                         ../../NN/Examples/ARM  \
                          ../../NN/Include/      \
                          ../../NN/Source/
 
@@ -852,7 +851,7 @@ EXCLUDE_SYMBOLS        =
 # that contain example code fragments that are included (see the \include
 # command).
 
-EXAMPLE_PATH           = ../../NN/Examples/ARM
+EXAMPLE_PATH           =
 
 # If the value of the EXAMPLE_PATH tag contains directories, you can use the
 # EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp and

CMSIS/DoxyGen/NN/src/history.txt

@@ -15,6 +15,7 @@
       the weight offset parameter is expected to be zero<br> </li>
       <li> Added unit test for Softmax </li>
       <li> Added MVE optimiztion for SVDF operator </li>
+      <li> Removed Examples folder </li>
       </ul>
     </td>
   </tr>

CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/EventRecorderStub.scvd

@@ -1,9 +0,0 @@
-<?xml version="1.0" encoding="utf-8"?>
-
-<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
-
-<component name="EventRecorderStub" version="1.0.0"/>       <!--name and version of the component-->
-  <events>
-  </events>
-
-</component_viewer>

CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Compiler/EventRecorderConf.h

@@ -1,44 +0,0 @@
-/*------------------------------------------------------------------------------
- * MDK - Component ::Event Recorder
- * Copyright (c) 2016 ARM Germany GmbH. All rights reserved.
- *------------------------------------------------------------------------------
- * Name:    EventRecorderConf.h
- * Purpose: Event Recorder Configuration
- * Rev.:    V1.0.0
- *----------------------------------------------------------------------------*/
-
-//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
-
-// <h>Event Recorder
-
-//   <o>Number of Records
-//     <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 <256=>256 <512=>512 <1024=>1024
-//     <2048=>2048 <4096=>4096 <8192=>8192 <16384=>16384 <32768=>32768
-//     <65536=>65536 <131072=>131072 <262144=>262144 <524288=>524288
-//     <1048576=>1048576
-//   <i>Configure size of Event Record Buffer (each record is 16 bytes)
-//   <i>Must be 2^n (min=8, max=1048576)
-#define EVENT_RECORD_COUNT      64U
-
-//   <o>Time Stamp Source
-//      <0=> DWT Cycle Counter  <1=> SysTick
-//      <3=> User Timer (Normal Reset)  <4=> User Timer (Power-On Reset)
-//   <i>Selects source for 32-bit time stamp
-#define EVENT_TIMESTAMP_SOURCE  1
-
-//   <h>SysTick Configuration
-//   <i>Configure values when Time Stamp Source is set to SysTick
-
-//     <o>SysTick Input Clock Frequency [Hz] <1-1000000000>
-//     <i>Defines SysTick input clock (typical identical with processor clock)
-#define SYSTICK_CLOCK           100000000U
-
-//     <o>SysTick Interrupt Period [us] <1-1000000000>
-//     <i>Defines time period of the SysTick timer interrupt
-#define SYSTICK_PERIOD_US       1000U
-
-//   </h>
-
-// </h>
-
-//------------- <<< end of configuration section >>> ---------------------------

CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM0/startup_ARMCM0.s

@@ -1,242 +0,0 @@
-;/**************************************************************************//**
-; * @file     startup_ARMCM0.s
-; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM0 Device Series
-; * @version  V5.00
-; * @date     02. March 2016
-; ******************************************************************************/
-;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
-; *
-; * SPDX-License-Identifier: Apache-2.0
-; *
-; * Licensed under the Apache License, Version 2.0 (the License); you may
-; * not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; */
-
-;/*
-;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
-
-
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000C00
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
-                DCD     RTC_IRQHandler            ;  1:  Real Time Clock
-                DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
-                DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
-                DCD     MCIA_IRQHandler           ;  4:  MCIa
-                DCD     MCIB_IRQHandler           ;  5:  MCIb
-                DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
-                DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
-                DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
-                DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
-                DCD     AACI_IRQHandler           ; 10: AACI / AC97
-                DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
-                DCD     ENET_IRQHandler           ; 12: Ethernet
-                DCD     USBDC_IRQHandler          ; 13: USB Device
-                DCD     USBHC_IRQHandler          ; 14: USB Host Controller
-                DCD     CHLCD_IRQHandler          ; 15: Character LCD
-                DCD     FLEXRAY_IRQHandler        ; 16: Flexray
-                DCD     CAN_IRQHandler            ; 17: CAN
-                DCD     LIN_IRQHandler            ; 18: LIN
-                DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
-                DCD     0                         ; 20: Reserved
-                DCD     0                         ; 21: Reserved
-                DCD     0                         ; 22: Reserved
-                DCD     0                         ; 23: Reserved
-                DCD     0                         ; 24: Reserved
-                DCD     0                         ; 25: Reserved
-                DCD     0                         ; 26: Reserved
-                DCD     0                         ; 27: Reserved
-                DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
-                DCD     0                         ; 29: Reserved - CPU FPGA
-                DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
-                DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
-__Vectors_End
-
-__Vectors_Size  EQU     __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-
-; Reset Handler
-
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  SystemInit
-                IMPORT  __main
-                LDR     R0, =SystemInit
-                BLX     R0
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler               [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WDT_IRQHandler            [WEAK]
-                EXPORT  RTC_IRQHandler            [WEAK]
-                EXPORT  TIM0_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler           [WEAK]
-                EXPORT  MCIA_IRQHandler           [WEAK]
-                EXPORT  MCIB_IRQHandler           [WEAK]
-                EXPORT  UART0_IRQHandler          [WEAK]
-                EXPORT  UART1_IRQHandler          [WEAK]
-                EXPORT  UART2_IRQHandler          [WEAK]
-                EXPORT  UART3_IRQHandler          [WEAK]
-                EXPORT  UART4_IRQHandler          [WEAK]
-                EXPORT  AACI_IRQHandler           [WEAK]
-                EXPORT  CLCD_IRQHandler           [WEAK]
-                EXPORT  ENET_IRQHandler           [WEAK]
-                EXPORT  USBDC_IRQHandler          [WEAK]
-                EXPORT  USBHC_IRQHandler          [WEAK]
-                EXPORT  CHLCD_IRQHandler          [WEAK]
-                EXPORT  FLEXRAY_IRQHandler        [WEAK]
-                EXPORT  CAN_IRQHandler            [WEAK]
-                EXPORT  LIN_IRQHandler            [WEAK]
-                EXPORT  I2C_IRQHandler            [WEAK]
-                EXPORT  CPU_CLCD_IRQHandler       [WEAK]
-                EXPORT  SPI_IRQHandler            [WEAK]
-
-WDT_IRQHandler
-RTC_IRQHandler
-TIM0_IRQHandler
-TIM2_IRQHandler
-MCIA_IRQHandler
-MCIB_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-UART3_IRQHandler
-UART4_IRQHandler
-AACI_IRQHandler
-CLCD_IRQHandler
-ENET_IRQHandler
-USBDC_IRQHandler
-USBHC_IRQHandler
-CHLCD_IRQHandler
-FLEXRAY_IRQHandler
-CAN_IRQHandler
-LIN_IRQHandler
-I2C_IRQHandler
-CPU_CLCD_IRQHandler
-SPI_IRQHandler
-                B       .
-
-                ENDP
-
-
-                ALIGN
-
-
-; User Initial Stack & Heap
-
-                IF      :DEF:__MICROLIB
-
-                EXPORT  __initial_sp
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-
-                ELSE
-
-                IMPORT  __use_two_region_memory
-                EXPORT  __user_initial_stackheap
-
-__user_initial_stackheap PROC
-                LDR     R0, =  Heap_Mem
-                LDR     R1, =(Stack_Mem + Stack_Size)
-                LDR     R2, = (Heap_Mem +  Heap_Size)
-                LDR     R3, = Stack_Mem
-                BX      LR
-                ENDP
-
-                ALIGN
-
-                ENDIF
-
-
-                END

CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM0/system_ARMCM0.c

@@ -1,56 +0,0 @@
-/**************************************************************************//**
- * @file     system_ARMCM0.c
- * @brief    CMSIS Device System Source File for
- *           ARMCM0 Device Series
- * @version  V5.00
- * @date     08. April 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "ARMCM0.h"
-
-/*----------------------------------------------------------------------------
-  Define clocks
- *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000U)      /* Oscillator frequency */
-
-#define  SYSTEM_CLOCK    (5 * XTAL)
-
-
-/*----------------------------------------------------------------------------
-  System Core Clock Variable
- *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
-
-
-/*----------------------------------------------------------------------------
-  System Core Clock update function
- *----------------------------------------------------------------------------*/
-void SystemCoreClockUpdate (void)
-{
-  SystemCoreClock = SYSTEM_CLOCK;
-}
-
-/*----------------------------------------------------------------------------
-  System initialization function
- *----------------------------------------------------------------------------*/
-void SystemInit (void)
-{
-  SystemCoreClock = SYSTEM_CLOCK;
-}

CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM3/startup_ARMCM3.s

@@ -1,262 +0,0 @@
-;/**************************************************************************//**
-; * @file     startup_ARMCM3.s
-; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM3 Device Series
-; * @version  V5.00
-; * @date     02. March 2016
-; ******************************************************************************/
-;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
-; *
-; * SPDX-License-Identifier: Apache-2.0
-; *
-; * Licensed under the Apache License, Version 2.0 (the License); you may
-; * not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; */
-
-;/*
-;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
-
-
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000C00
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
-                DCD     RTC_IRQHandler            ;  1:  Real Time Clock
-                DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
-                DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
-                DCD     MCIA_IRQHandler           ;  4:  MCIa
-                DCD     MCIB_IRQHandler           ;  5:  MCIb
-                DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
-                DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
-                DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
-                DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
-                DCD     AACI_IRQHandler           ; 10: AACI / AC97
-                DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
-                DCD     ENET_IRQHandler           ; 12: Ethernet
-                DCD     USBDC_IRQHandler          ; 13: USB Device
-                DCD     USBHC_IRQHandler          ; 14: USB Host Controller
-                DCD     CHLCD_IRQHandler          ; 15: Character LCD
-                DCD     FLEXRAY_IRQHandler        ; 16: Flexray
-                DCD     CAN_IRQHandler            ; 17: CAN
-                DCD     LIN_IRQHandler            ; 18: LIN
-                DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
-                DCD     0                         ; 20: Reserved
-                DCD     0                         ; 21: Reserved
-                DCD     0                         ; 22: Reserved
-                DCD     0                         ; 23: Reserved
-                DCD     0                         ; 24: Reserved
-                DCD     0                         ; 25: Reserved
-                DCD     0                         ; 26: Reserved
-                DCD     0                         ; 27: Reserved
-                DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
-                DCD     0                         ; 29: Reserved - CPU FPGA
-                DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
-                DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
-__Vectors_End
-
-__Vectors_Size  EQU     __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-
-; Reset Handler
-
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  SystemInit
-                IMPORT  __main
-                LDR     R0, =SystemInit
-                BLX     R0
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler               [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler         [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler          [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler        [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler          [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WDT_IRQHandler            [WEAK]
-                EXPORT  RTC_IRQHandler            [WEAK]
-                EXPORT  TIM0_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler           [WEAK]
-                EXPORT  MCIA_IRQHandler           [WEAK]
-                EXPORT  MCIB_IRQHandler           [WEAK]
-                EXPORT  UART0_IRQHandler          [WEAK]
-                EXPORT  UART1_IRQHandler          [WEAK]
-                EXPORT  UART2_IRQHandler          [WEAK]
-                EXPORT  UART3_IRQHandler          [WEAK]
-                EXPORT  UART4_IRQHandler          [WEAK]
-                EXPORT  AACI_IRQHandler           [WEAK]
-                EXPORT  CLCD_IRQHandler           [WEAK]
-                EXPORT  ENET_IRQHandler           [WEAK]
-                EXPORT  USBDC_IRQHandler          [WEAK]
-                EXPORT  USBHC_IRQHandler          [WEAK]
-                EXPORT  CHLCD_IRQHandler          [WEAK]
-                EXPORT  FLEXRAY_IRQHandler        [WEAK]
-                EXPORT  CAN_IRQHandler            [WEAK]
-                EXPORT  LIN_IRQHandler            [WEAK]
-                EXPORT  I2C_IRQHandler            [WEAK]
-                EXPORT  CPU_CLCD_IRQHandler       [WEAK]
-                EXPORT  SPI_IRQHandler            [WEAK]
-
-WDT_IRQHandler
-RTC_IRQHandler
-TIM0_IRQHandler
-TIM2_IRQHandler
-MCIA_IRQHandler
-MCIB_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-UART3_IRQHandler
-UART4_IRQHandler
-AACI_IRQHandler
-CLCD_IRQHandler
-ENET_IRQHandler
-USBDC_IRQHandler
-USBHC_IRQHandler
-CHLCD_IRQHandler
-FLEXRAY_IRQHandler
-CAN_IRQHandler
-LIN_IRQHandler
-I2C_IRQHandler
-CPU_CLCD_IRQHandler
-SPI_IRQHandler
-                B       .
-
-                ENDP
-
-
-                ALIGN
-
-
-; User Initial Stack & Heap
-
-                IF      :DEF:__MICROLIB
-
-                EXPORT  __initial_sp
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-
-                ELSE
-
-                IMPORT  __use_two_region_memory
-                EXPORT  __user_initial_stackheap
-
-__user_initial_stackheap PROC
-                LDR     R0, =  Heap_Mem
-                LDR     R1, =(Stack_Mem + Stack_Size)
-                LDR     R2, = (Heap_Mem +  Heap_Size)
-                LDR     R3, = Stack_Mem
-                BX      LR
-                ENDP
-
-                ALIGN
-
-                ENDIF
-
-
-                END

CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM3/system_ARMCM3.c

@@ -1,68 +0,0 @@
-/**************************************************************************//**
- * @file     system_ARMCM3.c
- * @brief    CMSIS Device System Source File for
- *           ARMCM3 Device Series
- * @version  V5.00
- * @date     08. April 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "ARMCM3.h"
-
-/*----------------------------------------------------------------------------
-  Define clocks
- *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000U)      /* Oscillator frequency */
-
-#define  SYSTEM_CLOCK    (5 * XTAL)
-
-
-/*----------------------------------------------------------------------------
-  Externals
- *----------------------------------------------------------------------------*/
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1)
-  extern uint32_t __Vectors;
-#endif
-
-/*----------------------------------------------------------------------------
-  System Core Clock Variable
- *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
-
-
-/*----------------------------------------------------------------------------
-  System Core Clock update function
- *----------------------------------------------------------------------------*/
-void SystemCoreClockUpdate (void)
-{
-  SystemCoreClock = SYSTEM_CLOCK;
-}
-
-/*----------------------------------------------------------------------------
-  System initialization function
- *----------------------------------------------------------------------------*/
-void SystemInit (void)
-{
-
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1)
-  SCB->VTOR = (uint32_t) &__Vectors;
-#endif
-
-  SystemCoreClock = SYSTEM_CLOCK;
-}

CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM4_FP/startup_ARMCM4.s

@@ -1,262 +0,0 @@
-;/**************************************************************************//**
-; * @file     startup_ARMCM4.s
-; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM4 Device Series
-; * @version  V5.00
-; * @date     02. March 2016
-; ******************************************************************************/
-;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
-; *
-; * SPDX-License-Identifier: Apache-2.0
-; *
-; * Licensed under the Apache License, Version 2.0 (the License); you may
-; * not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; */
-
-;/*
-;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
-
-
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000C00
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
-                DCD     RTC_IRQHandler            ;  1:  Real Time Clock
-                DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
-                DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
-                DCD     MCIA_IRQHandler           ;  4:  MCIa
-                DCD     MCIB_IRQHandler           ;  5:  MCIb
-                DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
-                DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
-                DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
-                DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
-                DCD     AACI_IRQHandler           ; 10: AACI / AC97
-                DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
-                DCD     ENET_IRQHandler           ; 12: Ethernet
-                DCD     USBDC_IRQHandler          ; 13: USB Device
-                DCD     USBHC_IRQHandler          ; 14: USB Host Controller
-                DCD     CHLCD_IRQHandler          ; 15: Character LCD
-                DCD     FLEXRAY_IRQHandler        ; 16: Flexray
-                DCD     CAN_IRQHandler            ; 17: CAN
-                DCD     LIN_IRQHandler            ; 18: LIN
-                DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
-                DCD     0                         ; 20: Reserved
-                DCD     0                         ; 21: Reserved
-                DCD     0                         ; 22: Reserved
-                DCD     0                         ; 23: Reserved
-                DCD     0                         ; 24: Reserved
-                DCD     0                         ; 25: Reserved
-                DCD     0                         ; 26: Reserved
-                DCD     0                         ; 27: Reserved
-                DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
-                DCD     0                         ; 29: Reserved - CPU FPGA
-                DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
-                DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
-__Vectors_End
-
-__Vectors_Size  EQU     __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-
-; Reset Handler
-
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  SystemInit
-                IMPORT  __main
-                LDR     R0, =SystemInit
-                BLX     R0
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler               [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler         [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler          [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler        [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler          [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WDT_IRQHandler            [WEAK]
-                EXPORT  RTC_IRQHandler            [WEAK]
-                EXPORT  TIM0_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler           [WEAK]
-                EXPORT  MCIA_IRQHandler           [WEAK]
-                EXPORT  MCIB_IRQHandler           [WEAK]
-                EXPORT  UART0_IRQHandler          [WEAK]
-                EXPORT  UART1_IRQHandler          [WEAK]
-                EXPORT  UART2_IRQHandler          [WEAK]
-                EXPORT  UART3_IRQHandler          [WEAK]
-                EXPORT  UART4_IRQHandler          [WEAK]
-                EXPORT  AACI_IRQHandler           [WEAK]
-                EXPORT  CLCD_IRQHandler           [WEAK]
-                EXPORT  ENET_IRQHandler           [WEAK]
-                EXPORT  USBDC_IRQHandler          [WEAK]
-                EXPORT  USBHC_IRQHandler          [WEAK]
-                EXPORT  CHLCD_IRQHandler          [WEAK]
-                EXPORT  FLEXRAY_IRQHandler        [WEAK]
-                EXPORT  CAN_IRQHandler            [WEAK]
-                EXPORT  LIN_IRQHandler            [WEAK]
-                EXPORT  I2C_IRQHandler            [WEAK]
-                EXPORT  CPU_CLCD_IRQHandler       [WEAK]
-                EXPORT  SPI_IRQHandler            [WEAK]
-
-WDT_IRQHandler
-RTC_IRQHandler
-TIM0_IRQHandler
-TIM2_IRQHandler
-MCIA_IRQHandler
-MCIB_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-UART3_IRQHandler
-UART4_IRQHandler
-AACI_IRQHandler
-CLCD_IRQHandler
-ENET_IRQHandler
-USBDC_IRQHandler
-USBHC_IRQHandler
-CHLCD_IRQHandler
-FLEXRAY_IRQHandler
-CAN_IRQHandler
-LIN_IRQHandler
-I2C_IRQHandler
-CPU_CLCD_IRQHandler
-SPI_IRQHandler
-                B       .
-
-                ENDP
-
-
-                ALIGN
-
-
-; User Initial Stack & Heap
-
-                IF      :DEF:__MICROLIB
-
-                EXPORT  __initial_sp
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-
-                ELSE
-
-                IMPORT  __use_two_region_memory
-                EXPORT  __user_initial_stackheap
-
-__user_initial_stackheap PROC
-                LDR     R0, =  Heap_Mem
-                LDR     R1, =(Stack_Mem + Stack_Size)
-                LDR     R2, = (Heap_Mem +  Heap_Size)
-                LDR     R3, = Stack_Mem
-                BX      LR
-                ENDP
-
-                ALIGN
-
-                ENDIF
-
-
-                END

CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM4_FP/system_ARMCM4.c

@@ -1,83 +0,0 @@
-/**************************************************************************//**
- * @file     system_ARMCM4.c
- * @brief    CMSIS Device System Source File for
- *           ARMCM4 Device Series
- * @version  V5.00
- * @date     08. April 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if defined (ARMCM4)
-  #include "ARMCM4.h"
-#elif defined (ARMCM4_FP)
-  #include "ARMCM4_FP.h"
-#else
-  #error device not specified!
-#endif
-
-/*----------------------------------------------------------------------------
-  Define clocks
- *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000U)      /* Oscillator frequency */
-
-#define  SYSTEM_CLOCK    (5 * XTAL)
-
-
-/*----------------------------------------------------------------------------
-  Externals
- *----------------------------------------------------------------------------*/
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1)
-  extern uint32_t __Vectors;
-#endif
-
-/*----------------------------------------------------------------------------
-  System Core Clock Variable
- *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
-
-
-/*----------------------------------------------------------------------------
-  System Core Clock update function
- *----------------------------------------------------------------------------*/
-void SystemCoreClockUpdate (void)
-{
-  SystemCoreClock = SYSTEM_CLOCK;
-}
-
-/*----------------------------------------------------------------------------
-  System initialization function
- *----------------------------------------------------------------------------*/
-void SystemInit (void)
-{
-
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1)
-  SCB->VTOR = (uint32_t) &__Vectors;
-#endif
-
-#if defined (__FPU_USED) && (__FPU_USED == 1)
-  SCB->CPACR |= ((3U << 10*2) |           /* set CP10 Full Access */
-                 (3U << 11*2)  );         /* set CP11 Full Access */
-#endif
-
-#ifdef UNALIGNED_SUPPORT_DISABLE
-  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
-#endif
-
-  SystemCoreClock = SYSTEM_CLOCK;
-}

CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/gcc_arm.ld

@@ -1,196 +0,0 @@
-/* Linker script to configure memory regions. */
-MEMORY
-{
-  FLASH (rx)  : ORIGIN = 0x00000000, LENGTH = 512K
-  RAM   (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
-}
-
-/* Library configurations */
-GROUP(libgcc.a libc.a libm.a libnosys.a)
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- *   Reset_Handler : Entry of reset handler
- *
- * It defines following symbols, which code can use without definition:
- *   __exidx_start
- *   __exidx_end
- *   __copy_table_start__
- *   __copy_table_end__
- *   __zero_table_start__
- *   __zero_table_end__
- *   __etext
- *   __data_start__
- *   __preinit_array_start
- *   __preinit_array_end
- *   __init_array_start
- *   __init_array_end
- *   __fini_array_start
- *   __fini_array_end
- *   __data_end__
- *   __bss_start__
- *   __bss_end__
- *   __end__
- *   end
- *   __HeapBase
- *   __HeapLimit
- *   __StackLimit
- *   __StackTop
- *   __stack
- *   __Vectors_End
- *   __Vectors_Size
- */
-ENTRY(Reset_Handler)
-
-SECTIONS
-{
-	.text :
-	{
-		KEEP(*(.vectors))
-		__Vectors_End = .;
-		__Vectors_Size = __Vectors_End - __Vectors;
-		__end__ = .;
-
-		*(.text*)
-
-		KEEP(*(.init))
-		KEEP(*(.fini))
-
-		/* .ctors */
-		*crtbegin.o(.ctors)
-		*crtbegin?.o(.ctors)
-		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
-		*(SORT(.ctors.*))
-		*(.ctors)
-
-		/* .dtors */
- 		*crtbegin.o(.dtors)
- 		*crtbegin?.o(.dtors)
- 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
- 		*(SORT(.dtors.*))
- 		*(.dtors)
-
-		*(.rodata*)
-
-		KEEP(*(.eh_frame*))
-	} > FLASH
-
-	.ARM.extab :
-	{
-		*(.ARM.extab* .gnu.linkonce.armextab.*)
-	} > FLASH
-
-	__exidx_start = .;
-	.ARM.exidx :
-	{
-		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
-	} > FLASH
-	__exidx_end = .;
-
-	/* To copy multiple ROM to RAM sections,
-	 * uncomment .copy.table section and,
-	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
-	/*
-	.copy.table :
-	{
-		. = ALIGN(4);
-		__copy_table_start__ = .;
-		LONG (__etext)
-		LONG (__data_start__)
-		LONG (__data_end__ - __data_start__)
-		LONG (__etext2)
-		LONG (__data2_start__)
-		LONG (__data2_end__ - __data2_start__)
-		__copy_table_end__ = .;
-	} > FLASH
-	*/
-
-	/* To clear multiple BSS sections,
-	 * uncomment .zero.table section and,
-	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
-	/*
-	.zero.table :
-	{
-		. = ALIGN(4);
-		__zero_table_start__ = .;
-		LONG (__bss_start__)
-		LONG (__bss_end__ - __bss_start__)
-		LONG (__bss2_start__)
-		LONG (__bss2_end__ - __bss2_start__)
-		__zero_table_end__ = .;
-	} > FLASH
-	*/
-
-	__etext = .;
-
-	.data : AT (__etext)
-	{
-		__data_start__ = .;
-		*(vtable)
-		*(.data*)
-
-		. = ALIGN(4);
-		/* preinit data */
-		PROVIDE_HIDDEN (__preinit_array_start = .);
-		KEEP(*(.preinit_array))
-		PROVIDE_HIDDEN (__preinit_array_end = .);
-
-		. = ALIGN(4);
-		/* init data */
-		PROVIDE_HIDDEN (__init_array_start = .);
-		KEEP(*(SORT(.init_array.*)))
-		KEEP(*(.init_array))
-		PROVIDE_HIDDEN (__init_array_end = .);
-
-
-		. = ALIGN(4);
-		/* finit data */
-		PROVIDE_HIDDEN (__fini_array_start = .);
-		KEEP(*(SORT(.fini_array.*)))
-		KEEP(*(.fini_array))
-		PROVIDE_HIDDEN (__fini_array_end = .);
-
-		KEEP(*(.jcr*))
-		. = ALIGN(4);
-		/* All data end */
-		__data_end__ = .;
-
-	} > RAM
-
-	.bss :
-	{
-		. = ALIGN(4);
-		__bss_start__ = .;
-		*(.bss*)
-		*(COMMON)
-		. = ALIGN(4);
-		__bss_end__ = .;
-	} > RAM
-
-	.heap (COPY):
-	{
-		__HeapBase = .;
-		__end__ = .;
-		end = __end__;
-		KEEP(*(.heap*))
-		__HeapLimit = .;
-	} > RAM
-
-	/* .stack_dummy section doesn't contains any symbols. It is only
-	 * used for linker to calculate size of stack sections, and assign
-	 * values to stack symbols later */
-	.stack_dummy (COPY):
-	{
-		KEEP(*(.stack*))
-	} > RAM
-
-	/* Set stack top to end of RAM, and stack limit move down by
-	 * size of stack_dummy section */
-	__StackTop = ORIGIN(RAM) + LENGTH(RAM);
-	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
-	PROVIDE(__stack = __StackTop);
-
-	/* Check if data + heap + stack exceeds RAM limit */
-	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
-}

CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/startup_ARMCM7.c

@@ -1,295 +0,0 @@
-/**************************************************************************//**
- * @file     startup_ARMCM7.s
- * @brief    CMSIS Core Device Startup File for
- *           ARMCM7 Device Series
- * @version  V5.00
- * @date     26. April 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include <stdint.h>
-
-
-/*----------------------------------------------------------------------------
-  Linker generated Symbols
- *----------------------------------------------------------------------------*/
-extern uint32_t __etext;
-extern uint32_t __data_start__;
-extern uint32_t __data_end__;
-extern uint32_t __copy_table_start__;
-extern uint32_t __copy_table_end__;
-extern uint32_t __zero_table_start__;
-extern uint32_t __zero_table_end__;
-extern uint32_t __bss_start__;
-extern uint32_t __bss_end__;
-extern uint32_t __StackTop;
-
-/*----------------------------------------------------------------------------
-  Exception / Interrupt Handler Function Prototype
- *----------------------------------------------------------------------------*/
-typedef void( *pFunc )( void );
-
-
-/*----------------------------------------------------------------------------
-  External References
- *----------------------------------------------------------------------------*/
-#ifndef __START
-extern void  _start(void) __attribute__((noreturn));    /* PreeMain (C library entry point) */
-#else
-extern int  __START(void) __attribute__((noreturn));    /* main entry point */
-#endif
-
-#ifndef __NO_SYSTEM_INIT
-extern void SystemInit (void);            /* CMSIS System Initialization      */
-#endif
-
-
-/*----------------------------------------------------------------------------
-  Internal References
- *----------------------------------------------------------------------------*/
-void Default_Handler(void);                          /* Default empty handler */
-void Reset_Handler(void);                            /* Reset Handler */
-
-
-/*----------------------------------------------------------------------------
-  User Initial Stack & Heap
- *----------------------------------------------------------------------------*/
-#ifndef __STACK_SIZE
-  #define	__STACK_SIZE  0x00000400
-#endif
-static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack")));
-
-#ifndef __HEAP_SIZE
-  #define	__HEAP_SIZE   0x00000C00
-#endif
-#if __HEAP_SIZE > 0
-static uint8_t heap[__HEAP_SIZE]   __attribute__ ((aligned(8), used, section(".heap")));
-#endif
-
-
-/*----------------------------------------------------------------------------
-  Exception / Interrupt Handler
- *----------------------------------------------------------------------------*/
-/* Cortex-M7 Processor Exceptions */
-void NMI_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
-void HardFault_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
-void MemManage_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
-void BusFault_Handler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UsageFault_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
-void SVC_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
-void DebugMon_Handler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void PendSV_Handler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void SysTick_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
-
-/* ARMCM7 Specific Interrupts */
-void WDT_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void RTC_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM0_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM2_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIA_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIB_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART0_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART1_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART2_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART4_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void AACI_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void CLCD_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void ENET_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBDC_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBHC_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void CHLCD_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void FLEXRAY_IRQHandler  (void) __attribute__ ((weak, alias("Default_Handler")));
-void CAN_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void LIN_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void I2C_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void CPU_CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART3_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void SPI_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-
-
-/*----------------------------------------------------------------------------
-  Exception / Interrupt Vector table
- *----------------------------------------------------------------------------*/
-const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = {
-  /* Cortex-M7 Exceptions Handler */
-  (pFunc)((uint32_t)&__StackTop),           /*      Initial Stack Pointer     */
-  Reset_Handler,                            /*      Reset Handler             */
-  NMI_Handler,                              /*      NMI Handler               */
-  HardFault_Handler,                        /*      Hard Fault Handler        */
-  MemManage_Handler,                        /*      MPU Fault Handler         */
-  BusFault_Handler,                         /*      Bus Fault Handler         */
-  UsageFault_Handler,                       /*      Usage Fault Handler       */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  SVC_Handler,                              /*      SVCall Handler            */
-  DebugMon_Handler,                         /*      Debug Monitor Handler     */
-  0,                                        /*      Reserved                  */
-  PendSV_Handler,                           /*      PendSV Handler            */
-  SysTick_Handler,                          /*      SysTick Handler           */
-
-  /* External interrupts */
-  WDT_IRQHandler,                           /*  0:  Watchdog Timer            */
-  RTC_IRQHandler,                           /*  1:  Real Time Clock           */
-  TIM0_IRQHandler,                          /*  2:  Timer0 / Timer1           */
-  TIM2_IRQHandler,                          /*  3:  Timer2 / Timer3           */
-  MCIA_IRQHandler,                          /*  4:  MCIa                      */
-  MCIB_IRQHandler,                          /*  5:  MCIb                      */
-  UART0_IRQHandler,                         /*  6:  UART0 - DUT FPGA          */
-  UART1_IRQHandler,                         /*  7:  UART1 - DUT FPGA          */
-  UART2_IRQHandler,                         /*  8:  UART2 - DUT FPGA          */
-  UART4_IRQHandler,                         /*  9:  UART4 - not connected     */
-  AACI_IRQHandler,                          /* 10: AACI / AC97                */
-  CLCD_IRQHandler,                          /* 11: CLCD Combined Interrupt    */
-  ENET_IRQHandler,                          /* 12: Ethernet                   */
-  USBDC_IRQHandler,                         /* 13: USB Device                 */
-  USBHC_IRQHandler,                         /* 14: USB Host Controller        */
-  CHLCD_IRQHandler,                         /* 15: Character LCD              */
-  FLEXRAY_IRQHandler,                       /* 16: Flexray                    */
-  CAN_IRQHandler,                           /* 17: CAN                        */
-  LIN_IRQHandler,                           /* 18: LIN                        */
-  I2C_IRQHandler,                           /* 19: I2C ADC/DAC                */
-  0,                                        /* 20: Reserved                   */
-  0,                                        /* 21: Reserved                   */
-  0,                                        /* 22: Reserved                   */
-  0,                                        /* 23: Reserved                   */
-  0,                                        /* 24: Reserved                   */
-  0,                                        /* 25: Reserved                   */
-  0,                                        /* 26: Reserved                   */
-  0,                                        /* 27: Reserved                   */
-  CPU_CLCD_IRQHandler,                      /* 28: Reserved - CPU FPGA CLCD   */
-  0,                                        /* 29: Reserved - CPU FPGA        */
-  UART3_IRQHandler,                         /* 30: UART3    - CPU FPGA        */
-  SPI_IRQHandler                            /* 31: SPI Touchscreen - CPU FPGA */
-};
-
-
-/*----------------------------------------------------------------------------
-  Reset Handler called on controller reset
- *----------------------------------------------------------------------------*/
-void Reset_Handler(void) {
-  uint32_t *pSrc, *pDest;
-  uint32_t *pTable __attribute__((unused));
-
-/*  Firstly it copies data from read only memory to RAM. There are two schemes
- *  to copy. One can copy more than one sections. Another can only copy
- *  one section.  The former scheme needs more instructions and read-only
- *  data to implement than the latter.
- *  Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.  */
-
-#ifdef __STARTUP_COPY_MULTIPLE
-/*  Multiple sections scheme.
- *
- *  Between symbol address __copy_table_start__ and __copy_table_end__,
- *  there are array of triplets, each of which specify:
- *    offset 0: LMA of start of a section to copy from
- *    offset 4: VMA of start of a section to copy to
- *    offset 8: size of the section to copy. Must be multiply of 4
- *
- *  All addresses must be aligned to 4 bytes boundary.
- */
-  pTable = &__copy_table_start__;
-
-  for (; pTable < &__copy_table_end__; pTable = pTable + 3) {
-		pSrc  = (uint32_t*)*(pTable + 0);
-		pDest = (uint32_t*)*(pTable + 1);
-		for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
-      *pDest++ = *pSrc++;
-		}
-	}
-#else
-/*  Single section scheme.
- *
- *  The ranges of copy from/to are specified by following symbols
- *    __etext: LMA of start of the section to copy from. Usually end of text
- *    __data_start__: VMA of start of the section to copy to
- *    __data_end__: VMA of end of the section to copy to
- *
- *  All addresses must be aligned to 4 bytes boundary.
- */
-  pSrc  = &__etext;
-  pDest = &__data_start__;
-
-  for ( ; pDest < &__data_end__ ; ) {
-    *pDest++ = *pSrc++;
-  }
-#endif /*__STARTUP_COPY_MULTIPLE */
-
-/*  This part of work usually is done in C library startup code. Otherwise,
- *  define this macro to enable it in this startup.
- *
- *  There are two schemes too. One can clear multiple BSS sections. Another
- *  can only clear one section. The former is more size expensive than the
- *  latter.
- *
- *  Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- *  Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
- */
-#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/*  Multiple sections scheme.
- *
- *  Between symbol address __copy_table_start__ and __copy_table_end__,
- *  there are array of tuples specifying:
- *    offset 0: Start of a BSS section
- *    offset 4: Size of this BSS section. Must be multiply of 4
- */
-  pTable = &__zero_table_start__;
-
-  for (; pTable < &__zero_table_end__; pTable = pTable + 2) {
-		pDest = (uint32_t*)*(pTable + 0);
-		for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
-      *pDest++ = 0;
-		}
-	}
-#elif defined (__STARTUP_CLEAR_BSS)
-/*  Single BSS section scheme.
- *
- *  The BSS section is specified by following symbols
- *    __bss_start__: start of the BSS section.
- *    __bss_end__: end of the BSS section.
- *
- *  Both addresses must be aligned to 4 bytes boundary.
- */
-  pDest = &__bss_start__;
-
-  for ( ; pDest < &__bss_end__ ; ) {
-    *pDest++ = 0UL;
-  }
-#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-
-#ifndef __NO_SYSTEM_INIT
-	SystemInit();
-#endif
-
-#ifndef __START
-#define __START _start
-#endif
-	__START();
-
-}
-
-
-/*----------------------------------------------------------------------------
-  Default Handler for Exceptions / Interrupts
- *----------------------------------------------------------------------------*/
-void Default_Handler(void) {
-
-	while(1);
-}

CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/startup_ARMCM7.s

@@ -1,262 +0,0 @@
-;/**************************************************************************//**
-; * @file     startup_ARMCM7.s
-; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM7 Device Series
-; * @version  V5.00
-; * @date     02. March 2016
-; ******************************************************************************/
-;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
-; *
-; * SPDX-License-Identifier: Apache-2.0
-; *
-; * Licensed under the Apache License, Version 2.0 (the License); you may
-; * not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; */
-
-;/*
-;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
-
-
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000C00
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
-                DCD     RTC_IRQHandler            ;  1:  Real Time Clock
-                DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
-                DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
-                DCD     MCIA_IRQHandler           ;  4:  MCIa
-                DCD     MCIB_IRQHandler           ;  5:  MCIb
-                DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
-                DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
-                DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
-                DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
-                DCD     AACI_IRQHandler           ; 10: AACI / AC97
-                DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
-                DCD     ENET_IRQHandler           ; 12: Ethernet
-                DCD     USBDC_IRQHandler          ; 13: USB Device
-                DCD     USBHC_IRQHandler          ; 14: USB Host Controller
-                DCD     CHLCD_IRQHandler          ; 15: Character LCD
-                DCD     FLEXRAY_IRQHandler        ; 16: Flexray
-                DCD     CAN_IRQHandler            ; 17: CAN
-                DCD     LIN_IRQHandler            ; 18: LIN
-                DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
-                DCD     0                         ; 20: Reserved
-                DCD     0                         ; 21: Reserved
-                DCD     0                         ; 22: Reserved
-                DCD     0                         ; 23: Reserved
-                DCD     0                         ; 24: Reserved
-                DCD     0                         ; 25: Reserved
-                DCD     0                         ; 26: Reserved
-                DCD     0                         ; 27: Reserved
-                DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
-                DCD     0                         ; 29: Reserved - CPU FPGA
-                DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
-                DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
-__Vectors_End
-
-__Vectors_Size  EQU     __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-
-; Reset Handler
-
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  SystemInit
-                IMPORT  __main
-                LDR     R0, =SystemInit
-                BLX     R0
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler               [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler         [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler          [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler        [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler          [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WDT_IRQHandler            [WEAK]
-                EXPORT  RTC_IRQHandler            [WEAK]
-                EXPORT  TIM0_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler           [WEAK]
-                EXPORT  MCIA_IRQHandler           [WEAK]
-                EXPORT  MCIB_IRQHandler           [WEAK]
-                EXPORT  UART0_IRQHandler          [WEAK]
-                EXPORT  UART1_IRQHandler          [WEAK]
-                EXPORT  UART2_IRQHandler          [WEAK]
-                EXPORT  UART3_IRQHandler          [WEAK]
-                EXPORT  UART4_IRQHandler          [WEAK]
-                EXPORT  AACI_IRQHandler           [WEAK]
-                EXPORT  CLCD_IRQHandler           [WEAK]
-                EXPORT  ENET_IRQHandler           [WEAK]
-                EXPORT  USBDC_IRQHandler          [WEAK]
-                EXPORT  USBHC_IRQHandler          [WEAK]
-                EXPORT  CHLCD_IRQHandler          [WEAK]
-                EXPORT  FLEXRAY_IRQHandler        [WEAK]
-                EXPORT  CAN_IRQHandler            [WEAK]
-                EXPORT  LIN_IRQHandler            [WEAK]
-                EXPORT  I2C_IRQHandler            [WEAK]
-                EXPORT  CPU_CLCD_IRQHandler       [WEAK]
-                EXPORT  SPI_IRQHandler            [WEAK]
-
-WDT_IRQHandler
-RTC_IRQHandler
-TIM0_IRQHandler
-TIM2_IRQHandler
-MCIA_IRQHandler
-MCIB_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-UART3_IRQHandler
-UART4_IRQHandler
-AACI_IRQHandler
-CLCD_IRQHandler
-ENET_IRQHandler
-USBDC_IRQHandler
-USBHC_IRQHandler
-CHLCD_IRQHandler
-FLEXRAY_IRQHandler
-CAN_IRQHandler
-LIN_IRQHandler
-I2C_IRQHandler
-CPU_CLCD_IRQHandler
-SPI_IRQHandler
-                B       .
-
-                ENDP
-
-
-                ALIGN
-
-
-; User Initial Stack & Heap
-
-                IF      :DEF:__MICROLIB
-
-                EXPORT  __initial_sp
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-
-                ELSE
-
-                IMPORT  __use_two_region_memory
-                EXPORT  __user_initial_stackheap
-
-__user_initial_stackheap PROC
-                LDR     R0, =  Heap_Mem
-                LDR     R1, =(Stack_Mem + Stack_Size)
-                LDR     R2, = (Heap_Mem +  Heap_Size)
-                LDR     R3, = Stack_Mem
-                BX      LR
-                ENDP
-
-                ALIGN
-
-                ENDIF
-
-
-                END

CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/system_ARMCM7.c

@@ -1,85 +0,0 @@
-/**************************************************************************//**
- * @file     system_ARMCM7.c
- * @brief    CMSIS Device System Source File for
- *           ARMCM7 Device Series
- * @version  V5.00
- * @date     08. April 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if defined (ARMCM7)
-  #include "ARMCM7.h"
-#elif defined (ARMCM7_SP)
-  #include "ARMCM7_SP.h"
-#elif defined (ARMCM7_DP)
-  #include "ARMCM7_DP.h"
-#else
-  #error device not specified!
-#endif
-
-/*----------------------------------------------------------------------------
-  Define clocks
- *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000U)      /* Oscillator frequency */
-
-#define  SYSTEM_CLOCK    (5 * XTAL)
-
-
-/*----------------------------------------------------------------------------
-  Externals
- *----------------------------------------------------------------------------*/
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1)
-  extern uint32_t __Vectors;
-#endif
-
-/*----------------------------------------------------------------------------
-  System Core Clock Variable
- *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
-
-
-/*----------------------------------------------------------------------------
-  System Core Clock update function
- *----------------------------------------------------------------------------*/
-void SystemCoreClockUpdate (void)
-{
-  SystemCoreClock = SYSTEM_CLOCK;
-}
-
-/*----------------------------------------------------------------------------
-  System initialization function
- *----------------------------------------------------------------------------*/
-void SystemInit (void)
-{
-
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1)
-  SCB->VTOR = (uint32_t) &__Vectors;
-#endif
-
-#if defined (__FPU_USED) && (__FPU_USED == 1)
-  SCB->CPACR |= ((3U << 10*2) |           /* set CP10 Full Access */
-                 (3U << 11*2)  );         /* set CP11 Full Access */
-#endif
-
-#ifdef UNALIGNED_SUPPORT_DISABLE
-  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
-#endif
-
-  SystemCoreClock = SYSTEM_CLOCK;
-}

CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM0/RTE_Components.h

@@ -1,24 +0,0 @@
-
-/*
- * Auto generated Run-Time-Environment Component Configuration File
- *      *** Do not modify ! ***
- *
- * Project: 'arm_nnexamples_cifar10' 
- * Target:  'ARMCM0' 
- */
-
-#ifndef RTE_COMPONENTS_H
-#define RTE_COMPONENTS_H
-
-
-/*
- * Define the Device Header File: 
- */
-#define CMSIS_device_header "ARMCM0.h"
-
-#define RTE_Compiler_EventRecorder
-          #define RTE_Compiler_EventRecorder_DAP
-#define RTE_Compiler_IO_STDOUT          /* Compiler I/O: STDOUT */
-          #define RTE_Compiler_IO_STDOUT_EVR      /* Compiler I/O: STDOUT EVR */
-
-#endif /* RTE_COMPONENTS_H */

CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM3/RTE_Components.h

@@ -1,22 +0,0 @@
-
-/*
- * Auto generated Run-Time-Environment Component Configuration File
- *      *** Do not modify ! ***
- *
- * Project: 'arm_nnexamples_cifar10' 
- * Target:  'ARMCM3' 
- */
-
-#ifndef RTE_COMPONENTS_H
-#define RTE_COMPONENTS_H
-
-
-/*
- * Define the Device Header File: 
- */
-#define CMSIS_device_header "ARMCM3.h"
-
-#define RTE_Compiler_IO_STDOUT          /* Compiler I/O: STDOUT */
-          #define RTE_Compiler_IO_STDOUT_ITM      /* Compiler I/O: STDOUT ITM */
-
-#endif /* RTE_COMPONENTS_H */

CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM4_FP/RTE_Components.h

@@ -1,22 +0,0 @@
-
-/*
- * Auto generated Run-Time-Environment Component Configuration File
- *      *** Do not modify ! ***
- *
- * Project: 'arm_nnexamples_cifar10' 
- * Target:  'ARMCM4_FP' 
- */
-
-#ifndef RTE_COMPONENTS_H
-#define RTE_COMPONENTS_H
-
-
-/*
- * Define the Device Header File: 
- */
-#define CMSIS_device_header "ARMCM4_FP.h"
-
-#define RTE_Compiler_IO_STDOUT          /* Compiler I/O: STDOUT */
-          #define RTE_Compiler_IO_STDOUT_ITM      /* Compiler I/O: STDOUT ITM */
-
-#endif /* RTE_COMPONENTS_H */

CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM7_SP/RTE_Components.h

@@ -1,22 +0,0 @@
-
-/*
- * Auto generated Run-Time-Environment Component Configuration File
- *      *** Do not modify ! ***
- *
- * Project: 'arm_nnexamples_cifar10' 
- * Target:  'ARMCM7_SP' 
- */
-
-#ifndef RTE_COMPONENTS_H
-#define RTE_COMPONENTS_H
-
-
-/*
- * Define the Device Header File: 
- */
-#define CMSIS_device_header "ARMCM7_SP.h"
-
-#define RTE_Compiler_IO_STDOUT          /* Compiler I/O: STDOUT */
-          #define RTE_Compiler_IO_STDOUT_ITM      /* Compiler I/O: STDOUT ITM */
-
-#endif /* RTE_COMPONENTS_H */

CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10.cpp

@@ -1,196 +0,0 @@
-/* ----------------------------------------------------------------------
-* Copyright (C) 2010-2018 Arm Limited. All rights reserved.
-*
-*
-* Project:       CMSIS NN Library
-* Title:         arm_nnexamples_cifar10.cpp
-*
-* Description:   Convolutional Neural Network Example
-*
-* Target Processor: Cortex-M4/Cortex-M7
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the
-*     distribution.
-*   - Neither the name of Arm LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.
-* -------------------------------------------------------------------- */
-
-/**
- * @ingroup groupExamples
- */
-
-/**
- * @defgroup CNNExample Convolutional Neural Network Example
- *
- * \par Description:
- * \par
- * Demonstrates a convolutional neural network (CNN) example with the use of convolution,
- * ReLU activation, pooling and fully-connected functions.
- *
- * \par Model definition:
- * \par
- * The CNN used in this example is based on CIFAR-10 example from Caffe [1]. 
- * The neural network consists
- * of 3 convolution layers interspersed by ReLU activation and max pooling layers, followed by a 
- * fully-connected layer at the end. The input to the network is a 32x32 pixel color image, which will 
- * be classified into one of the 10 output classes. 
- * This example model implementation needs 32.3 KB to store weights, 40 KB for activations and 
- * 3.1 KB for storing the \c im2col data.
- *
- * \image html CIFAR10_CNN.gif "Neural Network model definition"
- *
- * \par Variables Description:
- * \par
- * \li \c conv1_wt, \c conv2_wt, \c conv3_wt are convolution layer weight matrices
- * \li \c conv1_bias, \c conv2_bias, \c conv3_bias are convolution layer bias arrays
- * \li \c ip1_wt, ip1_bias point to fully-connected layer weights and biases
- * \li \c input_data points to the input image data
- * \li \c output_data points to the classification output
- * \li \c col_buffer is a buffer to store the \c im2col output
- * \li \c scratch_buffer is used to store the activation data (intermediate layer outputs)
- *
- * \par CMSIS DSP Software Library Functions Used:
- * \par
- * - arm_convolve_HWC_q7_RGB()
- * - arm_convolve_HWC_q7_fast()
- * - arm_relu_q7()
- * - arm_maxpool_q7_HWC()
- * - arm_avepool_q7_HWC()
- * - arm_fully_connected_q7_opt()
- * - arm_fully_connected_q7()
- *
- * <b> Refer  </b>
- * \link arm_nnexamples_cifar10.cpp \endlink
- *
- * \par [1] https://github.com/BVLC/caffe
- */
-
-#include <stdint.h>
-#include <stdio.h>
-#include "arm_math.h"
-#include "arm_nnexamples_cifar10_parameter.h"
-#include "arm_nnexamples_cifar10_weights.h"
-
-#include "arm_nnfunctions.h"
-#include "arm_nnexamples_cifar10_inputs.h"
-
-#ifdef _RTE_
-#include "RTE_Components.h"
-#ifdef RTE_Compiler_EventRecorder
-#include "EventRecorder.h"
-#endif
-#endif
-
-// include the input and weights
-
-static q7_t conv1_wt[CONV1_IM_CH * CONV1_KER_DIM * CONV1_KER_DIM * CONV1_OUT_CH] = CONV1_WT;
-static q7_t conv1_bias[CONV1_OUT_CH] = CONV1_BIAS;
-
-static q7_t conv2_wt[CONV2_IM_CH * CONV2_KER_DIM * CONV2_KER_DIM * CONV2_OUT_CH] = CONV2_WT;
-static q7_t conv2_bias[CONV2_OUT_CH] = CONV2_BIAS;
-
-static q7_t conv3_wt[CONV3_IM_CH * CONV3_KER_DIM * CONV3_KER_DIM * CONV3_OUT_CH] = CONV3_WT;
-static q7_t conv3_bias[CONV3_OUT_CH] = CONV3_BIAS;
-
-static q7_t ip1_wt[IP1_DIM * IP1_OUT] = IP1_WT;
-static q7_t ip1_bias[IP1_OUT] = IP1_BIAS;
-
-/* Here the image_data should be the raw uint8 type RGB image in [RGB, RGB, RGB ... RGB] format */
-uint8_t   image_data[CONV1_IM_CH * CONV1_IM_DIM * CONV1_IM_DIM] = IMG_DATA;
-q7_t      output_data[IP1_OUT];
-
-//vector buffer: max(im2col buffer,average pool buffer, fully connected buffer)
-q7_t      col_buffer[2 * 5 * 5 * 32 * 2];
-
-q7_t      scratch_buffer[32 * 32 * 10 * 4];
-
-int main()
-{
-  #ifdef RTE_Compiler_EventRecorder
-  EventRecorderInitialize (EventRecordAll, 1);  // initialize and start Event Recorder
-  #endif
-
-  printf("start execution\n");
-  /* start the execution */
-
-  q7_t     *img_buffer1 = scratch_buffer;
-  q7_t     *img_buffer2 = img_buffer1 + 32 * 32 * 32;
-
-  /* input pre-processing */
-  int mean_data[3] = INPUT_MEAN_SHIFT;
-  unsigned int scale_data[3] = INPUT_RIGHT_SHIFT;
-  for (int i=0;i<32*32*3; i+=3) {
-    img_buffer2[i] =   (q7_t)__SSAT( ((((int)image_data[i]   - mean_data[0])<<7) + (0x1<<(scale_data[0]-1)))
-                             >> scale_data[0], 8);
-    img_buffer2[i+1] = (q7_t)__SSAT( ((((int)image_data[i+1] - mean_data[1])<<7) + (0x1<<(scale_data[1]-1)))
-                             >> scale_data[1], 8);
-    img_buffer2[i+2] = (q7_t)__SSAT( ((((int)image_data[i+2] - mean_data[2])<<7) + (0x1<<(scale_data[2]-1)))
-                             >> scale_data[2], 8);
-  }
-  
-  // conv1 img_buffer2 -> img_buffer1
-  arm_convolve_HWC_q7_RGB(img_buffer2, CONV1_IM_DIM, CONV1_IM_CH, conv1_wt, CONV1_OUT_CH, CONV1_KER_DIM, CONV1_PADDING,
-                          CONV1_STRIDE, conv1_bias, CONV1_BIAS_LSHIFT, CONV1_OUT_RSHIFT, img_buffer1, CONV1_OUT_DIM,
-                          (q15_t *) col_buffer, NULL);
-
-  arm_relu_q7(img_buffer1, CONV1_OUT_DIM * CONV1_OUT_DIM * CONV1_OUT_CH);
-
-  // pool1 img_buffer1 -> img_buffer2
-  arm_maxpool_q7_HWC(img_buffer1, CONV1_OUT_DIM, CONV1_OUT_CH, POOL1_KER_DIM,
-                     POOL1_PADDING, POOL1_STRIDE, POOL1_OUT_DIM, NULL, img_buffer2);
-
-  // conv2 img_buffer2 -> img_buffer1
-  arm_convolve_HWC_q7_fast(img_buffer2, CONV2_IM_DIM, CONV2_IM_CH, conv2_wt, CONV2_OUT_CH, CONV2_KER_DIM,
-                           CONV2_PADDING, CONV2_STRIDE, conv2_bias, CONV2_BIAS_LSHIFT, CONV2_OUT_RSHIFT, img_buffer1,
-                           CONV2_OUT_DIM, (q15_t *) col_buffer, NULL);
-
-  arm_relu_q7(img_buffer1, CONV2_OUT_DIM * CONV2_OUT_DIM * CONV2_OUT_CH);
-
-  // pool2 img_buffer1 -> img_buffer2
-  arm_maxpool_q7_HWC(img_buffer1, CONV2_OUT_DIM, CONV2_OUT_CH, POOL2_KER_DIM,
-                     POOL2_PADDING, POOL2_STRIDE, POOL2_OUT_DIM, col_buffer, img_buffer2);
-
-// conv3 img_buffer2 -> img_buffer1
-  arm_convolve_HWC_q7_fast(img_buffer2, CONV3_IM_DIM, CONV3_IM_CH, conv3_wt, CONV3_OUT_CH, CONV3_KER_DIM,
-                           CONV3_PADDING, CONV3_STRIDE, conv3_bias, CONV3_BIAS_LSHIFT, CONV3_OUT_RSHIFT, img_buffer1,
-                           CONV3_OUT_DIM, (q15_t *) col_buffer, NULL);
-
-  arm_relu_q7(img_buffer1, CONV3_OUT_DIM * CONV3_OUT_DIM * CONV3_OUT_CH);
-
-  // pool3 img_buffer-> img_buffer2
-  arm_maxpool_q7_HWC(img_buffer1, CONV3_OUT_DIM, CONV3_OUT_CH, POOL3_KER_DIM,
-                     POOL3_PADDING, POOL3_STRIDE, POOL3_OUT_DIM, col_buffer, img_buffer2);
-
-  arm_fully_connected_q7_opt(img_buffer2, ip1_wt, IP1_DIM, IP1_OUT, IP1_BIAS_LSHIFT, IP1_OUT_RSHIFT, ip1_bias,
-                             output_data, (q15_t *) img_buffer1);
-
-  arm_softmax_q7(output_data, 10, output_data);
-
-  for (int i = 0; i < 10; i++)
-  {
-      printf("%d: %d\n", i, output_data[i]);
-  }
-
-  return 0;
-}

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-      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM7\Source\ARM\startup_ARMCM7.s" version="1.0.0">
-        <instance index="0">RTE\Device\ARMCM7_SP\startup_ARMCM7.s</instance>
-        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM7 CMSIS"/>
-        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.3.0"/>
-        <targetInfos>
-          <targetInfo name="ARMCM7_SP"/>
-        </targetInfos>
-      </file>
-      <file attr="config" category="sourceC" name="Device\ARM\ARMCM7\Source\system_ARMCM7.c" version="1.0.0">
-        <instance index="0">RTE\Device\ARMCM7_SP\system_ARMCM7.c</instance>
-        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM7 CMSIS"/>
-        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.3.0"/>
-        <targetInfos>
-          <targetInfo name="ARMCM7_SP"/>
-        </targetInfos>
-      </file>
-    </files>
-  </RTE>
-
-</Project>

CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_parameter.h

@@ -1,43 +0,0 @@
-#define CONV1_IM_DIM 32
-#define CONV1_IM_CH 3
-#define CONV1_KER_DIM 5
-#define CONV1_PADDING 2
-#define CONV1_STRIDE 1
-#define CONV1_OUT_CH 32
-#define CONV1_OUT_DIM 32
-
-#define POOL1_KER_DIM 3
-#define POOL1_STRIDE 2
-#define POOL1_PADDING 0
-#define POOL1_OUT_DIM 16
-
-#define CONV2_IM_DIM 16
-#define CONV2_IM_CH 32
-#define CONV2_KER_DIM 5
-#define CONV2_PADDING 2
-#define CONV2_STRIDE 1
-#define CONV2_OUT_CH 16
-#define CONV2_OUT_DIM 16
-
-#define POOL2_KER_DIM 3
-#define POOL2_STRIDE 2
-#define POOL2_PADDING 0
-#define POOL2_OUT_DIM 8
-
-#define CONV3_IM_DIM 8
-#define CONV3_IM_CH 16
-#define CONV3_KER_DIM 5
-#define CONV3_PADDING 2
-#define CONV3_STRIDE 1
-#define CONV3_OUT_CH 32
-#define CONV3_OUT_DIM 8
-
-#define POOL3_KER_DIM 3
-#define POOL3_STRIDE 2
-#define POOL3_PADDING 0
-#define POOL3_OUT_DIM 4
-
-#define IP1_DIM 4*4*32
-#define IP1_IM_DIM 4
-#define IP1_IM_CH 32
-#define IP1_OUT 10

CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/readme.txt

@@ -1,4 +0,0 @@
-CMSIS NN Lib example arm_nnexample_cifar10 for
-  Cortex-M4 and Cortex-M7.
-
-The example is configured for uVision Simulator.

CMSIS/NN/Examples/ARM/arm_nn_examples/gru/EventRecorderStub.scvd

@@ -1,9 +0,0 @@
-<?xml version="1.0" encoding="utf-8"?>
-
-<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
-
-<component name="EventRecorderStub" version="1.0.0"/>       <!--name and version of the component-->
-  <events>
-  </events>
-
-</component_viewer>

CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Compiler/EventRecorderConf.h

@@ -1,44 +0,0 @@
-/*------------------------------------------------------------------------------
- * MDK - Component ::Event Recorder
- * Copyright (c) 2016 ARM Germany GmbH. All rights reserved.
- *------------------------------------------------------------------------------
- * Name:    EventRecorderConf.h
- * Purpose: Event Recorder Configuration
- * Rev.:    V1.0.0
- *----------------------------------------------------------------------------*/
-
-//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
-
-// <h>Event Recorder
-
-//   <o>Number of Records
-//     <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 <256=>256 <512=>512 <1024=>1024
-//     <2048=>2048 <4096=>4096 <8192=>8192 <16384=>16384 <32768=>32768
-//     <65536=>65536 <131072=>131072 <262144=>262144 <524288=>524288
-//     <1048576=>1048576
-//   <i>Configure size of Event Record Buffer (each record is 16 bytes)
-//   <i>Must be 2^n (min=8, max=1048576)
-#define EVENT_RECORD_COUNT      64U
-
-//   <o>Time Stamp Source
-//      <0=> DWT Cycle Counter  <1=> SysTick
-//      <3=> User Timer (Normal Reset)  <4=> User Timer (Power-On Reset)
-//   <i>Selects source for 32-bit time stamp
-#define EVENT_TIMESTAMP_SOURCE  1
-
-//   <h>SysTick Configuration
-//   <i>Configure values when Time Stamp Source is set to SysTick
-
-//     <o>SysTick Input Clock Frequency [Hz] <1-1000000000>
-//     <i>Defines SysTick input clock (typical identical with processor clock)
-#define SYSTICK_CLOCK           100000000U
-
-//     <o>SysTick Interrupt Period [us] <1-1000000000>
-//     <i>Defines time period of the SysTick timer interrupt
-#define SYSTICK_PERIOD_US       1000U
-
-//   </h>
-
-// </h>
-
-//------------- <<< end of configuration section >>> ---------------------------

CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM0/startup_ARMCM0.s

@@ -1,242 +0,0 @@
-;/**************************************************************************//**
-; * @file     startup_ARMCM0.s
-; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM0 Device Series
-; * @version  V5.00
-; * @date     02. March 2016
-; ******************************************************************************/
-;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
-; *
-; * SPDX-License-Identifier: Apache-2.0
-; *
-; * Licensed under the Apache License, Version 2.0 (the License); you may
-; * not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; */
-
-;/*
-;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
-
-
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000C00
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
-                DCD     RTC_IRQHandler            ;  1:  Real Time Clock
-                DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
-                DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
-                DCD     MCIA_IRQHandler           ;  4:  MCIa
-                DCD     MCIB_IRQHandler           ;  5:  MCIb
-                DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
-                DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
-                DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
-                DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
-                DCD     AACI_IRQHandler           ; 10: AACI / AC97
-                DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
-                DCD     ENET_IRQHandler           ; 12: Ethernet
-                DCD     USBDC_IRQHandler          ; 13: USB Device
-                DCD     USBHC_IRQHandler          ; 14: USB Host Controller
-                DCD     CHLCD_IRQHandler          ; 15: Character LCD
-                DCD     FLEXRAY_IRQHandler        ; 16: Flexray
-                DCD     CAN_IRQHandler            ; 17: CAN
-                DCD     LIN_IRQHandler            ; 18: LIN
-                DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
-                DCD     0                         ; 20: Reserved
-                DCD     0                         ; 21: Reserved
-                DCD     0                         ; 22: Reserved
-                DCD     0                         ; 23: Reserved
-                DCD     0                         ; 24: Reserved
-                DCD     0                         ; 25: Reserved
-                DCD     0                         ; 26: Reserved
-                DCD     0                         ; 27: Reserved
-                DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
-                DCD     0                         ; 29: Reserved - CPU FPGA
-                DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
-                DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
-__Vectors_End
-
-__Vectors_Size  EQU     __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-
-; Reset Handler
-
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  SystemInit
-                IMPORT  __main
-                LDR     R0, =SystemInit
-                BLX     R0
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler               [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WDT_IRQHandler            [WEAK]
-                EXPORT  RTC_IRQHandler            [WEAK]
-                EXPORT  TIM0_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler           [WEAK]
-                EXPORT  MCIA_IRQHandler           [WEAK]
-                EXPORT  MCIB_IRQHandler           [WEAK]
-                EXPORT  UART0_IRQHandler          [WEAK]
-                EXPORT  UART1_IRQHandler          [WEAK]
-                EXPORT  UART2_IRQHandler          [WEAK]
-                EXPORT  UART3_IRQHandler          [WEAK]
-                EXPORT  UART4_IRQHandler          [WEAK]
-                EXPORT  AACI_IRQHandler           [WEAK]
-                EXPORT  CLCD_IRQHandler           [WEAK]
-                EXPORT  ENET_IRQHandler           [WEAK]
-                EXPORT  USBDC_IRQHandler          [WEAK]
-                EXPORT  USBHC_IRQHandler          [WEAK]
-                EXPORT  CHLCD_IRQHandler          [WEAK]
-                EXPORT  FLEXRAY_IRQHandler        [WEAK]
-                EXPORT  CAN_IRQHandler            [WEAK]
-                EXPORT  LIN_IRQHandler            [WEAK]
-                EXPORT  I2C_IRQHandler            [WEAK]
-                EXPORT  CPU_CLCD_IRQHandler       [WEAK]
-                EXPORT  SPI_IRQHandler            [WEAK]
-
-WDT_IRQHandler
-RTC_IRQHandler
-TIM0_IRQHandler
-TIM2_IRQHandler
-MCIA_IRQHandler
-MCIB_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-UART3_IRQHandler
-UART4_IRQHandler
-AACI_IRQHandler
-CLCD_IRQHandler
-ENET_IRQHandler
-USBDC_IRQHandler
-USBHC_IRQHandler
-CHLCD_IRQHandler
-FLEXRAY_IRQHandler
-CAN_IRQHandler
-LIN_IRQHandler
-I2C_IRQHandler
-CPU_CLCD_IRQHandler
-SPI_IRQHandler
-                B       .
-
-                ENDP
-
-
-                ALIGN
-
-
-; User Initial Stack & Heap
-
-                IF      :DEF:__MICROLIB
-
-                EXPORT  __initial_sp
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-
-                ELSE
-
-                IMPORT  __use_two_region_memory
-                EXPORT  __user_initial_stackheap
-
-__user_initial_stackheap PROC
-                LDR     R0, =  Heap_Mem
-                LDR     R1, =(Stack_Mem + Stack_Size)
-                LDR     R2, = (Heap_Mem +  Heap_Size)
-                LDR     R3, = Stack_Mem
-                BX      LR
-                ENDP
-
-                ALIGN
-
-                ENDIF
-
-
-                END

CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM0/system_ARMCM0.c

@@ -1,56 +0,0 @@
-/**************************************************************************//**
- * @file     system_ARMCM0.c
- * @brief    CMSIS Device System Source File for
- *           ARMCM0 Device Series
- * @version  V5.00
- * @date     08. April 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "ARMCM0.h"
-
-/*----------------------------------------------------------------------------
-  Define clocks
- *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000U)      /* Oscillator frequency */
-
-#define  SYSTEM_CLOCK    (5 * XTAL)
-
-
-/*----------------------------------------------------------------------------
-  System Core Clock Variable
- *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
-
-
-/*----------------------------------------------------------------------------
-  System Core Clock update function
- *----------------------------------------------------------------------------*/
-void SystemCoreClockUpdate (void)
-{
-  SystemCoreClock = SYSTEM_CLOCK;
-}
-
-/*----------------------------------------------------------------------------
-  System initialization function
- *----------------------------------------------------------------------------*/
-void SystemInit (void)
-{
-  SystemCoreClock = SYSTEM_CLOCK;
-}

CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM3/startup_ARMCM3.s

@@ -1,262 +0,0 @@
-;/**************************************************************************//**
-; * @file     startup_ARMCM3.s
-; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM3 Device Series
-; * @version  V5.00
-; * @date     02. March 2016
-; ******************************************************************************/
-;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
-; *
-; * SPDX-License-Identifier: Apache-2.0
-; *
-; * Licensed under the Apache License, Version 2.0 (the License); you may
-; * not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; */
-
-;/*
-;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
-
-
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000C00
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
-                DCD     RTC_IRQHandler            ;  1:  Real Time Clock
-                DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
-                DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
-                DCD     MCIA_IRQHandler           ;  4:  MCIa
-                DCD     MCIB_IRQHandler           ;  5:  MCIb
-                DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
-                DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
-                DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
-                DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
-                DCD     AACI_IRQHandler           ; 10: AACI / AC97
-                DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
-                DCD     ENET_IRQHandler           ; 12: Ethernet
-                DCD     USBDC_IRQHandler          ; 13: USB Device
-                DCD     USBHC_IRQHandler          ; 14: USB Host Controller
-                DCD     CHLCD_IRQHandler          ; 15: Character LCD
-                DCD     FLEXRAY_IRQHandler        ; 16: Flexray
-                DCD     CAN_IRQHandler            ; 17: CAN
-                DCD     LIN_IRQHandler            ; 18: LIN
-                DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
-                DCD     0                         ; 20: Reserved
-                DCD     0                         ; 21: Reserved
-                DCD     0                         ; 22: Reserved
-                DCD     0                         ; 23: Reserved
-                DCD     0                         ; 24: Reserved
-                DCD     0                         ; 25: Reserved
-                DCD     0                         ; 26: Reserved
-                DCD     0                         ; 27: Reserved
-                DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
-                DCD     0                         ; 29: Reserved - CPU FPGA
-                DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
-                DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
-__Vectors_End
-
-__Vectors_Size  EQU     __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-
-; Reset Handler
-
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  SystemInit
-                IMPORT  __main
-                LDR     R0, =SystemInit
-                BLX     R0
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler               [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler         [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler          [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler        [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler          [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WDT_IRQHandler            [WEAK]
-                EXPORT  RTC_IRQHandler            [WEAK]
-                EXPORT  TIM0_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler           [WEAK]
-                EXPORT  MCIA_IRQHandler           [WEAK]
-                EXPORT  MCIB_IRQHandler           [WEAK]
-                EXPORT  UART0_IRQHandler          [WEAK]
-                EXPORT  UART1_IRQHandler          [WEAK]
-                EXPORT  UART2_IRQHandler          [WEAK]
-                EXPORT  UART3_IRQHandler          [WEAK]
-                EXPORT  UART4_IRQHandler          [WEAK]
-                EXPORT  AACI_IRQHandler           [WEAK]
-                EXPORT  CLCD_IRQHandler           [WEAK]
-                EXPORT  ENET_IRQHandler           [WEAK]
-                EXPORT  USBDC_IRQHandler          [WEAK]
-                EXPORT  USBHC_IRQHandler          [WEAK]
-                EXPORT  CHLCD_IRQHandler          [WEAK]
-                EXPORT  FLEXRAY_IRQHandler        [WEAK]
-                EXPORT  CAN_IRQHandler            [WEAK]
-                EXPORT  LIN_IRQHandler            [WEAK]
-                EXPORT  I2C_IRQHandler            [WEAK]
-                EXPORT  CPU_CLCD_IRQHandler       [WEAK]
-                EXPORT  SPI_IRQHandler            [WEAK]
-
-WDT_IRQHandler
-RTC_IRQHandler
-TIM0_IRQHandler
-TIM2_IRQHandler
-MCIA_IRQHandler
-MCIB_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-UART3_IRQHandler
-UART4_IRQHandler
-AACI_IRQHandler
-CLCD_IRQHandler
-ENET_IRQHandler
-USBDC_IRQHandler
-USBHC_IRQHandler
-CHLCD_IRQHandler
-FLEXRAY_IRQHandler
-CAN_IRQHandler
-LIN_IRQHandler
-I2C_IRQHandler
-CPU_CLCD_IRQHandler
-SPI_IRQHandler
-                B       .
-
-                ENDP
-
-
-                ALIGN
-
-
-; User Initial Stack & Heap
-
-                IF      :DEF:__MICROLIB
-
-                EXPORT  __initial_sp
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-
-                ELSE
-
-                IMPORT  __use_two_region_memory
-                EXPORT  __user_initial_stackheap
-
-__user_initial_stackheap PROC
-                LDR     R0, =  Heap_Mem
-                LDR     R1, =(Stack_Mem + Stack_Size)
-                LDR     R2, = (Heap_Mem +  Heap_Size)
-                LDR     R3, = Stack_Mem
-                BX      LR
-                ENDP
-
-                ALIGN
-
-                ENDIF
-
-
-                END

CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM3/system_ARMCM3.c

@@ -1,68 +0,0 @@
-/**************************************************************************//**
- * @file     system_ARMCM3.c
- * @brief    CMSIS Device System Source File for
- *           ARMCM3 Device Series
- * @version  V5.00
- * @date     08. April 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "ARMCM3.h"
-
-/*----------------------------------------------------------------------------
-  Define clocks
- *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000U)      /* Oscillator frequency */
-
-#define  SYSTEM_CLOCK    (5 * XTAL)
-
-
-/*----------------------------------------------------------------------------
-  Externals
- *----------------------------------------------------------------------------*/
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1)
-  extern uint32_t __Vectors;
-#endif
-
-/*----------------------------------------------------------------------------
-  System Core Clock Variable
- *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
-
-
-/*----------------------------------------------------------------------------
-  System Core Clock update function
- *----------------------------------------------------------------------------*/
-void SystemCoreClockUpdate (void)
-{
-  SystemCoreClock = SYSTEM_CLOCK;
-}
-
-/*----------------------------------------------------------------------------
-  System initialization function
- *----------------------------------------------------------------------------*/
-void SystemInit (void)
-{
-
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1)
-  SCB->VTOR = (uint32_t) &__Vectors;
-#endif
-
-  SystemCoreClock = SYSTEM_CLOCK;
-}

CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM4_FP/startup_ARMCM4.s

@@ -1,262 +0,0 @@
-;/**************************************************************************//**
-; * @file     startup_ARMCM4.s
-; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM4 Device Series
-; * @version  V5.00
-; * @date     02. March 2016
-; ******************************************************************************/
-;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
-; *
-; * SPDX-License-Identifier: Apache-2.0
-; *
-; * Licensed under the Apache License, Version 2.0 (the License); you may
-; * not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; */
-
-;/*
-;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
-
-
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000C00
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
-                DCD     RTC_IRQHandler            ;  1:  Real Time Clock
-                DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
-                DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
-                DCD     MCIA_IRQHandler           ;  4:  MCIa
-                DCD     MCIB_IRQHandler           ;  5:  MCIb
-                DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
-                DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
-                DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
-                DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
-                DCD     AACI_IRQHandler           ; 10: AACI / AC97
-                DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
-                DCD     ENET_IRQHandler           ; 12: Ethernet
-                DCD     USBDC_IRQHandler          ; 13: USB Device
-                DCD     USBHC_IRQHandler          ; 14: USB Host Controller
-                DCD     CHLCD_IRQHandler          ; 15: Character LCD
-                DCD     FLEXRAY_IRQHandler        ; 16: Flexray
-                DCD     CAN_IRQHandler            ; 17: CAN
-                DCD     LIN_IRQHandler            ; 18: LIN
-                DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
-                DCD     0                         ; 20: Reserved
-                DCD     0                         ; 21: Reserved
-                DCD     0                         ; 22: Reserved
-                DCD     0                         ; 23: Reserved
-                DCD     0                         ; 24: Reserved
-                DCD     0                         ; 25: Reserved
-                DCD     0                         ; 26: Reserved
-                DCD     0                         ; 27: Reserved
-                DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
-                DCD     0                         ; 29: Reserved - CPU FPGA
-                DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
-                DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
-__Vectors_End
-
-__Vectors_Size  EQU     __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-
-; Reset Handler
-
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  SystemInit
-                IMPORT  __main
-                LDR     R0, =SystemInit
-                BLX     R0
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler               [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler         [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler          [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler        [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler          [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WDT_IRQHandler            [WEAK]
-                EXPORT  RTC_IRQHandler            [WEAK]
-                EXPORT  TIM0_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler           [WEAK]
-                EXPORT  MCIA_IRQHandler           [WEAK]
-                EXPORT  MCIB_IRQHandler           [WEAK]
-                EXPORT  UART0_IRQHandler          [WEAK]
-                EXPORT  UART1_IRQHandler          [WEAK]
-                EXPORT  UART2_IRQHandler          [WEAK]
-                EXPORT  UART3_IRQHandler          [WEAK]
-                EXPORT  UART4_IRQHandler          [WEAK]
-                EXPORT  AACI_IRQHandler           [WEAK]
-                EXPORT  CLCD_IRQHandler           [WEAK]
-                EXPORT  ENET_IRQHandler           [WEAK]
-                EXPORT  USBDC_IRQHandler          [WEAK]
-                EXPORT  USBHC_IRQHandler          [WEAK]
-                EXPORT  CHLCD_IRQHandler          [WEAK]
-                EXPORT  FLEXRAY_IRQHandler        [WEAK]
-                EXPORT  CAN_IRQHandler            [WEAK]
-                EXPORT  LIN_IRQHandler            [WEAK]
-                EXPORT  I2C_IRQHandler            [WEAK]
-                EXPORT  CPU_CLCD_IRQHandler       [WEAK]
-                EXPORT  SPI_IRQHandler            [WEAK]
-
-WDT_IRQHandler
-RTC_IRQHandler
-TIM0_IRQHandler
-TIM2_IRQHandler
-MCIA_IRQHandler
-MCIB_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-UART3_IRQHandler
-UART4_IRQHandler
-AACI_IRQHandler
-CLCD_IRQHandler
-ENET_IRQHandler
-USBDC_IRQHandler
-USBHC_IRQHandler
-CHLCD_IRQHandler
-FLEXRAY_IRQHandler
-CAN_IRQHandler
-LIN_IRQHandler
-I2C_IRQHandler
-CPU_CLCD_IRQHandler
-SPI_IRQHandler
-                B       .
-
-                ENDP
-
-
-                ALIGN
-
-
-; User Initial Stack & Heap
-
-                IF      :DEF:__MICROLIB
-
-                EXPORT  __initial_sp
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-
-                ELSE
-
-                IMPORT  __use_two_region_memory
-                EXPORT  __user_initial_stackheap
-
-__user_initial_stackheap PROC
-                LDR     R0, =  Heap_Mem
-                LDR     R1, =(Stack_Mem + Stack_Size)
-                LDR     R2, = (Heap_Mem +  Heap_Size)
-                LDR     R3, = Stack_Mem
-                BX      LR
-                ENDP
-
-                ALIGN
-
-                ENDIF
-
-
-                END

CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM4_FP/system_ARMCM4.c

@@ -1,83 +0,0 @@
-/**************************************************************************//**
- * @file     system_ARMCM4.c
- * @brief    CMSIS Device System Source File for
- *           ARMCM4 Device Series
- * @version  V5.00
- * @date     08. April 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if defined (ARMCM4)
-  #include "ARMCM4.h"
-#elif defined (ARMCM4_FP)
-  #include "ARMCM4_FP.h"
-#else
-  #error device not specified!
-#endif
-
-/*----------------------------------------------------------------------------
-  Define clocks
- *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000U)      /* Oscillator frequency */
-
-#define  SYSTEM_CLOCK    (5 * XTAL)
-
-
-/*----------------------------------------------------------------------------
-  Externals
- *----------------------------------------------------------------------------*/
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1)
-  extern uint32_t __Vectors;
-#endif
-
-/*----------------------------------------------------------------------------
-  System Core Clock Variable
- *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
-
-
-/*----------------------------------------------------------------------------
-  System Core Clock update function
- *----------------------------------------------------------------------------*/
-void SystemCoreClockUpdate (void)
-{
-  SystemCoreClock = SYSTEM_CLOCK;
-}
-
-/*----------------------------------------------------------------------------
-  System initialization function
- *----------------------------------------------------------------------------*/
-void SystemInit (void)
-{
-
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1)
-  SCB->VTOR = (uint32_t) &__Vectors;
-#endif
-
-#if defined (__FPU_USED) && (__FPU_USED == 1)
-  SCB->CPACR |= ((3U << 10*2) |           /* set CP10 Full Access */
-                 (3U << 11*2)  );         /* set CP11 Full Access */
-#endif
-
-#ifdef UNALIGNED_SUPPORT_DISABLE
-  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
-#endif
-
-  SystemCoreClock = SYSTEM_CLOCK;
-}

CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/gcc_arm.ld

@@ -1,196 +0,0 @@
-/* Linker script to configure memory regions. */
-MEMORY
-{
-  FLASH (rx)  : ORIGIN = 0x00000000, LENGTH = 512K
-  RAM   (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
-}
-
-/* Library configurations */
-GROUP(libgcc.a libc.a libm.a libnosys.a)
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- *   Reset_Handler : Entry of reset handler
- *
- * It defines following symbols, which code can use without definition:
- *   __exidx_start
- *   __exidx_end
- *   __copy_table_start__
- *   __copy_table_end__
- *   __zero_table_start__
- *   __zero_table_end__
- *   __etext
- *   __data_start__
- *   __preinit_array_start
- *   __preinit_array_end
- *   __init_array_start
- *   __init_array_end
- *   __fini_array_start
- *   __fini_array_end
- *   __data_end__
- *   __bss_start__
- *   __bss_end__
- *   __end__
- *   end
- *   __HeapBase
- *   __HeapLimit
- *   __StackLimit
- *   __StackTop
- *   __stack
- *   __Vectors_End
- *   __Vectors_Size
- */
-ENTRY(Reset_Handler)
-
-SECTIONS
-{
-	.text :
-	{
-		KEEP(*(.vectors))
-		__Vectors_End = .;
-		__Vectors_Size = __Vectors_End - __Vectors;
-		__end__ = .;
-
-		*(.text*)
-
-		KEEP(*(.init))
-		KEEP(*(.fini))
-
-		/* .ctors */
-		*crtbegin.o(.ctors)
-		*crtbegin?.o(.ctors)
-		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
-		*(SORT(.ctors.*))
-		*(.ctors)
-
-		/* .dtors */
- 		*crtbegin.o(.dtors)
- 		*crtbegin?.o(.dtors)
- 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
- 		*(SORT(.dtors.*))
- 		*(.dtors)
-
-		*(.rodata*)
-
-		KEEP(*(.eh_frame*))
-	} > FLASH
-
-	.ARM.extab :
-	{
-		*(.ARM.extab* .gnu.linkonce.armextab.*)
-	} > FLASH
-
-	__exidx_start = .;
-	.ARM.exidx :
-	{
-		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
-	} > FLASH
-	__exidx_end = .;
-
-	/* To copy multiple ROM to RAM sections,
-	 * uncomment .copy.table section and,
-	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
-	/*
-	.copy.table :
-	{
-		. = ALIGN(4);
-		__copy_table_start__ = .;
-		LONG (__etext)
-		LONG (__data_start__)
-		LONG (__data_end__ - __data_start__)
-		LONG (__etext2)
-		LONG (__data2_start__)
-		LONG (__data2_end__ - __data2_start__)
-		__copy_table_end__ = .;
-	} > FLASH
-	*/
-
-	/* To clear multiple BSS sections,
-	 * uncomment .zero.table section and,
-	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
-	/*
-	.zero.table :
-	{
-		. = ALIGN(4);
-		__zero_table_start__ = .;
-		LONG (__bss_start__)
-		LONG (__bss_end__ - __bss_start__)
-		LONG (__bss2_start__)
-		LONG (__bss2_end__ - __bss2_start__)
-		__zero_table_end__ = .;
-	} > FLASH
-	*/
-
-	__etext = .;
-
-	.data : AT (__etext)
-	{
-		__data_start__ = .;
-		*(vtable)
-		*(.data*)
-
-		. = ALIGN(4);
-		/* preinit data */
-		PROVIDE_HIDDEN (__preinit_array_start = .);
-		KEEP(*(.preinit_array))
-		PROVIDE_HIDDEN (__preinit_array_end = .);
-
-		. = ALIGN(4);
-		/* init data */
-		PROVIDE_HIDDEN (__init_array_start = .);
-		KEEP(*(SORT(.init_array.*)))
-		KEEP(*(.init_array))
-		PROVIDE_HIDDEN (__init_array_end = .);
-
-
-		. = ALIGN(4);
-		/* finit data */
-		PROVIDE_HIDDEN (__fini_array_start = .);
-		KEEP(*(SORT(.fini_array.*)))
-		KEEP(*(.fini_array))
-		PROVIDE_HIDDEN (__fini_array_end = .);
-
-		KEEP(*(.jcr*))
-		. = ALIGN(4);
-		/* All data end */
-		__data_end__ = .;
-
-	} > RAM
-
-	.bss :
-	{
-		. = ALIGN(4);
-		__bss_start__ = .;
-		*(.bss*)
-		*(COMMON)
-		. = ALIGN(4);
-		__bss_end__ = .;
-	} > RAM
-
-	.heap (COPY):
-	{
-		__HeapBase = .;
-		__end__ = .;
-		end = __end__;
-		KEEP(*(.heap*))
-		__HeapLimit = .;
-	} > RAM
-
-	/* .stack_dummy section doesn't contains any symbols. It is only
-	 * used for linker to calculate size of stack sections, and assign
-	 * values to stack symbols later */
-	.stack_dummy (COPY):
-	{
-		KEEP(*(.stack*))
-	} > RAM
-
-	/* Set stack top to end of RAM, and stack limit move down by
-	 * size of stack_dummy section */
-	__StackTop = ORIGIN(RAM) + LENGTH(RAM);
-	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
-	PROVIDE(__stack = __StackTop);
-
-	/* Check if data + heap + stack exceeds RAM limit */
-	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
-}

CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/startup_ARMCM7.c

@@ -1,295 +0,0 @@
-/**************************************************************************//**
- * @file     startup_ARMCM7.s
- * @brief    CMSIS Core Device Startup File for
- *           ARMCM7 Device Series
- * @version  V5.00
- * @date     26. April 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include <stdint.h>
-
-
-/*----------------------------------------------------------------------------
-  Linker generated Symbols
- *----------------------------------------------------------------------------*/
-extern uint32_t __etext;
-extern uint32_t __data_start__;
-extern uint32_t __data_end__;
-extern uint32_t __copy_table_start__;
-extern uint32_t __copy_table_end__;
-extern uint32_t __zero_table_start__;
-extern uint32_t __zero_table_end__;
-extern uint32_t __bss_start__;
-extern uint32_t __bss_end__;
-extern uint32_t __StackTop;
-
-/*----------------------------------------------------------------------------
-  Exception / Interrupt Handler Function Prototype
- *----------------------------------------------------------------------------*/
-typedef void( *pFunc )( void );
-
-
-/*----------------------------------------------------------------------------
-  External References
- *----------------------------------------------------------------------------*/
-#ifndef __START
-extern void  _start(void) __attribute__((noreturn));    /* PreeMain (C library entry point) */
-#else
-extern int  __START(void) __attribute__((noreturn));    /* main entry point */
-#endif
-
-#ifndef __NO_SYSTEM_INIT
-extern void SystemInit (void);            /* CMSIS System Initialization      */
-#endif
-
-
-/*----------------------------------------------------------------------------
-  Internal References
- *----------------------------------------------------------------------------*/
-void Default_Handler(void);                          /* Default empty handler */
-void Reset_Handler(void);                            /* Reset Handler */
-
-
-/*----------------------------------------------------------------------------
-  User Initial Stack & Heap
- *----------------------------------------------------------------------------*/
-#ifndef __STACK_SIZE
-  #define	__STACK_SIZE  0x00000400
-#endif
-static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack")));
-
-#ifndef __HEAP_SIZE
-  #define	__HEAP_SIZE   0x00000C00
-#endif
-#if __HEAP_SIZE > 0
-static uint8_t heap[__HEAP_SIZE]   __attribute__ ((aligned(8), used, section(".heap")));
-#endif
-
-
-/*----------------------------------------------------------------------------
-  Exception / Interrupt Handler
- *----------------------------------------------------------------------------*/
-/* Cortex-M7 Processor Exceptions */
-void NMI_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
-void HardFault_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
-void MemManage_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
-void BusFault_Handler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UsageFault_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
-void SVC_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
-void DebugMon_Handler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void PendSV_Handler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void SysTick_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
-
-/* ARMCM7 Specific Interrupts */
-void WDT_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void RTC_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM0_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM2_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIA_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIB_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART0_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART1_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART2_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART4_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void AACI_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void CLCD_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void ENET_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBDC_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBHC_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void CHLCD_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void FLEXRAY_IRQHandler  (void) __attribute__ ((weak, alias("Default_Handler")));
-void CAN_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void LIN_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void I2C_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void CPU_CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART3_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void SPI_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-
-
-/*----------------------------------------------------------------------------
-  Exception / Interrupt Vector table
- *----------------------------------------------------------------------------*/
-const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = {
-  /* Cortex-M7 Exceptions Handler */
-  (pFunc)((uint32_t)&__StackTop),           /*      Initial Stack Pointer     */
-  Reset_Handler,                            /*      Reset Handler             */
-  NMI_Handler,                              /*      NMI Handler               */
-  HardFault_Handler,                        /*      Hard Fault Handler        */
-  MemManage_Handler,                        /*      MPU Fault Handler         */
-  BusFault_Handler,                         /*      Bus Fault Handler         */
-  UsageFault_Handler,                       /*      Usage Fault Handler       */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  SVC_Handler,                              /*      SVCall Handler            */
-  DebugMon_Handler,                         /*      Debug Monitor Handler     */
-  0,                                        /*      Reserved                  */
-  PendSV_Handler,                           /*      PendSV Handler            */
-  SysTick_Handler,                          /*      SysTick Handler           */
-
-  /* External interrupts */
-  WDT_IRQHandler,                           /*  0:  Watchdog Timer            */
-  RTC_IRQHandler,                           /*  1:  Real Time Clock           */
-  TIM0_IRQHandler,                          /*  2:  Timer0 / Timer1           */
-  TIM2_IRQHandler,                          /*  3:  Timer2 / Timer3           */
-  MCIA_IRQHandler,                          /*  4:  MCIa                      */
-  MCIB_IRQHandler,                          /*  5:  MCIb                      */
-  UART0_IRQHandler,                         /*  6:  UART0 - DUT FPGA          */
-  UART1_IRQHandler,                         /*  7:  UART1 - DUT FPGA          */
-  UART2_IRQHandler,                         /*  8:  UART2 - DUT FPGA          */
-  UART4_IRQHandler,                         /*  9:  UART4 - not connected     */
-  AACI_IRQHandler,                          /* 10: AACI / AC97                */
-  CLCD_IRQHandler,                          /* 11: CLCD Combined Interrupt    */
-  ENET_IRQHandler,                          /* 12: Ethernet                   */
-  USBDC_IRQHandler,                         /* 13: USB Device                 */
-  USBHC_IRQHandler,                         /* 14: USB Host Controller        */
-  CHLCD_IRQHandler,                         /* 15: Character LCD              */
-  FLEXRAY_IRQHandler,                       /* 16: Flexray                    */
-  CAN_IRQHandler,                           /* 17: CAN                        */
-  LIN_IRQHandler,                           /* 18: LIN                        */
-  I2C_IRQHandler,                           /* 19: I2C ADC/DAC                */
-  0,                                        /* 20: Reserved                   */
-  0,                                        /* 21: Reserved                   */
-  0,                                        /* 22: Reserved                   */
-  0,                                        /* 23: Reserved                   */
-  0,                                        /* 24: Reserved                   */
-  0,                                        /* 25: Reserved                   */
-  0,                                        /* 26: Reserved                   */
-  0,                                        /* 27: Reserved                   */
-  CPU_CLCD_IRQHandler,                      /* 28: Reserved - CPU FPGA CLCD   */
-  0,                                        /* 29: Reserved - CPU FPGA        */
-  UART3_IRQHandler,                         /* 30: UART3    - CPU FPGA        */
-  SPI_IRQHandler                            /* 31: SPI Touchscreen - CPU FPGA */
-};
-
-
-/*----------------------------------------------------------------------------
-  Reset Handler called on controller reset
- *----------------------------------------------------------------------------*/
-void Reset_Handler(void) {
-  uint32_t *pSrc, *pDest;
-  uint32_t *pTable __attribute__((unused));
-
-/*  Firstly it copies data from read only memory to RAM. There are two schemes
- *  to copy. One can copy more than one sections. Another can only copy
- *  one section.  The former scheme needs more instructions and read-only
- *  data to implement than the latter.
- *  Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.  */
-
-#ifdef __STARTUP_COPY_MULTIPLE
-/*  Multiple sections scheme.
- *
- *  Between symbol address __copy_table_start__ and __copy_table_end__,
- *  there are array of triplets, each of which specify:
- *    offset 0: LMA of start of a section to copy from
- *    offset 4: VMA of start of a section to copy to
- *    offset 8: size of the section to copy. Must be multiply of 4
- *
- *  All addresses must be aligned to 4 bytes boundary.
- */
-  pTable = &__copy_table_start__;
-
-  for (; pTable < &__copy_table_end__; pTable = pTable + 3) {
-		pSrc  = (uint32_t*)*(pTable + 0);
-		pDest = (uint32_t*)*(pTable + 1);
-		for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
-      *pDest++ = *pSrc++;
-		}
-	}
-#else
-/*  Single section scheme.
- *
- *  The ranges of copy from/to are specified by following symbols
- *    __etext: LMA of start of the section to copy from. Usually end of text
- *    __data_start__: VMA of start of the section to copy to
- *    __data_end__: VMA of end of the section to copy to
- *
- *  All addresses must be aligned to 4 bytes boundary.
- */
-  pSrc  = &__etext;
-  pDest = &__data_start__;
-
-  for ( ; pDest < &__data_end__ ; ) {
-    *pDest++ = *pSrc++;
-  }
-#endif /*__STARTUP_COPY_MULTIPLE */
-
-/*  This part of work usually is done in C library startup code. Otherwise,
- *  define this macro to enable it in this startup.
- *
- *  There are two schemes too. One can clear multiple BSS sections. Another
- *  can only clear one section. The former is more size expensive than the
- *  latter.
- *
- *  Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- *  Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
- */
-#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/*  Multiple sections scheme.
- *
- *  Between symbol address __copy_table_start__ and __copy_table_end__,
- *  there are array of tuples specifying:
- *    offset 0: Start of a BSS section
- *    offset 4: Size of this BSS section. Must be multiply of 4
- */
-  pTable = &__zero_table_start__;
-
-  for (; pTable < &__zero_table_end__; pTable = pTable + 2) {
-		pDest = (uint32_t*)*(pTable + 0);
-		for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
-      *pDest++ = 0;
-		}
-	}
-#elif defined (__STARTUP_CLEAR_BSS)
-/*  Single BSS section scheme.
- *
- *  The BSS section is specified by following symbols
- *    __bss_start__: start of the BSS section.
- *    __bss_end__: end of the BSS section.
- *
- *  Both addresses must be aligned to 4 bytes boundary.
- */
-  pDest = &__bss_start__;
-
-  for ( ; pDest < &__bss_end__ ; ) {
-    *pDest++ = 0UL;
-  }
-#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-
-#ifndef __NO_SYSTEM_INIT
-	SystemInit();
-#endif
-
-#ifndef __START
-#define __START _start
-#endif
-	__START();
-
-}
-
-
-/*----------------------------------------------------------------------------
-  Default Handler for Exceptions / Interrupts
- *----------------------------------------------------------------------------*/
-void Default_Handler(void) {
-
-	while(1);
-}

CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/startup_ARMCM7.s

@@ -1,262 +0,0 @@
-;/**************************************************************************//**
-; * @file     startup_ARMCM7.s
-; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM7 Device Series
-; * @version  V5.00
-; * @date     02. March 2016
-; ******************************************************************************/
-;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
-; *
-; * SPDX-License-Identifier: Apache-2.0
-; *
-; * Licensed under the Apache License, Version 2.0 (the License); you may
-; * not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; */
-
-;/*
-;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
-
-
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000C00
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
-                DCD     RTC_IRQHandler            ;  1:  Real Time Clock
-                DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
-                DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
-                DCD     MCIA_IRQHandler           ;  4:  MCIa
-                DCD     MCIB_IRQHandler           ;  5:  MCIb
-                DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
-                DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
-                DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
-                DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
-                DCD     AACI_IRQHandler           ; 10: AACI / AC97
-                DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
-                DCD     ENET_IRQHandler           ; 12: Ethernet
-                DCD     USBDC_IRQHandler          ; 13: USB Device
-                DCD     USBHC_IRQHandler          ; 14: USB Host Controller
-                DCD     CHLCD_IRQHandler          ; 15: Character LCD
-                DCD     FLEXRAY_IRQHandler        ; 16: Flexray
-                DCD     CAN_IRQHandler            ; 17: CAN
-                DCD     LIN_IRQHandler            ; 18: LIN
-                DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
-                DCD     0                         ; 20: Reserved
-                DCD     0                         ; 21: Reserved
-                DCD     0                         ; 22: Reserved
-                DCD     0                         ; 23: Reserved
-                DCD     0                         ; 24: Reserved
-                DCD     0                         ; 25: Reserved
-                DCD     0                         ; 26: Reserved
-                DCD     0                         ; 27: Reserved
-                DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
-                DCD     0                         ; 29: Reserved - CPU FPGA
-                DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
-                DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
-__Vectors_End
-
-__Vectors_Size  EQU     __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-
-; Reset Handler
-
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  SystemInit
-                IMPORT  __main
-                LDR     R0, =SystemInit
-                BLX     R0
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler               [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler         [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler          [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler        [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler          [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WDT_IRQHandler            [WEAK]
-                EXPORT  RTC_IRQHandler            [WEAK]
-                EXPORT  TIM0_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler           [WEAK]
-                EXPORT  MCIA_IRQHandler           [WEAK]
-                EXPORT  MCIB_IRQHandler           [WEAK]
-                EXPORT  UART0_IRQHandler          [WEAK]
-                EXPORT  UART1_IRQHandler          [WEAK]
-                EXPORT  UART2_IRQHandler          [WEAK]
-                EXPORT  UART3_IRQHandler          [WEAK]
-                EXPORT  UART4_IRQHandler          [WEAK]
-                EXPORT  AACI_IRQHandler           [WEAK]
-                EXPORT  CLCD_IRQHandler           [WEAK]
-                EXPORT  ENET_IRQHandler           [WEAK]
-                EXPORT  USBDC_IRQHandler          [WEAK]
-                EXPORT  USBHC_IRQHandler          [WEAK]
-                EXPORT  CHLCD_IRQHandler          [WEAK]
-                EXPORT  FLEXRAY_IRQHandler        [WEAK]
-                EXPORT  CAN_IRQHandler            [WEAK]
-                EXPORT  LIN_IRQHandler            [WEAK]
-                EXPORT  I2C_IRQHandler            [WEAK]
-                EXPORT  CPU_CLCD_IRQHandler       [WEAK]
-                EXPORT  SPI_IRQHandler            [WEAK]
-
-WDT_IRQHandler
-RTC_IRQHandler
-TIM0_IRQHandler
-TIM2_IRQHandler
-MCIA_IRQHandler
-MCIB_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-UART3_IRQHandler
-UART4_IRQHandler
-AACI_IRQHandler
-CLCD_IRQHandler
-ENET_IRQHandler
-USBDC_IRQHandler
-USBHC_IRQHandler
-CHLCD_IRQHandler
-FLEXRAY_IRQHandler
-CAN_IRQHandler
-LIN_IRQHandler
-I2C_IRQHandler
-CPU_CLCD_IRQHandler
-SPI_IRQHandler
-                B       .
-
-                ENDP
-
-
-                ALIGN
-
-
-; User Initial Stack & Heap
-
-                IF      :DEF:__MICROLIB
-
-                EXPORT  __initial_sp
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-
-                ELSE
-
-                IMPORT  __use_two_region_memory
-                EXPORT  __user_initial_stackheap
-
-__user_initial_stackheap PROC
-                LDR     R0, =  Heap_Mem
-                LDR     R1, =(Stack_Mem + Stack_Size)
-                LDR     R2, = (Heap_Mem +  Heap_Size)
-                LDR     R3, = Stack_Mem
-                BX      LR
-                ENDP
-
-                ALIGN
-
-                ENDIF
-
-
-                END

CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/system_ARMCM7.c

@@ -1,85 +0,0 @@
-/**************************************************************************//**
- * @file     system_ARMCM7.c
- * @brief    CMSIS Device System Source File for
- *           ARMCM7 Device Series
- * @version  V5.00
- * @date     08. April 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if defined (ARMCM7)
-  #include "ARMCM7.h"
-#elif defined (ARMCM7_SP)
-  #include "ARMCM7_SP.h"
-#elif defined (ARMCM7_DP)
-  #include "ARMCM7_DP.h"
-#else
-  #error device not specified!
-#endif
-
-/*----------------------------------------------------------------------------
-  Define clocks
- *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000U)      /* Oscillator frequency */
-
-#define  SYSTEM_CLOCK    (5 * XTAL)
-
-
-/*----------------------------------------------------------------------------
-  Externals
- *----------------------------------------------------------------------------*/
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1)
-  extern uint32_t __Vectors;
-#endif
-
-/*----------------------------------------------------------------------------
-  System Core Clock Variable
- *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
-
-
-/*----------------------------------------------------------------------------
-  System Core Clock update function
- *----------------------------------------------------------------------------*/
-void SystemCoreClockUpdate (void)
-{
-  SystemCoreClock = SYSTEM_CLOCK;
-}
-
-/*----------------------------------------------------------------------------
-  System initialization function
- *----------------------------------------------------------------------------*/
-void SystemInit (void)
-{
-
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1)
-  SCB->VTOR = (uint32_t) &__Vectors;
-#endif
-
-#if defined (__FPU_USED) && (__FPU_USED == 1)
-  SCB->CPACR |= ((3U << 10*2) |           /* set CP10 Full Access */
-                 (3U << 11*2)  );         /* set CP11 Full Access */
-#endif
-
-#ifdef UNALIGNED_SUPPORT_DISABLE
-  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
-#endif
-
-  SystemCoreClock = SYSTEM_CLOCK;
-}

CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM0/RTE_Components.h

@@ -1,24 +0,0 @@
-
-/*
- * Auto generated Run-Time-Environment Component Configuration File
- *      *** Do not modify ! ***
- *
- * Project: 'arm_nnexamples_gru' 
- * Target:  'ARMCM0' 
- */
-
-#ifndef RTE_COMPONENTS_H
-#define RTE_COMPONENTS_H
-
-
-/*
- * Define the Device Header File: 
- */
-#define CMSIS_device_header "ARMCM0.h"
-
-#define RTE_Compiler_EventRecorder
-          #define RTE_Compiler_EventRecorder_DAP
-#define RTE_Compiler_IO_STDOUT          /* Compiler I/O: STDOUT */
-          #define RTE_Compiler_IO_STDOUT_EVR      /* Compiler I/O: STDOUT EVR */
-
-#endif /* RTE_COMPONENTS_H */

CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM3/RTE_Components.h

@@ -1,22 +0,0 @@
-
-/*
- * Auto generated Run-Time-Environment Component Configuration File
- *      *** Do not modify ! ***
- *
- * Project: 'arm_nnexamples_gru' 
- * Target:  'ARMCM3' 
- */
-
-#ifndef RTE_COMPONENTS_H
-#define RTE_COMPONENTS_H
-
-
-/*
- * Define the Device Header File: 
- */
-#define CMSIS_device_header "ARMCM3.h"
-
-#define RTE_Compiler_IO_STDOUT          /* Compiler I/O: STDOUT */
-          #define RTE_Compiler_IO_STDOUT_ITM      /* Compiler I/O: STDOUT ITM */
-
-#endif /* RTE_COMPONENTS_H */

CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM4_FP/RTE_Components.h

@@ -1,22 +0,0 @@
-
-/*
- * Auto generated Run-Time-Environment Component Configuration File
- *      *** Do not modify ! ***
- *
- * Project: 'arm_nnexamples_gru' 
- * Target:  'ARMCM4_FP' 
- */
-
-#ifndef RTE_COMPONENTS_H
-#define RTE_COMPONENTS_H
-
-
-/*
- * Define the Device Header File: 
- */
-#define CMSIS_device_header "ARMCM4_FP.h"
-
-#define RTE_Compiler_IO_STDOUT          /* Compiler I/O: STDOUT */
-          #define RTE_Compiler_IO_STDOUT_ITM      /* Compiler I/O: STDOUT ITM */
-
-#endif /* RTE_COMPONENTS_H */

CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM7_SP/RTE_Components.h

@@ -1,22 +0,0 @@
-
-/*
- * Auto generated Run-Time-Environment Component Configuration File
- *      *** Do not modify ! ***
- *
- * Project: 'arm_nnexamples_gru' 
- * Target:  'ARMCM7_SP' 
- */
-
-#ifndef RTE_COMPONENTS_H
-#define RTE_COMPONENTS_H
-
-
-/*
- * Define the Device Header File: 
- */
-#define CMSIS_device_header "ARMCM7_SP.h"
-
-#define RTE_Compiler_IO_STDOUT          /* Compiler I/O: STDOUT */
-          #define RTE_Compiler_IO_STDOUT_ITM      /* Compiler I/O: STDOUT ITM */
-
-#endif /* RTE_COMPONENTS_H */

CMSIS/NN/Examples/ARM/arm_nn_examples/gru/arm_nnexamples_gru.cpp

@@ -1,221 +0,0 @@
-/* ----------------------------------------------------------------------
-* Copyright (C) 2010-2018 Arm Limited. All rights reserved.
-*
-*
-* Project:       CMSIS NN Library
-* Title:         arm_nnexamples_gru.cpp
-*
-* Description:   Gated Recurrent Unit Example
-*
-* Target Processor: Cortex-M4/Cortex-M7
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the
-*     distribution.
-*   - Neither the name of Arm LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.
-* -------------------------------------------------------------------- */
-
-/**
- * @ingroup groupExamples
- */
-
-/**
- * @defgroup GRUExample Gated Recurrent Unit Example
- *
- * \par Description:
- * \par
- * Demonstrates a gated recurrent unit (GRU) example with the use of fully-connected,
- * Tanh/Sigmoid activation functions.
- *
- * \par Model definition:
- * \par
- * GRU is a type of recurrent neural network (RNN). It contains two sigmoid gates and one hidden
- * state. 
- * \par
- * The computation can be summarized as:
- * <pre>z[t] = sigmoid( W_z &sdot; {h[t-1],x[t]} )
- * r[t] = sigmoid( W_r &sdot; {h[t-1],x[t]} ) 
- * n[t] = tanh( W_n &sdot; [r[t] &times; {h[t-1], x[t]} ) 
- * h[t] = (1 - z[t]) &times; h[t-1] + z[t] &times; n[t] </pre>
- * \image html GRU.gif "Gate Recurrent Unit Diagram"
- *
- * \par Variables Description:
- * \par
- * \li \c update_gate_weights, \c reset_gate_weights, \c hidden_state_weights are weights corresponding to update gate (W_z), reset gate (W_r), and hidden state (W_n).
- * \li \c update_gate_bias, \c reset_gate_bias, \c hidden_state_bias are layer bias arrays
- * \li \c test_input1, \c test_input2, \c test_history are the inputs and initial history
- *
- * \par
- * The buffer is allocated as:
- * \par
- * | reset | input | history | update | hidden_state |
- * \par
- * In this way, the concatination is automatically done since (reset, input) and (input, history)
- * are physically concatinated in memory.
- * \par
- *  The ordering of the weight matrix should be adjusted accordingly.
- *
-  *
- * 
- * \par CMSIS DSP Software Library Functions Used:
- * \par
- * - arm_fully_connected_mat_q7_vec_q15_opt()
- * - arm_nn_activations_direct_q15()
- * - arm_mult_q15()
- * - arm_offset_q15()
- * - arm_sub_q15()
- * - arm_copy_q15()
- *
- * <b> Refer  </b>
- * \link arm_nnexamples_gru.cpp \endlink
- *
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <math.h>
-#include "arm_nnexamples_gru_test_data.h"
-#include "arm_math.h"
-#include "arm_nnfunctions.h"
-
-#ifdef _RTE_
-#include "RTE_Components.h"
-#ifdef RTE_Compiler_EventRecorder
-#include "EventRecorder.h"
-#endif
-#endif
-
-#define DIM_HISTORY 32
-#define DIM_INPUT 32
-#define DIM_VEC 64
-
-#define USE_X4
-
-#ifndef USE_X4
-static q7_t update_gate_weights[DIM_VEC * DIM_HISTORY] = UPDATE_GATE_WEIGHT_X2;
-static q7_t reset_gate_weights[DIM_VEC * DIM_HISTORY] = RESET_GATE_WEIGHT_X2;
-static q7_t hidden_state_weights[DIM_VEC * DIM_HISTORY] = HIDDEN_STATE_WEIGHT_X2;
-#else
-static q7_t update_gate_weights[DIM_VEC * DIM_HISTORY] = UPDATE_GATE_WEIGHT_X4;
-static q7_t reset_gate_weights[DIM_VEC * DIM_HISTORY] = RESET_GATE_WEIGHT_X4;
-static q7_t hidden_state_weights[DIM_VEC * DIM_HISTORY] = HIDDEN_STATE_WEIGHT_X4;
-#endif
-
-static q7_t update_gate_bias[DIM_HISTORY] = UPDATE_GATE_BIAS;
-static q7_t reset_gate_bias[DIM_HISTORY] = RESET_GATE_BIAS;
-static q7_t hidden_state_bias[DIM_HISTORY] = HIDDEN_STATE_BIAS;
-
-static q15_t test_input1[DIM_INPUT] = INPUT_DATA1;
-static q15_t test_input2[DIM_INPUT] = INPUT_DATA2;
-static q15_t test_history[DIM_HISTORY] = HISTORY_DATA;
-
-q15_t     scratch_buffer[DIM_HISTORY * 4 + DIM_INPUT];
-
-void gru_example(q15_t * scratch_input, uint16_t input_size, uint16_t history_size,
-                 q7_t * weights_update, q7_t * weights_reset, q7_t * weights_hidden_state,
-                 q7_t * bias_update, q7_t * bias_reset, q7_t * bias_hidden_state)
-{
-  q15_t    *reset = scratch_input;
-  q15_t    *input = scratch_input + history_size;
-  q15_t    *history = scratch_input + history_size + input_size;
-  q15_t    *update = scratch_input + 2 * history_size + input_size;
-  q15_t    *hidden_state = scratch_input + 3 * history_size + input_size;
-
-  // reset gate calculation
-  // the range of the output can be adjusted with bias_shift and output_shift
-#ifndef USE_X4
-  arm_fully_connected_mat_q7_vec_q15(input, weights_reset, input_size + history_size, history_size, 0, 15, bias_reset,
-                                     reset, NULL);
-#else
-  arm_fully_connected_mat_q7_vec_q15_opt(input, weights_reset, input_size + history_size, history_size, 0, 15,
-                                         bias_reset, reset, NULL);
-#endif
-  // sigmoid function, the size of the integer bit-width should be consistent with out_shift
-  arm_nn_activations_direct_q15(reset, history_size, 0, ARM_SIGMOID);
-  arm_mult_q15(history, reset, reset, history_size);
-
-  // update gate calculation
-  // the range of the output can be adjusted with bias_shift and output_shift
-#ifndef USE_X4
-  arm_fully_connected_mat_q7_vec_q15(input, weights_update, input_size + history_size, history_size, 0, 15,
-                                     bias_update, update, NULL);
-#else
-  arm_fully_connected_mat_q7_vec_q15_opt(input, weights_update, input_size + history_size, history_size, 0, 15,
-                                         bias_update, update, NULL);
-#endif
-
-  // sigmoid function, the size of the integer bit-width should be consistent with out_shift
-  arm_nn_activations_direct_q15(update, history_size, 0, ARM_SIGMOID);
-
-  // hidden state calculation
-#ifndef USE_X4
-  arm_fully_connected_mat_q7_vec_q15(reset, weights_hidden_state, input_size + history_size, history_size, 0, 15,
-                                     bias_hidden_state, hidden_state, NULL);
-#else
-  arm_fully_connected_mat_q7_vec_q15_opt(reset, weights_hidden_state, input_size + history_size, history_size, 0, 15,
-                                         bias_hidden_state, hidden_state, NULL);
-#endif
-
-  // tanh function, the size of the integer bit-width should be consistent with out_shift
-  arm_nn_activations_direct_q15(hidden_state, history_size, 0, ARM_TANH);
-  arm_mult_q15(update, hidden_state, hidden_state, history_size);
-
-  // we calculate z - 1 here
-  // so final addition becomes substraction
-  arm_offset_q15(update, 0x8000, update, history_size);
-  // multiply history
-  arm_mult_q15(history, update, update, history_size);
-  // calculate history_out
-  arm_sub_q15(hidden_state, update, history, history_size);
-
-  return;
-}
-
-int main()
-{
-  #ifdef RTE_Compiler_EventRecorder
-  EventRecorderInitialize (EventRecordAll, 1);  // initialize and start Event Recorder
-  #endif
-
-  printf("Start GRU execution\n");
-  int       input_size = DIM_INPUT;
-  int       history_size = DIM_HISTORY;
-
-  // copy over the input data 
-  arm_copy_q15(test_input1, scratch_buffer + history_size, input_size);
-  arm_copy_q15(test_history, scratch_buffer + history_size + input_size, history_size);
-
-  gru_example(scratch_buffer, input_size, history_size,
-              update_gate_weights, reset_gate_weights, hidden_state_weights,
-              update_gate_bias, reset_gate_bias, hidden_state_bias);
-  printf("Complete first iteration on GRU\n");
-
-  arm_copy_q15(test_input2, scratch_buffer + history_size, input_size);
-  gru_example(scratch_buffer, input_size, history_size,
-              update_gate_weights, reset_gate_weights, hidden_state_weights,
-              update_gate_bias, reset_gate_bias, hidden_state_bias);
-  printf("Complete second iteration on GRU\n");
-
-  return 0;
-}

CMSIS/NN/Examples/ARM/arm_nn_examples/gru/arm_nnexamples_gru.uvoptx

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CMSIS/NN/Examples/ARM/arm_nn_examples/gru/para_gen.py

@@ -1,183 +0,0 @@
-#!/usr/bin/env python
-
-#
-# This is a simple script to generate and convert weights
-# from regular ordering to specific ordering used by
-# q7_x4 or q7_q15_x4
-#
-
-
-import numpy as np
-
-def convert_to_x4_weights(weights):
-    [r, h, w, c] = weights.shape
-    weights = np.reshape(weights, (r, h*w*c))
-    num_of_rows = r
-    num_of_cols = h*w*c
-    new_weights = np.copy(weights)
-    new_weights = np.reshape(new_weights, (r*h*w*c))
-    counter = 0
-    for i in range(int(num_of_rows)/4):
-      # we only need to do the re-ordering for every 4 rows
-      row_base = 4*i
-      for j in range (int(num_of_cols)/4):
-        # for each 4 entries
-        column_base = 4*j
-        new_weights[counter]   =  weights[row_base  ][column_base  ]
-        new_weights[counter+1] =  weights[row_base+1][column_base  ]
-        new_weights[counter+2] =  weights[row_base  ][column_base+2]
-        new_weights[counter+3] =  weights[row_base+1][column_base+2]
-        new_weights[counter+4] =  weights[row_base+2][column_base  ]
-        new_weights[counter+5] =  weights[row_base+3][column_base  ]
-        new_weights[counter+6] =  weights[row_base+2][column_base+2]
-        new_weights[counter+7] =  weights[row_base+3][column_base+2]
-
-        new_weights[counter+8] =  weights[row_base  ][column_base+1]
-        new_weights[counter+9] =  weights[row_base+1][column_base+1]
-        new_weights[counter+10] = weights[row_base  ][column_base+3]
-        new_weights[counter+11] = weights[row_base+1][column_base+3]
-        new_weights[counter+12] = weights[row_base+2][column_base+1]
-        new_weights[counter+13] = weights[row_base+3][column_base+1]
-        new_weights[counter+14] = weights[row_base+2][column_base+3]
-        new_weights[counter+15] = weights[row_base+3][column_base+3]
-        counter = counter + 16
-      # the remaining ones are in order
-      for j in range((int)(num_of_cols-num_of_cols%4), int(num_of_cols)):
-        new_weights[counter] = weights[row_base][j]
-        new_weights[counter+1] = weights[row_base+1][j]
-        new_weights[counter+2] = weights[row_base+2][j]
-        new_weights[counter+3] = weights[row_base+3][j]
-        counter = counter + 4
-    return new_weights
-
-def convert_q7_q15_weights(weights):
-    [r, h, w, c] = weights.shape
-    weights = np.reshape(weights, (r, h*w*c))
-    num_of_rows = r
-    num_of_cols = h*w*c
-    new_weights = np.copy(weights)
-    new_weights = np.reshape(new_weights, (r*h*w*c))
-    counter = 0
-    for i in range(int(num_of_rows)/4):
-      # we only need to do the re-ordering for every 4 rows
-      row_base = 4*i
-      for j in range (int(num_of_cols)/2):
-        # for each 2 entries
-        column_base = 2*j
-        new_weights[counter]   =  weights[row_base  ][column_base  ]
-        new_weights[counter+1] =  weights[row_base+1][column_base  ]
-        new_weights[counter+2] =  weights[row_base  ][column_base+1]
-        new_weights[counter+3] =  weights[row_base+1][column_base+1]
-        new_weights[counter+4] =  weights[row_base+2][column_base  ]
-        new_weights[counter+5] =  weights[row_base+3][column_base  ]
-        new_weights[counter+6] =  weights[row_base+2][column_base+1]
-        new_weights[counter+7] =  weights[row_base+3][column_base+1]
-
-        counter = counter + 8
-      # the remaining ones are in order
-      for j in range((int)(num_of_cols-num_of_cols%2), int(num_of_cols)):
-        new_weights[counter] = weights[row_base][j]
-        new_weights[counter+1] = weights[row_base+1][j]
-        new_weights[counter+2] = weights[row_base+2][j]
-        new_weights[counter+3] = weights[row_base+3][j]
-        counter = counter + 4
-    return new_weights
-
-
-vec_dim = 64
-row_dim = 32
-
-update_weight = np.zeros((row_dim,vec_dim), dtype=int)
-reset_weight = np.zeros((row_dim,vec_dim), dtype=int)
-hidden_weight = np.zeros((row_dim,vec_dim), dtype=int)
-
-update_bias = np.zeros((row_dim), dtype=int)
-reset_bias = np.zeros((row_dim), dtype=int)
-hidden_bias = np.zeros((row_dim), dtype=int)
-
-input_data1 = np.zeros((vec_dim-row_dim), dtype=int)
-input_data2 = np.zeros((vec_dim-row_dim), dtype=int)
-history_data = np.zeros((row_dim), dtype=int)
-
-outfile = open("arm_nnexamples_gru_test_data.h", "w")
-
-for i in range(row_dim):
-  for j in range(vec_dim):
-    update_weight[i][j] = np.random.randint(256)-128
-    reset_weight[i][j] = np.random.randint(256)-128
-    hidden_weight[i][j] = np.random.randint(256)-128
-
-for i in range(row_dim):
-  update_bias[i] =  np.random.randint(256)-128
-  reset_bias[i] =  np.random.randint(256)-128
-  hidden_bias[i] =  np.random.randint(256)-128
-  history_data[i] = np.random.randint(2**10)-2**9
-
-for i in range(vec_dim-row_dim):
-  input_data1[i] = np.random.randint(2**10)-2**9
-  input_data2[i] = np.random.randint(2**10)-2**9
-
-weight = np.reshape(update_weight, (row_dim, vec_dim, 1, 1))
-new_weight = convert_to_x4_weights(weight)
-
-outfile.write("#define UPDATE_GATE_WEIGHT_X2 {")
-weight.tofile(outfile,sep=",",format="%d")
-outfile.write("}\n\n")
-
-new_weight = convert_q7_q15_weights(weight)
-outfile.write("#define UPDATE_GATE_WEIGHT_X4 {")
-new_weight.tofile(outfile,sep=",",format="%d")
-outfile.write("}\n\n")
-
-weight = np.reshape(reset_weight, (row_dim, vec_dim, 1, 1))
-new_weight = convert_to_x4_weights(weight)
-
-outfile.write("#define RESET_GATE_WEIGHT_X2 {")
-weight.tofile(outfile,sep=",",format="%d")
-outfile.write("}\n\n")
-
-new_weight = convert_q7_q15_weights(weight)
-outfile.write("#define RESET_GATE_WEIGHT_X4 {")
-new_weight.tofile(outfile,sep=",",format="%d")
-outfile.write("}\n\n")
-
-weight = np.reshape(hidden_weight, (row_dim, vec_dim, 1, 1))
-new_weight = convert_to_x4_weights(weight)
-
-outfile.write("#define HIDDEN_STATE_WEIGHT_X2 {")
-weight.tofile(outfile,sep=",",format="%d")
-outfile.write("}\n\n")
-
-new_weight = convert_q7_q15_weights(weight)
-outfile.write("#define HIDDEN_STATE_WEIGHT_X4 {")
-new_weight.tofile(outfile,sep=",",format="%d")
-outfile.write("}\n\n")
-
-outfile.write("#define UPDATE_GATE_BIAS {")
-update_bias.tofile(outfile,sep=",",format="%d")
-outfile.write("}\n\n")
-
-outfile.write("#define RESET_GATE_BIAS {")
-reset_bias.tofile(outfile,sep=",",format="%d")
-outfile.write("}\n\n")
-
-outfile.write("#define HIDDEN_STATE_BIAS {")
-update_bias.tofile(outfile,sep=",",format="%d")
-outfile.write("}\n\n")
-
-outfile.write("#define INPUT_DATA1 {")
-input_data1.tofile(outfile,sep=",",format="%d")
-outfile.write("}\n\n")
-
-outfile.write("#define INPUT_DATA2 {")
-input_data2.tofile(outfile,sep=",",format="%d")
-outfile.write("}\n\n")
-
-
-outfile.write("#define HISTORY_DATA {")
-history_data.tofile(outfile,sep=",",format="%d")
-outfile.write("}\n\n")
-
-
-
-outfile.close()

CMSIS/NN/Examples/ARM/arm_nn_examples/gru/readme.txt

@@ -1,4 +0,0 @@
-CMSIS NN Lib example arm_nnexample_gru0 for
-  Cortex-M4 and Cortex-M7.
-
-The example is configured for uVision Simulator.

CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-cifar10/NN-example-cifar10.ewp

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CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-cifar10/arm_nnexamples_cifar10.cpp

@@ -1,196 +0,0 @@
-/* ----------------------------------------------------------------------
-* Copyright (C) 2010-2018 Arm Limited. All rights reserved.
-*
-*
-* Project:       CMSIS NN Library
-* Title:         arm_nnexamples_cifar10.cpp
-*
-* Description:   Convolutional Neural Network Example
-*
-* Target Processor: Cortex-M4/Cortex-M7
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the
-*     distribution.
-*   - Neither the name of Arm LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.
-* -------------------------------------------------------------------- */
-
-/**
- * @ingroup groupExamples
- */
-
-/**
- * @defgroup CNNExample Convolutional Neural Network Example
- *
- * \par Description:
- * \par
- * Demonstrates a convolutional neural network (CNN) example with the use of convolution,
- * ReLU activation, pooling and fully-connected functions.
- *
- * \par Model definition:
- * \par
- * The CNN used in this example is based on CIFAR-10 example from Caffe [1]. 
- * The neural network consists
- * of 3 convolution layers interspersed by ReLU activation and max pooling layers, followed by a 
- * fully-connected layer at the end. The input to the network is a 32x32 pixel color image, which will 
- * be classified into one of the 10 output classes. 
- * This example model implementation needs 32.3 KB to store weights, 40 KB for activations and 
- * 3.1 KB for storing the \c im2col data.
- *
- * \image html CIFAR10_CNN.gif "Neural Network model definition"
- *
- * \par Variables Description:
- * \par
- * \li \c conv1_wt, \c conv2_wt, \c conv3_wt are convolution layer weight matrices
- * \li \c conv1_bias, \c conv2_bias, \c conv3_bias are convolution layer bias arrays
- * \li \c ip1_wt, ip1_bias point to fully-connected layer weights and biases
- * \li \c input_data points to the input image data
- * \li \c output_data points to the classification output
- * \li \c col_buffer is a buffer to store the \c im2col output
- * \li \c scratch_buffer is used to store the activation data (intermediate layer outputs)
- *
- * \par CMSIS DSP Software Library Functions Used:
- * \par
- * - arm_convolve_HWC_q7_RGB()
- * - arm_convolve_HWC_q7_fast()
- * - arm_relu_q7()
- * - arm_maxpool_q7_HWC()
- * - arm_avepool_q7_HWC()
- * - arm_fully_connected_q7_opt()
- * - arm_fully_connected_q7()
- *
- * <b> Refer  </b>
- * \link arm_nnexamples_cifar10.cpp \endlink
- *
- * \par [1] https://github.com/BVLC/caffe
- */
-
-#include <stdint.h>
-#include <stdio.h>
-#include "arm_math.h"
-#include "arm_nnexamples_cifar10_parameter.h"
-#include "arm_nnexamples_cifar10_weights.h"
-
-#include "arm_nnfunctions.h"
-#include "arm_nnexamples_cifar10_inputs.h"
-
-#ifdef _RTE_
-#include "RTE_Components.h"
-#ifdef RTE_Compiler_EventRecorder
-#include "EventRecorder.h"
-#endif
-#endif
-
-// include the input and weights
-
-static q7_t conv1_wt[CONV1_IM_CH * CONV1_KER_DIM * CONV1_KER_DIM * CONV1_OUT_CH] = CONV1_WT;
-static q7_t conv1_bias[CONV1_OUT_CH] = CONV1_BIAS;
-
-static q7_t conv2_wt[CONV2_IM_CH * CONV2_KER_DIM * CONV2_KER_DIM * CONV2_OUT_CH] = CONV2_WT;
-static q7_t conv2_bias[CONV2_OUT_CH] = CONV2_BIAS;
-
-static q7_t conv3_wt[CONV3_IM_CH * CONV3_KER_DIM * CONV3_KER_DIM * CONV3_OUT_CH] = CONV3_WT;
-static q7_t conv3_bias[CONV3_OUT_CH] = CONV3_BIAS;
-
-static q7_t ip1_wt[IP1_DIM * IP1_OUT] = IP1_WT;
-static q7_t ip1_bias[IP1_OUT] = IP1_BIAS;
-
-/* Here the image_data should be the raw uint8 type RGB image in [RGB, RGB, RGB ... RGB] format */
-uint8_t   image_data[CONV1_IM_CH * CONV1_IM_DIM * CONV1_IM_DIM] = IMG_DATA;
-q7_t      output_data[IP1_OUT];
-
-//vector buffer: max(im2col buffer,average pool buffer, fully connected buffer)
-q7_t      col_buffer[2 * 5 * 5 * 32 * 2];
-
-q7_t      scratch_buffer[32 * 32 * 10 * 4];
-
-int main()
-{
-  #ifdef RTE_Compiler_EventRecorder
-  EventRecorderInitialize (EventRecordAll, 1);  // initialize and start Event Recorder
-  #endif
-
-  printf("start execution\n");
-  /* start the execution */
-
-  q7_t     *img_buffer1 = scratch_buffer;
-  q7_t     *img_buffer2 = img_buffer1 + 32 * 32 * 32;
-
-  /* input pre-processing */
-  int mean_data[3] = INPUT_MEAN_SHIFT;
-  unsigned int scale_data[3] = INPUT_RIGHT_SHIFT;
-  for (int i=0;i<32*32*3; i+=3) {
-    img_buffer2[i] =   (q7_t)__SSAT( ((((int)image_data[i]   - mean_data[0])<<7) + (0x1<<(scale_data[0]-1)))
-                             >> scale_data[0], 8);
-    img_buffer2[i+1] = (q7_t)__SSAT( ((((int)image_data[i+1] - mean_data[1])<<7) + (0x1<<(scale_data[1]-1)))
-                             >> scale_data[1], 8);
-    img_buffer2[i+2] = (q7_t)__SSAT( ((((int)image_data[i+2] - mean_data[2])<<7) + (0x1<<(scale_data[2]-1)))
-                             >> scale_data[2], 8);
-  }
-  
-  // conv1 img_buffer2 -> img_buffer1
-  arm_convolve_HWC_q7_RGB(img_buffer2, CONV1_IM_DIM, CONV1_IM_CH, conv1_wt, CONV1_OUT_CH, CONV1_KER_DIM, CONV1_PADDING,
-                          CONV1_STRIDE, conv1_bias, CONV1_BIAS_LSHIFT, CONV1_OUT_RSHIFT, img_buffer1, CONV1_OUT_DIM,
-                          (q15_t *) col_buffer, NULL);
-
-  arm_relu_q7(img_buffer1, CONV1_OUT_DIM * CONV1_OUT_DIM * CONV1_OUT_CH);
-
-  // pool1 img_buffer1 -> img_buffer2
-  arm_maxpool_q7_HWC(img_buffer1, CONV1_OUT_DIM, CONV1_OUT_CH, POOL1_KER_DIM,
-                     POOL1_PADDING, POOL1_STRIDE, POOL1_OUT_DIM, NULL, img_buffer2);
-
-  // conv2 img_buffer2 -> img_buffer1
-  arm_convolve_HWC_q7_fast(img_buffer2, CONV2_IM_DIM, CONV2_IM_CH, conv2_wt, CONV2_OUT_CH, CONV2_KER_DIM,
-                           CONV2_PADDING, CONV2_STRIDE, conv2_bias, CONV2_BIAS_LSHIFT, CONV2_OUT_RSHIFT, img_buffer1,
-                           CONV2_OUT_DIM, (q15_t *) col_buffer, NULL);
-
-  arm_relu_q7(img_buffer1, CONV2_OUT_DIM * CONV2_OUT_DIM * CONV2_OUT_CH);
-
-  // pool2 img_buffer1 -> img_buffer2
-  arm_maxpool_q7_HWC(img_buffer1, CONV2_OUT_DIM, CONV2_OUT_CH, POOL2_KER_DIM,
-                     POOL2_PADDING, POOL2_STRIDE, POOL2_OUT_DIM, col_buffer, img_buffer2);
-
-// conv3 img_buffer2 -> img_buffer1
-  arm_convolve_HWC_q7_fast(img_buffer2, CONV3_IM_DIM, CONV3_IM_CH, conv3_wt, CONV3_OUT_CH, CONV3_KER_DIM,
-                           CONV3_PADDING, CONV3_STRIDE, conv3_bias, CONV3_BIAS_LSHIFT, CONV3_OUT_RSHIFT, img_buffer1,
-                           CONV3_OUT_DIM, (q15_t *) col_buffer, NULL);
-
-  arm_relu_q7(img_buffer1, CONV3_OUT_DIM * CONV3_OUT_DIM * CONV3_OUT_CH);
-
-  // pool3 img_buffer-> img_buffer2
-  arm_maxpool_q7_HWC(img_buffer1, CONV3_OUT_DIM, CONV3_OUT_CH, POOL3_KER_DIM,
-                     POOL3_PADDING, POOL3_STRIDE, POOL3_OUT_DIM, col_buffer, img_buffer2);
-
-  arm_fully_connected_q7_opt(img_buffer2, ip1_wt, IP1_DIM, IP1_OUT, IP1_BIAS_LSHIFT, IP1_OUT_RSHIFT, ip1_bias,
-                             output_data, (q15_t *) img_buffer1);
-
-  arm_softmax_q7(output_data, 10, output_data);
-
-  for (int i = 0; i < 10; i++)
-  {
-      printf("%d: %d\n", i, output_data[i]);
-  }
-
-  return 0;
-}

CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-cifar10/arm_nnexamples_cifar10_parameter.h

@@ -1,43 +0,0 @@
-#define CONV1_IM_DIM 32
-#define CONV1_IM_CH 3
-#define CONV1_KER_DIM 5
-#define CONV1_PADDING 2
-#define CONV1_STRIDE 1
-#define CONV1_OUT_CH 32
-#define CONV1_OUT_DIM 32
-
-#define POOL1_KER_DIM 3
-#define POOL1_STRIDE 2
-#define POOL1_PADDING 0
-#define POOL1_OUT_DIM 16
-
-#define CONV2_IM_DIM 16
-#define CONV2_IM_CH 32
-#define CONV2_KER_DIM 5
-#define CONV2_PADDING 2
-#define CONV2_STRIDE 1
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-#define CONV2_OUT_DIM 16
-
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-#define POOL2_PADDING 0
-#define POOL2_OUT_DIM 8
-
-#define CONV3_IM_DIM 8
-#define CONV3_IM_CH 16
-#define CONV3_KER_DIM 5
-#define CONV3_PADDING 2
-#define CONV3_STRIDE 1
-#define CONV3_OUT_CH 32
-#define CONV3_OUT_DIM 8
-
-#define POOL3_KER_DIM 3
-#define POOL3_STRIDE 2
-#define POOL3_PADDING 0
-#define POOL3_OUT_DIM 4
-
-#define IP1_DIM 4*4*32
-#define IP1_IM_DIM 4
-#define IP1_IM_CH 32
-#define IP1_OUT 10

CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-cifar10/readme_iar.txt

@@ -1,7 +0,0 @@
-CMSIS NN Lib example arm_nnexample_cifar10 for
-  Cortex-M0, Cortex-M3, Cortex-M4 and Cortex-M7.
-
-The example is configured for IAR Embedded Workbench for ARM Simulator.
-
-When changing target, remember to change the ARM_MATH_CMx and __FPU_PRESENT
-Preprocessor defines for C/C++ Compiler

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-                <name>${CMSIS_PACK_PATH_ARM#CMSIS#5.6.0-dev0}$\CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q7.c</name>
-            </file>
-        </group>
-        <group>
-            <name>Device Startup</name>
-            <tag>CMSISPack.Component</tag>
-            <file>
-                <name>$PROJ_DIR$\RTE\Device\ARMCM0\startup_ARMCM0.s</name>
-            </file>
-            <file>
-                <name>$PROJ_DIR$\RTE\Device\ARMCM0\system_ARMCM0.c</name>
-            </file>
-        </group>
-    </group>
-    <cmsisPackSettings>
-        <rte>&lt;?xml version="1.0" encoding="UTF-8" standalone="no"?&gt;
-&lt;configuration xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"&gt;
-  &lt;packages/&gt;
-  &lt;device Dclock="10000000" Dcore="Cortex-M0" DcoreVersion="r0p0" Dendian="Little-endian" Dfamily="ARM Cortex M0" Dfpu="NO_FPU" Dmpu="NO_MPU" Dname="ARMCM0" Dvendor="ARM:82" Pname=""&gt;
-    &lt;url&gt;http://www.keil.com/dd2/arm/armcm0&lt;/url&gt;
-    &lt;package info="CMSIS (Cortex Microcontroller Software Interface Standard)" name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0-dev0"/&gt;
-  &lt;/device&gt;
-  &lt;toolchain Tcompiler="IAR" Toutput="exe"/&gt;
-  &lt;components&gt;
-    &lt;component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.2.0"&gt;
-      &lt;package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0-dev0"/&gt;
-      &lt;file category="doc" name="CMSIS/Documentation/Core/html/index.html"/&gt;
-      &lt;file category="include" name="CMSIS/Core/Include/"/&gt;
-    &lt;/component&gt;
-    &lt;component Cclass="CMSIS" Cgroup="DSP" Cvariant="Library" Cvendor="ARM" Cversion="1.6.0"&gt;
-      &lt;package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0-dev0"/&gt;
-      &lt;file category="doc" name="CMSIS/Documentation/DSP/html/index.html"/&gt;
-      &lt;file category="header" name="CMSIS/DSP/Include/arm_math.h"/&gt;
-      &lt;file category="library" condition="CM0_LE_IAR" name="CMSIS/DSP/Lib/IAR/iar_cortexM0l_math.a" src="CMSIS/DSP/Source/IAR"/&gt;
-    &lt;/component&gt;
-    &lt;component Cclass="CMSIS" Cgroup="NN Lib" Cvendor="ARM" Cversion="1.1.0"&gt;
-      &lt;package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0-dev0"/&gt;
-      &lt;file category="doc" name="CMSIS/Documentation/NN/html/index.html"/&gt;
-      &lt;file category="header" name="CMSIS/NN/Include/arm_nnfunctions.h"/&gt;
-      &lt;file category="source" name="CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q7.c"/&gt;
-      &lt;file category="source" name="CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q15.c"/&gt;
-      &lt;file category="source" name="CMSIS/NN/Source/ActivationFunctions/arm_relu_q7.c"/&gt;
-      &lt;file category="source" name="CMSIS/NN/Source/ActivationFunctions/arm_relu_q15.c"/&gt;
-      &lt;file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_RGB.c"/&gt;
-      &lt;file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_basic.c"/&gt;
-      &lt;file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast.c"/&gt;
-      &lt;file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7.c"/&gt;
-      &lt;file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.c"/&gt;
-      &lt;file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.c"/&gt;
-      &lt;file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.c"/&gt;
-      &lt;file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_HWC_q7_fast_nonsquare.c"/&gt;
-      &lt;file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic.c"/&gt;
-      &lt;file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic_nonsquare.c"/&gt;
-      &lt;file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.c"/&gt;
-      &lt;file category="source" name="CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast_nonsquare.c"/&gt;
-      &lt;file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7.c"/&gt;
-      &lt;file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.c"/&gt;
-      &lt;file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15.c"/&gt;
-      &lt;file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.c"/&gt;
-      &lt;file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.c"/&gt;
-      &lt;file category="source" name="CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.c"/&gt;
-      &lt;file category="source" name="CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_no_shift.c"/&gt;
-      &lt;file category="source" name="CMSIS/NN/Source/NNSupportFunctions/arm_nntables.c"/&gt;
-      &lt;file category="source" name="CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.c"/&gt;
-      &lt;file category="source" name="CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q15.c"/&gt;
-      &lt;file category="source" name="CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q7.c"/&gt;
-      &lt;file category="source" name="CMSIS/NN/Source/PoolingFunctions/arm_pool_q7_HWC.c"/&gt;
-      &lt;file category="source" name="CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q15.c"/&gt;
-      &lt;file category="source" name="CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q7.c"/&gt;
-    &lt;/component&gt;
-    &lt;component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.2.0" deviceDependent="1"&gt;
-      &lt;package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0-dev0"/&gt;
-      &lt;file category="header" deviceDependent="1" name="Device/ARM/ARMCM0/Include/ARMCM0.h"/&gt;
-      &lt;file attr="config" category="sourceAsm" condition="IAR" deviceDependent="1" name="Device/ARM/ARMCM0/Source/IAR/startup_ARMCM0.s" version="1.0.0"/&gt;
-      &lt;file attr="config" category="sourceC" deviceDependent="1" name="Device/ARM/ARMCM0/Source/system_ARMCM0.c" version="1.0.0"/&gt;
-    &lt;/component&gt;
-  &lt;/components&gt;
-  &lt;apis/&gt;
-&lt;/configuration&gt;
-</rte>
-    </cmsisPackSettings>
-</project>

CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-gru/arm_nnexamples_gru.cpp

@@ -1,221 +0,0 @@
-/* ----------------------------------------------------------------------
-* Copyright (C) 2010-2018 Arm Limited. All rights reserved.
-*
-*
-* Project:       CMSIS NN Library
-* Title:         arm_nnexamples_gru.cpp
-*
-* Description:   Gated Recurrent Unit Example
-*
-* Target Processor: Cortex-M4/Cortex-M7
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the
-*     distribution.
-*   - Neither the name of Arm LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.
-* -------------------------------------------------------------------- */
-
-/**
- * @ingroup groupExamples
- */
-
-/**
- * @defgroup GRUExample Gated Recurrent Unit Example
- *
- * \par Description:
- * \par
- * Demonstrates a gated recurrent unit (GRU) example with the use of fully-connected,
- * Tanh/Sigmoid activation functions.
- *
- * \par Model definition:
- * \par
- * GRU is a type of recurrent neural network (RNN). It contains two sigmoid gates and one hidden
- * state. 
- * \par
- * The computation can be summarized as:
- * <pre>z[t] = sigmoid( W_z &sdot; {h[t-1],x[t]} )
- * r[t] = sigmoid( W_r &sdot; {h[t-1],x[t]} ) 
- * n[t] = tanh( W_n &sdot; [r[t] &times; {h[t-1], x[t]} ) 
- * h[t] = (1 - z[t]) &times; h[t-1] + z[t] &times; n[t] </pre>
- * \image html GRU.gif "Gate Recurrent Unit Diagram"
- *
- * \par Variables Description:
- * \par
- * \li \c update_gate_weights, \c reset_gate_weights, \c hidden_state_weights are weights corresponding to update gate (W_z), reset gate (W_r), and hidden state (W_n).
- * \li \c update_gate_bias, \c reset_gate_bias, \c hidden_state_bias are layer bias arrays
- * \li \c test_input1, \c test_input2, \c test_history are the inputs and initial history
- *
- * \par
- * The buffer is allocated as:
- * \par
- * | reset | input | history | update | hidden_state |
- * \par
- * In this way, the concatination is automatically done since (reset, input) and (input, history)
- * are physically concatinated in memory.
- * \par
- *  The ordering of the weight matrix should be adjusted accordingly.
- *
-  *
- * 
- * \par CMSIS DSP Software Library Functions Used:
- * \par
- * - arm_fully_connected_mat_q7_vec_q15_opt()
- * - arm_nn_activations_direct_q15()
- * - arm_mult_q15()
- * - arm_offset_q15()
- * - arm_sub_q15()
- * - arm_copy_q15()
- *
- * <b> Refer  </b>
- * \link arm_nnexamples_gru.cpp \endlink
- *
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <math.h>
-#include "arm_nnexamples_gru_test_data.h"
-#include "arm_math.h"
-#include "arm_nnfunctions.h"
-
-#ifdef _RTE_
-#include "RTE_Components.h"
-#ifdef RTE_Compiler_EventRecorder
-#include "EventRecorder.h"
-#endif
-#endif
-
-#define DIM_HISTORY 32
-#define DIM_INPUT 32
-#define DIM_VEC 64
-
-#define USE_X4
-
-#ifndef USE_X4
-static q7_t update_gate_weights[DIM_VEC * DIM_HISTORY] = UPDATE_GATE_WEIGHT_X2;
-static q7_t reset_gate_weights[DIM_VEC * DIM_HISTORY] = RESET_GATE_WEIGHT_X2;
-static q7_t hidden_state_weights[DIM_VEC * DIM_HISTORY] = HIDDEN_STATE_WEIGHT_X2;
-#else
-static q7_t update_gate_weights[DIM_VEC * DIM_HISTORY] = UPDATE_GATE_WEIGHT_X4;
-static q7_t reset_gate_weights[DIM_VEC * DIM_HISTORY] = RESET_GATE_WEIGHT_X4;
-static q7_t hidden_state_weights[DIM_VEC * DIM_HISTORY] = HIDDEN_STATE_WEIGHT_X4;
-#endif
-
-static q7_t update_gate_bias[DIM_HISTORY] = UPDATE_GATE_BIAS;
-static q7_t reset_gate_bias[DIM_HISTORY] = RESET_GATE_BIAS;
-static q7_t hidden_state_bias[DIM_HISTORY] = HIDDEN_STATE_BIAS;
-
-static q15_t test_input1[DIM_INPUT] = INPUT_DATA1;
-static q15_t test_input2[DIM_INPUT] = INPUT_DATA2;
-static q15_t test_history[DIM_HISTORY] = HISTORY_DATA;
-
-q15_t     scratch_buffer[DIM_HISTORY * 4 + DIM_INPUT];
-
-void gru_example(q15_t * scratch_input, uint16_t input_size, uint16_t history_size,
-                 q7_t * weights_update, q7_t * weights_reset, q7_t * weights_hidden_state,
-                 q7_t * bias_update, q7_t * bias_reset, q7_t * bias_hidden_state)
-{
-  q15_t    *reset = scratch_input;
-  q15_t    *input = scratch_input + history_size;
-  q15_t    *history = scratch_input + history_size + input_size;
-  q15_t    *update = scratch_input + 2 * history_size + input_size;
-  q15_t    *hidden_state = scratch_input + 3 * history_size + input_size;
-
-  // reset gate calculation
-  // the range of the output can be adjusted with bias_shift and output_shift
-#ifndef USE_X4
-  arm_fully_connected_mat_q7_vec_q15(input, weights_reset, input_size + history_size, history_size, 0, 15, bias_reset,
-                                     reset, NULL);
-#else
-  arm_fully_connected_mat_q7_vec_q15_opt(input, weights_reset, input_size + history_size, history_size, 0, 15,
-                                         bias_reset, reset, NULL);
-#endif
-  // sigmoid function, the size of the integer bit-width should be consistent with out_shift
-  arm_nn_activations_direct_q15(reset, history_size, 0, ARM_SIGMOID);
-  arm_mult_q15(history, reset, reset, history_size);
-
-  // update gate calculation
-  // the range of the output can be adjusted with bias_shift and output_shift
-#ifndef USE_X4
-  arm_fully_connected_mat_q7_vec_q15(input, weights_update, input_size + history_size, history_size, 0, 15,
-                                     bias_update, update, NULL);
-#else
-  arm_fully_connected_mat_q7_vec_q15_opt(input, weights_update, input_size + history_size, history_size, 0, 15,
-                                         bias_update, update, NULL);
-#endif
-
-  // sigmoid function, the size of the integer bit-width should be consistent with out_shift
-  arm_nn_activations_direct_q15(update, history_size, 0, ARM_SIGMOID);
-
-  // hidden state calculation
-#ifndef USE_X4
-  arm_fully_connected_mat_q7_vec_q15(reset, weights_hidden_state, input_size + history_size, history_size, 0, 15,
-                                     bias_hidden_state, hidden_state, NULL);
-#else
-  arm_fully_connected_mat_q7_vec_q15_opt(reset, weights_hidden_state, input_size + history_size, history_size, 0, 15,
-                                         bias_hidden_state, hidden_state, NULL);
-#endif
-
-  // tanh function, the size of the integer bit-width should be consistent with out_shift
-  arm_nn_activations_direct_q15(hidden_state, history_size, 0, ARM_TANH);
-  arm_mult_q15(update, hidden_state, hidden_state, history_size);
-
-  // we calculate z - 1 here
-  // so final addition becomes substraction
-  arm_offset_q15(update, 0x8000, update, history_size);
-  // multiply history
-  arm_mult_q15(history, update, update, history_size);
-  // calculate history_out
-  arm_sub_q15(hidden_state, update, history, history_size);
-
-  return;
-}
-
-int main()
-{
-  #ifdef RTE_Compiler_EventRecorder
-  EventRecorderInitialize (EventRecordAll, 1);  // initialize and start Event Recorder
-  #endif
-
-  printf("Start GRU execution\n");
-  int       input_size = DIM_INPUT;
-  int       history_size = DIM_HISTORY;
-
-  // copy over the input data 
-  arm_copy_q15(test_input1, scratch_buffer + history_size, input_size);
-  arm_copy_q15(test_history, scratch_buffer + history_size + input_size, history_size);
-
-  gru_example(scratch_buffer, input_size, history_size,
-              update_gate_weights, reset_gate_weights, hidden_state_weights,
-              update_gate_bias, reset_gate_bias, hidden_state_bias);
-  printf("Complete first iteration on GRU\n");
-
-  arm_copy_q15(test_input2, scratch_buffer + history_size, input_size);
-  gru_example(scratch_buffer, input_size, history_size,
-              update_gate_weights, reset_gate_weights, hidden_state_weights,
-              update_gate_bias, reset_gate_bias, hidden_state_bias);
-  printf("Complete second iteration on GRU\n");
-
-  return 0;
-}

CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-gru/readme_iar.txt

@@ -1,7 +0,0 @@
-CMSIS NN Lib example arm_nnexample_gru0 for
-  Cortex-M0, Cortex-M3, Cortex-M4 and Cortex-M7.
-
-The example is configured for IAR Embedded Workbench for ARM Simulator.
-
-When changing target, remember to change the ARM_MATH_CMx and __FPU_PRESENT
-Preprocessor defines for C/C++ Compiler

CMSIS/NN/Examples/IAR/iar_nn_examples/NN-examples.eww

@@ -1,10 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<workspace>
-    <project>
-        <path>$WS_DIR$\NN-example-cifar10\NN-example-cifar10.ewp</path>
-    </project>
-    <project>
-        <path>$WS_DIR$\NN-example-gru\NN-example-gru.ewp</path>
-    </project>
-    <batchBuild />
-</workspace>