Updated CoreValidation examples.

ARM.CMSIS.pdsc

@@ -13,6 +13,7 @@
        - Reworked ARM device support files.
        - Updated RTOS2 examples.
        - Updated DSP examples.
+       - Updated CoreValidation examples.
     </release>
     <release version="5.3.1-dev6">
       Utilities:

CMSIS/CoreValidation/Source/CV_CoreFunc.c

@@ -20,7 +20,7 @@ static volatile uint32_t irqActive = 0U;
 static void TC_CoreFunc_EnDisIRQIRQHandler(void) {
   ++irqTaken;
 #if defined(__CORTEX_M) && (__CORTEX_M > 0)
-  irqActive = NVIC_GetActive(WDT_IRQn);
+  irqActive = NVIC_GetActive(Interrupt0_IRQn);
 #endif
 }
 
@@ -52,12 +52,12 @@ void TC_CoreFunc_EnDisIRQ (void)
   __disable_irq();
 
   // Enable the interrupt
-  NVIC_EnableIRQ(WDT_IRQn);
-  ASSERT_TRUE(NVIC_GetEnableIRQ(WDT_IRQn) != 0U);
+  NVIC_EnableIRQ(Interrupt0_IRQn);
+  ASSERT_TRUE(NVIC_GetEnableIRQ(Interrupt0_IRQn) != 0U);
 
   // Clear its pending state
-  NVIC_ClearPendingIRQ(WDT_IRQn);
-  ASSERT_TRUE(NVIC_GetPendingIRQ(WDT_IRQn) == 0U);
+  NVIC_ClearPendingIRQ(Interrupt0_IRQn);
+  ASSERT_TRUE(NVIC_GetPendingIRQ(Interrupt0_IRQn) == 0U);
 
   // Register test interrupt handler.
   TST_IRQHandler = TC_CoreFunc_EnDisIRQIRQHandler;
@@ -67,14 +67,14 @@ void TC_CoreFunc_EnDisIRQ (void)
 #endif
 
   // Set the interrupt pending state
-  NVIC_SetPendingIRQ(WDT_IRQn);
+  NVIC_SetPendingIRQ(Interrupt0_IRQn);
   for(uint32_t i = 10U; i > 0U; --i) {}
 
   // Interrupt is not taken
   ASSERT_TRUE(irqTaken == 0U);
-  ASSERT_TRUE(NVIC_GetPendingIRQ(WDT_IRQn) != 0U);
+  ASSERT_TRUE(NVIC_GetPendingIRQ(Interrupt0_IRQn) != 0U);
 #if defined(__CORTEX_M) && (__CORTEX_M > 0)
-  ASSERT_TRUE(NVIC_GetActive(WDT_IRQn) == 0U);
+  ASSERT_TRUE(NVIC_GetActive(Interrupt0_IRQn) == 0U);
 #endif
 
   // Globally enable interrupt servicing
@@ -86,30 +86,30 @@ void TC_CoreFunc_EnDisIRQ (void)
   ASSERT_TRUE(irqTaken == 1U);
 #if defined(__CORTEX_M) && (__CORTEX_M > 0)
   ASSERT_TRUE(irqActive != 0U);
-  ASSERT_TRUE(NVIC_GetActive(WDT_IRQn) == 0U);
+  ASSERT_TRUE(NVIC_GetActive(Interrupt0_IRQn) == 0U);
 #endif
 
   // Interrupt it not pending anymore.
-  ASSERT_TRUE(NVIC_GetPendingIRQ(WDT_IRQn) == 0U);
+  ASSERT_TRUE(NVIC_GetPendingIRQ(Interrupt0_IRQn) == 0U);
 
   // Disable interrupt
-  NVIC_DisableIRQ(WDT_IRQn);
-  ASSERT_TRUE(NVIC_GetEnableIRQ(WDT_IRQn) == 0U);
+  NVIC_DisableIRQ(Interrupt0_IRQn);
+  ASSERT_TRUE(NVIC_GetEnableIRQ(Interrupt0_IRQn) == 0U);
 
   // Set interrupt pending
-  NVIC_SetPendingIRQ(WDT_IRQn);
+  NVIC_SetPendingIRQ(Interrupt0_IRQn);
   for(uint32_t i = 10U; i > 0U; --i) {}
 
   // Interrupt is not taken again
   ASSERT_TRUE(irqTaken == 1U);
-  ASSERT_TRUE(NVIC_GetPendingIRQ(WDT_IRQn) != 0U);
+  ASSERT_TRUE(NVIC_GetPendingIRQ(Interrupt0_IRQn) != 0U);
 
   // Clear interrupt pending
-  NVIC_ClearPendingIRQ(WDT_IRQn);
+  NVIC_ClearPendingIRQ(Interrupt0_IRQn);
   for(uint32_t i = 10U; i > 0U; --i) {}
 
   // Interrupt it not pending anymore.
-  ASSERT_TRUE(NVIC_GetPendingIRQ(WDT_IRQn) == 0U);
+  ASSERT_TRUE(NVIC_GetPendingIRQ(Interrupt0_IRQn) == 0U);
 
   // Globally disable interrupt servicing
   __disable_irq();
@@ -135,14 +135,14 @@ void TC_CoreFunc_IRQPrio (void)
   NVIC_SetPriority(SVCall_IRQn, orig);
 
   /* Test Interrupt Priority */
-  orig = NVIC_GetPriority(WDT_IRQn);
+  orig = NVIC_GetPriority(Interrupt0_IRQn);
 
-  NVIC_SetPriority(WDT_IRQn, orig+1U);
-  prio = NVIC_GetPriority(WDT_IRQn);
+  NVIC_SetPriority(Interrupt0_IRQn, orig+1U);
+  prio = NVIC_GetPriority(Interrupt0_IRQn);
 
   ASSERT_TRUE(prio == orig+1U);
 
-  NVIC_SetPriority(WDT_IRQn, orig);
+  NVIC_SetPriority(Interrupt0_IRQn, orig);
 }
 
 /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
@@ -219,14 +219,14 @@ void TC_CoreFunc_IRQVect(void) {
   ASSERT_TRUE(NVIC_GetVector(SysTick_IRQn) == (uint32_t)SysTick_Handler);
 
   /* reconfigure WDT IRQ vector */
-  extern void WDT_IRQHandler(void);
+  extern void Interrupt0_Handler(void);
 
-  const uint32_t wdtvec = NVIC_GetVector(WDT_IRQn);
-  ASSERT_TRUE(wdtvec == (uint32_t)WDT_IRQHandler);
+  const uint32_t wdtvec = NVIC_GetVector(Interrupt0_IRQn);
+  ASSERT_TRUE(wdtvec == (uint32_t)Interrupt0_Handler);
 
-  NVIC_SetVector(WDT_IRQn, wdtvec + 32U);
+  NVIC_SetVector(Interrupt0_IRQn, wdtvec + 32U);
 
-  ASSERT_TRUE(NVIC_GetVector(WDT_IRQn) == (wdtvec + 32U));
+  ASSERT_TRUE(NVIC_GetVector(Interrupt0_IRQn) == (wdtvec + 32U));
 
   /* restore vector table */
   SCB->VTOR = orig_vtor;
@@ -291,15 +291,15 @@ void TC_CoreFunc_IPSR (void) {
   irqIPSR = 0U;
   irqXPSR = 0U;
 
-  NVIC_ClearPendingIRQ(WDT_IRQn);
-  NVIC_EnableIRQ(WDT_IRQn);
+  NVIC_ClearPendingIRQ(Interrupt0_IRQn);
+  NVIC_EnableIRQ(Interrupt0_IRQn);
   __enable_irq();
 
-  NVIC_SetPendingIRQ(WDT_IRQn);
+  NVIC_SetPendingIRQ(Interrupt0_IRQn);
   for(uint32_t i = 10U; i > 0U; --i) {}
 
   __disable_irq();
-  NVIC_DisableIRQ(WDT_IRQn);
+  NVIC_DisableIRQ(Interrupt0_IRQn);
 
   ASSERT_TRUE(irqIPSR != 0U); // Exception Mode
   ASSERT_TRUE((irqXPSR & xPSR_ISR_Msk) != 0U); // Exception Mode

CMSIS/CoreValidation/Source/CV_CoreInstr.c

@@ -436,7 +436,7 @@ architecture, i.e. Cortex-A or Cortex-M.
 static void TC_CoreInstr_LoadStoreExclusive_IRQEnable(void) {
 #if defined(__CORTEX_M)
   TST_IRQHandler = TC_CoreInstr_LoadStoreExclusive_IRQHandler;
-  NVIC_EnableIRQ(WDT_IRQn);
+  NVIC_EnableIRQ(Interrupt0_IRQn);
 #elif defined(__CORTEX_A)
   IRQ_SetHandler(SGI0_IRQn, TC_CoreInstr_LoadStoreExclusive_IRQHandler);
   IRQ_Enable(SGI0_IRQn);
@@ -454,7 +454,7 @@ architecture, i.e. Cortex-A or Cortex-M.
 */
 static void TC_CoreInstr_LoadStoreExclusive_IRQPend(void) {
 #if defined(__CORTEX_M)
-  NVIC_SetPendingIRQ(WDT_IRQn);
+  NVIC_SetPendingIRQ(Interrupt0_IRQn);
 #elif defined(__CORTEX_A)
   IRQ_SetPending(SGI0_IRQn);
 #else
@@ -472,7 +472,7 @@ architecture, i.e. Cortex-A or Cortex-M.
 static void TC_CoreInstr_LoadStoreExclusive_IRQDisable(void) {
   __disable_irq();
 #if defined(__CORTEX_M)
-  NVIC_DisableIRQ(WDT_IRQn);
+  NVIC_DisableIRQ(Interrupt0_IRQn);
   TST_IRQHandler = NULL;
 #elif defined(__CORTEX_A)
   IRQ_Disable(SGI0_IRQn);

CMSIS/CoreValidation/Source/cmsis_cv.c

@@ -13,7 +13,7 @@
  *      Prototypes
  *----------------------------------------------------------------------------*/
 
-void WDT_IRQHandler(void);
+void Interrupt0_Handler(void);
 
 /*-----------------------------------------------------------------------------
  *      Variables declarations
@@ -21,7 +21,7 @@ void WDT_IRQHandler(void);
 
 void (*TST_IRQHandler)(void);
 
-void WDT_IRQHandler(void) {
+void Interrupt0_Handler(void) {
   if (TST_IRQHandler != NULL) TST_IRQHandler();
 }
 

CMSIS/CoreValidation/Tests/Cortex-M0/AC5/RTE/Device/ARMCM0/startup_ARMCM0.s

@@ -1,12 +1,12 @@
 ;/**************************************************************************//**
 ; * @file     startup_ARMCM0.s
 ; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM0 Device Series
-; * @version  V5.00
-; * @date     02. March 2016
+; *           ARMCM0 Device
+; * @version  V5.3.1
+; * @date     09. July 2018
 ; ******************************************************************************/
 ;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
 ; *
 ; * SPDX-License-Identifier: Apache-2.0
 ; *
@@ -23,32 +23,33 @@
 ; * limitations under the License.
 ; */
 
-;/*
 ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
 
 
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Stack Configuration
+;  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
 
-Stack_Size      EQU     0x00000400
+Stack_Size      EQU      0x00000400
 
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
+                AREA     STACK, NOINIT, READWRITE, ALIGN=3
+__stack_limit
+Stack_Mem       SPACE    Stack_Size
 __initial_sp
 
 
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Heap Configuration
+;  <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
 
-Heap_Size       EQU     0x00000C00
+Heap_Size       EQU      0x00000C00
 
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+                IF       Heap_Size != 0                      ; Heap is provided
+                AREA     HEAP, NOINIT, READWRITE, ALIGN=3
 __heap_base
-Heap_Mem        SPACE   Heap_Size
+Heap_Mem        SPACE    Heap_Size
 __heap_limit
+                ENDIF
 
 
                 PRESERVE8
@@ -57,186 +58,102 @@ __heap_limit
 
 ; Vector Table Mapped to Address 0 at Reset
 
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
-                DCD     RTC_IRQHandler            ;  1:  Real Time Clock
-                DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
-                DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
-                DCD     MCIA_IRQHandler           ;  4:  MCIa
-                DCD     MCIB_IRQHandler           ;  5:  MCIb
-                DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
-                DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
-                DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
-                DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
-                DCD     AACI_IRQHandler           ; 10: AACI / AC97
-                DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
-                DCD     ENET_IRQHandler           ; 12: Ethernet
-                DCD     USBDC_IRQHandler          ; 13: USB Device
-                DCD     USBHC_IRQHandler          ; 14: USB Host Controller
-                DCD     CHLCD_IRQHandler          ; 15: Character LCD
-                DCD     FLEXRAY_IRQHandler        ; 16: Flexray
-                DCD     CAN_IRQHandler            ; 17: CAN
-                DCD     LIN_IRQHandler            ; 18: LIN
-                DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
-                DCD     0                         ; 20: Reserved
-                DCD     0                         ; 21: Reserved
-                DCD     0                         ; 22: Reserved
-                DCD     0                         ; 23: Reserved
-                DCD     0                         ; 24: Reserved
-                DCD     0                         ; 25: Reserved
-                DCD     0                         ; 26: Reserved
-                DCD     0                         ; 27: Reserved
-                DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
-                DCD     0                         ; 29: Reserved - CPU FPGA
-                DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
-                DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
+                AREA     RESET, DATA, READONLY
+                EXPORT   __Vectors
+                EXPORT   __Vectors_End
+                EXPORT   __Vectors_Size
+
+__Vectors       DCD      __initial_sp                        ;     Top of Stack
+                DCD      Reset_Handler                       ;     Reset Handler
+                DCD      NMI_Handler                         ; -14 NMI Handler
+                DCD      HardFault_Handler                   ; -13 Hard Fault Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      SVC_Handler                         ;  -5 SVCall Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      PendSV_Handler                      ;  -2 PendSV Handler
+                DCD      SysTick_Handler                     ;  -1 SysTick Handler
+
+                ; Interrupts
+                DCD      Interrupt0_Handler                  ;   0 Interrupt 0
+                DCD      Interrupt1_Handler                  ;   1 Interrupt 1
+                DCD      Interrupt2_Handler                  ;   2 Interrupt 2
+                DCD      Interrupt3_Handler                  ;   3 Interrupt 3
+                DCD      Interrupt4_Handler                  ;   4 Interrupt 4
+                DCD      Interrupt5_Handler                  ;   5 Interrupt 5
+                DCD      Interrupt6_Handler                  ;   6 Interrupt 6
+                DCD      Interrupt7_Handler                  ;   7 Interrupt 7
+                DCD      Interrupt8_Handler                  ;   8 Interrupt 8
+                DCD      Interrupt9_Handler                  ;   9 Interrupt 9
+
+                SPACE    ( 22 * 4)                           ; Interrupts 10 .. 31 are left out
 __Vectors_End
+__Vectors_Size  EQU      __Vectors_End - __Vectors
 
-__Vectors_Size  EQU     __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
 
+                AREA     |.text|, CODE, READONLY
 
 ; Reset Handler
 
 Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  SystemInit
-                IMPORT  __main
-                LDR     R0, =SystemInit
-                BLX     R0
-                LDR     R0, =__main
-                BX      R0
+                EXPORT   Reset_Handler             [WEAK]
+                IMPORT   SystemInit
+                IMPORT   __main
+
+                LDR      R0, =SystemInit
+                BLX      R0
+                LDR      R0, =__main
+                BX       R0
                 ENDP
 
 
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler               [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+                MACRO
+                Set_Default_Handler  $Handler_Name
+$Handler_Name   PROC
+                EXPORT   $Handler_Name             [WEAK]
+                B        .
                 ENDP
+                MEND
 
-Default_Handler PROC
-
-                EXPORT  WDT_IRQHandler            [WEAK]
-                EXPORT  RTC_IRQHandler            [WEAK]
-                EXPORT  TIM0_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler           [WEAK]
-                EXPORT  MCIA_IRQHandler           [WEAK]
-                EXPORT  MCIB_IRQHandler           [WEAK]
-                EXPORT  UART0_IRQHandler          [WEAK]
-                EXPORT  UART1_IRQHandler          [WEAK]
-                EXPORT  UART2_IRQHandler          [WEAK]
-                EXPORT  UART3_IRQHandler          [WEAK]
-                EXPORT  UART4_IRQHandler          [WEAK]
-                EXPORT  AACI_IRQHandler           [WEAK]
-                EXPORT  CLCD_IRQHandler           [WEAK]
-                EXPORT  ENET_IRQHandler           [WEAK]
-                EXPORT  USBDC_IRQHandler          [WEAK]
-                EXPORT  USBHC_IRQHandler          [WEAK]
-                EXPORT  CHLCD_IRQHandler          [WEAK]
-                EXPORT  FLEXRAY_IRQHandler        [WEAK]
-                EXPORT  CAN_IRQHandler            [WEAK]
-                EXPORT  LIN_IRQHandler            [WEAK]
-                EXPORT  I2C_IRQHandler            [WEAK]
-                EXPORT  CPU_CLCD_IRQHandler       [WEAK]
-                EXPORT  SPI_IRQHandler            [WEAK]
-
-WDT_IRQHandler
-RTC_IRQHandler
-TIM0_IRQHandler
-TIM2_IRQHandler
-MCIA_IRQHandler
-MCIB_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-UART3_IRQHandler
-UART4_IRQHandler
-AACI_IRQHandler
-CLCD_IRQHandler
-ENET_IRQHandler
-USBDC_IRQHandler
-USBHC_IRQHandler
-CHLCD_IRQHandler
-FLEXRAY_IRQHandler
-CAN_IRQHandler
-LIN_IRQHandler
-I2C_IRQHandler
-CPU_CLCD_IRQHandler
-SPI_IRQHandler
-                B       .
 
-                ENDP
+; Default exception/interrupt handler
 
+                Set_Default_Handler  NMI_Handler
+                Set_Default_Handler  HardFault_Handler
+                Set_Default_Handler  SVC_Handler
+                Set_Default_Handler  PendSV_Handler
+                Set_Default_Handler  SysTick_Handler
 
-                ALIGN
+                Set_Default_Handler  Interrupt0_Handler
+                Set_Default_Handler  Interrupt1_Handler
+                Set_Default_Handler  Interrupt2_Handler
+                Set_Default_Handler  Interrupt3_Handler
+                Set_Default_Handler  Interrupt4_Handler
+                Set_Default_Handler  Interrupt5_Handler
+                Set_Default_Handler  Interrupt6_Handler
+                Set_Default_Handler  Interrupt7_Handler
+                Set_Default_Handler  Interrupt8_Handler
+                Set_Default_Handler  Interrupt9_Handler
 
+                ALIGN
 
-; User Initial Stack & Heap
-
-                IF      :DEF:__MICROLIB
-
-                EXPORT  __initial_sp
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-
-                ELSE
-
-                IMPORT  __use_two_region_memory
-                EXPORT  __user_initial_stackheap
-
-__user_initial_stackheap PROC
-                LDR     R0, =  Heap_Mem
-                LDR     R1, =(Stack_Mem + Stack_Size)
-                LDR     R2, = (Heap_Mem +  Heap_Size)
-                LDR     R3, = Stack_Mem
-                BX      LR
-                ENDP
 
-                ALIGN
+; User setup Stack & Heap
 
+                EXPORT   __stack_limit
+                EXPORT   __initial_sp
+                IF       Heap_Size != 0                      ; Heap is provided
+                EXPORT   __heap_base
+                EXPORT   __heap_limit
                 ENDIF
 
-
                 END

CMSIS/CoreValidation/Tests/Cortex-M0/AC5/RTE/Device/ARMCM0/system_ARMCM0.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
  * @file     system_ARMCM0.c
  * @brief    CMSIS Device System Source File for
- *           ARMCM0 Device Series
- * @version  V5.00
- * @date     07. September 2016
+ *           ARMCM0 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -28,15 +28,15 @@
 /*----------------------------------------------------------------------------
   Define clocks
  *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+#define  XTAL            (50000000UL)     /* Oscillator frequency */
 
-#define  SYSTEM_CLOCK    (5U * XTAL)
+#define  SYSTEM_CLOCK    (XTAL / 2U)
 
 
 /*----------------------------------------------------------------------------
   System Core Clock Variable
  *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */
 
 
 /*----------------------------------------------------------------------------

CMSIS/CoreValidation/Tests/Cortex-M0/AC6/RTE/Device/ARMCM0/startup_ARMCM0.s

@@ -1,12 +1,12 @@
 ;/**************************************************************************//**
 ; * @file     startup_ARMCM0.s
 ; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM0 Device Series
-; * @version  V5.00
-; * @date     02. March 2016
+; *           ARMCM0 Device
+; * @version  V5.3.1
+; * @date     09. July 2018
 ; ******************************************************************************/
 ;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
 ; *
 ; * SPDX-License-Identifier: Apache-2.0
 ; *
@@ -23,32 +23,33 @@
 ; * limitations under the License.
 ; */
 
-;/*
 ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
 
 
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Stack Configuration
+;  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
 
-Stack_Size      EQU     0x00000400
+Stack_Size      EQU      0x00000400
 
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
+                AREA     STACK, NOINIT, READWRITE, ALIGN=3
+__stack_limit
+Stack_Mem       SPACE    Stack_Size
 __initial_sp
 
 
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Heap Configuration
+;  <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
 
-Heap_Size       EQU     0x00000C00
+Heap_Size       EQU      0x00000C00
 
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+                IF       Heap_Size != 0                      ; Heap is provided
+                AREA     HEAP, NOINIT, READWRITE, ALIGN=3
 __heap_base
-Heap_Mem        SPACE   Heap_Size
+Heap_Mem        SPACE    Heap_Size
 __heap_limit
+                ENDIF
 
 
                 PRESERVE8
@@ -57,186 +58,102 @@ __heap_limit
 
 ; Vector Table Mapped to Address 0 at Reset
 
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
-                DCD     RTC_IRQHandler            ;  1:  Real Time Clock
-                DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
-                DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
-                DCD     MCIA_IRQHandler           ;  4:  MCIa
-                DCD     MCIB_IRQHandler           ;  5:  MCIb
-                DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
-                DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
-                DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
-                DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
-                DCD     AACI_IRQHandler           ; 10: AACI / AC97
-                DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
-                DCD     ENET_IRQHandler           ; 12: Ethernet
-                DCD     USBDC_IRQHandler          ; 13: USB Device
-                DCD     USBHC_IRQHandler          ; 14: USB Host Controller
-                DCD     CHLCD_IRQHandler          ; 15: Character LCD
-                DCD     FLEXRAY_IRQHandler        ; 16: Flexray
-                DCD     CAN_IRQHandler            ; 17: CAN
-                DCD     LIN_IRQHandler            ; 18: LIN
-                DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
-                DCD     0                         ; 20: Reserved
-                DCD     0                         ; 21: Reserved
-                DCD     0                         ; 22: Reserved
-                DCD     0                         ; 23: Reserved
-                DCD     0                         ; 24: Reserved
-                DCD     0                         ; 25: Reserved
-                DCD     0                         ; 26: Reserved
-                DCD     0                         ; 27: Reserved
-                DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
-                DCD     0                         ; 29: Reserved - CPU FPGA
-                DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
-                DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
+                AREA     RESET, DATA, READONLY
+                EXPORT   __Vectors
+                EXPORT   __Vectors_End
+                EXPORT   __Vectors_Size
+
+__Vectors       DCD      __initial_sp                        ;     Top of Stack
+                DCD      Reset_Handler                       ;     Reset Handler
+                DCD      NMI_Handler                         ; -14 NMI Handler
+                DCD      HardFault_Handler                   ; -13 Hard Fault Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      SVC_Handler                         ;  -5 SVCall Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      PendSV_Handler                      ;  -2 PendSV Handler
+                DCD      SysTick_Handler                     ;  -1 SysTick Handler
+
+                ; Interrupts
+                DCD      Interrupt0_Handler                  ;   0 Interrupt 0
+                DCD      Interrupt1_Handler                  ;   1 Interrupt 1
+                DCD      Interrupt2_Handler                  ;   2 Interrupt 2
+                DCD      Interrupt3_Handler                  ;   3 Interrupt 3
+                DCD      Interrupt4_Handler                  ;   4 Interrupt 4
+                DCD      Interrupt5_Handler                  ;   5 Interrupt 5
+                DCD      Interrupt6_Handler                  ;   6 Interrupt 6
+                DCD      Interrupt7_Handler                  ;   7 Interrupt 7
+                DCD      Interrupt8_Handler                  ;   8 Interrupt 8
+                DCD      Interrupt9_Handler                  ;   9 Interrupt 9
+
+                SPACE    ( 22 * 4)                           ; Interrupts 10 .. 31 are left out
 __Vectors_End
+__Vectors_Size  EQU      __Vectors_End - __Vectors
 
-__Vectors_Size  EQU     __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
 
+                AREA     |.text|, CODE, READONLY
 
 ; Reset Handler
 
 Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  SystemInit
-                IMPORT  __main
-                LDR     R0, =SystemInit
-                BLX     R0
-                LDR     R0, =__main
-                BX      R0
+                EXPORT   Reset_Handler             [WEAK]
+                IMPORT   SystemInit
+                IMPORT   __main
+
+                LDR      R0, =SystemInit
+                BLX      R0
+                LDR      R0, =__main
+                BX       R0
                 ENDP
 
 
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler               [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+                MACRO
+                Set_Default_Handler  $Handler_Name
+$Handler_Name   PROC
+                EXPORT   $Handler_Name             [WEAK]
+                B        .
                 ENDP
+                MEND
 
-Default_Handler PROC
-
-                EXPORT  WDT_IRQHandler            [WEAK]
-                EXPORT  RTC_IRQHandler            [WEAK]
-                EXPORT  TIM0_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler           [WEAK]
-                EXPORT  MCIA_IRQHandler           [WEAK]
-                EXPORT  MCIB_IRQHandler           [WEAK]
-                EXPORT  UART0_IRQHandler          [WEAK]
-                EXPORT  UART1_IRQHandler          [WEAK]
-                EXPORT  UART2_IRQHandler          [WEAK]
-                EXPORT  UART3_IRQHandler          [WEAK]
-                EXPORT  UART4_IRQHandler          [WEAK]
-                EXPORT  AACI_IRQHandler           [WEAK]
-                EXPORT  CLCD_IRQHandler           [WEAK]
-                EXPORT  ENET_IRQHandler           [WEAK]
-                EXPORT  USBDC_IRQHandler          [WEAK]
-                EXPORT  USBHC_IRQHandler          [WEAK]
-                EXPORT  CHLCD_IRQHandler          [WEAK]
-                EXPORT  FLEXRAY_IRQHandler        [WEAK]
-                EXPORT  CAN_IRQHandler            [WEAK]
-                EXPORT  LIN_IRQHandler            [WEAK]
-                EXPORT  I2C_IRQHandler            [WEAK]
-                EXPORT  CPU_CLCD_IRQHandler       [WEAK]
-                EXPORT  SPI_IRQHandler            [WEAK]
-
-WDT_IRQHandler
-RTC_IRQHandler
-TIM0_IRQHandler
-TIM2_IRQHandler
-MCIA_IRQHandler
-MCIB_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-UART3_IRQHandler
-UART4_IRQHandler
-AACI_IRQHandler
-CLCD_IRQHandler
-ENET_IRQHandler
-USBDC_IRQHandler
-USBHC_IRQHandler
-CHLCD_IRQHandler
-FLEXRAY_IRQHandler
-CAN_IRQHandler
-LIN_IRQHandler
-I2C_IRQHandler
-CPU_CLCD_IRQHandler
-SPI_IRQHandler
-                B       .
 
-                ENDP
+; Default exception/interrupt handler
 
+                Set_Default_Handler  NMI_Handler
+                Set_Default_Handler  HardFault_Handler
+                Set_Default_Handler  SVC_Handler
+                Set_Default_Handler  PendSV_Handler
+                Set_Default_Handler  SysTick_Handler
 
-                ALIGN
+                Set_Default_Handler  Interrupt0_Handler
+                Set_Default_Handler  Interrupt1_Handler
+                Set_Default_Handler  Interrupt2_Handler
+                Set_Default_Handler  Interrupt3_Handler
+                Set_Default_Handler  Interrupt4_Handler
+                Set_Default_Handler  Interrupt5_Handler
+                Set_Default_Handler  Interrupt6_Handler
+                Set_Default_Handler  Interrupt7_Handler
+                Set_Default_Handler  Interrupt8_Handler
+                Set_Default_Handler  Interrupt9_Handler
 
+                ALIGN
 
-; User Initial Stack & Heap
-
-                IF      :DEF:__MICROLIB
-
-                EXPORT  __initial_sp
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-
-                ELSE
-
-                IMPORT  __use_two_region_memory
-                EXPORT  __user_initial_stackheap
-
-__user_initial_stackheap PROC
-                LDR     R0, =  Heap_Mem
-                LDR     R1, =(Stack_Mem + Stack_Size)
-                LDR     R2, = (Heap_Mem +  Heap_Size)
-                LDR     R3, = Stack_Mem
-                BX      LR
-                ENDP
 
-                ALIGN
+; User setup Stack & Heap
 
+                EXPORT   __stack_limit
+                EXPORT   __initial_sp
+                IF       Heap_Size != 0                      ; Heap is provided
+                EXPORT   __heap_base
+                EXPORT   __heap_limit
                 ENDIF
 
-
                 END

CMSIS/CoreValidation/Tests/Cortex-M0/AC6/RTE/Device/ARMCM0/system_ARMCM0.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
  * @file     system_ARMCM0.c
  * @brief    CMSIS Device System Source File for
- *           ARMCM0 Device Series
- * @version  V5.00
- * @date     07. September 2016
+ *           ARMCM0 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -28,15 +28,15 @@
 /*----------------------------------------------------------------------------
   Define clocks
  *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+#define  XTAL            (50000000UL)     /* Oscillator frequency */
 
-#define  SYSTEM_CLOCK    (5U * XTAL)
+#define  SYSTEM_CLOCK    (XTAL / 2U)
 
 
 /*----------------------------------------------------------------------------
   System Core Clock Variable
  *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */
 
 
 /*----------------------------------------------------------------------------

CMSIS/CoreValidation/Tests/Cortex-M0/GCC/RTE/Device/ARMCM0/startup_ARMCM0.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
- * @file     startup_ARMCM0.s
+ * @file     startup_ARMCM0.c
  * @brief    CMSIS Core Device Startup File for
- *           ARMCM0 Device Series
- * @version  V5.00
- * @date     26. March 2016
+ *           ARMCM0 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -23,6 +23,10 @@
  * limitations under the License.
  */
 
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
 #include <stdint.h>
 
 
@@ -40,6 +44,7 @@ extern uint32_t __bss_start__;
 extern uint32_t __bss_end__;
 extern uint32_t __StackTop;
 
+
 /*----------------------------------------------------------------------------
   Exception / Interrupt Handler Function Prototype
  *----------------------------------------------------------------------------*/
@@ -49,35 +54,30 @@ typedef void( *pFunc )( void );
 /*----------------------------------------------------------------------------
   External References
  *----------------------------------------------------------------------------*/
-#ifndef __START
-extern void  _start(void) __attribute__((noreturn));    /* PreeMain (C library entry point) */
-#else
-extern int  __START(void) __attribute__((noreturn));    /* main entry point */
-#endif
-
-#ifndef __NO_SYSTEM_INIT
-extern void SystemInit (void);            /* CMSIS System Initialization      */
-#endif
+extern void _start     (void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
+extern void SystemInit (void);                           /* CMSIS System Initialization */
 
 
 /*----------------------------------------------------------------------------
   Internal References
  *----------------------------------------------------------------------------*/
-void Default_Handler(void);                          /* Default empty handler */
-void Reset_Handler(void);                            /* Reset Handler */
+void Default_Handler(void) __attribute__ ((noreturn));
+void Reset_Handler  (void) __attribute__ ((noreturn));
 
 
 /*----------------------------------------------------------------------------
   User Initial Stack & Heap
  *----------------------------------------------------------------------------*/
-#ifndef __STACK_SIZE
-  #define	__STACK_SIZE  0x00000400
-#endif
+//<h> Stack Configuration
+//  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//</h>
+#define  __STACK_SIZE  0x00000400
 static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack")));
 
-#ifndef __HEAP_SIZE
-  #define	__HEAP_SIZE   0x00000C00
-#endif
+//<h> Heap Configuration
+//  <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//</h>
+#define  __HEAP_SIZE   0x00000C00
 #if __HEAP_SIZE > 0
 static uint8_t heap[__HEAP_SIZE]   __attribute__ ((aligned(8), used, section(".heap")));
 #endif
@@ -86,94 +86,59 @@ static uint8_t heap[__HEAP_SIZE]   __attribute__ ((aligned(8), used, section(".h
 /*----------------------------------------------------------------------------
   Exception / Interrupt Handler
  *----------------------------------------------------------------------------*/
-/* Cortex-M0 Processor Exceptions */
-void NMI_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
-void HardFault_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
-void SVC_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
-void PendSV_Handler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void SysTick_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
-
-/* ARMCM0 Specific Interrupts */
-void WDT_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void RTC_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM0_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM2_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIA_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIB_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART0_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART1_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART2_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART4_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void AACI_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void CLCD_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void ENET_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBDC_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBHC_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void CHLCD_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void FLEXRAY_IRQHandler  (void) __attribute__ ((weak, alias("Default_Handler")));
-void CAN_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void LIN_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void I2C_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void CPU_CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART3_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void SPI_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+/* Exceptions */
+void NMI_Handler            (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler            (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler        (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
 
 
 /*----------------------------------------------------------------------------
   Exception / Interrupt Vector table
  *----------------------------------------------------------------------------*/
-const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = {
-  /* Cortex-M0 Exceptions Handler */
-  (pFunc)((uint32_t)&__StackTop),           /*      Initial Stack Pointer     */
-  Reset_Handler,                            /*      Reset Handler             */
-  NMI_Handler,                              /*      NMI Handler               */
-  HardFault_Handler,                        /*      Hard Fault Handler        */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  SVC_Handler,                              /*      SVCall Handler            */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  PendSV_Handler,                           /*      PendSV Handler            */
-  SysTick_Handler,                          /*      SysTick Handler           */
-
-  /* External interrupts */
-  WDT_IRQHandler,                           /*  0:  Watchdog Timer            */
-  RTC_IRQHandler,                           /*  1:  Real Time Clock           */
-  TIM0_IRQHandler,                          /*  2:  Timer0 / Timer1           */
-  TIM2_IRQHandler,                          /*  3:  Timer2 / Timer3           */
-  MCIA_IRQHandler,                          /*  4:  MCIa                      */
-  MCIB_IRQHandler,                          /*  5:  MCIb                      */
-  UART0_IRQHandler,                         /*  6:  UART0 - DUT FPGA          */
-  UART1_IRQHandler,                         /*  7:  UART1 - DUT FPGA          */
-  UART2_IRQHandler,                         /*  8:  UART2 - DUT FPGA          */
-  UART4_IRQHandler,                         /*  9:  UART4 - not connected     */
-  AACI_IRQHandler,                          /* 10: AACI / AC97                */
-  CLCD_IRQHandler,                          /* 11: CLCD Combined Interrupt    */
-  ENET_IRQHandler,                          /* 12: Ethernet                   */
-  USBDC_IRQHandler,                         /* 13: USB Device                 */
-  USBHC_IRQHandler,                         /* 14: USB Host Controller        */
-  CHLCD_IRQHandler,                         /* 15: Character LCD              */
-  FLEXRAY_IRQHandler,                       /* 16: Flexray                    */
-  CAN_IRQHandler,                           /* 17: CAN                        */
-  LIN_IRQHandler,                           /* 18: LIN                        */
-  I2C_IRQHandler,                           /* 19: I2C ADC/DAC                */
-  0,                                        /* 20: Reserved                   */
-  0,                                        /* 21: Reserved                   */
-  0,                                        /* 22: Reserved                   */
-  0,                                        /* 23: Reserved                   */
-  0,                                        /* 24: Reserved                   */
-  0,                                        /* 25: Reserved                   */
-  0,                                        /* 26: Reserved                   */
-  0,                                        /* 27: Reserved                   */
-  CPU_CLCD_IRQHandler,                      /* 28: Reserved - CPU FPGA CLCD   */
-  0,                                        /* 29: Reserved - CPU FPGA        */
-  UART3_IRQHandler,                         /* 30: UART3    - CPU FPGA        */
-  SPI_IRQHandler                            /* 31: SPI Touchscreen - CPU FPGA */
+extern const pFunc __Vectors[ 48];
+       const pFunc __Vectors[ 48] __attribute__ ((section(".vectors"))) = {
+  (pFunc)(&__StackTop),                     /*     Initial Stack Pointer */
+  Reset_Handler,                            /*     Reset Handler */
+  NMI_Handler,                              /* -14 NMI Handler */
+  HardFault_Handler,                        /* -13 Hard Fault Handler */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  SVC_Handler,                              /*  -5 SVCall Handler */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  PendSV_Handler,                           /*  -2 PendSV Handler */
+  SysTick_Handler,                          /*  -1 SysTick Handler */
+
+  /* Interrupts */
+  Interrupt0_Handler,                       /*   0 Interrupt 0 */
+  Interrupt1_Handler,                       /*   1 Interrupt 1 */
+  Interrupt2_Handler,                       /*   2 Interrupt 2 */
+  Interrupt3_Handler,                       /*   3 Interrupt 3 */
+  Interrupt4_Handler,                       /*   4 Interrupt 4 */
+  Interrupt5_Handler,                       /*   5 Interrupt 5 */
+  Interrupt6_Handler,                       /*   6 Interrupt 6 */
+  Interrupt7_Handler,                       /*   7 Interrupt 7 */
+  Interrupt8_Handler,                       /*   8 Interrupt 8 */
+  Interrupt9_Handler                        /*   9 Interrupt 9 */
+                                            /* Interrupts 10 .. 31 are left out */
 };
 
 
@@ -184,41 +149,42 @@ void Reset_Handler(void) {
   uint32_t *pSrc, *pDest;
   uint32_t *pTable __attribute__((unused));
 
-/*  Firstly it copies data from read only memory to RAM. There are two schemes
- *  to copy. One can copy more than one sections. Another can only copy
- *  one section.  The former scheme needs more instructions and read-only
- *  data to implement than the latter.
- *  Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.  */
+/* Firstly it copies data from read only memory to RAM.
+ * There are two schemes to copy. One can copy more than one sections.
+ * Another can copy only one section. The former scheme needs more
+ * instructions and read-only data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.
+ */
 
 #ifdef __STARTUP_COPY_MULTIPLE
-/*  Multiple sections scheme.
+/* Multiple sections scheme.
  *
- *  Between symbol address __copy_table_start__ and __copy_table_end__,
- *  there are array of triplets, each of which specify:
- *    offset 0: LMA of start of a section to copy from
- *    offset 4: VMA of start of a section to copy to
- *    offset 8: size of the section to copy. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ *   offset 0: LMA of start of a section to copy from
+ *   offset 4: VMA of start of a section to copy to
+ *   offset 8: size of the section to copy. Must be multiply of 4
  *
- *  All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
  */
   pTable = &__copy_table_start__;
 
   for (; pTable < &__copy_table_end__; pTable = pTable + 3) {
-		pSrc  = (uint32_t*)*(pTable + 0);
-		pDest = (uint32_t*)*(pTable + 1);
-		for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
+    pSrc  = (uint32_t*)*(pTable + 0);
+    pDest = (uint32_t*)*(pTable + 1);
+    for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
       *pDest++ = *pSrc++;
-		}
-	}
+    }
+  }
 #else
-/*  Single section scheme.
+/* Single section scheme.
  *
- *  The ranges of copy from/to are specified by following symbols
- *    __etext: LMA of start of the section to copy from. Usually end of text
- *    __data_start__: VMA of start of the section to copy to
- *    __data_end__: VMA of end of the section to copy to
+ * The ranges of copy from/to are specified by following symbols
+ *   __etext: LMA of start of the section to copy from. Usually end of text
+ *   __data_start__: VMA of start of the section to copy to
+ *   __data_end__: VMA of end of the section to copy to
  *
- *  All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
  */
   pSrc  = &__etext;
   pDest = &__data_start__;
@@ -228,40 +194,40 @@ void Reset_Handler(void) {
   }
 #endif /*__STARTUP_COPY_MULTIPLE */
 
-/*  This part of work usually is done in C library startup code. Otherwise,
- *  define this macro to enable it in this startup.
+/* This part of work usually is done in C library startup code.
+ * Otherwise, define this macro to enable it in this startup.
  *
- *  There are two schemes too. One can clear multiple BSS sections. Another
- *  can only clear one section. The former is more size expensive than the
- *  latter.
+ * There are two schemes too.
+ * One can clear multiple BSS sections. Another can only clear one section.
+ * The former is more size expensive than the latter.
  *
- *  Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- *  Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
  */
 #ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/*  Multiple sections scheme.
+/* Multiple sections scheme.
  *
- *  Between symbol address __copy_table_start__ and __copy_table_end__,
- *  there are array of tuples specifying:
- *    offset 0: Start of a BSS section
- *    offset 4: Size of this BSS section. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ *   offset 0: Start of a BSS section
+ *   offset 4: Size of this BSS section. Must be multiply of 4
  */
   pTable = &__zero_table_start__;
 
   for (; pTable < &__zero_table_end__; pTable = pTable + 2) {
-		pDest = (uint32_t*)*(pTable + 0);
-		for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
+    pDest = (uint32_t*)*(pTable + 0);
+    for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
       *pDest++ = 0;
-		}
-	}
+    }
+  }
 #elif defined (__STARTUP_CLEAR_BSS)
-/*  Single BSS section scheme.
+/* Single BSS section scheme.
  *
- *  The BSS section is specified by following symbols
- *    __bss_start__: start of the BSS section.
- *    __bss_end__: end of the BSS section.
+ * The BSS section is specified by following symbols
+ *   __bss_start__: start of the BSS section.
+ *   __bss_end__: end of the BSS section.
  *
- *  Both addresses must be aligned to 4 bytes boundary.
+ * Both addresses must be aligned to 4 bytes boundary.
  */
   pDest = &__bss_start__;
 
@@ -270,15 +236,8 @@ void Reset_Handler(void) {
   }
 #endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
 
-#ifndef __NO_SYSTEM_INIT
-	SystemInit();
-#endif
-
-#ifndef __START
-#define __START _start
-#endif
-	__START();
-
+  SystemInit();                             /* CMSIS System Initialization */
+  _start();                                 /* Enter PreeMain (C library entry point) */
 }
 
 
@@ -287,5 +246,5 @@ void Reset_Handler(void) {
  *----------------------------------------------------------------------------*/
 void Default_Handler(void) {
 
-	while(1);
+  while(1);
 }

CMSIS/CoreValidation/Tests/Cortex-M0/GCC/RTE/Device/ARMCM0/system_ARMCM0.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
  * @file     system_ARMCM0.c
  * @brief    CMSIS Device System Source File for
- *           ARMCM0 Device Series
- * @version  V5.00
- * @date     07. September 2016
+ *           ARMCM0 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -28,15 +28,15 @@
 /*----------------------------------------------------------------------------
   Define clocks
  *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+#define  XTAL            (50000000UL)     /* Oscillator frequency */
 
-#define  SYSTEM_CLOCK    (5U * XTAL)
+#define  SYSTEM_CLOCK    (XTAL / 2U)
 
 
 /*----------------------------------------------------------------------------
   System Core Clock Variable
  *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */
 
 
 /*----------------------------------------------------------------------------

CMSIS/CoreValidation/Tests/Cortex-M0/IAR/RTE/Device/ARMCM0/startup_ARMCM0.s

@@ -1,12 +1,12 @@
 ;/**************************************************************************//**
 ; * @file     startup_ARMCM0.s
 ; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM0 Device Series
-; * @version  V5.00
-; * @date     08. March 2016
+; *           ARMCM0 Device
+; * @version  V5.3.1
+; * @date     09. July 2018
 ; ******************************************************************************/
 ;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
 ; *
 ; * SPDX-License-Identifier: Apache-2.0
 ; *
@@ -39,232 +39,109 @@
 ; Cortex-M version
 ;
 
-        MODULE  ?cstartup
+                MODULE   ?cstartup
 
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
+                ;; Forward declaration of sections.
+                SECTION  CSTACK:DATA:NOROOT(3)
 
-        SECTION .intvec:CODE:NOROOT(2)
+                SECTION  .intvec:CODE:NOROOT(2)
 
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit
-        PUBLIC  __vector_table
-        PUBLIC  __vector_table_0x1c
-        PUBLIC  __Vectors
-        PUBLIC  __Vectors_End
-        PUBLIC  __Vectors_Size
+                EXTERN   __iar_program_start
+                EXTERN   SystemInit
+                PUBLIC   __vector_table
+                PUBLIC   __vector_table_0x1c
+                PUBLIC   __Vectors
+                PUBLIC   __Vectors_End
+                PUBLIC   __Vectors_Size
 
-        DATA
+                DATA
 
 __vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler
-
-        DCD     NMI_Handler
-        DCD     HardFault_Handler
-        DCD     0
-        DCD     0
-        DCD     0
+                DCD      sfe(CSTACK)                         ;     Top of Stack
+                DCD      Reset_Handler                       ;     Reset Handler
+                DCD      NMI_Handler                         ; -14 NMI Handler
+                DCD      HardFault_Handler                   ; -13 Hard Fault Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
 __vector_table_0x1c
-        DCD     0
-        DCD     0
-        DCD     0
-        DCD     0
-        DCD     SVC_Handler
-        DCD     0
-        DCD     0
-        DCD     PendSV_Handler
-        DCD     SysTick_Handler
-
-        ; External Interrupts
-        DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
-        DCD     RTC_IRQHandler            ;  1:  Real Time Clock
-        DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
-        DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
-        DCD     MCIA_IRQHandler           ;  4:  MCIa
-        DCD     MCIB_IRQHandler           ;  5:  MCIb
-        DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
-        DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
-        DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
-        DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
-        DCD     AACI_IRQHandler           ; 10: AACI / AC97
-        DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
-        DCD     ENET_IRQHandler           ; 12: Ethernet
-        DCD     USBDC_IRQHandler          ; 13: USB Device
-        DCD     USBHC_IRQHandler          ; 14: USB Host Controller
-        DCD     CHLCD_IRQHandler          ; 15: Character LCD
-        DCD     FLEXRAY_IRQHandler        ; 16: Flexray
-        DCD     CAN_IRQHandler            ; 17: CAN
-        DCD     LIN_IRQHandler            ; 18: LIN
-        DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
-        DCD     0                         ; 20: Reserved
-        DCD     0                         ; 21: Reserved
-        DCD     0                         ; 22: Reserved
-        DCD     0                         ; 23: Reserved
-        DCD     0                         ; 24: Reserved
-        DCD     0                         ; 25: Reserved
-        DCD     0                         ; 26: Reserved
-        DCD     0                         ; 27: Reserved
-        DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
-        DCD     0                         ; 29: Reserved - CPU FPGA
-        DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
-        DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      SVC_Handler                         ;  -5 SVCall Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      PendSV_Handler                      ;  -2 PendSV Handler
+                DCD      SysTick_Handler                     ;  -1 SysTick Handler
+
+                ; Interrupts
+                DCD      Interrupt0_Handler                  ;   0 Interrupt 0
+                DCD      Interrupt1_Handler                  ;   1 Interrupt 1
+                DCD      Interrupt2_Handler                  ;   2 Interrupt 2
+                DCD      Interrupt3_Handler                  ;   3 Interrupt 3
+                DCD      Interrupt4_Handler                  ;   4 Interrupt 4
+                DCD      Interrupt5_Handler                  ;   5 Interrupt 5
+                DCD      Interrupt6_Handler                  ;   6 Interrupt 6
+                DCD      Interrupt7_Handler                  ;   7 Interrupt 7
+                DCD      Interrupt8_Handler                  ;   8 Interrupt 8
+                DCD      Interrupt9_Handler                  ;   9 Interrupt 9
+
+                DS32    ( 22)                                ; Interrupts 10 .. 31 are left out
 __Vectors_End
 
-__Vectors       EQU   __vector_table
-__Vectors_Size  EQU   __Vectors_End - __Vectors
+__Vectors       EQU      __vector_table
+__Vectors_Size  EQU      __Vectors_End - __Vectors
 
 
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
+                THUMB
 
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
+; Reset Handler
 
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
+                PUBWEAK  Reset_Handler
+                SECTION  .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+                LDR      R0, =SystemInit
+                BLX      R0
+                LDR      R0, =__iar_program_start
+                BX       R0
+
+
+                PUBWEAK NMI_Handler
+                PUBWEAK HardFault_Handler
+                PUBWEAK SVC_Handler
+                PUBWEAK PendSV_Handler
+                PUBWEAK SysTick_Handler
+
+                PUBWEAK Interrupt0_Handler
+                PUBWEAK Interrupt1_Handler
+                PUBWEAK Interrupt2_Handler
+                PUBWEAK Interrupt3_Handler
+                PUBWEAK Interrupt4_Handler
+                PUBWEAK Interrupt5_Handler
+                PUBWEAK Interrupt6_Handler
+                PUBWEAK Interrupt7_Handler
+                PUBWEAK Interrupt8_Handler
+                PUBWEAK Interrupt9_Handler
+                SECTION .text:CODE:REORDER:NOROOT(1)
 NMI_Handler
-        B NMI_Handler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 HardFault_Handler
-        B HardFault_Handler
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 SVC_Handler
-        B SVC_Handler
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 SysTick_Handler
-        B SysTick_Handler
-
-        PUBWEAK WDT_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WDT_IRQHandler
-        B WDT_IRQHandler
-
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-
-        PUBWEAK TIM0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM0_IRQHandler
-        B TIM0_IRQHandler
-
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-
-        PUBWEAK MCIA_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MCIA_IRQHandler
-        B MCIA_IRQHandler
-
-        PUBWEAK MCIB_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MCIB_IRQHandler
-        B MCIB_IRQHandler
-
-        PUBWEAK UART0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART0_IRQHandler
-        B UART0_IRQHandler
-
-        PUBWEAK UART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART1_IRQHandler
-        B UART1_IRQHandler
-
-        PUBWEAK UART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART2_IRQHandler
-        B UART2_IRQHandler
-
-        PUBWEAK UART4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
-        B UART4_IRQHandler
-
-        PUBWEAK AACI_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-AACI_IRQHandler
-        B AACI_IRQHandler
-
-        PUBWEAK CLCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CLCD_IRQHandler
-        B CLCD_IRQHandler
-
-        PUBWEAK ENET_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ENET_IRQHandler
-        B ENET_IRQHandler
-
-        PUBWEAK USBDC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USBDC_IRQHandler
-        B USBDC_IRQHandler
-
-        PUBWEAK USBHC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USBHC_IRQHandler
-        B USBHC_IRQHandler
-
-        PUBWEAK CHLCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CHLCD_IRQHandler
-        B CHLCD_IRQHandler
-
-        PUBWEAK FLEXRAY_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLEXRAY_IRQHandler
-        B FLEXRAY_IRQHandler
-
-        PUBWEAK CAN_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN_IRQHandler
-        B CAN_IRQHandler
-
-        PUBWEAK LIN_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-LIN_IRQHandler
-        B LIN_IRQHandler
-
-        PUBWEAK I2C_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C_IRQHandler
-        B I2C_IRQHandler
-
-        PUBWEAK CPU_CLCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CPU_CLCD_IRQHandler
-        B CPU_CLCD_IRQHandler
-
-        PUBWEAK UART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART3_IRQHandler
-        B UART3_IRQHandler
-
-        PUBWEAK SPI_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI_IRQHandler
-        B SPI_IRQHandler
 
-        END
+Interrupt0_Handler
+Interrupt1_Handler
+Interrupt2_Handler
+Interrupt3_Handler
+Interrupt4_Handler
+Interrupt5_Handler
+Interrupt6_Handler
+Interrupt7_Handler
+Interrupt8_Handler
+Interrupt9_Handler
+Default_Handler
+                B        .
+
+
+                END

CMSIS/CoreValidation/Tests/Cortex-M0/IAR/RTE/Device/ARMCM0/system_ARMCM0.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
  * @file     system_ARMCM0.c
  * @brief    CMSIS Device System Source File for
- *           ARMCM0 Device Series
- * @version  V5.00
- * @date     07. September 2016
+ *           ARMCM0 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -28,15 +28,15 @@
 /*----------------------------------------------------------------------------
   Define clocks
  *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+#define  XTAL            (50000000UL)     /* Oscillator frequency */
 
-#define  SYSTEM_CLOCK    (5U * XTAL)
+#define  SYSTEM_CLOCK    (XTAL / 2U)
 
 
 /*----------------------------------------------------------------------------
   System Core Clock Variable
  *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */
 
 
 /*----------------------------------------------------------------------------

CMSIS/CoreValidation/Tests/Cortex-M0plus/AC5/RTE/Device/ARMCM0P_MPU/startup_ARMCM0plus.s

@@ -1,12 +1,12 @@
 ;/**************************************************************************//**
 ; * @file     startup_ARMCM0plus.s
 ; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM0plus Device Series
-; * @version  V5.00
-; * @date     02. March 2016
+; *           ARMCM0plus Device
+; * @version  V5.3.1
+; * @date     09. July 2018
 ; ******************************************************************************/
 ;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
 ; *
 ; * SPDX-License-Identifier: Apache-2.0
 ; *
@@ -23,32 +23,33 @@
 ; * limitations under the License.
 ; */
 
-;/*
 ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
 
 
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Stack Configuration
+;  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
 
-Stack_Size      EQU     0x00000400
+Stack_Size      EQU      0x00000400
 
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
+                AREA     STACK, NOINIT, READWRITE, ALIGN=3
+__stack_limit
+Stack_Mem       SPACE    Stack_Size
 __initial_sp
 
 
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Heap Configuration
+;  <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
 
-Heap_Size       EQU     0x00000C00
+Heap_Size       EQU      0x00000C00
 
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+                IF       Heap_Size != 0                      ; Heap is provided
+                AREA     HEAP, NOINIT, READWRITE, ALIGN=3
 __heap_base
-Heap_Mem        SPACE   Heap_Size
+Heap_Mem        SPACE    Heap_Size
 __heap_limit
+                ENDIF
 
 
                 PRESERVE8
@@ -57,186 +58,102 @@ __heap_limit
 
 ; Vector Table Mapped to Address 0 at Reset
 
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
-                DCD     RTC_IRQHandler            ;  1:  Real Time Clock
-                DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
-                DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
-                DCD     MCIA_IRQHandler           ;  4:  MCIa
-                DCD     MCIB_IRQHandler           ;  5:  MCIb
-                DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
-                DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
-                DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
-                DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
-                DCD     AACI_IRQHandler           ; 10: AACI / AC97
-                DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
-                DCD     ENET_IRQHandler           ; 12: Ethernet
-                DCD     USBDC_IRQHandler          ; 13: USB Device
-                DCD     USBHC_IRQHandler          ; 14: USB Host Controller
-                DCD     CHLCD_IRQHandler          ; 15: Character LCD
-                DCD     FLEXRAY_IRQHandler        ; 16: Flexray
-                DCD     CAN_IRQHandler            ; 17: CAN
-                DCD     LIN_IRQHandler            ; 18: LIN
-                DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
-                DCD     0                         ; 20: Reserved
-                DCD     0                         ; 21: Reserved
-                DCD     0                         ; 22: Reserved
-                DCD     0                         ; 23: Reserved
-                DCD     0                         ; 24: Reserved
-                DCD     0                         ; 25: Reserved
-                DCD     0                         ; 26: Reserved
-                DCD     0                         ; 27: Reserved
-                DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
-                DCD     0                         ; 29: Reserved - CPU FPGA
-                DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
-                DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
+                AREA     RESET, DATA, READONLY
+                EXPORT   __Vectors
+                EXPORT   __Vectors_End
+                EXPORT   __Vectors_Size
+
+__Vectors       DCD      __initial_sp                        ;     Top of Stack
+                DCD      Reset_Handler                       ;     Reset Handler
+                DCD      NMI_Handler                         ; -14 NMI Handler
+                DCD      HardFault_Handler                   ; -13 Hard Fault Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      SVC_Handler                         ;  -5 SVCall Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      PendSV_Handler                      ;  -2 PendSV Handler
+                DCD      SysTick_Handler                     ;  -1 SysTick Handler
+
+                ; Interrupts
+                DCD      Interrupt0_Handler                  ;   0 Interrupt 0
+                DCD      Interrupt1_Handler                  ;   1 Interrupt 1
+                DCD      Interrupt2_Handler                  ;   2 Interrupt 2
+                DCD      Interrupt3_Handler                  ;   3 Interrupt 3
+                DCD      Interrupt4_Handler                  ;   4 Interrupt 4
+                DCD      Interrupt5_Handler                  ;   5 Interrupt 5
+                DCD      Interrupt6_Handler                  ;   6 Interrupt 6
+                DCD      Interrupt7_Handler                  ;   7 Interrupt 7
+                DCD      Interrupt8_Handler                  ;   8 Interrupt 8
+                DCD      Interrupt9_Handler                  ;   9 Interrupt 9
+
+                SPACE    ( 22 * 4)                           ; Interrupts 10 .. 31 are left out
 __Vectors_End
+__Vectors_Size  EQU      __Vectors_End - __Vectors
 
-__Vectors_Size  EQU     __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
 
+                AREA     |.text|, CODE, READONLY
 
 ; Reset Handler
 
 Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  SystemInit
-                IMPORT  __main
-                LDR     R0, =SystemInit
-                BLX     R0
-                LDR     R0, =__main
-                BX      R0
+                EXPORT   Reset_Handler             [WEAK]
+                IMPORT   SystemInit
+                IMPORT   __main
+
+                LDR      R0, =SystemInit
+                BLX      R0
+                LDR      R0, =__main
+                BX       R0
                 ENDP
 
 
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler               [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+                MACRO
+                Set_Default_Handler  $Handler_Name
+$Handler_Name   PROC
+                EXPORT   $Handler_Name             [WEAK]
+                B        .
                 ENDP
+                MEND
 
-Default_Handler PROC
-
-                EXPORT  WDT_IRQHandler            [WEAK]
-                EXPORT  RTC_IRQHandler            [WEAK]
-                EXPORT  TIM0_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler           [WEAK]
-                EXPORT  MCIA_IRQHandler           [WEAK]
-                EXPORT  MCIB_IRQHandler           [WEAK]
-                EXPORT  UART0_IRQHandler          [WEAK]
-                EXPORT  UART1_IRQHandler          [WEAK]
-                EXPORT  UART2_IRQHandler          [WEAK]
-                EXPORT  UART3_IRQHandler          [WEAK]
-                EXPORT  UART4_IRQHandler          [WEAK]
-                EXPORT  AACI_IRQHandler           [WEAK]
-                EXPORT  CLCD_IRQHandler           [WEAK]
-                EXPORT  ENET_IRQHandler           [WEAK]
-                EXPORT  USBDC_IRQHandler          [WEAK]
-                EXPORT  USBHC_IRQHandler          [WEAK]
-                EXPORT  CHLCD_IRQHandler          [WEAK]
-                EXPORT  FLEXRAY_IRQHandler        [WEAK]
-                EXPORT  CAN_IRQHandler            [WEAK]
-                EXPORT  LIN_IRQHandler            [WEAK]
-                EXPORT  I2C_IRQHandler            [WEAK]
-                EXPORT  CPU_CLCD_IRQHandler       [WEAK]
-                EXPORT  SPI_IRQHandler            [WEAK]
-
-WDT_IRQHandler
-RTC_IRQHandler
-TIM0_IRQHandler
-TIM2_IRQHandler
-MCIA_IRQHandler
-MCIB_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-UART3_IRQHandler
-UART4_IRQHandler
-AACI_IRQHandler
-CLCD_IRQHandler
-ENET_IRQHandler
-USBDC_IRQHandler
-USBHC_IRQHandler
-CHLCD_IRQHandler
-FLEXRAY_IRQHandler
-CAN_IRQHandler
-LIN_IRQHandler
-I2C_IRQHandler
-CPU_CLCD_IRQHandler
-SPI_IRQHandler
-                B       .
 
-                ENDP
+; Default exception/interrupt handler
 
+                Set_Default_Handler  NMI_Handler
+                Set_Default_Handler  HardFault_Handler
+                Set_Default_Handler  SVC_Handler
+                Set_Default_Handler  PendSV_Handler
+                Set_Default_Handler  SysTick_Handler
 
-                ALIGN
+                Set_Default_Handler  Interrupt0_Handler
+                Set_Default_Handler  Interrupt1_Handler
+                Set_Default_Handler  Interrupt2_Handler
+                Set_Default_Handler  Interrupt3_Handler
+                Set_Default_Handler  Interrupt4_Handler
+                Set_Default_Handler  Interrupt5_Handler
+                Set_Default_Handler  Interrupt6_Handler
+                Set_Default_Handler  Interrupt7_Handler
+                Set_Default_Handler  Interrupt8_Handler
+                Set_Default_Handler  Interrupt9_Handler
 
+                ALIGN
 
-; User Initial Stack & Heap
-
-                IF      :DEF:__MICROLIB
-
-                EXPORT  __initial_sp
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-
-                ELSE
-
-                IMPORT  __use_two_region_memory
-                EXPORT  __user_initial_stackheap
-
-__user_initial_stackheap PROC
-                LDR     R0, =  Heap_Mem
-                LDR     R1, =(Stack_Mem + Stack_Size)
-                LDR     R2, = (Heap_Mem +  Heap_Size)
-                LDR     R3, = Stack_Mem
-                BX      LR
-                ENDP
 
-                ALIGN
+; User setup Stack & Heap
 
+                EXPORT   __stack_limit
+                EXPORT   __initial_sp
+                IF       Heap_Size != 0                      ; Heap is provided
+                EXPORT   __heap_base
+                EXPORT   __heap_limit
                 ENDIF
 
-
                 END

CMSIS/CoreValidation/Tests/Cortex-M0plus/AC5/RTE/Device/ARMCM0P_MPU/system_ARMCM0plus.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
  * @file     system_ARMCM0plus.c
  * @brief    CMSIS Device System Source File for
- *           ARMCM0plus Device Series
- * @version  V5.00
- * @date     07. September 2016
+ *           ARMCM0plus Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -28,9 +28,9 @@
 /*----------------------------------------------------------------------------
   Define clocks
  *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+#define  XTAL            (50000000UL)     /* Oscillator frequency */
 
-#define  SYSTEM_CLOCK    (5U * XTAL)
+#define  SYSTEM_CLOCK    (XTAL / 2U)
 
 
 /*----------------------------------------------------------------------------
@@ -43,7 +43,7 @@
 /*----------------------------------------------------------------------------
   System Core Clock Variable
  *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */
 
 
 /*----------------------------------------------------------------------------

CMSIS/CoreValidation/Tests/Cortex-M0plus/AC6/RTE/Device/ARMCM0P_MPU/startup_ARMCM0plus.s

@@ -1,12 +1,12 @@
 ;/**************************************************************************//**
 ; * @file     startup_ARMCM0plus.s
 ; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM0plus Device Series
-; * @version  V5.00
-; * @date     02. March 2016
+; *           ARMCM0plus Device
+; * @version  V5.3.1
+; * @date     09. July 2018
 ; ******************************************************************************/
 ;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
 ; *
 ; * SPDX-License-Identifier: Apache-2.0
 ; *
@@ -23,32 +23,33 @@
 ; * limitations under the License.
 ; */
 
-;/*
 ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
 
 
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Stack Configuration
+;  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
 
-Stack_Size      EQU     0x00000400
+Stack_Size      EQU      0x00000400
 
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
+                AREA     STACK, NOINIT, READWRITE, ALIGN=3
+__stack_limit
+Stack_Mem       SPACE    Stack_Size
 __initial_sp
 
 
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Heap Configuration
+;  <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
 
-Heap_Size       EQU     0x00000C00
+Heap_Size       EQU      0x00000C00
 
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+                IF       Heap_Size != 0                      ; Heap is provided
+                AREA     HEAP, NOINIT, READWRITE, ALIGN=3
 __heap_base
-Heap_Mem        SPACE   Heap_Size
+Heap_Mem        SPACE    Heap_Size
 __heap_limit
+                ENDIF
 
 
                 PRESERVE8
@@ -57,186 +58,102 @@ __heap_limit
 
 ; Vector Table Mapped to Address 0 at Reset
 
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
-                DCD     RTC_IRQHandler            ;  1:  Real Time Clock
-                DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
-                DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
-                DCD     MCIA_IRQHandler           ;  4:  MCIa
-                DCD     MCIB_IRQHandler           ;  5:  MCIb
-                DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
-                DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
-                DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
-                DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
-                DCD     AACI_IRQHandler           ; 10: AACI / AC97
-                DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
-                DCD     ENET_IRQHandler           ; 12: Ethernet
-                DCD     USBDC_IRQHandler          ; 13: USB Device
-                DCD     USBHC_IRQHandler          ; 14: USB Host Controller
-                DCD     CHLCD_IRQHandler          ; 15: Character LCD
-                DCD     FLEXRAY_IRQHandler        ; 16: Flexray
-                DCD     CAN_IRQHandler            ; 17: CAN
-                DCD     LIN_IRQHandler            ; 18: LIN
-                DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
-                DCD     0                         ; 20: Reserved
-                DCD     0                         ; 21: Reserved
-                DCD     0                         ; 22: Reserved
-                DCD     0                         ; 23: Reserved
-                DCD     0                         ; 24: Reserved
-                DCD     0                         ; 25: Reserved
-                DCD     0                         ; 26: Reserved
-                DCD     0                         ; 27: Reserved
-                DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
-                DCD     0                         ; 29: Reserved - CPU FPGA
-                DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
-                DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
+                AREA     RESET, DATA, READONLY
+                EXPORT   __Vectors
+                EXPORT   __Vectors_End
+                EXPORT   __Vectors_Size
+
+__Vectors       DCD      __initial_sp                        ;     Top of Stack
+                DCD      Reset_Handler                       ;     Reset Handler
+                DCD      NMI_Handler                         ; -14 NMI Handler
+                DCD      HardFault_Handler                   ; -13 Hard Fault Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      SVC_Handler                         ;  -5 SVCall Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      PendSV_Handler                      ;  -2 PendSV Handler
+                DCD      SysTick_Handler                     ;  -1 SysTick Handler
+
+                ; Interrupts
+                DCD      Interrupt0_Handler                  ;   0 Interrupt 0
+                DCD      Interrupt1_Handler                  ;   1 Interrupt 1
+                DCD      Interrupt2_Handler                  ;   2 Interrupt 2
+                DCD      Interrupt3_Handler                  ;   3 Interrupt 3
+                DCD      Interrupt4_Handler                  ;   4 Interrupt 4
+                DCD      Interrupt5_Handler                  ;   5 Interrupt 5
+                DCD      Interrupt6_Handler                  ;   6 Interrupt 6
+                DCD      Interrupt7_Handler                  ;   7 Interrupt 7
+                DCD      Interrupt8_Handler                  ;   8 Interrupt 8
+                DCD      Interrupt9_Handler                  ;   9 Interrupt 9
+
+                SPACE    ( 22 * 4)                           ; Interrupts 10 .. 31 are left out
 __Vectors_End
+__Vectors_Size  EQU      __Vectors_End - __Vectors
 
-__Vectors_Size  EQU     __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
 
+                AREA     |.text|, CODE, READONLY
 
 ; Reset Handler
 
 Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  SystemInit
-                IMPORT  __main
-                LDR     R0, =SystemInit
-                BLX     R0
-                LDR     R0, =__main
-                BX      R0
+                EXPORT   Reset_Handler             [WEAK]
+                IMPORT   SystemInit
+                IMPORT   __main
+
+                LDR      R0, =SystemInit
+                BLX      R0
+                LDR      R0, =__main
+                BX       R0
                 ENDP
 
 
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler               [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+                MACRO
+                Set_Default_Handler  $Handler_Name
+$Handler_Name   PROC
+                EXPORT   $Handler_Name             [WEAK]
+                B        .
                 ENDP
+                MEND
 
-Default_Handler PROC
-
-                EXPORT  WDT_IRQHandler            [WEAK]
-                EXPORT  RTC_IRQHandler            [WEAK]
-                EXPORT  TIM0_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler           [WEAK]
-                EXPORT  MCIA_IRQHandler           [WEAK]
-                EXPORT  MCIB_IRQHandler           [WEAK]
-                EXPORT  UART0_IRQHandler          [WEAK]
-                EXPORT  UART1_IRQHandler          [WEAK]
-                EXPORT  UART2_IRQHandler          [WEAK]
-                EXPORT  UART3_IRQHandler          [WEAK]
-                EXPORT  UART4_IRQHandler          [WEAK]
-                EXPORT  AACI_IRQHandler           [WEAK]
-                EXPORT  CLCD_IRQHandler           [WEAK]
-                EXPORT  ENET_IRQHandler           [WEAK]
-                EXPORT  USBDC_IRQHandler          [WEAK]
-                EXPORT  USBHC_IRQHandler          [WEAK]
-                EXPORT  CHLCD_IRQHandler          [WEAK]
-                EXPORT  FLEXRAY_IRQHandler        [WEAK]
-                EXPORT  CAN_IRQHandler            [WEAK]
-                EXPORT  LIN_IRQHandler            [WEAK]
-                EXPORT  I2C_IRQHandler            [WEAK]
-                EXPORT  CPU_CLCD_IRQHandler       [WEAK]
-                EXPORT  SPI_IRQHandler            [WEAK]
-
-WDT_IRQHandler
-RTC_IRQHandler
-TIM0_IRQHandler
-TIM2_IRQHandler
-MCIA_IRQHandler
-MCIB_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-UART3_IRQHandler
-UART4_IRQHandler
-AACI_IRQHandler
-CLCD_IRQHandler
-ENET_IRQHandler
-USBDC_IRQHandler
-USBHC_IRQHandler
-CHLCD_IRQHandler
-FLEXRAY_IRQHandler
-CAN_IRQHandler
-LIN_IRQHandler
-I2C_IRQHandler
-CPU_CLCD_IRQHandler
-SPI_IRQHandler
-                B       .
 
-                ENDP
+; Default exception/interrupt handler
 
+                Set_Default_Handler  NMI_Handler
+                Set_Default_Handler  HardFault_Handler
+                Set_Default_Handler  SVC_Handler
+                Set_Default_Handler  PendSV_Handler
+                Set_Default_Handler  SysTick_Handler
 
-                ALIGN
+                Set_Default_Handler  Interrupt0_Handler
+                Set_Default_Handler  Interrupt1_Handler
+                Set_Default_Handler  Interrupt2_Handler
+                Set_Default_Handler  Interrupt3_Handler
+                Set_Default_Handler  Interrupt4_Handler
+                Set_Default_Handler  Interrupt5_Handler
+                Set_Default_Handler  Interrupt6_Handler
+                Set_Default_Handler  Interrupt7_Handler
+                Set_Default_Handler  Interrupt8_Handler
+                Set_Default_Handler  Interrupt9_Handler
 
+                ALIGN
 
-; User Initial Stack & Heap
-
-                IF      :DEF:__MICROLIB
-
-                EXPORT  __initial_sp
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-
-                ELSE
-
-                IMPORT  __use_two_region_memory
-                EXPORT  __user_initial_stackheap
-
-__user_initial_stackheap PROC
-                LDR     R0, =  Heap_Mem
-                LDR     R1, =(Stack_Mem + Stack_Size)
-                LDR     R2, = (Heap_Mem +  Heap_Size)
-                LDR     R3, = Stack_Mem
-                BX      LR
-                ENDP
 
-                ALIGN
+; User setup Stack & Heap
 
+                EXPORT   __stack_limit
+                EXPORT   __initial_sp
+                IF       Heap_Size != 0                      ; Heap is provided
+                EXPORT   __heap_base
+                EXPORT   __heap_limit
                 ENDIF
 
-
                 END

CMSIS/CoreValidation/Tests/Cortex-M0plus/AC6/RTE/Device/ARMCM0P_MPU/system_ARMCM0plus.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
  * @file     system_ARMCM0plus.c
  * @brief    CMSIS Device System Source File for
- *           ARMCM0plus Device Series
- * @version  V5.00
- * @date     07. September 2016
+ *           ARMCM0plus Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -28,9 +28,9 @@
 /*----------------------------------------------------------------------------
   Define clocks
  *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+#define  XTAL            (50000000UL)     /* Oscillator frequency */
 
-#define  SYSTEM_CLOCK    (5U * XTAL)
+#define  SYSTEM_CLOCK    (XTAL / 2U)
 
 
 /*----------------------------------------------------------------------------
@@ -43,7 +43,7 @@
 /*----------------------------------------------------------------------------
   System Core Clock Variable
  *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */
 
 
 /*----------------------------------------------------------------------------

CMSIS/CoreValidation/Tests/Cortex-M0plus/GCC/RTE/Device/ARMCM0P_MPU/startup_ARMCM0plus.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
  * @file     startup_ARMCM0plus.s
  * @brief    CMSIS Core Device Startup File for
- *           ARMCM0plus Device Series
- * @version  V5.00
- * @date     26. March 2016
+ *           ARMCM0plus Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -23,6 +23,10 @@
  * limitations under the License.
  */
 
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
 #include <stdint.h>
 
 
@@ -40,6 +44,7 @@ extern uint32_t __bss_start__;
 extern uint32_t __bss_end__;
 extern uint32_t __StackTop;
 
+
 /*----------------------------------------------------------------------------
   Exception / Interrupt Handler Function Prototype
  *----------------------------------------------------------------------------*/
@@ -49,35 +54,30 @@ typedef void( *pFunc )( void );
 /*----------------------------------------------------------------------------
   External References
  *----------------------------------------------------------------------------*/
-#ifndef __START
-extern void  _start(void) __attribute__((noreturn));    /* PreeMain (C library entry point) */
-#else
-extern int  __START(void) __attribute__((noreturn));    /* main entry point */
-#endif
-
-#ifndef __NO_SYSTEM_INIT
-extern void SystemInit (void);            /* CMSIS System Initialization      */
-#endif
+extern void _start     (void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
+extern void SystemInit (void);                           /* CMSIS System Initialization */
 
 
 /*----------------------------------------------------------------------------
   Internal References
  *----------------------------------------------------------------------------*/
-void Default_Handler(void);                          /* Default empty handler */
-void Reset_Handler(void);                            /* Reset Handler */
+void Default_Handler(void) __attribute__ ((noreturn));
+void Reset_Handler  (void) __attribute__ ((noreturn));
 
 
 /*----------------------------------------------------------------------------
   User Initial Stack & Heap
  *----------------------------------------------------------------------------*/
-#ifndef __STACK_SIZE
-  #define	__STACK_SIZE  0x00000400
-#endif
+//<h> Stack Configuration
+//  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//</h>
+#define  __STACK_SIZE  0x00000400
 static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack")));
 
-#ifndef __HEAP_SIZE
-  #define	__HEAP_SIZE   0x00000C00
-#endif
+//<h> Heap Configuration
+//  <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//</h>
+#define  __HEAP_SIZE   0x00000C00
 #if __HEAP_SIZE > 0
 static uint8_t heap[__HEAP_SIZE]   __attribute__ ((aligned(8), used, section(".heap")));
 #endif
@@ -86,94 +86,59 @@ static uint8_t heap[__HEAP_SIZE]   __attribute__ ((aligned(8), used, section(".h
 /*----------------------------------------------------------------------------
   Exception / Interrupt Handler
  *----------------------------------------------------------------------------*/
-/* Cortex-M0+ Processor Exceptions */
-void NMI_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
-void HardFault_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
-void SVC_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
-void PendSV_Handler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void SysTick_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
-
-/* ARMCM0plus Specific Interrupts */
-void WDT_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void RTC_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM0_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM2_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIA_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIB_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART0_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART1_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART2_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART4_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void AACI_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void CLCD_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void ENET_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBDC_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBHC_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void CHLCD_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void FLEXRAY_IRQHandler  (void) __attribute__ ((weak, alias("Default_Handler")));
-void CAN_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void LIN_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void I2C_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void CPU_CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART3_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void SPI_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+/* Exceptions */
+void NMI_Handler            (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler            (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler        (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
 
 
 /*----------------------------------------------------------------------------
   Exception / Interrupt Vector table
  *----------------------------------------------------------------------------*/
-const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = {
-  /* Cortex-M0+ Exceptions Handler */
-  (pFunc)((uint32_t)&__StackTop),           /*      Initial Stack Pointer     */
-  Reset_Handler,                            /*      Reset Handler             */
-  NMI_Handler,                              /*      NMI Handler               */
-  HardFault_Handler,                        /*      Hard Fault Handler        */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  SVC_Handler,                              /*      SVCall Handler            */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  PendSV_Handler,                           /*      PendSV Handler            */
-  SysTick_Handler,                          /*      SysTick Handler           */
-
-  /* External interrupts */
-  WDT_IRQHandler,                           /*  0:  Watchdog Timer            */
-  RTC_IRQHandler,                           /*  1:  Real Time Clock           */
-  TIM0_IRQHandler,                          /*  2:  Timer0 / Timer1           */
-  TIM2_IRQHandler,                          /*  3:  Timer2 / Timer3           */
-  MCIA_IRQHandler,                          /*  4:  MCIa                      */
-  MCIB_IRQHandler,                          /*  5:  MCIb                      */
-  UART0_IRQHandler,                         /*  6:  UART0 - DUT FPGA          */
-  UART1_IRQHandler,                         /*  7:  UART1 - DUT FPGA          */
-  UART2_IRQHandler,                         /*  8:  UART2 - DUT FPGA          */
-  UART4_IRQHandler,                         /*  9:  UART4 - not connected     */
-  AACI_IRQHandler,                          /* 10: AACI / AC97                */
-  CLCD_IRQHandler,                          /* 11: CLCD Combined Interrupt    */
-  ENET_IRQHandler,                          /* 12: Ethernet                   */
-  USBDC_IRQHandler,                         /* 13: USB Device                 */
-  USBHC_IRQHandler,                         /* 14: USB Host Controller        */
-  CHLCD_IRQHandler,                         /* 15: Character LCD              */
-  FLEXRAY_IRQHandler,                       /* 16: Flexray                    */
-  CAN_IRQHandler,                           /* 17: CAN                        */
-  LIN_IRQHandler,                           /* 18: LIN                        */
-  I2C_IRQHandler,                           /* 19: I2C ADC/DAC                */
-  0,                                        /* 20: Reserved                   */
-  0,                                        /* 21: Reserved                   */
-  0,                                        /* 22: Reserved                   */
-  0,                                        /* 23: Reserved                   */
-  0,                                        /* 24: Reserved                   */
-  0,                                        /* 25: Reserved                   */
-  0,                                        /* 26: Reserved                   */
-  0,                                        /* 27: Reserved                   */
-  CPU_CLCD_IRQHandler,                      /* 28: Reserved - CPU FPGA CLCD   */
-  0,                                        /* 29: Reserved - CPU FPGA        */
-  UART3_IRQHandler,                         /* 30: UART3    - CPU FPGA        */
-  SPI_IRQHandler                            /* 31: SPI Touchscreen - CPU FPGA */
+extern const pFunc __Vectors[ 48];
+       const pFunc __Vectors[ 48] __attribute__ ((section(".vectors"))) = {
+  (pFunc)(&__StackTop),                     /*     Initial Stack Pointer */
+  Reset_Handler,                            /*     Reset Handler */
+  NMI_Handler,                              /* -14 NMI Handler */
+  HardFault_Handler,                        /* -13 Hard Fault Handler */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  SVC_Handler,                              /*  -5 SVCall Handler */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  PendSV_Handler,                           /*  -2 PendSV Handler */
+  SysTick_Handler,                          /*  -1 SysTick Handler */
+
+  /* Interrupts */
+  Interrupt0_Handler,                       /*   0 Interrupt 0 */
+  Interrupt1_Handler,                       /*   1 Interrupt 1 */
+  Interrupt2_Handler,                       /*   2 Interrupt 2 */
+  Interrupt3_Handler,                       /*   3 Interrupt 3 */
+  Interrupt4_Handler,                       /*   4 Interrupt 4 */
+  Interrupt5_Handler,                       /*   5 Interrupt 5 */
+  Interrupt6_Handler,                       /*   6 Interrupt 6 */
+  Interrupt7_Handler,                       /*   7 Interrupt 7 */
+  Interrupt8_Handler,                       /*   8 Interrupt 8 */
+  Interrupt9_Handler                        /*   9 Interrupt 9 */
+                                            /* Interrupts 10 .. 31 are left out */
 };
 
 
@@ -184,41 +149,42 @@ void Reset_Handler(void) {
   uint32_t *pSrc, *pDest;
   uint32_t *pTable __attribute__((unused));
 
-/*  Firstly it copies data from read only memory to RAM. There are two schemes
- *  to copy. One can copy more than one sections. Another can only copy
- *  one section.  The former scheme needs more instructions and read-only
- *  data to implement than the latter.
- *  Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.  */
+/* Firstly it copies data from read only memory to RAM.
+ * There are two schemes to copy. One can copy more than one sections.
+ * Another can copy only one section. The former scheme needs more
+ * instructions and read-only data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.
+ */
 
 #ifdef __STARTUP_COPY_MULTIPLE
-/*  Multiple sections scheme.
+/* Multiple sections scheme.
  *
- *  Between symbol address __copy_table_start__ and __copy_table_end__,
- *  there are array of triplets, each of which specify:
- *    offset 0: LMA of start of a section to copy from
- *    offset 4: VMA of start of a section to copy to
- *    offset 8: size of the section to copy. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ *   offset 0: LMA of start of a section to copy from
+ *   offset 4: VMA of start of a section to copy to
+ *   offset 8: size of the section to copy. Must be multiply of 4
  *
- *  All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
  */
   pTable = &__copy_table_start__;
 
   for (; pTable < &__copy_table_end__; pTable = pTable + 3) {
-		pSrc  = (uint32_t*)*(pTable + 0);
-		pDest = (uint32_t*)*(pTable + 1);
-		for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
+    pSrc  = (uint32_t*)*(pTable + 0);
+    pDest = (uint32_t*)*(pTable + 1);
+    for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
       *pDest++ = *pSrc++;
-		}
-	}
+    }
+  }
 #else
-/*  Single section scheme.
+/* Single section scheme.
  *
- *  The ranges of copy from/to are specified by following symbols
- *    __etext: LMA of start of the section to copy from. Usually end of text
- *    __data_start__: VMA of start of the section to copy to
- *    __data_end__: VMA of end of the section to copy to
+ * The ranges of copy from/to are specified by following symbols
+ *   __etext: LMA of start of the section to copy from. Usually end of text
+ *   __data_start__: VMA of start of the section to copy to
+ *   __data_end__: VMA of end of the section to copy to
  *
- *  All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
  */
   pSrc  = &__etext;
   pDest = &__data_start__;
@@ -228,40 +194,40 @@ void Reset_Handler(void) {
   }
 #endif /*__STARTUP_COPY_MULTIPLE */
 
-/*  This part of work usually is done in C library startup code. Otherwise,
- *  define this macro to enable it in this startup.
+/* This part of work usually is done in C library startup code.
+ * Otherwise, define this macro to enable it in this startup.
  *
- *  There are two schemes too. One can clear multiple BSS sections. Another
- *  can only clear one section. The former is more size expensive than the
- *  latter.
+ * There are two schemes too.
+ * One can clear multiple BSS sections. Another can only clear one section.
+ * The former is more size expensive than the latter.
  *
- *  Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- *  Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
  */
 #ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/*  Multiple sections scheme.
+/* Multiple sections scheme.
  *
- *  Between symbol address __copy_table_start__ and __copy_table_end__,
- *  there are array of tuples specifying:
- *    offset 0: Start of a BSS section
- *    offset 4: Size of this BSS section. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ *   offset 0: Start of a BSS section
+ *   offset 4: Size of this BSS section. Must be multiply of 4
  */
   pTable = &__zero_table_start__;
 
   for (; pTable < &__zero_table_end__; pTable = pTable + 2) {
-		pDest = (uint32_t*)*(pTable + 0);
-		for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
+    pDest = (uint32_t*)*(pTable + 0);
+    for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
       *pDest++ = 0;
-		}
-	}
+    }
+  }
 #elif defined (__STARTUP_CLEAR_BSS)
-/*  Single BSS section scheme.
+/* Single BSS section scheme.
  *
- *  The BSS section is specified by following symbols
- *    __bss_start__: start of the BSS section.
- *    __bss_end__: end of the BSS section.
+ * The BSS section is specified by following symbols
+ *   __bss_start__: start of the BSS section.
+ *   __bss_end__: end of the BSS section.
  *
- *  Both addresses must be aligned to 4 bytes boundary.
+ * Both addresses must be aligned to 4 bytes boundary.
  */
   pDest = &__bss_start__;
 
@@ -270,15 +236,8 @@ void Reset_Handler(void) {
   }
 #endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
 
-#ifndef __NO_SYSTEM_INIT
-	SystemInit();
-#endif
-
-#ifndef __START
-#define __START _start
-#endif
-	__START();
-
+  SystemInit();                             /* CMSIS System Initialization */
+  _start();                                 /* Enter PreeMain (C library entry point) */
 }
 
 
@@ -287,5 +246,5 @@ void Reset_Handler(void) {
  *----------------------------------------------------------------------------*/
 void Default_Handler(void) {
 
-	while(1);
+  while(1);
 }

CMSIS/CoreValidation/Tests/Cortex-M0plus/GCC/RTE/Device/ARMCM0P_MPU/system_ARMCM0plus.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
  * @file     system_ARMCM0plus.c
  * @brief    CMSIS Device System Source File for
- *           ARMCM0plus Device Series
- * @version  V5.00
- * @date     07. September 2016
+ *           ARMCM0plus Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -28,9 +28,9 @@
 /*----------------------------------------------------------------------------
   Define clocks
  *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+#define  XTAL            (50000000UL)     /* Oscillator frequency */
 
-#define  SYSTEM_CLOCK    (5U * XTAL)
+#define  SYSTEM_CLOCK    (XTAL / 2U)
 
 
 /*----------------------------------------------------------------------------
@@ -43,7 +43,7 @@
 /*----------------------------------------------------------------------------
   System Core Clock Variable
  *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */
 
 
 /*----------------------------------------------------------------------------

CMSIS/CoreValidation/Tests/Cortex-M0plus/IAR/RTE/Device/ARMCM0P_MPU/startup_ARMCM0plus.s

@@ -1,12 +1,12 @@
 ;/**************************************************************************//**
 ; * @file     startup_ARMCM0plus.s
 ; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM0plus Device Series
-; * @version  V5.00
-; * @date     08. March 2016
+; *           ARMCM0plus Device
+; * @version  V5.3.1
+; * @date     09. July 2018
 ; ******************************************************************************/
 ;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
 ; *
 ; * SPDX-License-Identifier: Apache-2.0
 ; *
@@ -39,232 +39,109 @@
 ; Cortex-M version
 ;
 
-        MODULE  ?cstartup
+                MODULE   ?cstartup
 
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
+                ;; Forward declaration of sections.
+                SECTION  CSTACK:DATA:NOROOT(3)
 
-        SECTION .intvec:CODE:NOROOT(2)
+                SECTION  .intvec:CODE:NOROOT(2)
 
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit
-        PUBLIC  __vector_table
-        PUBLIC  __vector_table_0x1c
-        PUBLIC  __Vectors
-        PUBLIC  __Vectors_End
-        PUBLIC  __Vectors_Size
+                EXTERN   __iar_program_start
+                EXTERN   SystemInit
+                PUBLIC   __vector_table
+                PUBLIC   __vector_table_0x1c
+                PUBLIC   __Vectors
+                PUBLIC   __Vectors_End
+                PUBLIC   __Vectors_Size
 
-        DATA
+                DATA
 
 __vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler
-
-        DCD     NMI_Handler
-        DCD     HardFault_Handler
-        DCD     0
-        DCD     0
-        DCD     0
+                DCD      sfe(CSTACK)                         ;     Top of Stack
+                DCD      Reset_Handler                       ;     Reset Handler
+                DCD      NMI_Handler                         ; -14 NMI Handler
+                DCD      HardFault_Handler                   ; -13 Hard Fault Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
 __vector_table_0x1c
-        DCD     0
-        DCD     0
-        DCD     0
-        DCD     0
-        DCD     SVC_Handler
-        DCD     0
-        DCD     0
-        DCD     PendSV_Handler
-        DCD     SysTick_Handler
-
-        ; External Interrupts
-        DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
-        DCD     RTC_IRQHandler            ;  1:  Real Time Clock
-        DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
-        DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
-        DCD     MCIA_IRQHandler           ;  4:  MCIa
-        DCD     MCIB_IRQHandler           ;  5:  MCIb
-        DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
-        DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
-        DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
-        DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
-        DCD     AACI_IRQHandler           ; 10: AACI / AC97
-        DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
-        DCD     ENET_IRQHandler           ; 12: Ethernet
-        DCD     USBDC_IRQHandler          ; 13: USB Device
-        DCD     USBHC_IRQHandler          ; 14: USB Host Controller
-        DCD     CHLCD_IRQHandler          ; 15: Character LCD
-        DCD     FLEXRAY_IRQHandler        ; 16: Flexray
-        DCD     CAN_IRQHandler            ; 17: CAN
-        DCD     LIN_IRQHandler            ; 18: LIN
-        DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
-        DCD     0                         ; 20: Reserved
-        DCD     0                         ; 21: Reserved
-        DCD     0                         ; 22: Reserved
-        DCD     0                         ; 23: Reserved
-        DCD     0                         ; 24: Reserved
-        DCD     0                         ; 25: Reserved
-        DCD     0                         ; 26: Reserved
-        DCD     0                         ; 27: Reserved
-        DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
-        DCD     0                         ; 29: Reserved - CPU FPGA
-        DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
-        DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      SVC_Handler                         ;  -5 SVCall Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      PendSV_Handler                      ;  -2 PendSV Handler
+                DCD      SysTick_Handler                     ;  -1 SysTick Handler
+
+                ; Interrupts
+                DCD      Interrupt0_Handler                  ;   0 Interrupt 0
+                DCD      Interrupt1_Handler                  ;   1 Interrupt 1
+                DCD      Interrupt2_Handler                  ;   2 Interrupt 2
+                DCD      Interrupt3_Handler                  ;   3 Interrupt 3
+                DCD      Interrupt4_Handler                  ;   4 Interrupt 4
+                DCD      Interrupt5_Handler                  ;   5 Interrupt 5
+                DCD      Interrupt6_Handler                  ;   6 Interrupt 6
+                DCD      Interrupt7_Handler                  ;   7 Interrupt 7
+                DCD      Interrupt8_Handler                  ;   8 Interrupt 8
+                DCD      Interrupt9_Handler                  ;   9 Interrupt 9
+
+                DS32    ( 22)                                ; Interrupts 10 .. 31 are left out
 __Vectors_End
 
-__Vectors       EQU   __vector_table
-__Vectors_Size  EQU   __Vectors_End - __Vectors
+__Vectors       EQU      __vector_table
+__Vectors_Size  EQU      __Vectors_End - __Vectors
 
 
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
+                THUMB
 
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
+; Reset Handler
 
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
+                PUBWEAK  Reset_Handler
+                SECTION  .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+                LDR      R0, =SystemInit
+                BLX      R0
+                LDR      R0, =__iar_program_start
+                BX       R0
+
+
+                PUBWEAK NMI_Handler
+                PUBWEAK HardFault_Handler
+                PUBWEAK SVC_Handler
+                PUBWEAK PendSV_Handler
+                PUBWEAK SysTick_Handler
+
+                PUBWEAK Interrupt0_Handler
+                PUBWEAK Interrupt1_Handler
+                PUBWEAK Interrupt2_Handler
+                PUBWEAK Interrupt3_Handler
+                PUBWEAK Interrupt4_Handler
+                PUBWEAK Interrupt5_Handler
+                PUBWEAK Interrupt6_Handler
+                PUBWEAK Interrupt7_Handler
+                PUBWEAK Interrupt8_Handler
+                PUBWEAK Interrupt9_Handler
+                SECTION .text:CODE:REORDER:NOROOT(1)
 NMI_Handler
-        B NMI_Handler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 HardFault_Handler
-        B HardFault_Handler
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 SVC_Handler
-        B SVC_Handler
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 SysTick_Handler
-        B SysTick_Handler
-
-        PUBWEAK WDT_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WDT_IRQHandler
-        B WDT_IRQHandler
-
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-
-        PUBWEAK TIM0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM0_IRQHandler
-        B TIM0_IRQHandler
-
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-
-        PUBWEAK MCIA_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MCIA_IRQHandler
-        B MCIA_IRQHandler
-
-        PUBWEAK MCIB_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MCIB_IRQHandler
-        B MCIB_IRQHandler
-
-        PUBWEAK UART0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART0_IRQHandler
-        B UART0_IRQHandler
-
-        PUBWEAK UART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART1_IRQHandler
-        B UART1_IRQHandler
-
-        PUBWEAK UART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART2_IRQHandler
-        B UART2_IRQHandler
-
-        PUBWEAK UART4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
-        B UART4_IRQHandler
-
-        PUBWEAK AACI_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-AACI_IRQHandler
-        B AACI_IRQHandler
-
-        PUBWEAK CLCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CLCD_IRQHandler
-        B CLCD_IRQHandler
-
-        PUBWEAK ENET_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ENET_IRQHandler
-        B ENET_IRQHandler
-
-        PUBWEAK USBDC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USBDC_IRQHandler
-        B USBDC_IRQHandler
-
-        PUBWEAK USBHC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USBHC_IRQHandler
-        B USBHC_IRQHandler
-
-        PUBWEAK CHLCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CHLCD_IRQHandler
-        B CHLCD_IRQHandler
-
-        PUBWEAK FLEXRAY_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLEXRAY_IRQHandler
-        B FLEXRAY_IRQHandler
-
-        PUBWEAK CAN_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN_IRQHandler
-        B CAN_IRQHandler
-
-        PUBWEAK LIN_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-LIN_IRQHandler
-        B LIN_IRQHandler
-
-        PUBWEAK I2C_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C_IRQHandler
-        B I2C_IRQHandler
-
-        PUBWEAK CPU_CLCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CPU_CLCD_IRQHandler
-        B CPU_CLCD_IRQHandler
-
-        PUBWEAK UART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART3_IRQHandler
-        B UART3_IRQHandler
-
-        PUBWEAK SPI_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI_IRQHandler
-        B SPI_IRQHandler
 
-        END
+Interrupt0_Handler
+Interrupt1_Handler
+Interrupt2_Handler
+Interrupt3_Handler
+Interrupt4_Handler
+Interrupt5_Handler
+Interrupt6_Handler
+Interrupt7_Handler
+Interrupt8_Handler
+Interrupt9_Handler
+Default_Handler
+                B        .
+
+
+                END

CMSIS/CoreValidation/Tests/Cortex-M0plus/IAR/RTE/Device/ARMCM0P_MPU/system_ARMCM0plus.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
  * @file     system_ARMCM0plus.c
  * @brief    CMSIS Device System Source File for
- *           ARMCM0plus Device Series
- * @version  V5.00
- * @date     07. September 2016
+ *           ARMCM0plus Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -28,9 +28,9 @@
 /*----------------------------------------------------------------------------
   Define clocks
  *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+#define  XTAL            (50000000UL)     /* Oscillator frequency */
 
-#define  SYSTEM_CLOCK    (5U * XTAL)
+#define  SYSTEM_CLOCK    (XTAL / 2U)
 
 
 /*----------------------------------------------------------------------------
@@ -43,7 +43,7 @@
 /*----------------------------------------------------------------------------
   System Core Clock Variable
  *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */
 
 
 /*----------------------------------------------------------------------------

CMSIS/CoreValidation/Tests/Cortex-M23/AC6/RTE/Device/ARMCM23/startup_ARMCM23.s

@@ -1,12 +1,12 @@
 ;/**************************************************************************//**
 ; * @file     startup_ARMCM23.s
 ; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM23 Device Series
-; * @version  V5.00
-; * @date     21. October 2016
+; *           ARMCM23 Device
+; * @version  V5.3.1
+; * @date     09. July 2018
 ; ******************************************************************************/
 ;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
 ; *
 ; * SPDX-License-Identifier: Apache-2.0
 ; *
@@ -23,32 +23,33 @@
 ; * limitations under the License.
 ; */
 
-;/*
 ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
 
 
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Stack Configuration
+;  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
 
-Stack_Size      EQU     0x00000400
+Stack_Size      EQU      0x00000400
 
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
+                AREA     STACK, NOINIT, READWRITE, ALIGN=3
+__stack_limit
+Stack_Mem       SPACE    Stack_Size
 __initial_sp
 
 
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Heap Configuration
+;  <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
 
-Heap_Size       EQU     0x00000C00
+Heap_Size       EQU      0x00000C00
 
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+                IF       Heap_Size != 0                      ; Heap is provided
+                AREA     HEAP, NOINIT, READWRITE, ALIGN=3
 __heap_base
-Heap_Mem        SPACE   Heap_Size
+Heap_Mem        SPACE    Heap_Size
 __heap_limit
+                ENDIF
 
 
                 PRESERVE8
@@ -57,186 +58,105 @@ __heap_limit
 
 ; Vector Table Mapped to Address 0 at Reset
 
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
-                DCD     RTC_IRQHandler            ;  1:  Real Time Clock
-                DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
-                DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
-                DCD     MCIA_IRQHandler           ;  4:  MCIa
-                DCD     MCIB_IRQHandler           ;  5:  MCIb
-                DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
-                DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
-                DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
-                DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
-                DCD     AACI_IRQHandler           ; 10: AACI / AC97
-                DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
-                DCD     ENET_IRQHandler           ; 12: Ethernet
-                DCD     USBDC_IRQHandler          ; 13: USB Device
-                DCD     USBHC_IRQHandler          ; 14: USB Host Controller
-                DCD     CHLCD_IRQHandler          ; 15: Character LCD
-                DCD     FLEXRAY_IRQHandler        ; 16: Flexray
-                DCD     CAN_IRQHandler            ; 17: CAN
-                DCD     LIN_IRQHandler            ; 18: LIN
-                DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
-                DCD     0                         ; 20: Reserved
-                DCD     0                         ; 21: Reserved
-                DCD     0                         ; 22: Reserved
-                DCD     0                         ; 23: Reserved
-                DCD     0                         ; 24: Reserved
-                DCD     0                         ; 25: Reserved
-                DCD     0                         ; 26: Reserved
-                DCD     0                         ; 27: Reserved
-                DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
-                DCD     0                         ; 29: Reserved - CPU FPGA
-                DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
-                DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
+                AREA     RESET, DATA, READONLY
+                EXPORT   __Vectors
+                EXPORT   __Vectors_End
+                EXPORT   __Vectors_Size
+
+__Vectors       DCD      __initial_sp                        ;     Top of Stack
+                DCD      Reset_Handler                       ;     Reset Handler
+                DCD      NMI_Handler                         ; -14 NMI Handler
+                DCD      HardFault_Handler                   ; -13 Hard Fault Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      SVC_Handler                         ;  -5 SVCall Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      PendSV_Handler                      ;  -2 PendSV Handler
+                DCD      SysTick_Handler                     ;  -1 SysTick Handler
+
+                ; Interrupts
+                DCD      Interrupt0_Handler                  ;   0 Interrupt 0
+                DCD      Interrupt1_Handler                  ;   1 Interrupt 1
+                DCD      Interrupt2_Handler                  ;   2 Interrupt 2
+                DCD      Interrupt3_Handler                  ;   3 Interrupt 3
+                DCD      Interrupt4_Handler                  ;   4 Interrupt 4
+                DCD      Interrupt5_Handler                  ;   5 Interrupt 5
+                DCD      Interrupt6_Handler                  ;   6 Interrupt 6
+                DCD      Interrupt7_Handler                  ;   7 Interrupt 7
+                DCD      Interrupt8_Handler                  ;   8 Interrupt 8
+                DCD      Interrupt9_Handler                  ;   9 Interrupt 9
+
+                SPACE    (214 * 4)                           ; Interrupts 10 .. 224 are left out
 __Vectors_End
+__Vectors_Size  EQU      __Vectors_End - __Vectors
 
-__Vectors_Size  EQU     __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
 
+                AREA     |.text|, CODE, READONLY
 
 ; Reset Handler
 
 Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  SystemInit
-                IMPORT  __main
-                LDR     R0, =SystemInit
-                BLX     R0
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-
+                EXPORT   Reset_Handler             [WEAK]
+                IMPORT   SystemInit
+                IMPORT   __main
 
-; Dummy Exception Handlers (infinite loops which can be modified)
+                LDR      R0, =__stack_limit
+                MSR      MSPLIM, R0                          ; Non-secure version of MSPLIM is RAZ/WI
 
-NMI_Handler     PROC
-                EXPORT  NMI_Handler               [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
+                LDR      R0, =SystemInit
+                BLX      R0
+                LDR      R0, =__main
+                BX       R0
                 ENDP
 
-Default_Handler PROC
-
-                EXPORT  WDT_IRQHandler            [WEAK]
-                EXPORT  RTC_IRQHandler            [WEAK]
-                EXPORT  TIM0_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler           [WEAK]
-                EXPORT  MCIA_IRQHandler           [WEAK]
-                EXPORT  MCIB_IRQHandler           [WEAK]
-                EXPORT  UART0_IRQHandler          [WEAK]
-                EXPORT  UART1_IRQHandler          [WEAK]
-                EXPORT  UART2_IRQHandler          [WEAK]
-                EXPORT  UART3_IRQHandler          [WEAK]
-                EXPORT  UART4_IRQHandler          [WEAK]
-                EXPORT  AACI_IRQHandler           [WEAK]
-                EXPORT  CLCD_IRQHandler           [WEAK]
-                EXPORT  ENET_IRQHandler           [WEAK]
-                EXPORT  USBDC_IRQHandler          [WEAK]
-                EXPORT  USBHC_IRQHandler          [WEAK]
-                EXPORT  CHLCD_IRQHandler          [WEAK]
-                EXPORT  FLEXRAY_IRQHandler        [WEAK]
-                EXPORT  CAN_IRQHandler            [WEAK]
-                EXPORT  LIN_IRQHandler            [WEAK]
-                EXPORT  I2C_IRQHandler            [WEAK]
-                EXPORT  CPU_CLCD_IRQHandler       [WEAK]
-                EXPORT  SPI_IRQHandler            [WEAK]
-
-WDT_IRQHandler
-RTC_IRQHandler
-TIM0_IRQHandler
-TIM2_IRQHandler
-MCIA_IRQHandler
-MCIB_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-UART3_IRQHandler
-UART4_IRQHandler
-AACI_IRQHandler
-CLCD_IRQHandler
-ENET_IRQHandler
-USBDC_IRQHandler
-USBHC_IRQHandler
-CHLCD_IRQHandler
-FLEXRAY_IRQHandler
-CAN_IRQHandler
-LIN_IRQHandler
-I2C_IRQHandler
-CPU_CLCD_IRQHandler
-SPI_IRQHandler
-                B       .
 
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+                MACRO
+                Set_Default_Handler  $Handler_Name
+$Handler_Name   PROC
+                EXPORT   $Handler_Name             [WEAK]
+                B        .
                 ENDP
+                MEND
 
 
-                ALIGN
-
-
-; User Initial Stack & Heap
-
-                IF      :DEF:__MICROLIB
+; Default exception/interrupt handler
 
-                EXPORT  __initial_sp
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
+                Set_Default_Handler  NMI_Handler
+                Set_Default_Handler  HardFault_Handler
+                Set_Default_Handler  SVC_Handler
+                Set_Default_Handler  PendSV_Handler
+                Set_Default_Handler  SysTick_Handler
 
-                ELSE
+                Set_Default_Handler  Interrupt0_Handler
+                Set_Default_Handler  Interrupt1_Handler
+                Set_Default_Handler  Interrupt2_Handler
+                Set_Default_Handler  Interrupt3_Handler
+                Set_Default_Handler  Interrupt4_Handler
+                Set_Default_Handler  Interrupt5_Handler
+                Set_Default_Handler  Interrupt6_Handler
+                Set_Default_Handler  Interrupt7_Handler
+                Set_Default_Handler  Interrupt8_Handler
+                Set_Default_Handler  Interrupt9_Handler
 
-                IMPORT  __use_two_region_memory
-                EXPORT  __user_initial_stackheap
+                ALIGN
 
-__user_initial_stackheap PROC
-                LDR     R0, =  Heap_Mem
-                LDR     R1, =(Stack_Mem + Stack_Size)
-                LDR     R2, = (Heap_Mem +  Heap_Size)
-                LDR     R3, = Stack_Mem
-                BX      LR
-                ENDP
 
-                ALIGN
+; User setup Stack & Heap
 
+                EXPORT   __stack_limit
+                EXPORT   __initial_sp
+                IF       Heap_Size != 0                      ; Heap is provided
+                EXPORT   __heap_base
+                EXPORT   __heap_limit
                 ENDIF
 
-
                 END

CMSIS/CoreValidation/Tests/Cortex-M23/AC6/RTE/Device/ARMCM23/system_ARMCM23.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
  * @file     system_ARMCM23.c
  * @brief    CMSIS Device System Source File for
- *           ARMCM23 Device Series
- * @version  V5.00
- * @date     21. October 2016
+ *           ARMCM23 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -38,9 +38,9 @@
 /*----------------------------------------------------------------------------
   Define clocks
  *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+#define  XTAL            (50000000UL)     /* Oscillator frequency */
 
-#define  SYSTEM_CLOCK    (5U * XTAL)
+#define  SYSTEM_CLOCK    (XTAL / 2U)
 
 
 /*----------------------------------------------------------------------------
@@ -53,7 +53,7 @@
 /*----------------------------------------------------------------------------
   System Core Clock Variable
  *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */
 
 
 /*----------------------------------------------------------------------------

CMSIS/CoreValidation/Tests/Cortex-M23/GCC/RTE/Device/ARMCM23/startup_ARMCM23.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
- * @file     startup_ARMCM23.s
+ * @file     startup_ARMCM23.c
  * @brief    CMSIS Core Device Startup File for
- *           ARMCM23 Device Series
- * @version  V5.00
- * @date     21. October 2016
+ *           ARMCM23 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -23,6 +23,10 @@
  * limitations under the License.
  */
 
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
 #include <stdint.h>
 
 
@@ -39,6 +43,7 @@ extern uint32_t __zero_table_end__;
 extern uint32_t __bss_start__;
 extern uint32_t __bss_end__;
 extern uint32_t __StackTop;
+extern uint32_t __StackLimit;
 
 /*----------------------------------------------------------------------------
   Exception / Interrupt Handler Function Prototype
@@ -49,35 +54,30 @@ typedef void( *pFunc )( void );
 /*----------------------------------------------------------------------------
   External References
  *----------------------------------------------------------------------------*/
-#ifndef __START
-extern void  _start(void) __attribute__((noreturn));    /* PreeMain (C library entry point) */
-#else
-extern int  __START(void) __attribute__((noreturn));    /* main entry point */
-#endif
-
-#ifndef __NO_SYSTEM_INIT
-extern void SystemInit (void);            /* CMSIS System Initialization      */
-#endif
+extern void _start     (void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
+extern void SystemInit (void);                           /* CMSIS System Initialization */
 
 
 /*----------------------------------------------------------------------------
   Internal References
  *----------------------------------------------------------------------------*/
-void Default_Handler(void);                          /* Default empty handler */
-void Reset_Handler(void);                            /* Reset Handler */
+void Default_Handler(void) __attribute__ ((noreturn));
+void Reset_Handler  (void) __attribute__ ((noreturn));
 
 
 /*----------------------------------------------------------------------------
   User Initial Stack & Heap
  *----------------------------------------------------------------------------*/
-#ifndef __STACK_SIZE
-  #define	__STACK_SIZE  0x00000400
-#endif
+//<h> Stack Configuration
+//  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//</h>
+#define  __STACK_SIZE  0x00000400
 static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack")));
 
-#ifndef __HEAP_SIZE
-  #define	__HEAP_SIZE   0x00000C00
-#endif
+//<h> Heap Configuration
+//  <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//</h>
+#define  __HEAP_SIZE   0x00000C00
 #if __HEAP_SIZE > 0
 static uint8_t heap[__HEAP_SIZE]   __attribute__ ((aligned(8), used, section(".heap")));
 #endif
@@ -86,94 +86,59 @@ static uint8_t heap[__HEAP_SIZE]   __attribute__ ((aligned(8), used, section(".h
 /*----------------------------------------------------------------------------
   Exception / Interrupt Handler
  *----------------------------------------------------------------------------*/
-/* ARMCM23 Processor Exceptions */
-void NMI_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
-void HardFault_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
-void SVC_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
-void PendSV_Handler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void SysTick_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
-
-/* ARMCM23 Specific Interrupts */
-void WDT_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void RTC_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM0_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM2_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIA_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIB_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART0_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART1_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART2_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART4_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void AACI_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void CLCD_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void ENET_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBDC_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBHC_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void CHLCD_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void FLEXRAY_IRQHandler  (void) __attribute__ ((weak, alias("Default_Handler")));
-void CAN_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void LIN_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void I2C_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void CPU_CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART3_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void SPI_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+/* Exceptions */
+void NMI_Handler            (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler            (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler        (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
 
 
 /*----------------------------------------------------------------------------
   Exception / Interrupt Vector table
  *----------------------------------------------------------------------------*/
-const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = {
-  /* ARMCM23 Exceptions Handler */
-  (pFunc)((uint32_t)&__StackTop),           /*      Initial Stack Pointer     */
-  Reset_Handler,                            /*      Reset Handler             */
-  NMI_Handler,                              /*      NMI Handler               */
-  HardFault_Handler,                        /*      Hard Fault Handler        */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  SVC_Handler,                              /*      SVCall Handler            */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  PendSV_Handler,                           /*      PendSV Handler            */
-  SysTick_Handler,                          /*      SysTick Handler           */
-
-  /* External interrupts */
-  WDT_IRQHandler,                           /*  0:  Watchdog Timer            */
-  RTC_IRQHandler,                           /*  1:  Real Time Clock           */
-  TIM0_IRQHandler,                          /*  2:  Timer0 / Timer1           */
-  TIM2_IRQHandler,                          /*  3:  Timer2 / Timer3           */
-  MCIA_IRQHandler,                          /*  4:  MCIa                      */
-  MCIB_IRQHandler,                          /*  5:  MCIb                      */
-  UART0_IRQHandler,                         /*  6:  UART0 - DUT FPGA          */
-  UART1_IRQHandler,                         /*  7:  UART1 - DUT FPGA          */
-  UART2_IRQHandler,                         /*  8:  UART2 - DUT FPGA          */
-  UART4_IRQHandler,                         /*  9:  UART4 - not connected     */
-  AACI_IRQHandler,                          /* 10: AACI / AC97                */
-  CLCD_IRQHandler,                          /* 11: CLCD Combined Interrupt    */
-  ENET_IRQHandler,                          /* 12: Ethernet                   */
-  USBDC_IRQHandler,                         /* 13: USB Device                 */
-  USBHC_IRQHandler,                         /* 14: USB Host Controller        */
-  CHLCD_IRQHandler,                         /* 15: Character LCD              */
-  FLEXRAY_IRQHandler,                       /* 16: Flexray                    */
-  CAN_IRQHandler,                           /* 17: CAN                        */
-  LIN_IRQHandler,                           /* 18: LIN                        */
-  I2C_IRQHandler,                           /* 19: I2C ADC/DAC                */
-  0,                                        /* 20: Reserved                   */
-  0,                                        /* 21: Reserved                   */
-  0,                                        /* 22: Reserved                   */
-  0,                                        /* 23: Reserved                   */
-  0,                                        /* 24: Reserved                   */
-  0,                                        /* 25: Reserved                   */
-  0,                                        /* 26: Reserved                   */
-  0,                                        /* 27: Reserved                   */
-  CPU_CLCD_IRQHandler,                      /* 28: Reserved - CPU FPGA CLCD   */
-  0,                                        /* 29: Reserved - CPU FPGA        */
-  UART3_IRQHandler,                         /* 30: UART3    - CPU FPGA        */
-  SPI_IRQHandler                            /* 31: SPI Touchscreen - CPU FPGA */
+extern const pFunc __Vectors[240];
+       const pFunc __Vectors[240] __attribute__ ((section(".vectors"))) = {
+  (pFunc)(&__StackTop),                     /*     Initial Stack Pointer */
+  Reset_Handler,                            /*     Reset Handler */
+  NMI_Handler,                              /* -14 NMI Handler */
+  HardFault_Handler,                        /* -13 Hard Fault Handler */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  SVC_Handler,                              /*  -5 SVCall Handler */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  PendSV_Handler,                           /*  -2 PendSV Handler */
+  SysTick_Handler,                          /*  -1 SysTick Handler */
+
+  /* Interrupts */
+  Interrupt0_Handler,                       /*   0 Interrupt 0 */
+  Interrupt1_Handler,                       /*   1 Interrupt 1 */
+  Interrupt2_Handler,                       /*   2 Interrupt 2 */
+  Interrupt3_Handler,                       /*   3 Interrupt 3 */
+  Interrupt4_Handler,                       /*   4 Interrupt 4 */
+  Interrupt5_Handler,                       /*   5 Interrupt 5 */
+  Interrupt6_Handler,                       /*   6 Interrupt 6 */
+  Interrupt7_Handler,                       /*   7 Interrupt 7 */
+  Interrupt8_Handler,                       /*   8 Interrupt 8 */
+  Interrupt9_Handler                        /*   9 Interrupt 9 */
+                                            /* Interrupts 10 .. 224 are left out */
 };
 
 
@@ -184,41 +149,42 @@ void Reset_Handler(void) {
   uint32_t *pSrc, *pDest;
   uint32_t *pTable __attribute__((unused));
 
-/*  Firstly it copies data from read only memory to RAM. There are two schemes
- *  to copy. One can copy more than one sections. Another can only copy
- *  one section.  The former scheme needs more instructions and read-only
- *  data to implement than the latter.
- *  Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.  */
+/* Firstly it copies data from read only memory to RAM.
+ * There are two schemes to copy. One can copy more than one sections.
+ * Another can copy only one section. The former scheme needs more
+ * instructions and read-only data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.
+ */
 
 #ifdef __STARTUP_COPY_MULTIPLE
-/*  Multiple sections scheme.
+/* Multiple sections scheme.
  *
- *  Between symbol address __copy_table_start__ and __copy_table_end__,
- *  there are array of triplets, each of which specify:
- *    offset 0: LMA of start of a section to copy from
- *    offset 4: VMA of start of a section to copy to
- *    offset 8: size of the section to copy. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ *   offset 0: LMA of start of a section to copy from
+ *   offset 4: VMA of start of a section to copy to
+ *   offset 8: size of the section to copy. Must be multiply of 4
  *
- *  All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
  */
   pTable = &__copy_table_start__;
 
   for (; pTable < &__copy_table_end__; pTable = pTable + 3) {
-		pSrc  = (uint32_t*)*(pTable + 0);
-		pDest = (uint32_t*)*(pTable + 1);
-		for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
+    pSrc  = (uint32_t*)*(pTable + 0);
+    pDest = (uint32_t*)*(pTable + 1);
+    for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
       *pDest++ = *pSrc++;
-		}
-	}
+    }
+  }
 #else
-/*  Single section scheme.
+/* Single section scheme.
  *
- *  The ranges of copy from/to are specified by following symbols
- *    __etext: LMA of start of the section to copy from. Usually end of text
- *    __data_start__: VMA of start of the section to copy to
- *    __data_end__: VMA of end of the section to copy to
+ * The ranges of copy from/to are specified by following symbols
+ *   __etext: LMA of start of the section to copy from. Usually end of text
+ *   __data_start__: VMA of start of the section to copy to
+ *   __data_end__: VMA of end of the section to copy to
  *
- *  All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
  */
   pSrc  = &__etext;
   pDest = &__data_start__;
@@ -228,40 +194,40 @@ void Reset_Handler(void) {
   }
 #endif /*__STARTUP_COPY_MULTIPLE */
 
-/*  This part of work usually is done in C library startup code. Otherwise,
- *  define this macro to enable it in this startup.
+/* This part of work usually is done in C library startup code.
+ * Otherwise, define this macro to enable it in this startup.
  *
- *  There are two schemes too. One can clear multiple BSS sections. Another
- *  can only clear one section. The former is more size expensive than the
- *  latter.
+ * There are two schemes too.
+ * One can clear multiple BSS sections. Another can only clear one section.
+ * The former is more size expensive than the latter.
  *
- *  Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- *  Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
  */
 #ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/*  Multiple sections scheme.
+/* Multiple sections scheme.
  *
- *  Between symbol address __copy_table_start__ and __copy_table_end__,
- *  there are array of tuples specifying:
- *    offset 0: Start of a BSS section
- *    offset 4: Size of this BSS section. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ *   offset 0: Start of a BSS section
+ *   offset 4: Size of this BSS section. Must be multiply of 4
  */
   pTable = &__zero_table_start__;
 
   for (; pTable < &__zero_table_end__; pTable = pTable + 2) {
-		pDest = (uint32_t*)*(pTable + 0);
-		for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
+    pDest = (uint32_t*)*(pTable + 0);
+    for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
       *pDest++ = 0;
-		}
-	}
+    }
+  }
 #elif defined (__STARTUP_CLEAR_BSS)
-/*  Single BSS section scheme.
+/* Single BSS section scheme.
  *
- *  The BSS section is specified by following symbols
- *    __bss_start__: start of the BSS section.
- *    __bss_end__: end of the BSS section.
+ * The BSS section is specified by following symbols
+ *   __bss_start__: start of the BSS section.
+ *   __bss_end__: end of the BSS section.
  *
- *  Both addresses must be aligned to 4 bytes boundary.
+ * Both addresses must be aligned to 4 bytes boundary.
  */
   pDest = &__bss_start__;
 
@@ -270,15 +236,10 @@ void Reset_Handler(void) {
   }
 #endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
 
-#ifndef __NO_SYSTEM_INIT
-	SystemInit();
-#endif
-
-#ifndef __START
-#define __START _start
-#endif
-	__START();
+  __set_MSPLIM((uint32_t)&__StackLimit);
 
+  SystemInit();                             /* CMSIS System Initialization */
+  _start();                                 /* Enter PreeMain (C library entry point) */
 }
 
 
@@ -287,5 +248,5 @@ void Reset_Handler(void) {
  *----------------------------------------------------------------------------*/
 void Default_Handler(void) {
 
-	while(1);
+  while(1);
 }

CMSIS/CoreValidation/Tests/Cortex-M23/GCC/RTE/Device/ARMCM23/system_ARMCM23.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
  * @file     system_ARMCM23.c
  * @brief    CMSIS Device System Source File for
- *           ARMCM23 Device Series
- * @version  V5.00
- * @date     21. October 2016
+ *           ARMCM23 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -38,9 +38,9 @@
 /*----------------------------------------------------------------------------
   Define clocks
  *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+#define  XTAL            (50000000UL)     /* Oscillator frequency */
 
-#define  SYSTEM_CLOCK    (5U * XTAL)
+#define  SYSTEM_CLOCK    (XTAL / 2U)
 
 
 /*----------------------------------------------------------------------------
@@ -53,7 +53,7 @@
 /*----------------------------------------------------------------------------
   System Core Clock Variable
  *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */
 
 
 /*----------------------------------------------------------------------------

CMSIS/CoreValidation/Tests/Cortex-M23/IAR/RTE/Device/ARMCM23/partition_ARMCM23.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     partition_ARMCM23.h
  * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM23
- * @version  V5.00
- * @date     28. October 2016
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -707,374 +707,6 @@
 //   </e>
 */
 
-/*
-//   <e>Initialize ITNS 8 (Interrupts 256..287)
-*/
-#define NVIC_INIT_ITNS8    0
-
-/*
-// Interrupts 0..31
-//   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 259 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 260 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 261 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 262 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 263 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 264 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 265 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS8_VAL      0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 9 (Interrupts 288..319)
-*/
-#define NVIC_INIT_ITNS9    0
-
-/*
-// Interrupts 32..63
-//   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 291 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 292 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 293 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 294 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 295 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 296 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 297 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS9_VAL      0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 10 (Interrupts 320..351)
-*/
-#define NVIC_INIT_ITNS10   0
-
-/*
-// Interrupts 64..95
-//   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 323 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 324 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 325 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 326 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 327 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 328 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 329 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS10_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 11 (Interrupts 352..383)
-*/
-#define NVIC_INIT_ITNS11   0
-
-/*
-// Interrupts 96..127
-//   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 355 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 356 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 357 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 358 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 359 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 360 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 361 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS11_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 12 (Interrupts 384..415)
-*/
-#define NVIC_INIT_ITNS12   0
-
-/*
-// Interrupts 128..159
-//   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 387 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 388 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 389 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 390 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 391 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 392 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 393 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS12_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 13 (Interrupts 416..447)
-*/
-#define NVIC_INIT_ITNS13   0
-
-/*
-// Interrupts 160..191
-//   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 419 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 420 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 421 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 422 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 423 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 424 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 425 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS13_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 14 (Interrupts 448..479)
-*/
-#define NVIC_INIT_ITNS14   0
-
-/*
-// Interrupts 192..223
-//   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 451 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 452 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 453 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 454 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 455 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 456 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 457 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS14_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 15 (Interrupts 480..511)
-*/
-#define NVIC_INIT_ITNS15   0
-
-/*
-// Interrupts 224..255
-//   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 483 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 484 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 485 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 486 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 487 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 488 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 489 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS15_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
 /*
 // </h>
 */
@@ -1193,38 +825,6 @@ __STATIC_INLINE void TZ_SAU_Setup (void)
     NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;
   #endif
 
-  #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)
-    NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)
-    NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)
-    NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)
-    NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)
-    NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)
-    NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)
-    NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)
-    NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;
-  #endif
-
   /* repeat this for all possible ITNS elements */
 
 }

CMSIS/CoreValidation/Tests/Cortex-M23/IAR/RTE/Device/ARMCM23/startup_ARMCM23.s

@@ -1,12 +1,12 @@
 ;/**************************************************************************//**
 ; * @file     startup_ARMCM23.s
 ; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM23 Device Series
-; * @version  V5.00
-; * @date     21. October 2016
+; *           ARMCM23 Device
+; * @version  V5.3.1
+; * @date     09. July 2018
 ; ******************************************************************************/
 ;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
 ; *
 ; * SPDX-License-Identifier: Apache-2.0
 ; *
@@ -39,234 +39,109 @@
 ; Cortex-M version
 ;
 
-        MODULE  ?cstartup
+                MODULE   ?cstartup
 
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
+                ;; Forward declaration of sections.
+                SECTION  CSTACK:DATA:NOROOT(3)
 
-        SECTION .intvec:CODE:NOROOT(2)
+                SECTION  .intvec:CODE:NOROOT(2)
 
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit
-        PUBLIC  __vector_table
-        PUBLIC  __vector_table_0x1c
-        PUBLIC  __Vectors
-        PUBLIC  __Vectors_End
-        PUBLIC  __Vectors_Size
+                EXTERN   __iar_program_start
+                EXTERN   SystemInit
+                PUBLIC   __vector_table
+                PUBLIC   __vector_table_0x1c
+                PUBLIC   __Vectors
+                PUBLIC   __Vectors_End
+                PUBLIC   __Vectors_Size
 
-        DATA
+                DATA
 
 __vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler
-
-        DCD     NMI_Handler
-        DCD     HardFault_Handler
-        DCD     0
-        DCD     0
-        DCD     0
+                DCD      sfe(CSTACK)                         ;     Top of Stack
+                DCD      Reset_Handler                       ;     Reset Handler
+                DCD      NMI_Handler                         ; -14 NMI Handler
+                DCD      HardFault_Handler                   ; -13 Hard Fault Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
 __vector_table_0x1c
-        DCD     0
-        DCD     0
-        DCD     0
-        DCD     0
-        DCD     SVC_Handler
-        DCD     0
-        DCD     0
-        DCD     PendSV_Handler
-        DCD     SysTick_Handler
-
-        ; External Interrupts
-        DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
-        DCD     RTC_IRQHandler            ;  1:  Real Time Clock
-        DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
-        DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
-        DCD     MCIA_IRQHandler           ;  4:  MCIa
-        DCD     MCIB_IRQHandler           ;  5:  MCIb
-        DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
-        DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
-        DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
-        DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
-        DCD     AACI_IRQHandler           ; 10: AACI / AC97
-        DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
-        DCD     ENET_IRQHandler           ; 12: Ethernet
-        DCD     USBDC_IRQHandler          ; 13: USB Device
-        DCD     USBHC_IRQHandler          ; 14: USB Host Controller
-        DCD     CHLCD_IRQHandler          ; 15: Character LCD
-        DCD     FLEXRAY_IRQHandler        ; 16: Flexray
-        DCD     CAN_IRQHandler            ; 17: CAN
-        DCD     LIN_IRQHandler            ; 18: LIN
-        DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
-        DCD     0                         ; 20: Reserved
-        DCD     0                         ; 21: Reserved
-        DCD     0                         ; 22: Reserved
-        DCD     0                         ; 23: Reserved
-        DCD     0                         ; 24: Reserved
-        DCD     0                         ; 25: Reserved
-        DCD     0                         ; 26: Reserved
-        DCD     0                         ; 27: Reserved
-        DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
-        DCD     0                         ; 29: Reserved - CPU FPGA
-        DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
-        DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      SVC_Handler                         ;  -5 SVCall Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      PendSV_Handler                      ;  -2 PendSV Handler
+                DCD      SysTick_Handler                     ;  -1 SysTick Handler
+
+                ; Interrupts
+                DCD      Interrupt0_Handler                  ;   0 Interrupt 0
+                DCD      Interrupt1_Handler                  ;   1 Interrupt 1
+                DCD      Interrupt2_Handler                  ;   2 Interrupt 2
+                DCD      Interrupt3_Handler                  ;   3 Interrupt 3
+                DCD      Interrupt4_Handler                  ;   4 Interrupt 4
+                DCD      Interrupt5_Handler                  ;   5 Interrupt 5
+                DCD      Interrupt6_Handler                  ;   6 Interrupt 6
+                DCD      Interrupt7_Handler                  ;   7 Interrupt 7
+                DCD      Interrupt8_Handler                  ;   8 Interrupt 8
+                DCD      Interrupt9_Handler                  ;   9 Interrupt 9
+
+                DS32    (214)                                ; Interrupts 10 .. 224 are left out
 __Vectors_End
 
-__Vectors       EQU   __vector_table
-__Vectors_Size  EQU   __Vectors_End - __Vectors
+__Vectors       EQU      __vector_table
+__Vectors_Size  EQU      __Vectors_End - __Vectors
 
 
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
+                THUMB
 
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
+; Reset Handler
 
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
+                PUBWEAK  Reset_Handler
+                SECTION  .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+                LDR      R0, =SystemInit
+                BLX      R0
+                LDR      R0, =__iar_program_start
+                BX       R0
+
+
+                PUBWEAK NMI_Handler
+                PUBWEAK HardFault_Handler
+                PUBWEAK SVC_Handler
+                PUBWEAK PendSV_Handler
+                PUBWEAK SysTick_Handler
+
+                PUBWEAK Interrupt0_Handler
+                PUBWEAK Interrupt1_Handler
+                PUBWEAK Interrupt2_Handler
+                PUBWEAK Interrupt3_Handler
+                PUBWEAK Interrupt4_Handler
+                PUBWEAK Interrupt5_Handler
+                PUBWEAK Interrupt6_Handler
+                PUBWEAK Interrupt7_Handler
+                PUBWEAK Interrupt8_Handler
+                PUBWEAK Interrupt9_Handler
+                SECTION .text:CODE:REORDER:NOROOT(1)
 NMI_Handler
-        B NMI_Handler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 HardFault_Handler
-        B HardFault_Handler
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 SVC_Handler
-        B SVC_Handler
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 SysTick_Handler
-        B SysTick_Handler
-
-        PUBWEAK WDT_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WDT_IRQHandler
-        B WDT_IRQHandler
-
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-
-        PUBWEAK TIM0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM0_IRQHandler
-        B TIM0_IRQHandler
-
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-
-        PUBWEAK MCIA_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MCIA_IRQHandler
-        B MCIA_IRQHandler
-
-        PUBWEAK MCIB_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MCIB_IRQHandler
-        B MCIB_IRQHandler
-
-        PUBWEAK UART0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART0_IRQHandler
-        B UART0_IRQHandler
-
-        PUBWEAK UART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART1_IRQHandler
-        B UART1_IRQHandler
-
-        PUBWEAK UART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART2_IRQHandler
-        B UART2_IRQHandler
-
-        PUBWEAK UART4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
-        B UART4_IRQHandler
-
-        PUBWEAK AACI_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-AACI_IRQHandler
-        B AACI_IRQHandler
-
-        PUBWEAK CLCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CLCD_IRQHandler
-        B CLCD_IRQHandler
-
-        PUBWEAK ENET_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ENET_IRQHandler
-        B ENET_IRQHandler
-
-        PUBWEAK USBDC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USBDC_IRQHandler
-        B USBDC_IRQHandler
-
-        PUBWEAK USBHC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USBHC_IRQHandler
-        B USBHC_IRQHandler
-
-        PUBWEAK CHLCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CHLCD_IRQHandler
-        B CHLCD_IRQHandler
-
-        PUBWEAK FLEXRAY_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLEXRAY_IRQHandler
-        B FLEXRAY_IRQHandler
-
-        PUBWEAK CAN_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN_IRQHandler
-        B CAN_IRQHandler
-
-        PUBWEAK LIN_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-LIN_IRQHandler
-        B LIN_IRQHandler
-
-        PUBWEAK I2C_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C_IRQHandler
-        B I2C_IRQHandler
-
-        PUBWEAK CPU_CLCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CPU_CLCD_IRQHandler
-        B CPU_CLCD_IRQHandler
-
-        PUBWEAK UART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART3_IRQHandler
-        B UART3_IRQHandler
-
-        PUBWEAK SPI_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI_IRQHandler
-        B SPI_IRQHandler
 
-        END
+Interrupt0_Handler
+Interrupt1_Handler
+Interrupt2_Handler
+Interrupt3_Handler
+Interrupt4_Handler
+Interrupt5_Handler
+Interrupt6_Handler
+Interrupt7_Handler
+Interrupt8_Handler
+Interrupt9_Handler
+Default_Handler
+                B        .
+
+
+                END

CMSIS/CoreValidation/Tests/Cortex-M23/IAR/RTE/Device/ARMCM23/system_ARMCM23.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
  * @file     system_ARMCM23.c
  * @brief    CMSIS Device System Source File for
- *           ARMCM23 Device Series
- * @version  V5.00
- * @date     21. October 2016
+ *           ARMCM23 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -38,9 +38,9 @@
 /*----------------------------------------------------------------------------
   Define clocks
  *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+#define  XTAL            (50000000UL)     /* Oscillator frequency */
 
-#define  SYSTEM_CLOCK    (5U * XTAL)
+#define  SYSTEM_CLOCK    (XTAL / 2U)
 
 
 /*----------------------------------------------------------------------------
@@ -53,7 +53,7 @@
 /*----------------------------------------------------------------------------
   System Core Clock Variable
  *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */
 
 
 /*----------------------------------------------------------------------------

CMSIS/CoreValidation/Tests/Cortex-M23NS/AC6/Bootloader/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     partition_ARMCM23.h
  * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM23
- * @version  V5.00
- * @date     28. October 2016
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -707,374 +707,6 @@
 //   </e>
 */
 
-/*
-//   <e>Initialize ITNS 8 (Interrupts 256..287)
-*/
-#define NVIC_INIT_ITNS8    0
-
-/*
-// Interrupts 0..31
-//   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 259 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 260 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 261 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 262 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 263 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 264 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 265 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS8_VAL      0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 9 (Interrupts 288..319)
-*/
-#define NVIC_INIT_ITNS9    0
-
-/*
-// Interrupts 32..63
-//   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 291 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 292 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 293 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 294 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 295 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 296 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 297 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS9_VAL      0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 10 (Interrupts 320..351)
-*/
-#define NVIC_INIT_ITNS10   0
-
-/*
-// Interrupts 64..95
-//   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 323 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 324 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 325 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 326 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 327 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 328 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 329 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS10_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 11 (Interrupts 352..383)
-*/
-#define NVIC_INIT_ITNS11   0
-
-/*
-// Interrupts 96..127
-//   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 355 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 356 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 357 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 358 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 359 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 360 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 361 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS11_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 12 (Interrupts 384..415)
-*/
-#define NVIC_INIT_ITNS12   0
-
-/*
-// Interrupts 128..159
-//   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 387 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 388 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 389 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 390 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 391 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 392 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 393 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS12_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 13 (Interrupts 416..447)
-*/
-#define NVIC_INIT_ITNS13   0
-
-/*
-// Interrupts 160..191
-//   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 419 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 420 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 421 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 422 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 423 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 424 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 425 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS13_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 14 (Interrupts 448..479)
-*/
-#define NVIC_INIT_ITNS14   0
-
-/*
-// Interrupts 192..223
-//   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 451 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 452 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 453 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 454 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 455 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 456 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 457 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS14_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 15 (Interrupts 480..511)
-*/
-#define NVIC_INIT_ITNS15   0
-
-/*
-// Interrupts 224..255
-//   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 483 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 484 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 485 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 486 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 487 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 488 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 489 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS15_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
 /*
 // </h>
 */
@@ -1193,38 +825,6 @@ __STATIC_INLINE void TZ_SAU_Setup (void)
     NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;
   #endif
 
-  #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)
-    NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)
-    NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)
-    NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)
-    NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)
-    NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)
-    NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)
-    NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)
-    NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;
-  #endif
-
   /* repeat this for all possible ITNS elements */
 
 }

CMSIS/CoreValidation/Tests/Cortex-M23NS/AC6/Bootloader/RTE/Device/ARMCM23_TZ/startup_ARMCM23.s

@@ -1,12 +1,12 @@
 ;/**************************************************************************//**
 ; * @file     startup_ARMCM23.s
 ; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM23 Device Series
-; * @version  V5.00
-; * @date     21. October 2016
+; *           ARMCM23 Device
+; * @version  V5.3.1
+; * @date     09. July 2018
 ; ******************************************************************************/
 ;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
 ; *
 ; * SPDX-License-Identifier: Apache-2.0
 ; *
@@ -23,32 +23,33 @@
 ; * limitations under the License.
 ; */
 
-;/*
 ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
 
 
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Stack Configuration
+;  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
 
-Stack_Size      EQU     0x00000400
+Stack_Size      EQU      0x00000400
 
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
+                AREA     STACK, NOINIT, READWRITE, ALIGN=3
+__stack_limit
+Stack_Mem       SPACE    Stack_Size
 __initial_sp
 
 
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Heap Configuration
+;  <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
 
-Heap_Size       EQU     0x00000C00
+Heap_Size       EQU      0x00000C00
 
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+                IF       Heap_Size != 0                      ; Heap is provided
+                AREA     HEAP, NOINIT, READWRITE, ALIGN=3
 __heap_base
-Heap_Mem        SPACE   Heap_Size
+Heap_Mem        SPACE    Heap_Size
 __heap_limit
+                ENDIF
 
 
                 PRESERVE8
@@ -57,186 +58,105 @@ __heap_limit
 
 ; Vector Table Mapped to Address 0 at Reset
 
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
-                DCD     RTC_IRQHandler            ;  1:  Real Time Clock
-                DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
-                DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
-                DCD     MCIA_IRQHandler           ;  4:  MCIa
-                DCD     MCIB_IRQHandler           ;  5:  MCIb
-                DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
-                DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
-                DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
-                DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
-                DCD     AACI_IRQHandler           ; 10: AACI / AC97
-                DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
-                DCD     ENET_IRQHandler           ; 12: Ethernet
-                DCD     USBDC_IRQHandler          ; 13: USB Device
-                DCD     USBHC_IRQHandler          ; 14: USB Host Controller
-                DCD     CHLCD_IRQHandler          ; 15: Character LCD
-                DCD     FLEXRAY_IRQHandler        ; 16: Flexray
-                DCD     CAN_IRQHandler            ; 17: CAN
-                DCD     LIN_IRQHandler            ; 18: LIN
-                DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
-                DCD     0                         ; 20: Reserved
-                DCD     0                         ; 21: Reserved
-                DCD     0                         ; 22: Reserved
-                DCD     0                         ; 23: Reserved
-                DCD     0                         ; 24: Reserved
-                DCD     0                         ; 25: Reserved
-                DCD     0                         ; 26: Reserved
-                DCD     0                         ; 27: Reserved
-                DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
-                DCD     0                         ; 29: Reserved - CPU FPGA
-                DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
-                DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
+                AREA     RESET, DATA, READONLY
+                EXPORT   __Vectors
+                EXPORT   __Vectors_End
+                EXPORT   __Vectors_Size
+
+__Vectors       DCD      __initial_sp                        ;     Top of Stack
+                DCD      Reset_Handler                       ;     Reset Handler
+                DCD      NMI_Handler                         ; -14 NMI Handler
+                DCD      HardFault_Handler                   ; -13 Hard Fault Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      SVC_Handler                         ;  -5 SVCall Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      PendSV_Handler                      ;  -2 PendSV Handler
+                DCD      SysTick_Handler                     ;  -1 SysTick Handler
+
+                ; Interrupts
+                DCD      Interrupt0_Handler                  ;   0 Interrupt 0
+                DCD      Interrupt1_Handler                  ;   1 Interrupt 1
+                DCD      Interrupt2_Handler                  ;   2 Interrupt 2
+                DCD      Interrupt3_Handler                  ;   3 Interrupt 3
+                DCD      Interrupt4_Handler                  ;   4 Interrupt 4
+                DCD      Interrupt5_Handler                  ;   5 Interrupt 5
+                DCD      Interrupt6_Handler                  ;   6 Interrupt 6
+                DCD      Interrupt7_Handler                  ;   7 Interrupt 7
+                DCD      Interrupt8_Handler                  ;   8 Interrupt 8
+                DCD      Interrupt9_Handler                  ;   9 Interrupt 9
+
+                SPACE    (214 * 4)                           ; Interrupts 10 .. 224 are left out
 __Vectors_End
+__Vectors_Size  EQU      __Vectors_End - __Vectors
 
-__Vectors_Size  EQU     __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
 
+                AREA     |.text|, CODE, READONLY
 
 ; Reset Handler
 
 Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  SystemInit
-                IMPORT  __main
-                LDR     R0, =SystemInit
-                BLX     R0
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-
+                EXPORT   Reset_Handler             [WEAK]
+                IMPORT   SystemInit
+                IMPORT   __main
 
-; Dummy Exception Handlers (infinite loops which can be modified)
+                LDR      R0, =__stack_limit
+                MSR      MSPLIM, R0                          ; Non-secure version of MSPLIM is RAZ/WI
 
-NMI_Handler     PROC
-                EXPORT  NMI_Handler               [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
+                LDR      R0, =SystemInit
+                BLX      R0
+                LDR      R0, =__main
+                BX       R0
                 ENDP
 
-Default_Handler PROC
-
-                EXPORT  WDT_IRQHandler            [WEAK]
-                EXPORT  RTC_IRQHandler            [WEAK]
-                EXPORT  TIM0_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler           [WEAK]
-                EXPORT  MCIA_IRQHandler           [WEAK]
-                EXPORT  MCIB_IRQHandler           [WEAK]
-                EXPORT  UART0_IRQHandler          [WEAK]
-                EXPORT  UART1_IRQHandler          [WEAK]
-                EXPORT  UART2_IRQHandler          [WEAK]
-                EXPORT  UART3_IRQHandler          [WEAK]
-                EXPORT  UART4_IRQHandler          [WEAK]
-                EXPORT  AACI_IRQHandler           [WEAK]
-                EXPORT  CLCD_IRQHandler           [WEAK]
-                EXPORT  ENET_IRQHandler           [WEAK]
-                EXPORT  USBDC_IRQHandler          [WEAK]
-                EXPORT  USBHC_IRQHandler          [WEAK]
-                EXPORT  CHLCD_IRQHandler          [WEAK]
-                EXPORT  FLEXRAY_IRQHandler        [WEAK]
-                EXPORT  CAN_IRQHandler            [WEAK]
-                EXPORT  LIN_IRQHandler            [WEAK]
-                EXPORT  I2C_IRQHandler            [WEAK]
-                EXPORT  CPU_CLCD_IRQHandler       [WEAK]
-                EXPORT  SPI_IRQHandler            [WEAK]
-
-WDT_IRQHandler
-RTC_IRQHandler
-TIM0_IRQHandler
-TIM2_IRQHandler
-MCIA_IRQHandler
-MCIB_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-UART3_IRQHandler
-UART4_IRQHandler
-AACI_IRQHandler
-CLCD_IRQHandler
-ENET_IRQHandler
-USBDC_IRQHandler
-USBHC_IRQHandler
-CHLCD_IRQHandler
-FLEXRAY_IRQHandler
-CAN_IRQHandler
-LIN_IRQHandler
-I2C_IRQHandler
-CPU_CLCD_IRQHandler
-SPI_IRQHandler
-                B       .
 
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+                MACRO
+                Set_Default_Handler  $Handler_Name
+$Handler_Name   PROC
+                EXPORT   $Handler_Name             [WEAK]
+                B        .
                 ENDP
+                MEND
 
 
-                ALIGN
-
-
-; User Initial Stack & Heap
-
-                IF      :DEF:__MICROLIB
+; Default exception/interrupt handler
 
-                EXPORT  __initial_sp
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
+                Set_Default_Handler  NMI_Handler
+                Set_Default_Handler  HardFault_Handler
+                Set_Default_Handler  SVC_Handler
+                Set_Default_Handler  PendSV_Handler
+                Set_Default_Handler  SysTick_Handler
 
-                ELSE
+                Set_Default_Handler  Interrupt0_Handler
+                Set_Default_Handler  Interrupt1_Handler
+                Set_Default_Handler  Interrupt2_Handler
+                Set_Default_Handler  Interrupt3_Handler
+                Set_Default_Handler  Interrupt4_Handler
+                Set_Default_Handler  Interrupt5_Handler
+                Set_Default_Handler  Interrupt6_Handler
+                Set_Default_Handler  Interrupt7_Handler
+                Set_Default_Handler  Interrupt8_Handler
+                Set_Default_Handler  Interrupt9_Handler
 
-                IMPORT  __use_two_region_memory
-                EXPORT  __user_initial_stackheap
+                ALIGN
 
-__user_initial_stackheap PROC
-                LDR     R0, =  Heap_Mem
-                LDR     R1, =(Stack_Mem + Stack_Size)
-                LDR     R2, = (Heap_Mem +  Heap_Size)
-                LDR     R3, = Stack_Mem
-                BX      LR
-                ENDP
 
-                ALIGN
+; User setup Stack & Heap
 
+                EXPORT   __stack_limit
+                EXPORT   __initial_sp
+                IF       Heap_Size != 0                      ; Heap is provided
+                EXPORT   __heap_base
+                EXPORT   __heap_limit
                 ENDIF
 
-
                 END

CMSIS/CoreValidation/Tests/Cortex-M23NS/AC6/Bootloader/RTE/Device/ARMCM23_TZ/system_ARMCM23.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
  * @file     system_ARMCM23.c
  * @brief    CMSIS Device System Source File for
- *           ARMCM23 Device Series
- * @version  V5.00
- * @date     21. October 2016
+ *           ARMCM23 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -38,9 +38,9 @@
 /*----------------------------------------------------------------------------
   Define clocks
  *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+#define  XTAL            (50000000UL)     /* Oscillator frequency */
 
-#define  SYSTEM_CLOCK    (5U * XTAL)
+#define  SYSTEM_CLOCK    (XTAL / 2U)
 
 
 /*----------------------------------------------------------------------------
@@ -53,7 +53,7 @@
 /*----------------------------------------------------------------------------
   System Core Clock Variable
  *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */
 
 
 /*----------------------------------------------------------------------------

CMSIS/CoreValidation/Tests/Cortex-M23NS/AC6/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     partition_ARMCM23.h
  * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM23
- * @version  V5.00
- * @date     28. October 2016
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -707,374 +707,6 @@
 //   </e>
 */
 
-/*
-//   <e>Initialize ITNS 8 (Interrupts 256..287)
-*/
-#define NVIC_INIT_ITNS8    0
-
-/*
-// Interrupts 0..31
-//   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 259 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 260 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 261 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 262 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 263 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 264 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 265 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS8_VAL      0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 9 (Interrupts 288..319)
-*/
-#define NVIC_INIT_ITNS9    0
-
-/*
-// Interrupts 32..63
-//   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 291 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 292 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 293 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 294 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 295 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 296 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 297 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS9_VAL      0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 10 (Interrupts 320..351)
-*/
-#define NVIC_INIT_ITNS10   0
-
-/*
-// Interrupts 64..95
-//   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 323 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 324 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 325 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 326 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 327 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 328 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 329 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS10_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 11 (Interrupts 352..383)
-*/
-#define NVIC_INIT_ITNS11   0
-
-/*
-// Interrupts 96..127
-//   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 355 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 356 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 357 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 358 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 359 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 360 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 361 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS11_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 12 (Interrupts 384..415)
-*/
-#define NVIC_INIT_ITNS12   0
-
-/*
-// Interrupts 128..159
-//   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 387 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 388 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 389 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 390 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 391 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 392 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 393 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS12_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 13 (Interrupts 416..447)
-*/
-#define NVIC_INIT_ITNS13   0
-
-/*
-// Interrupts 160..191
-//   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 419 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 420 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 421 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 422 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 423 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 424 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 425 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS13_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 14 (Interrupts 448..479)
-*/
-#define NVIC_INIT_ITNS14   0
-
-/*
-// Interrupts 192..223
-//   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 451 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 452 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 453 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 454 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 455 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 456 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 457 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS14_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 15 (Interrupts 480..511)
-*/
-#define NVIC_INIT_ITNS15   0
-
-/*
-// Interrupts 224..255
-//   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 483 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 484 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 485 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 486 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 487 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 488 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 489 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS15_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
 /*
 // </h>
 */
@@ -1193,38 +825,6 @@ __STATIC_INLINE void TZ_SAU_Setup (void)
     NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;
   #endif
 
-  #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)
-    NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)
-    NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)
-    NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)
-    NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)
-    NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)
-    NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)
-    NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)
-    NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;
-  #endif
-
   /* repeat this for all possible ITNS elements */
 
 }

CMSIS/CoreValidation/Tests/Cortex-M23NS/AC6/RTE/Device/ARMCM23_TZ/startup_ARMCM23.s

@@ -1,12 +1,12 @@
 ;/**************************************************************************//**
 ; * @file     startup_ARMCM23.s
 ; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM23 Device Series
-; * @version  V5.00
-; * @date     21. October 2016
+; *           ARMCM23 Device
+; * @version  V5.3.1
+; * @date     09. July 2018
 ; ******************************************************************************/
 ;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
 ; *
 ; * SPDX-License-Identifier: Apache-2.0
 ; *
@@ -23,32 +23,33 @@
 ; * limitations under the License.
 ; */
 
-;/*
 ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
 
 
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Stack Configuration
+;  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
 
-Stack_Size      EQU     0x00000400
+Stack_Size      EQU      0x00000400
 
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
+                AREA     STACK, NOINIT, READWRITE, ALIGN=3
+__stack_limit
+Stack_Mem       SPACE    Stack_Size
 __initial_sp
 
 
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Heap Configuration
+;  <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
 
-Heap_Size       EQU     0x00000C00
+Heap_Size       EQU      0x00000C00
 
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+                IF       Heap_Size != 0                      ; Heap is provided
+                AREA     HEAP, NOINIT, READWRITE, ALIGN=3
 __heap_base
-Heap_Mem        SPACE   Heap_Size
+Heap_Mem        SPACE    Heap_Size
 __heap_limit
+                ENDIF
 
 
                 PRESERVE8
@@ -57,186 +58,105 @@ __heap_limit
 
 ; Vector Table Mapped to Address 0 at Reset
 
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
-                DCD     RTC_IRQHandler            ;  1:  Real Time Clock
-                DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
-                DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
-                DCD     MCIA_IRQHandler           ;  4:  MCIa
-                DCD     MCIB_IRQHandler           ;  5:  MCIb
-                DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
-                DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
-                DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
-                DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
-                DCD     AACI_IRQHandler           ; 10: AACI / AC97
-                DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
-                DCD     ENET_IRQHandler           ; 12: Ethernet
-                DCD     USBDC_IRQHandler          ; 13: USB Device
-                DCD     USBHC_IRQHandler          ; 14: USB Host Controller
-                DCD     CHLCD_IRQHandler          ; 15: Character LCD
-                DCD     FLEXRAY_IRQHandler        ; 16: Flexray
-                DCD     CAN_IRQHandler            ; 17: CAN
-                DCD     LIN_IRQHandler            ; 18: LIN
-                DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
-                DCD     0                         ; 20: Reserved
-                DCD     0                         ; 21: Reserved
-                DCD     0                         ; 22: Reserved
-                DCD     0                         ; 23: Reserved
-                DCD     0                         ; 24: Reserved
-                DCD     0                         ; 25: Reserved
-                DCD     0                         ; 26: Reserved
-                DCD     0                         ; 27: Reserved
-                DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
-                DCD     0                         ; 29: Reserved - CPU FPGA
-                DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
-                DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
+                AREA     RESET, DATA, READONLY
+                EXPORT   __Vectors
+                EXPORT   __Vectors_End
+                EXPORT   __Vectors_Size
+
+__Vectors       DCD      __initial_sp                        ;     Top of Stack
+                DCD      Reset_Handler                       ;     Reset Handler
+                DCD      NMI_Handler                         ; -14 NMI Handler
+                DCD      HardFault_Handler                   ; -13 Hard Fault Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      SVC_Handler                         ;  -5 SVCall Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      PendSV_Handler                      ;  -2 PendSV Handler
+                DCD      SysTick_Handler                     ;  -1 SysTick Handler
+
+                ; Interrupts
+                DCD      Interrupt0_Handler                  ;   0 Interrupt 0
+                DCD      Interrupt1_Handler                  ;   1 Interrupt 1
+                DCD      Interrupt2_Handler                  ;   2 Interrupt 2
+                DCD      Interrupt3_Handler                  ;   3 Interrupt 3
+                DCD      Interrupt4_Handler                  ;   4 Interrupt 4
+                DCD      Interrupt5_Handler                  ;   5 Interrupt 5
+                DCD      Interrupt6_Handler                  ;   6 Interrupt 6
+                DCD      Interrupt7_Handler                  ;   7 Interrupt 7
+                DCD      Interrupt8_Handler                  ;   8 Interrupt 8
+                DCD      Interrupt9_Handler                  ;   9 Interrupt 9
+
+                SPACE    (214 * 4)                           ; Interrupts 10 .. 224 are left out
 __Vectors_End
+__Vectors_Size  EQU      __Vectors_End - __Vectors
 
-__Vectors_Size  EQU     __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
 
+                AREA     |.text|, CODE, READONLY
 
 ; Reset Handler
 
 Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  SystemInit
-                IMPORT  __main
-                LDR     R0, =SystemInit
-                BLX     R0
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-
+                EXPORT   Reset_Handler             [WEAK]
+                IMPORT   SystemInit
+                IMPORT   __main
 
-; Dummy Exception Handlers (infinite loops which can be modified)
+                LDR      R0, =__stack_limit
+                MSR      MSPLIM, R0                          ; Non-secure version of MSPLIM is RAZ/WI
 
-NMI_Handler     PROC
-                EXPORT  NMI_Handler               [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
+                LDR      R0, =SystemInit
+                BLX      R0
+                LDR      R0, =__main
+                BX       R0
                 ENDP
 
-Default_Handler PROC
-
-                EXPORT  WDT_IRQHandler            [WEAK]
-                EXPORT  RTC_IRQHandler            [WEAK]
-                EXPORT  TIM0_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler           [WEAK]
-                EXPORT  MCIA_IRQHandler           [WEAK]
-                EXPORT  MCIB_IRQHandler           [WEAK]
-                EXPORT  UART0_IRQHandler          [WEAK]
-                EXPORT  UART1_IRQHandler          [WEAK]
-                EXPORT  UART2_IRQHandler          [WEAK]
-                EXPORT  UART3_IRQHandler          [WEAK]
-                EXPORT  UART4_IRQHandler          [WEAK]
-                EXPORT  AACI_IRQHandler           [WEAK]
-                EXPORT  CLCD_IRQHandler           [WEAK]
-                EXPORT  ENET_IRQHandler           [WEAK]
-                EXPORT  USBDC_IRQHandler          [WEAK]
-                EXPORT  USBHC_IRQHandler          [WEAK]
-                EXPORT  CHLCD_IRQHandler          [WEAK]
-                EXPORT  FLEXRAY_IRQHandler        [WEAK]
-                EXPORT  CAN_IRQHandler            [WEAK]
-                EXPORT  LIN_IRQHandler            [WEAK]
-                EXPORT  I2C_IRQHandler            [WEAK]
-                EXPORT  CPU_CLCD_IRQHandler       [WEAK]
-                EXPORT  SPI_IRQHandler            [WEAK]
-
-WDT_IRQHandler
-RTC_IRQHandler
-TIM0_IRQHandler
-TIM2_IRQHandler
-MCIA_IRQHandler
-MCIB_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-UART3_IRQHandler
-UART4_IRQHandler
-AACI_IRQHandler
-CLCD_IRQHandler
-ENET_IRQHandler
-USBDC_IRQHandler
-USBHC_IRQHandler
-CHLCD_IRQHandler
-FLEXRAY_IRQHandler
-CAN_IRQHandler
-LIN_IRQHandler
-I2C_IRQHandler
-CPU_CLCD_IRQHandler
-SPI_IRQHandler
-                B       .
 
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+                MACRO
+                Set_Default_Handler  $Handler_Name
+$Handler_Name   PROC
+                EXPORT   $Handler_Name             [WEAK]
+                B        .
                 ENDP
+                MEND
 
 
-                ALIGN
-
-
-; User Initial Stack & Heap
-
-                IF      :DEF:__MICROLIB
+; Default exception/interrupt handler
 
-                EXPORT  __initial_sp
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
+                Set_Default_Handler  NMI_Handler
+                Set_Default_Handler  HardFault_Handler
+                Set_Default_Handler  SVC_Handler
+                Set_Default_Handler  PendSV_Handler
+                Set_Default_Handler  SysTick_Handler
 
-                ELSE
+                Set_Default_Handler  Interrupt0_Handler
+                Set_Default_Handler  Interrupt1_Handler
+                Set_Default_Handler  Interrupt2_Handler
+                Set_Default_Handler  Interrupt3_Handler
+                Set_Default_Handler  Interrupt4_Handler
+                Set_Default_Handler  Interrupt5_Handler
+                Set_Default_Handler  Interrupt6_Handler
+                Set_Default_Handler  Interrupt7_Handler
+                Set_Default_Handler  Interrupt8_Handler
+                Set_Default_Handler  Interrupt9_Handler
 
-                IMPORT  __use_two_region_memory
-                EXPORT  __user_initial_stackheap
+                ALIGN
 
-__user_initial_stackheap PROC
-                LDR     R0, =  Heap_Mem
-                LDR     R1, =(Stack_Mem + Stack_Size)
-                LDR     R2, = (Heap_Mem +  Heap_Size)
-                LDR     R3, = Stack_Mem
-                BX      LR
-                ENDP
 
-                ALIGN
+; User setup Stack & Heap
 
+                EXPORT   __stack_limit
+                EXPORT   __initial_sp
+                IF       Heap_Size != 0                      ; Heap is provided
+                EXPORT   __heap_base
+                EXPORT   __heap_limit
                 ENDIF
 
-
                 END

CMSIS/CoreValidation/Tests/Cortex-M23NS/AC6/RTE/Device/ARMCM23_TZ/system_ARMCM23.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
  * @file     system_ARMCM23.c
  * @brief    CMSIS Device System Source File for
- *           ARMCM23 Device Series
- * @version  V5.00
- * @date     21. October 2016
+ *           ARMCM23 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -38,9 +38,9 @@
 /*----------------------------------------------------------------------------
   Define clocks
  *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+#define  XTAL            (50000000UL)     /* Oscillator frequency */
 
-#define  SYSTEM_CLOCK    (5U * XTAL)
+#define  SYSTEM_CLOCK    (XTAL / 2U)
 
 
 /*----------------------------------------------------------------------------
@@ -53,7 +53,7 @@
 /*----------------------------------------------------------------------------
   System Core Clock Variable
  *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */
 
 
 /*----------------------------------------------------------------------------

CMSIS/CoreValidation/Tests/Cortex-M23NS/GCC/Bootloader/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     partition_ARMCM23.h
  * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM23
- * @version  V5.00
- * @date     28. October 2016
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -707,374 +707,6 @@
 //   </e>
 */
 
-/*
-//   <e>Initialize ITNS 8 (Interrupts 256..287)
-*/
-#define NVIC_INIT_ITNS8    0
-
-/*
-// Interrupts 0..31
-//   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 259 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 260 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 261 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 262 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 263 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 264 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 265 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS8_VAL      0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 9 (Interrupts 288..319)
-*/
-#define NVIC_INIT_ITNS9    0
-
-/*
-// Interrupts 32..63
-//   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 291 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 292 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 293 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 294 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 295 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 296 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 297 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS9_VAL      0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 10 (Interrupts 320..351)
-*/
-#define NVIC_INIT_ITNS10   0
-
-/*
-// Interrupts 64..95
-//   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 323 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 324 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 325 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 326 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 327 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 328 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 329 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS10_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 11 (Interrupts 352..383)
-*/
-#define NVIC_INIT_ITNS11   0
-
-/*
-// Interrupts 96..127
-//   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 355 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 356 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 357 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 358 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 359 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 360 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 361 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS11_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 12 (Interrupts 384..415)
-*/
-#define NVIC_INIT_ITNS12   0
-
-/*
-// Interrupts 128..159
-//   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 387 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 388 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 389 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 390 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 391 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 392 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 393 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS12_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 13 (Interrupts 416..447)
-*/
-#define NVIC_INIT_ITNS13   0
-
-/*
-// Interrupts 160..191
-//   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 419 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 420 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 421 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 422 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 423 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 424 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 425 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS13_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 14 (Interrupts 448..479)
-*/
-#define NVIC_INIT_ITNS14   0
-
-/*
-// Interrupts 192..223
-//   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 451 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 452 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 453 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 454 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 455 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 456 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 457 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS14_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 15 (Interrupts 480..511)
-*/
-#define NVIC_INIT_ITNS15   0
-
-/*
-// Interrupts 224..255
-//   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 483 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 484 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 485 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 486 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 487 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 488 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 489 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS15_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
 /*
 // </h>
 */
@@ -1193,38 +825,6 @@ __STATIC_INLINE void TZ_SAU_Setup (void)
     NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;
   #endif
 
-  #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)
-    NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)
-    NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)
-    NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)
-    NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)
-    NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)
-    NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)
-    NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)
-    NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;
-  #endif
-
   /* repeat this for all possible ITNS elements */
 
 }

CMSIS/CoreValidation/Tests/Cortex-M23NS/GCC/Bootloader/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
- * @file     startup_ARMCM23.s
+ * @file     startup_ARMCM23.c
  * @brief    CMSIS Core Device Startup File for
- *           ARMCM23 Device Series
- * @version  V5.00
- * @date     21. October 2016
+ *           ARMCM23 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -23,6 +23,10 @@
  * limitations under the License.
  */
 
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
 #include <stdint.h>
 
 
@@ -39,6 +43,7 @@ extern uint32_t __zero_table_end__;
 extern uint32_t __bss_start__;
 extern uint32_t __bss_end__;
 extern uint32_t __StackTop;
+extern uint32_t __StackLimit;
 
 /*----------------------------------------------------------------------------
   Exception / Interrupt Handler Function Prototype
@@ -49,35 +54,30 @@ typedef void( *pFunc )( void );
 /*----------------------------------------------------------------------------
   External References
  *----------------------------------------------------------------------------*/
-#ifndef __START
-extern void  _start(void) __attribute__((noreturn));    /* PreeMain (C library entry point) */
-#else
-extern int  __START(void) __attribute__((noreturn));    /* main entry point */
-#endif
-
-#ifndef __NO_SYSTEM_INIT
-extern void SystemInit (void);            /* CMSIS System Initialization      */
-#endif
+extern void _start     (void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
+extern void SystemInit (void);                           /* CMSIS System Initialization */
 
 
 /*----------------------------------------------------------------------------
   Internal References
  *----------------------------------------------------------------------------*/
-void Default_Handler(void);                          /* Default empty handler */
-void Reset_Handler(void);                            /* Reset Handler */
+void Default_Handler(void) __attribute__ ((noreturn));
+void Reset_Handler  (void) __attribute__ ((noreturn));
 
 
 /*----------------------------------------------------------------------------
   User Initial Stack & Heap
  *----------------------------------------------------------------------------*/
-#ifndef __STACK_SIZE
-  #define	__STACK_SIZE  0x00000400
-#endif
+//<h> Stack Configuration
+//  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//</h>
+#define  __STACK_SIZE  0x00000400
 static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack")));
 
-#ifndef __HEAP_SIZE
-  #define	__HEAP_SIZE   0x00000C00
-#endif
+//<h> Heap Configuration
+//  <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//</h>
+#define  __HEAP_SIZE   0x00000C00
 #if __HEAP_SIZE > 0
 static uint8_t heap[__HEAP_SIZE]   __attribute__ ((aligned(8), used, section(".heap")));
 #endif
@@ -86,94 +86,59 @@ static uint8_t heap[__HEAP_SIZE]   __attribute__ ((aligned(8), used, section(".h
 /*----------------------------------------------------------------------------
   Exception / Interrupt Handler
  *----------------------------------------------------------------------------*/
-/* ARMCM23 Processor Exceptions */
-void NMI_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
-void HardFault_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
-void SVC_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
-void PendSV_Handler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void SysTick_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
-
-/* ARMCM23 Specific Interrupts */
-void WDT_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void RTC_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM0_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM2_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIA_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIB_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART0_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART1_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART2_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART4_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void AACI_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void CLCD_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void ENET_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBDC_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBHC_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void CHLCD_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void FLEXRAY_IRQHandler  (void) __attribute__ ((weak, alias("Default_Handler")));
-void CAN_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void LIN_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void I2C_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void CPU_CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART3_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void SPI_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+/* Exceptions */
+void NMI_Handler            (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler            (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler        (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
 
 
 /*----------------------------------------------------------------------------
   Exception / Interrupt Vector table
  *----------------------------------------------------------------------------*/
-const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = {
-  /* ARMCM23 Exceptions Handler */
-  (pFunc)((uint32_t)&__StackTop),           /*      Initial Stack Pointer     */
-  Reset_Handler,                            /*      Reset Handler             */
-  NMI_Handler,                              /*      NMI Handler               */
-  HardFault_Handler,                        /*      Hard Fault Handler        */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  SVC_Handler,                              /*      SVCall Handler            */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  PendSV_Handler,                           /*      PendSV Handler            */
-  SysTick_Handler,                          /*      SysTick Handler           */
-
-  /* External interrupts */
-  WDT_IRQHandler,                           /*  0:  Watchdog Timer            */
-  RTC_IRQHandler,                           /*  1:  Real Time Clock           */
-  TIM0_IRQHandler,                          /*  2:  Timer0 / Timer1           */
-  TIM2_IRQHandler,                          /*  3:  Timer2 / Timer3           */
-  MCIA_IRQHandler,                          /*  4:  MCIa                      */
-  MCIB_IRQHandler,                          /*  5:  MCIb                      */
-  UART0_IRQHandler,                         /*  6:  UART0 - DUT FPGA          */
-  UART1_IRQHandler,                         /*  7:  UART1 - DUT FPGA          */
-  UART2_IRQHandler,                         /*  8:  UART2 - DUT FPGA          */
-  UART4_IRQHandler,                         /*  9:  UART4 - not connected     */
-  AACI_IRQHandler,                          /* 10: AACI / AC97                */
-  CLCD_IRQHandler,                          /* 11: CLCD Combined Interrupt    */
-  ENET_IRQHandler,                          /* 12: Ethernet                   */
-  USBDC_IRQHandler,                         /* 13: USB Device                 */
-  USBHC_IRQHandler,                         /* 14: USB Host Controller        */
-  CHLCD_IRQHandler,                         /* 15: Character LCD              */
-  FLEXRAY_IRQHandler,                       /* 16: Flexray                    */
-  CAN_IRQHandler,                           /* 17: CAN                        */
-  LIN_IRQHandler,                           /* 18: LIN                        */
-  I2C_IRQHandler,                           /* 19: I2C ADC/DAC                */
-  0,                                        /* 20: Reserved                   */
-  0,                                        /* 21: Reserved                   */
-  0,                                        /* 22: Reserved                   */
-  0,                                        /* 23: Reserved                   */
-  0,                                        /* 24: Reserved                   */
-  0,                                        /* 25: Reserved                   */
-  0,                                        /* 26: Reserved                   */
-  0,                                        /* 27: Reserved                   */
-  CPU_CLCD_IRQHandler,                      /* 28: Reserved - CPU FPGA CLCD   */
-  0,                                        /* 29: Reserved - CPU FPGA        */
-  UART3_IRQHandler,                         /* 30: UART3    - CPU FPGA        */
-  SPI_IRQHandler                            /* 31: SPI Touchscreen - CPU FPGA */
+extern const pFunc __Vectors[240];
+       const pFunc __Vectors[240] __attribute__ ((section(".vectors"))) = {
+  (pFunc)(&__StackTop),                     /*     Initial Stack Pointer */
+  Reset_Handler,                            /*     Reset Handler */
+  NMI_Handler,                              /* -14 NMI Handler */
+  HardFault_Handler,                        /* -13 Hard Fault Handler */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  SVC_Handler,                              /*  -5 SVCall Handler */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  PendSV_Handler,                           /*  -2 PendSV Handler */
+  SysTick_Handler,                          /*  -1 SysTick Handler */
+
+  /* Interrupts */
+  Interrupt0_Handler,                       /*   0 Interrupt 0 */
+  Interrupt1_Handler,                       /*   1 Interrupt 1 */
+  Interrupt2_Handler,                       /*   2 Interrupt 2 */
+  Interrupt3_Handler,                       /*   3 Interrupt 3 */
+  Interrupt4_Handler,                       /*   4 Interrupt 4 */
+  Interrupt5_Handler,                       /*   5 Interrupt 5 */
+  Interrupt6_Handler,                       /*   6 Interrupt 6 */
+  Interrupt7_Handler,                       /*   7 Interrupt 7 */
+  Interrupt8_Handler,                       /*   8 Interrupt 8 */
+  Interrupt9_Handler                        /*   9 Interrupt 9 */
+                                            /* Interrupts 10 .. 224 are left out */
 };
 
 
@@ -184,41 +149,42 @@ void Reset_Handler(void) {
   uint32_t *pSrc, *pDest;
   uint32_t *pTable __attribute__((unused));
 
-/*  Firstly it copies data from read only memory to RAM. There are two schemes
- *  to copy. One can copy more than one sections. Another can only copy
- *  one section.  The former scheme needs more instructions and read-only
- *  data to implement than the latter.
- *  Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.  */
+/* Firstly it copies data from read only memory to RAM.
+ * There are two schemes to copy. One can copy more than one sections.
+ * Another can copy only one section. The former scheme needs more
+ * instructions and read-only data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.
+ */
 
 #ifdef __STARTUP_COPY_MULTIPLE
-/*  Multiple sections scheme.
+/* Multiple sections scheme.
  *
- *  Between symbol address __copy_table_start__ and __copy_table_end__,
- *  there are array of triplets, each of which specify:
- *    offset 0: LMA of start of a section to copy from
- *    offset 4: VMA of start of a section to copy to
- *    offset 8: size of the section to copy. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ *   offset 0: LMA of start of a section to copy from
+ *   offset 4: VMA of start of a section to copy to
+ *   offset 8: size of the section to copy. Must be multiply of 4
  *
- *  All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
  */
   pTable = &__copy_table_start__;
 
   for (; pTable < &__copy_table_end__; pTable = pTable + 3) {
-		pSrc  = (uint32_t*)*(pTable + 0);
-		pDest = (uint32_t*)*(pTable + 1);
-		for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
+    pSrc  = (uint32_t*)*(pTable + 0);
+    pDest = (uint32_t*)*(pTable + 1);
+    for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
       *pDest++ = *pSrc++;
-		}
-	}
+    }
+  }
 #else
-/*  Single section scheme.
+/* Single section scheme.
  *
- *  The ranges of copy from/to are specified by following symbols
- *    __etext: LMA of start of the section to copy from. Usually end of text
- *    __data_start__: VMA of start of the section to copy to
- *    __data_end__: VMA of end of the section to copy to
+ * The ranges of copy from/to are specified by following symbols
+ *   __etext: LMA of start of the section to copy from. Usually end of text
+ *   __data_start__: VMA of start of the section to copy to
+ *   __data_end__: VMA of end of the section to copy to
  *
- *  All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
  */
   pSrc  = &__etext;
   pDest = &__data_start__;
@@ -228,40 +194,40 @@ void Reset_Handler(void) {
   }
 #endif /*__STARTUP_COPY_MULTIPLE */
 
-/*  This part of work usually is done in C library startup code. Otherwise,
- *  define this macro to enable it in this startup.
+/* This part of work usually is done in C library startup code.
+ * Otherwise, define this macro to enable it in this startup.
  *
- *  There are two schemes too. One can clear multiple BSS sections. Another
- *  can only clear one section. The former is more size expensive than the
- *  latter.
+ * There are two schemes too.
+ * One can clear multiple BSS sections. Another can only clear one section.
+ * The former is more size expensive than the latter.
  *
- *  Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- *  Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
  */
 #ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/*  Multiple sections scheme.
+/* Multiple sections scheme.
  *
- *  Between symbol address __copy_table_start__ and __copy_table_end__,
- *  there are array of tuples specifying:
- *    offset 0: Start of a BSS section
- *    offset 4: Size of this BSS section. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ *   offset 0: Start of a BSS section
+ *   offset 4: Size of this BSS section. Must be multiply of 4
  */
   pTable = &__zero_table_start__;
 
   for (; pTable < &__zero_table_end__; pTable = pTable + 2) {
-		pDest = (uint32_t*)*(pTable + 0);
-		for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
+    pDest = (uint32_t*)*(pTable + 0);
+    for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
       *pDest++ = 0;
-		}
-	}
+    }
+  }
 #elif defined (__STARTUP_CLEAR_BSS)
-/*  Single BSS section scheme.
+/* Single BSS section scheme.
  *
- *  The BSS section is specified by following symbols
- *    __bss_start__: start of the BSS section.
- *    __bss_end__: end of the BSS section.
+ * The BSS section is specified by following symbols
+ *   __bss_start__: start of the BSS section.
+ *   __bss_end__: end of the BSS section.
  *
- *  Both addresses must be aligned to 4 bytes boundary.
+ * Both addresses must be aligned to 4 bytes boundary.
  */
   pDest = &__bss_start__;
 
@@ -270,15 +236,10 @@ void Reset_Handler(void) {
   }
 #endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
 
-#ifndef __NO_SYSTEM_INIT
-	SystemInit();
-#endif
-
-#ifndef __START
-#define __START _start
-#endif
-	__START();
+  __set_MSPLIM((uint32_t)&__StackLimit);
 
+  SystemInit();                             /* CMSIS System Initialization */
+  _start();                                 /* Enter PreeMain (C library entry point) */
 }
 
 
@@ -287,5 +248,5 @@ void Reset_Handler(void) {
  *----------------------------------------------------------------------------*/
 void Default_Handler(void) {
 
-	while(1);
+  while(1);
 }

CMSIS/CoreValidation/Tests/Cortex-M23NS/GCC/Bootloader/RTE/Device/ARMCM23_TZ/system_ARMCM23.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
  * @file     system_ARMCM23.c
  * @brief    CMSIS Device System Source File for
- *           ARMCM23 Device Series
- * @version  V5.00
- * @date     21. October 2016
+ *           ARMCM23 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -38,9 +38,9 @@
 /*----------------------------------------------------------------------------
   Define clocks
  *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+#define  XTAL            (50000000UL)     /* Oscillator frequency */
 
-#define  SYSTEM_CLOCK    (5U * XTAL)
+#define  SYSTEM_CLOCK    (XTAL / 2U)
 
 
 /*----------------------------------------------------------------------------
@@ -53,7 +53,7 @@
 /*----------------------------------------------------------------------------
   System Core Clock Variable
  *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */
 
 
 /*----------------------------------------------------------------------------

CMSIS/CoreValidation/Tests/Cortex-M23NS/GCC/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     partition_ARMCM23.h
  * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM23
- * @version  V5.00
- * @date     28. October 2016
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -707,374 +707,6 @@
 //   </e>
 */
 
-/*
-//   <e>Initialize ITNS 8 (Interrupts 256..287)
-*/
-#define NVIC_INIT_ITNS8    0
-
-/*
-// Interrupts 0..31
-//   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 259 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 260 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 261 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 262 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 263 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 264 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 265 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS8_VAL      0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 9 (Interrupts 288..319)
-*/
-#define NVIC_INIT_ITNS9    0
-
-/*
-// Interrupts 32..63
-//   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 291 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 292 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 293 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 294 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 295 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 296 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 297 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS9_VAL      0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 10 (Interrupts 320..351)
-*/
-#define NVIC_INIT_ITNS10   0
-
-/*
-// Interrupts 64..95
-//   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 323 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 324 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 325 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 326 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 327 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 328 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 329 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS10_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 11 (Interrupts 352..383)
-*/
-#define NVIC_INIT_ITNS11   0
-
-/*
-// Interrupts 96..127
-//   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 355 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 356 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 357 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 358 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 359 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 360 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 361 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS11_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 12 (Interrupts 384..415)
-*/
-#define NVIC_INIT_ITNS12   0
-
-/*
-// Interrupts 128..159
-//   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 387 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 388 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 389 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 390 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 391 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 392 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 393 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS12_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 13 (Interrupts 416..447)
-*/
-#define NVIC_INIT_ITNS13   0
-
-/*
-// Interrupts 160..191
-//   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 419 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 420 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 421 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 422 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 423 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 424 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 425 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS13_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 14 (Interrupts 448..479)
-*/
-#define NVIC_INIT_ITNS14   0
-
-/*
-// Interrupts 192..223
-//   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 451 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 452 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 453 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 454 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 455 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 456 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 457 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS14_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 15 (Interrupts 480..511)
-*/
-#define NVIC_INIT_ITNS15   0
-
-/*
-// Interrupts 224..255
-//   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 483 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 484 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 485 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 486 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 487 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 488 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 489 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS15_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
 /*
 // </h>
 */
@@ -1193,38 +825,6 @@ __STATIC_INLINE void TZ_SAU_Setup (void)
     NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;
   #endif
 
-  #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)
-    NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)
-    NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)
-    NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)
-    NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)
-    NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)
-    NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)
-    NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)
-    NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;
-  #endif
-
   /* repeat this for all possible ITNS elements */
 
 }

CMSIS/CoreValidation/Tests/Cortex-M23NS/GCC/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
- * @file     startup_ARMCM23.s
+ * @file     startup_ARMCM23.c
  * @brief    CMSIS Core Device Startup File for
- *           ARMCM23 Device Series
- * @version  V5.00
- * @date     21. October 2016
+ *           ARMCM23 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -23,6 +23,10 @@
  * limitations under the License.
  */
 
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
 #include <stdint.h>
 
 
@@ -39,6 +43,7 @@ extern uint32_t __zero_table_end__;
 extern uint32_t __bss_start__;
 extern uint32_t __bss_end__;
 extern uint32_t __StackTop;
+extern uint32_t __StackLimit;
 
 /*----------------------------------------------------------------------------
   Exception / Interrupt Handler Function Prototype
@@ -49,35 +54,30 @@ typedef void( *pFunc )( void );
 /*----------------------------------------------------------------------------
   External References
  *----------------------------------------------------------------------------*/
-#ifndef __START
-extern void  _start(void) __attribute__((noreturn));    /* PreeMain (C library entry point) */
-#else
-extern int  __START(void) __attribute__((noreturn));    /* main entry point */
-#endif
-
-#ifndef __NO_SYSTEM_INIT
-extern void SystemInit (void);            /* CMSIS System Initialization      */
-#endif
+extern void _start     (void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
+extern void SystemInit (void);                           /* CMSIS System Initialization */
 
 
 /*----------------------------------------------------------------------------
   Internal References
  *----------------------------------------------------------------------------*/
-void Default_Handler(void);                          /* Default empty handler */
-void Reset_Handler(void);                            /* Reset Handler */
+void Default_Handler(void) __attribute__ ((noreturn));
+void Reset_Handler  (void) __attribute__ ((noreturn));
 
 
 /*----------------------------------------------------------------------------
   User Initial Stack & Heap
  *----------------------------------------------------------------------------*/
-#ifndef __STACK_SIZE
-  #define	__STACK_SIZE  0x00000400
-#endif
+//<h> Stack Configuration
+//  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//</h>
+#define  __STACK_SIZE  0x00000400
 static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack")));
 
-#ifndef __HEAP_SIZE
-  #define	__HEAP_SIZE   0x00000C00
-#endif
+//<h> Heap Configuration
+//  <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//</h>
+#define  __HEAP_SIZE   0x00000C00
 #if __HEAP_SIZE > 0
 static uint8_t heap[__HEAP_SIZE]   __attribute__ ((aligned(8), used, section(".heap")));
 #endif
@@ -86,94 +86,59 @@ static uint8_t heap[__HEAP_SIZE]   __attribute__ ((aligned(8), used, section(".h
 /*----------------------------------------------------------------------------
   Exception / Interrupt Handler
  *----------------------------------------------------------------------------*/
-/* ARMCM23 Processor Exceptions */
-void NMI_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
-void HardFault_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
-void SVC_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
-void PendSV_Handler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void SysTick_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
-
-/* ARMCM23 Specific Interrupts */
-void WDT_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void RTC_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM0_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM2_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIA_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIB_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART0_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART1_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART2_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART4_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void AACI_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void CLCD_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void ENET_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBDC_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBHC_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void CHLCD_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void FLEXRAY_IRQHandler  (void) __attribute__ ((weak, alias("Default_Handler")));
-void CAN_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void LIN_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void I2C_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void CPU_CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART3_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void SPI_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+/* Exceptions */
+void NMI_Handler            (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler            (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler        (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
 
 
 /*----------------------------------------------------------------------------
   Exception / Interrupt Vector table
  *----------------------------------------------------------------------------*/
-const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = {
-  /* ARMCM23 Exceptions Handler */
-  (pFunc)((uint32_t)&__StackTop),           /*      Initial Stack Pointer     */
-  Reset_Handler,                            /*      Reset Handler             */
-  NMI_Handler,                              /*      NMI Handler               */
-  HardFault_Handler,                        /*      Hard Fault Handler        */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  SVC_Handler,                              /*      SVCall Handler            */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  PendSV_Handler,                           /*      PendSV Handler            */
-  SysTick_Handler,                          /*      SysTick Handler           */
-
-  /* External interrupts */
-  WDT_IRQHandler,                           /*  0:  Watchdog Timer            */
-  RTC_IRQHandler,                           /*  1:  Real Time Clock           */
-  TIM0_IRQHandler,                          /*  2:  Timer0 / Timer1           */
-  TIM2_IRQHandler,                          /*  3:  Timer2 / Timer3           */
-  MCIA_IRQHandler,                          /*  4:  MCIa                      */
-  MCIB_IRQHandler,                          /*  5:  MCIb                      */
-  UART0_IRQHandler,                         /*  6:  UART0 - DUT FPGA          */
-  UART1_IRQHandler,                         /*  7:  UART1 - DUT FPGA          */
-  UART2_IRQHandler,                         /*  8:  UART2 - DUT FPGA          */
-  UART4_IRQHandler,                         /*  9:  UART4 - not connected     */
-  AACI_IRQHandler,                          /* 10: AACI / AC97                */
-  CLCD_IRQHandler,                          /* 11: CLCD Combined Interrupt    */
-  ENET_IRQHandler,                          /* 12: Ethernet                   */
-  USBDC_IRQHandler,                         /* 13: USB Device                 */
-  USBHC_IRQHandler,                         /* 14: USB Host Controller        */
-  CHLCD_IRQHandler,                         /* 15: Character LCD              */
-  FLEXRAY_IRQHandler,                       /* 16: Flexray                    */
-  CAN_IRQHandler,                           /* 17: CAN                        */
-  LIN_IRQHandler,                           /* 18: LIN                        */
-  I2C_IRQHandler,                           /* 19: I2C ADC/DAC                */
-  0,                                        /* 20: Reserved                   */
-  0,                                        /* 21: Reserved                   */
-  0,                                        /* 22: Reserved                   */
-  0,                                        /* 23: Reserved                   */
-  0,                                        /* 24: Reserved                   */
-  0,                                        /* 25: Reserved                   */
-  0,                                        /* 26: Reserved                   */
-  0,                                        /* 27: Reserved                   */
-  CPU_CLCD_IRQHandler,                      /* 28: Reserved - CPU FPGA CLCD   */
-  0,                                        /* 29: Reserved - CPU FPGA        */
-  UART3_IRQHandler,                         /* 30: UART3    - CPU FPGA        */
-  SPI_IRQHandler                            /* 31: SPI Touchscreen - CPU FPGA */
+extern const pFunc __Vectors[240];
+       const pFunc __Vectors[240] __attribute__ ((section(".vectors"))) = {
+  (pFunc)(&__StackTop),                     /*     Initial Stack Pointer */
+  Reset_Handler,                            /*     Reset Handler */
+  NMI_Handler,                              /* -14 NMI Handler */
+  HardFault_Handler,                        /* -13 Hard Fault Handler */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  SVC_Handler,                              /*  -5 SVCall Handler */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  PendSV_Handler,                           /*  -2 PendSV Handler */
+  SysTick_Handler,                          /*  -1 SysTick Handler */
+
+  /* Interrupts */
+  Interrupt0_Handler,                       /*   0 Interrupt 0 */
+  Interrupt1_Handler,                       /*   1 Interrupt 1 */
+  Interrupt2_Handler,                       /*   2 Interrupt 2 */
+  Interrupt3_Handler,                       /*   3 Interrupt 3 */
+  Interrupt4_Handler,                       /*   4 Interrupt 4 */
+  Interrupt5_Handler,                       /*   5 Interrupt 5 */
+  Interrupt6_Handler,                       /*   6 Interrupt 6 */
+  Interrupt7_Handler,                       /*   7 Interrupt 7 */
+  Interrupt8_Handler,                       /*   8 Interrupt 8 */
+  Interrupt9_Handler                        /*   9 Interrupt 9 */
+                                            /* Interrupts 10 .. 224 are left out */
 };
 
 
@@ -184,41 +149,42 @@ void Reset_Handler(void) {
   uint32_t *pSrc, *pDest;
   uint32_t *pTable __attribute__((unused));
 
-/*  Firstly it copies data from read only memory to RAM. There are two schemes
- *  to copy. One can copy more than one sections. Another can only copy
- *  one section.  The former scheme needs more instructions and read-only
- *  data to implement than the latter.
- *  Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.  */
+/* Firstly it copies data from read only memory to RAM.
+ * There are two schemes to copy. One can copy more than one sections.
+ * Another can copy only one section. The former scheme needs more
+ * instructions and read-only data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.
+ */
 
 #ifdef __STARTUP_COPY_MULTIPLE
-/*  Multiple sections scheme.
+/* Multiple sections scheme.
  *
- *  Between symbol address __copy_table_start__ and __copy_table_end__,
- *  there are array of triplets, each of which specify:
- *    offset 0: LMA of start of a section to copy from
- *    offset 4: VMA of start of a section to copy to
- *    offset 8: size of the section to copy. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ *   offset 0: LMA of start of a section to copy from
+ *   offset 4: VMA of start of a section to copy to
+ *   offset 8: size of the section to copy. Must be multiply of 4
  *
- *  All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
  */
   pTable = &__copy_table_start__;
 
   for (; pTable < &__copy_table_end__; pTable = pTable + 3) {
-		pSrc  = (uint32_t*)*(pTable + 0);
-		pDest = (uint32_t*)*(pTable + 1);
-		for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
+    pSrc  = (uint32_t*)*(pTable + 0);
+    pDest = (uint32_t*)*(pTable + 1);
+    for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
       *pDest++ = *pSrc++;
-		}
-	}
+    }
+  }
 #else
-/*  Single section scheme.
+/* Single section scheme.
  *
- *  The ranges of copy from/to are specified by following symbols
- *    __etext: LMA of start of the section to copy from. Usually end of text
- *    __data_start__: VMA of start of the section to copy to
- *    __data_end__: VMA of end of the section to copy to
+ * The ranges of copy from/to are specified by following symbols
+ *   __etext: LMA of start of the section to copy from. Usually end of text
+ *   __data_start__: VMA of start of the section to copy to
+ *   __data_end__: VMA of end of the section to copy to
  *
- *  All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
  */
   pSrc  = &__etext;
   pDest = &__data_start__;
@@ -228,40 +194,40 @@ void Reset_Handler(void) {
   }
 #endif /*__STARTUP_COPY_MULTIPLE */
 
-/*  This part of work usually is done in C library startup code. Otherwise,
- *  define this macro to enable it in this startup.
+/* This part of work usually is done in C library startup code.
+ * Otherwise, define this macro to enable it in this startup.
  *
- *  There are two schemes too. One can clear multiple BSS sections. Another
- *  can only clear one section. The former is more size expensive than the
- *  latter.
+ * There are two schemes too.
+ * One can clear multiple BSS sections. Another can only clear one section.
+ * The former is more size expensive than the latter.
  *
- *  Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- *  Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
  */
 #ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/*  Multiple sections scheme.
+/* Multiple sections scheme.
  *
- *  Between symbol address __copy_table_start__ and __copy_table_end__,
- *  there are array of tuples specifying:
- *    offset 0: Start of a BSS section
- *    offset 4: Size of this BSS section. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ *   offset 0: Start of a BSS section
+ *   offset 4: Size of this BSS section. Must be multiply of 4
  */
   pTable = &__zero_table_start__;
 
   for (; pTable < &__zero_table_end__; pTable = pTable + 2) {
-		pDest = (uint32_t*)*(pTable + 0);
-		for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
+    pDest = (uint32_t*)*(pTable + 0);
+    for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
       *pDest++ = 0;
-		}
-	}
+    }
+  }
 #elif defined (__STARTUP_CLEAR_BSS)
-/*  Single BSS section scheme.
+/* Single BSS section scheme.
  *
- *  The BSS section is specified by following symbols
- *    __bss_start__: start of the BSS section.
- *    __bss_end__: end of the BSS section.
+ * The BSS section is specified by following symbols
+ *   __bss_start__: start of the BSS section.
+ *   __bss_end__: end of the BSS section.
  *
- *  Both addresses must be aligned to 4 bytes boundary.
+ * Both addresses must be aligned to 4 bytes boundary.
  */
   pDest = &__bss_start__;
 
@@ -270,15 +236,10 @@ void Reset_Handler(void) {
   }
 #endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
 
-#ifndef __NO_SYSTEM_INIT
-	SystemInit();
-#endif
-
-#ifndef __START
-#define __START _start
-#endif
-	__START();
+  __set_MSPLIM((uint32_t)&__StackLimit);
 
+  SystemInit();                             /* CMSIS System Initialization */
+  _start();                                 /* Enter PreeMain (C library entry point) */
 }
 
 
@@ -287,5 +248,5 @@ void Reset_Handler(void) {
  *----------------------------------------------------------------------------*/
 void Default_Handler(void) {
 
-	while(1);
+  while(1);
 }

CMSIS/CoreValidation/Tests/Cortex-M23NS/GCC/RTE/Device/ARMCM23_TZ/system_ARMCM23.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
  * @file     system_ARMCM23.c
  * @brief    CMSIS Device System Source File for
- *           ARMCM23 Device Series
- * @version  V5.00
- * @date     21. October 2016
+ *           ARMCM23 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -38,9 +38,9 @@
 /*----------------------------------------------------------------------------
   Define clocks
  *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+#define  XTAL            (50000000UL)     /* Oscillator frequency */
 
-#define  SYSTEM_CLOCK    (5U * XTAL)
+#define  SYSTEM_CLOCK    (XTAL / 2U)
 
 
 /*----------------------------------------------------------------------------
@@ -53,7 +53,7 @@
 /*----------------------------------------------------------------------------
   System Core Clock Variable
  *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */
 
 
 /*----------------------------------------------------------------------------

CMSIS/CoreValidation/Tests/Cortex-M23NS/IAR/Bootloader/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     partition_ARMCM23.h
  * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM23
- * @version  V5.00
- * @date     28. October 2016
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -707,374 +707,6 @@
 //   </e>
 */
 
-/*
-//   <e>Initialize ITNS 8 (Interrupts 256..287)
-*/
-#define NVIC_INIT_ITNS8    0
-
-/*
-// Interrupts 0..31
-//   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 259 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 260 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 261 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 262 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 263 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 264 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 265 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS8_VAL      0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 9 (Interrupts 288..319)
-*/
-#define NVIC_INIT_ITNS9    0
-
-/*
-// Interrupts 32..63
-//   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 291 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 292 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 293 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 294 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 295 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 296 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 297 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS9_VAL      0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 10 (Interrupts 320..351)
-*/
-#define NVIC_INIT_ITNS10   0
-
-/*
-// Interrupts 64..95
-//   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 323 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 324 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 325 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 326 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 327 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 328 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 329 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS10_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 11 (Interrupts 352..383)
-*/
-#define NVIC_INIT_ITNS11   0
-
-/*
-// Interrupts 96..127
-//   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 355 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 356 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 357 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 358 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 359 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 360 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 361 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS11_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 12 (Interrupts 384..415)
-*/
-#define NVIC_INIT_ITNS12   0
-
-/*
-// Interrupts 128..159
-//   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 387 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 388 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 389 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 390 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 391 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 392 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 393 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS12_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 13 (Interrupts 416..447)
-*/
-#define NVIC_INIT_ITNS13   0
-
-/*
-// Interrupts 160..191
-//   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 419 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 420 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 421 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 422 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 423 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 424 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 425 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS13_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 14 (Interrupts 448..479)
-*/
-#define NVIC_INIT_ITNS14   0
-
-/*
-// Interrupts 192..223
-//   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 451 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 452 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 453 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 454 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 455 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 456 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 457 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS14_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 15 (Interrupts 480..511)
-*/
-#define NVIC_INIT_ITNS15   0
-
-/*
-// Interrupts 224..255
-//   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 483 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 484 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 485 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 486 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 487 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 488 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 489 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS15_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
 /*
 // </h>
 */
@@ -1193,38 +825,6 @@ __STATIC_INLINE void TZ_SAU_Setup (void)
     NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;
   #endif
 
-  #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)
-    NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)
-    NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)
-    NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)
-    NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)
-    NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)
-    NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)
-    NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)
-    NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;
-  #endif
-
   /* repeat this for all possible ITNS elements */
 
 }

CMSIS/CoreValidation/Tests/Cortex-M23NS/IAR/Bootloader/RTE/Device/ARMCM23_TZ/startup_ARMCM23.s

@@ -1,12 +1,12 @@
 ;/**************************************************************************//**
 ; * @file     startup_ARMCM23.s
 ; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM23 Device Series
-; * @version  V5.00
-; * @date     21. October 2016
+; *           ARMCM23 Device
+; * @version  V5.3.1
+; * @date     09. July 2018
 ; ******************************************************************************/
 ;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
 ; *
 ; * SPDX-License-Identifier: Apache-2.0
 ; *
@@ -39,234 +39,109 @@
 ; Cortex-M version
 ;
 
-        MODULE  ?cstartup
+                MODULE   ?cstartup
 
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
+                ;; Forward declaration of sections.
+                SECTION  CSTACK:DATA:NOROOT(3)
 
-        SECTION .intvec:CODE:NOROOT(2)
+                SECTION  .intvec:CODE:NOROOT(2)
 
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit
-        PUBLIC  __vector_table
-        PUBLIC  __vector_table_0x1c
-        PUBLIC  __Vectors
-        PUBLIC  __Vectors_End
-        PUBLIC  __Vectors_Size
+                EXTERN   __iar_program_start
+                EXTERN   SystemInit
+                PUBLIC   __vector_table
+                PUBLIC   __vector_table_0x1c
+                PUBLIC   __Vectors
+                PUBLIC   __Vectors_End
+                PUBLIC   __Vectors_Size
 
-        DATA
+                DATA
 
 __vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler
-
-        DCD     NMI_Handler
-        DCD     HardFault_Handler
-        DCD     0
-        DCD     0
-        DCD     0
+                DCD      sfe(CSTACK)                         ;     Top of Stack
+                DCD      Reset_Handler                       ;     Reset Handler
+                DCD      NMI_Handler                         ; -14 NMI Handler
+                DCD      HardFault_Handler                   ; -13 Hard Fault Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
 __vector_table_0x1c
-        DCD     0
-        DCD     0
-        DCD     0
-        DCD     0
-        DCD     SVC_Handler
-        DCD     0
-        DCD     0
-        DCD     PendSV_Handler
-        DCD     SysTick_Handler
-
-        ; External Interrupts
-        DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
-        DCD     RTC_IRQHandler            ;  1:  Real Time Clock
-        DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
-        DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
-        DCD     MCIA_IRQHandler           ;  4:  MCIa
-        DCD     MCIB_IRQHandler           ;  5:  MCIb
-        DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
-        DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
-        DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
-        DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
-        DCD     AACI_IRQHandler           ; 10: AACI / AC97
-        DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
-        DCD     ENET_IRQHandler           ; 12: Ethernet
-        DCD     USBDC_IRQHandler          ; 13: USB Device
-        DCD     USBHC_IRQHandler          ; 14: USB Host Controller
-        DCD     CHLCD_IRQHandler          ; 15: Character LCD
-        DCD     FLEXRAY_IRQHandler        ; 16: Flexray
-        DCD     CAN_IRQHandler            ; 17: CAN
-        DCD     LIN_IRQHandler            ; 18: LIN
-        DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
-        DCD     0                         ; 20: Reserved
-        DCD     0                         ; 21: Reserved
-        DCD     0                         ; 22: Reserved
-        DCD     0                         ; 23: Reserved
-        DCD     0                         ; 24: Reserved
-        DCD     0                         ; 25: Reserved
-        DCD     0                         ; 26: Reserved
-        DCD     0                         ; 27: Reserved
-        DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
-        DCD     0                         ; 29: Reserved - CPU FPGA
-        DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
-        DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      SVC_Handler                         ;  -5 SVCall Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      PendSV_Handler                      ;  -2 PendSV Handler
+                DCD      SysTick_Handler                     ;  -1 SysTick Handler
+
+                ; Interrupts
+                DCD      Interrupt0_Handler                  ;   0 Interrupt 0
+                DCD      Interrupt1_Handler                  ;   1 Interrupt 1
+                DCD      Interrupt2_Handler                  ;   2 Interrupt 2
+                DCD      Interrupt3_Handler                  ;   3 Interrupt 3
+                DCD      Interrupt4_Handler                  ;   4 Interrupt 4
+                DCD      Interrupt5_Handler                  ;   5 Interrupt 5
+                DCD      Interrupt6_Handler                  ;   6 Interrupt 6
+                DCD      Interrupt7_Handler                  ;   7 Interrupt 7
+                DCD      Interrupt8_Handler                  ;   8 Interrupt 8
+                DCD      Interrupt9_Handler                  ;   9 Interrupt 9
+
+                DS32    (214)                                ; Interrupts 10 .. 224 are left out
 __Vectors_End
 
-__Vectors       EQU   __vector_table
-__Vectors_Size  EQU   __Vectors_End - __Vectors
+__Vectors       EQU      __vector_table
+__Vectors_Size  EQU      __Vectors_End - __Vectors
 
 
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
+                THUMB
 
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
+; Reset Handler
 
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
+                PUBWEAK  Reset_Handler
+                SECTION  .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+                LDR      R0, =SystemInit
+                BLX      R0
+                LDR      R0, =__iar_program_start
+                BX       R0
+
+
+                PUBWEAK NMI_Handler
+                PUBWEAK HardFault_Handler
+                PUBWEAK SVC_Handler
+                PUBWEAK PendSV_Handler
+                PUBWEAK SysTick_Handler
+
+                PUBWEAK Interrupt0_Handler
+                PUBWEAK Interrupt1_Handler
+                PUBWEAK Interrupt2_Handler
+                PUBWEAK Interrupt3_Handler
+                PUBWEAK Interrupt4_Handler
+                PUBWEAK Interrupt5_Handler
+                PUBWEAK Interrupt6_Handler
+                PUBWEAK Interrupt7_Handler
+                PUBWEAK Interrupt8_Handler
+                PUBWEAK Interrupt9_Handler
+                SECTION .text:CODE:REORDER:NOROOT(1)
 NMI_Handler
-        B NMI_Handler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 HardFault_Handler
-        B HardFault_Handler
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 SVC_Handler
-        B SVC_Handler
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 SysTick_Handler
-        B SysTick_Handler
-
-        PUBWEAK WDT_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WDT_IRQHandler
-        B WDT_IRQHandler
-
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-
-        PUBWEAK TIM0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM0_IRQHandler
-        B TIM0_IRQHandler
-
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-
-        PUBWEAK MCIA_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MCIA_IRQHandler
-        B MCIA_IRQHandler
-
-        PUBWEAK MCIB_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MCIB_IRQHandler
-        B MCIB_IRQHandler
-
-        PUBWEAK UART0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART0_IRQHandler
-        B UART0_IRQHandler
-
-        PUBWEAK UART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART1_IRQHandler
-        B UART1_IRQHandler
-
-        PUBWEAK UART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART2_IRQHandler
-        B UART2_IRQHandler
-
-        PUBWEAK UART4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
-        B UART4_IRQHandler
-
-        PUBWEAK AACI_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-AACI_IRQHandler
-        B AACI_IRQHandler
-
-        PUBWEAK CLCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CLCD_IRQHandler
-        B CLCD_IRQHandler
-
-        PUBWEAK ENET_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ENET_IRQHandler
-        B ENET_IRQHandler
-
-        PUBWEAK USBDC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USBDC_IRQHandler
-        B USBDC_IRQHandler
-
-        PUBWEAK USBHC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USBHC_IRQHandler
-        B USBHC_IRQHandler
-
-        PUBWEAK CHLCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CHLCD_IRQHandler
-        B CHLCD_IRQHandler
-
-        PUBWEAK FLEXRAY_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLEXRAY_IRQHandler
-        B FLEXRAY_IRQHandler
-
-        PUBWEAK CAN_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN_IRQHandler
-        B CAN_IRQHandler
-
-        PUBWEAK LIN_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-LIN_IRQHandler
-        B LIN_IRQHandler
-
-        PUBWEAK I2C_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C_IRQHandler
-        B I2C_IRQHandler
-
-        PUBWEAK CPU_CLCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CPU_CLCD_IRQHandler
-        B CPU_CLCD_IRQHandler
-
-        PUBWEAK UART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART3_IRQHandler
-        B UART3_IRQHandler
-
-        PUBWEAK SPI_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI_IRQHandler
-        B SPI_IRQHandler
 
-        END
+Interrupt0_Handler
+Interrupt1_Handler
+Interrupt2_Handler
+Interrupt3_Handler
+Interrupt4_Handler
+Interrupt5_Handler
+Interrupt6_Handler
+Interrupt7_Handler
+Interrupt8_Handler
+Interrupt9_Handler
+Default_Handler
+                B        .
+
+
+                END

CMSIS/CoreValidation/Tests/Cortex-M23NS/IAR/Bootloader/RTE/Device/ARMCM23_TZ/system_ARMCM23.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
  * @file     system_ARMCM23.c
  * @brief    CMSIS Device System Source File for
- *           ARMCM23 Device Series
- * @version  V5.00
- * @date     21. October 2016
+ *           ARMCM23 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -38,9 +38,9 @@
 /*----------------------------------------------------------------------------
   Define clocks
  *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+#define  XTAL            (50000000UL)     /* Oscillator frequency */
 
-#define  SYSTEM_CLOCK    (5U * XTAL)
+#define  SYSTEM_CLOCK    (XTAL / 2U)
 
 
 /*----------------------------------------------------------------------------
@@ -53,7 +53,7 @@
 /*----------------------------------------------------------------------------
   System Core Clock Variable
  *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */
 
 
 /*----------------------------------------------------------------------------

CMSIS/CoreValidation/Tests/Cortex-M23NS/IAR/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     partition_ARMCM23.h
  * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM23
- * @version  V5.00
- * @date     28. October 2016
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -707,374 +707,6 @@
 //   </e>
 */
 
-/*
-//   <e>Initialize ITNS 8 (Interrupts 256..287)
-*/
-#define NVIC_INIT_ITNS8    0
-
-/*
-// Interrupts 0..31
-//   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 259 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 260 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 261 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 262 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 263 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 264 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 265 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS8_VAL      0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 9 (Interrupts 288..319)
-*/
-#define NVIC_INIT_ITNS9    0
-
-/*
-// Interrupts 32..63
-//   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 291 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 292 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 293 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 294 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 295 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 296 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 297 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS9_VAL      0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 10 (Interrupts 320..351)
-*/
-#define NVIC_INIT_ITNS10   0
-
-/*
-// Interrupts 64..95
-//   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 323 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 324 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 325 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 326 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 327 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 328 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 329 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS10_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 11 (Interrupts 352..383)
-*/
-#define NVIC_INIT_ITNS11   0
-
-/*
-// Interrupts 96..127
-//   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 355 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 356 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 357 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 358 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 359 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 360 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 361 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS11_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 12 (Interrupts 384..415)
-*/
-#define NVIC_INIT_ITNS12   0
-
-/*
-// Interrupts 128..159
-//   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 387 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 388 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 389 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 390 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 391 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 392 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 393 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS12_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 13 (Interrupts 416..447)
-*/
-#define NVIC_INIT_ITNS13   0
-
-/*
-// Interrupts 160..191
-//   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 419 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 420 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 421 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 422 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 423 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 424 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 425 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS13_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 14 (Interrupts 448..479)
-*/
-#define NVIC_INIT_ITNS14   0
-
-/*
-// Interrupts 192..223
-//   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 451 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 452 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 453 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 454 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 455 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 456 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 457 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS14_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 15 (Interrupts 480..511)
-*/
-#define NVIC_INIT_ITNS15   0
-
-/*
-// Interrupts 224..255
-//   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 483 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 484 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 485 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 486 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 487 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 488 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 489 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS15_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
 /*
 // </h>
 */
@@ -1193,38 +825,6 @@ __STATIC_INLINE void TZ_SAU_Setup (void)
     NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;
   #endif
 
-  #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)
-    NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)
-    NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)
-    NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)
-    NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)
-    NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)
-    NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)
-    NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)
-    NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;
-  #endif
-
   /* repeat this for all possible ITNS elements */
 
 }

CMSIS/CoreValidation/Tests/Cortex-M23NS/IAR/RTE/Device/ARMCM23_TZ/startup_ARMCM23.s

@@ -1,12 +1,12 @@
 ;/**************************************************************************//**
 ; * @file     startup_ARMCM23.s
 ; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM23 Device Series
-; * @version  V5.00
-; * @date     21. October 2016
+; *           ARMCM23 Device
+; * @version  V5.3.1
+; * @date     09. July 2018
 ; ******************************************************************************/
 ;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
 ; *
 ; * SPDX-License-Identifier: Apache-2.0
 ; *
@@ -39,234 +39,109 @@
 ; Cortex-M version
 ;
 
-        MODULE  ?cstartup
+                MODULE   ?cstartup
 
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
+                ;; Forward declaration of sections.
+                SECTION  CSTACK:DATA:NOROOT(3)
 
-        SECTION .intvec:CODE:NOROOT(2)
+                SECTION  .intvec:CODE:NOROOT(2)
 
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit
-        PUBLIC  __vector_table
-        PUBLIC  __vector_table_0x1c
-        PUBLIC  __Vectors
-        PUBLIC  __Vectors_End
-        PUBLIC  __Vectors_Size
+                EXTERN   __iar_program_start
+                EXTERN   SystemInit
+                PUBLIC   __vector_table
+                PUBLIC   __vector_table_0x1c
+                PUBLIC   __Vectors
+                PUBLIC   __Vectors_End
+                PUBLIC   __Vectors_Size
 
-        DATA
+                DATA
 
 __vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler
-
-        DCD     NMI_Handler
-        DCD     HardFault_Handler
-        DCD     0
-        DCD     0
-        DCD     0
+                DCD      sfe(CSTACK)                         ;     Top of Stack
+                DCD      Reset_Handler                       ;     Reset Handler
+                DCD      NMI_Handler                         ; -14 NMI Handler
+                DCD      HardFault_Handler                   ; -13 Hard Fault Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
 __vector_table_0x1c
-        DCD     0
-        DCD     0
-        DCD     0
-        DCD     0
-        DCD     SVC_Handler
-        DCD     0
-        DCD     0
-        DCD     PendSV_Handler
-        DCD     SysTick_Handler
-
-        ; External Interrupts
-        DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
-        DCD     RTC_IRQHandler            ;  1:  Real Time Clock
-        DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
-        DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
-        DCD     MCIA_IRQHandler           ;  4:  MCIa
-        DCD     MCIB_IRQHandler           ;  5:  MCIb
-        DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
-        DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
-        DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
-        DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
-        DCD     AACI_IRQHandler           ; 10: AACI / AC97
-        DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
-        DCD     ENET_IRQHandler           ; 12: Ethernet
-        DCD     USBDC_IRQHandler          ; 13: USB Device
-        DCD     USBHC_IRQHandler          ; 14: USB Host Controller
-        DCD     CHLCD_IRQHandler          ; 15: Character LCD
-        DCD     FLEXRAY_IRQHandler        ; 16: Flexray
-        DCD     CAN_IRQHandler            ; 17: CAN
-        DCD     LIN_IRQHandler            ; 18: LIN
-        DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
-        DCD     0                         ; 20: Reserved
-        DCD     0                         ; 21: Reserved
-        DCD     0                         ; 22: Reserved
-        DCD     0                         ; 23: Reserved
-        DCD     0                         ; 24: Reserved
-        DCD     0                         ; 25: Reserved
-        DCD     0                         ; 26: Reserved
-        DCD     0                         ; 27: Reserved
-        DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
-        DCD     0                         ; 29: Reserved - CPU FPGA
-        DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
-        DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      SVC_Handler                         ;  -5 SVCall Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      PendSV_Handler                      ;  -2 PendSV Handler
+                DCD      SysTick_Handler                     ;  -1 SysTick Handler
+
+                ; Interrupts
+                DCD      Interrupt0_Handler                  ;   0 Interrupt 0
+                DCD      Interrupt1_Handler                  ;   1 Interrupt 1
+                DCD      Interrupt2_Handler                  ;   2 Interrupt 2
+                DCD      Interrupt3_Handler                  ;   3 Interrupt 3
+                DCD      Interrupt4_Handler                  ;   4 Interrupt 4
+                DCD      Interrupt5_Handler                  ;   5 Interrupt 5
+                DCD      Interrupt6_Handler                  ;   6 Interrupt 6
+                DCD      Interrupt7_Handler                  ;   7 Interrupt 7
+                DCD      Interrupt8_Handler                  ;   8 Interrupt 8
+                DCD      Interrupt9_Handler                  ;   9 Interrupt 9
+
+                DS32    (214)                                ; Interrupts 10 .. 224 are left out
 __Vectors_End
 
-__Vectors       EQU   __vector_table
-__Vectors_Size  EQU   __Vectors_End - __Vectors
+__Vectors       EQU      __vector_table
+__Vectors_Size  EQU      __Vectors_End - __Vectors
 
 
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
+                THUMB
 
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
+; Reset Handler
 
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
+                PUBWEAK  Reset_Handler
+                SECTION  .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+                LDR      R0, =SystemInit
+                BLX      R0
+                LDR      R0, =__iar_program_start
+                BX       R0
+
+
+                PUBWEAK NMI_Handler
+                PUBWEAK HardFault_Handler
+                PUBWEAK SVC_Handler
+                PUBWEAK PendSV_Handler
+                PUBWEAK SysTick_Handler
+
+                PUBWEAK Interrupt0_Handler
+                PUBWEAK Interrupt1_Handler
+                PUBWEAK Interrupt2_Handler
+                PUBWEAK Interrupt3_Handler
+                PUBWEAK Interrupt4_Handler
+                PUBWEAK Interrupt5_Handler
+                PUBWEAK Interrupt6_Handler
+                PUBWEAK Interrupt7_Handler
+                PUBWEAK Interrupt8_Handler
+                PUBWEAK Interrupt9_Handler
+                SECTION .text:CODE:REORDER:NOROOT(1)
 NMI_Handler
-        B NMI_Handler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 HardFault_Handler
-        B HardFault_Handler
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 SVC_Handler
-        B SVC_Handler
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 SysTick_Handler
-        B SysTick_Handler
-
-        PUBWEAK WDT_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WDT_IRQHandler
-        B WDT_IRQHandler
-
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-
-        PUBWEAK TIM0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM0_IRQHandler
-        B TIM0_IRQHandler
-
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-
-        PUBWEAK MCIA_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MCIA_IRQHandler
-        B MCIA_IRQHandler
-
-        PUBWEAK MCIB_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MCIB_IRQHandler
-        B MCIB_IRQHandler
-
-        PUBWEAK UART0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART0_IRQHandler
-        B UART0_IRQHandler
-
-        PUBWEAK UART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART1_IRQHandler
-        B UART1_IRQHandler
-
-        PUBWEAK UART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART2_IRQHandler
-        B UART2_IRQHandler
-
-        PUBWEAK UART4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
-        B UART4_IRQHandler
-
-        PUBWEAK AACI_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-AACI_IRQHandler
-        B AACI_IRQHandler
-
-        PUBWEAK CLCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CLCD_IRQHandler
-        B CLCD_IRQHandler
-
-        PUBWEAK ENET_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ENET_IRQHandler
-        B ENET_IRQHandler
-
-        PUBWEAK USBDC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USBDC_IRQHandler
-        B USBDC_IRQHandler
-
-        PUBWEAK USBHC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USBHC_IRQHandler
-        B USBHC_IRQHandler
-
-        PUBWEAK CHLCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CHLCD_IRQHandler
-        B CHLCD_IRQHandler
-
-        PUBWEAK FLEXRAY_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLEXRAY_IRQHandler
-        B FLEXRAY_IRQHandler
-
-        PUBWEAK CAN_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN_IRQHandler
-        B CAN_IRQHandler
-
-        PUBWEAK LIN_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-LIN_IRQHandler
-        B LIN_IRQHandler
-
-        PUBWEAK I2C_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C_IRQHandler
-        B I2C_IRQHandler
-
-        PUBWEAK CPU_CLCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CPU_CLCD_IRQHandler
-        B CPU_CLCD_IRQHandler
-
-        PUBWEAK UART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART3_IRQHandler
-        B UART3_IRQHandler
-
-        PUBWEAK SPI_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI_IRQHandler
-        B SPI_IRQHandler
 
-        END
+Interrupt0_Handler
+Interrupt1_Handler
+Interrupt2_Handler
+Interrupt3_Handler
+Interrupt4_Handler
+Interrupt5_Handler
+Interrupt6_Handler
+Interrupt7_Handler
+Interrupt8_Handler
+Interrupt9_Handler
+Default_Handler
+                B        .
+
+
+                END

CMSIS/CoreValidation/Tests/Cortex-M23NS/IAR/RTE/Device/ARMCM23_TZ/system_ARMCM23.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
  * @file     system_ARMCM23.c
  * @brief    CMSIS Device System Source File for
- *           ARMCM23 Device Series
- * @version  V5.00
- * @date     21. October 2016
+ *           ARMCM23 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -38,9 +38,9 @@
 /*----------------------------------------------------------------------------
   Define clocks
  *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+#define  XTAL            (50000000UL)     /* Oscillator frequency */
 
-#define  SYSTEM_CLOCK    (5U * XTAL)
+#define  SYSTEM_CLOCK    (XTAL / 2U)
 
 
 /*----------------------------------------------------------------------------
@@ -53,7 +53,7 @@
 /*----------------------------------------------------------------------------
   System Core Clock Variable
  *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */
 
 
 /*----------------------------------------------------------------------------

CMSIS/CoreValidation/Tests/Cortex-M23S/AC6/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     partition_ARMCM23.h
  * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM23
- * @version  V5.00
- * @date     28. October 2016
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -707,374 +707,6 @@
 //   </e>
 */
 
-/*
-//   <e>Initialize ITNS 8 (Interrupts 256..287)
-*/
-#define NVIC_INIT_ITNS8    0
-
-/*
-// Interrupts 0..31
-//   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 259 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 260 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 261 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 262 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 263 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 264 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 265 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS8_VAL      0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 9 (Interrupts 288..319)
-*/
-#define NVIC_INIT_ITNS9    0
-
-/*
-// Interrupts 32..63
-//   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 291 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 292 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 293 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 294 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 295 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 296 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 297 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS9_VAL      0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 10 (Interrupts 320..351)
-*/
-#define NVIC_INIT_ITNS10   0
-
-/*
-// Interrupts 64..95
-//   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 323 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 324 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 325 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 326 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 327 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 328 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 329 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS10_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 11 (Interrupts 352..383)
-*/
-#define NVIC_INIT_ITNS11   0
-
-/*
-// Interrupts 96..127
-//   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 355 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 356 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 357 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 358 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 359 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 360 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 361 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS11_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 12 (Interrupts 384..415)
-*/
-#define NVIC_INIT_ITNS12   0
-
-/*
-// Interrupts 128..159
-//   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 387 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 388 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 389 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 390 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 391 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 392 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 393 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS12_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 13 (Interrupts 416..447)
-*/
-#define NVIC_INIT_ITNS13   0
-
-/*
-// Interrupts 160..191
-//   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 419 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 420 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 421 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 422 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 423 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 424 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 425 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS13_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 14 (Interrupts 448..479)
-*/
-#define NVIC_INIT_ITNS14   0
-
-/*
-// Interrupts 192..223
-//   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 451 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 452 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 453 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 454 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 455 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 456 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 457 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS14_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 15 (Interrupts 480..511)
-*/
-#define NVIC_INIT_ITNS15   0
-
-/*
-// Interrupts 224..255
-//   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 483 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 484 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 485 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 486 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 487 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 488 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 489 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS15_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
 /*
 // </h>
 */
@@ -1193,38 +825,6 @@ __STATIC_INLINE void TZ_SAU_Setup (void)
     NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;
   #endif
 
-  #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)
-    NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)
-    NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)
-    NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)
-    NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)
-    NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)
-    NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)
-    NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)
-    NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;
-  #endif
-
   /* repeat this for all possible ITNS elements */
 
 }

CMSIS/CoreValidation/Tests/Cortex-M23S/AC6/RTE/Device/ARMCM23_TZ/startup_ARMCM23.s

@@ -1,12 +1,12 @@
 ;/**************************************************************************//**
 ; * @file     startup_ARMCM23.s
 ; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM23 Device Series
-; * @version  V5.00
-; * @date     21. October 2016
+; *           ARMCM23 Device
+; * @version  V5.3.1
+; * @date     09. July 2018
 ; ******************************************************************************/
 ;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
 ; *
 ; * SPDX-License-Identifier: Apache-2.0
 ; *
@@ -23,32 +23,33 @@
 ; * limitations under the License.
 ; */
 
-;/*
 ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
 
 
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Stack Configuration
+;  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
 
-Stack_Size      EQU     0x00000400
+Stack_Size      EQU      0x00000400
 
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
+                AREA     STACK, NOINIT, READWRITE, ALIGN=3
+__stack_limit
+Stack_Mem       SPACE    Stack_Size
 __initial_sp
 
 
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Heap Configuration
+;  <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
 
-Heap_Size       EQU     0x00000C00
+Heap_Size       EQU      0x00000C00
 
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+                IF       Heap_Size != 0                      ; Heap is provided
+                AREA     HEAP, NOINIT, READWRITE, ALIGN=3
 __heap_base
-Heap_Mem        SPACE   Heap_Size
+Heap_Mem        SPACE    Heap_Size
 __heap_limit
+                ENDIF
 
 
                 PRESERVE8
@@ -57,186 +58,105 @@ __heap_limit
 
 ; Vector Table Mapped to Address 0 at Reset
 
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
-                DCD     RTC_IRQHandler            ;  1:  Real Time Clock
-                DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
-                DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
-                DCD     MCIA_IRQHandler           ;  4:  MCIa
-                DCD     MCIB_IRQHandler           ;  5:  MCIb
-                DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
-                DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
-                DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
-                DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
-                DCD     AACI_IRQHandler           ; 10: AACI / AC97
-                DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
-                DCD     ENET_IRQHandler           ; 12: Ethernet
-                DCD     USBDC_IRQHandler          ; 13: USB Device
-                DCD     USBHC_IRQHandler          ; 14: USB Host Controller
-                DCD     CHLCD_IRQHandler          ; 15: Character LCD
-                DCD     FLEXRAY_IRQHandler        ; 16: Flexray
-                DCD     CAN_IRQHandler            ; 17: CAN
-                DCD     LIN_IRQHandler            ; 18: LIN
-                DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
-                DCD     0                         ; 20: Reserved
-                DCD     0                         ; 21: Reserved
-                DCD     0                         ; 22: Reserved
-                DCD     0                         ; 23: Reserved
-                DCD     0                         ; 24: Reserved
-                DCD     0                         ; 25: Reserved
-                DCD     0                         ; 26: Reserved
-                DCD     0                         ; 27: Reserved
-                DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
-                DCD     0                         ; 29: Reserved - CPU FPGA
-                DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
-                DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
+                AREA     RESET, DATA, READONLY
+                EXPORT   __Vectors
+                EXPORT   __Vectors_End
+                EXPORT   __Vectors_Size
+
+__Vectors       DCD      __initial_sp                        ;     Top of Stack
+                DCD      Reset_Handler                       ;     Reset Handler
+                DCD      NMI_Handler                         ; -14 NMI Handler
+                DCD      HardFault_Handler                   ; -13 Hard Fault Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      SVC_Handler                         ;  -5 SVCall Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      PendSV_Handler                      ;  -2 PendSV Handler
+                DCD      SysTick_Handler                     ;  -1 SysTick Handler
+
+                ; Interrupts
+                DCD      Interrupt0_Handler                  ;   0 Interrupt 0
+                DCD      Interrupt1_Handler                  ;   1 Interrupt 1
+                DCD      Interrupt2_Handler                  ;   2 Interrupt 2
+                DCD      Interrupt3_Handler                  ;   3 Interrupt 3
+                DCD      Interrupt4_Handler                  ;   4 Interrupt 4
+                DCD      Interrupt5_Handler                  ;   5 Interrupt 5
+                DCD      Interrupt6_Handler                  ;   6 Interrupt 6
+                DCD      Interrupt7_Handler                  ;   7 Interrupt 7
+                DCD      Interrupt8_Handler                  ;   8 Interrupt 8
+                DCD      Interrupt9_Handler                  ;   9 Interrupt 9
+
+                SPACE    (214 * 4)                           ; Interrupts 10 .. 224 are left out
 __Vectors_End
+__Vectors_Size  EQU      __Vectors_End - __Vectors
 
-__Vectors_Size  EQU     __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
 
+                AREA     |.text|, CODE, READONLY
 
 ; Reset Handler
 
 Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  SystemInit
-                IMPORT  __main
-                LDR     R0, =SystemInit
-                BLX     R0
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-
+                EXPORT   Reset_Handler             [WEAK]
+                IMPORT   SystemInit
+                IMPORT   __main
 
-; Dummy Exception Handlers (infinite loops which can be modified)
+                LDR      R0, =__stack_limit
+                MSR      MSPLIM, R0                          ; Non-secure version of MSPLIM is RAZ/WI
 
-NMI_Handler     PROC
-                EXPORT  NMI_Handler               [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
+                LDR      R0, =SystemInit
+                BLX      R0
+                LDR      R0, =__main
+                BX       R0
                 ENDP
 
-Default_Handler PROC
-
-                EXPORT  WDT_IRQHandler            [WEAK]
-                EXPORT  RTC_IRQHandler            [WEAK]
-                EXPORT  TIM0_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler           [WEAK]
-                EXPORT  MCIA_IRQHandler           [WEAK]
-                EXPORT  MCIB_IRQHandler           [WEAK]
-                EXPORT  UART0_IRQHandler          [WEAK]
-                EXPORT  UART1_IRQHandler          [WEAK]
-                EXPORT  UART2_IRQHandler          [WEAK]
-                EXPORT  UART3_IRQHandler          [WEAK]
-                EXPORT  UART4_IRQHandler          [WEAK]
-                EXPORT  AACI_IRQHandler           [WEAK]
-                EXPORT  CLCD_IRQHandler           [WEAK]
-                EXPORT  ENET_IRQHandler           [WEAK]
-                EXPORT  USBDC_IRQHandler          [WEAK]
-                EXPORT  USBHC_IRQHandler          [WEAK]
-                EXPORT  CHLCD_IRQHandler          [WEAK]
-                EXPORT  FLEXRAY_IRQHandler        [WEAK]
-                EXPORT  CAN_IRQHandler            [WEAK]
-                EXPORT  LIN_IRQHandler            [WEAK]
-                EXPORT  I2C_IRQHandler            [WEAK]
-                EXPORT  CPU_CLCD_IRQHandler       [WEAK]
-                EXPORT  SPI_IRQHandler            [WEAK]
-
-WDT_IRQHandler
-RTC_IRQHandler
-TIM0_IRQHandler
-TIM2_IRQHandler
-MCIA_IRQHandler
-MCIB_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-UART3_IRQHandler
-UART4_IRQHandler
-AACI_IRQHandler
-CLCD_IRQHandler
-ENET_IRQHandler
-USBDC_IRQHandler
-USBHC_IRQHandler
-CHLCD_IRQHandler
-FLEXRAY_IRQHandler
-CAN_IRQHandler
-LIN_IRQHandler
-I2C_IRQHandler
-CPU_CLCD_IRQHandler
-SPI_IRQHandler
-                B       .
 
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+                MACRO
+                Set_Default_Handler  $Handler_Name
+$Handler_Name   PROC
+                EXPORT   $Handler_Name             [WEAK]
+                B        .
                 ENDP
+                MEND
 
 
-                ALIGN
-
-
-; User Initial Stack & Heap
-
-                IF      :DEF:__MICROLIB
+; Default exception/interrupt handler
 
-                EXPORT  __initial_sp
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
+                Set_Default_Handler  NMI_Handler
+                Set_Default_Handler  HardFault_Handler
+                Set_Default_Handler  SVC_Handler
+                Set_Default_Handler  PendSV_Handler
+                Set_Default_Handler  SysTick_Handler
 
-                ELSE
+                Set_Default_Handler  Interrupt0_Handler
+                Set_Default_Handler  Interrupt1_Handler
+                Set_Default_Handler  Interrupt2_Handler
+                Set_Default_Handler  Interrupt3_Handler
+                Set_Default_Handler  Interrupt4_Handler
+                Set_Default_Handler  Interrupt5_Handler
+                Set_Default_Handler  Interrupt6_Handler
+                Set_Default_Handler  Interrupt7_Handler
+                Set_Default_Handler  Interrupt8_Handler
+                Set_Default_Handler  Interrupt9_Handler
 
-                IMPORT  __use_two_region_memory
-                EXPORT  __user_initial_stackheap
+                ALIGN
 
-__user_initial_stackheap PROC
-                LDR     R0, =  Heap_Mem
-                LDR     R1, =(Stack_Mem + Stack_Size)
-                LDR     R2, = (Heap_Mem +  Heap_Size)
-                LDR     R3, = Stack_Mem
-                BX      LR
-                ENDP
 
-                ALIGN
+; User setup Stack & Heap
 
+                EXPORT   __stack_limit
+                EXPORT   __initial_sp
+                IF       Heap_Size != 0                      ; Heap is provided
+                EXPORT   __heap_base
+                EXPORT   __heap_limit
                 ENDIF
 
-
                 END

CMSIS/CoreValidation/Tests/Cortex-M23S/AC6/RTE/Device/ARMCM23_TZ/system_ARMCM23.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
  * @file     system_ARMCM23.c
  * @brief    CMSIS Device System Source File for
- *           ARMCM23 Device Series
- * @version  V5.00
- * @date     21. October 2016
+ *           ARMCM23 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -38,9 +38,9 @@
 /*----------------------------------------------------------------------------
   Define clocks
  *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+#define  XTAL            (50000000UL)     /* Oscillator frequency */
 
-#define  SYSTEM_CLOCK    (5U * XTAL)
+#define  SYSTEM_CLOCK    (XTAL / 2U)
 
 
 /*----------------------------------------------------------------------------
@@ -53,7 +53,7 @@
 /*----------------------------------------------------------------------------
   System Core Clock Variable
  *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */
 
 
 /*----------------------------------------------------------------------------

CMSIS/CoreValidation/Tests/Cortex-M23S/GCC/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     partition_ARMCM23.h
  * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM23
- * @version  V5.00
- * @date     28. October 2016
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -707,374 +707,6 @@
 //   </e>
 */
 
-/*
-//   <e>Initialize ITNS 8 (Interrupts 256..287)
-*/
-#define NVIC_INIT_ITNS8    0
-
-/*
-// Interrupts 0..31
-//   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 259 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 260 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 261 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 262 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 263 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 264 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 265 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS8_VAL      0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 9 (Interrupts 288..319)
-*/
-#define NVIC_INIT_ITNS9    0
-
-/*
-// Interrupts 32..63
-//   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 291 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 292 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 293 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 294 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 295 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 296 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 297 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS9_VAL      0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 10 (Interrupts 320..351)
-*/
-#define NVIC_INIT_ITNS10   0
-
-/*
-// Interrupts 64..95
-//   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 323 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 324 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 325 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 326 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 327 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 328 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 329 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS10_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 11 (Interrupts 352..383)
-*/
-#define NVIC_INIT_ITNS11   0
-
-/*
-// Interrupts 96..127
-//   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 355 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 356 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 357 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 358 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 359 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 360 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 361 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS11_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 12 (Interrupts 384..415)
-*/
-#define NVIC_INIT_ITNS12   0
-
-/*
-// Interrupts 128..159
-//   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 387 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 388 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 389 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 390 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 391 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 392 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 393 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS12_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 13 (Interrupts 416..447)
-*/
-#define NVIC_INIT_ITNS13   0
-
-/*
-// Interrupts 160..191
-//   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 419 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 420 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 421 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 422 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 423 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 424 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 425 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS13_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 14 (Interrupts 448..479)
-*/
-#define NVIC_INIT_ITNS14   0
-
-/*
-// Interrupts 192..223
-//   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 451 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 452 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 453 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 454 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 455 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 456 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 457 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS14_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 15 (Interrupts 480..511)
-*/
-#define NVIC_INIT_ITNS15   0
-
-/*
-// Interrupts 224..255
-//   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 483 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 484 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 485 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 486 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 487 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 488 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 489 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS15_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
 /*
 // </h>
 */
@@ -1193,38 +825,6 @@ __STATIC_INLINE void TZ_SAU_Setup (void)
     NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;
   #endif
 
-  #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)
-    NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)
-    NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)
-    NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)
-    NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)
-    NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)
-    NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)
-    NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)
-    NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;
-  #endif
-
   /* repeat this for all possible ITNS elements */
 
 }

CMSIS/CoreValidation/Tests/Cortex-M23S/GCC/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
- * @file     startup_ARMCM23.s
+ * @file     startup_ARMCM23.c
  * @brief    CMSIS Core Device Startup File for
- *           ARMCM23 Device Series
- * @version  V5.00
- * @date     21. October 2016
+ *           ARMCM23 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -23,6 +23,10 @@
  * limitations under the License.
  */
 
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
 #include <stdint.h>
 
 
@@ -39,6 +43,7 @@ extern uint32_t __zero_table_end__;
 extern uint32_t __bss_start__;
 extern uint32_t __bss_end__;
 extern uint32_t __StackTop;
+extern uint32_t __StackLimit;
 
 /*----------------------------------------------------------------------------
   Exception / Interrupt Handler Function Prototype
@@ -49,35 +54,30 @@ typedef void( *pFunc )( void );
 /*----------------------------------------------------------------------------
   External References
  *----------------------------------------------------------------------------*/
-#ifndef __START
-extern void  _start(void) __attribute__((noreturn));    /* PreeMain (C library entry point) */
-#else
-extern int  __START(void) __attribute__((noreturn));    /* main entry point */
-#endif
-
-#ifndef __NO_SYSTEM_INIT
-extern void SystemInit (void);            /* CMSIS System Initialization      */
-#endif
+extern void _start     (void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
+extern void SystemInit (void);                           /* CMSIS System Initialization */
 
 
 /*----------------------------------------------------------------------------
   Internal References
  *----------------------------------------------------------------------------*/
-void Default_Handler(void);                          /* Default empty handler */
-void Reset_Handler(void);                            /* Reset Handler */
+void Default_Handler(void) __attribute__ ((noreturn));
+void Reset_Handler  (void) __attribute__ ((noreturn));
 
 
 /*----------------------------------------------------------------------------
   User Initial Stack & Heap
  *----------------------------------------------------------------------------*/
-#ifndef __STACK_SIZE
-  #define	__STACK_SIZE  0x00000400
-#endif
+//<h> Stack Configuration
+//  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//</h>
+#define  __STACK_SIZE  0x00000400
 static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack")));
 
-#ifndef __HEAP_SIZE
-  #define	__HEAP_SIZE   0x00000C00
-#endif
+//<h> Heap Configuration
+//  <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//</h>
+#define  __HEAP_SIZE   0x00000C00
 #if __HEAP_SIZE > 0
 static uint8_t heap[__HEAP_SIZE]   __attribute__ ((aligned(8), used, section(".heap")));
 #endif
@@ -86,94 +86,59 @@ static uint8_t heap[__HEAP_SIZE]   __attribute__ ((aligned(8), used, section(".h
 /*----------------------------------------------------------------------------
   Exception / Interrupt Handler
  *----------------------------------------------------------------------------*/
-/* ARMCM23 Processor Exceptions */
-void NMI_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
-void HardFault_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
-void SVC_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
-void PendSV_Handler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void SysTick_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
-
-/* ARMCM23 Specific Interrupts */
-void WDT_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void RTC_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM0_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM2_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIA_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIB_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART0_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART1_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART2_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART4_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void AACI_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void CLCD_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void ENET_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBDC_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBHC_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void CHLCD_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void FLEXRAY_IRQHandler  (void) __attribute__ ((weak, alias("Default_Handler")));
-void CAN_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void LIN_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void I2C_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void CPU_CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART3_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void SPI_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+/* Exceptions */
+void NMI_Handler            (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler            (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler        (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
 
 
 /*----------------------------------------------------------------------------
   Exception / Interrupt Vector table
  *----------------------------------------------------------------------------*/
-const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = {
-  /* ARMCM23 Exceptions Handler */
-  (pFunc)((uint32_t)&__StackTop),           /*      Initial Stack Pointer     */
-  Reset_Handler,                            /*      Reset Handler             */
-  NMI_Handler,                              /*      NMI Handler               */
-  HardFault_Handler,                        /*      Hard Fault Handler        */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  SVC_Handler,                              /*      SVCall Handler            */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  PendSV_Handler,                           /*      PendSV Handler            */
-  SysTick_Handler,                          /*      SysTick Handler           */
-
-  /* External interrupts */
-  WDT_IRQHandler,                           /*  0:  Watchdog Timer            */
-  RTC_IRQHandler,                           /*  1:  Real Time Clock           */
-  TIM0_IRQHandler,                          /*  2:  Timer0 / Timer1           */
-  TIM2_IRQHandler,                          /*  3:  Timer2 / Timer3           */
-  MCIA_IRQHandler,                          /*  4:  MCIa                      */
-  MCIB_IRQHandler,                          /*  5:  MCIb                      */
-  UART0_IRQHandler,                         /*  6:  UART0 - DUT FPGA          */
-  UART1_IRQHandler,                         /*  7:  UART1 - DUT FPGA          */
-  UART2_IRQHandler,                         /*  8:  UART2 - DUT FPGA          */
-  UART4_IRQHandler,                         /*  9:  UART4 - not connected     */
-  AACI_IRQHandler,                          /* 10: AACI / AC97                */
-  CLCD_IRQHandler,                          /* 11: CLCD Combined Interrupt    */
-  ENET_IRQHandler,                          /* 12: Ethernet                   */
-  USBDC_IRQHandler,                         /* 13: USB Device                 */
-  USBHC_IRQHandler,                         /* 14: USB Host Controller        */
-  CHLCD_IRQHandler,                         /* 15: Character LCD              */
-  FLEXRAY_IRQHandler,                       /* 16: Flexray                    */
-  CAN_IRQHandler,                           /* 17: CAN                        */
-  LIN_IRQHandler,                           /* 18: LIN                        */
-  I2C_IRQHandler,                           /* 19: I2C ADC/DAC                */
-  0,                                        /* 20: Reserved                   */
-  0,                                        /* 21: Reserved                   */
-  0,                                        /* 22: Reserved                   */
-  0,                                        /* 23: Reserved                   */
-  0,                                        /* 24: Reserved                   */
-  0,                                        /* 25: Reserved                   */
-  0,                                        /* 26: Reserved                   */
-  0,                                        /* 27: Reserved                   */
-  CPU_CLCD_IRQHandler,                      /* 28: Reserved - CPU FPGA CLCD   */
-  0,                                        /* 29: Reserved - CPU FPGA        */
-  UART3_IRQHandler,                         /* 30: UART3    - CPU FPGA        */
-  SPI_IRQHandler                            /* 31: SPI Touchscreen - CPU FPGA */
+extern const pFunc __Vectors[240];
+       const pFunc __Vectors[240] __attribute__ ((section(".vectors"))) = {
+  (pFunc)(&__StackTop),                     /*     Initial Stack Pointer */
+  Reset_Handler,                            /*     Reset Handler */
+  NMI_Handler,                              /* -14 NMI Handler */
+  HardFault_Handler,                        /* -13 Hard Fault Handler */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  SVC_Handler,                              /*  -5 SVCall Handler */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  PendSV_Handler,                           /*  -2 PendSV Handler */
+  SysTick_Handler,                          /*  -1 SysTick Handler */
+
+  /* Interrupts */
+  Interrupt0_Handler,                       /*   0 Interrupt 0 */
+  Interrupt1_Handler,                       /*   1 Interrupt 1 */
+  Interrupt2_Handler,                       /*   2 Interrupt 2 */
+  Interrupt3_Handler,                       /*   3 Interrupt 3 */
+  Interrupt4_Handler,                       /*   4 Interrupt 4 */
+  Interrupt5_Handler,                       /*   5 Interrupt 5 */
+  Interrupt6_Handler,                       /*   6 Interrupt 6 */
+  Interrupt7_Handler,                       /*   7 Interrupt 7 */
+  Interrupt8_Handler,                       /*   8 Interrupt 8 */
+  Interrupt9_Handler                        /*   9 Interrupt 9 */
+                                            /* Interrupts 10 .. 224 are left out */
 };
 
 
@@ -184,41 +149,42 @@ void Reset_Handler(void) {
   uint32_t *pSrc, *pDest;
   uint32_t *pTable __attribute__((unused));
 
-/*  Firstly it copies data from read only memory to RAM. There are two schemes
- *  to copy. One can copy more than one sections. Another can only copy
- *  one section.  The former scheme needs more instructions and read-only
- *  data to implement than the latter.
- *  Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.  */
+/* Firstly it copies data from read only memory to RAM.
+ * There are two schemes to copy. One can copy more than one sections.
+ * Another can copy only one section. The former scheme needs more
+ * instructions and read-only data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.
+ */
 
 #ifdef __STARTUP_COPY_MULTIPLE
-/*  Multiple sections scheme.
+/* Multiple sections scheme.
  *
- *  Between symbol address __copy_table_start__ and __copy_table_end__,
- *  there are array of triplets, each of which specify:
- *    offset 0: LMA of start of a section to copy from
- *    offset 4: VMA of start of a section to copy to
- *    offset 8: size of the section to copy. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ *   offset 0: LMA of start of a section to copy from
+ *   offset 4: VMA of start of a section to copy to
+ *   offset 8: size of the section to copy. Must be multiply of 4
  *
- *  All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
  */
   pTable = &__copy_table_start__;
 
   for (; pTable < &__copy_table_end__; pTable = pTable + 3) {
-		pSrc  = (uint32_t*)*(pTable + 0);
-		pDest = (uint32_t*)*(pTable + 1);
-		for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
+    pSrc  = (uint32_t*)*(pTable + 0);
+    pDest = (uint32_t*)*(pTable + 1);
+    for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
       *pDest++ = *pSrc++;
-		}
-	}
+    }
+  }
 #else
-/*  Single section scheme.
+/* Single section scheme.
  *
- *  The ranges of copy from/to are specified by following symbols
- *    __etext: LMA of start of the section to copy from. Usually end of text
- *    __data_start__: VMA of start of the section to copy to
- *    __data_end__: VMA of end of the section to copy to
+ * The ranges of copy from/to are specified by following symbols
+ *   __etext: LMA of start of the section to copy from. Usually end of text
+ *   __data_start__: VMA of start of the section to copy to
+ *   __data_end__: VMA of end of the section to copy to
  *
- *  All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
  */
   pSrc  = &__etext;
   pDest = &__data_start__;
@@ -228,40 +194,40 @@ void Reset_Handler(void) {
   }
 #endif /*__STARTUP_COPY_MULTIPLE */
 
-/*  This part of work usually is done in C library startup code. Otherwise,
- *  define this macro to enable it in this startup.
+/* This part of work usually is done in C library startup code.
+ * Otherwise, define this macro to enable it in this startup.
  *
- *  There are two schemes too. One can clear multiple BSS sections. Another
- *  can only clear one section. The former is more size expensive than the
- *  latter.
+ * There are two schemes too.
+ * One can clear multiple BSS sections. Another can only clear one section.
+ * The former is more size expensive than the latter.
  *
- *  Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- *  Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
  */
 #ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/*  Multiple sections scheme.
+/* Multiple sections scheme.
  *
- *  Between symbol address __copy_table_start__ and __copy_table_end__,
- *  there are array of tuples specifying:
- *    offset 0: Start of a BSS section
- *    offset 4: Size of this BSS section. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ *   offset 0: Start of a BSS section
+ *   offset 4: Size of this BSS section. Must be multiply of 4
  */
   pTable = &__zero_table_start__;
 
   for (; pTable < &__zero_table_end__; pTable = pTable + 2) {
-		pDest = (uint32_t*)*(pTable + 0);
-		for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
+    pDest = (uint32_t*)*(pTable + 0);
+    for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
       *pDest++ = 0;
-		}
-	}
+    }
+  }
 #elif defined (__STARTUP_CLEAR_BSS)
-/*  Single BSS section scheme.
+/* Single BSS section scheme.
  *
- *  The BSS section is specified by following symbols
- *    __bss_start__: start of the BSS section.
- *    __bss_end__: end of the BSS section.
+ * The BSS section is specified by following symbols
+ *   __bss_start__: start of the BSS section.
+ *   __bss_end__: end of the BSS section.
  *
- *  Both addresses must be aligned to 4 bytes boundary.
+ * Both addresses must be aligned to 4 bytes boundary.
  */
   pDest = &__bss_start__;
 
@@ -270,15 +236,10 @@ void Reset_Handler(void) {
   }
 #endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
 
-#ifndef __NO_SYSTEM_INIT
-	SystemInit();
-#endif
-
-#ifndef __START
-#define __START _start
-#endif
-	__START();
+  __set_MSPLIM((uint32_t)&__StackLimit);
 
+  SystemInit();                             /* CMSIS System Initialization */
+  _start();                                 /* Enter PreeMain (C library entry point) */
 }
 
 
@@ -287,5 +248,5 @@ void Reset_Handler(void) {
  *----------------------------------------------------------------------------*/
 void Default_Handler(void) {
 
-	while(1);
+  while(1);
 }

CMSIS/CoreValidation/Tests/Cortex-M23S/GCC/RTE/Device/ARMCM23_TZ/system_ARMCM23.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
  * @file     system_ARMCM23.c
  * @brief    CMSIS Device System Source File for
- *           ARMCM23 Device Series
- * @version  V5.00
- * @date     21. October 2016
+ *           ARMCM23 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -38,9 +38,9 @@
 /*----------------------------------------------------------------------------
   Define clocks
  *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+#define  XTAL            (50000000UL)     /* Oscillator frequency */
 
-#define  SYSTEM_CLOCK    (5U * XTAL)
+#define  SYSTEM_CLOCK    (XTAL / 2U)
 
 
 /*----------------------------------------------------------------------------
@@ -53,7 +53,7 @@
 /*----------------------------------------------------------------------------
   System Core Clock Variable
  *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */
 
 
 /*----------------------------------------------------------------------------

CMSIS/CoreValidation/Tests/Cortex-M23S/IAR/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     partition_ARMCM23.h
  * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM23
- * @version  V5.00
- * @date     28. October 2016
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -707,374 +707,6 @@
 //   </e>
 */
 
-/*
-//   <e>Initialize ITNS 8 (Interrupts 256..287)
-*/
-#define NVIC_INIT_ITNS8    0
-
-/*
-// Interrupts 0..31
-//   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 259 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 260 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 261 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 262 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 263 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 264 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 265 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS8_VAL      0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 9 (Interrupts 288..319)
-*/
-#define NVIC_INIT_ITNS9    0
-
-/*
-// Interrupts 32..63
-//   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 291 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 292 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 293 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 294 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 295 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 296 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 297 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS9_VAL      0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 10 (Interrupts 320..351)
-*/
-#define NVIC_INIT_ITNS10   0
-
-/*
-// Interrupts 64..95
-//   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 323 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 324 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 325 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 326 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 327 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 328 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 329 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS10_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 11 (Interrupts 352..383)
-*/
-#define NVIC_INIT_ITNS11   0
-
-/*
-// Interrupts 96..127
-//   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 355 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 356 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 357 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 358 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 359 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 360 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 361 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS11_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 12 (Interrupts 384..415)
-*/
-#define NVIC_INIT_ITNS12   0
-
-/*
-// Interrupts 128..159
-//   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 387 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 388 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 389 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 390 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 391 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 392 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 393 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS12_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 13 (Interrupts 416..447)
-*/
-#define NVIC_INIT_ITNS13   0
-
-/*
-// Interrupts 160..191
-//   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 419 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 420 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 421 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 422 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 423 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 424 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 425 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS13_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 14 (Interrupts 448..479)
-*/
-#define NVIC_INIT_ITNS14   0
-
-/*
-// Interrupts 192..223
-//   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 451 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 452 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 453 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 454 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 455 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 456 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 457 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS14_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
-/*
-//   <e>Initialize ITNS 15 (Interrupts 480..511)
-*/
-#define NVIC_INIT_ITNS15   0
-
-/*
-// Interrupts 224..255
-//   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state
-//   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state
-//   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state
-//   <o.3>  Interrupt 483 <0=> Secure state <1=> Non-Secure state
-//   <o.4>  Interrupt 484 <0=> Secure state <1=> Non-Secure state
-//   <o.5>  Interrupt 485 <0=> Secure state <1=> Non-Secure state
-//   <o.6>  Interrupt 486 <0=> Secure state <1=> Non-Secure state
-//   <o.7>  Interrupt 487 <0=> Secure state <1=> Non-Secure state
-//   <o.8>  Interrupt 488 <0=> Secure state <1=> Non-Secure state
-//   <o.9>  Interrupt 489 <0=> Secure state <1=> Non-Secure state
-//   <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state
-//   <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state
-//   <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state
-//   <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state
-//   <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state
-//   <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state
-//   <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state
-//   <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state
-//   <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state
-//   <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state
-//   <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state
-//   <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state
-//   <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state
-//   <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state
-//   <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state
-//   <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state
-//   <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state
-//   <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state
-//   <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state
-//   <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state
-//   <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state
-//   <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state
-*/
-#define NVIC_INIT_ITNS15_VAL     0x00000000
-
-/*
-//   </e>
-*/
-
 /*
 // </h>
 */
@@ -1193,38 +825,6 @@ __STATIC_INLINE void TZ_SAU_Setup (void)
     NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;
   #endif
 
-  #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)
-    NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)
-    NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)
-    NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)
-    NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)
-    NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)
-    NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)
-    NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;
-  #endif
-
-  #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)
-    NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;
-  #endif
-
   /* repeat this for all possible ITNS elements */
 
 }

CMSIS/CoreValidation/Tests/Cortex-M23S/IAR/RTE/Device/ARMCM23_TZ/startup_ARMCM23.s

@@ -1,12 +1,12 @@
 ;/**************************************************************************//**
 ; * @file     startup_ARMCM23.s
 ; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM23 Device Series
-; * @version  V5.00
-; * @date     21. October 2016
+; *           ARMCM23 Device
+; * @version  V5.3.1
+; * @date     09. July 2018
 ; ******************************************************************************/
 ;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
 ; *
 ; * SPDX-License-Identifier: Apache-2.0
 ; *
@@ -39,234 +39,109 @@
 ; Cortex-M version
 ;
 
-        MODULE  ?cstartup
+                MODULE   ?cstartup
 
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
+                ;; Forward declaration of sections.
+                SECTION  CSTACK:DATA:NOROOT(3)
 
-        SECTION .intvec:CODE:NOROOT(2)
+                SECTION  .intvec:CODE:NOROOT(2)
 
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit
-        PUBLIC  __vector_table
-        PUBLIC  __vector_table_0x1c
-        PUBLIC  __Vectors
-        PUBLIC  __Vectors_End
-        PUBLIC  __Vectors_Size
+                EXTERN   __iar_program_start
+                EXTERN   SystemInit
+                PUBLIC   __vector_table
+                PUBLIC   __vector_table_0x1c
+                PUBLIC   __Vectors
+                PUBLIC   __Vectors_End
+                PUBLIC   __Vectors_Size
 
-        DATA
+                DATA
 
 __vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler
-
-        DCD     NMI_Handler
-        DCD     HardFault_Handler
-        DCD     0
-        DCD     0
-        DCD     0
+                DCD      sfe(CSTACK)                         ;     Top of Stack
+                DCD      Reset_Handler                       ;     Reset Handler
+                DCD      NMI_Handler                         ; -14 NMI Handler
+                DCD      HardFault_Handler                   ; -13 Hard Fault Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
 __vector_table_0x1c
-        DCD     0
-        DCD     0
-        DCD     0
-        DCD     0
-        DCD     SVC_Handler
-        DCD     0
-        DCD     0
-        DCD     PendSV_Handler
-        DCD     SysTick_Handler
-
-        ; External Interrupts
-        DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
-        DCD     RTC_IRQHandler            ;  1:  Real Time Clock
-        DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
-        DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
-        DCD     MCIA_IRQHandler           ;  4:  MCIa
-        DCD     MCIB_IRQHandler           ;  5:  MCIb
-        DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
-        DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
-        DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
-        DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
-        DCD     AACI_IRQHandler           ; 10: AACI / AC97
-        DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
-        DCD     ENET_IRQHandler           ; 12: Ethernet
-        DCD     USBDC_IRQHandler          ; 13: USB Device
-        DCD     USBHC_IRQHandler          ; 14: USB Host Controller
-        DCD     CHLCD_IRQHandler          ; 15: Character LCD
-        DCD     FLEXRAY_IRQHandler        ; 16: Flexray
-        DCD     CAN_IRQHandler            ; 17: CAN
-        DCD     LIN_IRQHandler            ; 18: LIN
-        DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
-        DCD     0                         ; 20: Reserved
-        DCD     0                         ; 21: Reserved
-        DCD     0                         ; 22: Reserved
-        DCD     0                         ; 23: Reserved
-        DCD     0                         ; 24: Reserved
-        DCD     0                         ; 25: Reserved
-        DCD     0                         ; 26: Reserved
-        DCD     0                         ; 27: Reserved
-        DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
-        DCD     0                         ; 29: Reserved - CPU FPGA
-        DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
-        DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      SVC_Handler                         ;  -5 SVCall Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      PendSV_Handler                      ;  -2 PendSV Handler
+                DCD      SysTick_Handler                     ;  -1 SysTick Handler
+
+                ; Interrupts
+                DCD      Interrupt0_Handler                  ;   0 Interrupt 0
+                DCD      Interrupt1_Handler                  ;   1 Interrupt 1
+                DCD      Interrupt2_Handler                  ;   2 Interrupt 2
+                DCD      Interrupt3_Handler                  ;   3 Interrupt 3
+                DCD      Interrupt4_Handler                  ;   4 Interrupt 4
+                DCD      Interrupt5_Handler                  ;   5 Interrupt 5
+                DCD      Interrupt6_Handler                  ;   6 Interrupt 6
+                DCD      Interrupt7_Handler                  ;   7 Interrupt 7
+                DCD      Interrupt8_Handler                  ;   8 Interrupt 8
+                DCD      Interrupt9_Handler                  ;   9 Interrupt 9
+
+                DS32    (214)                                ; Interrupts 10 .. 224 are left out
 __Vectors_End
 
-__Vectors       EQU   __vector_table
-__Vectors_Size  EQU   __Vectors_End - __Vectors
+__Vectors       EQU      __vector_table
+__Vectors_Size  EQU      __Vectors_End - __Vectors
 
 
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
+                THUMB
 
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
+; Reset Handler
 
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
+                PUBWEAK  Reset_Handler
+                SECTION  .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+                LDR      R0, =SystemInit
+                BLX      R0
+                LDR      R0, =__iar_program_start
+                BX       R0
+
+
+                PUBWEAK NMI_Handler
+                PUBWEAK HardFault_Handler
+                PUBWEAK SVC_Handler
+                PUBWEAK PendSV_Handler
+                PUBWEAK SysTick_Handler
+
+                PUBWEAK Interrupt0_Handler
+                PUBWEAK Interrupt1_Handler
+                PUBWEAK Interrupt2_Handler
+                PUBWEAK Interrupt3_Handler
+                PUBWEAK Interrupt4_Handler
+                PUBWEAK Interrupt5_Handler
+                PUBWEAK Interrupt6_Handler
+                PUBWEAK Interrupt7_Handler
+                PUBWEAK Interrupt8_Handler
+                PUBWEAK Interrupt9_Handler
+                SECTION .text:CODE:REORDER:NOROOT(1)
 NMI_Handler
-        B NMI_Handler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 HardFault_Handler
-        B HardFault_Handler
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 SVC_Handler
-        B SVC_Handler
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 SysTick_Handler
-        B SysTick_Handler
-
-        PUBWEAK WDT_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WDT_IRQHandler
-        B WDT_IRQHandler
-
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-
-        PUBWEAK TIM0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM0_IRQHandler
-        B TIM0_IRQHandler
-
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-
-        PUBWEAK MCIA_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MCIA_IRQHandler
-        B MCIA_IRQHandler
-
-        PUBWEAK MCIB_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MCIB_IRQHandler
-        B MCIB_IRQHandler
-
-        PUBWEAK UART0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART0_IRQHandler
-        B UART0_IRQHandler
-
-        PUBWEAK UART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART1_IRQHandler
-        B UART1_IRQHandler
-
-        PUBWEAK UART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART2_IRQHandler
-        B UART2_IRQHandler
-
-        PUBWEAK UART4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
-        B UART4_IRQHandler
-
-        PUBWEAK AACI_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-AACI_IRQHandler
-        B AACI_IRQHandler
-
-        PUBWEAK CLCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CLCD_IRQHandler
-        B CLCD_IRQHandler
-
-        PUBWEAK ENET_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ENET_IRQHandler
-        B ENET_IRQHandler
-
-        PUBWEAK USBDC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USBDC_IRQHandler
-        B USBDC_IRQHandler
-
-        PUBWEAK USBHC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USBHC_IRQHandler
-        B USBHC_IRQHandler
-
-        PUBWEAK CHLCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CHLCD_IRQHandler
-        B CHLCD_IRQHandler
-
-        PUBWEAK FLEXRAY_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLEXRAY_IRQHandler
-        B FLEXRAY_IRQHandler
-
-        PUBWEAK CAN_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN_IRQHandler
-        B CAN_IRQHandler
-
-        PUBWEAK LIN_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-LIN_IRQHandler
-        B LIN_IRQHandler
-
-        PUBWEAK I2C_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C_IRQHandler
-        B I2C_IRQHandler
-
-        PUBWEAK CPU_CLCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CPU_CLCD_IRQHandler
-        B CPU_CLCD_IRQHandler
-
-        PUBWEAK UART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART3_IRQHandler
-        B UART3_IRQHandler
-
-        PUBWEAK SPI_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI_IRQHandler
-        B SPI_IRQHandler
 
-        END
+Interrupt0_Handler
+Interrupt1_Handler
+Interrupt2_Handler
+Interrupt3_Handler
+Interrupt4_Handler
+Interrupt5_Handler
+Interrupt6_Handler
+Interrupt7_Handler
+Interrupt8_Handler
+Interrupt9_Handler
+Default_Handler
+                B        .
+
+
+                END

CMSIS/CoreValidation/Tests/Cortex-M23S/IAR/RTE/Device/ARMCM23_TZ/system_ARMCM23.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
  * @file     system_ARMCM23.c
  * @brief    CMSIS Device System Source File for
- *           ARMCM23 Device Series
- * @version  V5.00
- * @date     21. October 2016
+ *           ARMCM23 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -38,9 +38,9 @@
 /*----------------------------------------------------------------------------
   Define clocks
  *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+#define  XTAL            (50000000UL)     /* Oscillator frequency */
 
-#define  SYSTEM_CLOCK    (5U * XTAL)
+#define  SYSTEM_CLOCK    (XTAL / 2U)
 
 
 /*----------------------------------------------------------------------------
@@ -53,7 +53,7 @@
 /*----------------------------------------------------------------------------
   System Core Clock Variable
  *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */
 
 
 /*----------------------------------------------------------------------------

CMSIS/CoreValidation/Tests/Cortex-M3/AC5/RTE/Device/ARMCM3/startup_ARMCM3.s

@@ -1,12 +1,12 @@
 ;/**************************************************************************//**
 ; * @file     startup_ARMCM3.s
 ; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM3 Device Series
-; * @version  V5.00
-; * @date     02. March 2016
+; *           ARMCM3 Device
+; * @version  V5.3.1
+; * @date     09. July 2018
 ; ******************************************************************************/
 ;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
 ; *
 ; * SPDX-License-Identifier: Apache-2.0
 ; *
@@ -23,32 +23,33 @@
 ; * limitations under the License.
 ; */
 
-;/*
 ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
 
 
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Stack Configuration
+;  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
 
-Stack_Size      EQU     0x00000400
+Stack_Size      EQU      0x00000400
 
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
+                AREA     STACK, NOINIT, READWRITE, ALIGN=3
+__stack_limit
+Stack_Mem       SPACE    Stack_Size
 __initial_sp
 
 
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Heap Configuration
+;  <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
 
-Heap_Size       EQU     0x00000C00
+Heap_Size       EQU      0x00000C00
 
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+                IF       Heap_Size != 0                      ; Heap is provided
+                AREA     HEAP, NOINIT, READWRITE, ALIGN=3
 __heap_base
-Heap_Mem        SPACE   Heap_Size
+Heap_Mem        SPACE    Heap_Size
 __heap_limit
+                ENDIF
 
 
                 PRESERVE8
@@ -57,206 +58,106 @@ __heap_limit
 
 ; Vector Table Mapped to Address 0 at Reset
 
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
-                DCD     RTC_IRQHandler            ;  1:  Real Time Clock
-                DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
-                DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
-                DCD     MCIA_IRQHandler           ;  4:  MCIa
-                DCD     MCIB_IRQHandler           ;  5:  MCIb
-                DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
-                DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
-                DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
-                DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
-                DCD     AACI_IRQHandler           ; 10: AACI / AC97
-                DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
-                DCD     ENET_IRQHandler           ; 12: Ethernet
-                DCD     USBDC_IRQHandler          ; 13: USB Device
-                DCD     USBHC_IRQHandler          ; 14: USB Host Controller
-                DCD     CHLCD_IRQHandler          ; 15: Character LCD
-                DCD     FLEXRAY_IRQHandler        ; 16: Flexray
-                DCD     CAN_IRQHandler            ; 17: CAN
-                DCD     LIN_IRQHandler            ; 18: LIN
-                DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
-                DCD     0                         ; 20: Reserved
-                DCD     0                         ; 21: Reserved
-                DCD     0                         ; 22: Reserved
-                DCD     0                         ; 23: Reserved
-                DCD     0                         ; 24: Reserved
-                DCD     0                         ; 25: Reserved
-                DCD     0                         ; 26: Reserved
-                DCD     0                         ; 27: Reserved
-                DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
-                DCD     0                         ; 29: Reserved - CPU FPGA
-                DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
-                DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
+                AREA     RESET, DATA, READONLY
+                EXPORT   __Vectors
+                EXPORT   __Vectors_End
+                EXPORT   __Vectors_Size
+
+__Vectors       DCD      __initial_sp                        ;     Top of Stack
+                DCD      Reset_Handler                       ;     Reset Handler
+                DCD      NMI_Handler                         ; -14 NMI Handler
+                DCD      HardFault_Handler                   ; -13 Hard Fault Handler
+                DCD      MemManage_Handler                   ; -12 MPU Fault Handler
+                DCD      BusFault_Handler                    ; -11 Bus Fault Handler
+                DCD      UsageFault_Handler                  ; -10 Usage Fault Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      SVC_Handler                         ;  -5 SVCall Handler
+                DCD      DebugMon_Handler                    ;  -4 Debug Monitor Handler
+                DCD      0                                   ;     Reserved
+                DCD      PendSV_Handler                      ;  -2 PendSV Handler
+                DCD      SysTick_Handler                     ;  -1 SysTick Handler
+
+                ; Interrupts
+                DCD      Interrupt0_Handler                  ;   0 Interrupt 0
+                DCD      Interrupt1_Handler                  ;   1 Interrupt 1
+                DCD      Interrupt2_Handler                  ;   2 Interrupt 2
+                DCD      Interrupt3_Handler                  ;   3 Interrupt 3
+                DCD      Interrupt4_Handler                  ;   4 Interrupt 4
+                DCD      Interrupt5_Handler                  ;   5 Interrupt 5
+                DCD      Interrupt6_Handler                  ;   6 Interrupt 6
+                DCD      Interrupt7_Handler                  ;   7 Interrupt 7
+                DCD      Interrupt8_Handler                  ;   8 Interrupt 8
+                DCD      Interrupt9_Handler                  ;   9 Interrupt 9
+
+                SPACE    (214 * 4)                           ; Interrupts 10 .. 224 are left out
 __Vectors_End
+__Vectors_Size  EQU      __Vectors_End - __Vectors
 
-__Vectors_Size  EQU     __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
 
+                AREA     |.text|, CODE, READONLY
 
 ; Reset Handler
 
 Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  SystemInit
-                IMPORT  __main
-                LDR     R0, =SystemInit
-                BLX     R0
-                LDR     R0, =__main
-                BX      R0
+                EXPORT   Reset_Handler             [WEAK]
+                IMPORT   SystemInit
+                IMPORT   __main
+
+                LDR      R0, =SystemInit
+                BLX      R0
+                LDR      R0, =__main
+                BX       R0
                 ENDP
 
 
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler               [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler         [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler          [WEAK]
-                B       .
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+                MACRO
+                Set_Default_Handler  $Handler_Name
+$Handler_Name   PROC
+                EXPORT   $Handler_Name             [WEAK]
+                B        .
                 ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler        [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler          [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WDT_IRQHandler            [WEAK]
-                EXPORT  RTC_IRQHandler            [WEAK]
-                EXPORT  TIM0_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler           [WEAK]
-                EXPORT  MCIA_IRQHandler           [WEAK]
-                EXPORT  MCIB_IRQHandler           [WEAK]
-                EXPORT  UART0_IRQHandler          [WEAK]
-                EXPORT  UART1_IRQHandler          [WEAK]
-                EXPORT  UART2_IRQHandler          [WEAK]
-                EXPORT  UART3_IRQHandler          [WEAK]
-                EXPORT  UART4_IRQHandler          [WEAK]
-                EXPORT  AACI_IRQHandler           [WEAK]
-                EXPORT  CLCD_IRQHandler           [WEAK]
-                EXPORT  ENET_IRQHandler           [WEAK]
-                EXPORT  USBDC_IRQHandler          [WEAK]
-                EXPORT  USBHC_IRQHandler          [WEAK]
-                EXPORT  CHLCD_IRQHandler          [WEAK]
-                EXPORT  FLEXRAY_IRQHandler        [WEAK]
-                EXPORT  CAN_IRQHandler            [WEAK]
-                EXPORT  LIN_IRQHandler            [WEAK]
-                EXPORT  I2C_IRQHandler            [WEAK]
-                EXPORT  CPU_CLCD_IRQHandler       [WEAK]
-                EXPORT  SPI_IRQHandler            [WEAK]
-
-WDT_IRQHandler
-RTC_IRQHandler
-TIM0_IRQHandler
-TIM2_IRQHandler
-MCIA_IRQHandler
-MCIB_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-UART3_IRQHandler
-UART4_IRQHandler
-AACI_IRQHandler
-CLCD_IRQHandler
-ENET_IRQHandler
-USBDC_IRQHandler
-USBHC_IRQHandler
-CHLCD_IRQHandler
-FLEXRAY_IRQHandler
-CAN_IRQHandler
-LIN_IRQHandler
-I2C_IRQHandler
-CPU_CLCD_IRQHandler
-SPI_IRQHandler
-                B       .
-
-                ENDP
-
+                MEND
+
+
+; Default exception/interrupt handler
+
+                Set_Default_Handler  NMI_Handler
+                Set_Default_Handler  HardFault_Handler
+                Set_Default_Handler  MemManage_Handler
+                Set_Default_Handler  BusFault_Handler
+                Set_Default_Handler  UsageFault_Handler
+                Set_Default_Handler  SVC_Handler
+                Set_Default_Handler  DebugMon_Handler
+                Set_Default_Handler  PendSV_Handler
+                Set_Default_Handler  SysTick_Handler
+
+                Set_Default_Handler  Interrupt0_Handler
+                Set_Default_Handler  Interrupt1_Handler
+                Set_Default_Handler  Interrupt2_Handler
+                Set_Default_Handler  Interrupt3_Handler
+                Set_Default_Handler  Interrupt4_Handler
+                Set_Default_Handler  Interrupt5_Handler
+                Set_Default_Handler  Interrupt6_Handler
+                Set_Default_Handler  Interrupt7_Handler
+                Set_Default_Handler  Interrupt8_Handler
+                Set_Default_Handler  Interrupt9_Handler
 
                 ALIGN
 
 
-; User Initial Stack & Heap
-
-                IF      :DEF:__MICROLIB
-
-                EXPORT  __initial_sp
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-
-                ELSE
-
-                IMPORT  __use_two_region_memory
-                EXPORT  __user_initial_stackheap
-
-__user_initial_stackheap PROC
-                LDR     R0, =  Heap_Mem
-                LDR     R1, =(Stack_Mem + Stack_Size)
-                LDR     R2, = (Heap_Mem +  Heap_Size)
-                LDR     R3, = Stack_Mem
-                BX      LR
-                ENDP
-
-                ALIGN
+; User setup Stack & Heap
 
+                EXPORT   __stack_limit
+                EXPORT   __initial_sp
+                IF       Heap_Size != 0                      ; Heap is provided
+                EXPORT   __heap_base
+                EXPORT   __heap_limit
                 ENDIF
 
-
                 END

CMSIS/CoreValidation/Tests/Cortex-M3/AC5/RTE/Device/ARMCM3/system_ARMCM3.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
  * @file     system_ARMCM3.c
  * @brief    CMSIS Device System Source File for
- *           ARMCM3 Device Series
- * @version  V5.00
- * @date     07. September 2016
+ *           ARMCM3 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -28,9 +28,9 @@
 /*----------------------------------------------------------------------------
   Define clocks
  *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+#define  XTAL            (50000000UL)     /* Oscillator frequency */
 
-#define  SYSTEM_CLOCK    (5U * XTAL)
+#define  SYSTEM_CLOCK    (XTAL / 2U)
 
 
 /*----------------------------------------------------------------------------
@@ -43,7 +43,7 @@
 /*----------------------------------------------------------------------------
   System Core Clock Variable
  *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */
 
 
 /*----------------------------------------------------------------------------

CMSIS/CoreValidation/Tests/Cortex-M3/AC6/RTE/Device/ARMCM3/startup_ARMCM3.s

@@ -1,12 +1,12 @@
 ;/**************************************************************************//**
 ; * @file     startup_ARMCM3.s
 ; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM3 Device Series
-; * @version  V5.00
-; * @date     02. March 2016
+; *           ARMCM3 Device
+; * @version  V5.3.1
+; * @date     09. July 2018
 ; ******************************************************************************/
 ;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
 ; *
 ; * SPDX-License-Identifier: Apache-2.0
 ; *
@@ -23,32 +23,33 @@
 ; * limitations under the License.
 ; */
 
-;/*
 ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
 
 
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Stack Configuration
+;  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
 
-Stack_Size      EQU     0x00000400
+Stack_Size      EQU      0x00000400
 
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
+                AREA     STACK, NOINIT, READWRITE, ALIGN=3
+__stack_limit
+Stack_Mem       SPACE    Stack_Size
 __initial_sp
 
 
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Heap Configuration
+;  <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
 
-Heap_Size       EQU     0x00000C00
+Heap_Size       EQU      0x00000C00
 
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+                IF       Heap_Size != 0                      ; Heap is provided
+                AREA     HEAP, NOINIT, READWRITE, ALIGN=3
 __heap_base
-Heap_Mem        SPACE   Heap_Size
+Heap_Mem        SPACE    Heap_Size
 __heap_limit
+                ENDIF
 
 
                 PRESERVE8
@@ -57,206 +58,106 @@ __heap_limit
 
 ; Vector Table Mapped to Address 0 at Reset
 
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
-                DCD     RTC_IRQHandler            ;  1:  Real Time Clock
-                DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
-                DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
-                DCD     MCIA_IRQHandler           ;  4:  MCIa
-                DCD     MCIB_IRQHandler           ;  5:  MCIb
-                DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
-                DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
-                DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
-                DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
-                DCD     AACI_IRQHandler           ; 10: AACI / AC97
-                DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
-                DCD     ENET_IRQHandler           ; 12: Ethernet
-                DCD     USBDC_IRQHandler          ; 13: USB Device
-                DCD     USBHC_IRQHandler          ; 14: USB Host Controller
-                DCD     CHLCD_IRQHandler          ; 15: Character LCD
-                DCD     FLEXRAY_IRQHandler        ; 16: Flexray
-                DCD     CAN_IRQHandler            ; 17: CAN
-                DCD     LIN_IRQHandler            ; 18: LIN
-                DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
-                DCD     0                         ; 20: Reserved
-                DCD     0                         ; 21: Reserved
-                DCD     0                         ; 22: Reserved
-                DCD     0                         ; 23: Reserved
-                DCD     0                         ; 24: Reserved
-                DCD     0                         ; 25: Reserved
-                DCD     0                         ; 26: Reserved
-                DCD     0                         ; 27: Reserved
-                DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
-                DCD     0                         ; 29: Reserved - CPU FPGA
-                DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
-                DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
+                AREA     RESET, DATA, READONLY
+                EXPORT   __Vectors
+                EXPORT   __Vectors_End
+                EXPORT   __Vectors_Size
+
+__Vectors       DCD      __initial_sp                        ;     Top of Stack
+                DCD      Reset_Handler                       ;     Reset Handler
+                DCD      NMI_Handler                         ; -14 NMI Handler
+                DCD      HardFault_Handler                   ; -13 Hard Fault Handler
+                DCD      MemManage_Handler                   ; -12 MPU Fault Handler
+                DCD      BusFault_Handler                    ; -11 Bus Fault Handler
+                DCD      UsageFault_Handler                  ; -10 Usage Fault Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      SVC_Handler                         ;  -5 SVCall Handler
+                DCD      DebugMon_Handler                    ;  -4 Debug Monitor Handler
+                DCD      0                                   ;     Reserved
+                DCD      PendSV_Handler                      ;  -2 PendSV Handler
+                DCD      SysTick_Handler                     ;  -1 SysTick Handler
+
+                ; Interrupts
+                DCD      Interrupt0_Handler                  ;   0 Interrupt 0
+                DCD      Interrupt1_Handler                  ;   1 Interrupt 1
+                DCD      Interrupt2_Handler                  ;   2 Interrupt 2
+                DCD      Interrupt3_Handler                  ;   3 Interrupt 3
+                DCD      Interrupt4_Handler                  ;   4 Interrupt 4
+                DCD      Interrupt5_Handler                  ;   5 Interrupt 5
+                DCD      Interrupt6_Handler                  ;   6 Interrupt 6
+                DCD      Interrupt7_Handler                  ;   7 Interrupt 7
+                DCD      Interrupt8_Handler                  ;   8 Interrupt 8
+                DCD      Interrupt9_Handler                  ;   9 Interrupt 9
+
+                SPACE    (214 * 4)                           ; Interrupts 10 .. 224 are left out
 __Vectors_End
+__Vectors_Size  EQU      __Vectors_End - __Vectors
 
-__Vectors_Size  EQU     __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
 
+                AREA     |.text|, CODE, READONLY
 
 ; Reset Handler
 
 Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  SystemInit
-                IMPORT  __main
-                LDR     R0, =SystemInit
-                BLX     R0
-                LDR     R0, =__main
-                BX      R0
+                EXPORT   Reset_Handler             [WEAK]
+                IMPORT   SystemInit
+                IMPORT   __main
+
+                LDR      R0, =SystemInit
+                BLX      R0
+                LDR      R0, =__main
+                BX       R0
                 ENDP
 
 
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler               [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler         [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler          [WEAK]
-                B       .
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+                MACRO
+                Set_Default_Handler  $Handler_Name
+$Handler_Name   PROC
+                EXPORT   $Handler_Name             [WEAK]
+                B        .
                 ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler        [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler          [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WDT_IRQHandler            [WEAK]
-                EXPORT  RTC_IRQHandler            [WEAK]
-                EXPORT  TIM0_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler           [WEAK]
-                EXPORT  MCIA_IRQHandler           [WEAK]
-                EXPORT  MCIB_IRQHandler           [WEAK]
-                EXPORT  UART0_IRQHandler          [WEAK]
-                EXPORT  UART1_IRQHandler          [WEAK]
-                EXPORT  UART2_IRQHandler          [WEAK]
-                EXPORT  UART3_IRQHandler          [WEAK]
-                EXPORT  UART4_IRQHandler          [WEAK]
-                EXPORT  AACI_IRQHandler           [WEAK]
-                EXPORT  CLCD_IRQHandler           [WEAK]
-                EXPORT  ENET_IRQHandler           [WEAK]
-                EXPORT  USBDC_IRQHandler          [WEAK]
-                EXPORT  USBHC_IRQHandler          [WEAK]
-                EXPORT  CHLCD_IRQHandler          [WEAK]
-                EXPORT  FLEXRAY_IRQHandler        [WEAK]
-                EXPORT  CAN_IRQHandler            [WEAK]
-                EXPORT  LIN_IRQHandler            [WEAK]
-                EXPORT  I2C_IRQHandler            [WEAK]
-                EXPORT  CPU_CLCD_IRQHandler       [WEAK]
-                EXPORT  SPI_IRQHandler            [WEAK]
-
-WDT_IRQHandler
-RTC_IRQHandler
-TIM0_IRQHandler
-TIM2_IRQHandler
-MCIA_IRQHandler
-MCIB_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-UART3_IRQHandler
-UART4_IRQHandler
-AACI_IRQHandler
-CLCD_IRQHandler
-ENET_IRQHandler
-USBDC_IRQHandler
-USBHC_IRQHandler
-CHLCD_IRQHandler
-FLEXRAY_IRQHandler
-CAN_IRQHandler
-LIN_IRQHandler
-I2C_IRQHandler
-CPU_CLCD_IRQHandler
-SPI_IRQHandler
-                B       .
-
-                ENDP
-
+                MEND
+
+
+; Default exception/interrupt handler
+
+                Set_Default_Handler  NMI_Handler
+                Set_Default_Handler  HardFault_Handler
+                Set_Default_Handler  MemManage_Handler
+                Set_Default_Handler  BusFault_Handler
+                Set_Default_Handler  UsageFault_Handler
+                Set_Default_Handler  SVC_Handler
+                Set_Default_Handler  DebugMon_Handler
+                Set_Default_Handler  PendSV_Handler
+                Set_Default_Handler  SysTick_Handler
+
+                Set_Default_Handler  Interrupt0_Handler
+                Set_Default_Handler  Interrupt1_Handler
+                Set_Default_Handler  Interrupt2_Handler
+                Set_Default_Handler  Interrupt3_Handler
+                Set_Default_Handler  Interrupt4_Handler
+                Set_Default_Handler  Interrupt5_Handler
+                Set_Default_Handler  Interrupt6_Handler
+                Set_Default_Handler  Interrupt7_Handler
+                Set_Default_Handler  Interrupt8_Handler
+                Set_Default_Handler  Interrupt9_Handler
 
                 ALIGN
 
 
-; User Initial Stack & Heap
-
-                IF      :DEF:__MICROLIB
-
-                EXPORT  __initial_sp
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-
-                ELSE
-
-                IMPORT  __use_two_region_memory
-                EXPORT  __user_initial_stackheap
-
-__user_initial_stackheap PROC
-                LDR     R0, =  Heap_Mem
-                LDR     R1, =(Stack_Mem + Stack_Size)
-                LDR     R2, = (Heap_Mem +  Heap_Size)
-                LDR     R3, = Stack_Mem
-                BX      LR
-                ENDP
-
-                ALIGN
+; User setup Stack & Heap
 
+                EXPORT   __stack_limit
+                EXPORT   __initial_sp
+                IF       Heap_Size != 0                      ; Heap is provided
+                EXPORT   __heap_base
+                EXPORT   __heap_limit
                 ENDIF
 
-
                 END

CMSIS/CoreValidation/Tests/Cortex-M3/AC6/RTE/Device/ARMCM3/system_ARMCM3.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
  * @file     system_ARMCM3.c
  * @brief    CMSIS Device System Source File for
- *           ARMCM3 Device Series
- * @version  V5.00
- * @date     07. September 2016
+ *           ARMCM3 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -28,9 +28,9 @@
 /*----------------------------------------------------------------------------
   Define clocks
  *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+#define  XTAL            (50000000UL)     /* Oscillator frequency */
 
-#define  SYSTEM_CLOCK    (5U * XTAL)
+#define  SYSTEM_CLOCK    (XTAL / 2U)
 
 
 /*----------------------------------------------------------------------------
@@ -43,7 +43,7 @@
 /*----------------------------------------------------------------------------
   System Core Clock Variable
  *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */
 
 
 /*----------------------------------------------------------------------------

CMSIS/CoreValidation/Tests/Cortex-M3/GCC/RTE/Device/ARMCM3/startup_ARMCM3.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
- * @file     startup_ARMCM3.s
+ * @file     startup_ARMCM3.c
  * @brief    CMSIS Core Device Startup File for
- *           ARMCM3 Device Series
- * @version  V5.00
- * @date     26. April 2016
+ *           ARMCM3 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -23,6 +23,10 @@
  * limitations under the License.
  */
 
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
 #include <stdint.h>
 
 
@@ -40,6 +44,7 @@ extern uint32_t __bss_start__;
 extern uint32_t __bss_end__;
 extern uint32_t __StackTop;
 
+
 /*----------------------------------------------------------------------------
   Exception / Interrupt Handler Function Prototype
  *----------------------------------------------------------------------------*/
@@ -49,35 +54,30 @@ typedef void( *pFunc )( void );
 /*----------------------------------------------------------------------------
   External References
  *----------------------------------------------------------------------------*/
-#ifndef __START
-extern void  _start(void) __attribute__((noreturn));    /* PreeMain (C library entry point) */
-#else
-extern int  __START(void) __attribute__((noreturn));    /* main entry point */
-#endif
-
-#ifndef __NO_SYSTEM_INIT
-extern void SystemInit (void);            /* CMSIS System Initialization      */
-#endif
+extern void _start     (void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
+extern void SystemInit (void);                           /* CMSIS System Initialization */
 
 
 /*----------------------------------------------------------------------------
   Internal References
  *----------------------------------------------------------------------------*/
-void Default_Handler(void);                          /* Default empty handler */
-void Reset_Handler(void);                            /* Reset Handler */
+void Default_Handler(void) __attribute__ ((noreturn));
+void Reset_Handler  (void) __attribute__ ((noreturn));
 
 
 /*----------------------------------------------------------------------------
   User Initial Stack & Heap
  *----------------------------------------------------------------------------*/
-#ifndef __STACK_SIZE
-  #define	__STACK_SIZE  0x00000400
-#endif
+//<h> Stack Configuration
+//  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//</h>
+#define  __STACK_SIZE  0x00000400
 static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack")));
 
-#ifndef __HEAP_SIZE
-  #define	__HEAP_SIZE   0x00000C00
-#endif
+//<h> Heap Configuration
+//  <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//</h>
+#define  __HEAP_SIZE   0x00000C00
 #if __HEAP_SIZE > 0
 static uint8_t heap[__HEAP_SIZE]   __attribute__ ((aligned(8), used, section(".heap")));
 #endif
@@ -86,98 +86,63 @@ static uint8_t heap[__HEAP_SIZE]   __attribute__ ((aligned(8), used, section(".h
 /*----------------------------------------------------------------------------
   Exception / Interrupt Handler
  *----------------------------------------------------------------------------*/
-/* Cortex-M3 Processor Exceptions */
-void NMI_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
-void HardFault_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
-void MemManage_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
-void BusFault_Handler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UsageFault_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
-void SVC_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
-void DebugMon_Handler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void PendSV_Handler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void SysTick_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
-
-/* ARMCM3 Specific Interrupts */
-void WDT_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void RTC_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM0_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM2_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIA_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIB_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART0_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART1_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART2_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART4_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void AACI_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void CLCD_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void ENET_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBDC_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBHC_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void CHLCD_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void FLEXRAY_IRQHandler  (void) __attribute__ ((weak, alias("Default_Handler")));
-void CAN_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void LIN_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void I2C_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void CPU_CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART3_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void SPI_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+/* Exceptions */
+void NMI_Handler            (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void MemManage_Handler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler       (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler            (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler       (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler        (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
 
 
 /*----------------------------------------------------------------------------
   Exception / Interrupt Vector table
  *----------------------------------------------------------------------------*/
-const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = {
-  /* Cortex-M3 Exceptions Handler */
-  (pFunc)((uint32_t)&__StackTop),           /*      Initial Stack Pointer     */
-  Reset_Handler,                            /*      Reset Handler             */
-  NMI_Handler,                              /*      NMI Handler               */
-  HardFault_Handler,                        /*      Hard Fault Handler        */
-  MemManage_Handler,                        /*      MPU Fault Handler         */
-  BusFault_Handler,                         /*      Bus Fault Handler         */
-  UsageFault_Handler,                       /*      Usage Fault Handler       */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  SVC_Handler,                              /*      SVCall Handler            */
-  DebugMon_Handler,                         /*      Debug Monitor Handler     */
-  0,                                        /*      Reserved                  */
-  PendSV_Handler,                           /*      PendSV Handler            */
-  SysTick_Handler,                          /*      SysTick Handler           */
-
-  /* External interrupts */
-  WDT_IRQHandler,                           /*  0:  Watchdog Timer            */
-  RTC_IRQHandler,                           /*  1:  Real Time Clock           */
-  TIM0_IRQHandler,                          /*  2:  Timer0 / Timer1           */
-  TIM2_IRQHandler,                          /*  3:  Timer2 / Timer3           */
-  MCIA_IRQHandler,                          /*  4:  MCIa                      */
-  MCIB_IRQHandler,                          /*  5:  MCIb                      */
-  UART0_IRQHandler,                         /*  6:  UART0 - DUT FPGA          */
-  UART1_IRQHandler,                         /*  7:  UART1 - DUT FPGA          */
-  UART2_IRQHandler,                         /*  8:  UART2 - DUT FPGA          */
-  UART4_IRQHandler,                         /*  9:  UART4 - not connected     */
-  AACI_IRQHandler,                          /* 10: AACI / AC97                */
-  CLCD_IRQHandler,                          /* 11: CLCD Combined Interrupt    */
-  ENET_IRQHandler,                          /* 12: Ethernet                   */
-  USBDC_IRQHandler,                         /* 13: USB Device                 */
-  USBHC_IRQHandler,                         /* 14: USB Host Controller        */
-  CHLCD_IRQHandler,                         /* 15: Character LCD              */
-  FLEXRAY_IRQHandler,                       /* 16: Flexray                    */
-  CAN_IRQHandler,                           /* 17: CAN                        */
-  LIN_IRQHandler,                           /* 18: LIN                        */
-  I2C_IRQHandler,                           /* 19: I2C ADC/DAC                */
-  0,                                        /* 20: Reserved                   */
-  0,                                        /* 21: Reserved                   */
-  0,                                        /* 22: Reserved                   */
-  0,                                        /* 23: Reserved                   */
-  0,                                        /* 24: Reserved                   */
-  0,                                        /* 25: Reserved                   */
-  0,                                        /* 26: Reserved                   */
-  0,                                        /* 27: Reserved                   */
-  CPU_CLCD_IRQHandler,                      /* 28: Reserved - CPU FPGA CLCD   */
-  0,                                        /* 29: Reserved - CPU FPGA        */
-  UART3_IRQHandler,                         /* 30: UART3    - CPU FPGA        */
-  SPI_IRQHandler                            /* 31: SPI Touchscreen - CPU FPGA */
+extern const pFunc __Vectors[240];
+       const pFunc __Vectors[240] __attribute__ ((section(".vectors"))) = {
+  (pFunc)(&__StackTop),                     /*     Initial Stack Pointer */
+  Reset_Handler,                            /*     Reset Handler */
+  NMI_Handler,                              /* -14 NMI Handler */
+  HardFault_Handler,                        /* -13 Hard Fault Handler */
+  MemManage_Handler,                        /* -12 MPU Fault Handler */
+  BusFault_Handler,                         /* -11 Bus Fault Handler */
+  UsageFault_Handler,                       /* -10 Usage Fault Handler */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  SVC_Handler,                              /*  -5 SVCall Handler */
+  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */
+  0,                                        /*     Reserved */
+  PendSV_Handler,                           /*  -2 PendSV Handler */
+  SysTick_Handler,                          /*  -1 SysTick Handler */
+
+  /* Interrupts */
+  Interrupt0_Handler,                       /*   0 Interrupt 0 */
+  Interrupt1_Handler,                       /*   1 Interrupt 1 */
+  Interrupt2_Handler,                       /*   2 Interrupt 2 */
+  Interrupt3_Handler,                       /*   3 Interrupt 3 */
+  Interrupt4_Handler,                       /*   4 Interrupt 4 */
+  Interrupt5_Handler,                       /*   5 Interrupt 5 */
+  Interrupt6_Handler,                       /*   6 Interrupt 6 */
+  Interrupt7_Handler,                       /*   7 Interrupt 7 */
+  Interrupt8_Handler,                       /*   8 Interrupt 8 */
+  Interrupt9_Handler                        /*   9 Interrupt 9 */
+                                            /* Interrupts 10 .. 224 are left out */
 };
 
 
@@ -188,41 +153,42 @@ void Reset_Handler(void) {
   uint32_t *pSrc, *pDest;
   uint32_t *pTable __attribute__((unused));
 
-/*  Firstly it copies data from read only memory to RAM. There are two schemes
- *  to copy. One can copy more than one sections. Another can only copy
- *  one section.  The former scheme needs more instructions and read-only
- *  data to implement than the latter.
- *  Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.  */
+/* Firstly it copies data from read only memory to RAM.
+ * There are two schemes to copy. One can copy more than one sections.
+ * Another can copy only one section. The former scheme needs more
+ * instructions and read-only data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.
+ */
 
 #ifdef __STARTUP_COPY_MULTIPLE
-/*  Multiple sections scheme.
+/* Multiple sections scheme.
  *
- *  Between symbol address __copy_table_start__ and __copy_table_end__,
- *  there are array of triplets, each of which specify:
- *    offset 0: LMA of start of a section to copy from
- *    offset 4: VMA of start of a section to copy to
- *    offset 8: size of the section to copy. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ *   offset 0: LMA of start of a section to copy from
+ *   offset 4: VMA of start of a section to copy to
+ *   offset 8: size of the section to copy. Must be multiply of 4
  *
- *  All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
  */
   pTable = &__copy_table_start__;
 
   for (; pTable < &__copy_table_end__; pTable = pTable + 3) {
-		pSrc  = (uint32_t*)*(pTable + 0);
-		pDest = (uint32_t*)*(pTable + 1);
-		for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
+    pSrc  = (uint32_t*)*(pTable + 0);
+    pDest = (uint32_t*)*(pTable + 1);
+    for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
       *pDest++ = *pSrc++;
-		}
-	}
+    }
+  }
 #else
-/*  Single section scheme.
+/* Single section scheme.
  *
- *  The ranges of copy from/to are specified by following symbols
- *    __etext: LMA of start of the section to copy from. Usually end of text
- *    __data_start__: VMA of start of the section to copy to
- *    __data_end__: VMA of end of the section to copy to
+ * The ranges of copy from/to are specified by following symbols
+ *   __etext: LMA of start of the section to copy from. Usually end of text
+ *   __data_start__: VMA of start of the section to copy to
+ *   __data_end__: VMA of end of the section to copy to
  *
- *  All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
  */
   pSrc  = &__etext;
   pDest = &__data_start__;
@@ -232,40 +198,40 @@ void Reset_Handler(void) {
   }
 #endif /*__STARTUP_COPY_MULTIPLE */
 
-/*  This part of work usually is done in C library startup code. Otherwise,
- *  define this macro to enable it in this startup.
+/* This part of work usually is done in C library startup code.
+ * Otherwise, define this macro to enable it in this startup.
  *
- *  There are two schemes too. One can clear multiple BSS sections. Another
- *  can only clear one section. The former is more size expensive than the
- *  latter.
+ * There are two schemes too.
+ * One can clear multiple BSS sections. Another can only clear one section.
+ * The former is more size expensive than the latter.
  *
- *  Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- *  Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
  */
 #ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/*  Multiple sections scheme.
+/* Multiple sections scheme.
  *
- *  Between symbol address __copy_table_start__ and __copy_table_end__,
- *  there are array of tuples specifying:
- *    offset 0: Start of a BSS section
- *    offset 4: Size of this BSS section. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ *   offset 0: Start of a BSS section
+ *   offset 4: Size of this BSS section. Must be multiply of 4
  */
   pTable = &__zero_table_start__;
 
   for (; pTable < &__zero_table_end__; pTable = pTable + 2) {
-		pDest = (uint32_t*)*(pTable + 0);
-		for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
+    pDest = (uint32_t*)*(pTable + 0);
+    for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
       *pDest++ = 0;
-		}
-	}
+    }
+  }
 #elif defined (__STARTUP_CLEAR_BSS)
-/*  Single BSS section scheme.
+/* Single BSS section scheme.
  *
- *  The BSS section is specified by following symbols
- *    __bss_start__: start of the BSS section.
- *    __bss_end__: end of the BSS section.
+ * The BSS section is specified by following symbols
+ *   __bss_start__: start of the BSS section.
+ *   __bss_end__: end of the BSS section.
  *
- *  Both addresses must be aligned to 4 bytes boundary.
+ * Both addresses must be aligned to 4 bytes boundary.
  */
   pDest = &__bss_start__;
 
@@ -274,15 +240,8 @@ void Reset_Handler(void) {
   }
 #endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
 
-#ifndef __NO_SYSTEM_INIT
-	SystemInit();
-#endif
-
-#ifndef __START
-#define __START _start
-#endif
-	__START();
-
+  SystemInit();                             /* CMSIS System Initialization */
+  _start();                                 /* Enter PreeMain (C library entry point) */
 }
 
 
@@ -291,5 +250,5 @@ void Reset_Handler(void) {
  *----------------------------------------------------------------------------*/
 void Default_Handler(void) {
 
-	while(1);
+  while(1);
 }

CMSIS/CoreValidation/Tests/Cortex-M3/GCC/RTE/Device/ARMCM3/system_ARMCM3.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
  * @file     system_ARMCM3.c
  * @brief    CMSIS Device System Source File for
- *           ARMCM3 Device Series
- * @version  V5.00
- * @date     07. September 2016
+ *           ARMCM3 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -28,9 +28,9 @@
 /*----------------------------------------------------------------------------
   Define clocks
  *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+#define  XTAL            (50000000UL)     /* Oscillator frequency */
 
-#define  SYSTEM_CLOCK    (5U * XTAL)
+#define  SYSTEM_CLOCK    (XTAL / 2U)
 
 
 /*----------------------------------------------------------------------------
@@ -43,7 +43,7 @@
 /*----------------------------------------------------------------------------
   System Core Clock Variable
  *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */
 
 
 /*----------------------------------------------------------------------------

CMSIS/CoreValidation/Tests/Cortex-M3/IAR/RTE/Device/ARMCM3/startup_ARMCM3.s

@@ -1,12 +1,12 @@
 ;/**************************************************************************//**
 ; * @file     startup_ARMCM3.s
 ; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM3 Device Series
-; * @version  V5.00
-; * @date     08. March 2016
+; *           ARMCM3 Device
+; * @version  V5.3.1
+; * @date     09. July 2018
 ; ******************************************************************************/
 ;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
 ; *
 ; * SPDX-License-Identifier: Apache-2.0
 ; *
@@ -39,254 +39,117 @@
 ; Cortex-M version
 ;
 
-        MODULE  ?cstartup
+                MODULE   ?cstartup
 
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
+                ;; Forward declaration of sections.
+                SECTION  CSTACK:DATA:NOROOT(3)
 
-        SECTION .intvec:CODE:NOROOT(2)
+                SECTION  .intvec:CODE:NOROOT(2)
 
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit
-        PUBLIC  __vector_table
-        PUBLIC  __vector_table_0x1c
-        PUBLIC  __Vectors
-        PUBLIC  __Vectors_End
-        PUBLIC  __Vectors_Size
+                EXTERN   __iar_program_start
+                EXTERN   SystemInit
+                PUBLIC   __vector_table
+                PUBLIC   __vector_table_0x1c
+                PUBLIC   __Vectors
+                PUBLIC   __Vectors_End
+                PUBLIC   __Vectors_Size
 
-        DATA
+                DATA
 
 __vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler
-
-        DCD     NMI_Handler
-        DCD     HardFault_Handler
-        DCD     MemManage_Handler
-        DCD     BusFault_Handler
-        DCD     UsageFault_Handler
+                DCD      sfe(CSTACK)                         ;     Top of Stack
+                DCD      Reset_Handler                       ;     Reset Handler
+                DCD      NMI_Handler                         ; -14 NMI Handler
+                DCD      HardFault_Handler                   ; -13 Hard Fault Handler
+                DCD      MemManage_Handler                   ; -12 MPU Fault Handler
+                DCD      BusFault_Handler                    ; -11 Bus Fault Handler
+                DCD      UsageFault_Handler                  ; -10 Usage Fault Handler
 __vector_table_0x1c
-        DCD     0
-        DCD     0
-        DCD     0
-        DCD     0
-        DCD     SVC_Handler
-        DCD     DebugMon_Handler
-        DCD     0
-        DCD     PendSV_Handler
-        DCD     SysTick_Handler
-
-        ; External Interrupts
-        DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
-        DCD     RTC_IRQHandler            ;  1:  Real Time Clock
-        DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
-        DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
-        DCD     MCIA_IRQHandler           ;  4:  MCIa
-        DCD     MCIB_IRQHandler           ;  5:  MCIb
-        DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
-        DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
-        DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
-        DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
-        DCD     AACI_IRQHandler           ; 10: AACI / AC97
-        DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
-        DCD     ENET_IRQHandler           ; 12: Ethernet
-        DCD     USBDC_IRQHandler          ; 13: USB Device
-        DCD     USBHC_IRQHandler          ; 14: USB Host Controller
-        DCD     CHLCD_IRQHandler          ; 15: Character LCD
-        DCD     FLEXRAY_IRQHandler        ; 16: Flexray
-        DCD     CAN_IRQHandler            ; 17: CAN
-        DCD     LIN_IRQHandler            ; 18: LIN
-        DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
-        DCD     0                         ; 20: Reserved
-        DCD     0                         ; 21: Reserved
-        DCD     0                         ; 22: Reserved
-        DCD     0                         ; 23: Reserved
-        DCD     0                         ; 24: Reserved
-        DCD     0                         ; 25: Reserved
-        DCD     0                         ; 26: Reserved
-        DCD     0                         ; 27: Reserved
-        DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
-        DCD     0                         ; 29: Reserved - CPU FPGA
-        DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
-        DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      SVC_Handler                         ;  -5 SVCall Handler
+                DCD      DebugMon_Handler                    ;  -4 Debug Monitor Handler
+                DCD      0                                   ;     Reserved
+                DCD      PendSV_Handler                      ;  -2 PendSV Handler
+                DCD      SysTick_Handler                     ;  -1 SysTick Handler
+
+                ; Interrupts
+                DCD      Interrupt0_Handler                  ;   0 Interrupt 0
+                DCD      Interrupt1_Handler                  ;   1 Interrupt 1
+                DCD      Interrupt2_Handler                  ;   2 Interrupt 2
+                DCD      Interrupt3_Handler                  ;   3 Interrupt 3
+                DCD      Interrupt4_Handler                  ;   4 Interrupt 4
+                DCD      Interrupt5_Handler                  ;   5 Interrupt 5
+                DCD      Interrupt6_Handler                  ;   6 Interrupt 6
+                DCD      Interrupt7_Handler                  ;   7 Interrupt 7
+                DCD      Interrupt8_Handler                  ;   8 Interrupt 8
+                DCD      Interrupt9_Handler                  ;   9 Interrupt 9
+
+                DS32    (214)                                ; Interrupts 10 .. 224 are left out
 __Vectors_End
 
-__Vectors       EQU   __vector_table
-__Vectors_Size  EQU   __Vectors_End - __Vectors
+__Vectors       EQU      __vector_table
+__Vectors_Size  EQU      __Vectors_End - __Vectors
 
 
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
+                THUMB
 
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
+; Reset Handler
 
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
+                PUBWEAK  Reset_Handler
+                SECTION  .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+                LDR      R0, =SystemInit
+                BLX      R0
+                LDR      R0, =__iar_program_start
+                BX       R0
+
+
+                PUBWEAK NMI_Handler
+                PUBWEAK HardFault_Handler
+                PUBWEAK MemManage_Handler
+                PUBWEAK BusFault_Handler
+                PUBWEAK UsageFault_Handler
+                PUBWEAK SVC_Handler
+                PUBWEAK DebugMon_Handler
+                PUBWEAK PendSV_Handler
+                PUBWEAK SysTick_Handler
+
+                PUBWEAK Interrupt0_Handler
+                PUBWEAK Interrupt1_Handler
+                PUBWEAK Interrupt2_Handler
+                PUBWEAK Interrupt3_Handler
+                PUBWEAK Interrupt4_Handler
+                PUBWEAK Interrupt5_Handler
+                PUBWEAK Interrupt6_Handler
+                PUBWEAK Interrupt7_Handler
+                PUBWEAK Interrupt8_Handler
+                PUBWEAK Interrupt9_Handler
+                SECTION .text:CODE:REORDER:NOROOT(1)
 NMI_Handler
-        B NMI_Handler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 HardFault_Handler
-        B HardFault_Handler
-
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 MemManage_Handler
-        B MemManage_Handler
-
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 BusFault_Handler
-        B BusFault_Handler
-
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 UsageFault_Handler
-        B UsageFault_Handler
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 SVC_Handler
-        B SVC_Handler
-
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 DebugMon_Handler
-        B DebugMon_Handler
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 SysTick_Handler
-        B SysTick_Handler
-
-        PUBWEAK WDT_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WDT_IRQHandler
-        B WDT_IRQHandler
-
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-
-        PUBWEAK TIM0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM0_IRQHandler
-        B TIM0_IRQHandler
-
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-
-        PUBWEAK MCIA_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MCIA_IRQHandler
-        B MCIA_IRQHandler
-
-        PUBWEAK MCIB_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MCIB_IRQHandler
-        B MCIB_IRQHandler
-
-        PUBWEAK UART0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART0_IRQHandler
-        B UART0_IRQHandler
-
-        PUBWEAK UART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART1_IRQHandler
-        B UART1_IRQHandler
-
-        PUBWEAK UART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART2_IRQHandler
-        B UART2_IRQHandler
-
-        PUBWEAK UART4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
-        B UART4_IRQHandler
-
-        PUBWEAK AACI_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-AACI_IRQHandler
-        B AACI_IRQHandler
-
-        PUBWEAK CLCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CLCD_IRQHandler
-        B CLCD_IRQHandler
-
-        PUBWEAK ENET_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ENET_IRQHandler
-        B ENET_IRQHandler
-
-        PUBWEAK USBDC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USBDC_IRQHandler
-        B USBDC_IRQHandler
-
-        PUBWEAK USBHC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USBHC_IRQHandler
-        B USBHC_IRQHandler
-
-        PUBWEAK CHLCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CHLCD_IRQHandler
-        B CHLCD_IRQHandler
-
-        PUBWEAK FLEXRAY_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLEXRAY_IRQHandler
-        B FLEXRAY_IRQHandler
-
-        PUBWEAK CAN_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN_IRQHandler
-        B CAN_IRQHandler
-
-        PUBWEAK LIN_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-LIN_IRQHandler
-        B LIN_IRQHandler
-
-        PUBWEAK I2C_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C_IRQHandler
-        B I2C_IRQHandler
-
-        PUBWEAK CPU_CLCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CPU_CLCD_IRQHandler
-        B CPU_CLCD_IRQHandler
-
-        PUBWEAK UART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART3_IRQHandler
-        B UART3_IRQHandler
-
-        PUBWEAK SPI_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI_IRQHandler
-        B SPI_IRQHandler
 
-        END
+Interrupt0_Handler
+Interrupt1_Handler
+Interrupt2_Handler
+Interrupt3_Handler
+Interrupt4_Handler
+Interrupt5_Handler
+Interrupt6_Handler
+Interrupt7_Handler
+Interrupt8_Handler
+Interrupt9_Handler
+Default_Handler
+                B        .
+
+
+                END

CMSIS/CoreValidation/Tests/Cortex-M3/IAR/RTE/Device/ARMCM3/system_ARMCM3.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
  * @file     system_ARMCM3.c
  * @brief    CMSIS Device System Source File for
- *           ARMCM3 Device Series
- * @version  V5.00
- * @date     07. September 2016
+ *           ARMCM3 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -28,9 +28,9 @@
 /*----------------------------------------------------------------------------
   Define clocks
  *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+#define  XTAL            (50000000UL)     /* Oscillator frequency */
 
-#define  SYSTEM_CLOCK    (5U * XTAL)
+#define  SYSTEM_CLOCK    (XTAL / 2U)
 
 
 /*----------------------------------------------------------------------------
@@ -43,7 +43,7 @@
 /*----------------------------------------------------------------------------
   System Core Clock Variable
  *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */
 
 
 /*----------------------------------------------------------------------------

CMSIS/CoreValidation/Tests/Cortex-M33/AC6/RTE/Device/ARMCM33/startup_ARMCM33.s

@@ -1,12 +1,12 @@
 ;/**************************************************************************//**
 ; * @file     startup_ARMCM33.s
 ; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM33 Device Series
-; * @version  V5.00
-; * @date     21. October 2016
+; *           ARMCM33 Device
+; * @version  V5.3.1
+; * @date     09. July 2018
 ; ******************************************************************************/
 ;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
 ; *
 ; * SPDX-License-Identifier: Apache-2.0
 ; *
@@ -23,32 +23,33 @@
 ; * limitations under the License.
 ; */
 
-;/*
 ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
 
 
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Stack Configuration
+;  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
 
-Stack_Size      EQU     0x00000400
+Stack_Size      EQU      0x00000400
 
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
+                AREA     STACK, NOINIT, READWRITE, ALIGN=3
+__stack_limit
+Stack_Mem       SPACE    Stack_Size
 __initial_sp
 
 
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Heap Configuration
+;  <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
 
-Heap_Size       EQU     0x00000C00
+Heap_Size       EQU      0x00000C00
 
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+                IF       Heap_Size != 0                      ; Heap is provided
+                AREA     HEAP, NOINIT, READWRITE, ALIGN=3
 __heap_base
-Heap_Mem        SPACE   Heap_Size
+Heap_Mem        SPACE    Heap_Size
 __heap_limit
+                ENDIF
 
 
                 PRESERVE8
@@ -57,211 +58,110 @@ __heap_limit
 
 ; Vector Table Mapped to Address 0 at Reset
 
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     SecureFault_Handler       ; Secure Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
-                DCD     RTC_IRQHandler            ;  1:  Real Time Clock
-                DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
-                DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
-                DCD     MCIA_IRQHandler           ;  4:  MCIa
-                DCD     MCIB_IRQHandler           ;  5:  MCIb
-                DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
-                DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
-                DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
-                DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
-                DCD     AACI_IRQHandler           ; 10: AACI / AC97
-                DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
-                DCD     ENET_IRQHandler           ; 12: Ethernet
-                DCD     USBDC_IRQHandler          ; 13: USB Device
-                DCD     USBHC_IRQHandler          ; 14: USB Host Controller
-                DCD     CHLCD_IRQHandler          ; 15: Character LCD
-                DCD     FLEXRAY_IRQHandler        ; 16: Flexray
-                DCD     CAN_IRQHandler            ; 17: CAN
-                DCD     LIN_IRQHandler            ; 18: LIN
-                DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
-                DCD     0                         ; 20: Reserved
-                DCD     0                         ; 21: Reserved
-                DCD     0                         ; 22: Reserved
-                DCD     0                         ; 23: Reserved
-                DCD     0                         ; 24: Reserved
-                DCD     0                         ; 25: Reserved
-                DCD     0                         ; 26: Reserved
-                DCD     0                         ; 27: Reserved
-                DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
-                DCD     0                         ; 29: Reserved - CPU FPGA
-                DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
-                DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
+                AREA     RESET, DATA, READONLY
+                EXPORT   __Vectors
+                EXPORT   __Vectors_End
+                EXPORT   __Vectors_Size
+
+__Vectors       DCD      __initial_sp                        ;     Top of Stack
+                DCD      Reset_Handler                       ;     Reset Handler
+                DCD      NMI_Handler                         ; -14 NMI Handler
+                DCD      HardFault_Handler                   ; -13 Hard Fault Handler
+                DCD      MemManage_Handler                   ; -12 MPU Fault Handler
+                DCD      BusFault_Handler                    ; -11 Bus Fault Handler
+                DCD      UsageFault_Handler                  ; -10 Usage Fault Handler
+                DCD      SecureFault_Handler                 ;  -9 Secure Fault Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      SVC_Handler                         ;  -5 SVCall Handler
+                DCD      DebugMon_Handler                    ;  -4 Debug Monitor Handler
+                DCD      0                                   ;     Reserved
+                DCD      PendSV_Handler                      ;  -2 PendSV Handler
+                DCD      SysTick_Handler                     ;  -1 SysTick Handler
+
+                ; Interrupts
+                DCD      Interrupt0_Handler                  ;   0 Interrupt 0
+                DCD      Interrupt1_Handler                  ;   1 Interrupt 1
+                DCD      Interrupt2_Handler                  ;   2 Interrupt 2
+                DCD      Interrupt3_Handler                  ;   3 Interrupt 3
+                DCD      Interrupt4_Handler                  ;   4 Interrupt 4
+                DCD      Interrupt5_Handler                  ;   5 Interrupt 5
+                DCD      Interrupt6_Handler                  ;   6 Interrupt 6
+                DCD      Interrupt7_Handler                  ;   7 Interrupt 7
+                DCD      Interrupt8_Handler                  ;   8 Interrupt 8
+                DCD      Interrupt9_Handler                  ;   9 Interrupt 9
+
+                SPACE    (470 * 4)                           ; Interrupts 10 .. 480 are left out
 __Vectors_End
+__Vectors_Size  EQU      __Vectors_End - __Vectors
 
-__Vectors_Size  EQU     __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
 
+                AREA     |.text|, CODE, READONLY
 
 ; Reset Handler
 
 Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  SystemInit
-                IMPORT  __main
-                LDR     R0, =SystemInit
-                BLX     R0
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-
+                EXPORT   Reset_Handler             [WEAK]
+                IMPORT   SystemInit
+                IMPORT   __main
 
-; Dummy Exception Handlers (infinite loops which can be modified)
+                LDR      R0, =__stack_limit
+                MSR      MSPLIM, R0                          ; Non-secure version of MSPLIM is RAZ/WI
 
-NMI_Handler     PROC
-                EXPORT  NMI_Handler               [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler         [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler          [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler        [WEAK]
-                B       .
-                ENDP
-SecureFault_Handler\
-                PROC
-                EXPORT  SecureFault_Handler       [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler          [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
+                LDR      R0, =SystemInit
+                BLX      R0
+                LDR      R0, =__main
+                BX       R0
                 ENDP
 
-Default_Handler PROC
-
-                EXPORT  WDT_IRQHandler            [WEAK]
-                EXPORT  RTC_IRQHandler            [WEAK]
-                EXPORT  TIM0_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler           [WEAK]
-                EXPORT  MCIA_IRQHandler           [WEAK]
-                EXPORT  MCIB_IRQHandler           [WEAK]
-                EXPORT  UART0_IRQHandler          [WEAK]
-                EXPORT  UART1_IRQHandler          [WEAK]
-                EXPORT  UART2_IRQHandler          [WEAK]
-                EXPORT  UART3_IRQHandler          [WEAK]
-                EXPORT  UART4_IRQHandler          [WEAK]
-                EXPORT  AACI_IRQHandler           [WEAK]
-                EXPORT  CLCD_IRQHandler           [WEAK]
-                EXPORT  ENET_IRQHandler           [WEAK]
-                EXPORT  USBDC_IRQHandler          [WEAK]
-                EXPORT  USBHC_IRQHandler          [WEAK]
-                EXPORT  CHLCD_IRQHandler          [WEAK]
-                EXPORT  FLEXRAY_IRQHandler        [WEAK]
-                EXPORT  CAN_IRQHandler            [WEAK]
-                EXPORT  LIN_IRQHandler            [WEAK]
-                EXPORT  I2C_IRQHandler            [WEAK]
-                EXPORT  CPU_CLCD_IRQHandler       [WEAK]
-                EXPORT  SPI_IRQHandler            [WEAK]
-
-WDT_IRQHandler
-RTC_IRQHandler
-TIM0_IRQHandler
-TIM2_IRQHandler
-MCIA_IRQHandler
-MCIB_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-UART3_IRQHandler
-UART4_IRQHandler
-AACI_IRQHandler
-CLCD_IRQHandler
-ENET_IRQHandler
-USBDC_IRQHandler
-USBHC_IRQHandler
-CHLCD_IRQHandler
-FLEXRAY_IRQHandler
-CAN_IRQHandler
-LIN_IRQHandler
-I2C_IRQHandler
-CPU_CLCD_IRQHandler
-SPI_IRQHandler
-                B       .
 
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+                MACRO
+                Set_Default_Handler  $Handler_Name
+$Handler_Name   PROC
+                EXPORT   $Handler_Name             [WEAK]
+                B        .
                 ENDP
-
+                MEND
+
+
+; Default exception/interrupt handler
+
+                Set_Default_Handler  NMI_Handler
+                Set_Default_Handler  HardFault_Handler
+                Set_Default_Handler  MemManage_Handler
+                Set_Default_Handler  BusFault_Handler
+                Set_Default_Handler  UsageFault_Handler
+                Set_Default_Handler  SecureFault_Handler
+                Set_Default_Handler  SVC_Handler
+                Set_Default_Handler  DebugMon_Handler
+                Set_Default_Handler  PendSV_Handler
+                Set_Default_Handler  SysTick_Handler
+
+                Set_Default_Handler  Interrupt0_Handler
+                Set_Default_Handler  Interrupt1_Handler
+                Set_Default_Handler  Interrupt2_Handler
+                Set_Default_Handler  Interrupt3_Handler
+                Set_Default_Handler  Interrupt4_Handler
+                Set_Default_Handler  Interrupt5_Handler
+                Set_Default_Handler  Interrupt6_Handler
+                Set_Default_Handler  Interrupt7_Handler
+                Set_Default_Handler  Interrupt8_Handler
+                Set_Default_Handler  Interrupt9_Handler
 
                 ALIGN
 
 
-; User Initial Stack & Heap
-
-                IF      :DEF:__MICROLIB
-
-                EXPORT  __initial_sp
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-
-                ELSE
-
-                IMPORT  __use_two_region_memory
-                EXPORT  __user_initial_stackheap
-
-__user_initial_stackheap PROC
-                LDR     R0, =  Heap_Mem
-                LDR     R1, =(Stack_Mem + Stack_Size)
-                LDR     R2, = (Heap_Mem +  Heap_Size)
-                LDR     R3, = Stack_Mem
-                BX      LR
-                ENDP
-
-                ALIGN
+; User setup Stack & Heap
 
+                EXPORT   __stack_limit
+                EXPORT   __initial_sp
+                IF       Heap_Size != 0                      ; Heap is provided
+                EXPORT   __heap_base
+                EXPORT   __heap_limit
                 ENDIF
 
-
                 END

CMSIS/CoreValidation/Tests/Cortex-M33/AC6/RTE/Device/ARMCM33/system_ARMCM33.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
  * @file     system_ARMCM33.c
  * @brief    CMSIS Device System Source File for
- *           ARMCM33 Device Series
- * @version  V5.00
- * @date     02. November 2016
+ *           ARMCM33 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -46,9 +46,9 @@
 /*----------------------------------------------------------------------------
   Define clocks
  *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+#define  XTAL            (50000000UL)     /* Oscillator frequency */
 
-#define  SYSTEM_CLOCK    (5U * XTAL)
+#define  SYSTEM_CLOCK    (XTAL / 2U)
 
 
 /*----------------------------------------------------------------------------
@@ -61,7 +61,7 @@
 /*----------------------------------------------------------------------------
   System Core Clock Variable
  *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */
 
 
 /*----------------------------------------------------------------------------

CMSIS/CoreValidation/Tests/Cortex-M33/GCC/RTE/Device/ARMCM33/startup_ARMCM33.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
- * @file     startup_ARMCM33.s
+ * @file     startup_ARMCM33.c
  * @brief    CMSIS Core Device Startup File for
- *           ARMCM33 Device Series
- * @version  V5.00
- * @date     21. October 2016
+ *           ARMCM33 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -23,6 +23,10 @@
  * limitations under the License.
  */
 
+/*
+ //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
 #include <stdint.h>
 
 
@@ -39,6 +43,7 @@ extern uint32_t __zero_table_end__;
 extern uint32_t __bss_start__;
 extern uint32_t __bss_end__;
 extern uint32_t __StackTop;
+extern uint32_t __StackLimit;
 
 /*----------------------------------------------------------------------------
   Exception / Interrupt Handler Function Prototype
@@ -49,35 +54,30 @@ typedef void( *pFunc )( void );
 /*----------------------------------------------------------------------------
   External References
  *----------------------------------------------------------------------------*/
-#ifndef __START
-extern void  _start(void) __attribute__((noreturn));    /* PreeMain (C library entry point) */
-#else
-extern int  __START(void) __attribute__((noreturn));    /* main entry point */
-#endif
-
-#ifndef __NO_SYSTEM_INIT
-extern void SystemInit (void);            /* CMSIS System Initialization      */
-#endif
+extern void _start     (void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
+extern void SystemInit (void);                           /* CMSIS System Initialization */
 
 
 /*----------------------------------------------------------------------------
   Internal References
  *----------------------------------------------------------------------------*/
-void Default_Handler(void);                          /* Default empty handler */
-void Reset_Handler(void);                            /* Reset Handler */
+void Default_Handler(void) __attribute__ ((noreturn));
+void Reset_Handler  (void) __attribute__ ((noreturn));
 
 
 /*----------------------------------------------------------------------------
   User Initial Stack & Heap
  *----------------------------------------------------------------------------*/
-#ifndef __STACK_SIZE
-  #define	__STACK_SIZE  0x00000400
-#endif
+//<h> Stack Configuration
+//  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//</h>
+#define  __STACK_SIZE  0x00000400
 static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack")));
 
-#ifndef __HEAP_SIZE
-  #define	__HEAP_SIZE   0x00000C00
-#endif
+//<h> Heap Configuration
+//  <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//</h>
+#define  __HEAP_SIZE   0x00000C00
 #if __HEAP_SIZE > 0
 static uint8_t heap[__HEAP_SIZE]   __attribute__ ((aligned(8), used, section(".heap")));
 #endif
@@ -86,99 +86,64 @@ static uint8_t heap[__HEAP_SIZE]   __attribute__ ((aligned(8), used, section(".h
 /*----------------------------------------------------------------------------
   Exception / Interrupt Handler
  *----------------------------------------------------------------------------*/
-/* ARMCM33 Processor Exceptions */
-void NMI_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
-void HardFault_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
-void MemManage_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
-void BusFault_Handler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UsageFault_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
-void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void SVC_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
-void DebugMon_Handler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void PendSV_Handler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void SysTick_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
-
-/* ARMCM33 Specific Interrupts */
-void WDT_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void RTC_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM0_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM2_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIA_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIB_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART0_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART1_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART2_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART4_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void AACI_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void CLCD_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void ENET_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBDC_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBHC_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void CHLCD_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void FLEXRAY_IRQHandler  (void) __attribute__ ((weak, alias("Default_Handler")));
-void CAN_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void LIN_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void I2C_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void CPU_CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART3_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void SPI_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+/* Exceptions */
+void NMI_Handler            (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void MemManage_Handler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler       (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void SecureFault_Handler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler            (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler       (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler        (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
 
 
 /*----------------------------------------------------------------------------
   Exception / Interrupt Vector table
  *----------------------------------------------------------------------------*/
-const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = {
-  /* ARMCM33 Exceptions Handler */
-  (pFunc)((uint32_t)&__StackTop),           /*      Initial Stack Pointer     */
-  Reset_Handler,                            /*      Reset Handler             */
-  NMI_Handler,                              /*      NMI Handler               */
-  HardFault_Handler,                        /*      Hard Fault Handler        */
-  MemManage_Handler,                        /*      MPU Fault Handler         */
-  BusFault_Handler,                         /*      Bus Fault Handler         */
-  UsageFault_Handler,                       /*      Usage Fault Handler       */
-  SecureFault_Handler,                      /*      Secure Fault Handler      */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  SVC_Handler,                              /*      SVCall Handler            */
-  DebugMon_Handler,                         /*      Debug Monitor Handler     */
-  0,                                        /*      Reserved                  */
-  PendSV_Handler,                           /*      PendSV Handler            */
-  SysTick_Handler,                          /*      SysTick Handler           */
-
-  /* External interrupts */
-  WDT_IRQHandler,                           /*  0:  Watchdog Timer            */
-  RTC_IRQHandler,                           /*  1:  Real Time Clock           */
-  TIM0_IRQHandler,                          /*  2:  Timer0 / Timer1           */
-  TIM2_IRQHandler,                          /*  3:  Timer2 / Timer3           */
-  MCIA_IRQHandler,                          /*  4:  MCIa                      */
-  MCIB_IRQHandler,                          /*  5:  MCIb                      */
-  UART0_IRQHandler,                         /*  6:  UART0 - DUT FPGA          */
-  UART1_IRQHandler,                         /*  7:  UART1 - DUT FPGA          */
-  UART2_IRQHandler,                         /*  8:  UART2 - DUT FPGA          */
-  UART4_IRQHandler,                         /*  9:  UART4 - not connected     */
-  AACI_IRQHandler,                          /* 10: AACI / AC97                */
-  CLCD_IRQHandler,                          /* 11: CLCD Combined Interrupt    */
-  ENET_IRQHandler,                          /* 12: Ethernet                   */
-  USBDC_IRQHandler,                         /* 13: USB Device                 */
-  USBHC_IRQHandler,                         /* 14: USB Host Controller        */
-  CHLCD_IRQHandler,                         /* 15: Character LCD              */
-  FLEXRAY_IRQHandler,                       /* 16: Flexray                    */
-  CAN_IRQHandler,                           /* 17: CAN                        */
-  LIN_IRQHandler,                           /* 18: LIN                        */
-  I2C_IRQHandler,                           /* 19: I2C ADC/DAC                */
-  0,                                        /* 20: Reserved                   */
-  0,                                        /* 21: Reserved                   */
-  0,                                        /* 22: Reserved                   */
-  0,                                        /* 23: Reserved                   */
-  0,                                        /* 24: Reserved                   */
-  0,                                        /* 25: Reserved                   */
-  0,                                        /* 26: Reserved                   */
-  0,                                        /* 27: Reserved                   */
-  CPU_CLCD_IRQHandler,                      /* 28: Reserved - CPU FPGA CLCD   */
-  0,                                        /* 29: Reserved - CPU FPGA        */
-  UART3_IRQHandler,                         /* 30: UART3    - CPU FPGA        */
-  SPI_IRQHandler                            /* 31: SPI Touchscreen - CPU FPGA */
+extern const pFunc __Vectors[496];
+       const pFunc __Vectors[496] __attribute__ ((section(".vectors"))) = {
+  (pFunc)(&__StackTop),                     /*     Initial Stack Pointer */
+  Reset_Handler,                            /*     Reset Handler */
+  NMI_Handler,                              /* -14 NMI Handler */
+  HardFault_Handler,                        /* -13 Hard Fault Handler */
+  MemManage_Handler,                        /* -12 MPU Fault Handler */
+  BusFault_Handler,                         /* -11 Bus Fault Handler */
+  UsageFault_Handler,                       /* -10 Usage Fault Handler */
+  SecureFault_Handler,                      /*  -9 Secure Fault Handler */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  SVC_Handler,                              /*  -5 SVCall Handler */
+  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */
+  0,                                        /*     Reserved */
+  PendSV_Handler,                           /*  -2 PendSV Handler */
+  SysTick_Handler,                          /*  -1 SysTick Handler */
+
+  /* Interrupts */
+  Interrupt0_Handler,                       /*   0 Interrupt 0 */
+  Interrupt1_Handler,                       /*   1 Interrupt 1 */
+  Interrupt2_Handler,                       /*   2 Interrupt 2 */
+  Interrupt3_Handler,                       /*   3 Interrupt 3 */
+  Interrupt4_Handler,                       /*   4 Interrupt 4 */
+  Interrupt5_Handler,                       /*   5 Interrupt 5 */
+  Interrupt6_Handler,                       /*   6 Interrupt 6 */
+  Interrupt7_Handler,                       /*   7 Interrupt 7 */
+  Interrupt8_Handler,                       /*   8 Interrupt 8 */
+  Interrupt9_Handler                        /*   9 Interrupt 9 */
+                                            /* Interrupts 10 .. 480 are left out */
 };
 
 
@@ -189,41 +154,42 @@ void Reset_Handler(void) {
   uint32_t *pSrc, *pDest;
   uint32_t *pTable __attribute__((unused));
 
-/*  Firstly it copies data from read only memory to RAM. There are two schemes
- *  to copy. One can copy more than one sections. Another can only copy
- *  one section.  The former scheme needs more instructions and read-only
- *  data to implement than the latter.
- *  Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.  */
+/* Firstly it copies data from read only memory to RAM.
+ * There are two schemes to copy. One can copy more than one sections.
+ * Another can copy only one section. The former scheme needs more
+ * instructions and read-only data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.
+ */
 
 #ifdef __STARTUP_COPY_MULTIPLE
-/*  Multiple sections scheme.
+/* Multiple sections scheme.
  *
- *  Between symbol address __copy_table_start__ and __copy_table_end__,
- *  there are array of triplets, each of which specify:
- *    offset 0: LMA of start of a section to copy from
- *    offset 4: VMA of start of a section to copy to
- *    offset 8: size of the section to copy. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ *   offset 0: LMA of start of a section to copy from
+ *   offset 4: VMA of start of a section to copy to
+ *   offset 8: size of the section to copy. Must be multiply of 4
  *
- *  All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
  */
   pTable = &__copy_table_start__;
 
   for (; pTable < &__copy_table_end__; pTable = pTable + 3) {
-		pSrc  = (uint32_t*)*(pTable + 0);
-		pDest = (uint32_t*)*(pTable + 1);
-		for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
+    pSrc  = (uint32_t*)*(pTable + 0);
+    pDest = (uint32_t*)*(pTable + 1);
+    for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
       *pDest++ = *pSrc++;
-		}
-	}
+    }
+  }
 #else
-/*  Single section scheme.
+/* Single section scheme.
  *
- *  The ranges of copy from/to are specified by following symbols
- *    __etext: LMA of start of the section to copy from. Usually end of text
- *    __data_start__: VMA of start of the section to copy to
- *    __data_end__: VMA of end of the section to copy to
+ * The ranges of copy from/to are specified by following symbols
+ *   __etext: LMA of start of the section to copy from. Usually end of text
+ *   __data_start__: VMA of start of the section to copy to
+ *   __data_end__: VMA of end of the section to copy to
  *
- *  All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
  */
   pSrc  = &__etext;
   pDest = &__data_start__;
@@ -233,40 +199,40 @@ void Reset_Handler(void) {
   }
 #endif /*__STARTUP_COPY_MULTIPLE */
 
-/*  This part of work usually is done in C library startup code. Otherwise,
- *  define this macro to enable it in this startup.
+/* This part of work usually is done in C library startup code.
+ * Otherwise, define this macro to enable it in this startup.
  *
- *  There are two schemes too. One can clear multiple BSS sections. Another
- *  can only clear one section. The former is more size expensive than the
- *  latter.
+ * There are two schemes too.
+ * One can clear multiple BSS sections. Another can only clear one section.
+ * The former is more size expensive than the latter.
  *
- *  Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- *  Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
  */
 #ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/*  Multiple sections scheme.
+/* Multiple sections scheme.
  *
- *  Between symbol address __copy_table_start__ and __copy_table_end__,
- *  there are array of tuples specifying:
- *    offset 0: Start of a BSS section
- *    offset 4: Size of this BSS section. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ *   offset 0: Start of a BSS section
+ *   offset 4: Size of this BSS section. Must be multiply of 4
  */
   pTable = &__zero_table_start__;
 
   for (; pTable < &__zero_table_end__; pTable = pTable + 2) {
-		pDest = (uint32_t*)*(pTable + 0);
-		for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
+    pDest = (uint32_t*)*(pTable + 0);
+    for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
       *pDest++ = 0;
-		}
-	}
+    }
+  }
 #elif defined (__STARTUP_CLEAR_BSS)
-/*  Single BSS section scheme.
+/* Single BSS section scheme.
  *
- *  The BSS section is specified by following symbols
- *    __bss_start__: start of the BSS section.
- *    __bss_end__: end of the BSS section.
+ * The BSS section is specified by following symbols
+ *   __bss_start__: start of the BSS section.
+ *   __bss_end__: end of the BSS section.
  *
- *  Both addresses must be aligned to 4 bytes boundary.
+ * Both addresses must be aligned to 4 bytes boundary.
  */
   pDest = &__bss_start__;
 
@@ -275,15 +241,10 @@ void Reset_Handler(void) {
   }
 #endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
 
-#ifndef __NO_SYSTEM_INIT
-	SystemInit();
-#endif
-
-#ifndef __START
-#define __START _start
-#endif
-	__START();
+  __set_MSPLIM((uint32_t)&__StackLimit);
 
+  SystemInit();                             /* CMSIS System Initialization */
+  _start();                                 /* Enter PreeMain (C library entry point) */
 }
 
 
@@ -292,5 +253,5 @@ void Reset_Handler(void) {
  *----------------------------------------------------------------------------*/
 void Default_Handler(void) {
 
-	while(1);
+  while(1);
 }

CMSIS/CoreValidation/Tests/Cortex-M33/GCC/RTE/Device/ARMCM33/system_ARMCM33.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
  * @file     system_ARMCM33.c
  * @brief    CMSIS Device System Source File for
- *           ARMCM33 Device Series
- * @version  V5.00
- * @date     02. November 2016
+ *           ARMCM33 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -46,9 +46,9 @@
 /*----------------------------------------------------------------------------
   Define clocks
  *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+#define  XTAL            (50000000UL)     /* Oscillator frequency */
 
-#define  SYSTEM_CLOCK    (5U * XTAL)
+#define  SYSTEM_CLOCK    (XTAL / 2U)
 
 
 /*----------------------------------------------------------------------------
@@ -61,7 +61,7 @@
 /*----------------------------------------------------------------------------
   System Core Clock Variable
  *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */
 
 
 /*----------------------------------------------------------------------------

CMSIS/CoreValidation/Tests/Cortex-M33/IAR/RTE/Device/ARMCM33/partition_ARMCM33.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     partition_ARMCM33.h
  * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM33
- * @version  V5.0.1
- * @date     07. December 2016
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -734,7 +734,7 @@
 #define NVIC_INIT_ITNS8    0
 
 /*
-// Interrupts 0..31
+// Interrupts 256..287
 //   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state
@@ -780,7 +780,7 @@
 #define NVIC_INIT_ITNS9    0
 
 /*
-// Interrupts 32..63
+// Interrupts 288..319
 //   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state
@@ -826,7 +826,7 @@
 #define NVIC_INIT_ITNS10   0
 
 /*
-// Interrupts 64..95
+// Interrupts 320..351
 //   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state
@@ -872,7 +872,7 @@
 #define NVIC_INIT_ITNS11   0
 
 /*
-// Interrupts 96..127
+// Interrupts 352..383
 //   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state
@@ -918,7 +918,7 @@
 #define NVIC_INIT_ITNS12   0
 
 /*
-// Interrupts 128..159
+// Interrupts 384..415
 //   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state
@@ -964,7 +964,7 @@
 #define NVIC_INIT_ITNS13   0
 
 /*
-// Interrupts 160..191
+// Interrupts 416..447
 //   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state
@@ -1010,7 +1010,7 @@
 #define NVIC_INIT_ITNS14   0
 
 /*
-// Interrupts 192..223
+// Interrupts 448..479
 //   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state
@@ -1056,7 +1056,7 @@
 #define NVIC_INIT_ITNS15   0
 
 /*
-// Interrupts 224..255
+// Interrupts 480..511
 //   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state

CMSIS/CoreValidation/Tests/Cortex-M33/IAR/RTE/Device/ARMCM33/startup_ARMCM33.s

@@ -1,12 +1,12 @@
 ;/**************************************************************************//**
 ; * @file     startup_ARMCM33.s
 ; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM33 Device Series
-; * @version  V5.00
-; * @date     21. October 2016
+; *           ARMCM33 Device
+; * @version  V5.3.1
+; * @date     09. July 2018
 ; ******************************************************************************/
 ;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
 ; *
 ; * SPDX-License-Identifier: Apache-2.0
 ; *
@@ -39,259 +39,119 @@
 ; Cortex-M version
 ;
 
-        MODULE  ?cstartup
+                MODULE   ?cstartup
 
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
+                ;; Forward declaration of sections.
+                SECTION  CSTACK:DATA:NOROOT(3)
 
-        SECTION .intvec:CODE:NOROOT(2)
+                SECTION  .intvec:CODE:NOROOT(2)
 
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit
-        PUBLIC  __vector_table
-        PUBLIC  __vector_table_0x1c
-        PUBLIC  __Vectors
-        PUBLIC  __Vectors_End
-        PUBLIC  __Vectors_Size
+                EXTERN   __iar_program_start
+                EXTERN   SystemInit
+                PUBLIC   __vector_table
+                PUBLIC   __vector_table_0x1c
+                PUBLIC   __Vectors
+                PUBLIC   __Vectors_End
+                PUBLIC   __Vectors_Size
 
-        DATA
+                DATA
 
 __vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler
-
-        DCD     NMI_Handler
-        DCD     HardFault_Handler
-        DCD     MemManage_Handler
-        DCD     BusFault_Handler
-        DCD     UsageFault_Handler
+                DCD      sfe(CSTACK)                         ;     Top of Stack
+                DCD      Reset_Handler                       ;     Reset Handler
+                DCD      NMI_Handler                         ; -14 NMI Handler
+                DCD      HardFault_Handler                   ; -13 Hard Fault Handler
+                DCD      MemManage_Handler                   ; -12 MPU Fault Handler
+                DCD      BusFault_Handler                    ; -11 Bus Fault Handler
+                DCD      UsageFault_Handler                  ; -10 Usage Fault Handler
 __vector_table_0x1c
-        DCD     SecureFault_Handler
-        DCD     0
-        DCD     0
-        DCD     0
-        DCD     SVC_Handler
-        DCD     DebugMon_Handler
-        DCD     0
-        DCD     PendSV_Handler
-        DCD     SysTick_Handler
-
-        ; External Interrupts
-        DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
-        DCD     RTC_IRQHandler            ;  1:  Real Time Clock
-        DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
-        DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
-        DCD     MCIA_IRQHandler           ;  4:  MCIa
-        DCD     MCIB_IRQHandler           ;  5:  MCIb
-        DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
-        DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
-        DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
-        DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
-        DCD     AACI_IRQHandler           ; 10: AACI / AC97
-        DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
-        DCD     ENET_IRQHandler           ; 12: Ethernet
-        DCD     USBDC_IRQHandler          ; 13: USB Device
-        DCD     USBHC_IRQHandler          ; 14: USB Host Controller
-        DCD     CHLCD_IRQHandler          ; 15: Character LCD
-        DCD     FLEXRAY_IRQHandler        ; 16: Flexray
-        DCD     CAN_IRQHandler            ; 17: CAN
-        DCD     LIN_IRQHandler            ; 18: LIN
-        DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
-        DCD     0                         ; 20: Reserved
-        DCD     0                         ; 21: Reserved
-        DCD     0                         ; 22: Reserved
-        DCD     0                         ; 23: Reserved
-        DCD     0                         ; 24: Reserved
-        DCD     0                         ; 25: Reserved
-        DCD     0                         ; 26: Reserved
-        DCD     0                         ; 27: Reserved
-        DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
-        DCD     0                         ; 29: Reserved - CPU FPGA
-        DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
-        DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
+                DCD      SecureFault_Handler                 ;  -9 Security Fault Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      SVC_Handler                         ;  -5 SVCall Handler
+                DCD      DebugMon_Handler                    ;  -4 Debug Monitor Handler
+                DCD      0                                   ;     Reserved
+                DCD      PendSV_Handler                      ;  -2 PendSV Handler
+                DCD      SysTick_Handler                     ;  -1 SysTick Handler
+
+                ; Interrupts
+                DCD      Interrupt0_Handler                  ;   0 Interrupt 0
+                DCD      Interrupt1_Handler                  ;   1 Interrupt 1
+                DCD      Interrupt2_Handler                  ;   2 Interrupt 2
+                DCD      Interrupt3_Handler                  ;   3 Interrupt 3
+                DCD      Interrupt4_Handler                  ;   4 Interrupt 4
+                DCD      Interrupt5_Handler                  ;   5 Interrupt 5
+                DCD      Interrupt6_Handler                  ;   6 Interrupt 6
+                DCD      Interrupt7_Handler                  ;   7 Interrupt 7
+                DCD      Interrupt8_Handler                  ;   8 Interrupt 8
+                DCD      Interrupt9_Handler                  ;   9 Interrupt 9
+
+                DS32    (470)                                ; Interrupts 10 .. 480 are left out
 __Vectors_End
 
-__Vectors       EQU   __vector_table
-__Vectors_Size  EQU   __Vectors_End - __Vectors
+__Vectors       EQU      __vector_table
+__Vectors_Size  EQU      __Vectors_End - __Vectors
 
 
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
+                THUMB
 
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
+; Reset Handler
 
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
+                PUBWEAK  Reset_Handler
+                SECTION  .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+                LDR      R0, =SystemInit
+                BLX      R0
+                LDR      R0, =__iar_program_start
+                BX       R0
+
+
+                PUBWEAK NMI_Handler
+                PUBWEAK HardFault_Handler
+                PUBWEAK MemManage_Handler
+                PUBWEAK BusFault_Handler
+                PUBWEAK UsageFault_Handler
+                PUBWEAK SecureFault_Handler
+                PUBWEAK SVC_Handler
+                PUBWEAK DebugMon_Handler
+                PUBWEAK PendSV_Handler
+                PUBWEAK SysTick_Handler
+
+                PUBWEAK Interrupt0_Handler
+                PUBWEAK Interrupt1_Handler
+                PUBWEAK Interrupt2_Handler
+                PUBWEAK Interrupt3_Handler
+                PUBWEAK Interrupt4_Handler
+                PUBWEAK Interrupt5_Handler
+                PUBWEAK Interrupt6_Handler
+                PUBWEAK Interrupt7_Handler
+                PUBWEAK Interrupt8_Handler
+                PUBWEAK Interrupt9_Handler
+                SECTION .text:CODE:REORDER:NOROOT(1)
 NMI_Handler
-        B NMI_Handler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 HardFault_Handler
-        B HardFault_Handler
-
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 MemManage_Handler
-        B MemManage_Handler
-
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 BusFault_Handler
-        B BusFault_Handler
-
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 UsageFault_Handler
-        B UsageFault_Handler
-
-        PUBWEAK SecureFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 SecureFault_Handler
-        B SecureFault_Handler
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 SVC_Handler
-        B SVC_Handler
-
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 DebugMon_Handler
-        B DebugMon_Handler
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 SysTick_Handler
-        B SysTick_Handler
-
-        PUBWEAK WDT_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WDT_IRQHandler
-        B WDT_IRQHandler
-
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-
-        PUBWEAK TIM0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM0_IRQHandler
-        B TIM0_IRQHandler
-
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-
-        PUBWEAK MCIA_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MCIA_IRQHandler
-        B MCIA_IRQHandler
-
-        PUBWEAK MCIB_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MCIB_IRQHandler
-        B MCIB_IRQHandler
-
-        PUBWEAK UART0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART0_IRQHandler
-        B UART0_IRQHandler
-
-        PUBWEAK UART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART1_IRQHandler
-        B UART1_IRQHandler
-
-        PUBWEAK UART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART2_IRQHandler
-        B UART2_IRQHandler
-
-        PUBWEAK UART4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
-        B UART4_IRQHandler
-
-        PUBWEAK AACI_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-AACI_IRQHandler
-        B AACI_IRQHandler
-
-        PUBWEAK CLCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CLCD_IRQHandler
-        B CLCD_IRQHandler
-
-        PUBWEAK ENET_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ENET_IRQHandler
-        B ENET_IRQHandler
-
-        PUBWEAK USBDC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USBDC_IRQHandler
-        B USBDC_IRQHandler
-
-        PUBWEAK USBHC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USBHC_IRQHandler
-        B USBHC_IRQHandler
-
-        PUBWEAK CHLCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CHLCD_IRQHandler
-        B CHLCD_IRQHandler
-
-        PUBWEAK FLEXRAY_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLEXRAY_IRQHandler
-        B FLEXRAY_IRQHandler
-
-        PUBWEAK CAN_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN_IRQHandler
-        B CAN_IRQHandler
-
-        PUBWEAK LIN_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-LIN_IRQHandler
-        B LIN_IRQHandler
-
-        PUBWEAK I2C_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C_IRQHandler
-        B I2C_IRQHandler
-
-        PUBWEAK CPU_CLCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CPU_CLCD_IRQHandler
-        B CPU_CLCD_IRQHandler
-
-        PUBWEAK UART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART3_IRQHandler
-        B UART3_IRQHandler
-
-        PUBWEAK SPI_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI_IRQHandler
-        B SPI_IRQHandler
 
-        END
+Interrupt0_Handler
+Interrupt1_Handler
+Interrupt2_Handler
+Interrupt3_Handler
+Interrupt4_Handler
+Interrupt5_Handler
+Interrupt6_Handler
+Interrupt7_Handler
+Interrupt8_Handler
+Interrupt9_Handler
+Default_Handler
+                B        .
+
+
+                END

CMSIS/CoreValidation/Tests/Cortex-M33/IAR/RTE/Device/ARMCM33/system_ARMCM33.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
  * @file     system_ARMCM33.c
  * @brief    CMSIS Device System Source File for
- *           ARMCM33 Device Series
- * @version  V5.00
- * @date     02. November 2016
+ *           ARMCM33 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -46,9 +46,9 @@
 /*----------------------------------------------------------------------------
   Define clocks
  *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+#define  XTAL            (50000000UL)     /* Oscillator frequency */
 
-#define  SYSTEM_CLOCK    (5U * XTAL)
+#define  SYSTEM_CLOCK    (XTAL / 2U)
 
 
 /*----------------------------------------------------------------------------
@@ -61,7 +61,7 @@
 /*----------------------------------------------------------------------------
   System Core Clock Variable
  *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */
 
 
 /*----------------------------------------------------------------------------

CMSIS/CoreValidation/Tests/Cortex-M33NS/AC6/Bootloader/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     partition_ARMCM33.h
  * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM33
- * @version  V5.0.1
- * @date     07. December 2016
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -734,7 +734,7 @@
 #define NVIC_INIT_ITNS8    0
 
 /*
-// Interrupts 0..31
+// Interrupts 256..287
 //   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state
@@ -780,7 +780,7 @@
 #define NVIC_INIT_ITNS9    0
 
 /*
-// Interrupts 32..63
+// Interrupts 288..319
 //   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state
@@ -826,7 +826,7 @@
 #define NVIC_INIT_ITNS10   0
 
 /*
-// Interrupts 64..95
+// Interrupts 320..351
 //   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state
@@ -872,7 +872,7 @@
 #define NVIC_INIT_ITNS11   0
 
 /*
-// Interrupts 96..127
+// Interrupts 352..383
 //   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state
@@ -918,7 +918,7 @@
 #define NVIC_INIT_ITNS12   0
 
 /*
-// Interrupts 128..159
+// Interrupts 384..415
 //   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state
@@ -964,7 +964,7 @@
 #define NVIC_INIT_ITNS13   0
 
 /*
-// Interrupts 160..191
+// Interrupts 416..447
 //   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state
@@ -1010,7 +1010,7 @@
 #define NVIC_INIT_ITNS14   0
 
 /*
-// Interrupts 192..223
+// Interrupts 448..479
 //   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state
@@ -1056,7 +1056,7 @@
 #define NVIC_INIT_ITNS15   0
 
 /*
-// Interrupts 224..255
+// Interrupts 480..511
 //   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state

CMSIS/CoreValidation/Tests/Cortex-M33NS/AC6/Bootloader/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.s

@@ -1,12 +1,12 @@
 ;/**************************************************************************//**
 ; * @file     startup_ARMCM33.s
 ; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM33 Device Series
-; * @version  V5.00
-; * @date     21. October 2016
+; *           ARMCM33 Device
+; * @version  V5.3.1
+; * @date     09. July 2018
 ; ******************************************************************************/
 ;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
 ; *
 ; * SPDX-License-Identifier: Apache-2.0
 ; *
@@ -23,32 +23,33 @@
 ; * limitations under the License.
 ; */
 
-;/*
 ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
 
 
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Stack Configuration
+;  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
 
-Stack_Size      EQU     0x00000400
+Stack_Size      EQU      0x00000400
 
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
+                AREA     STACK, NOINIT, READWRITE, ALIGN=3
+__stack_limit
+Stack_Mem       SPACE    Stack_Size
 __initial_sp
 
 
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Heap Configuration
+;  <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
 
-Heap_Size       EQU     0x00000C00
+Heap_Size       EQU      0x00000C00
 
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+                IF       Heap_Size != 0                      ; Heap is provided
+                AREA     HEAP, NOINIT, READWRITE, ALIGN=3
 __heap_base
-Heap_Mem        SPACE   Heap_Size
+Heap_Mem        SPACE    Heap_Size
 __heap_limit
+                ENDIF
 
 
                 PRESERVE8
@@ -57,211 +58,110 @@ __heap_limit
 
 ; Vector Table Mapped to Address 0 at Reset
 
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     SecureFault_Handler       ; Secure Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
-                DCD     RTC_IRQHandler            ;  1:  Real Time Clock
-                DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
-                DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
-                DCD     MCIA_IRQHandler           ;  4:  MCIa
-                DCD     MCIB_IRQHandler           ;  5:  MCIb
-                DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
-                DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
-                DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
-                DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
-                DCD     AACI_IRQHandler           ; 10: AACI / AC97
-                DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
-                DCD     ENET_IRQHandler           ; 12: Ethernet
-                DCD     USBDC_IRQHandler          ; 13: USB Device
-                DCD     USBHC_IRQHandler          ; 14: USB Host Controller
-                DCD     CHLCD_IRQHandler          ; 15: Character LCD
-                DCD     FLEXRAY_IRQHandler        ; 16: Flexray
-                DCD     CAN_IRQHandler            ; 17: CAN
-                DCD     LIN_IRQHandler            ; 18: LIN
-                DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
-                DCD     0                         ; 20: Reserved
-                DCD     0                         ; 21: Reserved
-                DCD     0                         ; 22: Reserved
-                DCD     0                         ; 23: Reserved
-                DCD     0                         ; 24: Reserved
-                DCD     0                         ; 25: Reserved
-                DCD     0                         ; 26: Reserved
-                DCD     0                         ; 27: Reserved
-                DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
-                DCD     0                         ; 29: Reserved - CPU FPGA
-                DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
-                DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
+                AREA     RESET, DATA, READONLY
+                EXPORT   __Vectors
+                EXPORT   __Vectors_End
+                EXPORT   __Vectors_Size
+
+__Vectors       DCD      __initial_sp                        ;     Top of Stack
+                DCD      Reset_Handler                       ;     Reset Handler
+                DCD      NMI_Handler                         ; -14 NMI Handler
+                DCD      HardFault_Handler                   ; -13 Hard Fault Handler
+                DCD      MemManage_Handler                   ; -12 MPU Fault Handler
+                DCD      BusFault_Handler                    ; -11 Bus Fault Handler
+                DCD      UsageFault_Handler                  ; -10 Usage Fault Handler
+                DCD      SecureFault_Handler                 ;  -9 Secure Fault Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      SVC_Handler                         ;  -5 SVCall Handler
+                DCD      DebugMon_Handler                    ;  -4 Debug Monitor Handler
+                DCD      0                                   ;     Reserved
+                DCD      PendSV_Handler                      ;  -2 PendSV Handler
+                DCD      SysTick_Handler                     ;  -1 SysTick Handler
+
+                ; Interrupts
+                DCD      Interrupt0_Handler                  ;   0 Interrupt 0
+                DCD      Interrupt1_Handler                  ;   1 Interrupt 1
+                DCD      Interrupt2_Handler                  ;   2 Interrupt 2
+                DCD      Interrupt3_Handler                  ;   3 Interrupt 3
+                DCD      Interrupt4_Handler                  ;   4 Interrupt 4
+                DCD      Interrupt5_Handler                  ;   5 Interrupt 5
+                DCD      Interrupt6_Handler                  ;   6 Interrupt 6
+                DCD      Interrupt7_Handler                  ;   7 Interrupt 7
+                DCD      Interrupt8_Handler                  ;   8 Interrupt 8
+                DCD      Interrupt9_Handler                  ;   9 Interrupt 9
+
+                SPACE    (470 * 4)                           ; Interrupts 10 .. 480 are left out
 __Vectors_End
+__Vectors_Size  EQU      __Vectors_End - __Vectors
 
-__Vectors_Size  EQU     __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
 
+                AREA     |.text|, CODE, READONLY
 
 ; Reset Handler
 
 Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  SystemInit
-                IMPORT  __main
-                LDR     R0, =SystemInit
-                BLX     R0
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-
+                EXPORT   Reset_Handler             [WEAK]
+                IMPORT   SystemInit
+                IMPORT   __main
 
-; Dummy Exception Handlers (infinite loops which can be modified)
+                LDR      R0, =__stack_limit
+                MSR      MSPLIM, R0                          ; Non-secure version of MSPLIM is RAZ/WI
 
-NMI_Handler     PROC
-                EXPORT  NMI_Handler               [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler         [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler          [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler        [WEAK]
-                B       .
-                ENDP
-SecureFault_Handler\
-                PROC
-                EXPORT  SecureFault_Handler       [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler          [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
+                LDR      R0, =SystemInit
+                BLX      R0
+                LDR      R0, =__main
+                BX       R0
                 ENDP
 
-Default_Handler PROC
-
-                EXPORT  WDT_IRQHandler            [WEAK]
-                EXPORT  RTC_IRQHandler            [WEAK]
-                EXPORT  TIM0_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler           [WEAK]
-                EXPORT  MCIA_IRQHandler           [WEAK]
-                EXPORT  MCIB_IRQHandler           [WEAK]
-                EXPORT  UART0_IRQHandler          [WEAK]
-                EXPORT  UART1_IRQHandler          [WEAK]
-                EXPORT  UART2_IRQHandler          [WEAK]
-                EXPORT  UART3_IRQHandler          [WEAK]
-                EXPORT  UART4_IRQHandler          [WEAK]
-                EXPORT  AACI_IRQHandler           [WEAK]
-                EXPORT  CLCD_IRQHandler           [WEAK]
-                EXPORT  ENET_IRQHandler           [WEAK]
-                EXPORT  USBDC_IRQHandler          [WEAK]
-                EXPORT  USBHC_IRQHandler          [WEAK]
-                EXPORT  CHLCD_IRQHandler          [WEAK]
-                EXPORT  FLEXRAY_IRQHandler        [WEAK]
-                EXPORT  CAN_IRQHandler            [WEAK]
-                EXPORT  LIN_IRQHandler            [WEAK]
-                EXPORT  I2C_IRQHandler            [WEAK]
-                EXPORT  CPU_CLCD_IRQHandler       [WEAK]
-                EXPORT  SPI_IRQHandler            [WEAK]
-
-WDT_IRQHandler
-RTC_IRQHandler
-TIM0_IRQHandler
-TIM2_IRQHandler
-MCIA_IRQHandler
-MCIB_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-UART3_IRQHandler
-UART4_IRQHandler
-AACI_IRQHandler
-CLCD_IRQHandler
-ENET_IRQHandler
-USBDC_IRQHandler
-USBHC_IRQHandler
-CHLCD_IRQHandler
-FLEXRAY_IRQHandler
-CAN_IRQHandler
-LIN_IRQHandler
-I2C_IRQHandler
-CPU_CLCD_IRQHandler
-SPI_IRQHandler
-                B       .
 
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+                MACRO
+                Set_Default_Handler  $Handler_Name
+$Handler_Name   PROC
+                EXPORT   $Handler_Name             [WEAK]
+                B        .
                 ENDP
-
+                MEND
+
+
+; Default exception/interrupt handler
+
+                Set_Default_Handler  NMI_Handler
+                Set_Default_Handler  HardFault_Handler
+                Set_Default_Handler  MemManage_Handler
+                Set_Default_Handler  BusFault_Handler
+                Set_Default_Handler  UsageFault_Handler
+                Set_Default_Handler  SecureFault_Handler
+                Set_Default_Handler  SVC_Handler
+                Set_Default_Handler  DebugMon_Handler
+                Set_Default_Handler  PendSV_Handler
+                Set_Default_Handler  SysTick_Handler
+
+                Set_Default_Handler  Interrupt0_Handler
+                Set_Default_Handler  Interrupt1_Handler
+                Set_Default_Handler  Interrupt2_Handler
+                Set_Default_Handler  Interrupt3_Handler
+                Set_Default_Handler  Interrupt4_Handler
+                Set_Default_Handler  Interrupt5_Handler
+                Set_Default_Handler  Interrupt6_Handler
+                Set_Default_Handler  Interrupt7_Handler
+                Set_Default_Handler  Interrupt8_Handler
+                Set_Default_Handler  Interrupt9_Handler
 
                 ALIGN
 
 
-; User Initial Stack & Heap
-
-                IF      :DEF:__MICROLIB
-
-                EXPORT  __initial_sp
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-
-                ELSE
-
-                IMPORT  __use_two_region_memory
-                EXPORT  __user_initial_stackheap
-
-__user_initial_stackheap PROC
-                LDR     R0, =  Heap_Mem
-                LDR     R1, =(Stack_Mem + Stack_Size)
-                LDR     R2, = (Heap_Mem +  Heap_Size)
-                LDR     R3, = Stack_Mem
-                BX      LR
-                ENDP
-
-                ALIGN
+; User setup Stack & Heap
 
+                EXPORT   __stack_limit
+                EXPORT   __initial_sp
+                IF       Heap_Size != 0                      ; Heap is provided
+                EXPORT   __heap_base
+                EXPORT   __heap_limit
                 ENDIF
 
-
                 END

CMSIS/CoreValidation/Tests/Cortex-M33NS/AC6/Bootloader/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
  * @file     system_ARMCM33.c
  * @brief    CMSIS Device System Source File for
- *           ARMCM33 Device Series
- * @version  V5.00
- * @date     02. November 2016
+ *           ARMCM33 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -46,9 +46,9 @@
 /*----------------------------------------------------------------------------
   Define clocks
  *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+#define  XTAL            (50000000UL)     /* Oscillator frequency */
 
-#define  SYSTEM_CLOCK    (5U * XTAL)
+#define  SYSTEM_CLOCK    (XTAL / 2U)
 
 
 /*----------------------------------------------------------------------------
@@ -61,7 +61,7 @@
 /*----------------------------------------------------------------------------
   System Core Clock Variable
  *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */
 
 
 /*----------------------------------------------------------------------------

CMSIS/CoreValidation/Tests/Cortex-M33NS/AC6/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     partition_ARMCM33.h
  * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM33
- * @version  V5.0.1
- * @date     07. December 2016
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -734,7 +734,7 @@
 #define NVIC_INIT_ITNS8    0
 
 /*
-// Interrupts 0..31
+// Interrupts 256..287
 //   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state
@@ -780,7 +780,7 @@
 #define NVIC_INIT_ITNS9    0
 
 /*
-// Interrupts 32..63
+// Interrupts 288..319
 //   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state
@@ -826,7 +826,7 @@
 #define NVIC_INIT_ITNS10   0
 
 /*
-// Interrupts 64..95
+// Interrupts 320..351
 //   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state
@@ -872,7 +872,7 @@
 #define NVIC_INIT_ITNS11   0
 
 /*
-// Interrupts 96..127
+// Interrupts 352..383
 //   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state
@@ -918,7 +918,7 @@
 #define NVIC_INIT_ITNS12   0
 
 /*
-// Interrupts 128..159
+// Interrupts 384..415
 //   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state
@@ -964,7 +964,7 @@
 #define NVIC_INIT_ITNS13   0
 
 /*
-// Interrupts 160..191
+// Interrupts 416..447
 //   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state
@@ -1010,7 +1010,7 @@
 #define NVIC_INIT_ITNS14   0
 
 /*
-// Interrupts 192..223
+// Interrupts 448..479
 //   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state
@@ -1056,7 +1056,7 @@
 #define NVIC_INIT_ITNS15   0
 
 /*
-// Interrupts 224..255
+// Interrupts 480..511
 //   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state

CMSIS/CoreValidation/Tests/Cortex-M33NS/AC6/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.s

@@ -1,12 +1,12 @@
 ;/**************************************************************************//**
 ; * @file     startup_ARMCM33.s
 ; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM33 Device Series
-; * @version  V5.00
-; * @date     21. October 2016
+; *           ARMCM33 Device
+; * @version  V5.3.1
+; * @date     09. July 2018
 ; ******************************************************************************/
 ;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
 ; *
 ; * SPDX-License-Identifier: Apache-2.0
 ; *
@@ -23,32 +23,33 @@
 ; * limitations under the License.
 ; */
 
-;/*
 ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
 
 
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Stack Configuration
+;  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
 
-Stack_Size      EQU     0x00000400
+Stack_Size      EQU      0x00000400
 
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
+                AREA     STACK, NOINIT, READWRITE, ALIGN=3
+__stack_limit
+Stack_Mem       SPACE    Stack_Size
 __initial_sp
 
 
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Heap Configuration
+;  <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
 
-Heap_Size       EQU     0x00000C00
+Heap_Size       EQU      0x00000C00
 
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+                IF       Heap_Size != 0                      ; Heap is provided
+                AREA     HEAP, NOINIT, READWRITE, ALIGN=3
 __heap_base
-Heap_Mem        SPACE   Heap_Size
+Heap_Mem        SPACE    Heap_Size
 __heap_limit
+                ENDIF
 
 
                 PRESERVE8
@@ -57,211 +58,110 @@ __heap_limit
 
 ; Vector Table Mapped to Address 0 at Reset
 
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     SecureFault_Handler       ; Secure Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
-                DCD     RTC_IRQHandler            ;  1:  Real Time Clock
-                DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
-                DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
-                DCD     MCIA_IRQHandler           ;  4:  MCIa
-                DCD     MCIB_IRQHandler           ;  5:  MCIb
-                DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
-                DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
-                DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
-                DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
-                DCD     AACI_IRQHandler           ; 10: AACI / AC97
-                DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
-                DCD     ENET_IRQHandler           ; 12: Ethernet
-                DCD     USBDC_IRQHandler          ; 13: USB Device
-                DCD     USBHC_IRQHandler          ; 14: USB Host Controller
-                DCD     CHLCD_IRQHandler          ; 15: Character LCD
-                DCD     FLEXRAY_IRQHandler        ; 16: Flexray
-                DCD     CAN_IRQHandler            ; 17: CAN
-                DCD     LIN_IRQHandler            ; 18: LIN
-                DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
-                DCD     0                         ; 20: Reserved
-                DCD     0                         ; 21: Reserved
-                DCD     0                         ; 22: Reserved
-                DCD     0                         ; 23: Reserved
-                DCD     0                         ; 24: Reserved
-                DCD     0                         ; 25: Reserved
-                DCD     0                         ; 26: Reserved
-                DCD     0                         ; 27: Reserved
-                DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
-                DCD     0                         ; 29: Reserved - CPU FPGA
-                DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
-                DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
+                AREA     RESET, DATA, READONLY
+                EXPORT   __Vectors
+                EXPORT   __Vectors_End
+                EXPORT   __Vectors_Size
+
+__Vectors       DCD      __initial_sp                        ;     Top of Stack
+                DCD      Reset_Handler                       ;     Reset Handler
+                DCD      NMI_Handler                         ; -14 NMI Handler
+                DCD      HardFault_Handler                   ; -13 Hard Fault Handler
+                DCD      MemManage_Handler                   ; -12 MPU Fault Handler
+                DCD      BusFault_Handler                    ; -11 Bus Fault Handler
+                DCD      UsageFault_Handler                  ; -10 Usage Fault Handler
+                DCD      SecureFault_Handler                 ;  -9 Secure Fault Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      SVC_Handler                         ;  -5 SVCall Handler
+                DCD      DebugMon_Handler                    ;  -4 Debug Monitor Handler
+                DCD      0                                   ;     Reserved
+                DCD      PendSV_Handler                      ;  -2 PendSV Handler
+                DCD      SysTick_Handler                     ;  -1 SysTick Handler
+
+                ; Interrupts
+                DCD      Interrupt0_Handler                  ;   0 Interrupt 0
+                DCD      Interrupt1_Handler                  ;   1 Interrupt 1
+                DCD      Interrupt2_Handler                  ;   2 Interrupt 2
+                DCD      Interrupt3_Handler                  ;   3 Interrupt 3
+                DCD      Interrupt4_Handler                  ;   4 Interrupt 4
+                DCD      Interrupt5_Handler                  ;   5 Interrupt 5
+                DCD      Interrupt6_Handler                  ;   6 Interrupt 6
+                DCD      Interrupt7_Handler                  ;   7 Interrupt 7
+                DCD      Interrupt8_Handler                  ;   8 Interrupt 8
+                DCD      Interrupt9_Handler                  ;   9 Interrupt 9
+
+                SPACE    (470 * 4)                           ; Interrupts 10 .. 480 are left out
 __Vectors_End
+__Vectors_Size  EQU      __Vectors_End - __Vectors
 
-__Vectors_Size  EQU     __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
 
+                AREA     |.text|, CODE, READONLY
 
 ; Reset Handler
 
 Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  SystemInit
-                IMPORT  __main
-                LDR     R0, =SystemInit
-                BLX     R0
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-
+                EXPORT   Reset_Handler             [WEAK]
+                IMPORT   SystemInit
+                IMPORT   __main
 
-; Dummy Exception Handlers (infinite loops which can be modified)
+                LDR      R0, =__stack_limit
+                MSR      MSPLIM, R0                          ; Non-secure version of MSPLIM is RAZ/WI
 
-NMI_Handler     PROC
-                EXPORT  NMI_Handler               [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler         [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler          [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler        [WEAK]
-                B       .
-                ENDP
-SecureFault_Handler\
-                PROC
-                EXPORT  SecureFault_Handler       [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler          [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
+                LDR      R0, =SystemInit
+                BLX      R0
+                LDR      R0, =__main
+                BX       R0
                 ENDP
 
-Default_Handler PROC
-
-                EXPORT  WDT_IRQHandler            [WEAK]
-                EXPORT  RTC_IRQHandler            [WEAK]
-                EXPORT  TIM0_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler           [WEAK]
-                EXPORT  MCIA_IRQHandler           [WEAK]
-                EXPORT  MCIB_IRQHandler           [WEAK]
-                EXPORT  UART0_IRQHandler          [WEAK]
-                EXPORT  UART1_IRQHandler          [WEAK]
-                EXPORT  UART2_IRQHandler          [WEAK]
-                EXPORT  UART3_IRQHandler          [WEAK]
-                EXPORT  UART4_IRQHandler          [WEAK]
-                EXPORT  AACI_IRQHandler           [WEAK]
-                EXPORT  CLCD_IRQHandler           [WEAK]
-                EXPORT  ENET_IRQHandler           [WEAK]
-                EXPORT  USBDC_IRQHandler          [WEAK]
-                EXPORT  USBHC_IRQHandler          [WEAK]
-                EXPORT  CHLCD_IRQHandler          [WEAK]
-                EXPORT  FLEXRAY_IRQHandler        [WEAK]
-                EXPORT  CAN_IRQHandler            [WEAK]
-                EXPORT  LIN_IRQHandler            [WEAK]
-                EXPORT  I2C_IRQHandler            [WEAK]
-                EXPORT  CPU_CLCD_IRQHandler       [WEAK]
-                EXPORT  SPI_IRQHandler            [WEAK]
-
-WDT_IRQHandler
-RTC_IRQHandler
-TIM0_IRQHandler
-TIM2_IRQHandler
-MCIA_IRQHandler
-MCIB_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-UART3_IRQHandler
-UART4_IRQHandler
-AACI_IRQHandler
-CLCD_IRQHandler
-ENET_IRQHandler
-USBDC_IRQHandler
-USBHC_IRQHandler
-CHLCD_IRQHandler
-FLEXRAY_IRQHandler
-CAN_IRQHandler
-LIN_IRQHandler
-I2C_IRQHandler
-CPU_CLCD_IRQHandler
-SPI_IRQHandler
-                B       .
 
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+                MACRO
+                Set_Default_Handler  $Handler_Name
+$Handler_Name   PROC
+                EXPORT   $Handler_Name             [WEAK]
+                B        .
                 ENDP
-
+                MEND
+
+
+; Default exception/interrupt handler
+
+                Set_Default_Handler  NMI_Handler
+                Set_Default_Handler  HardFault_Handler
+                Set_Default_Handler  MemManage_Handler
+                Set_Default_Handler  BusFault_Handler
+                Set_Default_Handler  UsageFault_Handler
+                Set_Default_Handler  SecureFault_Handler
+                Set_Default_Handler  SVC_Handler
+                Set_Default_Handler  DebugMon_Handler
+                Set_Default_Handler  PendSV_Handler
+                Set_Default_Handler  SysTick_Handler
+
+                Set_Default_Handler  Interrupt0_Handler
+                Set_Default_Handler  Interrupt1_Handler
+                Set_Default_Handler  Interrupt2_Handler
+                Set_Default_Handler  Interrupt3_Handler
+                Set_Default_Handler  Interrupt4_Handler
+                Set_Default_Handler  Interrupt5_Handler
+                Set_Default_Handler  Interrupt6_Handler
+                Set_Default_Handler  Interrupt7_Handler
+                Set_Default_Handler  Interrupt8_Handler
+                Set_Default_Handler  Interrupt9_Handler
 
                 ALIGN
 
 
-; User Initial Stack & Heap
-
-                IF      :DEF:__MICROLIB
-
-                EXPORT  __initial_sp
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-
-                ELSE
-
-                IMPORT  __use_two_region_memory
-                EXPORT  __user_initial_stackheap
-
-__user_initial_stackheap PROC
-                LDR     R0, =  Heap_Mem
-                LDR     R1, =(Stack_Mem + Stack_Size)
-                LDR     R2, = (Heap_Mem +  Heap_Size)
-                LDR     R3, = Stack_Mem
-                BX      LR
-                ENDP
-
-                ALIGN
+; User setup Stack & Heap
 
+                EXPORT   __stack_limit
+                EXPORT   __initial_sp
+                IF       Heap_Size != 0                      ; Heap is provided
+                EXPORT   __heap_base
+                EXPORT   __heap_limit
                 ENDIF
 
-
                 END

CMSIS/CoreValidation/Tests/Cortex-M33NS/AC6/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
  * @file     system_ARMCM33.c
  * @brief    CMSIS Device System Source File for
- *           ARMCM33 Device Series
- * @version  V5.00
- * @date     02. November 2016
+ *           ARMCM33 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -46,9 +46,9 @@
 /*----------------------------------------------------------------------------
   Define clocks
  *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+#define  XTAL            (50000000UL)     /* Oscillator frequency */
 
-#define  SYSTEM_CLOCK    (5U * XTAL)
+#define  SYSTEM_CLOCK    (XTAL / 2U)
 
 
 /*----------------------------------------------------------------------------
@@ -61,7 +61,7 @@
 /*----------------------------------------------------------------------------
   System Core Clock Variable
  *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */
 
 
 /*----------------------------------------------------------------------------

CMSIS/CoreValidation/Tests/Cortex-M33NS/GCC/Bootloader/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     partition_ARMCM33.h
  * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM33
- * @version  V5.0.1
- * @date     07. December 2016
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -734,7 +734,7 @@
 #define NVIC_INIT_ITNS8    0
 
 /*
-// Interrupts 0..31
+// Interrupts 256..287
 //   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state
@@ -780,7 +780,7 @@
 #define NVIC_INIT_ITNS9    0
 
 /*
-// Interrupts 32..63
+// Interrupts 288..319
 //   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state
@@ -826,7 +826,7 @@
 #define NVIC_INIT_ITNS10   0
 
 /*
-// Interrupts 64..95
+// Interrupts 320..351
 //   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state
@@ -872,7 +872,7 @@
 #define NVIC_INIT_ITNS11   0
 
 /*
-// Interrupts 96..127
+// Interrupts 352..383
 //   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state
@@ -918,7 +918,7 @@
 #define NVIC_INIT_ITNS12   0
 
 /*
-// Interrupts 128..159
+// Interrupts 384..415
 //   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state
@@ -964,7 +964,7 @@
 #define NVIC_INIT_ITNS13   0
 
 /*
-// Interrupts 160..191
+// Interrupts 416..447
 //   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state
@@ -1010,7 +1010,7 @@
 #define NVIC_INIT_ITNS14   0
 
 /*
-// Interrupts 192..223
+// Interrupts 448..479
 //   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state
@@ -1056,7 +1056,7 @@
 #define NVIC_INIT_ITNS15   0
 
 /*
-// Interrupts 224..255
+// Interrupts 480..511
 //   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state

CMSIS/CoreValidation/Tests/Cortex-M33NS/GCC/Bootloader/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
- * @file     startup_ARMCM33.s
+ * @file     startup_ARMCM33.c
  * @brief    CMSIS Core Device Startup File for
- *           ARMCM33 Device Series
- * @version  V5.00
- * @date     21. October 2016
+ *           ARMCM33 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -23,6 +23,10 @@
  * limitations under the License.
  */
 
+/*
+ //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
 #include <stdint.h>
 
 
@@ -39,6 +43,7 @@ extern uint32_t __zero_table_end__;
 extern uint32_t __bss_start__;
 extern uint32_t __bss_end__;
 extern uint32_t __StackTop;
+extern uint32_t __StackLimit;
 
 /*----------------------------------------------------------------------------
   Exception / Interrupt Handler Function Prototype
@@ -49,35 +54,30 @@ typedef void( *pFunc )( void );
 /*----------------------------------------------------------------------------
   External References
  *----------------------------------------------------------------------------*/
-#ifndef __START
-extern void  _start(void) __attribute__((noreturn));    /* PreeMain (C library entry point) */
-#else
-extern int  __START(void) __attribute__((noreturn));    /* main entry point */
-#endif
-
-#ifndef __NO_SYSTEM_INIT
-extern void SystemInit (void);            /* CMSIS System Initialization      */
-#endif
+extern void _start     (void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
+extern void SystemInit (void);                           /* CMSIS System Initialization */
 
 
 /*----------------------------------------------------------------------------
   Internal References
  *----------------------------------------------------------------------------*/
-void Default_Handler(void);                          /* Default empty handler */
-void Reset_Handler(void);                            /* Reset Handler */
+void Default_Handler(void) __attribute__ ((noreturn));
+void Reset_Handler  (void) __attribute__ ((noreturn));
 
 
 /*----------------------------------------------------------------------------
   User Initial Stack & Heap
  *----------------------------------------------------------------------------*/
-#ifndef __STACK_SIZE
-  #define	__STACK_SIZE  0x00000400
-#endif
+//<h> Stack Configuration
+//  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//</h>
+#define  __STACK_SIZE  0x00000400
 static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack")));
 
-#ifndef __HEAP_SIZE
-  #define	__HEAP_SIZE   0x00000C00
-#endif
+//<h> Heap Configuration
+//  <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//</h>
+#define  __HEAP_SIZE   0x00000C00
 #if __HEAP_SIZE > 0
 static uint8_t heap[__HEAP_SIZE]   __attribute__ ((aligned(8), used, section(".heap")));
 #endif
@@ -86,99 +86,64 @@ static uint8_t heap[__HEAP_SIZE]   __attribute__ ((aligned(8), used, section(".h
 /*----------------------------------------------------------------------------
   Exception / Interrupt Handler
  *----------------------------------------------------------------------------*/
-/* ARMCM33 Processor Exceptions */
-void NMI_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
-void HardFault_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
-void MemManage_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
-void BusFault_Handler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UsageFault_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
-void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void SVC_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
-void DebugMon_Handler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void PendSV_Handler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void SysTick_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
-
-/* ARMCM33 Specific Interrupts */
-void WDT_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void RTC_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM0_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM2_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIA_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIB_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART0_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART1_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART2_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART4_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void AACI_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void CLCD_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void ENET_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBDC_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBHC_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void CHLCD_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void FLEXRAY_IRQHandler  (void) __attribute__ ((weak, alias("Default_Handler")));
-void CAN_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void LIN_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void I2C_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void CPU_CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART3_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void SPI_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+/* Exceptions */
+void NMI_Handler            (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void MemManage_Handler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler       (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void SecureFault_Handler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler            (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler       (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler        (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
 
 
 /*----------------------------------------------------------------------------
   Exception / Interrupt Vector table
  *----------------------------------------------------------------------------*/
-const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = {
-  /* ARMCM33 Exceptions Handler */
-  (pFunc)((uint32_t)&__StackTop),           /*      Initial Stack Pointer     */
-  Reset_Handler,                            /*      Reset Handler             */
-  NMI_Handler,                              /*      NMI Handler               */
-  HardFault_Handler,                        /*      Hard Fault Handler        */
-  MemManage_Handler,                        /*      MPU Fault Handler         */
-  BusFault_Handler,                         /*      Bus Fault Handler         */
-  UsageFault_Handler,                       /*      Usage Fault Handler       */
-  SecureFault_Handler,                      /*      Secure Fault Handler      */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  SVC_Handler,                              /*      SVCall Handler            */
-  DebugMon_Handler,                         /*      Debug Monitor Handler     */
-  0,                                        /*      Reserved                  */
-  PendSV_Handler,                           /*      PendSV Handler            */
-  SysTick_Handler,                          /*      SysTick Handler           */
-
-  /* External interrupts */
-  WDT_IRQHandler,                           /*  0:  Watchdog Timer            */
-  RTC_IRQHandler,                           /*  1:  Real Time Clock           */
-  TIM0_IRQHandler,                          /*  2:  Timer0 / Timer1           */
-  TIM2_IRQHandler,                          /*  3:  Timer2 / Timer3           */
-  MCIA_IRQHandler,                          /*  4:  MCIa                      */
-  MCIB_IRQHandler,                          /*  5:  MCIb                      */
-  UART0_IRQHandler,                         /*  6:  UART0 - DUT FPGA          */
-  UART1_IRQHandler,                         /*  7:  UART1 - DUT FPGA          */
-  UART2_IRQHandler,                         /*  8:  UART2 - DUT FPGA          */
-  UART4_IRQHandler,                         /*  9:  UART4 - not connected     */
-  AACI_IRQHandler,                          /* 10: AACI / AC97                */
-  CLCD_IRQHandler,                          /* 11: CLCD Combined Interrupt    */
-  ENET_IRQHandler,                          /* 12: Ethernet                   */
-  USBDC_IRQHandler,                         /* 13: USB Device                 */
-  USBHC_IRQHandler,                         /* 14: USB Host Controller        */
-  CHLCD_IRQHandler,                         /* 15: Character LCD              */
-  FLEXRAY_IRQHandler,                       /* 16: Flexray                    */
-  CAN_IRQHandler,                           /* 17: CAN                        */
-  LIN_IRQHandler,                           /* 18: LIN                        */
-  I2C_IRQHandler,                           /* 19: I2C ADC/DAC                */
-  0,                                        /* 20: Reserved                   */
-  0,                                        /* 21: Reserved                   */
-  0,                                        /* 22: Reserved                   */
-  0,                                        /* 23: Reserved                   */
-  0,                                        /* 24: Reserved                   */
-  0,                                        /* 25: Reserved                   */
-  0,                                        /* 26: Reserved                   */
-  0,                                        /* 27: Reserved                   */
-  CPU_CLCD_IRQHandler,                      /* 28: Reserved - CPU FPGA CLCD   */
-  0,                                        /* 29: Reserved - CPU FPGA        */
-  UART3_IRQHandler,                         /* 30: UART3    - CPU FPGA        */
-  SPI_IRQHandler                            /* 31: SPI Touchscreen - CPU FPGA */
+extern const pFunc __Vectors[496];
+       const pFunc __Vectors[496] __attribute__ ((section(".vectors"))) = {
+  (pFunc)(&__StackTop),                     /*     Initial Stack Pointer */
+  Reset_Handler,                            /*     Reset Handler */
+  NMI_Handler,                              /* -14 NMI Handler */
+  HardFault_Handler,                        /* -13 Hard Fault Handler */
+  MemManage_Handler,                        /* -12 MPU Fault Handler */
+  BusFault_Handler,                         /* -11 Bus Fault Handler */
+  UsageFault_Handler,                       /* -10 Usage Fault Handler */
+  SecureFault_Handler,                      /*  -9 Secure Fault Handler */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  SVC_Handler,                              /*  -5 SVCall Handler */
+  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */
+  0,                                        /*     Reserved */
+  PendSV_Handler,                           /*  -2 PendSV Handler */
+  SysTick_Handler,                          /*  -1 SysTick Handler */
+
+  /* Interrupts */
+  Interrupt0_Handler,                       /*   0 Interrupt 0 */
+  Interrupt1_Handler,                       /*   1 Interrupt 1 */
+  Interrupt2_Handler,                       /*   2 Interrupt 2 */
+  Interrupt3_Handler,                       /*   3 Interrupt 3 */
+  Interrupt4_Handler,                       /*   4 Interrupt 4 */
+  Interrupt5_Handler,                       /*   5 Interrupt 5 */
+  Interrupt6_Handler,                       /*   6 Interrupt 6 */
+  Interrupt7_Handler,                       /*   7 Interrupt 7 */
+  Interrupt8_Handler,                       /*   8 Interrupt 8 */
+  Interrupt9_Handler                        /*   9 Interrupt 9 */
+                                            /* Interrupts 10 .. 480 are left out */
 };
 
 
@@ -189,41 +154,42 @@ void Reset_Handler(void) {
   uint32_t *pSrc, *pDest;
   uint32_t *pTable __attribute__((unused));
 
-/*  Firstly it copies data from read only memory to RAM. There are two schemes
- *  to copy. One can copy more than one sections. Another can only copy
- *  one section.  The former scheme needs more instructions and read-only
- *  data to implement than the latter.
- *  Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.  */
+/* Firstly it copies data from read only memory to RAM.
+ * There are two schemes to copy. One can copy more than one sections.
+ * Another can copy only one section. The former scheme needs more
+ * instructions and read-only data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.
+ */
 
 #ifdef __STARTUP_COPY_MULTIPLE
-/*  Multiple sections scheme.
+/* Multiple sections scheme.
  *
- *  Between symbol address __copy_table_start__ and __copy_table_end__,
- *  there are array of triplets, each of which specify:
- *    offset 0: LMA of start of a section to copy from
- *    offset 4: VMA of start of a section to copy to
- *    offset 8: size of the section to copy. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ *   offset 0: LMA of start of a section to copy from
+ *   offset 4: VMA of start of a section to copy to
+ *   offset 8: size of the section to copy. Must be multiply of 4
  *
- *  All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
  */
   pTable = &__copy_table_start__;
 
   for (; pTable < &__copy_table_end__; pTable = pTable + 3) {
-		pSrc  = (uint32_t*)*(pTable + 0);
-		pDest = (uint32_t*)*(pTable + 1);
-		for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
+    pSrc  = (uint32_t*)*(pTable + 0);
+    pDest = (uint32_t*)*(pTable + 1);
+    for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
       *pDest++ = *pSrc++;
-		}
-	}
+    }
+  }
 #else
-/*  Single section scheme.
+/* Single section scheme.
  *
- *  The ranges of copy from/to are specified by following symbols
- *    __etext: LMA of start of the section to copy from. Usually end of text
- *    __data_start__: VMA of start of the section to copy to
- *    __data_end__: VMA of end of the section to copy to
+ * The ranges of copy from/to are specified by following symbols
+ *   __etext: LMA of start of the section to copy from. Usually end of text
+ *   __data_start__: VMA of start of the section to copy to
+ *   __data_end__: VMA of end of the section to copy to
  *
- *  All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
  */
   pSrc  = &__etext;
   pDest = &__data_start__;
@@ -233,40 +199,40 @@ void Reset_Handler(void) {
   }
 #endif /*__STARTUP_COPY_MULTIPLE */
 
-/*  This part of work usually is done in C library startup code. Otherwise,
- *  define this macro to enable it in this startup.
+/* This part of work usually is done in C library startup code.
+ * Otherwise, define this macro to enable it in this startup.
  *
- *  There are two schemes too. One can clear multiple BSS sections. Another
- *  can only clear one section. The former is more size expensive than the
- *  latter.
+ * There are two schemes too.
+ * One can clear multiple BSS sections. Another can only clear one section.
+ * The former is more size expensive than the latter.
  *
- *  Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- *  Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
  */
 #ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/*  Multiple sections scheme.
+/* Multiple sections scheme.
  *
- *  Between symbol address __copy_table_start__ and __copy_table_end__,
- *  there are array of tuples specifying:
- *    offset 0: Start of a BSS section
- *    offset 4: Size of this BSS section. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ *   offset 0: Start of a BSS section
+ *   offset 4: Size of this BSS section. Must be multiply of 4
  */
   pTable = &__zero_table_start__;
 
   for (; pTable < &__zero_table_end__; pTable = pTable + 2) {
-		pDest = (uint32_t*)*(pTable + 0);
-		for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
+    pDest = (uint32_t*)*(pTable + 0);
+    for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
       *pDest++ = 0;
-		}
-	}
+    }
+  }
 #elif defined (__STARTUP_CLEAR_BSS)
-/*  Single BSS section scheme.
+/* Single BSS section scheme.
  *
- *  The BSS section is specified by following symbols
- *    __bss_start__: start of the BSS section.
- *    __bss_end__: end of the BSS section.
+ * The BSS section is specified by following symbols
+ *   __bss_start__: start of the BSS section.
+ *   __bss_end__: end of the BSS section.
  *
- *  Both addresses must be aligned to 4 bytes boundary.
+ * Both addresses must be aligned to 4 bytes boundary.
  */
   pDest = &__bss_start__;
 
@@ -275,15 +241,10 @@ void Reset_Handler(void) {
   }
 #endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
 
-#ifndef __NO_SYSTEM_INIT
-	SystemInit();
-#endif
-
-#ifndef __START
-#define __START _start
-#endif
-	__START();
+  __set_MSPLIM((uint32_t)&__StackLimit);
 
+  SystemInit();                             /* CMSIS System Initialization */
+  _start();                                 /* Enter PreeMain (C library entry point) */
 }
 
 
@@ -292,5 +253,5 @@ void Reset_Handler(void) {
  *----------------------------------------------------------------------------*/
 void Default_Handler(void) {
 
-	while(1);
+  while(1);
 }

CMSIS/CoreValidation/Tests/Cortex-M33NS/GCC/Bootloader/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
  * @file     system_ARMCM33.c
  * @brief    CMSIS Device System Source File for
- *           ARMCM33 Device Series
- * @version  V5.00
- * @date     02. November 2016
+ *           ARMCM33 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -46,9 +46,9 @@
 /*----------------------------------------------------------------------------
   Define clocks
  *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+#define  XTAL            (50000000UL)     /* Oscillator frequency */
 
-#define  SYSTEM_CLOCK    (5U * XTAL)
+#define  SYSTEM_CLOCK    (XTAL / 2U)
 
 
 /*----------------------------------------------------------------------------
@@ -61,7 +61,7 @@
 /*----------------------------------------------------------------------------
   System Core Clock Variable
  *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */
 
 
 /*----------------------------------------------------------------------------
@@ -75,7 +75,6 @@ void SystemCoreClockUpdate (void)
 /*----------------------------------------------------------------------------
   System initialization function
  *----------------------------------------------------------------------------*/
-
 void SystemInit (void)
 {
 

CMSIS/CoreValidation/Tests/Cortex-M33NS/GCC/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     partition_ARMCM33.h
  * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM33
- * @version  V5.0.1
- * @date     07. December 2016
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -734,7 +734,7 @@
 #define NVIC_INIT_ITNS8    0
 
 /*
-// Interrupts 0..31
+// Interrupts 256..287
 //   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state
@@ -780,7 +780,7 @@
 #define NVIC_INIT_ITNS9    0
 
 /*
-// Interrupts 32..63
+// Interrupts 288..319
 //   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state
@@ -826,7 +826,7 @@
 #define NVIC_INIT_ITNS10   0
 
 /*
-// Interrupts 64..95
+// Interrupts 320..351
 //   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state
@@ -872,7 +872,7 @@
 #define NVIC_INIT_ITNS11   0
 
 /*
-// Interrupts 96..127
+// Interrupts 352..383
 //   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state
@@ -918,7 +918,7 @@
 #define NVIC_INIT_ITNS12   0
 
 /*
-// Interrupts 128..159
+// Interrupts 384..415
 //   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state
@@ -964,7 +964,7 @@
 #define NVIC_INIT_ITNS13   0
 
 /*
-// Interrupts 160..191
+// Interrupts 416..447
 //   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state
@@ -1010,7 +1010,7 @@
 #define NVIC_INIT_ITNS14   0
 
 /*
-// Interrupts 192..223
+// Interrupts 448..479
 //   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state
@@ -1056,7 +1056,7 @@
 #define NVIC_INIT_ITNS15   0
 
 /*
-// Interrupts 224..255
+// Interrupts 480..511
 //   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state

CMSIS/CoreValidation/Tests/Cortex-M33NS/GCC/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
- * @file     startup_ARMCM33.s
+ * @file     startup_ARMCM33.c
  * @brief    CMSIS Core Device Startup File for
- *           ARMCM33 Device Series
- * @version  V5.00
- * @date     21. October 2016
+ *           ARMCM33 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -23,6 +23,10 @@
  * limitations under the License.
  */
 
+/*
+ //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
 #include <stdint.h>
 
 
@@ -39,6 +43,7 @@ extern uint32_t __zero_table_end__;
 extern uint32_t __bss_start__;
 extern uint32_t __bss_end__;
 extern uint32_t __StackTop;
+extern uint32_t __StackLimit;
 
 /*----------------------------------------------------------------------------
   Exception / Interrupt Handler Function Prototype
@@ -49,35 +54,30 @@ typedef void( *pFunc )( void );
 /*----------------------------------------------------------------------------
   External References
  *----------------------------------------------------------------------------*/
-#ifndef __START
-extern void  _start(void) __attribute__((noreturn));    /* PreeMain (C library entry point) */
-#else
-extern int  __START(void) __attribute__((noreturn));    /* main entry point */
-#endif
-
-#ifndef __NO_SYSTEM_INIT
-extern void SystemInit (void);            /* CMSIS System Initialization      */
-#endif
+extern void _start     (void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
+extern void SystemInit (void);                           /* CMSIS System Initialization */
 
 
 /*----------------------------------------------------------------------------
   Internal References
  *----------------------------------------------------------------------------*/
-void Default_Handler(void);                          /* Default empty handler */
-void Reset_Handler(void);                            /* Reset Handler */
+void Default_Handler(void) __attribute__ ((noreturn));
+void Reset_Handler  (void) __attribute__ ((noreturn));
 
 
 /*----------------------------------------------------------------------------
   User Initial Stack & Heap
  *----------------------------------------------------------------------------*/
-#ifndef __STACK_SIZE
-  #define	__STACK_SIZE  0x00000400
-#endif
+//<h> Stack Configuration
+//  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//</h>
+#define  __STACK_SIZE  0x00000400
 static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack")));
 
-#ifndef __HEAP_SIZE
-  #define	__HEAP_SIZE   0x00000C00
-#endif
+//<h> Heap Configuration
+//  <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//</h>
+#define  __HEAP_SIZE   0x00000C00
 #if __HEAP_SIZE > 0
 static uint8_t heap[__HEAP_SIZE]   __attribute__ ((aligned(8), used, section(".heap")));
 #endif
@@ -86,99 +86,64 @@ static uint8_t heap[__HEAP_SIZE]   __attribute__ ((aligned(8), used, section(".h
 /*----------------------------------------------------------------------------
   Exception / Interrupt Handler
  *----------------------------------------------------------------------------*/
-/* ARMCM33 Processor Exceptions */
-void NMI_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
-void HardFault_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
-void MemManage_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
-void BusFault_Handler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UsageFault_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
-void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void SVC_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
-void DebugMon_Handler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void PendSV_Handler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void SysTick_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
-
-/* ARMCM33 Specific Interrupts */
-void WDT_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void RTC_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM0_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM2_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIA_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIB_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART0_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART1_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART2_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART4_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void AACI_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void CLCD_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void ENET_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBDC_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBHC_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void CHLCD_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void FLEXRAY_IRQHandler  (void) __attribute__ ((weak, alias("Default_Handler")));
-void CAN_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void LIN_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void I2C_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void CPU_CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART3_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void SPI_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+/* Exceptions */
+void NMI_Handler            (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void MemManage_Handler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler       (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void SecureFault_Handler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler            (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler       (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler        (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
 
 
 /*----------------------------------------------------------------------------
   Exception / Interrupt Vector table
  *----------------------------------------------------------------------------*/
-const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = {
-  /* ARMCM33 Exceptions Handler */
-  (pFunc)((uint32_t)&__StackTop),           /*      Initial Stack Pointer     */
-  Reset_Handler,                            /*      Reset Handler             */
-  NMI_Handler,                              /*      NMI Handler               */
-  HardFault_Handler,                        /*      Hard Fault Handler        */
-  MemManage_Handler,                        /*      MPU Fault Handler         */
-  BusFault_Handler,                         /*      Bus Fault Handler         */
-  UsageFault_Handler,                       /*      Usage Fault Handler       */
-  SecureFault_Handler,                      /*      Secure Fault Handler      */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  SVC_Handler,                              /*      SVCall Handler            */
-  DebugMon_Handler,                         /*      Debug Monitor Handler     */
-  0,                                        /*      Reserved                  */
-  PendSV_Handler,                           /*      PendSV Handler            */
-  SysTick_Handler,                          /*      SysTick Handler           */
-
-  /* External interrupts */
-  WDT_IRQHandler,                           /*  0:  Watchdog Timer            */
-  RTC_IRQHandler,                           /*  1:  Real Time Clock           */
-  TIM0_IRQHandler,                          /*  2:  Timer0 / Timer1           */
-  TIM2_IRQHandler,                          /*  3:  Timer2 / Timer3           */
-  MCIA_IRQHandler,                          /*  4:  MCIa                      */
-  MCIB_IRQHandler,                          /*  5:  MCIb                      */
-  UART0_IRQHandler,                         /*  6:  UART0 - DUT FPGA          */
-  UART1_IRQHandler,                         /*  7:  UART1 - DUT FPGA          */
-  UART2_IRQHandler,                         /*  8:  UART2 - DUT FPGA          */
-  UART4_IRQHandler,                         /*  9:  UART4 - not connected     */
-  AACI_IRQHandler,                          /* 10: AACI / AC97                */
-  CLCD_IRQHandler,                          /* 11: CLCD Combined Interrupt    */
-  ENET_IRQHandler,                          /* 12: Ethernet                   */
-  USBDC_IRQHandler,                         /* 13: USB Device                 */
-  USBHC_IRQHandler,                         /* 14: USB Host Controller        */
-  CHLCD_IRQHandler,                         /* 15: Character LCD              */
-  FLEXRAY_IRQHandler,                       /* 16: Flexray                    */
-  CAN_IRQHandler,                           /* 17: CAN                        */
-  LIN_IRQHandler,                           /* 18: LIN                        */
-  I2C_IRQHandler,                           /* 19: I2C ADC/DAC                */
-  0,                                        /* 20: Reserved                   */
-  0,                                        /* 21: Reserved                   */
-  0,                                        /* 22: Reserved                   */
-  0,                                        /* 23: Reserved                   */
-  0,                                        /* 24: Reserved                   */
-  0,                                        /* 25: Reserved                   */
-  0,                                        /* 26: Reserved                   */
-  0,                                        /* 27: Reserved                   */
-  CPU_CLCD_IRQHandler,                      /* 28: Reserved - CPU FPGA CLCD   */
-  0,                                        /* 29: Reserved - CPU FPGA        */
-  UART3_IRQHandler,                         /* 30: UART3    - CPU FPGA        */
-  SPI_IRQHandler                            /* 31: SPI Touchscreen - CPU FPGA */
+extern const pFunc __Vectors[496];
+       const pFunc __Vectors[496] __attribute__ ((section(".vectors"))) = {
+  (pFunc)(&__StackTop),                     /*     Initial Stack Pointer */
+  Reset_Handler,                            /*     Reset Handler */
+  NMI_Handler,                              /* -14 NMI Handler */
+  HardFault_Handler,                        /* -13 Hard Fault Handler */
+  MemManage_Handler,                        /* -12 MPU Fault Handler */
+  BusFault_Handler,                         /* -11 Bus Fault Handler */
+  UsageFault_Handler,                       /* -10 Usage Fault Handler */
+  SecureFault_Handler,                      /*  -9 Secure Fault Handler */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  SVC_Handler,                              /*  -5 SVCall Handler */
+  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */
+  0,                                        /*     Reserved */
+  PendSV_Handler,                           /*  -2 PendSV Handler */
+  SysTick_Handler,                          /*  -1 SysTick Handler */
+
+  /* Interrupts */
+  Interrupt0_Handler,                       /*   0 Interrupt 0 */
+  Interrupt1_Handler,                       /*   1 Interrupt 1 */
+  Interrupt2_Handler,                       /*   2 Interrupt 2 */
+  Interrupt3_Handler,                       /*   3 Interrupt 3 */
+  Interrupt4_Handler,                       /*   4 Interrupt 4 */
+  Interrupt5_Handler,                       /*   5 Interrupt 5 */
+  Interrupt6_Handler,                       /*   6 Interrupt 6 */
+  Interrupt7_Handler,                       /*   7 Interrupt 7 */
+  Interrupt8_Handler,                       /*   8 Interrupt 8 */
+  Interrupt9_Handler                        /*   9 Interrupt 9 */
+                                            /* Interrupts 10 .. 480 are left out */
 };
 
 
@@ -189,41 +154,42 @@ void Reset_Handler(void) {
   uint32_t *pSrc, *pDest;
   uint32_t *pTable __attribute__((unused));
 
-/*  Firstly it copies data from read only memory to RAM. There are two schemes
- *  to copy. One can copy more than one sections. Another can only copy
- *  one section.  The former scheme needs more instructions and read-only
- *  data to implement than the latter.
- *  Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.  */
+/* Firstly it copies data from read only memory to RAM.
+ * There are two schemes to copy. One can copy more than one sections.
+ * Another can copy only one section. The former scheme needs more
+ * instructions and read-only data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.
+ */
 
 #ifdef __STARTUP_COPY_MULTIPLE
-/*  Multiple sections scheme.
+/* Multiple sections scheme.
  *
- *  Between symbol address __copy_table_start__ and __copy_table_end__,
- *  there are array of triplets, each of which specify:
- *    offset 0: LMA of start of a section to copy from
- *    offset 4: VMA of start of a section to copy to
- *    offset 8: size of the section to copy. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ *   offset 0: LMA of start of a section to copy from
+ *   offset 4: VMA of start of a section to copy to
+ *   offset 8: size of the section to copy. Must be multiply of 4
  *
- *  All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
  */
   pTable = &__copy_table_start__;
 
   for (; pTable < &__copy_table_end__; pTable = pTable + 3) {
-		pSrc  = (uint32_t*)*(pTable + 0);
-		pDest = (uint32_t*)*(pTable + 1);
-		for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
+    pSrc  = (uint32_t*)*(pTable + 0);
+    pDest = (uint32_t*)*(pTable + 1);
+    for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
       *pDest++ = *pSrc++;
-		}
-	}
+    }
+  }
 #else
-/*  Single section scheme.
+/* Single section scheme.
  *
- *  The ranges of copy from/to are specified by following symbols
- *    __etext: LMA of start of the section to copy from. Usually end of text
- *    __data_start__: VMA of start of the section to copy to
- *    __data_end__: VMA of end of the section to copy to
+ * The ranges of copy from/to are specified by following symbols
+ *   __etext: LMA of start of the section to copy from. Usually end of text
+ *   __data_start__: VMA of start of the section to copy to
+ *   __data_end__: VMA of end of the section to copy to
  *
- *  All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
  */
   pSrc  = &__etext;
   pDest = &__data_start__;
@@ -233,40 +199,40 @@ void Reset_Handler(void) {
   }
 #endif /*__STARTUP_COPY_MULTIPLE */
 
-/*  This part of work usually is done in C library startup code. Otherwise,
- *  define this macro to enable it in this startup.
+/* This part of work usually is done in C library startup code.
+ * Otherwise, define this macro to enable it in this startup.
  *
- *  There are two schemes too. One can clear multiple BSS sections. Another
- *  can only clear one section. The former is more size expensive than the
- *  latter.
+ * There are two schemes too.
+ * One can clear multiple BSS sections. Another can only clear one section.
+ * The former is more size expensive than the latter.
  *
- *  Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- *  Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
  */
 #ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/*  Multiple sections scheme.
+/* Multiple sections scheme.
  *
- *  Between symbol address __copy_table_start__ and __copy_table_end__,
- *  there are array of tuples specifying:
- *    offset 0: Start of a BSS section
- *    offset 4: Size of this BSS section. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ *   offset 0: Start of a BSS section
+ *   offset 4: Size of this BSS section. Must be multiply of 4
  */
   pTable = &__zero_table_start__;
 
   for (; pTable < &__zero_table_end__; pTable = pTable + 2) {
-		pDest = (uint32_t*)*(pTable + 0);
-		for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
+    pDest = (uint32_t*)*(pTable + 0);
+    for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
       *pDest++ = 0;
-		}
-	}
+    }
+  }
 #elif defined (__STARTUP_CLEAR_BSS)
-/*  Single BSS section scheme.
+/* Single BSS section scheme.
  *
- *  The BSS section is specified by following symbols
- *    __bss_start__: start of the BSS section.
- *    __bss_end__: end of the BSS section.
+ * The BSS section is specified by following symbols
+ *   __bss_start__: start of the BSS section.
+ *   __bss_end__: end of the BSS section.
  *
- *  Both addresses must be aligned to 4 bytes boundary.
+ * Both addresses must be aligned to 4 bytes boundary.
  */
   pDest = &__bss_start__;
 
@@ -275,15 +241,10 @@ void Reset_Handler(void) {
   }
 #endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
 
-#ifndef __NO_SYSTEM_INIT
-	SystemInit();
-#endif
-
-#ifndef __START
-#define __START _start
-#endif
-	__START();
+  __set_MSPLIM((uint32_t)&__StackLimit);
 
+  SystemInit();                             /* CMSIS System Initialization */
+  _start();                                 /* Enter PreeMain (C library entry point) */
 }
 
 
@@ -292,5 +253,5 @@ void Reset_Handler(void) {
  *----------------------------------------------------------------------------*/
 void Default_Handler(void) {
 
-	while(1);
+  while(1);
 }

CMSIS/CoreValidation/Tests/Cortex-M33NS/GCC/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
  * @file     system_ARMCM33.c
  * @brief    CMSIS Device System Source File for
- *           ARMCM33 Device Series
- * @version  V5.00
- * @date     02. November 2016
+ *           ARMCM33 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -46,9 +46,9 @@
 /*----------------------------------------------------------------------------
   Define clocks
  *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+#define  XTAL            (50000000UL)     /* Oscillator frequency */
 
-#define  SYSTEM_CLOCK    (5U * XTAL)
+#define  SYSTEM_CLOCK    (XTAL / 2U)
 
 
 /*----------------------------------------------------------------------------
@@ -61,7 +61,7 @@
 /*----------------------------------------------------------------------------
   System Core Clock Variable
  *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */
 
 
 /*----------------------------------------------------------------------------

CMSIS/CoreValidation/Tests/Cortex-M33NS/IAR/Bootloader/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     partition_ARMCM33.h
  * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM33
- * @version  V5.0.1
- * @date     07. December 2016
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -734,7 +734,7 @@
 #define NVIC_INIT_ITNS8    0
 
 /*
-// Interrupts 0..31
+// Interrupts 256..287
 //   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state
@@ -780,7 +780,7 @@
 #define NVIC_INIT_ITNS9    0
 
 /*
-// Interrupts 32..63
+// Interrupts 288..319
 //   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state
@@ -826,7 +826,7 @@
 #define NVIC_INIT_ITNS10   0
 
 /*
-// Interrupts 64..95
+// Interrupts 320..351
 //   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state
@@ -872,7 +872,7 @@
 #define NVIC_INIT_ITNS11   0
 
 /*
-// Interrupts 96..127
+// Interrupts 352..383
 //   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state
@@ -918,7 +918,7 @@
 #define NVIC_INIT_ITNS12   0
 
 /*
-// Interrupts 128..159
+// Interrupts 384..415
 //   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state
@@ -964,7 +964,7 @@
 #define NVIC_INIT_ITNS13   0
 
 /*
-// Interrupts 160..191
+// Interrupts 416..447
 //   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state
@@ -1010,7 +1010,7 @@
 #define NVIC_INIT_ITNS14   0
 
 /*
-// Interrupts 192..223
+// Interrupts 448..479
 //   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state
@@ -1056,7 +1056,7 @@
 #define NVIC_INIT_ITNS15   0
 
 /*
-// Interrupts 224..255
+// Interrupts 480..511
 //   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state

CMSIS/CoreValidation/Tests/Cortex-M33NS/IAR/Bootloader/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.s

@@ -1,12 +1,12 @@
 ;/**************************************************************************//**
 ; * @file     startup_ARMCM33.s
 ; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM33 Device Series
-; * @version  V5.00
-; * @date     21. October 2016
+; *           ARMCM33 Device
+; * @version  V5.3.1
+; * @date     09. July 2018
 ; ******************************************************************************/
 ;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
 ; *
 ; * SPDX-License-Identifier: Apache-2.0
 ; *
@@ -39,259 +39,119 @@
 ; Cortex-M version
 ;
 
-        MODULE  ?cstartup
+                MODULE   ?cstartup
 
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
+                ;; Forward declaration of sections.
+                SECTION  CSTACK:DATA:NOROOT(3)
 
-        SECTION .intvec:CODE:NOROOT(2)
+                SECTION  .intvec:CODE:NOROOT(2)
 
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit
-        PUBLIC  __vector_table
-        PUBLIC  __vector_table_0x1c
-        PUBLIC  __Vectors
-        PUBLIC  __Vectors_End
-        PUBLIC  __Vectors_Size
+                EXTERN   __iar_program_start
+                EXTERN   SystemInit
+                PUBLIC   __vector_table
+                PUBLIC   __vector_table_0x1c
+                PUBLIC   __Vectors
+                PUBLIC   __Vectors_End
+                PUBLIC   __Vectors_Size
 
-        DATA
+                DATA
 
 __vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler
-
-        DCD     NMI_Handler
-        DCD     HardFault_Handler
-        DCD     MemManage_Handler
-        DCD     BusFault_Handler
-        DCD     UsageFault_Handler
+                DCD      sfe(CSTACK)                         ;     Top of Stack
+                DCD      Reset_Handler                       ;     Reset Handler
+                DCD      NMI_Handler                         ; -14 NMI Handler
+                DCD      HardFault_Handler                   ; -13 Hard Fault Handler
+                DCD      MemManage_Handler                   ; -12 MPU Fault Handler
+                DCD      BusFault_Handler                    ; -11 Bus Fault Handler
+                DCD      UsageFault_Handler                  ; -10 Usage Fault Handler
 __vector_table_0x1c
-        DCD     SecureFault_Handler
-        DCD     0
-        DCD     0
-        DCD     0
-        DCD     SVC_Handler
-        DCD     DebugMon_Handler
-        DCD     0
-        DCD     PendSV_Handler
-        DCD     SysTick_Handler
-
-        ; External Interrupts
-        DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
-        DCD     RTC_IRQHandler            ;  1:  Real Time Clock
-        DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
-        DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
-        DCD     MCIA_IRQHandler           ;  4:  MCIa
-        DCD     MCIB_IRQHandler           ;  5:  MCIb
-        DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
-        DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
-        DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
-        DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
-        DCD     AACI_IRQHandler           ; 10: AACI / AC97
-        DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
-        DCD     ENET_IRQHandler           ; 12: Ethernet
-        DCD     USBDC_IRQHandler          ; 13: USB Device
-        DCD     USBHC_IRQHandler          ; 14: USB Host Controller
-        DCD     CHLCD_IRQHandler          ; 15: Character LCD
-        DCD     FLEXRAY_IRQHandler        ; 16: Flexray
-        DCD     CAN_IRQHandler            ; 17: CAN
-        DCD     LIN_IRQHandler            ; 18: LIN
-        DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
-        DCD     0                         ; 20: Reserved
-        DCD     0                         ; 21: Reserved
-        DCD     0                         ; 22: Reserved
-        DCD     0                         ; 23: Reserved
-        DCD     0                         ; 24: Reserved
-        DCD     0                         ; 25: Reserved
-        DCD     0                         ; 26: Reserved
-        DCD     0                         ; 27: Reserved
-        DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
-        DCD     0                         ; 29: Reserved - CPU FPGA
-        DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
-        DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
+                DCD      SecureFault_Handler                 ;  -9 Security Fault Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      SVC_Handler                         ;  -5 SVCall Handler
+                DCD      DebugMon_Handler                    ;  -4 Debug Monitor Handler
+                DCD      0                                   ;     Reserved
+                DCD      PendSV_Handler                      ;  -2 PendSV Handler
+                DCD      SysTick_Handler                     ;  -1 SysTick Handler
+
+                ; Interrupts
+                DCD      Interrupt0_Handler                  ;   0 Interrupt 0
+                DCD      Interrupt1_Handler                  ;   1 Interrupt 1
+                DCD      Interrupt2_Handler                  ;   2 Interrupt 2
+                DCD      Interrupt3_Handler                  ;   3 Interrupt 3
+                DCD      Interrupt4_Handler                  ;   4 Interrupt 4
+                DCD      Interrupt5_Handler                  ;   5 Interrupt 5
+                DCD      Interrupt6_Handler                  ;   6 Interrupt 6
+                DCD      Interrupt7_Handler                  ;   7 Interrupt 7
+                DCD      Interrupt8_Handler                  ;   8 Interrupt 8
+                DCD      Interrupt9_Handler                  ;   9 Interrupt 9
+
+                DS32    (470)                                ; Interrupts 10 .. 480 are left out
 __Vectors_End
 
-__Vectors       EQU   __vector_table
-__Vectors_Size  EQU   __Vectors_End - __Vectors
+__Vectors       EQU      __vector_table
+__Vectors_Size  EQU      __Vectors_End - __Vectors
 
 
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
+                THUMB
 
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
+; Reset Handler
 
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
+                PUBWEAK  Reset_Handler
+                SECTION  .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+                LDR      R0, =SystemInit
+                BLX      R0
+                LDR      R0, =__iar_program_start
+                BX       R0
+
+
+                PUBWEAK NMI_Handler
+                PUBWEAK HardFault_Handler
+                PUBWEAK MemManage_Handler
+                PUBWEAK BusFault_Handler
+                PUBWEAK UsageFault_Handler
+                PUBWEAK SecureFault_Handler
+                PUBWEAK SVC_Handler
+                PUBWEAK DebugMon_Handler
+                PUBWEAK PendSV_Handler
+                PUBWEAK SysTick_Handler
+
+                PUBWEAK Interrupt0_Handler
+                PUBWEAK Interrupt1_Handler
+                PUBWEAK Interrupt2_Handler
+                PUBWEAK Interrupt3_Handler
+                PUBWEAK Interrupt4_Handler
+                PUBWEAK Interrupt5_Handler
+                PUBWEAK Interrupt6_Handler
+                PUBWEAK Interrupt7_Handler
+                PUBWEAK Interrupt8_Handler
+                PUBWEAK Interrupt9_Handler
+                SECTION .text:CODE:REORDER:NOROOT(1)
 NMI_Handler
-        B NMI_Handler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 HardFault_Handler
-        B HardFault_Handler
-
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 MemManage_Handler
-        B MemManage_Handler
-
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 BusFault_Handler
-        B BusFault_Handler
-
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 UsageFault_Handler
-        B UsageFault_Handler
-
-        PUBWEAK SecureFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 SecureFault_Handler
-        B SecureFault_Handler
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 SVC_Handler
-        B SVC_Handler
-
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 DebugMon_Handler
-        B DebugMon_Handler
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 SysTick_Handler
-        B SysTick_Handler
-
-        PUBWEAK WDT_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WDT_IRQHandler
-        B WDT_IRQHandler
-
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-
-        PUBWEAK TIM0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM0_IRQHandler
-        B TIM0_IRQHandler
-
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-
-        PUBWEAK MCIA_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MCIA_IRQHandler
-        B MCIA_IRQHandler
-
-        PUBWEAK MCIB_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MCIB_IRQHandler
-        B MCIB_IRQHandler
-
-        PUBWEAK UART0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART0_IRQHandler
-        B UART0_IRQHandler
-
-        PUBWEAK UART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART1_IRQHandler
-        B UART1_IRQHandler
-
-        PUBWEAK UART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART2_IRQHandler
-        B UART2_IRQHandler
-
-        PUBWEAK UART4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
-        B UART4_IRQHandler
-
-        PUBWEAK AACI_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-AACI_IRQHandler
-        B AACI_IRQHandler
-
-        PUBWEAK CLCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CLCD_IRQHandler
-        B CLCD_IRQHandler
-
-        PUBWEAK ENET_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ENET_IRQHandler
-        B ENET_IRQHandler
-
-        PUBWEAK USBDC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USBDC_IRQHandler
-        B USBDC_IRQHandler
-
-        PUBWEAK USBHC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USBHC_IRQHandler
-        B USBHC_IRQHandler
-
-        PUBWEAK CHLCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CHLCD_IRQHandler
-        B CHLCD_IRQHandler
-
-        PUBWEAK FLEXRAY_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLEXRAY_IRQHandler
-        B FLEXRAY_IRQHandler
-
-        PUBWEAK CAN_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN_IRQHandler
-        B CAN_IRQHandler
-
-        PUBWEAK LIN_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-LIN_IRQHandler
-        B LIN_IRQHandler
-
-        PUBWEAK I2C_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C_IRQHandler
-        B I2C_IRQHandler
-
-        PUBWEAK CPU_CLCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CPU_CLCD_IRQHandler
-        B CPU_CLCD_IRQHandler
-
-        PUBWEAK UART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART3_IRQHandler
-        B UART3_IRQHandler
-
-        PUBWEAK SPI_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI_IRQHandler
-        B SPI_IRQHandler
 
-        END
+Interrupt0_Handler
+Interrupt1_Handler
+Interrupt2_Handler
+Interrupt3_Handler
+Interrupt4_Handler
+Interrupt5_Handler
+Interrupt6_Handler
+Interrupt7_Handler
+Interrupt8_Handler
+Interrupt9_Handler
+Default_Handler
+                B        .
+
+
+                END

CMSIS/CoreValidation/Tests/Cortex-M33NS/IAR/Bootloader/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
  * @file     system_ARMCM33.c
  * @brief    CMSIS Device System Source File for
- *           ARMCM33 Device Series
- * @version  V5.00
- * @date     02. November 2016
+ *           ARMCM33 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -46,9 +46,9 @@
 /*----------------------------------------------------------------------------
   Define clocks
  *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+#define  XTAL            (50000000UL)     /* Oscillator frequency */
 
-#define  SYSTEM_CLOCK    (5U * XTAL)
+#define  SYSTEM_CLOCK    (XTAL / 2U)
 
 
 /*----------------------------------------------------------------------------
@@ -61,7 +61,7 @@
 /*----------------------------------------------------------------------------
   System Core Clock Variable
  *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */
 
 
 /*----------------------------------------------------------------------------

CMSIS/CoreValidation/Tests/Cortex-M33NS/IAR/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     partition_ARMCM33.h
  * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM33
- * @version  V5.0.1
- * @date     07. December 2016
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -734,7 +734,7 @@
 #define NVIC_INIT_ITNS8    0
 
 /*
-// Interrupts 0..31
+// Interrupts 256..287
 //   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state
@@ -780,7 +780,7 @@
 #define NVIC_INIT_ITNS9    0
 
 /*
-// Interrupts 32..63
+// Interrupts 288..319
 //   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state
@@ -826,7 +826,7 @@
 #define NVIC_INIT_ITNS10   0
 
 /*
-// Interrupts 64..95
+// Interrupts 320..351
 //   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state
@@ -872,7 +872,7 @@
 #define NVIC_INIT_ITNS11   0
 
 /*
-// Interrupts 96..127
+// Interrupts 352..383
 //   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state
@@ -918,7 +918,7 @@
 #define NVIC_INIT_ITNS12   0
 
 /*
-// Interrupts 128..159
+// Interrupts 384..415
 //   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state
@@ -964,7 +964,7 @@
 #define NVIC_INIT_ITNS13   0
 
 /*
-// Interrupts 160..191
+// Interrupts 416..447
 //   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state
@@ -1010,7 +1010,7 @@
 #define NVIC_INIT_ITNS14   0
 
 /*
-// Interrupts 192..223
+// Interrupts 448..479
 //   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state
@@ -1056,7 +1056,7 @@
 #define NVIC_INIT_ITNS15   0
 
 /*
-// Interrupts 224..255
+// Interrupts 480..511
 //   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state

CMSIS/CoreValidation/Tests/Cortex-M33NS/IAR/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.s

@@ -1,12 +1,12 @@
 ;/**************************************************************************//**
 ; * @file     startup_ARMCM33.s
 ; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM33 Device Series
-; * @version  V5.00
-; * @date     21. October 2016
+; *           ARMCM33 Device
+; * @version  V5.3.1
+; * @date     09. July 2018
 ; ******************************************************************************/
 ;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
 ; *
 ; * SPDX-License-Identifier: Apache-2.0
 ; *
@@ -39,259 +39,119 @@
 ; Cortex-M version
 ;
 
-        MODULE  ?cstartup
+                MODULE   ?cstartup
 
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
+                ;; Forward declaration of sections.
+                SECTION  CSTACK:DATA:NOROOT(3)
 
-        SECTION .intvec:CODE:NOROOT(2)
+                SECTION  .intvec:CODE:NOROOT(2)
 
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit
-        PUBLIC  __vector_table
-        PUBLIC  __vector_table_0x1c
-        PUBLIC  __Vectors
-        PUBLIC  __Vectors_End
-        PUBLIC  __Vectors_Size
+                EXTERN   __iar_program_start
+                EXTERN   SystemInit
+                PUBLIC   __vector_table
+                PUBLIC   __vector_table_0x1c
+                PUBLIC   __Vectors
+                PUBLIC   __Vectors_End
+                PUBLIC   __Vectors_Size
 
-        DATA
+                DATA
 
 __vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler
-
-        DCD     NMI_Handler
-        DCD     HardFault_Handler
-        DCD     MemManage_Handler
-        DCD     BusFault_Handler
-        DCD     UsageFault_Handler
+                DCD      sfe(CSTACK)                         ;     Top of Stack
+                DCD      Reset_Handler                       ;     Reset Handler
+                DCD      NMI_Handler                         ; -14 NMI Handler
+                DCD      HardFault_Handler                   ; -13 Hard Fault Handler
+                DCD      MemManage_Handler                   ; -12 MPU Fault Handler
+                DCD      BusFault_Handler                    ; -11 Bus Fault Handler
+                DCD      UsageFault_Handler                  ; -10 Usage Fault Handler
 __vector_table_0x1c
-        DCD     SecureFault_Handler
-        DCD     0
-        DCD     0
-        DCD     0
-        DCD     SVC_Handler
-        DCD     DebugMon_Handler
-        DCD     0
-        DCD     PendSV_Handler
-        DCD     SysTick_Handler
-
-        ; External Interrupts
-        DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
-        DCD     RTC_IRQHandler            ;  1:  Real Time Clock
-        DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
-        DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
-        DCD     MCIA_IRQHandler           ;  4:  MCIa
-        DCD     MCIB_IRQHandler           ;  5:  MCIb
-        DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
-        DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
-        DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
-        DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
-        DCD     AACI_IRQHandler           ; 10: AACI / AC97
-        DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
-        DCD     ENET_IRQHandler           ; 12: Ethernet
-        DCD     USBDC_IRQHandler          ; 13: USB Device
-        DCD     USBHC_IRQHandler          ; 14: USB Host Controller
-        DCD     CHLCD_IRQHandler          ; 15: Character LCD
-        DCD     FLEXRAY_IRQHandler        ; 16: Flexray
-        DCD     CAN_IRQHandler            ; 17: CAN
-        DCD     LIN_IRQHandler            ; 18: LIN
-        DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
-        DCD     0                         ; 20: Reserved
-        DCD     0                         ; 21: Reserved
-        DCD     0                         ; 22: Reserved
-        DCD     0                         ; 23: Reserved
-        DCD     0                         ; 24: Reserved
-        DCD     0                         ; 25: Reserved
-        DCD     0                         ; 26: Reserved
-        DCD     0                         ; 27: Reserved
-        DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
-        DCD     0                         ; 29: Reserved - CPU FPGA
-        DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
-        DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
+                DCD      SecureFault_Handler                 ;  -9 Security Fault Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      SVC_Handler                         ;  -5 SVCall Handler
+                DCD      DebugMon_Handler                    ;  -4 Debug Monitor Handler
+                DCD      0                                   ;     Reserved
+                DCD      PendSV_Handler                      ;  -2 PendSV Handler
+                DCD      SysTick_Handler                     ;  -1 SysTick Handler
+
+                ; Interrupts
+                DCD      Interrupt0_Handler                  ;   0 Interrupt 0
+                DCD      Interrupt1_Handler                  ;   1 Interrupt 1
+                DCD      Interrupt2_Handler                  ;   2 Interrupt 2
+                DCD      Interrupt3_Handler                  ;   3 Interrupt 3
+                DCD      Interrupt4_Handler                  ;   4 Interrupt 4
+                DCD      Interrupt5_Handler                  ;   5 Interrupt 5
+                DCD      Interrupt6_Handler                  ;   6 Interrupt 6
+                DCD      Interrupt7_Handler                  ;   7 Interrupt 7
+                DCD      Interrupt8_Handler                  ;   8 Interrupt 8
+                DCD      Interrupt9_Handler                  ;   9 Interrupt 9
+
+                DS32    (470)                                ; Interrupts 10 .. 480 are left out
 __Vectors_End
 
-__Vectors       EQU   __vector_table
-__Vectors_Size  EQU   __Vectors_End - __Vectors
+__Vectors       EQU      __vector_table
+__Vectors_Size  EQU      __Vectors_End - __Vectors
 
 
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
+                THUMB
 
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
+; Reset Handler
 
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
+                PUBWEAK  Reset_Handler
+                SECTION  .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+                LDR      R0, =SystemInit
+                BLX      R0
+                LDR      R0, =__iar_program_start
+                BX       R0
+
+
+                PUBWEAK NMI_Handler
+                PUBWEAK HardFault_Handler
+                PUBWEAK MemManage_Handler
+                PUBWEAK BusFault_Handler
+                PUBWEAK UsageFault_Handler
+                PUBWEAK SecureFault_Handler
+                PUBWEAK SVC_Handler
+                PUBWEAK DebugMon_Handler
+                PUBWEAK PendSV_Handler
+                PUBWEAK SysTick_Handler
+
+                PUBWEAK Interrupt0_Handler
+                PUBWEAK Interrupt1_Handler
+                PUBWEAK Interrupt2_Handler
+                PUBWEAK Interrupt3_Handler
+                PUBWEAK Interrupt4_Handler
+                PUBWEAK Interrupt5_Handler
+                PUBWEAK Interrupt6_Handler
+                PUBWEAK Interrupt7_Handler
+                PUBWEAK Interrupt8_Handler
+                PUBWEAK Interrupt9_Handler
+                SECTION .text:CODE:REORDER:NOROOT(1)
 NMI_Handler
-        B NMI_Handler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 HardFault_Handler
-        B HardFault_Handler
-
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 MemManage_Handler
-        B MemManage_Handler
-
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 BusFault_Handler
-        B BusFault_Handler
-
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 UsageFault_Handler
-        B UsageFault_Handler
-
-        PUBWEAK SecureFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 SecureFault_Handler
-        B SecureFault_Handler
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 SVC_Handler
-        B SVC_Handler
-
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 DebugMon_Handler
-        B DebugMon_Handler
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 SysTick_Handler
-        B SysTick_Handler
-
-        PUBWEAK WDT_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WDT_IRQHandler
-        B WDT_IRQHandler
-
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-
-        PUBWEAK TIM0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM0_IRQHandler
-        B TIM0_IRQHandler
-
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-
-        PUBWEAK MCIA_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MCIA_IRQHandler
-        B MCIA_IRQHandler
-
-        PUBWEAK MCIB_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MCIB_IRQHandler
-        B MCIB_IRQHandler
-
-        PUBWEAK UART0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART0_IRQHandler
-        B UART0_IRQHandler
-
-        PUBWEAK UART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART1_IRQHandler
-        B UART1_IRQHandler
-
-        PUBWEAK UART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART2_IRQHandler
-        B UART2_IRQHandler
-
-        PUBWEAK UART4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
-        B UART4_IRQHandler
-
-        PUBWEAK AACI_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-AACI_IRQHandler
-        B AACI_IRQHandler
-
-        PUBWEAK CLCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CLCD_IRQHandler
-        B CLCD_IRQHandler
-
-        PUBWEAK ENET_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ENET_IRQHandler
-        B ENET_IRQHandler
-
-        PUBWEAK USBDC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USBDC_IRQHandler
-        B USBDC_IRQHandler
-
-        PUBWEAK USBHC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USBHC_IRQHandler
-        B USBHC_IRQHandler
-
-        PUBWEAK CHLCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CHLCD_IRQHandler
-        B CHLCD_IRQHandler
-
-        PUBWEAK FLEXRAY_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLEXRAY_IRQHandler
-        B FLEXRAY_IRQHandler
-
-        PUBWEAK CAN_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN_IRQHandler
-        B CAN_IRQHandler
-
-        PUBWEAK LIN_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-LIN_IRQHandler
-        B LIN_IRQHandler
-
-        PUBWEAK I2C_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C_IRQHandler
-        B I2C_IRQHandler
-
-        PUBWEAK CPU_CLCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CPU_CLCD_IRQHandler
-        B CPU_CLCD_IRQHandler
-
-        PUBWEAK UART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART3_IRQHandler
-        B UART3_IRQHandler
-
-        PUBWEAK SPI_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI_IRQHandler
-        B SPI_IRQHandler
 
-        END
+Interrupt0_Handler
+Interrupt1_Handler
+Interrupt2_Handler
+Interrupt3_Handler
+Interrupt4_Handler
+Interrupt5_Handler
+Interrupt6_Handler
+Interrupt7_Handler
+Interrupt8_Handler
+Interrupt9_Handler
+Default_Handler
+                B        .
+
+
+                END

CMSIS/CoreValidation/Tests/Cortex-M33NS/IAR/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
  * @file     system_ARMCM33.c
  * @brief    CMSIS Device System Source File for
- *           ARMCM33 Device Series
- * @version  V5.00
- * @date     02. November 2016
+ *           ARMCM33 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -46,9 +46,9 @@
 /*----------------------------------------------------------------------------
   Define clocks
  *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+#define  XTAL            (50000000UL)     /* Oscillator frequency */
 
-#define  SYSTEM_CLOCK    (5U * XTAL)
+#define  SYSTEM_CLOCK    (XTAL / 2U)
 
 
 /*----------------------------------------------------------------------------
@@ -61,7 +61,7 @@
 /*----------------------------------------------------------------------------
   System Core Clock Variable
  *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */
 
 
 /*----------------------------------------------------------------------------

CMSIS/CoreValidation/Tests/Cortex-M33S/AC6/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     partition_ARMCM33.h
  * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM33
- * @version  V5.0.1
- * @date     07. December 2016
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -734,7 +734,7 @@
 #define NVIC_INIT_ITNS8    0
 
 /*
-// Interrupts 0..31
+// Interrupts 256..287
 //   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state
@@ -780,7 +780,7 @@
 #define NVIC_INIT_ITNS9    0
 
 /*
-// Interrupts 32..63
+// Interrupts 288..319
 //   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state
@@ -826,7 +826,7 @@
 #define NVIC_INIT_ITNS10   0
 
 /*
-// Interrupts 64..95
+// Interrupts 320..351
 //   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state
@@ -872,7 +872,7 @@
 #define NVIC_INIT_ITNS11   0
 
 /*
-// Interrupts 96..127
+// Interrupts 352..383
 //   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state
@@ -918,7 +918,7 @@
 #define NVIC_INIT_ITNS12   0
 
 /*
-// Interrupts 128..159
+// Interrupts 384..415
 //   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state
@@ -964,7 +964,7 @@
 #define NVIC_INIT_ITNS13   0
 
 /*
-// Interrupts 160..191
+// Interrupts 416..447
 //   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state
@@ -1010,7 +1010,7 @@
 #define NVIC_INIT_ITNS14   0
 
 /*
-// Interrupts 192..223
+// Interrupts 448..479
 //   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state
@@ -1056,7 +1056,7 @@
 #define NVIC_INIT_ITNS15   0
 
 /*
-// Interrupts 224..255
+// Interrupts 480..511
 //   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state

CMSIS/CoreValidation/Tests/Cortex-M33S/AC6/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.s

@@ -1,12 +1,12 @@
 ;/**************************************************************************//**
 ; * @file     startup_ARMCM33.s
 ; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM33 Device Series
-; * @version  V5.00
-; * @date     21. October 2016
+; *           ARMCM33 Device
+; * @version  V5.3.1
+; * @date     09. July 2018
 ; ******************************************************************************/
 ;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
 ; *
 ; * SPDX-License-Identifier: Apache-2.0
 ; *
@@ -23,32 +23,33 @@
 ; * limitations under the License.
 ; */
 
-;/*
 ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
 
 
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Stack Configuration
+;  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
 
-Stack_Size      EQU     0x00000400
+Stack_Size      EQU      0x00000400
 
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
+                AREA     STACK, NOINIT, READWRITE, ALIGN=3
+__stack_limit
+Stack_Mem       SPACE    Stack_Size
 __initial_sp
 
 
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Heap Configuration
+;  <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
 
-Heap_Size       EQU     0x00000C00
+Heap_Size       EQU      0x00000C00
 
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+                IF       Heap_Size != 0                      ; Heap is provided
+                AREA     HEAP, NOINIT, READWRITE, ALIGN=3
 __heap_base
-Heap_Mem        SPACE   Heap_Size
+Heap_Mem        SPACE    Heap_Size
 __heap_limit
+                ENDIF
 
 
                 PRESERVE8
@@ -57,211 +58,110 @@ __heap_limit
 
 ; Vector Table Mapped to Address 0 at Reset
 
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     SecureFault_Handler       ; Secure Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
-                DCD     RTC_IRQHandler            ;  1:  Real Time Clock
-                DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
-                DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
-                DCD     MCIA_IRQHandler           ;  4:  MCIa
-                DCD     MCIB_IRQHandler           ;  5:  MCIb
-                DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
-                DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
-                DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
-                DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
-                DCD     AACI_IRQHandler           ; 10: AACI / AC97
-                DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
-                DCD     ENET_IRQHandler           ; 12: Ethernet
-                DCD     USBDC_IRQHandler          ; 13: USB Device
-                DCD     USBHC_IRQHandler          ; 14: USB Host Controller
-                DCD     CHLCD_IRQHandler          ; 15: Character LCD
-                DCD     FLEXRAY_IRQHandler        ; 16: Flexray
-                DCD     CAN_IRQHandler            ; 17: CAN
-                DCD     LIN_IRQHandler            ; 18: LIN
-                DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
-                DCD     0                         ; 20: Reserved
-                DCD     0                         ; 21: Reserved
-                DCD     0                         ; 22: Reserved
-                DCD     0                         ; 23: Reserved
-                DCD     0                         ; 24: Reserved
-                DCD     0                         ; 25: Reserved
-                DCD     0                         ; 26: Reserved
-                DCD     0                         ; 27: Reserved
-                DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
-                DCD     0                         ; 29: Reserved - CPU FPGA
-                DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
-                DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
+                AREA     RESET, DATA, READONLY
+                EXPORT   __Vectors
+                EXPORT   __Vectors_End
+                EXPORT   __Vectors_Size
+
+__Vectors       DCD      __initial_sp                        ;     Top of Stack
+                DCD      Reset_Handler                       ;     Reset Handler
+                DCD      NMI_Handler                         ; -14 NMI Handler
+                DCD      HardFault_Handler                   ; -13 Hard Fault Handler
+                DCD      MemManage_Handler                   ; -12 MPU Fault Handler
+                DCD      BusFault_Handler                    ; -11 Bus Fault Handler
+                DCD      UsageFault_Handler                  ; -10 Usage Fault Handler
+                DCD      SecureFault_Handler                 ;  -9 Secure Fault Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      SVC_Handler                         ;  -5 SVCall Handler
+                DCD      DebugMon_Handler                    ;  -4 Debug Monitor Handler
+                DCD      0                                   ;     Reserved
+                DCD      PendSV_Handler                      ;  -2 PendSV Handler
+                DCD      SysTick_Handler                     ;  -1 SysTick Handler
+
+                ; Interrupts
+                DCD      Interrupt0_Handler                  ;   0 Interrupt 0
+                DCD      Interrupt1_Handler                  ;   1 Interrupt 1
+                DCD      Interrupt2_Handler                  ;   2 Interrupt 2
+                DCD      Interrupt3_Handler                  ;   3 Interrupt 3
+                DCD      Interrupt4_Handler                  ;   4 Interrupt 4
+                DCD      Interrupt5_Handler                  ;   5 Interrupt 5
+                DCD      Interrupt6_Handler                  ;   6 Interrupt 6
+                DCD      Interrupt7_Handler                  ;   7 Interrupt 7
+                DCD      Interrupt8_Handler                  ;   8 Interrupt 8
+                DCD      Interrupt9_Handler                  ;   9 Interrupt 9
+
+                SPACE    (470 * 4)                           ; Interrupts 10 .. 480 are left out
 __Vectors_End
+__Vectors_Size  EQU      __Vectors_End - __Vectors
 
-__Vectors_Size  EQU     __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
 
+                AREA     |.text|, CODE, READONLY
 
 ; Reset Handler
 
 Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  SystemInit
-                IMPORT  __main
-                LDR     R0, =SystemInit
-                BLX     R0
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-
+                EXPORT   Reset_Handler             [WEAK]
+                IMPORT   SystemInit
+                IMPORT   __main
 
-; Dummy Exception Handlers (infinite loops which can be modified)
+                LDR      R0, =__stack_limit
+                MSR      MSPLIM, R0                          ; Non-secure version of MSPLIM is RAZ/WI
 
-NMI_Handler     PROC
-                EXPORT  NMI_Handler               [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler         [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler          [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler        [WEAK]
-                B       .
-                ENDP
-SecureFault_Handler\
-                PROC
-                EXPORT  SecureFault_Handler       [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler          [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
+                LDR      R0, =SystemInit
+                BLX      R0
+                LDR      R0, =__main
+                BX       R0
                 ENDP
 
-Default_Handler PROC
-
-                EXPORT  WDT_IRQHandler            [WEAK]
-                EXPORT  RTC_IRQHandler            [WEAK]
-                EXPORT  TIM0_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler           [WEAK]
-                EXPORT  MCIA_IRQHandler           [WEAK]
-                EXPORT  MCIB_IRQHandler           [WEAK]
-                EXPORT  UART0_IRQHandler          [WEAK]
-                EXPORT  UART1_IRQHandler          [WEAK]
-                EXPORT  UART2_IRQHandler          [WEAK]
-                EXPORT  UART3_IRQHandler          [WEAK]
-                EXPORT  UART4_IRQHandler          [WEAK]
-                EXPORT  AACI_IRQHandler           [WEAK]
-                EXPORT  CLCD_IRQHandler           [WEAK]
-                EXPORT  ENET_IRQHandler           [WEAK]
-                EXPORT  USBDC_IRQHandler          [WEAK]
-                EXPORT  USBHC_IRQHandler          [WEAK]
-                EXPORT  CHLCD_IRQHandler          [WEAK]
-                EXPORT  FLEXRAY_IRQHandler        [WEAK]
-                EXPORT  CAN_IRQHandler            [WEAK]
-                EXPORT  LIN_IRQHandler            [WEAK]
-                EXPORT  I2C_IRQHandler            [WEAK]
-                EXPORT  CPU_CLCD_IRQHandler       [WEAK]
-                EXPORT  SPI_IRQHandler            [WEAK]
-
-WDT_IRQHandler
-RTC_IRQHandler
-TIM0_IRQHandler
-TIM2_IRQHandler
-MCIA_IRQHandler
-MCIB_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-UART3_IRQHandler
-UART4_IRQHandler
-AACI_IRQHandler
-CLCD_IRQHandler
-ENET_IRQHandler
-USBDC_IRQHandler
-USBHC_IRQHandler
-CHLCD_IRQHandler
-FLEXRAY_IRQHandler
-CAN_IRQHandler
-LIN_IRQHandler
-I2C_IRQHandler
-CPU_CLCD_IRQHandler
-SPI_IRQHandler
-                B       .
 
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+                MACRO
+                Set_Default_Handler  $Handler_Name
+$Handler_Name   PROC
+                EXPORT   $Handler_Name             [WEAK]
+                B        .
                 ENDP
-
+                MEND
+
+
+; Default exception/interrupt handler
+
+                Set_Default_Handler  NMI_Handler
+                Set_Default_Handler  HardFault_Handler
+                Set_Default_Handler  MemManage_Handler
+                Set_Default_Handler  BusFault_Handler
+                Set_Default_Handler  UsageFault_Handler
+                Set_Default_Handler  SecureFault_Handler
+                Set_Default_Handler  SVC_Handler
+                Set_Default_Handler  DebugMon_Handler
+                Set_Default_Handler  PendSV_Handler
+                Set_Default_Handler  SysTick_Handler
+
+                Set_Default_Handler  Interrupt0_Handler
+                Set_Default_Handler  Interrupt1_Handler
+                Set_Default_Handler  Interrupt2_Handler
+                Set_Default_Handler  Interrupt3_Handler
+                Set_Default_Handler  Interrupt4_Handler
+                Set_Default_Handler  Interrupt5_Handler
+                Set_Default_Handler  Interrupt6_Handler
+                Set_Default_Handler  Interrupt7_Handler
+                Set_Default_Handler  Interrupt8_Handler
+                Set_Default_Handler  Interrupt9_Handler
 
                 ALIGN
 
 
-; User Initial Stack & Heap
-
-                IF      :DEF:__MICROLIB
-
-                EXPORT  __initial_sp
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-
-                ELSE
-
-                IMPORT  __use_two_region_memory
-                EXPORT  __user_initial_stackheap
-
-__user_initial_stackheap PROC
-                LDR     R0, =  Heap_Mem
-                LDR     R1, =(Stack_Mem + Stack_Size)
-                LDR     R2, = (Heap_Mem +  Heap_Size)
-                LDR     R3, = Stack_Mem
-                BX      LR
-                ENDP
-
-                ALIGN
+; User setup Stack & Heap
 
+                EXPORT   __stack_limit
+                EXPORT   __initial_sp
+                IF       Heap_Size != 0                      ; Heap is provided
+                EXPORT   __heap_base
+                EXPORT   __heap_limit
                 ENDIF
 
-
                 END

CMSIS/CoreValidation/Tests/Cortex-M33S/AC6/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
  * @file     system_ARMCM33.c
  * @brief    CMSIS Device System Source File for
- *           ARMCM33 Device Series
- * @version  V5.00
- * @date     02. November 2016
+ *           ARMCM33 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -46,9 +46,9 @@
 /*----------------------------------------------------------------------------
   Define clocks
  *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+#define  XTAL            (50000000UL)     /* Oscillator frequency */
 
-#define  SYSTEM_CLOCK    (5U * XTAL)
+#define  SYSTEM_CLOCK    (XTAL / 2U)
 
 
 /*----------------------------------------------------------------------------
@@ -61,7 +61,7 @@
 /*----------------------------------------------------------------------------
   System Core Clock Variable
  *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */
 
 
 /*----------------------------------------------------------------------------

CMSIS/CoreValidation/Tests/Cortex-M33S/GCC/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     partition_ARMCM33.h
  * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM33
- * @version  V5.0.1
- * @date     07. December 2016
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -734,7 +734,7 @@
 #define NVIC_INIT_ITNS8    0
 
 /*
-// Interrupts 0..31
+// Interrupts 256..287
 //   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state
@@ -780,7 +780,7 @@
 #define NVIC_INIT_ITNS9    0
 
 /*
-// Interrupts 32..63
+// Interrupts 288..319
 //   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state
@@ -826,7 +826,7 @@
 #define NVIC_INIT_ITNS10   0
 
 /*
-// Interrupts 64..95
+// Interrupts 320..351
 //   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state
@@ -872,7 +872,7 @@
 #define NVIC_INIT_ITNS11   0
 
 /*
-// Interrupts 96..127
+// Interrupts 352..383
 //   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state
@@ -918,7 +918,7 @@
 #define NVIC_INIT_ITNS12   0
 
 /*
-// Interrupts 128..159
+// Interrupts 384..415
 //   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state
@@ -964,7 +964,7 @@
 #define NVIC_INIT_ITNS13   0
 
 /*
-// Interrupts 160..191
+// Interrupts 416..447
 //   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state
@@ -1010,7 +1010,7 @@
 #define NVIC_INIT_ITNS14   0
 
 /*
-// Interrupts 192..223
+// Interrupts 448..479
 //   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state
@@ -1056,7 +1056,7 @@
 #define NVIC_INIT_ITNS15   0
 
 /*
-// Interrupts 224..255
+// Interrupts 480..511
 //   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state

CMSIS/CoreValidation/Tests/Cortex-M33S/GCC/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
- * @file     startup_ARMCM33.s
+ * @file     startup_ARMCM33.c
  * @brief    CMSIS Core Device Startup File for
- *           ARMCM33 Device Series
- * @version  V5.00
- * @date     21. October 2016
+ *           ARMCM33 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -23,6 +23,10 @@
  * limitations under the License.
  */
 
+/*
+ //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
 #include <stdint.h>
 
 
@@ -39,6 +43,7 @@ extern uint32_t __zero_table_end__;
 extern uint32_t __bss_start__;
 extern uint32_t __bss_end__;
 extern uint32_t __StackTop;
+extern uint32_t __StackLimit;
 
 /*----------------------------------------------------------------------------
   Exception / Interrupt Handler Function Prototype
@@ -49,35 +54,30 @@ typedef void( *pFunc )( void );
 /*----------------------------------------------------------------------------
   External References
  *----------------------------------------------------------------------------*/
-#ifndef __START
-extern void  _start(void) __attribute__((noreturn));    /* PreeMain (C library entry point) */
-#else
-extern int  __START(void) __attribute__((noreturn));    /* main entry point */
-#endif
-
-#ifndef __NO_SYSTEM_INIT
-extern void SystemInit (void);            /* CMSIS System Initialization      */
-#endif
+extern void _start     (void) __attribute__((noreturn)); /* PreeMain (C library entry point) */
+extern void SystemInit (void);                           /* CMSIS System Initialization */
 
 
 /*----------------------------------------------------------------------------
   Internal References
  *----------------------------------------------------------------------------*/
-void Default_Handler(void);                          /* Default empty handler */
-void Reset_Handler(void);                            /* Reset Handler */
+void Default_Handler(void) __attribute__ ((noreturn));
+void Reset_Handler  (void) __attribute__ ((noreturn));
 
 
 /*----------------------------------------------------------------------------
   User Initial Stack & Heap
  *----------------------------------------------------------------------------*/
-#ifndef __STACK_SIZE
-  #define	__STACK_SIZE  0x00000400
-#endif
+//<h> Stack Configuration
+//  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//</h>
+#define  __STACK_SIZE  0x00000400
 static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack")));
 
-#ifndef __HEAP_SIZE
-  #define	__HEAP_SIZE   0x00000C00
-#endif
+//<h> Heap Configuration
+//  <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//</h>
+#define  __HEAP_SIZE   0x00000C00
 #if __HEAP_SIZE > 0
 static uint8_t heap[__HEAP_SIZE]   __attribute__ ((aligned(8), used, section(".heap")));
 #endif
@@ -86,99 +86,64 @@ static uint8_t heap[__HEAP_SIZE]   __attribute__ ((aligned(8), used, section(".h
 /*----------------------------------------------------------------------------
   Exception / Interrupt Handler
  *----------------------------------------------------------------------------*/
-/* ARMCM33 Processor Exceptions */
-void NMI_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
-void HardFault_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
-void MemManage_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
-void BusFault_Handler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UsageFault_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
-void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void SVC_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
-void DebugMon_Handler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void PendSV_Handler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void SysTick_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
-
-/* ARMCM33 Specific Interrupts */
-void WDT_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void RTC_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM0_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void TIM2_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIA_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void MCIB_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART0_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART1_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART2_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART4_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void AACI_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void CLCD_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void ENET_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBDC_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void USBHC_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void CHLCD_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void FLEXRAY_IRQHandler  (void) __attribute__ ((weak, alias("Default_Handler")));
-void CAN_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void LIN_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void I2C_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
-void CPU_CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
-void UART3_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
-void SPI_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+/* Exceptions */
+void NMI_Handler            (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void MemManage_Handler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler       (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void SecureFault_Handler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler            (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler       (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler        (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
 
 
 /*----------------------------------------------------------------------------
   Exception / Interrupt Vector table
  *----------------------------------------------------------------------------*/
-const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = {
-  /* ARMCM33 Exceptions Handler */
-  (pFunc)((uint32_t)&__StackTop),           /*      Initial Stack Pointer     */
-  Reset_Handler,                            /*      Reset Handler             */
-  NMI_Handler,                              /*      NMI Handler               */
-  HardFault_Handler,                        /*      Hard Fault Handler        */
-  MemManage_Handler,                        /*      MPU Fault Handler         */
-  BusFault_Handler,                         /*      Bus Fault Handler         */
-  UsageFault_Handler,                       /*      Usage Fault Handler       */
-  SecureFault_Handler,                      /*      Secure Fault Handler      */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  0,                                        /*      Reserved                  */
-  SVC_Handler,                              /*      SVCall Handler            */
-  DebugMon_Handler,                         /*      Debug Monitor Handler     */
-  0,                                        /*      Reserved                  */
-  PendSV_Handler,                           /*      PendSV Handler            */
-  SysTick_Handler,                          /*      SysTick Handler           */
-
-  /* External interrupts */
-  WDT_IRQHandler,                           /*  0:  Watchdog Timer            */
-  RTC_IRQHandler,                           /*  1:  Real Time Clock           */
-  TIM0_IRQHandler,                          /*  2:  Timer0 / Timer1           */
-  TIM2_IRQHandler,                          /*  3:  Timer2 / Timer3           */
-  MCIA_IRQHandler,                          /*  4:  MCIa                      */
-  MCIB_IRQHandler,                          /*  5:  MCIb                      */
-  UART0_IRQHandler,                         /*  6:  UART0 - DUT FPGA          */
-  UART1_IRQHandler,                         /*  7:  UART1 - DUT FPGA          */
-  UART2_IRQHandler,                         /*  8:  UART2 - DUT FPGA          */
-  UART4_IRQHandler,                         /*  9:  UART4 - not connected     */
-  AACI_IRQHandler,                          /* 10: AACI / AC97                */
-  CLCD_IRQHandler,                          /* 11: CLCD Combined Interrupt    */
-  ENET_IRQHandler,                          /* 12: Ethernet                   */
-  USBDC_IRQHandler,                         /* 13: USB Device                 */
-  USBHC_IRQHandler,                         /* 14: USB Host Controller        */
-  CHLCD_IRQHandler,                         /* 15: Character LCD              */
-  FLEXRAY_IRQHandler,                       /* 16: Flexray                    */
-  CAN_IRQHandler,                           /* 17: CAN                        */
-  LIN_IRQHandler,                           /* 18: LIN                        */
-  I2C_IRQHandler,                           /* 19: I2C ADC/DAC                */
-  0,                                        /* 20: Reserved                   */
-  0,                                        /* 21: Reserved                   */
-  0,                                        /* 22: Reserved                   */
-  0,                                        /* 23: Reserved                   */
-  0,                                        /* 24: Reserved                   */
-  0,                                        /* 25: Reserved                   */
-  0,                                        /* 26: Reserved                   */
-  0,                                        /* 27: Reserved                   */
-  CPU_CLCD_IRQHandler,                      /* 28: Reserved - CPU FPGA CLCD   */
-  0,                                        /* 29: Reserved - CPU FPGA        */
-  UART3_IRQHandler,                         /* 30: UART3    - CPU FPGA        */
-  SPI_IRQHandler                            /* 31: SPI Touchscreen - CPU FPGA */
+extern const pFunc __Vectors[496];
+       const pFunc __Vectors[496] __attribute__ ((section(".vectors"))) = {
+  (pFunc)(&__StackTop),                     /*     Initial Stack Pointer */
+  Reset_Handler,                            /*     Reset Handler */
+  NMI_Handler,                              /* -14 NMI Handler */
+  HardFault_Handler,                        /* -13 Hard Fault Handler */
+  MemManage_Handler,                        /* -12 MPU Fault Handler */
+  BusFault_Handler,                         /* -11 Bus Fault Handler */
+  UsageFault_Handler,                       /* -10 Usage Fault Handler */
+  SecureFault_Handler,                      /*  -9 Secure Fault Handler */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  0,                                        /*     Reserved */
+  SVC_Handler,                              /*  -5 SVCall Handler */
+  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */
+  0,                                        /*     Reserved */
+  PendSV_Handler,                           /*  -2 PendSV Handler */
+  SysTick_Handler,                          /*  -1 SysTick Handler */
+
+  /* Interrupts */
+  Interrupt0_Handler,                       /*   0 Interrupt 0 */
+  Interrupt1_Handler,                       /*   1 Interrupt 1 */
+  Interrupt2_Handler,                       /*   2 Interrupt 2 */
+  Interrupt3_Handler,                       /*   3 Interrupt 3 */
+  Interrupt4_Handler,                       /*   4 Interrupt 4 */
+  Interrupt5_Handler,                       /*   5 Interrupt 5 */
+  Interrupt6_Handler,                       /*   6 Interrupt 6 */
+  Interrupt7_Handler,                       /*   7 Interrupt 7 */
+  Interrupt8_Handler,                       /*   8 Interrupt 8 */
+  Interrupt9_Handler                        /*   9 Interrupt 9 */
+                                            /* Interrupts 10 .. 480 are left out */
 };
 
 
@@ -189,41 +154,42 @@ void Reset_Handler(void) {
   uint32_t *pSrc, *pDest;
   uint32_t *pTable __attribute__((unused));
 
-/*  Firstly it copies data from read only memory to RAM. There are two schemes
- *  to copy. One can copy more than one sections. Another can only copy
- *  one section.  The former scheme needs more instructions and read-only
- *  data to implement than the latter.
- *  Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.  */
+/* Firstly it copies data from read only memory to RAM.
+ * There are two schemes to copy. One can copy more than one sections.
+ * Another can copy only one section. The former scheme needs more
+ * instructions and read-only data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.
+ */
 
 #ifdef __STARTUP_COPY_MULTIPLE
-/*  Multiple sections scheme.
+/* Multiple sections scheme.
  *
- *  Between symbol address __copy_table_start__ and __copy_table_end__,
- *  there are array of triplets, each of which specify:
- *    offset 0: LMA of start of a section to copy from
- *    offset 4: VMA of start of a section to copy to
- *    offset 8: size of the section to copy. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ *   offset 0: LMA of start of a section to copy from
+ *   offset 4: VMA of start of a section to copy to
+ *   offset 8: size of the section to copy. Must be multiply of 4
  *
- *  All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
  */
   pTable = &__copy_table_start__;
 
   for (; pTable < &__copy_table_end__; pTable = pTable + 3) {
-		pSrc  = (uint32_t*)*(pTable + 0);
-		pDest = (uint32_t*)*(pTable + 1);
-		for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
+    pSrc  = (uint32_t*)*(pTable + 0);
+    pDest = (uint32_t*)*(pTable + 1);
+    for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
       *pDest++ = *pSrc++;
-		}
-	}
+    }
+  }
 #else
-/*  Single section scheme.
+/* Single section scheme.
  *
- *  The ranges of copy from/to are specified by following symbols
- *    __etext: LMA of start of the section to copy from. Usually end of text
- *    __data_start__: VMA of start of the section to copy to
- *    __data_end__: VMA of end of the section to copy to
+ * The ranges of copy from/to are specified by following symbols
+ *   __etext: LMA of start of the section to copy from. Usually end of text
+ *   __data_start__: VMA of start of the section to copy to
+ *   __data_end__: VMA of end of the section to copy to
  *
- *  All addresses must be aligned to 4 bytes boundary.
+ * All addresses must be aligned to 4 bytes boundary.
  */
   pSrc  = &__etext;
   pDest = &__data_start__;
@@ -233,40 +199,40 @@ void Reset_Handler(void) {
   }
 #endif /*__STARTUP_COPY_MULTIPLE */
 
-/*  This part of work usually is done in C library startup code. Otherwise,
- *  define this macro to enable it in this startup.
+/* This part of work usually is done in C library startup code.
+ * Otherwise, define this macro to enable it in this startup.
  *
- *  There are two schemes too. One can clear multiple BSS sections. Another
- *  can only clear one section. The former is more size expensive than the
- *  latter.
+ * There are two schemes too.
+ * One can clear multiple BSS sections. Another can only clear one section.
+ * The former is more size expensive than the latter.
  *
- *  Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- *  Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
  */
 #ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/*  Multiple sections scheme.
+/* Multiple sections scheme.
  *
- *  Between symbol address __copy_table_start__ and __copy_table_end__,
- *  there are array of tuples specifying:
- *    offset 0: Start of a BSS section
- *    offset 4: Size of this BSS section. Must be multiply of 4
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ *   offset 0: Start of a BSS section
+ *   offset 4: Size of this BSS section. Must be multiply of 4
  */
   pTable = &__zero_table_start__;
 
   for (; pTable < &__zero_table_end__; pTable = pTable + 2) {
-		pDest = (uint32_t*)*(pTable + 0);
-		for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
+    pDest = (uint32_t*)*(pTable + 0);
+    for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
       *pDest++ = 0;
-		}
-	}
+    }
+  }
 #elif defined (__STARTUP_CLEAR_BSS)
-/*  Single BSS section scheme.
+/* Single BSS section scheme.
  *
- *  The BSS section is specified by following symbols
- *    __bss_start__: start of the BSS section.
- *    __bss_end__: end of the BSS section.
+ * The BSS section is specified by following symbols
+ *   __bss_start__: start of the BSS section.
+ *   __bss_end__: end of the BSS section.
  *
- *  Both addresses must be aligned to 4 bytes boundary.
+ * Both addresses must be aligned to 4 bytes boundary.
  */
   pDest = &__bss_start__;
 
@@ -275,15 +241,10 @@ void Reset_Handler(void) {
   }
 #endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
 
-#ifndef __NO_SYSTEM_INIT
-	SystemInit();
-#endif
-
-#ifndef __START
-#define __START _start
-#endif
-	__START();
+  __set_MSPLIM((uint32_t)&__StackLimit);
 
+  SystemInit();                             /* CMSIS System Initialization */
+  _start();                                 /* Enter PreeMain (C library entry point) */
 }
 
 
@@ -292,5 +253,5 @@ void Reset_Handler(void) {
  *----------------------------------------------------------------------------*/
 void Default_Handler(void) {
 
-	while(1);
+  while(1);
 }

CMSIS/CoreValidation/Tests/Cortex-M33S/GCC/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
  * @file     system_ARMCM33.c
  * @brief    CMSIS Device System Source File for
- *           ARMCM33 Device Series
- * @version  V5.00
- * @date     02. November 2016
+ *           ARMCM33 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -46,9 +46,9 @@
 /*----------------------------------------------------------------------------
   Define clocks
  *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+#define  XTAL            (50000000UL)     /* Oscillator frequency */
 
-#define  SYSTEM_CLOCK    (5U * XTAL)
+#define  SYSTEM_CLOCK    (XTAL / 2U)
 
 
 /*----------------------------------------------------------------------------
@@ -61,7 +61,7 @@
 /*----------------------------------------------------------------------------
   System Core Clock Variable
  *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */
 
 
 /*----------------------------------------------------------------------------

CMSIS/CoreValidation/Tests/Cortex-M33S/IAR/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     partition_ARMCM33.h
  * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM33
- * @version  V5.0.1
- * @date     07. December 2016
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -734,7 +734,7 @@
 #define NVIC_INIT_ITNS8    0
 
 /*
-// Interrupts 0..31
+// Interrupts 256..287
 //   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state
@@ -780,7 +780,7 @@
 #define NVIC_INIT_ITNS9    0
 
 /*
-// Interrupts 32..63
+// Interrupts 288..319
 //   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state
@@ -826,7 +826,7 @@
 #define NVIC_INIT_ITNS10   0
 
 /*
-// Interrupts 64..95
+// Interrupts 320..351
 //   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state
@@ -872,7 +872,7 @@
 #define NVIC_INIT_ITNS11   0
 
 /*
-// Interrupts 96..127
+// Interrupts 352..383
 //   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state
@@ -918,7 +918,7 @@
 #define NVIC_INIT_ITNS12   0
 
 /*
-// Interrupts 128..159
+// Interrupts 384..415
 //   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state
@@ -964,7 +964,7 @@
 #define NVIC_INIT_ITNS13   0
 
 /*
-// Interrupts 160..191
+// Interrupts 416..447
 //   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state
@@ -1010,7 +1010,7 @@
 #define NVIC_INIT_ITNS14   0
 
 /*
-// Interrupts 192..223
+// Interrupts 448..479
 //   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state
@@ -1056,7 +1056,7 @@
 #define NVIC_INIT_ITNS15   0
 
 /*
-// Interrupts 224..255
+// Interrupts 480..511
 //   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state
 //   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state
 //   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state

CMSIS/CoreValidation/Tests/Cortex-M33S/IAR/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.s

@@ -1,12 +1,12 @@
 ;/**************************************************************************//**
 ; * @file     startup_ARMCM33.s
 ; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM33 Device Series
-; * @version  V5.00
-; * @date     21. October 2016
+; *           ARMCM33 Device
+; * @version  V5.3.1
+; * @date     09. July 2018
 ; ******************************************************************************/
 ;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
 ; *
 ; * SPDX-License-Identifier: Apache-2.0
 ; *
@@ -39,259 +39,119 @@
 ; Cortex-M version
 ;
 
-        MODULE  ?cstartup
+                MODULE   ?cstartup
 
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
+                ;; Forward declaration of sections.
+                SECTION  CSTACK:DATA:NOROOT(3)
 
-        SECTION .intvec:CODE:NOROOT(2)
+                SECTION  .intvec:CODE:NOROOT(2)
 
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit
-        PUBLIC  __vector_table
-        PUBLIC  __vector_table_0x1c
-        PUBLIC  __Vectors
-        PUBLIC  __Vectors_End
-        PUBLIC  __Vectors_Size
+                EXTERN   __iar_program_start
+                EXTERN   SystemInit
+                PUBLIC   __vector_table
+                PUBLIC   __vector_table_0x1c
+                PUBLIC   __Vectors
+                PUBLIC   __Vectors_End
+                PUBLIC   __Vectors_Size
 
-        DATA
+                DATA
 
 __vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler
-
-        DCD     NMI_Handler
-        DCD     HardFault_Handler
-        DCD     MemManage_Handler
-        DCD     BusFault_Handler
-        DCD     UsageFault_Handler
+                DCD      sfe(CSTACK)                         ;     Top of Stack
+                DCD      Reset_Handler                       ;     Reset Handler
+                DCD      NMI_Handler                         ; -14 NMI Handler
+                DCD      HardFault_Handler                   ; -13 Hard Fault Handler
+                DCD      MemManage_Handler                   ; -12 MPU Fault Handler
+                DCD      BusFault_Handler                    ; -11 Bus Fault Handler
+                DCD      UsageFault_Handler                  ; -10 Usage Fault Handler
 __vector_table_0x1c
-        DCD     SecureFault_Handler
-        DCD     0
-        DCD     0
-        DCD     0
-        DCD     SVC_Handler
-        DCD     DebugMon_Handler
-        DCD     0
-        DCD     PendSV_Handler
-        DCD     SysTick_Handler
-
-        ; External Interrupts
-        DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
-        DCD     RTC_IRQHandler            ;  1:  Real Time Clock
-        DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
-        DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
-        DCD     MCIA_IRQHandler           ;  4:  MCIa
-        DCD     MCIB_IRQHandler           ;  5:  MCIb
-        DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
-        DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
-        DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
-        DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
-        DCD     AACI_IRQHandler           ; 10: AACI / AC97
-        DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
-        DCD     ENET_IRQHandler           ; 12: Ethernet
-        DCD     USBDC_IRQHandler          ; 13: USB Device
-        DCD     USBHC_IRQHandler          ; 14: USB Host Controller
-        DCD     CHLCD_IRQHandler          ; 15: Character LCD
-        DCD     FLEXRAY_IRQHandler        ; 16: Flexray
-        DCD     CAN_IRQHandler            ; 17: CAN
-        DCD     LIN_IRQHandler            ; 18: LIN
-        DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
-        DCD     0                         ; 20: Reserved
-        DCD     0                         ; 21: Reserved
-        DCD     0                         ; 22: Reserved
-        DCD     0                         ; 23: Reserved
-        DCD     0                         ; 24: Reserved
-        DCD     0                         ; 25: Reserved
-        DCD     0                         ; 26: Reserved
-        DCD     0                         ; 27: Reserved
-        DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
-        DCD     0                         ; 29: Reserved - CPU FPGA
-        DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
-        DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
+                DCD      SecureFault_Handler                 ;  -9 Security Fault Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      SVC_Handler                         ;  -5 SVCall Handler
+                DCD      DebugMon_Handler                    ;  -4 Debug Monitor Handler
+                DCD      0                                   ;     Reserved
+                DCD      PendSV_Handler                      ;  -2 PendSV Handler
+                DCD      SysTick_Handler                     ;  -1 SysTick Handler
+
+                ; Interrupts
+                DCD      Interrupt0_Handler                  ;   0 Interrupt 0
+                DCD      Interrupt1_Handler                  ;   1 Interrupt 1
+                DCD      Interrupt2_Handler                  ;   2 Interrupt 2
+                DCD      Interrupt3_Handler                  ;   3 Interrupt 3
+                DCD      Interrupt4_Handler                  ;   4 Interrupt 4
+                DCD      Interrupt5_Handler                  ;   5 Interrupt 5
+                DCD      Interrupt6_Handler                  ;   6 Interrupt 6
+                DCD      Interrupt7_Handler                  ;   7 Interrupt 7
+                DCD      Interrupt8_Handler                  ;   8 Interrupt 8
+                DCD      Interrupt9_Handler                  ;   9 Interrupt 9
+
+                DS32    (470)                                ; Interrupts 10 .. 480 are left out
 __Vectors_End
 
-__Vectors       EQU   __vector_table
-__Vectors_Size  EQU   __Vectors_End - __Vectors
+__Vectors       EQU      __vector_table
+__Vectors_Size  EQU      __Vectors_End - __Vectors
 
 
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
+                THUMB
 
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
+; Reset Handler
 
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
+                PUBWEAK  Reset_Handler
+                SECTION  .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+                LDR      R0, =SystemInit
+                BLX      R0
+                LDR      R0, =__iar_program_start
+                BX       R0
+
+
+                PUBWEAK NMI_Handler
+                PUBWEAK HardFault_Handler
+                PUBWEAK MemManage_Handler
+                PUBWEAK BusFault_Handler
+                PUBWEAK UsageFault_Handler
+                PUBWEAK SecureFault_Handler
+                PUBWEAK SVC_Handler
+                PUBWEAK DebugMon_Handler
+                PUBWEAK PendSV_Handler
+                PUBWEAK SysTick_Handler
+
+                PUBWEAK Interrupt0_Handler
+                PUBWEAK Interrupt1_Handler
+                PUBWEAK Interrupt2_Handler
+                PUBWEAK Interrupt3_Handler
+                PUBWEAK Interrupt4_Handler
+                PUBWEAK Interrupt5_Handler
+                PUBWEAK Interrupt6_Handler
+                PUBWEAK Interrupt7_Handler
+                PUBWEAK Interrupt8_Handler
+                PUBWEAK Interrupt9_Handler
+                SECTION .text:CODE:REORDER:NOROOT(1)
 NMI_Handler
-        B NMI_Handler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 HardFault_Handler
-        B HardFault_Handler
-
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 MemManage_Handler
-        B MemManage_Handler
-
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 BusFault_Handler
-        B BusFault_Handler
-
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 UsageFault_Handler
-        B UsageFault_Handler
-
-        PUBWEAK SecureFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 SecureFault_Handler
-        B SecureFault_Handler
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 SVC_Handler
-        B SVC_Handler
-
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 DebugMon_Handler
-        B DebugMon_Handler
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
 SysTick_Handler
-        B SysTick_Handler
-
-        PUBWEAK WDT_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WDT_IRQHandler
-        B WDT_IRQHandler
-
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-
-        PUBWEAK TIM0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM0_IRQHandler
-        B TIM0_IRQHandler
-
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-
-        PUBWEAK MCIA_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MCIA_IRQHandler
-        B MCIA_IRQHandler
-
-        PUBWEAK MCIB_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MCIB_IRQHandler
-        B MCIB_IRQHandler
-
-        PUBWEAK UART0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART0_IRQHandler
-        B UART0_IRQHandler
-
-        PUBWEAK UART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART1_IRQHandler
-        B UART1_IRQHandler
-
-        PUBWEAK UART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART2_IRQHandler
-        B UART2_IRQHandler
-
-        PUBWEAK UART4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
-        B UART4_IRQHandler
-
-        PUBWEAK AACI_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-AACI_IRQHandler
-        B AACI_IRQHandler
-
-        PUBWEAK CLCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CLCD_IRQHandler
-        B CLCD_IRQHandler
-
-        PUBWEAK ENET_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ENET_IRQHandler
-        B ENET_IRQHandler
-
-        PUBWEAK USBDC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USBDC_IRQHandler
-        B USBDC_IRQHandler
-
-        PUBWEAK USBHC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USBHC_IRQHandler
-        B USBHC_IRQHandler
-
-        PUBWEAK CHLCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CHLCD_IRQHandler
-        B CHLCD_IRQHandler
-
-        PUBWEAK FLEXRAY_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLEXRAY_IRQHandler
-        B FLEXRAY_IRQHandler
-
-        PUBWEAK CAN_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN_IRQHandler
-        B CAN_IRQHandler
-
-        PUBWEAK LIN_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-LIN_IRQHandler
-        B LIN_IRQHandler
-
-        PUBWEAK I2C_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C_IRQHandler
-        B I2C_IRQHandler
-
-        PUBWEAK CPU_CLCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CPU_CLCD_IRQHandler
-        B CPU_CLCD_IRQHandler
-
-        PUBWEAK UART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART3_IRQHandler
-        B UART3_IRQHandler
-
-        PUBWEAK SPI_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI_IRQHandler
-        B SPI_IRQHandler
 
-        END
+Interrupt0_Handler
+Interrupt1_Handler
+Interrupt2_Handler
+Interrupt3_Handler
+Interrupt4_Handler
+Interrupt5_Handler
+Interrupt6_Handler
+Interrupt7_Handler
+Interrupt8_Handler
+Interrupt9_Handler
+Default_Handler
+                B        .
+
+
+                END

CMSIS/CoreValidation/Tests/Cortex-M33S/IAR/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
  * @file     system_ARMCM33.c
  * @brief    CMSIS Device System Source File for
- *           ARMCM33 Device Series
- * @version  V5.00
- * @date     02. November 2016
+ *           ARMCM33 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -46,9 +46,9 @@
 /*----------------------------------------------------------------------------
   Define clocks
  *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+#define  XTAL            (50000000UL)     /* Oscillator frequency */
 
-#define  SYSTEM_CLOCK    (5U * XTAL)
+#define  SYSTEM_CLOCK    (XTAL / 2U)
 
 
 /*----------------------------------------------------------------------------
@@ -61,7 +61,7 @@
 /*----------------------------------------------------------------------------
   System Core Clock Variable
  *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */
 
 
 /*----------------------------------------------------------------------------

CMSIS/CoreValidation/Tests/Cortex-M4/AC5/RTE/Device/ARMCM4/startup_ARMCM4.s

@@ -1,12 +1,12 @@
 ;/**************************************************************************//**
 ; * @file     startup_ARMCM4.s
 ; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM4 Device Series
-; * @version  V5.00
-; * @date     02. March 2016
+; *           ARMCM4 Device
+; * @version  V5.3.1
+; * @date     09. July 2018
 ; ******************************************************************************/
 ;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
 ; *
 ; * SPDX-License-Identifier: Apache-2.0
 ; *
@@ -23,32 +23,33 @@
 ; * limitations under the License.
 ; */
 
-;/*
 ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
 
 
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Stack Configuration
+;  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
 
-Stack_Size      EQU     0x00000400
+Stack_Size      EQU      0x00000400
 
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
+                AREA     STACK, NOINIT, READWRITE, ALIGN=3
+__stack_limit
+Stack_Mem       SPACE    Stack_Size
 __initial_sp
 
 
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Heap Configuration
+;  <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
 
-Heap_Size       EQU     0x00000C00
+Heap_Size       EQU      0x00000C00
 
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+                IF       Heap_Size != 0                      ; Heap is provided
+                AREA     HEAP, NOINIT, READWRITE, ALIGN=3
 __heap_base
-Heap_Mem        SPACE   Heap_Size
+Heap_Mem        SPACE    Heap_Size
 __heap_limit
+                ENDIF
 
 
                 PRESERVE8
@@ -57,206 +58,106 @@ __heap_limit
 
 ; Vector Table Mapped to Address 0 at Reset
 
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
-                DCD     RTC_IRQHandler            ;  1:  Real Time Clock
-                DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
-                DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
-                DCD     MCIA_IRQHandler           ;  4:  MCIa
-                DCD     MCIB_IRQHandler           ;  5:  MCIb
-                DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
-                DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
-                DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
-                DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
-                DCD     AACI_IRQHandler           ; 10: AACI / AC97
-                DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
-                DCD     ENET_IRQHandler           ; 12: Ethernet
-                DCD     USBDC_IRQHandler          ; 13: USB Device
-                DCD     USBHC_IRQHandler          ; 14: USB Host Controller
-                DCD     CHLCD_IRQHandler          ; 15: Character LCD
-                DCD     FLEXRAY_IRQHandler        ; 16: Flexray
-                DCD     CAN_IRQHandler            ; 17: CAN
-                DCD     LIN_IRQHandler            ; 18: LIN
-                DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
-                DCD     0                         ; 20: Reserved
-                DCD     0                         ; 21: Reserved
-                DCD     0                         ; 22: Reserved
-                DCD     0                         ; 23: Reserved
-                DCD     0                         ; 24: Reserved
-                DCD     0                         ; 25: Reserved
-                DCD     0                         ; 26: Reserved
-                DCD     0                         ; 27: Reserved
-                DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
-                DCD     0                         ; 29: Reserved - CPU FPGA
-                DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
-                DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
+                AREA     RESET, DATA, READONLY
+                EXPORT   __Vectors
+                EXPORT   __Vectors_End
+                EXPORT   __Vectors_Size
+
+__Vectors       DCD      __initial_sp                        ;     Top of Stack
+                DCD      Reset_Handler                       ;     Reset Handler
+                DCD      NMI_Handler                         ; -14 NMI Handler
+                DCD      HardFault_Handler                   ; -13 Hard Fault Handler
+                DCD      MemManage_Handler                   ; -12 MPU Fault Handler
+                DCD      BusFault_Handler                    ; -11 Bus Fault Handler
+                DCD      UsageFault_Handler                  ; -10 Usage Fault Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      SVC_Handler                         ;  -5 SVCall Handler
+                DCD      DebugMon_Handler                    ;  -4 Debug Monitor Handler
+                DCD      0                                   ;     Reserved
+                DCD      PendSV_Handler                      ;  -2 PendSV Handler
+                DCD      SysTick_Handler                     ;  -1 SysTick Handler
+
+                ; Interrupts
+                DCD      Interrupt0_Handler                  ;   0 Interrupt 0
+                DCD      Interrupt1_Handler                  ;   1 Interrupt 1
+                DCD      Interrupt2_Handler                  ;   2 Interrupt 2
+                DCD      Interrupt3_Handler                  ;   3 Interrupt 3
+                DCD      Interrupt4_Handler                  ;   4 Interrupt 4
+                DCD      Interrupt5_Handler                  ;   5 Interrupt 5
+                DCD      Interrupt6_Handler                  ;   6 Interrupt 6
+                DCD      Interrupt7_Handler                  ;   7 Interrupt 7
+                DCD      Interrupt8_Handler                  ;   8 Interrupt 8
+                DCD      Interrupt9_Handler                  ;   9 Interrupt 9
+
+                SPACE    (214 * 4)                           ; Interrupts 10 .. 224 are left out
 __Vectors_End
+__Vectors_Size  EQU      __Vectors_End - __Vectors
 
-__Vectors_Size  EQU     __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
 
+                AREA     |.text|, CODE, READONLY
 
 ; Reset Handler
 
 Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  SystemInit
-                IMPORT  __main
-                LDR     R0, =SystemInit
-                BLX     R0
-                LDR     R0, =__main
-                BX      R0
+                EXPORT   Reset_Handler             [WEAK]
+                IMPORT   SystemInit
+                IMPORT   __main
+
+                LDR      R0, =SystemInit
+                BLX      R0
+                LDR      R0, =__main
+                BX       R0
                 ENDP
 
 
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler               [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler         [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler          [WEAK]
-                B       .
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+                MACRO
+                Set_Default_Handler  $Handler_Name
+$Handler_Name   PROC
+                EXPORT   $Handler_Name             [WEAK]
+                B        .
                 ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler        [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler          [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WDT_IRQHandler            [WEAK]
-                EXPORT  RTC_IRQHandler            [WEAK]
-                EXPORT  TIM0_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler           [WEAK]
-                EXPORT  MCIA_IRQHandler           [WEAK]
-                EXPORT  MCIB_IRQHandler           [WEAK]
-                EXPORT  UART0_IRQHandler          [WEAK]
-                EXPORT  UART1_IRQHandler          [WEAK]
-                EXPORT  UART2_IRQHandler          [WEAK]
-                EXPORT  UART3_IRQHandler          [WEAK]
-                EXPORT  UART4_IRQHandler          [WEAK]
-                EXPORT  AACI_IRQHandler           [WEAK]
-                EXPORT  CLCD_IRQHandler           [WEAK]
-                EXPORT  ENET_IRQHandler           [WEAK]
-                EXPORT  USBDC_IRQHandler          [WEAK]
-                EXPORT  USBHC_IRQHandler          [WEAK]
-                EXPORT  CHLCD_IRQHandler          [WEAK]
-                EXPORT  FLEXRAY_IRQHandler        [WEAK]
-                EXPORT  CAN_IRQHandler            [WEAK]
-                EXPORT  LIN_IRQHandler            [WEAK]
-                EXPORT  I2C_IRQHandler            [WEAK]
-                EXPORT  CPU_CLCD_IRQHandler       [WEAK]
-                EXPORT  SPI_IRQHandler            [WEAK]
-
-WDT_IRQHandler
-RTC_IRQHandler
-TIM0_IRQHandler
-TIM2_IRQHandler
-MCIA_IRQHandler
-MCIB_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-UART3_IRQHandler
-UART4_IRQHandler
-AACI_IRQHandler
-CLCD_IRQHandler
-ENET_IRQHandler
-USBDC_IRQHandler
-USBHC_IRQHandler
-CHLCD_IRQHandler
-FLEXRAY_IRQHandler
-CAN_IRQHandler
-LIN_IRQHandler
-I2C_IRQHandler
-CPU_CLCD_IRQHandler
-SPI_IRQHandler
-                B       .
-
-                ENDP
-
+                MEND
+
+
+; Default exception/interrupt handler
+
+                Set_Default_Handler  NMI_Handler
+                Set_Default_Handler  HardFault_Handler
+                Set_Default_Handler  MemManage_Handler
+                Set_Default_Handler  BusFault_Handler
+                Set_Default_Handler  UsageFault_Handler
+                Set_Default_Handler  SVC_Handler
+                Set_Default_Handler  DebugMon_Handler
+                Set_Default_Handler  PendSV_Handler
+                Set_Default_Handler  SysTick_Handler
+
+                Set_Default_Handler  Interrupt0_Handler
+                Set_Default_Handler  Interrupt1_Handler
+                Set_Default_Handler  Interrupt2_Handler
+                Set_Default_Handler  Interrupt3_Handler
+                Set_Default_Handler  Interrupt4_Handler
+                Set_Default_Handler  Interrupt5_Handler
+                Set_Default_Handler  Interrupt6_Handler
+                Set_Default_Handler  Interrupt7_Handler
+                Set_Default_Handler  Interrupt8_Handler
+                Set_Default_Handler  Interrupt9_Handler
 
                 ALIGN
 
 
-; User Initial Stack & Heap
-
-                IF      :DEF:__MICROLIB
-
-                EXPORT  __initial_sp
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-
-                ELSE
-
-                IMPORT  __use_two_region_memory
-                EXPORT  __user_initial_stackheap
-
-__user_initial_stackheap PROC
-                LDR     R0, =  Heap_Mem
-                LDR     R1, =(Stack_Mem + Stack_Size)
-                LDR     R2, = (Heap_Mem +  Heap_Size)
-                LDR     R3, = Stack_Mem
-                BX      LR
-                ENDP
-
-                ALIGN
+; User setup Stack & Heap
 
+                EXPORT   __stack_limit
+                EXPORT   __initial_sp
+                IF       Heap_Size != 0                      ; Heap is provided
+                EXPORT   __heap_base
+                EXPORT   __heap_limit
                 ENDIF
 
-
                 END

CMSIS/CoreValidation/Tests/Cortex-M4/AC5/RTE/Device/ARMCM4/system_ARMCM4.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
  * @file     system_ARMCM4.c
  * @brief    CMSIS Device System Source File for
- *           ARMCM4 Device Series
- * @version  V5.00
- * @date     07. September 2016
+ *           ARMCM4 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -34,9 +34,9 @@
 /*----------------------------------------------------------------------------
   Define clocks
  *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+#define  XTAL            (50000000UL)     /* Oscillator frequency */
 
-#define  SYSTEM_CLOCK    (5U * XTAL)
+#define  SYSTEM_CLOCK    (XTAL / 2U)
 
 
 /*----------------------------------------------------------------------------
@@ -49,7 +49,7 @@
 /*----------------------------------------------------------------------------
   System Core Clock Variable
  *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */
 
 
 /*----------------------------------------------------------------------------
@@ -71,8 +71,8 @@ void SystemInit (void)
 #endif
 
 #if defined (__FPU_USED) && (__FPU_USED == 1U)
-  SCB->CPACR |= ((3U << 10U*2U) |           /* set CP10 Full Access */
-                 (3U << 11U*2U)  );         /* set CP11 Full Access */
+  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */
+                 (3U << 11U*2U)  );         /* enable CP11 Full Access */
 #endif
 
 #ifdef UNALIGNED_SUPPORT_DISABLE

CMSIS/CoreValidation/Tests/Cortex-M4/AC6/RTE/Device/ARMCM4/startup_ARMCM4.s

@@ -1,12 +1,12 @@
 ;/**************************************************************************//**
 ; * @file     startup_ARMCM4.s
 ; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM4 Device Series
-; * @version  V5.00
-; * @date     02. March 2016
+; *           ARMCM4 Device
+; * @version  V5.3.1
+; * @date     09. July 2018
 ; ******************************************************************************/
 ;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
 ; *
 ; * SPDX-License-Identifier: Apache-2.0
 ; *
@@ -23,32 +23,33 @@
 ; * limitations under the License.
 ; */
 
-;/*
 ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-;*/
 
 
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Stack Configuration
+;  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
 
-Stack_Size      EQU     0x00000400
+Stack_Size      EQU      0x00000400
 
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
+                AREA     STACK, NOINIT, READWRITE, ALIGN=3
+__stack_limit
+Stack_Mem       SPACE    Stack_Size
 __initial_sp
 
 
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
+;<h> Heap Configuration
+;  <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
 
-Heap_Size       EQU     0x00000C00
+Heap_Size       EQU      0x00000C00
 
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+                IF       Heap_Size != 0                      ; Heap is provided
+                AREA     HEAP, NOINIT, READWRITE, ALIGN=3
 __heap_base
-Heap_Mem        SPACE   Heap_Size
+Heap_Mem        SPACE    Heap_Size
 __heap_limit
+                ENDIF
 
 
                 PRESERVE8
@@ -57,206 +58,106 @@ __heap_limit
 
 ; Vector Table Mapped to Address 0 at Reset
 
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
-                DCD     RTC_IRQHandler            ;  1:  Real Time Clock
-                DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
-                DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
-                DCD     MCIA_IRQHandler           ;  4:  MCIa
-                DCD     MCIB_IRQHandler           ;  5:  MCIb
-                DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
-                DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
-                DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
-                DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
-                DCD     AACI_IRQHandler           ; 10: AACI / AC97
-                DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
-                DCD     ENET_IRQHandler           ; 12: Ethernet
-                DCD     USBDC_IRQHandler          ; 13: USB Device
-                DCD     USBHC_IRQHandler          ; 14: USB Host Controller
-                DCD     CHLCD_IRQHandler          ; 15: Character LCD
-                DCD     FLEXRAY_IRQHandler        ; 16: Flexray
-                DCD     CAN_IRQHandler            ; 17: CAN
-                DCD     LIN_IRQHandler            ; 18: LIN
-                DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
-                DCD     0                         ; 20: Reserved
-                DCD     0                         ; 21: Reserved
-                DCD     0                         ; 22: Reserved
-                DCD     0                         ; 23: Reserved
-                DCD     0                         ; 24: Reserved
-                DCD     0                         ; 25: Reserved
-                DCD     0                         ; 26: Reserved
-                DCD     0                         ; 27: Reserved
-                DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
-                DCD     0                         ; 29: Reserved - CPU FPGA
-                DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
-                DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
+                AREA     RESET, DATA, READONLY
+                EXPORT   __Vectors
+                EXPORT   __Vectors_End
+                EXPORT   __Vectors_Size
+
+__Vectors       DCD      __initial_sp                        ;     Top of Stack
+                DCD      Reset_Handler                       ;     Reset Handler
+                DCD      NMI_Handler                         ; -14 NMI Handler
+                DCD      HardFault_Handler                   ; -13 Hard Fault Handler
+                DCD      MemManage_Handler                   ; -12 MPU Fault Handler
+                DCD      BusFault_Handler                    ; -11 Bus Fault Handler
+                DCD      UsageFault_Handler                  ; -10 Usage Fault Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      SVC_Handler                         ;  -5 SVCall Handler
+                DCD      DebugMon_Handler                    ;  -4 Debug Monitor Handler
+                DCD      0                                   ;     Reserved
+                DCD      PendSV_Handler                      ;  -2 PendSV Handler
+                DCD      SysTick_Handler                     ;  -1 SysTick Handler
+
+                ; Interrupts
+                DCD      Interrupt0_Handler                  ;   0 Interrupt 0
+                DCD      Interrupt1_Handler                  ;   1 Interrupt 1
+                DCD      Interrupt2_Handler                  ;   2 Interrupt 2
+                DCD      Interrupt3_Handler                  ;   3 Interrupt 3
+                DCD      Interrupt4_Handler                  ;   4 Interrupt 4
+                DCD      Interrupt5_Handler                  ;   5 Interrupt 5
+                DCD      Interrupt6_Handler                  ;   6 Interrupt 6
+                DCD      Interrupt7_Handler                  ;   7 Interrupt 7
+                DCD      Interrupt8_Handler                  ;   8 Interrupt 8
+                DCD      Interrupt9_Handler                  ;   9 Interrupt 9
+
+                SPACE    (214 * 4)                           ; Interrupts 10 .. 224 are left out
 __Vectors_End
+__Vectors_Size  EQU      __Vectors_End - __Vectors
 
-__Vectors_Size  EQU     __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
 
+                AREA     |.text|, CODE, READONLY
 
 ; Reset Handler
 
 Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  SystemInit
-                IMPORT  __main
-                LDR     R0, =SystemInit
-                BLX     R0
-                LDR     R0, =__main
-                BX      R0
+                EXPORT   Reset_Handler             [WEAK]
+                IMPORT   SystemInit
+                IMPORT   __main
+
+                LDR      R0, =SystemInit
+                BLX      R0
+                LDR      R0, =__main
+                BX       R0
                 ENDP
 
 
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler               [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler         [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler          [WEAK]
-                B       .
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+                MACRO
+                Set_Default_Handler  $Handler_Name
+$Handler_Name   PROC
+                EXPORT   $Handler_Name             [WEAK]
+                B        .
                 ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler        [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler          [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WDT_IRQHandler            [WEAK]
-                EXPORT  RTC_IRQHandler            [WEAK]
-                EXPORT  TIM0_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler           [WEAK]
-                EXPORT  MCIA_IRQHandler           [WEAK]
-                EXPORT  MCIB_IRQHandler           [WEAK]
-                EXPORT  UART0_IRQHandler          [WEAK]
-                EXPORT  UART1_IRQHandler          [WEAK]
-                EXPORT  UART2_IRQHandler          [WEAK]
-                EXPORT  UART3_IRQHandler          [WEAK]
-                EXPORT  UART4_IRQHandler          [WEAK]
-                EXPORT  AACI_IRQHandler           [WEAK]
-                EXPORT  CLCD_IRQHandler           [WEAK]
-                EXPORT  ENET_IRQHandler           [WEAK]
-                EXPORT  USBDC_IRQHandler          [WEAK]
-                EXPORT  USBHC_IRQHandler          [WEAK]
-                EXPORT  CHLCD_IRQHandler          [WEAK]
-                EXPORT  FLEXRAY_IRQHandler        [WEAK]
-                EXPORT  CAN_IRQHandler            [WEAK]
-                EXPORT  LIN_IRQHandler            [WEAK]
-                EXPORT  I2C_IRQHandler            [WEAK]
-                EXPORT  CPU_CLCD_IRQHandler       [WEAK]
-                EXPORT  SPI_IRQHandler            [WEAK]
-
-WDT_IRQHandler
-RTC_IRQHandler
-TIM0_IRQHandler
-TIM2_IRQHandler
-MCIA_IRQHandler
-MCIB_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-UART3_IRQHandler
-UART4_IRQHandler
-AACI_IRQHandler
-CLCD_IRQHandler
-ENET_IRQHandler
-USBDC_IRQHandler
-USBHC_IRQHandler
-CHLCD_IRQHandler
-FLEXRAY_IRQHandler
-CAN_IRQHandler
-LIN_IRQHandler
-I2C_IRQHandler
-CPU_CLCD_IRQHandler
-SPI_IRQHandler
-                B       .
-
-                ENDP
-
+                MEND
+
+
+; Default exception/interrupt handler
+
+                Set_Default_Handler  NMI_Handler
+                Set_Default_Handler  HardFault_Handler
+                Set_Default_Handler  MemManage_Handler
+                Set_Default_Handler  BusFault_Handler
+                Set_Default_Handler  UsageFault_Handler
+                Set_Default_Handler  SVC_Handler
+                Set_Default_Handler  DebugMon_Handler
+                Set_Default_Handler  PendSV_Handler
+                Set_Default_Handler  SysTick_Handler
+
+                Set_Default_Handler  Interrupt0_Handler
+                Set_Default_Handler  Interrupt1_Handler
+                Set_Default_Handler  Interrupt2_Handler
+                Set_Default_Handler  Interrupt3_Handler
+                Set_Default_Handler  Interrupt4_Handler
+                Set_Default_Handler  Interrupt5_Handler
+                Set_Default_Handler  Interrupt6_Handler
+                Set_Default_Handler  Interrupt7_Handler
+                Set_Default_Handler  Interrupt8_Handler
+                Set_Default_Handler  Interrupt9_Handler
 
                 ALIGN
 
 
-; User Initial Stack & Heap
-
-                IF      :DEF:__MICROLIB
-
-                EXPORT  __initial_sp
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-
-                ELSE
-
-                IMPORT  __use_two_region_memory
-                EXPORT  __user_initial_stackheap
-
-__user_initial_stackheap PROC
-                LDR     R0, =  Heap_Mem
-                LDR     R1, =(Stack_Mem + Stack_Size)
-                LDR     R2, = (Heap_Mem +  Heap_Size)
-                LDR     R3, = Stack_Mem
-                BX      LR
-                ENDP
-
-                ALIGN
+; User setup Stack & Heap
 
+                EXPORT   __stack_limit
+                EXPORT   __initial_sp
+                IF       Heap_Size != 0                      ; Heap is provided
+                EXPORT   __heap_base
+                EXPORT   __heap_limit
                 ENDIF
 
-
                 END

CMSIS/CoreValidation/Tests/Cortex-M4/AC6/RTE/Device/ARMCM4/system_ARMCM4.c

@@ -1,12 +1,12 @@
 /**************************************************************************//**
  * @file     system_ARMCM4.c
  * @brief    CMSIS Device System Source File for
- *           ARMCM4 Device Series
- * @version  V5.00
- * @date     07. September 2016
+ *           ARMCM4 Device
+ * @version  V5.3.1
+ * @date     09. July 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -34,9 +34,9 @@
 /*----------------------------------------------------------------------------
   Define clocks
  *----------------------------------------------------------------------------*/
-#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+#define  XTAL            (50000000UL)     /* Oscillator frequency */
 
-#define  SYSTEM_CLOCK    (5U * XTAL)
+#define  SYSTEM_CLOCK    (XTAL / 2U)
 
 
 /*----------------------------------------------------------------------------
@@ -49,7 +49,7 @@
 /*----------------------------------------------------------------------------
   System Core Clock Variable
  *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */
 
 
 /*----------------------------------------------------------------------------
@@ -71,8 +71,8 @@ void SystemInit (void)
 #endif
 
 #if defined (__FPU_USED) && (__FPU_USED == 1U)
-  SCB->CPACR |= ((3U << 10U*2U) |           /* set CP10 Full Access */
-                 (3U << 11U*2U)  );         /* set CP11 Full Access */
+  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */
+                 (3U << 11U*2U)  );         /* enable CP11 Full Access */
 #endif
 
 #ifdef UNALIGNED_SUPPORT_DISABLE