RTX5: fixed optimization issue when using GCC optimization level 3

ARM.CMSIS.pdsc

@@ -10,6 +10,8 @@
   <releases>
     <release version="5.3.1-dev1">
       Active development...
+      CMSIS-RTOS2:
+        - RTX 5.3.1 (see revision history for details)
     </release>
     <release version="5.3.1-dev0">
       Patch release scheduled for after EW18.
@@ -2704,7 +2706,7 @@ and 8-bit Java bytecodes in Jazelle state.
     </component>
 
     <!-- CMSIS-RTOS Keil RTX5 component -->
-    <component Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX5" Cversion="5.3.0" Capiversion="1.0.0" condition="RTOS RTX5">
+    <component Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX5" Cversion="5.3.1" Capiversion="1.0.0" condition="RTOS RTX5">
       <description>CMSIS-RTOS RTX5 implementation for Cortex-M, SC000, and SC300</description>
       <RTE_Components_h>
         <!-- the following content goes into file 'RTE_Components.h' -->
@@ -2720,7 +2722,7 @@ and 8-bit Java bytecodes in Jazelle state.
     </component>
 
     <!-- CMSIS-RTOS2 Keil RTX5 component -->
-    <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cversion="5.3.0" Capiversion="2.1.2" condition="RTOS2 RTX5 Lib">
+    <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cversion="5.3.1" Capiversion="2.1.2" condition="RTOS2 RTX5 Lib">
       <description>CMSIS-RTOS2 RTX5 for Cortex-M, SC000, C300 and Armv8-M (Library)</description>
       <RTE_Components_h>
         <!-- the following content goes into file 'RTE_Components.h' -->
@@ -2789,7 +2791,7 @@ and 8-bit Java bytecodes in Jazelle state.
         <file category="library" condition="CM7_FP_LE_IAR"        name="CMSIS/RTOS2/RTX/Library/IAR/RTX_CM4F.a"     src="CMSIS/RTOS2/RTX/Source"/>
       </files>
     </component>
-    <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library_NS" Cversion="5.3.0" Capiversion="2.1.2" condition="RTOS2 RTX5 NS">
+    <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library_NS" Cversion="5.3.1" Capiversion="2.1.2" condition="RTOS2 RTX5 NS">
       <description>CMSIS-RTOS2 RTX5 for Armv8-M Non-Secure Domain (Library)</description>
       <RTE_Components_h>
         <!-- the following content goes into file 'RTE_Components.h' -->
@@ -2840,7 +2842,7 @@ and 8-bit Java bytecodes in Jazelle state.
         <file category="library" condition="ARMv8MML_FP_LE_GCC"   name="CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMFN.a" src="CMSIS/RTOS2/RTX/Source"/>
       </files>
     </component>
-    <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source" Cversion="5.3.0" Capiversion="2.1.2" condition="RTOS2 RTX5">
+    <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source" Cversion="5.3.1" Capiversion="2.1.2" condition="RTOS2 RTX5">
       <description>CMSIS-RTOS2 RTX5 for Cortex-M, SC000, C300 and Armv8-M (Source)</description>
       <RTE_Components_h>
         <!-- the following content goes into file 'RTE_Components.h' -->
@@ -2929,7 +2931,7 @@ and 8-bit Java bytecodes in Jazelle state.
         <file category="source" name="CMSIS/RTOS2/Source/os_systick.c"/>
       </files>
     </component>
-    <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source" Cversion="5.3.0" Capiversion="2.1.2" condition="RTOS2 RTX5 v7-A">
+    <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source" Cversion="5.3.1" Capiversion="2.1.2" condition="RTOS2 RTX5 v7-A">
       <description>CMSIS-RTOS2 RTX5 for Armv7-A (Source)</description>
       <RTE_Components_h>
         <!-- the following content goes into file 'RTE_Components.h' -->
@@ -2986,7 +2988,7 @@ and 8-bit Java bytecodes in Jazelle state.
         <file category="source" name="CMSIS/RTOS2/RTX/Source/IAR/irq_ca.s"          condition="CA_IAR"/>
       </files>
     </component>
-    <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source_NS" Cversion="5.3.0" Capiversion="2.1.2" condition="RTOS2 RTX5 NS">
+    <component Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Source_NS" Cversion="5.3.1" Capiversion="2.1.2" condition="RTOS2 RTX5 NS">
       <description>CMSIS-RTOS2 RTX5 for Armv8-M Non-Secure Domain (Source)</description>
       <RTE_Components_h>
         <!-- the following content goes into file 'RTE_Components.h' -->

CMSIS/DoxyGen/RTOS2/src/cmsis_os2.txt

@@ -160,6 +160,12 @@ File/Folder                  | Content
       <th>Version</th>
       <th>Description</th>
     </tr>
+    <tr>
+      <td>V5.3.1</td>
+      <td>
+       - Fixed optimization issue when using GCC optimization level 3.
+      </td>
+    </tr>
     <tr>
       <td>V5.3.0</td>
       <td>

CMSIS/RTOS2/RTX/Include/rtx_os.h

@@ -38,8 +38,8 @@ extern "C"
  
 /// Kernel Information
 #define osRtxVersionAPI      20010002   ///< API version (2.1.2)
-#define osRtxVersionKernel   50030000   ///< Kernel version (5.3.0)
-#define osRtxKernelId     "RTX V5.3.0"  ///< Kernel identification string
+#define osRtxVersionKernel   50030001   ///< Kernel version (5.3.1)
+#define osRtxKernelId     "RTX V5.3.1"  ///< Kernel identification string
  
  
 //  ==== Common definitions ====

CMSIS/RTOS2/RTX/Source/rtx_thread.c

@@ -151,7 +151,7 @@ void osRtxThreadListPut (os_object_t *object, os_thread_t *thread) {
   priority = thread->priority;
 
   prev = osRtxThreadObject(object);
-  next = object->thread_list;
+  next = prev->thread_next;
   while ((next != NULL) && (next->priority >= priority)) {
     prev = next;
     next = next->thread_next;