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+/*
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+ * Copyright (C) 2022 Arm Limited or its affiliates.
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+ *
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+ * SPDX-License-Identifier: Apache-2.0
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+ *
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+ * Licensed under the Apache License, Version 2.0 (the License); you may
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+ * not use this file except in compliance with the License.
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+ * You may obtain a copy of the License at
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+ *
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+ * www.apache.org/licenses/LICENSE-2.0
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+ *
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+ * Unless required by applicable law or agreed to in writing, software
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+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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+ * See the License for the specific language governing permissions and
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+ * limitations under the License.
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+ */
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+
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+/* ----------------------------------------------------------------------
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+ * Project: CMSIS NN Library
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+ * Title: arm_svdf_s8.c
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+ * Description: S8 basic SVDF layer function
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+ *
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+ * $Date: 8 April 2022
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+ * $Revision: V.1.0.0
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+ *
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+ * Target Processor: Cortex-M processors
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+ *
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+ * -------------------------------------------------------------------- */
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+
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+#include "arm_nnfunctions.h"
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+#include "arm_nnsupportfunctions.h"
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+
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+/**
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+ * @ingroup groupNN
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+ */
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+
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+/**
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+ * @addtogroup SVDF
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+ * @{
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+ */
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+
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+/*
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+ * S8 SVDF layer function for TensorFlow Lite with 16 bit state tensor
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+ *
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+ * Refer to header file for details.
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+ *
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+ */
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+
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+arm_status arm_svdf_state_s16_s8(const cmsis_nn_context *input_ctx,
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+ const cmsis_nn_context *output_ctx,
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+ const cmsis_nn_svdf_params *svdf_params,
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+ const cmsis_nn_per_tensor_quant_params *input_quant_params,
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+ const cmsis_nn_per_tensor_quant_params *output_quant_params,
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+ const cmsis_nn_dims *input_dims,
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+ const q7_t *input_data,
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+ const cmsis_nn_dims *state_dims,
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+ q15_t *state_data,
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+ const cmsis_nn_dims *weights_feature_dims,
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+ const q7_t *weights_feature_data,
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+ const cmsis_nn_dims *weights_time_dims,
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+ const q15_t *weights_time_data,
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+ const cmsis_nn_dims *bias_dims,
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+ const q31_t *bias_data,
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+ const cmsis_nn_dims *output_dims,
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+ q7_t *output_data)
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+{
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+ (void)bias_dims;
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+ (void)state_dims;
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+ (void)output_dims;
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+
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+ const q31_t multiplier_in = input_quant_params->multiplier;
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+ const q31_t shift_in = input_quant_params->shift;
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+ const q31_t multiplier_out = output_quant_params->multiplier;
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+ const q31_t shift_2 = output_quant_params->shift;
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+ const int32_t zp_in = svdf_params->input_offset;
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+ const int32_t zp_out = svdf_params->output_offset;
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+ const int32_t in_activation_min = svdf_params->input_activation.min;
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+ const int32_t in_activation_max = svdf_params->input_activation.max;
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+ const int32_t out_activation_min = svdf_params->output_activation.min;
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+ const int32_t out_activation_max = svdf_params->output_activation.max;
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+ const int16_t rank = svdf_params->rank;
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+
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+ const int32_t input_batches = input_dims->n;
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+ const int32_t input_height = input_dims->h;
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+ const int32_t feature_batches = weights_feature_dims->n;
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+ const int32_t time_batches = weights_time_dims->h;
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+ const int32_t unit_count = feature_batches / rank;
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+
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+ if (input_ctx->buf == NULL)
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+ {
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+ return ARM_MATH_ARGUMENT_ERROR;
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+ }
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+ q31_t *buffer_a = (q31_t *)input_ctx->buf;
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+
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+ if (output_ctx->buf == NULL)
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+ {
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+ return ARM_MATH_ARGUMENT_ERROR;
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+ }
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+ q31_t *buffer_b = (q31_t *)output_ctx->buf;
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+
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+ memmove((q15_t *)state_data,
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+ (q15_t *)state_data + 1,
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+ (size_t)((input_batches * feature_batches * time_batches - 1) * (int32_t)sizeof(int16_t)));
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+
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+ for (int i_batch = 0; i_batch < input_batches; i_batch++)
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+ {
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+ q15_t *res_ptr = state_data + (time_batches * i_batch * feature_batches) + (time_batches - 1);
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+ const q7_t *weight = weights_feature_data;
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+ const q7_t *input = input_data + i_batch * input_height;
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+
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+ arm_status res = arm_nn_vec_mat_mult_t_svdf_s8(input,
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+ weight,
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+ res_ptr,
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+ -zp_in,
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+ 0,
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+ time_batches,
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+ multiplier_in,
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+ shift_in,
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+ input_height,
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+ feature_batches,
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+ in_activation_min,
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+ in_activation_max);
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+
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+ if (res != ARM_MATH_SUCCESS)
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+ {
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+ return res;
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+ }
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+ }
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+
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+ {
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+ q31_t *ptr_a = buffer_a;
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+ const q15_t *v2 = state_data;
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+ for (int i_batch = 0; i_batch < input_batches; i_batch++)
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+ {
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+ const q15_t *v1 = weights_time_data;
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+
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+ for (int i_feature_batch = 0; i_feature_batch < feature_batches; i_feature_batch++)
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+ {
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+ *ptr_a = 0;
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+ int32_t sum = 0;
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+#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI)
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+ int j = 0;
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+ int32_t block_count = time_batches >> 1;
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+ for (int i = 0; i < block_count; i++)
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+ {
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+ j += 2;
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+ q31_t r1 = arm_nn_read_q15x2_ia(&v1);
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+ q31_t r2 = arm_nn_read_q15x2_ia(&v2);
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+
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+ sum = __SMLAD(r1, r2, sum);
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+ }
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+
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+ // Process the remaining data
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+ for (; j < time_batches; j++)
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+ {
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+ sum += *v1 * *v2;
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+ v1++;
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+ v2++;
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+ }
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+#else
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+ for (int j = 0; j < time_batches; j++)
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+ {
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+ sum += *v1 * *v2;
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+ v1++;
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+ v2++;
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+ }
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+#endif
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+
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+ *ptr_a = sum;
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+ ptr_a++;
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+ }
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+ }
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+ }
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+
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+ if (bias_data)
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+ {
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+ if (unit_count == feature_batches)
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+ {
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+ for (int i = 0; i < input_batches; i++)
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+ {
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+ q31_t *output_temp = buffer_b + i * feature_batches;
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+ const q31_t *ptr_a = buffer_a + i * feature_batches;
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+
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+ const int32_t *bi = bias_data;
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+ for (int j = 0; j < feature_batches; j++)
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+ {
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+ output_temp[j] = ptr_a[j] + bi[j];
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+ }
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+ }
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+ }
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+ else
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+ {
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+ for (int i_batch = 0; i_batch < input_batches; i_batch++)
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+ {
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+ q31_t *output_data_temp = buffer_b + i_batch * unit_count;
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+ q31_t *ptr_a = buffer_a + i_batch * feature_batches;
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+
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+ for (int i = 0; i < unit_count; i++)
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+ {
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+ int32_t sum = bias_data[i];
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+ for (int j = 0; j < rank; j++)
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+ {
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+ sum += *ptr_a;
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+ ptr_a++;
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+ }
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+ output_data_temp[i] = sum;
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+ }
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+ }
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+ }
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+ }
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+ else
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+ {
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+ for (int i_batch = 0; i_batch < input_batches; i_batch++)
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+ {
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+ q31_t *output_data_temp = buffer_b + i_batch * unit_count;
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+ q31_t *ptr_a = buffer_a + i_batch * feature_batches;
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+
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+ for (int i = 0; i < unit_count; i++)
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+ {
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+ int32_t sum = 0;
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+ for (int j = 0; j < rank; j++)
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+ {
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+ sum += *ptr_a;
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+ ptr_a++;
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+ }
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+ output_data_temp[i] = sum;
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+ }
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+ }
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+ }
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+
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+#if defined(ARM_MATH_MVEI)
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+ int32_t num_elements = input_batches * unit_count;
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+ const int32_t loop_count = (num_elements + 3) / 4;
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+ for (int i_op = 0; i_op < loop_count; i_op++)
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+ {
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+ mve_pred16_t p = vctp32q((uint32_t)num_elements);
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+ int32x4_t op = vldrwq_z_s32(buffer_b, p);
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+ op = arm_requantize_mve(op, multiplier_out, shift_2);
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+ op = vaddq_n_s32(op, zp_out);
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+ const int32x4_t min_vec = vdupq_n_s32((int8_t)out_activation_min);
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+ const int32x4_t max_vec = vdupq_n_s32((int8_t)out_activation_max);
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+ op = vmaxq_s32(op, min_vec);
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+ op = vminq_s32(op, max_vec);
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+ vstrbq_p_s32(output_data, op, p);
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+ output_data += 4;
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+ buffer_b += 4;
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+ num_elements -= 4;
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+ }
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+#else
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+ for (int i = 0; i < input_batches * unit_count; i++)
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+ {
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+ output_data[i] = (q7_t)CLAMP(
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+ arm_nn_requantize(buffer_b[i], multiplier_out, shift_2) + zp_out, out_activation_max, out_activation_min);
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+ }
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+#endif
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+
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+ return (ARM_MATH_SUCCESS);
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+}
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+
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+/**
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+ * @} end of SVDF group
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+ */
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