CoreValidation: Fixed Cortex-A test cases.

Change-Id: I1b397e953fdcbca9f82f5390ec39d2429c5ef8db

CMSIS/CoreValidation/Source/CV_CoreAFunc.c

@@ -47,14 +47,14 @@ void TC_CoreAFunc_FPSCR(void) {
 
 /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
 #if defined(__CC_ARM)
-#define __SUBS(Rd, Rm, Rn) __ASM("SUBS " # Rd ", " # Rm ", " # Rn)
-#define __ADDS(Rd, Rm, Rn) __ASM("ADDS " # Rd ", " # Rm ", " # Rn)
+#define __SUBS(Rd, Rm, Rn) __ASM volatile("SUBS " # Rd ", " # Rm ", " # Rn)
+#define __ADDS(Rd, Rm, Rn) __ASM volatile("ADDS " # Rd ", " # Rm ", " # Rn)
 #elif defined( __GNUC__ ) && defined(__thumb__)
-#define __SUBS(Rd, Rm, Rn) __ASM("SUB %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn))
-#define __ADDS(Rd, Rm, Rn) __ASM("ADD %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn))
+#define __SUBS(Rd, Rm, Rn) __ASM volatile("SUB %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn))
+#define __ADDS(Rd, Rm, Rn) __ASM volatile("ADD %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn))
 #else
-#define __SUBS(Rd, Rm, Rn) __ASM("SUBS %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn))
-#define __ADDS(Rd, Rm, Rn) __ASM("ADDS %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn))
+#define __SUBS(Rd, Rm, Rn) __ASM volatile("SUBS %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn))
+#define __ADDS(Rd, Rm, Rn) __ASM volatile("ADDS %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn))
 #endif
 
 void TC_CoreAFunc_CPSR(void) {

CMSIS/CoreValidation/Source/CV_L1Cache.c

@@ -93,7 +93,7 @@ void TC_L1Cache_InvalidateDCacheAll(void) {
   
   /* setup */
   uint32_t orig = __get_SCTLR();
-  uint32_t value = 0x0815U;
+  volatile uint32_t value = 0x0815U;
 
   L1C_EnableCaches();