CMSIS CORE: Adding support for __SXTB16_RORn

CMSIS/Core/Include/cmsis_armcc.h

@@ -1,8 +1,8 @@
 /**************************************************************************//**
  * @file     cmsis_armcc.h
  * @brief    CMSIS compiler ARMCC (Arm Compiler 5) header file
- * @version  V5.1.1
- * @date     30. July 2019
+ * @version  V5.2.0
+ * @date     28. January 2020
  ******************************************************************************/
 /*
  * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
@@ -875,6 +875,10 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint
 #define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
                                                       ((int64_t)(ARG3) << 32U)     ) >> 32U))
 
+#define __SXTB16_RORn(ARG1, ARG2)        __SXTB16(__ROR(ARG1, ARG2))
+#endif
+}
+
 #endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
 /*@} end of group CMSIS_SIMD_intrinsics */
 

CMSIS/Core/Include/cmsis_armclang.h

@@ -1,8 +1,8 @@
 /**************************************************************************//**
  * @file     cmsis_armclang.h
  * @brief    CMSIS compiler armclang (Arm Compiler 6) header file
- * @version  V5.2.1
- * @date     30. July 2019
+ * @version  V5.3.0
+ * @date     28. January 2020
  ******************************************************************************/
 /*
  * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
@@ -1429,6 +1429,8 @@ __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
 #define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
                                            ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
 
+#define __SXTB16_RORn(ARG1, ARG2)        __SXTB16(__ROR(ARG1, ARG2))
+
 __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
 {
   int32_t result;

CMSIS/Core/Include/cmsis_armclang_ltm.h

@@ -1,8 +1,8 @@
 /**************************************************************************//**
  * @file     cmsis_armclang_ltm.h
  * @brief    CMSIS compiler armclang (Arm Compiler 6) header file
- * @version  V1.2.1
- * @date     30. July 2019
+ * @version  V1.3.0
+ * @date     28. January 2020
  ******************************************************************************/
 /*
  * Copyright (c) 2018-2019 Arm Limited. All rights reserved.
@@ -1876,6 +1876,8 @@ __STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
 #define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
                                            ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
 
+#define __SXTB16_RORn(ARG1, ARG2)        __SXTB16(__ROR(ARG1, ARG2))
+
 __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
 {
   int32_t result;

CMSIS/Core/Include/cmsis_gcc.h

@@ -1,8 +1,8 @@
 /**************************************************************************//**
  * @file     cmsis_gcc.h
  * @brief    CMSIS compiler GCC header file
- * @version  V5.2.1
- * @date     30. July 2019
+ * @version  V5.3.0
+ * @date     28. January 2020
  ******************************************************************************/
 /*
  * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
@@ -1962,6 +1962,15 @@ __STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
   return(result);
 }
 
+__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate)
+{
+  uint32_t result;
+
+  __ASM ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) );
+
+  return result;
+}
+
 __STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
 {
   uint32_t result;

CMSIS/Core/Include/cmsis_iccarm.h

@@ -1,8 +1,8 @@
 /**************************************************************************//**
  * @file     cmsis_iccarm.h
  * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file
- * @version  V5.1.1
- * @date     30. July 2019
+ * @version  V5.2.0
+ * @date     28. January 2020
  ******************************************************************************/
 
 //------------------------------------------------------------------------------
@@ -961,4 +961,6 @@ __packed struct  __iar_u32 { uint32_t v; };
 #pragma diag_default=Pe940
 #pragma diag_default=Pe177
 
+#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
+
 #endif /* __CMSIS_ICCARM_H__ */

CMSIS/CoreValidation/Source/CV_CoreSimd.c

@@ -83,6 +83,7 @@ void TC_CoreSimd_ParSat16 (void) {
 \details
 - Check Packing and unpacking:
   __SXTB16
+  __SXTB16_RORn
   __SXTAB16
   __UXTB16
   __UXTAB16
@@ -98,6 +99,21 @@ void TC_CoreSimd_PackUnpack (void) {
   res_s32 = __SXTB16(op1_s32);
   ASSERT_TRUE(res_s32 == (int32_t)0xFF830068);
 
+  /* --- __SXTB16_ROR8 Test ----------------------------------------- */
+  op1_s32 = (int32_t)0x80830168;
+  res_s32 = __SXTB16_RORn(op1_s32, 8);
+  ASSERT_TRUE(res_s32 == (int32_t)0xFF800001);
+
+  /* --- __SXTB16_ROR16 Test ---------------------------------------- */
+  op1_s32 = (int32_t)0x80830168;
+  res_s32 = __SXTB16_RORn(op1_s32, 16);
+  ASSERT_TRUE(res_s32 == (int32_t)0x68FF83);
+
+  /* --- __SXTB16_ROR24 Test ---------------------------------------- */
+  op1_s32 = (int32_t)0x80830168;
+  res_s32 = __SXTB16_RORn(op1_s32, 24);
+  ASSERT_TRUE(res_s32 == (int32_t)0x1FF80);
+
   /* --- __SXTAB16 Test ---------------------------------------------- */
   op1_s32 = (int32_t)0x000D0008;
   op2_s32 = (int32_t)0x80830168;

CMSIS/DoxyGen/Core/src/Ref_cm4_simd.txt

@@ -1378,6 +1378,33 @@ uint32_t __UXTAB16(uint32_t val1, uint32_t val2);
 uint32_t __SXTB16(uint32_t val);
 
 
+/**************************************************************************************************/
+/** 
+    \brief      Rotate right, dual extract 8-bits and sign extend each to 16-bits
+    
+    \details    This function enables you to rotate an operand by 8/16/24 bit, extract two 8-bit values and sign-extend 
+          them to 16 bits each.
+                
+    \param      val     two 8-bit values in val[7:0] and val[23:16] to be sign-extended.
+    \param      rotate  number of bits to rotate val. Only 8,16 and 24 are accepted
+
+              
+    \returns
+        the 8-bit values sign-extended to 16-bit values.
+            \li     sign-extended value of val[7:0] in the low halfword of the return value.
+            \li     sign-extended value of val[23:16] in the high halfword of the return value.
+        
+    
+    \par Operation:
+        \code
+   val        = Rotate(val, rotate)
+   res[15:0]  = SignExtended(val[7:0])
+   res[31:16] = SignExtended(val[23:16])
+        \endcode
+*/
+uint32_t __SXTB16_RORn(uint32_t val, uint32_r rotate);
+
+
 /**************************************************************************************************/
 /** 
     \brief      Dual extracted 8-bit to 16-bit signed addition