RTX5: improved MISRA compliance (defines and macros)

CMSIS/RTOS2/RTX/Library/ARM/MDK/RTX_CM.uvprojx

@@ -2846,7 +2846,7 @@
             <v6Rtti>0</v6Rtti>
             <VariousControls>
               <MiscControls></MiscControls>
-              <Define>EVR_RTX_DISABLE __DOMAIN_NS=1U</Define>
+              <Define>EVR_RTX_DISABLE DOMAIN_NS=1</Define>
               <Undefine></Undefine>
               <IncludePath>..\..\..\Config;..\..\..\Include;..\..\..\..\Include</IncludePath>
             </VariousControls>
@@ -2864,7 +2864,7 @@
             <uClangAs>0</uClangAs>
             <VariousControls>
               <MiscControls>--no_hide_all</MiscControls>
-              <Define>__DOMAIN_NS=1</Define>
+              <Define>DOMAIN_NS=1</Define>
               <Undefine></Undefine>
               <IncludePath></IncludePath>
             </VariousControls>
@@ -4102,7 +4102,7 @@
             <v6Rtti>0</v6Rtti>
             <VariousControls>
               <MiscControls></MiscControls>
-              <Define>EVR_RTX_DISABLE __DOMAIN_NS=1U</Define>
+              <Define>EVR_RTX_DISABLE DOMAIN_NS=1</Define>
               <Undefine></Undefine>
               <IncludePath>..\..\..\Config;..\..\..\Include;..\..\..\..\Include</IncludePath>
             </VariousControls>
@@ -4120,7 +4120,7 @@
             <uClangAs>0</uClangAs>
             <VariousControls>
               <MiscControls>--no_hide_all</MiscControls>
-              <Define>__DOMAIN_NS=1</Define>
+              <Define>DOMAIN_NS=1</Define>
               <Undefine></Undefine>
               <IncludePath></IncludePath>
             </VariousControls>
@@ -5358,7 +5358,7 @@
             <v6Rtti>0</v6Rtti>
             <VariousControls>
               <MiscControls></MiscControls>
-              <Define>EVR_RTX_DISABLE __DOMAIN_NS=1U</Define>
+              <Define>EVR_RTX_DISABLE DOMAIN_NS=1</Define>
               <Undefine></Undefine>
               <IncludePath>..\..\..\Config;..\..\..\Include;..\..\..\..\Include</IncludePath>
             </VariousControls>
@@ -5376,7 +5376,7 @@
             <uClangAs>0</uClangAs>
             <VariousControls>
               <MiscControls>--no_hide_all</MiscControls>
-              <Define>__DOMAIN_NS=1</Define>
+              <Define>DOMAIN_NS=1</Define>
               <Undefine></Undefine>
               <IncludePath></IncludePath>
             </VariousControls>

CMSIS/RTOS2/RTX/Library/GCC/MDK/RTX_CM.uvprojx

@@ -2303,7 +2303,7 @@
             <uThumb>1</uThumb>
             <VariousControls>
               <MiscControls>-march=armv8-m.base -ffunction-sections</MiscControls>
-              <Define>EVR_RTX_DISABLE __DOMAIN_NS=1U</Define>
+              <Define>EVR_RTX_DISABLE DOMAIN_NS=1</Define>
               <Undefine></Undefine>
               <IncludePath>..\..\..\Config;..\..\..\Include;..\..\..\..\Include</IncludePath>
             </VariousControls>
@@ -2313,7 +2313,7 @@
             <interw>0</interw>
             <VariousControls>
               <MiscControls>-march=armv8-m.base</MiscControls>
-              <Define>__DOMAIN_NS=1</Define>
+              <Define>DOMAIN_NS=1</Define>
               <Undefine></Undefine>
               <IncludePath></IncludePath>
             </VariousControls>
@@ -3381,7 +3381,7 @@
             <uThumb>1</uThumb>
             <VariousControls>
               <MiscControls>-march=armv8-m.main -ffunction-sections</MiscControls>
-              <Define>EVR_RTX_DISABLE __DOMAIN_NS=1U</Define>
+              <Define>EVR_RTX_DISABLE DOMAIN_NS=1</Define>
               <Undefine></Undefine>
               <IncludePath>..\..\..\Config;..\..\..\Include;..\..\..\..\Include</IncludePath>
             </VariousControls>
@@ -3391,7 +3391,7 @@
             <interw>0</interw>
             <VariousControls>
               <MiscControls>-march=armv8-m.main</MiscControls>
-              <Define>__DOMAIN_NS=1</Define>
+              <Define>DOMAIN_NS=1</Define>
               <Undefine></Undefine>
               <IncludePath></IncludePath>
             </VariousControls>
@@ -4459,7 +4459,7 @@
             <uThumb>1</uThumb>
             <VariousControls>
               <MiscControls>-march=armv8-m.main -mfpu=fpv5-sp-d16 -mfloat-abi=hard -ffunction-sections</MiscControls>
-              <Define>EVR_RTX_DISABLE __DOMAIN_NS=1U</Define>
+              <Define>EVR_RTX_DISABLE DOMAIN_NS=1</Define>
               <Undefine></Undefine>
               <IncludePath>..\..\..\Config;..\..\..\Include;..\..\..\..\Include</IncludePath>
             </VariousControls>
@@ -4469,7 +4469,7 @@
             <interw>0</interw>
             <VariousControls>
               <MiscControls>-march=armv8-m.main -mfpu=fpv5-sp-d16 -mfloat-abi=hard</MiscControls>
-              <Define>__FPU_USED=1 __DOMAIN_NS=1</Define>
+              <Define>__FPU_USED=1 DOMAIN_NS=1</Define>
               <Undefine></Undefine>
               <IncludePath></IncludePath>
             </VariousControls>

CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mbl.s

@@ -24,8 +24,8 @@
 ; */
 
 
-                IF       :LNOT::DEF:__DOMAIN_NS
-__DOMAIN_NS     EQU      0
+                IF       :LNOT::DEF:DOMAIN_NS
+DOMAIN_NS       EQU      0
                 ENDIF
 
 I_T_RUN_OFS     EQU      20                     ; osRtxInfo.thread.run offset
@@ -51,7 +51,7 @@ SVC_Handler     PROC
                 EXPORT   SVC_Handler
                 IMPORT   osRtxUserSVC
                 IMPORT   osRtxInfo
-                IF       __DOMAIN_NS = 1
+                IF       DOMAIN_NS = 1
                 IMPORT   TZ_LoadContext_S
                 IMPORT   TZ_StoreContext_S
                 ENDIF
@@ -84,7 +84,7 @@ SVC_Context
                 CBZ      R1,SVC_ContextSwitch   ; Branch if running thread is deleted
 
 SVC_ContextSave
-                IF       __DOMAIN_NS = 1
+                IF       DOMAIN_NS = 1
                 LDR      R0,[R1,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
                 CBZ      R0,SVC_ContextSave1    ; Branch if there is no secure context
                 PUSH     {R1,R2,R3,R7}          ; Save registers
@@ -115,7 +115,7 @@ SVC_ContextSwitch
                 STR      R2,[R3]                ; osRtxInfo.thread.run: curr = next
 
 SVC_ContextRestore
-                IF       __DOMAIN_NS = 1
+                IF       DOMAIN_NS = 1
                 LDR      R0,[R2,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
                 CBZ      R0,SVC_ContextRestore1 ; Branch if there is no secure context
                 PUSH     {R2,R3}                ; Save registers
@@ -132,7 +132,7 @@ SVC_ContextRestore1
                 ORRS     R0,R1
                 MOV      LR,R0                  ; Set EXC_RETURN
 
-                IF       __DOMAIN_NS = 1
+                IF       DOMAIN_NS = 1
                 LSLS     R0,R0,#25              ; Check domain of interrupted thread
                 BPL      SVC_ContextRestore2    ; Branch if non-secure
                 LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
@@ -215,7 +215,7 @@ SysTick_Handler PROC
 Sys_Context     PROC
                 EXPORT   Sys_Context
                 IMPORT   osRtxInfo
-                IF       __DOMAIN_NS = 1
+                IF       DOMAIN_NS = 1
                 IMPORT   TZ_LoadContext_S
                 IMPORT   TZ_StoreContext_S
                 ENDIF
@@ -226,7 +226,7 @@ Sys_Context     PROC
                 BEQ      Sys_ContextExit        ; Branch when threads are the same
 
 Sys_ContextSave
-                IF       __DOMAIN_NS = 1
+                IF       DOMAIN_NS = 1
                 LDR      R0,[R1,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
                 CBZ      R0,Sys_ContextSave1    ; Branch if there is no secure context
                 PUSH     {R1,R2,R3,R7}          ; Save registers
@@ -263,7 +263,7 @@ Sys_ContextSwitch
                 STR      R2,[R3]                ; osRtxInfo.run: curr = next
 
 Sys_ContextRestore
-                IF       __DOMAIN_NS = 1
+                IF       DOMAIN_NS = 1
                 LDR      R0,[R2,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
                 CBZ      R0,Sys_ContextRestore1 ; Branch if there is no secure context
                 PUSH     {R2,R3}                ; Save registers
@@ -280,7 +280,7 @@ Sys_ContextRestore1
                 ORRS     R0,R1
                 MOV      LR,R0                  ; Set EXC_RETURN
 
-                IF       __DOMAIN_NS = 1
+                IF       DOMAIN_NS = 1
                 LSLS     R0,R0,#25              ; Check domain of interrupted thread
                 BPL      Sys_ContextRestore2    ; Branch if non-secure
                 LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP

CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mbl_ns.s

@@ -1,3 +1,3 @@
-__DOMAIN_NS     EQU      1
+DOMAIN_NS       EQU      1
                 INCLUDE  irq_armv8mbl.s
                 END

CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.s

@@ -24,8 +24,8 @@
 ; */
 
 
-                IF       :LNOT::DEF:__DOMAIN_NS
-__DOMAIN_NS     EQU      0
+                IF       :LNOT::DEF:DOMAIN_NS
+DOMAIN_NS       EQU      0
                 ENDIF
 
                 IF       ({FPU}="FPv5-SP") || ({FPU}="FPv5_D16")
@@ -57,7 +57,7 @@ SVC_Handler     PROC
                 EXPORT   SVC_Handler
                 IMPORT   osRtxUserSVC
                 IMPORT   osRtxInfo
-                IF       __DOMAIN_NS = 1
+                IF       DOMAIN_NS = 1
                 IMPORT   TZ_LoadContext_S
                 IMPORT   TZ_StoreContext_S
                 ENDIF
@@ -99,7 +99,7 @@ SVC_Context
                 ENDIF
 
 SVC_ContextSave
-                IF       __DOMAIN_NS = 1
+                IF       DOMAIN_NS = 1
                 LDR      R0,[R1,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
                 CBZ      R0,SVC_ContextSave1    ; Branch if there is no secure context
                 PUSH     {R1,R2,R3,LR}          ; Save registers and EXC_RETURN
@@ -124,7 +124,7 @@ SVC_ContextSwitch
                 STR      R2,[R3]                ; osRtxInfo.thread.run: curr = next
 
 SVC_ContextRestore
-                IF       __DOMAIN_NS = 1
+                IF       DOMAIN_NS = 1
                 LDR      R0,[R2,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
                 CBZ      R0,SVC_ContextRestore1 ; Branch if there is no secure context
                 PUSH     {R2,R3}                ; Save registers
@@ -139,7 +139,7 @@ SVC_ContextRestore1
                 LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
                 ORR      LR,R1,#0xFFFFFF00      ; Set EXC_RETURN
 
-                IF       __DOMAIN_NS = 1
+                IF       DOMAIN_NS = 1
                 TST      LR,#0x40               ; Check domain of interrupted thread
                 BNE      SVC_ContextRestore2    ; Branch if secure
                 ENDIF
@@ -205,7 +205,7 @@ SysTick_Handler PROC
 Sys_Context     PROC
                 EXPORT   Sys_Context
                 IMPORT   osRtxInfo
-                IF       __DOMAIN_NS = 1
+                IF       DOMAIN_NS = 1
                 IMPORT   TZ_LoadContext_S
                 IMPORT   TZ_StoreContext_S
                 ENDIF
@@ -217,7 +217,7 @@ Sys_Context     PROC
                 BXEQ     LR                     ; Exit when threads are the same
 
 Sys_ContextSave
-                IF       __DOMAIN_NS = 1
+                IF       DOMAIN_NS = 1
                 LDR      R0,[R1,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
                 CBZ      R0,Sys_ContextSave1    ; Branch if there is no secure context
                 PUSH     {R1,R2,R3,LR}          ; Save registers and EXC_RETURN
@@ -246,7 +246,7 @@ Sys_ContextSwitch
                 STR      R2,[R3]                ; osRtxInfo.run: curr = next
 
 Sys_ContextRestore
-                IF       __DOMAIN_NS = 1
+                IF       DOMAIN_NS = 1
                 LDR      R0,[R2,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
                 CBZ      R0,Sys_ContextRestore1 ; Branch if there is no secure context
                 PUSH     {R2,R3}                ; Save registers
@@ -261,7 +261,7 @@ Sys_ContextRestore1
                 LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
                 ORR      LR,R1,#0xFFFFFF00      ; Set EXC_RETURN
 
-                IF       __DOMAIN_NS = 1
+                IF       DOMAIN_NS = 1
                 TST      LR,#0x40               ; Check domain of interrupted thread
                 BNE      Sys_ContextRestore2    ; Branch if secure
                 ENDIF

CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml_ns.s

@@ -1,3 +1,3 @@
-__DOMAIN_NS     EQU      1
+DOMAIN_NS       EQU      1
                 INCLUDE  irq_armv8mml.s
                 END

CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl.S

@@ -27,8 +27,8 @@
         .file    "irq_armv8mbl.S"
         .syntax  unified
 
-        .ifndef  __DOMAIN_NS
-        .equ     __DOMAIN_NS, 0
+        .ifndef  DOMAIN_NS
+        .equ     DOMAIN_NS, 0
         .endif
 
         .equ     I_T_RUN_OFS, 20        // osRtxInfo.thread.run offset
@@ -83,7 +83,7 @@ SVC_Context:
         CBZ      R1,SVC_ContextSwitch   // Branch if running thread is deleted
 
 SVC_ContextSave:
-        .if      __DOMAIN_NS == 1
+        .if      DOMAIN_NS == 1
         LDR      R0,[R1,#TCB_TZM_OFS]   // Load TrustZone memory identifier
         CBZ      R0,SVC_ContextSave1    // Branch if there is no secure context
         PUSH     {R1,R2,R3,R7}          // Save registers
@@ -114,7 +114,7 @@ SVC_ContextSwitch:
         STR      R2,[R3]                // osRtxInfo.thread.run: curr = next
 
 SVC_ContextRestore:
-        .if      __DOMAIN_NS == 1
+        .if      DOMAIN_NS == 1
         LDR      R0,[R2,#TCB_TZM_OFS]   // Load TrustZone memory identifier
         CBZ      R0,SVC_ContextRestore1 // Branch if there is no secure context
         PUSH     {R2,R3}                // Save registers
@@ -131,7 +131,7 @@ SVC_ContextRestore1:
         ORRS     R0,R1
         MOV      LR,R0                  // Set EXC_RETURN
 
-        .if      __DOMAIN_NS == 1
+        .if      DOMAIN_NS == 1
         LSLS     R0,R0,#25              // Check domain of interrupted thread
         BPL      SVC_ContextRestore2    // Branch if non-secure
         LDR      R0,[R2,#TCB_SP_OFS]    // Load SP
@@ -230,7 +230,7 @@ Sys_Context:
         BEQ      Sys_ContextExit        // Branch when threads are the same
 
 Sys_ContextSave:
-        .if      __DOMAIN_NS == 1
+        .if      DOMAIN_NS == 1
         LDR      R0,[R1,#TCB_TZM_OFS]   // Load TrustZone memory identifier
         CBZ      R0,Sys_ContextSave1    // Branch if there is no secure context
         PUSH     {R1,R2,R3,R7}          // Save registers
@@ -267,7 +267,7 @@ Sys_ContextSwitch:
         STR      R2,[R3]                // osRtxInfo.run: curr = next
 
 Sys_ContextRestore:
-        .if      __DOMAIN_NS == 1
+        .if      DOMAIN_NS == 1
         LDR      R0,[R2,#TCB_TZM_OFS]   // Load TrustZone memory identifier
         CBZ      R0,Sys_ContextRestore1 // Branch if there is no secure context
         PUSH     {R2,R3}                // Save registers
@@ -284,7 +284,7 @@ Sys_ContextRestore1:
         ORRS     R0,R1
         MOV      LR,R0                  // Set EXC_RETURN
 
-        .if      __DOMAIN_NS == 1
+        .if      DOMAIN_NS == 1
         LSLS     R0,R0,#25              // Check domain of interrupted thread
         BPL      Sys_ContextRestore2    // Branch if non-secure
         LDR      R0,[R2,#TCB_SP_OFS]    // Load SP

CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl_ns.S

@@ -1,3 +1,3 @@
-        .equ     __DOMAIN_NS, 1
+        .equ     DOMAIN_NS,   1
         .include "../Source/GCC/irq_armv8mbl.S"
         .end

CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S

@@ -27,8 +27,8 @@
         .file    "irq_armv8mml.S"
         .syntax  unified
 
-        .ifndef  __DOMAIN_NS
-        .equ     __DOMAIN_NS, 0
+        .ifndef  DOMAIN_NS
+        .equ     DOMAIN_NS, 0
         .endif
 
         .ifndef  __FPU_USED
@@ -96,7 +96,7 @@ SVC_Context:
         .endif
 
 SVC_ContextSave:
-        .if      __DOMAIN_NS == 1
+        .if      DOMAIN_NS == 1
         LDR      R0,[R1,#TCB_TZM_OFS]   // Load TrustZone memory identifier
         CBZ      R0,SVC_ContextSave1    // Branch if there is no secure context
         PUSH     {R1,R2,R3,LR}          // Save registers and EXC_RETURN
@@ -121,7 +121,7 @@ SVC_ContextSwitch:
         STR      R2,[R3]                // osRtxInfo.thread.run: curr = next
 
 SVC_ContextRestore:
-        .if      __DOMAIN_NS == 1
+        .if      DOMAIN_NS == 1
         LDR      R0,[R2,#TCB_TZM_OFS]   // Load TrustZone memory identifier
         CBZ      R0,SVC_ContextRestore1 // Branch if there is no secure context
         PUSH     {R2,R3}                // Save registers
@@ -136,7 +136,7 @@ SVC_ContextRestore1:
         LDR      R0,[R2,#TCB_SP_OFS]    // Load SP
         ORR      LR,R1,#0xFFFFFF00      // Set EXC_RETURN
 
-        .if      __DOMAIN_NS == 1
+        .if      DOMAIN_NS == 1
         TST      LR,#0x40               // Check domain of interrupted thread
         BNE      SVC_ContextRestore2    // Branch if secure
         .endif
@@ -219,7 +219,7 @@ Sys_Context:
         BXEQ     LR                     // Exit when threads are the same
 
 Sys_ContextSave:
-        .if      __DOMAIN_NS == 1
+        .if      DOMAIN_NS == 1
         LDR      R0,[R1,#TCB_TZM_OFS]   // Load TrustZone memory identifier
         CBZ      R0,Sys_ContextSave1    // Branch if there is no secure context
         PUSH     {R1,R2,R3,LR}          // Save registers and EXC_RETURN
@@ -248,7 +248,7 @@ Sys_ContextSwitch:
         STR      R2,[R3]                // osRtxInfo.run: curr = next
 
 Sys_ContextRestore:
-        .if      __DOMAIN_NS == 1
+        .if      DOMAIN_NS == 1
         LDR      R0,[R2,#TCB_TZM_OFS]   // Load TrustZone memory identifier
         CBZ      R0,Sys_ContextRestore1 // Branch if there is no secure context
         PUSH     {R2,R3}                // Save registers
@@ -263,7 +263,7 @@ Sys_ContextRestore1:
         LDR      R0,[R2,#TCB_SP_OFS]    // Load SP
         ORR      LR,R1,#0xFFFFFF00      // Set EXC_RETURN
 
-        .if      __DOMAIN_NS == 1
+        .if      DOMAIN_NS == 1
         TST      LR,#0x40               // Check domain of interrupted thread
         BNE      Sys_ContextRestore2    // Branch if secure
         .endif

CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_fp_ns.S

@@ -1,4 +1,4 @@
         .equ     __FPU_USED,  1
-        .equ     __DOMAIN_NS, 1
+        .equ     DOMAIN_NS,   1
         .include "../Source/GCC/irq_armv8mml.S"
         .end

CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml_ns.S

@@ -1,3 +1,3 @@
-        .equ     __DOMAIN_NS, 1
+        .equ     DOMAIN_NS,   1
         .include "../Source/GCC/irq_armv8mml.S"
         .end

CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl.s

@@ -1,4 +1,4 @@
                 NAME    irq_armv8mbl.s
-                #define __DOMAIN_NS 0
+                #define DOMAIN_NS 0
                 INCLUDE irq_armv8mbl_common.s
                 END

CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl_common.s

@@ -24,8 +24,8 @@
 ; */
 
 
-#ifndef __DOMAIN_NS
-#define __DOMAIN_NS      0
+#ifndef DOMAIN_NS
+#define DOMAIN_NS        0
 #endif
 
 I_T_RUN_OFS     EQU      20                     ; osRtxInfo.thread.run offset
@@ -51,7 +51,7 @@ SVC_Handler
                 EXPORT   SVC_Handler
                 IMPORT   osRtxUserSVC
                 IMPORT   osRtxInfo
-                #if     (__DOMAIN_NS == 1)
+                #if     (DOMAIN_NS == 1)
                 IMPORT   TZ_LoadContext_S
                 IMPORT   TZ_StoreContext_S
                 #endif
@@ -84,7 +84,7 @@ SVC_Context
                 CBZ      R1,SVC_ContextSwitch   ; Branch if running thread is deleted
 
 SVC_ContextSave
-                #if     (__DOMAIN_NS == 1)
+                #if     (DOMAIN_NS == 1)
                 LDR      R0,[R1,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
                 CBZ      R0,SVC_ContextSave1    ; Branch if there is no secure context
                 PUSH     {R1,R2,R3,R7}          ; Save registers
@@ -115,7 +115,7 @@ SVC_ContextSwitch
                 STR      R2,[R3]                ; osRtxInfo.thread.run: curr = next
 
 SVC_ContextRestore
-                #if     (__DOMAIN_NS == 1)
+                #if     (DOMAIN_NS == 1)
                 LDR      R0,[R2,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
                 CBZ      R0,SVC_ContextRestore1 ; Branch if there is no secure context
                 PUSH     {R2,R3}                ; Save registers
@@ -132,7 +132,7 @@ SVC_ContextRestore1
                 ORRS     R0,R1
                 MOV      LR,R0                  ; Set EXC_RETURN
 
-                #if     (__DOMAIN_NS == 1)
+                #if     (DOMAIN_NS == 1)
                 LSLS     R0,R0,#25              ; Check domain of interrupted thread
                 BPL      SVC_ContextRestore2    ; Branch if non-secure
                 LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
@@ -207,7 +207,7 @@ SysTick_Handler
 Sys_Context
                 EXPORT   Sys_Context
                 IMPORT   osRtxInfo
-                #if     (__DOMAIN_NS == 1)
+                #if     (DOMAIN_NS == 1)
                 IMPORT   TZ_LoadContext_S
                 IMPORT   TZ_StoreContext_S
                 #endif
@@ -218,7 +218,7 @@ Sys_Context
                 BEQ      Sys_ContextExit        ; Branch when threads are the same
 
 Sys_ContextSave
-                #if     (__DOMAIN_NS == 1)
+                #if     (DOMAIN_NS == 1)
                 LDR      R0,[R1,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
                 CBZ      R0,Sys_ContextSave1    ; Branch if there is no secure context
                 PUSH     {R1,R2,R3,R7}          ; Save registers
@@ -255,7 +255,7 @@ Sys_ContextSwitch
                 STR      R2,[R3]                ; osRtxInfo.run: curr = next
 
 Sys_ContextRestore
-                #if     (__DOMAIN_NS == 1)
+                #if     (DOMAIN_NS == 1)
                 LDR      R0,[R2,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
                 CBZ      R0,Sys_ContextRestore1 ; Branch if there is no secure context
                 PUSH     {R2,R3}                ; Save registers
@@ -272,7 +272,7 @@ Sys_ContextRestore1
                 ORRS     R0,R1
                 MOV      LR,R0                  ; Set EXC_RETURN
 
-                #if     (__DOMAIN_NS == 1)
+                #if     (DOMAIN_NS == 1)
                 LSLS     R0,R0,#25              ; Check domain of interrupted thread
                 BPL      Sys_ContextRestore2    ; Branch if non-secure
                 LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP

CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl_ns.s

@@ -1,4 +1,4 @@
                 NAME    irq_armv8mbl_ns.s
-                #define __DOMAIN_NS 1
+                #define DOMAIN_NS 1
                 INCLUDE irq_armv8mbl_common.s
                 END

CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s

@@ -1,4 +1,4 @@
                 NAME    irq_armv8mml.s
-                #define __DOMAIN_NS 0
+                #define DOMAIN_NS 0
                 INCLUDE irq_armv8mml_common.s
                 END

CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_common.s

@@ -24,8 +24,8 @@
 ; */
 
 
-#ifndef __DOMAIN_NS
-#define __DOMAIN_NS      0
+#ifndef DOMAIN_NS
+#define DOMAIN_NS        0
 #endif
 
 #ifdef __ARMVFP__
@@ -57,7 +57,7 @@ SVC_Handler
                 EXPORT   SVC_Handler
                 IMPORT   osRtxUserSVC
                 IMPORT   osRtxInfo
-                #if     (__DOMAIN_NS == 1)
+                #if     (DOMAIN_NS == 1)
                 IMPORT   TZ_LoadContext_S
                 IMPORT   TZ_StoreContext_S
                 #endif
@@ -99,7 +99,7 @@ SVC_Context
                 #endif
 
 SVC_ContextSave
-                #if     (__DOMAIN_NS == 1)
+                #if     (DOMAIN_NS == 1)
                 LDR      R0,[R1,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
                 CBZ      R0,SVC_ContextSave1    ; Branch if there is no secure context
                 PUSH     {R1,R2,R3,LR}          ; Save registers and EXC_RETURN
@@ -124,7 +124,7 @@ SVC_ContextSwitch
                 STR      R2,[R3]                ; osRtxInfo.thread.run: curr = next
 
 SVC_ContextRestore
-                #if     (__DOMAIN_NS == 1)
+                #if     (DOMAIN_NS == 1)
                 LDR      R0,[R2,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
                 CBZ      R0,SVC_ContextRestore1 ; Branch if there is no secure context
                 PUSH     {R2,R3}                ; Save registers
@@ -139,7 +139,7 @@ SVC_ContextRestore1
                 LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
                 ORR      LR,R1,#0xFFFFFF00      ; Set EXC_RETURN
 
-                #if     (__DOMAIN_NS == 1)
+                #if     (DOMAIN_NS == 1)
                 TST      LR,#0x40               ; Check domain of interrupted thread
                 BNE      SVC_ContextRestore2    ; Branch if secure
                 #endif
@@ -197,7 +197,7 @@ SysTick_Handler
 Sys_Context
                 EXPORT   Sys_Context
                 IMPORT   osRtxInfo
-                #if     (__DOMAIN_NS == 1)
+                #if     (DOMAIN_NS == 1)
                 IMPORT   TZ_LoadContext_S
                 IMPORT   TZ_StoreContext_S
                 #endif
@@ -209,7 +209,7 @@ Sys_Context
                 BXEQ     LR                     ; Exit when threads are the same
 
 Sys_ContextSave
-                #if     (__DOMAIN_NS == 1)
+                #if     (DOMAIN_NS == 1)
                 LDR      R0,[R1,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
                 CBZ      R0,Sys_ContextSave1    ; Branch if there is no secure context
                 PUSH     {R1,R2,R3,LR}          ; Save registers and EXC_RETURN
@@ -238,7 +238,7 @@ Sys_ContextSwitch
                 STR      R2,[R3]                ; osRtxInfo.run: curr = next
 
 Sys_ContextRestore
-                #if     (__DOMAIN_NS == 1)
+                #if     (DOMAIN_NS == 1)
                 LDR      R0,[R2,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
                 CBZ      R0,Sys_ContextRestore1 ; Branch if there is no secure context
                 PUSH     {R2,R3}                ; Save registers
@@ -253,7 +253,7 @@ Sys_ContextRestore1
                 LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
                 ORR      LR,R1,#0xFFFFFF00      ; Set EXC_RETURN
 
-                #if     (__DOMAIN_NS == 1)
+                #if     (DOMAIN_NS == 1)
                 TST      LR,#0x40               ; Check domain of interrupted thread
                 BNE      Sys_ContextRestore2    ; Branch if secure
                 #endif

CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s

@@ -1,4 +1,4 @@
                 NAME    irq_armv8mml_ns.s
-                #define __DOMAIN_NS 1
+                #define DOMAIN_NS 1
                 INCLUDE irq_armv8mml_common.s
                 END

CMSIS/RTOS2/RTX/Source/rtx_core_c.h

@@ -29,35 +29,16 @@
 #include "RTE_Components.h"
 #include CMSIS_device_header
 
-#ifndef __ARM_ARCH_6M__
-#define __ARM_ARCH_6M__         0U
-#endif
-#ifndef __ARM_ARCH_7A__
-#define __ARM_ARCH_7A__         0U
-#endif
-#ifndef __ARM_ARCH_7M__
-#define __ARM_ARCH_7M__         0U
-#endif
-#ifndef __ARM_ARCH_7EM__
-#define __ARM_ARCH_7EM__        0U
-#endif
-#ifndef __ARM_ARCH_8M_BASE__
-#define __ARM_ARCH_8M_BASE__    0U
-#endif
-#ifndef __ARM_ARCH_8M_MAIN__
-#define __ARM_ARCH_8M_MAIN__    0U
-#endif
-
-#if   ((__ARM_ARCH_6M__      + \
-        __ARM_ARCH_7A__      + \
-        __ARM_ARCH_7M__      + \
-        __ARM_ARCH_7EM__     + \
-        __ARM_ARCH_8M_BASE__ + \
-        __ARM_ARCH_8M_MAIN__) != 1U)
+#if ((!defined(__ARM_ARCH_6M__))      && \
+     (!defined(__ARM_ARCH_7A__))      && \
+     (!defined(__ARM_ARCH_7M__))      && \
+     (!defined(__ARM_ARCH_7EM__))     && \
+     (!defined(__ARM_ARCH_8M_BASE__)) && \
+     (!defined(__ARM_ARCH_8M_MAIN__)))
 #error "Unknown ARM Architecture!"
 #endif
 
-#if (__ARM_ARCH_7A__ != 0U)
+#if   (defined(__ARM_ARCH_7A__) && (__ARM_ARCH_7A__ != 0))
 #include "rtx_core_ca.h"
 #else
 #include "rtx_core_cm.h"

CMSIS/RTOS2/RTX/Source/rtx_core_ca.h

@@ -26,44 +26,83 @@
 #ifndef RTX_CORE_CA_H_
 #define RTX_CORE_CA_H_
 
+#ifndef RTX_CORE_C_H_
 #include "RTE_Components.h"
 #include CMSIS_device_header
+#endif
+
+#include <stdbool.h>
+typedef bool bool_t;
+#define FALSE                   ((bool_t)0)
+#define TRUE                    ((bool_t)1)
 
-#define __DOMAIN_NS             0U
-#define __EXCLUSIVE_ACCESS      1U
+#define DOMAIN_NS               0
+#define EXCLUSIVE_ACCESS        1
 
-/* CPSR bit definitions */
+#define OS_TICK_HANDLER         osRtxTick_Handler
+
+// CPSR bit definitions
 #define CPSR_T_BIT              0x20U
 #define CPSR_I_BIT              0x80U
 #define CPSR_F_BIT              0x40U
 
-/* CPSR mode bitmasks */
+// CPSR mode bitmasks
 #define CPSR_MODE_USER          0x10U
 #define CPSR_MODE_SYSTEM        0x1FU
 
-/* Determine privilege level */
-#define IS_PRIVILEGED()          (__get_mode() != CPSR_MODE_USER)
-#define IS_IRQ_MODE()           ((__get_mode() != CPSR_MODE_USER) && (__get_mode() != CPSR_MODE_SYSTEM))
-#define IS_IRQ_MASKED()         (0U)
-
-#define xPSR_INIT(privileged, thumb)                                \
-  ((privileged) != 0U) ? (CPSR_MODE_SYSTEM | (((thumb) != 0U) ? CPSR_T_BIT : 0U)) : \
-                         (CPSR_MODE_USER   | (((thumb) != 0U) ? CPSR_T_BIT : 0U))
-
-#define STACK_FRAME_INIT        0x00U
+/// xPSR_Initialization Value
+/// \param[in]  privileged      true=privileged, false=unprivileged
+/// \param[in]  thumb           true=Thumb, false=ARM
+/// \return                     xPSR Init Value
+__STATIC_INLINE uint32_t xPSR_InitVal (bool_t privileged, bool_t thumb) {
+  uint32_t psr;
+
+  if (privileged) {
+    if (thumb) {
+      psr = CPSR_MODE_SYSTEM | CPSR_T_BIT;
+    } else {
+      psr = CPSR_MODE_SYSTEM;
+    }
+  } else {
+    if (thumb) {
+      psr = CPSR_MODE_USER   | CPSR_T_BIT;
+    } else {
+      psr = CPSR_MODE_USER;
+    }
+  }
+  
+  return psr;
+}
 
 // Stack Frame:
 //  - VFP-D32: D16-31, D0-D15, FPSCR, Reserved, R4-R11, R0-R3, R12, LR, PC, CPSR
 //  - VFP-D16:         D0-D15, FPSCR, Reserved, R4-R11, R0-R3, R12, LR, PC, CPSR
 //  - Basic:                                    R4-R11, R0-R3, R12, LR, PC, CPSR
-#define STACK_OFFSET_R0(stack_frame)                                  \
-  ((((stack_frame) & 0x04U) != 0U) ? ((32U*8U) + (2U*4U) + (8U*4U)) : \
-   (((stack_frame) & 0x02U) != 0U) ? ((16U*8U) + (2U*4U) + (8U*4U)) : \
-                                                           (8U*4U))
 
-#define OS_TICK_HANDLER         osRtxTick_Handler
+/// Stack Frame Initialization Value
+#define STACK_FRAME_INIT        0x00U
 
-/* Emulate M profile get_PSP: SP_usr - (8*4) */
+/// Stack Offset of Register R0
+/// \param[in]  stack_frame     Stack Frame
+/// \return                     R0 Offset
+__STATIC_INLINE uint32_t StackOffsetR0 (uint8_t stack_frame) {
+  uint32_t offset;
+
+  if        ((stack_frame & 0x04U) != 0U) {
+    offset = (32U*8U) + (2U*4U) + (8U*4U);
+  } else if ((stack_frame & 0x02U) != 0U) {
+    offset = (16U*8U) + (2U*4U) + (8U*4U);
+  } else {
+    offset =                      (8U*4U);
+  }
+  return offset;
+}
+
+
+//  ==== Emulated Cortex-M functions ====
+
+/// Get xPSR Register - emulate M profile: SP_usr - (8*4)
+/// \return      xPSR Register value
 #if defined(__CC_ARM)
 static __asm    uint32_t __get_PSP (void) {
   arm
@@ -77,8 +116,8 @@ static __asm    uint32_t __get_PSP (void) {
 __STATIC_INLINE uint32_t __get_PSP (void) {
   register uint32_t ret;
 
-  __asm volatile (
-#if !defined ( __ICCARM__ )
+  __ASM volatile (
+#ifndef __ICCARM__
     ".syntax unified\n\t"
     ".arm\n\t"
 #endif
@@ -95,7 +134,57 @@ __STATIC_INLINE uint32_t __get_PSP (void) {
 }
 #endif
 
+/// Set Control Register - not needed for A profile
+/// \param[in]  control         Control Register value to set
 __STATIC_INLINE void __set_CONTROL(uint32_t control) {
+  (void)control;
+}
+
+
+//  ==== Core functions ====
+
+/// Check if running Privileged
+/// \return     true=privileged, false=unprivileged
+__STATIC_INLINE bool_t IsPrivileged (void) {
+  return (__get_mode() != CPSR_MODE_USER);
+}
+
+/// Check if in IRQ Mode
+/// \return     true=IRQ, false=thread
+__STATIC_INLINE bool_t IsIrqMode (void) {
+  return ((__get_mode() != CPSR_MODE_USER) && (__get_mode() != CPSR_MODE_SYSTEM));
+}
+
+/// Check if IRQ is Masked
+/// \return     true=masked, false=not masked
+__STATIC_INLINE bool_t IsIrqMasked (void) {
+  return  FALSE;
+#endif
+}
+
+
+//  ==== Core Peripherals functions ====
+
+extern uint8_t IRQ_PendSV;
+
+/// Setup SVC and PendSV System Service Calls (not needed on Cortex-A)
+__STATIC_INLINE void SVC_Setup (void) {
+}
+
+/// Get Pending SV (Service Call) Flag
+/// \return     Pending SV Flag
+__STATIC_INLINE uint8_t GetPendSV (void) {
+  return (IRQ_PendSV);
+}
+
+/// Clear Pending SV (Service Call) Flag
+__STATIC_INLINE void ClrPendSV (void) {
+  IRQ_PendSV = 0U;
+}
+
+/// Set Pending SV (Service Call) Flag
+__STATIC_INLINE void SetPendSV (void) {
+  IRQ_PendSV = 1U;
 }
 
 
@@ -256,7 +345,6 @@ register uint32_t __rf   __ASM(SVC_RegF) = (uint32_t)f
 
 #define SVC_Out0
 #define SVC_Out1 "=r"(__r0)
-#define SVC_Out2 "=r"(__r0),"=r"(__r1)
 
 #define SVC_CL0
 #define SVC_CL1 "r1"
@@ -334,34 +422,9 @@ __STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) {                      \
 #endif
 
 
-//  ==== Core Peripherals functions ====
-
-extern uint8_t IRQ_PendSV;
-
-/// Setup SVC and PendSV System Service Calls (not needed on Cortex-A)
-__STATIC_INLINE void SVC_Setup (void) {
-}
-
-/// Get Pending SV (Service Call) Flag
-/// \return    Pending SV Flag
-__STATIC_INLINE uint8_t GetPendSV (void) {
-  return (IRQ_PendSV);
-}
-
-/// Clear Pending SV (Service Call) Flag
-__STATIC_INLINE void ClrPendSV (void) {
-  IRQ_PendSV = 0U;
-}
-
-/// Set Pending SV (Service Call) Flag
-__STATIC_INLINE void SetPendSV (void) {
-  IRQ_PendSV = 1U;
-}
-
-
 //  ==== Exclusive Access Operation ====
 
-#if (__EXCLUSIVE_ACCESS == 1U)
+#if (EXCLUSIVE_ACCESS == 1)
 
 /// Atomic Access Operation: Write (8-bit)
 /// \param[in]  mem             Memory address
@@ -1078,7 +1141,7 @@ __STATIC_INLINE void atomic_link_put (void **root, void *link) {
 }
 #endif
 
-#endif  // (__EXCLUSIVE_ACCESS == 1U)
+#endif  // (EXCLUSIVE_ACCESS == 1)
 
 
 #endif  // RTX_CORE_CA_H_

CMSIS/RTOS2/RTX/Source/rtx_core_cm.h

@@ -26,77 +26,173 @@
 #ifndef RTX_CORE_CM_H_
 #define RTX_CORE_CM_H_
 
+#ifndef RTX_CORE_C_H_
 #include "RTE_Components.h"
 #include CMSIS_device_header
+#endif
+
+#include <stdbool.h>
+typedef bool bool_t;
+#define FALSE                   ((bool_t)0)
+#define TRUE                    ((bool_t)1)
+
+#ifdef  RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS
+#define DOMAIN_NS               1
+#endif
 
-#ifdef RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS
-#define __DOMAIN_NS             1U
+#ifndef DOMAIN_NS
+#define DOMAIN_NS               0
 #endif
 
-#ifndef __DOMAIN_NS
-#define __DOMAIN_NS             0U
-#elif ((__DOMAIN_NS          == 1U) && \
-      ((__ARM_ARCH_6M__      == 1U) || \
-       (__ARM_ARCH_7M__      == 1U) || \
-       (__ARM_ARCH_7EM__     == 1U)))
+#if    (DOMAIN_NS == 1)
+#if   ((!defined(__ARM_ARCH_8M_BASE__) || (__ARM_ARCH_8M_BASE__ == 0)) && \
+       (!defined(__ARM_ARCH_8M_MAIN__) || (__ARM_ARCH_8M_MAIN__ == 0)))
 #error "Non-secure domain requires ARMv8-M Architecture!"
 #endif
+#endif
 
-#ifndef __EXCLUSIVE_ACCESS
-#if   ((__ARM_ARCH_7M__      == 1U) || \
-       (__ARM_ARCH_7EM__     == 1U) || \
-       (__ARM_ARCH_8M_BASE__ == 1U) || \
-       (__ARM_ARCH_8M_MAIN__ == 1U))
-#define __EXCLUSIVE_ACCESS      1U
+#ifndef EXCLUSIVE_ACCESS
+#if    ((defined(__ARM_ARCH_7M__)      && (__ARM_ARCH_7M__      != 0)) || \
+        (defined(__ARM_ARCH_7EM__)     && (__ARM_ARCH_7EM__     != 0)) || \
+        (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)) || \
+        (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)))
+#define EXCLUSIVE_ACCESS        1
 #else
-#define __EXCLUSIVE_ACCESS      0U
+#define EXCLUSIVE_ACCESS        0
 #endif
 #endif
 
-#define IS_PRIVILEGED()         ((__get_CONTROL() & 1U) == 0U)
+#define OS_TICK_HANDLER         SysTick_Handler
+
+/// xPSR_Initialization Value
+/// \param[in]  privileged      true=privileged, false=unprivileged
+/// \param[in]  thumb           true=Thumb, false=ARM
+/// \return                     xPSR Init Value
+__STATIC_INLINE uint32_t xPSR_InitVal (bool_t privileged, bool_t thumb) {
+  (void)privileged;
+  (void)thumb;
+  return (0x01000000U);
+}
 
-#define IS_IRQ_MODE()            (__get_IPSR() != 0U)
+// Stack Frame:
+//  - Extended: S16-S31, R4-R11, R0-R3, R12, LR, PC, xPSR, S0-S15, FPSCR
+//  - Basic:             R4-R11, R0-R3, R12, LR, PC, xPSR
 
-#if   ((__ARM_ARCH_7M__      == 1U) || \
-       (__ARM_ARCH_7EM__     == 1U) || \
-       (__ARM_ARCH_8M_MAIN__ == 1U))
-#define IS_IRQ_MASKED()         ((__get_PRIMASK() != 0U) || (__get_BASEPRI() != 0U))
+/// Stack Frame Initialization Value (EXC_RETURN[7..0])
+#if (DOMAIN_NS == 1)
+#define STACK_FRAME_INIT_VAL    0xBCU
 #else
-#define IS_IRQ_MASKED()          (__get_PRIMASK() != 0U) 
+#define STACK_FRAME_INIT_VAL    0xFDU
 #endif
 
-#define xPSR_INIT(...)          0x01000000U
-
-#if    (__DOMAIN_NS == 1U)
-#define STACK_FRAME_INIT        0xBCU
+/// Stack Offset of Register R0
+/// \param[in]  stack_frame     Stack Frame (EXC_RETURN[7..0])
+/// \return                     R0 Offset
+__STATIC_INLINE uint32_t StackOffsetR0 (uint8_t stack_frame) {
+#if (__FPU_USED == 1U)
+  return (((stack_frame & 0x10U) == 0U) ? ((16U+8U)*4U) : (8U*4U));
 #else
-#define STACK_FRAME_INIT        0xFDU
+  (void)stack_frame;
+  return (8U*4U);
 #endif
+}
 
-// Stack Frame:
-//  - Extended: S16-S31, R4-R11, R0-R3, R12, LR, PC, xPSR, S0-S15, FPSCR
-//  - Basic:             R4-R11, R0-R3, R12, LR, PC, xPSR
-#if (__FPU_USED == 1U)
-#define STACK_OFFSET_R0(stack_frame)                 \
-  ((((stack_frame) & 0x10U) == 0U) ? ((16U+8U)*4U) : \
-                                          (8U *4U))
+
+//  ==== Core functions ====
+
+/// Check if running Privileged
+/// \return     true=privileged, false=unprivileged
+__STATIC_INLINE bool_t IsPrivileged (void) {
+  return ((__get_CONTROL() & 1U) == 0U);
+}
+
+/// Check if in IRQ Mode
+/// \return     true=IRQ, false=thread
+__STATIC_INLINE bool_t IsIrqMode (void) {
+  return (__get_IPSR() != 0U);
+}
+
+/// Check if IRQ is Masked
+/// \return     true=masked, false=not masked
+__STATIC_INLINE bool_t IsIrqMasked (void) {
+#if   ((defined(__ARM_ARCH_7M__)      && (__ARM_ARCH_7M__      != 0)) || \
+       (defined(__ARM_ARCH_7EM__)     && (__ARM_ARCH_7EM__     != 0)) || \
+       (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)))
+  return ((__get_PRIMASK() != 0U) || (__get_BASEPRI() != 0U));
 #else
-#define STACK_OFFSET_R0(stack_frame)      (8U *4U)
+  return  (__get_PRIMASK() != 0U);
 #endif
+}
 
-#define OS_TICK_HANDLER         SysTick_Handler
+
+//  ==== Core Peripherals functions ====
+
+/// Setup SVC and PendSV System Service Calls
+__STATIC_INLINE void SVC_Setup (void) {
+#if   ((defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)) || \
+       (defined(__CORTEX_M)           && (__CORTEX_M == 7U)))
+  uint32_t p, n;
+
+  SCB->SHPR[10] = 0xFFU;
+  n = 32U - (uint32_t)__CLZ(~(SCB->SHPR[10] | 0xFFFFFF00U));
+  p = NVIC_GetPriorityGrouping();
+  if (p >= n) {
+    n = p + 1U;
+  }
+  SCB->SHPR[7] = (uint8_t)(0xFEU << n);
+#elif  (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0))
+  uint32_t n;
+
+  SCB->SHPR[1] |= 0x00FF0000U;
+  n = SCB->SHPR[1];
+  SCB->SHPR[0] |= (n << (8+1)) & 0xFC000000U;
+#elif ((defined(__ARM_ARCH_7M__)      && (__ARM_ARCH_7M__      != 0)) || \
+       (defined(__ARM_ARCH_7EM__)     && (__ARM_ARCH_7EM__     != 0)))
+  uint32_t p, n;
+
+  SCB->SHP[10] = 0xFFU;
+  n = 32U - (uint32_t)__CLZ(~(SCB->SHP[10] | 0xFFFFFF00U));
+  p = NVIC_GetPriorityGrouping();
+  if (p >= n) {
+    n = p + 1U;
+  }
+  SCB->SHP[7] = (uint8_t)(0xFEU << n);
+#elif  (defined(__ARM_ARCH_6M__)      && (__ARM_ARCH_6M__      != 0))
+  uint32_t n;
+
+  SCB->SHP[1] |= 0x00FF0000U;
+  n = SCB->SHP[1];
+  SCB->SHP[0] |= (n << (8+1)) & 0xFC000000U;
+#endif
+}
+
+/// Get Pending SV (Service Call) Flag
+/// \return     Pending SV Flag
+__STATIC_INLINE uint8_t GetPendSV (void) {
+  return ((uint8_t)((SCB->ICSR & (SCB_ICSR_PENDSVSET_Msk)) >> 24));
+}
+
+/// Clear Pending SV (Service Call) Flag
+__STATIC_INLINE void ClrPendSV (void) {
+  SCB->ICSR = SCB_ICSR_PENDSVCLR_Msk;
+}
+
+/// Set Pending SV (Service Call) Flag
+__STATIC_INLINE void SetPendSV (void) {
+  SCB->ICSR = SCB_ICSR_PENDSVSET_Msk;
+}
 
 
 //  ==== Service Calls definitions ====
 
 #if defined(__CC_ARM)
 
-#if   ((__ARM_ARCH_7M__      == 1U) || \
-       (__ARM_ARCH_7EM__     == 1U) || \
-       (__ARM_ARCH_8M_MAIN__ == 1U))
+#if   ((defined(__ARM_ARCH_7M__)      && (__ARM_ARCH_7M__      != 0)) ||       \
+       (defined(__ARM_ARCH_7EM__)     && (__ARM_ARCH_7EM__     != 0)) ||       \
+       (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)))
 #define __SVC_INDIRECT(n) __svc_indirect(n)
-#elif ((__ARM_ARCH_6M__      == 1U) || \
-       (__ARM_ARCH_8M_BASE__ == 1U))
+#elif ((defined(__ARM_ARCH_6M__)      && (__ARM_ARCH_6M__      != 0)) ||       \
+       (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)))
 #define __SVC_INDIRECT(n) __svc_indirect_r7(n)
 #endif
 
@@ -158,17 +254,17 @@ __STATIC_INLINE   t  __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) {                   \
 
 #elif defined(__ICCARM__)
 
-#if   ((__ARM_ARCH_7M__      == 1U) || \
-       (__ARM_ARCH_7EM__     == 1U) || \
-       (__ARM_ARCH_8M_MAIN__ == 1U))
-#define SVC_ArgF(f)                                                           \
+#if   ((defined(__ARM_ARCH_7M__)      && (__ARM_ARCH_7M__      != 0)) ||       \
+       (defined(__ARM_ARCH_7EM__)     && (__ARM_ARCH_7EM__     != 0)) ||       \
+       (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)))
+#define SVC_ArgF(f)                                                            \
   __asm(                                                                       \
     "mov r12,%0\n"                                                             \
     :: "r"(&f): "r12"                                                          \
   );
-#elif ((__ARM_ARCH_6M__      == 1U) || \
-       (__ARM_ARCH_8M_BASE__ == 1U))
-#define SVC_ArgF(f)                                                           \
+#elif ((defined(__ARM_ARCH_6M__)      && (__ARM_ARCH_6M__      != 0)) ||       \
+       (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)))
+#define SVC_ArgF(f)                                                            \
   __asm(                                                                       \
     "mov r7,%0\n"                                                              \
     :: "r"(&f): "r7"                                                           \
@@ -243,12 +339,12 @@ __STATIC_INLINE   t  __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) {                   \
 
 #else   // !(defined(__CC_ARM) || defined(__ICCARM__))
 
-#if   ((__ARM_ARCH_7M__      == 1U) || \
-       (__ARM_ARCH_7EM__     == 1U) || \
-       (__ARM_ARCH_8M_MAIN__ == 1U))
+#if   ((defined(__ARM_ARCH_7M__)      && (__ARM_ARCH_7M__      != 0)) ||       \
+       (defined(__ARM_ARCH_7EM__)     && (__ARM_ARCH_7EM__     != 0)) ||       \
+       (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)))
 #define SVC_RegF "r12"
-#elif ((__ARM_ARCH_6M__      == 1U) || \
-       (__ARM_ARCH_8M_BASE__ == 1U))
+#elif ((defined(__ARM_ARCH_6M__)      && (__ARM_ARCH_6M__      != 0)) ||       \
+       (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)))
 #define SVC_RegF "r7"
 #endif
 
@@ -269,7 +365,6 @@ register uint32_t __rf   __ASM(SVC_RegF) = (uint32_t)f
 
 #define SVC_Out0
 #define SVC_Out1 "=r"(__r0)
-#define SVC_Out2 "=r"(__r0),"=r"(__r1)
 
 #define SVC_CL0
 #define SVC_CL1 "r1"
@@ -347,66 +442,9 @@ __STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) {                      \
 #endif
 
 
-//  ==== Core Peripherals functions ====
-
-/// Setup SVC and PendSV System Service Calls
-__STATIC_INLINE void SVC_Setup (void) {
-#if   ((__ARM_ARCH_8M_MAIN__ == 1U) || (defined(__CORTEX_M) && (__CORTEX_M == 7U)))
-  uint32_t p, n;
-
-  SCB->SHPR[10] = 0xFFU;
-  n = 32U - (uint32_t)__CLZ(~(SCB->SHPR[10] | 0xFFFFFF00U));
-  p = NVIC_GetPriorityGrouping();
-  if (p >= n) {
-    n = p + 1U;
-  }
-  SCB->SHPR[7] = (uint8_t)(0xFEU << n);
-#elif  (__ARM_ARCH_8M_BASE__ == 1U)
-  uint32_t n;
-
-  SCB->SHPR[1] |= 0x00FF0000U;
-  n = SCB->SHPR[1];
-  SCB->SHPR[0] |= (n << (8+1)) & 0xFC000000U;
-#elif ((__ARM_ARCH_7M__      == 1U) || \
-       (__ARM_ARCH_7EM__     == 1U))
-  uint32_t p, n;
-
-  SCB->SHP[10] = 0xFFU;
-  n = 32U - (uint32_t)__CLZ(~(SCB->SHP[10] | 0xFFFFFF00U));
-  p = NVIC_GetPriorityGrouping();
-  if (p >= n) {
-    n = p + 1U;
-  }
-  SCB->SHP[7] = (uint8_t)(0xFEU << n);
-#elif  (__ARM_ARCH_6M__      == 1U)
-  uint32_t n;
-
-  SCB->SHP[1] |= 0x00FF0000U;
-  n = SCB->SHP[1];
-  SCB->SHP[0] |= (n << (8+1)) & 0xFC000000U;
-#endif
-}
-
-/// Get Pending SV (Service Call) Flag
-/// \return    Pending SV Flag
-__STATIC_INLINE uint8_t GetPendSV (void) {
-  return ((uint8_t)((SCB->ICSR & (SCB_ICSR_PENDSVSET_Msk)) >> 24));
-}
-
-/// Clear Pending SV (Service Call) Flag
-__STATIC_INLINE void ClrPendSV (void) {
-  SCB->ICSR = SCB_ICSR_PENDSVCLR_Msk;
-}
-
-/// Set Pending SV (Service Call) Flag
-__STATIC_INLINE void SetPendSV (void) {
-  SCB->ICSR = SCB_ICSR_PENDSVSET_Msk;
-}
-
-
 //  ==== Exclusive Access Operation ====
 
-#if (__EXCLUSIVE_ACCESS == 1U)
+#if (EXCLUSIVE_ACCESS == 1)
 
 /// Atomic Access Operation: Write (8-bit)
 /// \param[in]  mem             Memory address
@@ -488,7 +526,7 @@ __STATIC_INLINE uint32_t atomic_set32 (uint32_t *mem, uint32_t bits) {
 #endif
   "1:\n\t"
     "ldrex %[val],[%[mem]]\n\t"
-#if (__ARM_ARCH_8M_BASE__ == 1U)
+#if (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0))
     "mov   %[ret],%[val]\n\t"
     "orrs  %[ret],%[bits]\n\t"
 #else
@@ -503,7 +541,7 @@ __STATIC_INLINE uint32_t atomic_set32 (uint32_t *mem, uint32_t bits) {
     [res]  "=&l" (res)
   : [mem]  "l"   (mem),
     [bits] "l"   (bits)
-#if (__ARM_ARCH_8M_BASE__ == 1U)
+#if (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0))
   : "memory", "cc"
 #else
   : "memory"
@@ -548,7 +586,7 @@ __STATIC_INLINE uint32_t atomic_clr32 (uint32_t *mem, uint32_t bits) {
 #endif
   "1:\n\t"
     "ldrex %[ret],[%[mem]]\n\t"
-#if (__ARM_ARCH_8M_BASE__ == 1U)
+#if (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0))
     "mov   %[val],%[ret]\n\t"
     "bics  %[val],%[bits]\n\t"
 #else
@@ -563,7 +601,7 @@ __STATIC_INLINE uint32_t atomic_clr32 (uint32_t *mem, uint32_t bits) {
     [res]  "=&l" (res)
   : [mem]  "l"   (mem),
     [bits] "l"   (bits)
-#if (__ARM_ARCH_8M_BASE__ == 1U)
+#if (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0))
   : "memory", "cc"
 #else
   : "memory"
@@ -615,7 +653,7 @@ __STATIC_INLINE uint32_t atomic_chk32_all (uint32_t *mem, uint32_t bits) {
 #endif
   "1:\n\t"
     "ldrex %[ret],[%[mem]]\n\t"
-#if (__ARM_ARCH_8M_BASE__ == 1U)
+#if (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0))
     "mov   %[val],%[ret]\n\t"
     "ands  %[val],%[bits]\n\t"
 #else
@@ -627,7 +665,7 @@ __STATIC_INLINE uint32_t atomic_chk32_all (uint32_t *mem, uint32_t bits) {
     "movs  %[ret],#0\n\t"
     "b     3f\n"
   "2:\n\t"
-#if (__ARM_ARCH_8M_BASE__ == 1U)
+#if (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0))
     "mov   %[val],%[ret]\n\t"
     "bics  %[val],%[bits]\n\t"
 #else
@@ -695,7 +733,7 @@ __STATIC_INLINE uint32_t atomic_chk32_any (uint32_t *mem, uint32_t bits) {
     "movs  %[ret],#0\n\t"
     "b     3f\n"
   "2:\n\t"
-#if (__ARM_ARCH_8M_BASE__ == 1U)
+#if (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0))
     "mov   %[val],%[ret]\n\t"
     "bics  %[val],%[bits]\n\t"
 #else
@@ -1169,7 +1207,7 @@ __STATIC_INLINE void atomic_link_put (void **root, void *link) {
 }
 #endif
 
-#endif  // (__EXCLUSIVE_ACCESS == 1U)
+#endif  // (EXCLUSIVE_ACCESS == 1)
 
 
 #endif  // RTX_CORE_CM_H_

CMSIS/RTOS2/RTX/Source/rtx_delay.c

@@ -69,7 +69,7 @@ osStatus_t svcRtxDelayUntil (uint32_t ticks) {
 /// Wait for Timeout (Time Delay).
 osStatus_t osDelay (uint32_t ticks) {
   EvrRtxThreadDelay(ticks);
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxThreadError(NULL, (int32_t)osErrorISR);
     return osErrorISR;
   }
@@ -79,7 +79,7 @@ osStatus_t osDelay (uint32_t ticks) {
 /// Wait until specified time.
 osStatus_t osDelayUntil (uint32_t ticks) {
   EvrRtxThreadDelayUntil(ticks);
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxThreadError(NULL, (int32_t)osErrorISR);
     return osErrorISR;
   }

CMSIS/RTOS2/RTX/Source/rtx_evflags.c

@@ -33,12 +33,12 @@
 /// \param[in]  flags           specifies the flags to set.
 /// \return event flags after setting.
 static uint32_t EventFlagsSet (os_event_flags_t *ef, uint32_t flags) {
-#if (__EXCLUSIVE_ACCESS == 0U)
+#if (EXCLUSIVE_ACCESS == 0)
   uint32_t primask = __get_PRIMASK();
 #endif
   uint32_t event_flags;
 
-#if (__EXCLUSIVE_ACCESS == 0U)
+#if (EXCLUSIVE_ACCESS == 0)
   __disable_irq();
 
   ef->event_flags |= flags;
@@ -59,12 +59,12 @@ static uint32_t EventFlagsSet (os_event_flags_t *ef, uint32_t flags) {
 /// \param[in]  flags           specifies the flags to clear.
 /// \return event flags before clearing.
 static uint32_t EventFlagsClear (os_event_flags_t *ef, uint32_t flags) {
-#if (__EXCLUSIVE_ACCESS == 0U)
+#if (EXCLUSIVE_ACCESS == 0)
   uint32_t primask = __get_PRIMASK();
 #endif
   uint32_t event_flags;
 
-#if (__EXCLUSIVE_ACCESS == 0U)
+#if (EXCLUSIVE_ACCESS == 0)
   __disable_irq();
 
   event_flags = ef->event_flags;
@@ -86,13 +86,13 @@ static uint32_t EventFlagsClear (os_event_flags_t *ef, uint32_t flags) {
 /// \param[in]  options         specifies flags options (osFlagsXxxx).
 /// \return event flags before clearing or 0 if specified flags have not been set.
 static uint32_t EventFlagsCheck (os_event_flags_t *ef, uint32_t flags, uint32_t options) {
-#if (__EXCLUSIVE_ACCESS == 0U)
+#if (EXCLUSIVE_ACCESS == 0)
   uint32_t primask;
 #endif
   uint32_t event_flags;
 
   if ((options & osFlagsNoClear) == 0U) {
-#if (__EXCLUSIVE_ACCESS == 0U)
+#if (EXCLUSIVE_ACCESS == 0)
     primask = __get_PRIMASK();
     __disable_irq();
 
@@ -511,7 +511,7 @@ uint32_t isrRtxEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t
 /// Create and Initialize an Event Flags object.
 osEventFlagsId_t osEventFlagsNew (const osEventFlagsAttr_t *attr) {
   EvrRtxEventFlagsNew(attr);
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxEventFlagsError(NULL, (int32_t)osErrorISR);
     return NULL;
   }
@@ -520,7 +520,7 @@ osEventFlagsId_t osEventFlagsNew (const osEventFlagsAttr_t *attr) {
 
 /// Get name of an Event Flags object.
 const char *osEventFlagsGetName (osEventFlagsId_t ef_id) {
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxEventFlagsGetName(ef_id, NULL);
     return NULL;
   }
@@ -530,7 +530,7 @@ const char *osEventFlagsGetName (osEventFlagsId_t ef_id) {
 /// Set the specified Event Flags.
 uint32_t osEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags) {
   EvrRtxEventFlagsSet(ef_id, flags);
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     return isrRtxEventFlagsSet(ef_id, flags);
   } else {
     return  __svcEventFlagsSet(ef_id, flags);
@@ -540,7 +540,7 @@ uint32_t osEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags) {
 /// Clear the specified Event Flags.
 uint32_t osEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags) {
   EvrRtxEventFlagsClear(ef_id, flags);
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     return svcRtxEventFlagsClear(ef_id, flags);
   } else {
     return  __svcEventFlagsClear(ef_id, flags);
@@ -549,7 +549,7 @@ uint32_t osEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags) {
 
 /// Get the current Event Flags.
 uint32_t osEventFlagsGet (osEventFlagsId_t ef_id) {
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     return svcRtxEventFlagsGet(ef_id);
   } else {
     return  __svcEventFlagsGet(ef_id);
@@ -559,7 +559,7 @@ uint32_t osEventFlagsGet (osEventFlagsId_t ef_id) {
 /// Wait for one or more Event Flags to become signaled.
 uint32_t osEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout) {
   EvrRtxEventFlagsWait(ef_id, flags, options, timeout);
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     return isrRtxEventFlagsWait(ef_id, flags, options, timeout);
   } else {
     return  __svcEventFlagsWait(ef_id, flags, options, timeout);
@@ -569,7 +569,7 @@ uint32_t osEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t opti
 /// Delete an Event Flags object.
 osStatus_t osEventFlagsDelete (osEventFlagsId_t ef_id) {
   EvrRtxEventFlagsDelete(ef_id);
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxEventFlagsError(ef_id, (int32_t)osErrorISR);
     return osErrorISR;
   }

CMSIS/RTOS2/RTX/Source/rtx_kernel.c

@@ -187,7 +187,7 @@ osStatus_t svcRtxKernelInitialize (void) {
     osRtxInfo.mpi.message_queue = osRtxConfig.mpi.message_queue;
   }
 
-#if (__DOMAIN_NS == 1U)
+#if (DOMAIN_NS == 1)
   // Initialize Secure Process Stack
   if (TZ_InitContextSystem_S() == 0U) {
     EvrRtxKernelError(osRtxErrorTZ_InitContext_S);
@@ -270,9 +270,7 @@ osStatus_t svcRtxKernelStart (void) {
   osRtxInfo.tick_irqn = OS_Tick_GetIRQn();
 
   // Enable RTOS Tick
-  if (OS_Tick_Enable() != 0U) {
-    return osError;
-  }
+  OS_Tick_Enable();
 
   // Switch to Ready Thread with highest Priority
   thread = osRtxThreadListGet(&osRtxInfo.thread.ready);
@@ -502,7 +500,7 @@ uint32_t svcRtxKernelGetSysTimerFreq (void) {
 /// Initialize the RTOS Kernel.
 osStatus_t osKernelInitialize (void) {
   EvrRtxKernelInitialize();
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxKernelError((int32_t)osErrorISR);
     return osErrorISR;
   }
@@ -512,7 +510,7 @@ osStatus_t osKernelInitialize (void) {
 ///  Get RTOS Kernel Information.
 osStatus_t osKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size) {
   EvrRtxKernelGetInfo(version, id_buf, id_size);
-  if (IS_PRIVILEGED() || IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsPrivileged() || IsIrqMode() || IsIrqMasked()) {
     return svcRtxKernelGetInfo(version, id_buf, id_size);
   } else {
     return  __svcKernelGetInfo(version, id_buf, id_size);
@@ -521,7 +519,7 @@ osStatus_t osKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size
 
 /// Get the current RTOS Kernel state.
 osKernelState_t osKernelGetState (void) {
-  if (IS_PRIVILEGED() || IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsPrivileged() || IsIrqMode() || IsIrqMasked()) {
     return svcRtxKernelGetState();
   } else {
     return  __svcKernelGetState();
@@ -531,7 +529,7 @@ osKernelState_t osKernelGetState (void) {
 /// Start the RTOS Kernel scheduler.
 osStatus_t osKernelStart (void) {
   EvrRtxKernelStart();
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxKernelError((int32_t)osErrorISR);
     return osErrorISR;
   }
@@ -541,7 +539,7 @@ osStatus_t osKernelStart (void) {
 /// Lock the RTOS Kernel scheduler.
 int32_t osKernelLock (void) {
   EvrRtxKernelLock();
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxKernelError((int32_t)osErrorISR);
     return osErrorISR;
   }
@@ -551,7 +549,7 @@ int32_t osKernelLock (void) {
 /// Unlock the RTOS Kernel scheduler.
 int32_t osKernelUnlock (void) {
   EvrRtxKernelUnlock();
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxKernelError((int32_t)osErrorISR);
     return osErrorISR;
   }
@@ -561,7 +559,7 @@ int32_t osKernelUnlock (void) {
 /// Restore the RTOS Kernel scheduler lock state.
 int32_t osKernelRestoreLock (int32_t lock) {
   EvrRtxKernelRestoreLock(lock);
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxKernelError((int32_t)osErrorISR);
     return osErrorISR;
   }
@@ -571,7 +569,7 @@ int32_t osKernelRestoreLock (int32_t lock) {
 /// Suspend the RTOS Kernel scheduler.
 uint32_t osKernelSuspend (void) {
   EvrRtxKernelSuspend();
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxKernelError((int32_t)osErrorISR);
     return 0U;
   }
@@ -581,7 +579,7 @@ uint32_t osKernelSuspend (void) {
 /// Resume the RTOS Kernel scheduler.
 void osKernelResume (uint32_t sleep_ticks) {
   EvrRtxKernelResume(sleep_ticks);
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxKernelError((int32_t)osErrorISR);
     return;
   }
@@ -590,7 +588,7 @@ void osKernelResume (uint32_t sleep_ticks) {
 
 /// Get the RTOS kernel tick count.
 uint32_t osKernelGetTickCount (void) {
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     return svcRtxKernelGetTickCount();
   } else {
     return  __svcKernelGetTickCount();
@@ -599,7 +597,7 @@ uint32_t osKernelGetTickCount (void) {
 
 /// Get the RTOS kernel tick frequency.
 uint32_t osKernelGetTickFreq (void) {
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     return svcRtxKernelGetTickFreq();
   } else {
     return  __svcKernelGetTickFreq();
@@ -608,7 +606,7 @@ uint32_t osKernelGetTickFreq (void) {
 
 /// Get the RTOS kernel system timer count.
 uint32_t osKernelGetSysTimerCount (void) {
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     return svcRtxKernelGetSysTimerCount();
   } else {
     return  __svcKernelGetSysTimerCount();
@@ -617,7 +615,7 @@ uint32_t osKernelGetSysTimerCount (void) {
 
 /// Get the RTOS kernel system timer frequency.
 uint32_t osKernelGetSysTimerFreq (void) {
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     return svcRtxKernelGetSysTimerFreq();
   } else {
     return  __svcKernelGetSysTimerFreq();

CMSIS/RTOS2/RTX/Source/rtx_lib.h

@@ -29,7 +29,8 @@
 #include <string.h>
 #include <stdbool.h>
 #include "rtx_core_c.h"                 // Cortex core definitions
-#if ((__ARM_ARCH_8M_BASE__ != 0) || (__ARM_ARCH_8M_MAIN__ != 0))
+#if ((defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)) || \
+     (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)))
 #include "tz_context.h"                 // TrustZone Context API
 #endif
 #include "os_tick.h"

CMSIS/RTOS2/RTX/Source/rtx_mempool.c

@@ -67,7 +67,7 @@ uint32_t osRtxMemoryPoolInit (os_mp_info_t *mp_info, uint32_t block_count, uint3
 /// \param[in]  mp_info         memory pool info.
 /// \return address of the allocated memory block or NULL in case of no memory is available.
 void *osRtxMemoryPoolAlloc (os_mp_info_t *mp_info) {
-#if (__EXCLUSIVE_ACCESS == 0U)
+#if (EXCLUSIVE_ACCESS == 0)
   uint32_t primask = __get_PRIMASK();
 #endif
   void *block;
@@ -77,7 +77,7 @@ void *osRtxMemoryPoolAlloc (os_mp_info_t *mp_info) {
     return NULL;
   }
 
-#if (__EXCLUSIVE_ACCESS == 0U)
+#if (EXCLUSIVE_ACCESS == 0)
   __disable_irq();
 
   if (mp_info->used_blocks < mp_info->max_blocks) {
@@ -111,7 +111,7 @@ void *osRtxMemoryPoolAlloc (os_mp_info_t *mp_info) {
 /// \param[in]  block           address of the allocated memory block to be returned to the memory pool.
 /// \return status code that indicates the execution status of the function.
 osStatus_t osRtxMemoryPoolFree (os_mp_info_t *mp_info, void *block) {
-#if (__EXCLUSIVE_ACCESS == 0U)
+#if (EXCLUSIVE_ACCESS == 0)
   uint32_t primask = __get_PRIMASK();
 #endif
   osStatus_t status;
@@ -121,7 +121,7 @@ osStatus_t osRtxMemoryPoolFree (os_mp_info_t *mp_info, void *block) {
     return osErrorParameter;
   }
 
-#if (__EXCLUSIVE_ACCESS == 0U)
+#if (EXCLUSIVE_ACCESS == 0)
   __disable_irq();
 
   if (mp_info->used_blocks != 0U) {
@@ -602,7 +602,7 @@ osStatus_t isrRtxMemoryPoolFree (osMemoryPoolId_t mp_id, void *block) {
 /// Create and Initialize a Memory Pool object.
 osMemoryPoolId_t osMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr) {
   EvrRtxMemoryPoolNew(block_count, block_size, attr);
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxMemoryPoolError(NULL, (int32_t)osErrorISR);
     return NULL;
   }
@@ -611,7 +611,7 @@ osMemoryPoolId_t osMemoryPoolNew (uint32_t block_count, uint32_t block_size, con
 
 /// Get name of a Memory Pool object.
 const char *osMemoryPoolGetName (osMemoryPoolId_t mp_id) {
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxMemoryPoolGetName(mp_id, NULL);
     return NULL;
   }
@@ -621,7 +621,7 @@ const char *osMemoryPoolGetName (osMemoryPoolId_t mp_id) {
 /// Allocate a memory block from a Memory Pool.
 void *osMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout) {
   EvrRtxMemoryPoolAlloc(mp_id, timeout);
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     return isrRtxMemoryPoolAlloc(mp_id, timeout);
   } else {
     return  __svcMemoryPoolAlloc(mp_id, timeout);
@@ -631,7 +631,7 @@ void *osMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout) {
 /// Return an allocated memory block back to a Memory Pool.
 osStatus_t osMemoryPoolFree (osMemoryPoolId_t mp_id, void *block) {
   EvrRtxMemoryPoolFree(mp_id, block);
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     return isrRtxMemoryPoolFree(mp_id, block);
   } else {
     return  __svcMemoryPoolFree(mp_id, block);
@@ -640,7 +640,7 @@ osStatus_t osMemoryPoolFree (osMemoryPoolId_t mp_id, void *block) {
 
 /// Get maximum number of memory blocks in a Memory Pool.
 uint32_t osMemoryPoolGetCapacity (osMemoryPoolId_t mp_id) {
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     return svcRtxMemoryPoolGetCapacity(mp_id);
   } else {
     return  __svcMemoryPoolGetCapacity(mp_id);
@@ -649,7 +649,7 @@ uint32_t osMemoryPoolGetCapacity (osMemoryPoolId_t mp_id) {
 
 /// Get memory block size in a Memory Pool.
 uint32_t osMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id) {
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     return svcRtxMemoryPoolGetBlockSize(mp_id);
   } else {
     return  __svcMemoryPoolGetBlockSize(mp_id);
@@ -658,7 +658,7 @@ uint32_t osMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id) {
 
 /// Get number of memory blocks used in a Memory Pool.
 uint32_t osMemoryPoolGetCount (osMemoryPoolId_t mp_id) {
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     return svcRtxMemoryPoolGetCount(mp_id);
   } else {
     return  __svcMemoryPoolGetCount(mp_id);
@@ -667,7 +667,7 @@ uint32_t osMemoryPoolGetCount (osMemoryPoolId_t mp_id) {
 
 /// Get number of memory blocks available in a Memory Pool.
 uint32_t osMemoryPoolGetSpace (osMemoryPoolId_t mp_id) {
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     return svcRtxMemoryPoolGetSpace(mp_id);
   } else {
     return  __svcMemoryPoolGetSpace(mp_id);
@@ -677,7 +677,7 @@ uint32_t osMemoryPoolGetSpace (osMemoryPoolId_t mp_id) {
 /// Delete a Memory Pool object.
 osStatus_t osMemoryPoolDelete (osMemoryPoolId_t mp_id) {
   EvrRtxMemoryPoolDelete(mp_id);
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxMemoryPoolError(mp_id, (int32_t)osErrorISR);
     return osErrorISR;
   }

CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c

@@ -32,7 +32,7 @@
 /// \param[in]  mq              message queue object.
 /// \param[in]  msg             message object.
 static void MessageQueuePut (os_message_queue_t *mq, os_message_t *msg) {
-#if (__EXCLUSIVE_ACCESS == 0U)
+#if (EXCLUSIVE_ACCESS == 0)
   uint32_t      primask = __get_PRIMASK();
 #endif
   os_message_t *prev, *next;
@@ -63,7 +63,7 @@ static void MessageQueuePut (os_message_queue_t *mq, os_message_t *msg) {
     mq->msg_last = msg;
   }
 
-#if (__EXCLUSIVE_ACCESS == 0U)
+#if (EXCLUSIVE_ACCESS == 0)
   __disable_irq();
 
   mq->msg_count++;
@@ -80,14 +80,14 @@ static void MessageQueuePut (os_message_queue_t *mq, os_message_t *msg) {
 /// \param[in]  mq              message queue object.
 /// \return message object or NULL.
 static os_message_t *MessageQueueGet (os_message_queue_t *mq) {
-#if (__EXCLUSIVE_ACCESS == 0U)
+#if (EXCLUSIVE_ACCESS == 0)
   uint32_t      primask = __get_PRIMASK();
 #endif
   os_message_t *msg;
   uint32_t      count;
   uint8_t       flags;
 
-#if (__EXCLUSIVE_ACCESS == 0U)
+#if (EXCLUSIVE_ACCESS == 0)
   __disable_irq();
 
   count = mq->msg_count;
@@ -109,7 +109,7 @@ static os_message_t *MessageQueueGet (os_message_queue_t *mq) {
   msg = mq->msg_first;
 
   while (msg != NULL) {
-#if (__EXCLUSIVE_ACCESS == 0U)
+#if (EXCLUSIVE_ACCESS == 0)
     __disable_irq();
 
     flags = msg->flags;
@@ -812,7 +812,7 @@ osStatus_t isrRtxMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8
 /// Create and Initialize a Message Queue object.
 osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr) {
   EvrRtxMessageQueueNew(msg_count, msg_size, attr);
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxMessageQueueError(NULL, (int32_t)osErrorISR);
     return NULL;
   }
@@ -821,7 +821,7 @@ osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, con
 
 /// Get name of a Message Queue object.
 const char *osMessageQueueGetName (osMessageQueueId_t mq_id) {
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxMessageQueueGetName(mq_id, NULL);
     return NULL;
   }
@@ -831,7 +831,7 @@ const char *osMessageQueueGetName (osMessageQueueId_t mq_id) {
 /// Put a Message into a Queue or timeout if Queue is full.
 osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) {
   EvrRtxMessageQueuePut(mq_id, msg_ptr, msg_prio, timeout);
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     return isrRtxMessageQueuePut(mq_id, msg_ptr, msg_prio, timeout);
   } else {
     return  __svcMessageQueuePut(mq_id, msg_ptr, msg_prio, timeout);
@@ -841,7 +841,7 @@ osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uin
 /// Get a Message from a Queue or timeout if Queue is empty.
 osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) {
   EvrRtxMessageQueueGet(mq_id, msg_ptr, msg_prio, timeout);
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     return isrRtxMessageQueueGet(mq_id, msg_ptr, msg_prio, timeout);
   } else {
     return  __svcMessageQueueGet(mq_id, msg_ptr, msg_prio, timeout);
@@ -850,7 +850,7 @@ osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *
 
 /// Get maximum number of messages in a Message Queue.
 uint32_t osMessageQueueGetCapacity (osMessageQueueId_t mq_id) {
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     return svcRtxMessageQueueGetCapacity(mq_id);
   } else {
     return  __svcMessageQueueGetCapacity(mq_id);
@@ -859,7 +859,7 @@ uint32_t osMessageQueueGetCapacity (osMessageQueueId_t mq_id) {
 
 /// Get maximum message size in a Memory Pool.
 uint32_t osMessageQueueGetMsgSize (osMessageQueueId_t mq_id) {
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     return svcRtxMessageQueueGetMsgSize(mq_id);
   } else {
     return  __svcMessageQueueGetMsgSize(mq_id);
@@ -868,7 +868,7 @@ uint32_t osMessageQueueGetMsgSize (osMessageQueueId_t mq_id) {
 
 /// Get number of queued messages in a Message Queue.
 uint32_t osMessageQueueGetCount (osMessageQueueId_t mq_id) {
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     return svcRtxMessageQueueGetCount(mq_id);
   } else {
     return  __svcMessageQueueGetCount(mq_id);
@@ -877,7 +877,7 @@ uint32_t osMessageQueueGetCount (osMessageQueueId_t mq_id) {
 
 /// Get number of available slots for messages in a Message Queue.
 uint32_t osMessageQueueGetSpace (osMessageQueueId_t mq_id) {
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     return svcRtxMessageQueueGetSpace(mq_id);
   } else {
     return  __svcMessageQueueGetSpace(mq_id);
@@ -887,7 +887,7 @@ uint32_t osMessageQueueGetSpace (osMessageQueueId_t mq_id) {
 /// Reset a Message Queue to initial empty state.
 osStatus_t osMessageQueueReset (osMessageQueueId_t mq_id) {
   EvrRtxMessageQueueReset(mq_id);
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxMessageQueueError(mq_id, (int32_t)osErrorISR);
     return osErrorISR;
   }
@@ -897,7 +897,7 @@ osStatus_t osMessageQueueReset (osMessageQueueId_t mq_id) {
 /// Delete a Message Queue object.
 osStatus_t osMessageQueueDelete (osMessageQueueId_t mq_id) {
   EvrRtxMessageQueueDelete(mq_id);
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxMessageQueueError(mq_id, (int32_t)osErrorISR);
     return osErrorISR;
   }

CMSIS/RTOS2/RTX/Source/rtx_mutex.c

@@ -440,7 +440,7 @@ osStatus_t svcRtxMutexDelete (osMutexId_t mutex_id) {
 /// Create and Initialize a Mutex object.
 osMutexId_t osMutexNew (const osMutexAttr_t *attr) {
   EvrRtxMutexNew(attr);
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxMutexError(NULL, (int32_t)osErrorISR);
     return NULL;
   }
@@ -449,7 +449,7 @@ osMutexId_t osMutexNew (const osMutexAttr_t *attr) {
 
 /// Get name of a Mutex object.
 const char *osMutexGetName (osMutexId_t mutex_id) {
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxMutexGetName(mutex_id, NULL);
     return NULL;
   }
@@ -459,7 +459,7 @@ const char *osMutexGetName (osMutexId_t mutex_id) {
 /// Acquire a Mutex or timeout if it is locked.
 osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) {
   EvrRtxMutexAcquire(mutex_id, timeout);
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxMutexError(mutex_id, (int32_t)osErrorISR);
     return osErrorISR;
   }
@@ -469,7 +469,7 @@ osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) {
 /// Release a Mutex that was acquired by \ref osMutexAcquire.
 osStatus_t osMutexRelease (osMutexId_t mutex_id) {
   EvrRtxMutexRelease(mutex_id);
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxMutexError(mutex_id, (int32_t)osErrorISR);
     return osErrorISR;
   }
@@ -478,7 +478,7 @@ osStatus_t osMutexRelease (osMutexId_t mutex_id) {
 
 /// Get Thread which owns a Mutex object.
 osThreadId_t osMutexGetOwner (osMutexId_t mutex_id) {
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxMutexGetOwner(mutex_id, NULL);
     return NULL;
   }
@@ -488,7 +488,7 @@ osThreadId_t osMutexGetOwner (osMutexId_t mutex_id) {
 /// Delete a Mutex object.
 osStatus_t osMutexDelete (osMutexId_t mutex_id) {
   EvrRtxMutexDelete(mutex_id);
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxMutexError(mutex_id, (int32_t)osErrorISR);
     return osErrorISR;
   }

CMSIS/RTOS2/RTX/Source/rtx_semaphore.c

@@ -32,12 +32,12 @@
 /// \param[in]  semaphore       semaphore object.
 /// \return 1 - success, 0 - failure.
 static uint32_t SemaphoreTokenDecrement (os_semaphore_t *semaphore) {
-#if (__EXCLUSIVE_ACCESS == 0U)
+#if (EXCLUSIVE_ACCESS == 0)
   uint32_t primask = __get_PRIMASK();
 #endif
   uint32_t ret;
 
-#if (__EXCLUSIVE_ACCESS == 0U)
+#if (EXCLUSIVE_ACCESS == 0)
   __disable_irq();
 
   if (semaphore->tokens != 0U) {
@@ -65,12 +65,12 @@ static uint32_t SemaphoreTokenDecrement (os_semaphore_t *semaphore) {
 /// \param[in]  semaphore       semaphore object.
 /// \return 1 - success, 0 - failure.
 static uint32_t SemaphoreTokenIncrement (os_semaphore_t *semaphore) {
-#if (__EXCLUSIVE_ACCESS == 0U)
+#if (EXCLUSIVE_ACCESS == 0)
   uint32_t primask = __get_PRIMASK();
 #endif
   uint32_t ret;
 
-#if (__EXCLUSIVE_ACCESS == 0U)
+#if (EXCLUSIVE_ACCESS == 0)
   __disable_irq();
 
   if (semaphore->tokens < semaphore->max_tokens) {
@@ -428,7 +428,7 @@ osStatus_t isrRtxSemaphoreRelease (osSemaphoreId_t semaphore_id) {
 /// Create and Initialize a Semaphore object.
 osSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr) {
   EvrRtxSemaphoreNew(max_count, initial_count, attr);
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxSemaphoreError(NULL, (int32_t)osErrorISR);
     return NULL;
   }
@@ -437,7 +437,7 @@ osSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, cons
 
 /// Get name of a Semaphore object.
 const char *osSemaphoreGetName (osSemaphoreId_t semaphore_id) {
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxSemaphoreGetName(semaphore_id, NULL);
     return NULL;
   }
@@ -447,7 +447,7 @@ const char *osSemaphoreGetName (osSemaphoreId_t semaphore_id) {
 /// Acquire a Semaphore token or timeout if no tokens are available.
 osStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout) {
   EvrRtxSemaphoreAcquire(semaphore_id, timeout);
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     return isrRtxSemaphoreAcquire(semaphore_id, timeout);
   } else {
     return  __svcSemaphoreAcquire(semaphore_id, timeout);
@@ -457,7 +457,7 @@ osStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout) {
 /// Release a Semaphore token that was acquired by osSemaphoreAcquire.
 osStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id) {
   EvrRtxSemaphoreRelease(semaphore_id);
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     return isrRtxSemaphoreRelease(semaphore_id);
   } else {
     return  __svcSemaphoreRelease(semaphore_id);
@@ -466,7 +466,7 @@ osStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id) {
 
 /// Get current Semaphore token count.
 uint32_t osSemaphoreGetCount (osSemaphoreId_t semaphore_id) {
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     return svcRtxSemaphoreGetCount(semaphore_id);
   } else {
     return  __svcSemaphoreGetCount(semaphore_id);
@@ -476,7 +476,7 @@ uint32_t osSemaphoreGetCount (osSemaphoreId_t semaphore_id) {
 /// Delete a Semaphore object.
 osStatus_t osSemaphoreDelete (osSemaphoreId_t semaphore_id) {
   EvrRtxSemaphoreDelete(semaphore_id);
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxSemaphoreError(semaphore_id, (int32_t)osErrorISR);
     return osErrorISR;
   }

CMSIS/RTOS2/RTX/Source/rtx_system.c

@@ -32,7 +32,7 @@
 /// \param[in]  object          object.
 /// \return 1 - success, 0 - failure.
 static uint32_t isr_queue_put (void *object) {
-#if (__EXCLUSIVE_ACCESS == 0U)
+#if (EXCLUSIVE_ACCESS == 0)
   uint32_t primask = __get_PRIMASK();
 #else
   uint32_t n;
@@ -42,7 +42,7 @@ static uint32_t isr_queue_put (void *object) {
 
   max = osRtxInfo.isr_queue.max;
 
-#if (__EXCLUSIVE_ACCESS == 0U)
+#if (EXCLUSIVE_ACCESS == 0)
   __disable_irq();
 
   if (osRtxInfo.isr_queue.cnt < max) {
@@ -75,7 +75,7 @@ static uint32_t isr_queue_put (void *object) {
 /// Get Object from ISR Queue.
 /// \return object or NULL.
 static void *isr_queue_get (void) {
-#if (__EXCLUSIVE_ACCESS == 0U)
+#if (EXCLUSIVE_ACCESS == 0)
   uint32_t primask = __get_PRIMASK();
 #else
   uint32_t n;
@@ -85,7 +85,7 @@ static void *isr_queue_get (void) {
 
   max = osRtxInfo.isr_queue.max;
 
-#if (__EXCLUSIVE_ACCESS == 0U)
+#if (EXCLUSIVE_ACCESS == 0)
   __disable_irq();
 
   if (osRtxInfo.isr_queue.cnt != 0U) {

CMSIS/RTOS2/RTX/Source/rtx_thread.c

@@ -33,12 +33,12 @@
 /// \param[in]  flags           specifies the flags to set.
 /// \return thread flags after setting.
 static uint32_t ThreadFlagsSet (os_thread_t *thread, uint32_t flags) {
-#if (__EXCLUSIVE_ACCESS == 0U)
+#if (EXCLUSIVE_ACCESS == 0)
   uint32_t primask = __get_PRIMASK();
 #endif
   uint32_t thread_flags;
 
-#if (__EXCLUSIVE_ACCESS == 0U)
+#if (EXCLUSIVE_ACCESS == 0)
   __disable_irq();
 
   thread->thread_flags |= flags;
@@ -59,12 +59,12 @@ static uint32_t ThreadFlagsSet (os_thread_t *thread, uint32_t flags) {
 /// \param[in]  flags           specifies the flags to clear.
 /// \return thread flags before clearing.
 static uint32_t ThreadFlagsClear (os_thread_t *thread, uint32_t flags) {
-#if (__EXCLUSIVE_ACCESS == 0U)
+#if (EXCLUSIVE_ACCESS == 0)
   uint32_t primask = __get_PRIMASK();
 #endif
   uint32_t thread_flags;
 
-#if (__EXCLUSIVE_ACCESS == 0U)
+#if (EXCLUSIVE_ACCESS == 0)
   __disable_irq();
 
   thread_flags = thread->thread_flags;
@@ -86,13 +86,13 @@ static uint32_t ThreadFlagsClear (os_thread_t *thread, uint32_t flags) {
 /// \param[in]  options         specifies flags options (osFlagsXxxx).
 /// \return thread flags before clearing or 0 if specified flags have not been set.
 static uint32_t ThreadFlagsCheck (os_thread_t *thread, uint32_t flags, uint32_t options) {
-#if (__EXCLUSIVE_ACCESS == 0U)
+#if (EXCLUSIVE_ACCESS == 0)
   uint32_t primask;
 #endif
   uint32_t thread_flags;
 
   if ((options & osFlagsNoClear) == 0U) {
-#if (__EXCLUSIVE_ACCESS == 0U)
+#if (EXCLUSIVE_ACCESS == 0)
     primask = __get_PRIMASK();
     __disable_irq();
 
@@ -377,7 +377,7 @@ void osRtxThreadDelayTick (void) {
 /// \param[in]  thread          thread object.
 /// \return pointer to registers R0-R3.
 uint32_t *osRtxThreadRegPtr (os_thread_t *thread) {
-  return ((uint32_t *)(thread->sp + STACK_OFFSET_R0(thread->stack_frame)));
+  return ((uint32_t *)(thread->sp + StackOffsetR0(thread->stack_frame)));
 }
 
 /// Block running Thread execution and register it as Ready to Run.
@@ -425,7 +425,7 @@ void osRtxThreadDispatch (os_thread_t *thread) {
 
   kernel_state   = osRtxKernelGetState();
   thread_running = osRtxThreadGetRunning();
-#if (__ARM_ARCH_7A__ != 0U)
+#if (defined(__ARM_ARCH_7A__) && (__ARM_ARCH_7A__ != 0))
   // On Cortex-A PendSV_Handler is executed before final context switch.
   if ((thread_running != NULL) && (thread_running->state != osRtxThreadRunning)) {
     thread_running = osRtxInfo.thread.run.next;
@@ -578,7 +578,7 @@ osThreadId_t svcRtxThreadNew (osThreadFunc_t func, void *argument, const osThrea
   const char   *name;
   uint32_t     *ptr;
   uint32_t      n;
-#if (__DOMAIN_NS == 1U)
+#if (DOMAIN_NS == 1)
   TZ_ModuleId_t tz_module;
   TZ_MemoryId_t tz_memory;
 #endif
@@ -597,7 +597,7 @@ osThreadId_t svcRtxThreadNew (osThreadFunc_t func, void *argument, const osThrea
     stack_mem  = attr->stack_mem;
     stack_size = attr->stack_size;
     priority   = attr->priority;
-#if (__DOMAIN_NS == 1U)
+#if (DOMAIN_NS == 1)
     tz_module  = attr->tz_module;
 #endif
     if (thread != NULL) {
@@ -632,7 +632,7 @@ osThreadId_t svcRtxThreadNew (osThreadFunc_t func, void *argument, const osThrea
     stack_mem  = NULL;
     stack_size = 0U;
     priority   = osPriorityNormal;
-#if (__DOMAIN_NS == 1U)
+#if (DOMAIN_NS == 1)
     tz_module  = 0U;
 #endif
   }
@@ -688,7 +688,7 @@ osThreadId_t svcRtxThreadNew (osThreadFunc_t func, void *argument, const osThrea
     flags |= osRtxFlagSystemMemory;
   }
 
-#if (__DOMAIN_NS == 1U)
+#if (DOMAIN_NS == 1)
   // Allocate secure process stack
   if (tz_module != 0U) {
     tz_memory = TZ_AllocModuleContext_S(tz_module);
@@ -729,7 +729,7 @@ osThreadId_t svcRtxThreadNew (osThreadFunc_t func, void *argument, const osThrea
   thread->delay         = 0U;
   thread->priority      = (int8_t)priority;
   thread->priority_base = (int8_t)priority;
-  thread->stack_frame   = STACK_FRAME_INIT;
+  thread->stack_frame   = STACK_FRAME_INIT_VAL;
   thread->flags_options = 0U;
   thread->wait_flags    = 0U;
   thread->thread_flags  = 0U;
@@ -738,7 +738,7 @@ osThreadId_t svcRtxThreadNew (osThreadFunc_t func, void *argument, const osThrea
   thread->stack_size    = stack_size;
   thread->sp            = (uint32_t)stack_mem + stack_size - 64U;
   thread->thread_addr   = (uint32_t)func;
-#if (__DOMAIN_NS == 1U)
+#if (DOMAIN_NS == 1)
   thread->tz_memory     = tz_memory;
 #endif
 
@@ -757,7 +757,7 @@ osThreadId_t svcRtxThreadNew (osThreadFunc_t func, void *argument, const osThrea
   }
   *ptr++   = (uint32_t)osThreadExit;    // LR
   *ptr++   = (uint32_t)func;            // PC
-  *ptr++   = xPSR_INIT(
+  *ptr++   = xPSR_InitVal(
               (osRtxConfig.flags & osRtxConfigPrivilegedMode),
               ((uint32_t)func & 1U)
              );                         // xPSR
@@ -1040,7 +1040,7 @@ static void osRtxThreadFree (os_thread_t *thread) {
   // Mark object as inactive
   thread->state = osRtxThreadInactive;
 
-#if (__DOMAIN_NS == 1U)
+#if (DOMAIN_NS == 1)
   // Free secure process stack
   if (thread->tz_memory != 0U) {
     TZ_FreeModuleContext_S(thread->tz_memory);
@@ -1502,7 +1502,7 @@ uint32_t isrRtxThreadFlagsSet (osThreadId_t thread_id, uint32_t flags) {
 /// Create a thread and add it to Active Threads.
 osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) {
   EvrRtxThreadNew(func, argument, attr);
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxThreadError(NULL, (int32_t)osErrorISR);
     return NULL;
   }
@@ -1511,7 +1511,7 @@ osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAtt
 
 /// Get name of a thread.
 const char *osThreadGetName (osThreadId_t thread_id) {
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxThreadGetName(thread_id, NULL);
     return NULL;
   }
@@ -1520,7 +1520,7 @@ const char *osThreadGetName (osThreadId_t thread_id) {
 
 /// Return the thread ID of the current running thread.
 osThreadId_t osThreadGetId (void) {
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxThreadGetId(NULL);
     return NULL;
   }
@@ -1529,7 +1529,7 @@ osThreadId_t osThreadGetId (void) {
 
 /// Get current thread state of a thread.
 osThreadState_t osThreadGetState (osThreadId_t thread_id) {
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxThreadGetState(thread_id, osThreadError);
     return osThreadError;
   }
@@ -1538,7 +1538,7 @@ osThreadState_t osThreadGetState (osThreadId_t thread_id) {
 
 /// Get stack size of a thread.
 uint32_t osThreadGetStackSize (osThreadId_t thread_id) {
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxThreadGetStackSize(thread_id, 0U);
     return 0U;
   }
@@ -1547,7 +1547,7 @@ uint32_t osThreadGetStackSize (osThreadId_t thread_id) {
 
 /// Get available stack space of a thread based on stack watermark recording during execution.
 uint32_t osThreadGetStackSpace (osThreadId_t thread_id) {
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxThreadGetStackSpace(thread_id, 0U);
     return 0U;
   }
@@ -1557,7 +1557,7 @@ uint32_t osThreadGetStackSpace (osThreadId_t thread_id) {
 /// Change priority of a thread.
 osStatus_t osThreadSetPriority (osThreadId_t thread_id, osPriority_t priority) {
   EvrRtxThreadSetPriority(thread_id, priority);
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxThreadError(thread_id, (int32_t)osErrorISR);
     return osErrorISR;
   }
@@ -1566,7 +1566,7 @@ osStatus_t osThreadSetPriority (osThreadId_t thread_id, osPriority_t priority) {
 
 /// Get current priority of a thread.
 osPriority_t osThreadGetPriority (osThreadId_t thread_id) {
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxThreadGetPriority(thread_id, osPriorityError);
     return osPriorityError;
   }
@@ -1576,7 +1576,7 @@ osPriority_t osThreadGetPriority (osThreadId_t thread_id) {
 /// Pass control to next thread that is in state READY.
 osStatus_t osThreadYield (void) {
   EvrRtxThreadYield();
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxThreadError(NULL, (int32_t)osErrorISR);
     return osErrorISR;
   }
@@ -1586,7 +1586,7 @@ osStatus_t osThreadYield (void) {
 /// Suspend execution of a thread.
 osStatus_t osThreadSuspend (osThreadId_t thread_id) {
   EvrRtxThreadSuspend(thread_id);
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxThreadError(thread_id, (int32_t)osErrorISR);
     return osErrorISR;
   }
@@ -1596,7 +1596,7 @@ osStatus_t osThreadSuspend (osThreadId_t thread_id) {
 /// Resume execution of a thread.
 osStatus_t osThreadResume (osThreadId_t thread_id) {
   EvrRtxThreadResume(thread_id);
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxThreadError(thread_id, (int32_t)osErrorISR);
     return osErrorISR;
   }
@@ -1606,7 +1606,7 @@ osStatus_t osThreadResume (osThreadId_t thread_id) {
 /// Detach a thread (thread storage can be reclaimed when thread terminates).
 osStatus_t osThreadDetach (osThreadId_t thread_id) {
   EvrRtxThreadDetach(thread_id);
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxThreadError(thread_id, (int32_t)osErrorISR);
     return osErrorISR;
   }
@@ -1616,7 +1616,7 @@ osStatus_t osThreadDetach (osThreadId_t thread_id) {
 /// Wait for specified thread to terminate.
 osStatus_t osThreadJoin (osThreadId_t thread_id) {
   EvrRtxThreadJoin(thread_id);
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxThreadError(thread_id, (int32_t)osErrorISR);
     return osErrorISR;
   }
@@ -1634,7 +1634,7 @@ __NO_RETURN void osThreadExit (void) {
 /// Terminate execution of a thread.
 osStatus_t osThreadTerminate (osThreadId_t thread_id) {
   EvrRtxThreadTerminate(thread_id);
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxThreadError(thread_id, (int32_t)osErrorISR);
     return osErrorISR;
   }
@@ -1643,7 +1643,7 @@ osStatus_t osThreadTerminate (osThreadId_t thread_id) {
 
 /// Get number of active threads.
 uint32_t osThreadGetCount (void) {
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxThreadGetCount(0U);
     return 0U;
   }
@@ -1652,7 +1652,7 @@ uint32_t osThreadGetCount (void) {
 
 /// Enumerate active threads.
 uint32_t osThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items) {
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxThreadEnumerate(thread_array, array_items, 0U);
     return 0U;
   }
@@ -1662,7 +1662,7 @@ uint32_t osThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items) {
 /// Set the specified Thread Flags of a thread.
 uint32_t osThreadFlagsSet (osThreadId_t thread_id, uint32_t flags) {
   EvrRtxThreadFlagsSet(thread_id, flags);
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     return isrRtxThreadFlagsSet(thread_id, flags);
   } else {
     return  __svcThreadFlagsSet(thread_id, flags);
@@ -1672,7 +1672,7 @@ uint32_t osThreadFlagsSet (osThreadId_t thread_id, uint32_t flags) {
 /// Clear the specified Thread Flags of current running thread.
 uint32_t osThreadFlagsClear (uint32_t flags) {
   EvrRtxThreadFlagsClear(flags);
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxThreadError(NULL, (int32_t)osErrorISR);
     return ((uint32_t)osErrorISR);
   }
@@ -1681,7 +1681,7 @@ uint32_t osThreadFlagsClear (uint32_t flags) {
 
 /// Get the current Thread Flags of current running thread.
 uint32_t osThreadFlagsGet (void) {
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxThreadFlagsGet(0U);
     return 0U;
   }
@@ -1691,7 +1691,7 @@ uint32_t osThreadFlagsGet (void) {
 /// Wait for one or more Thread Flags of the current running thread to become signaled.
 uint32_t osThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout) {
   EvrRtxThreadFlagsWait(flags, options, timeout);
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxThreadError(NULL, (int32_t)osErrorISR);
     return ((uint32_t)osErrorISR);
   }

CMSIS/RTOS2/RTX/Source/rtx_timer.c

@@ -359,7 +359,7 @@ osStatus_t svcRtxTimerDelete (osTimerId_t timer_id) {
 /// Create and Initialize a timer.
 osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr) {
   EvrRtxTimerNew(func, type, argument, attr);
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxTimerError(NULL, (int32_t)osErrorISR);
     return NULL;
   }
@@ -368,7 +368,7 @@ osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument,
 
 /// Get name of a timer.
 const char *osTimerGetName (osTimerId_t timer_id) {
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxTimerGetName(timer_id, NULL);
     return NULL;
   }
@@ -378,7 +378,7 @@ const char *osTimerGetName (osTimerId_t timer_id) {
 /// Start or restart a timer.
 osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks) {
   EvrRtxTimerStart(timer_id, ticks);
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxTimerError(timer_id, (int32_t)osErrorISR);
     return osErrorISR;
   }
@@ -388,7 +388,7 @@ osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks) {
 /// Stop a timer.
 osStatus_t osTimerStop (osTimerId_t timer_id) {
   EvrRtxTimerStop(timer_id);
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxTimerError(timer_id, (int32_t)osErrorISR);
     return osErrorISR;
   }
@@ -397,7 +397,7 @@ osStatus_t osTimerStop (osTimerId_t timer_id) {
 
 /// Check if a timer is running.
 uint32_t osTimerIsRunning (osTimerId_t timer_id) {
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxTimerIsRunning(timer_id, 0U);
     return 0U;
   }
@@ -407,7 +407,7 @@ uint32_t osTimerIsRunning (osTimerId_t timer_id) {
 /// Delete a timer.
 osStatus_t osTimerDelete (osTimerId_t timer_id) {
   EvrRtxTimerDelete(timer_id);
-  if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
+  if (IsIrqMode() || IsIrqMasked()) {
     EvrRtxTimerError(timer_id, (int32_t)osErrorISR);
     return osErrorISR;
   }