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@@ -1,8 +1,8 @@
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/**************************************************************************//**
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* @file core_armv81mml.h
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* @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File
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- * @version V1.0.0
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- * @date 15. March 2019
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+ * @version V1.1.0
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+ * @date 23. July 2019
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******************************************************************************/
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/*
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* Copyright (c) 2018-2019 Arm Limited. All rights reserved.
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@@ -71,11 +71,10 @@
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#define __CORTEX_M (81U) /*!< Cortex-M Core */
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-/** __FPU_USED indicates whether an FPU is used or not.
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- For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
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-*/
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#if defined ( __CC_ARM )
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- #if defined __TARGET_FPU_VFP
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+ #error Legacy Arm Compiler does not support Armv8.1-M target architecture.
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+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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+ #if defined __ARM_FP
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#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
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#define __FPU_USED 1U
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#else
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@@ -97,27 +96,15 @@
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#define __DSP_USED 0U
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#endif
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-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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- #if defined __ARM_FP
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- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
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- #define __FPU_USED 1U
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+ #if defined(__ARM_FEATURE_MVE)
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+ #if defined(__MVE_PRESENT) && (__MVE_PRESENT == 1U)
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+ #define __MVE_USED 1U
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#else
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- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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- #define __FPU_USED 0U
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+ #error "Compiler generates MVE instructions for a devices without MVE extensions (check __MVE_PRESENT)"
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+ #define __MVE_USED 0U
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#endif
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#else
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- #define __FPU_USED 0U
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- #endif
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-
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- #if defined(__ARM_FEATURE_DSP)
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- #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
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- #define __DSP_USED 1U
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- #else
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- #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
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- #define __DSP_USED 0U
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- #endif
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- #else
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- #define __DSP_USED 0U
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+ #define __MVE_USED 0U
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#endif
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#elif defined ( __GNUC__ )
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@@ -142,6 +129,17 @@
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#else
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#define __DSP_USED 0U
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#endif
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+
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+ #if defined(__ARM_FEATURE_MVE)
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+ #if defined(__MVE_PRESENT) && (__MVE_PRESENT == 1U)
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+ #define __MVE_USED 1U
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+ #else
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+ #error "Compiler generates MVE instructions for a devices without MVE extensions (check __MVE_PRESENT)"
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+ #define __MVE_USED 0U
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+ #endif
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+ #else
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+ #define __MVE_USED 0U
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+ #endif
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#elif defined ( __ICCARM__ )
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#if defined __ARMVFP__
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@@ -165,6 +163,17 @@
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#else
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#define __DSP_USED 0U
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#endif
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+
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+ #if defined(__ARM_FEATURE_MVE)
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+ #if defined(__MVE_PRESENT) && (__MVE_PRESENT == 1U)
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+ #define __MVE_USED 1U
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+ #else
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+ #error "Compiler generates MVE instructions for a devices without MVE extensions (check __MVE_PRESENT)"
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+ #define __MVE_USED 0U
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+ #endif
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+ #else
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+ #define __MVE_USED 0U
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+ #endif
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#elif defined ( __TI_ARM__ )
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#if defined __TI_VFP_SUPPORT__
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@@ -249,6 +258,11 @@
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#warning "__DSP_PRESENT not defined in device header file; using default!"
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#endif
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+ #ifndef __MVE_PRESENT
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+ #define __MVE_PRESENT 0U
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+ #warning "__MVE_PRESENT not defined in device header file; using default!"
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+ #endif
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+
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#ifndef __NVIC_PRIO_BITS
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#define __NVIC_PRIO_BITS 3U
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#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
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@@ -1591,8 +1605,8 @@ typedef struct
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#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
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/* MPU Region Base Address Register Definitions */
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-#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
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-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
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+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
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+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
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#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
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#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
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@@ -2143,6 +2157,27 @@ typedef struct
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#define NVIC_USER_IRQ_OFFSET 16
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+/* Special LR values for Secure/Non-Secure call handling and exception handling */
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+
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+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
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+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
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+
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+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
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+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
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+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
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+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
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+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
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+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
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+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
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+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
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+
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+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
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+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
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+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
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+#else
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+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
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+#endif
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+
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/**
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\brief Set Priority Grouping
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@@ -2162,7 +2197,7 @@ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
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reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
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reg_value = (reg_value |
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((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
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- (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
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+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
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SCB->AIRCR = reg_value;
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}
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@@ -2188,7 +2223,9 @@ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
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{
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if ((int32_t)(IRQn) >= 0)
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{
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+ __COMPILER_BARRIER();
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NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
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+ __COMPILER_BARRIER();
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}
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}
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@@ -2537,7 +2574,7 @@ __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
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reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
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reg_value = (reg_value |
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((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
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- (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
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+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
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SCB_NS->AIRCR = reg_value;
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}
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Jonatan Antoni