Bump version and docs for release.

Change-Id: I185d5c5599ee1e2141518ca86628ae7fb812db7a

ARM.CMSIS.pdsc

@@ -8,7 +8,7 @@
   <url>http://www.keil.com/pack/</url>
 
   <releases>
-    <release version="5.7.0-rc2">
+    <release version="5.7.0" date="2020-04-09">
       CMSIS-Build: 0.9.0 (beta)
         - Draft for CMSIS Project description (CPRJ)
       CMSIS-Core(M): 5.4.0 (see revision history for details)

docs/Build/html/CmdLineBuild.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Build
-   &#160;<span id="projectnumber">Version 0.1.0</span>
+   &#160;<span id="projectnumber">Version 0.9.0 (beta)</span>
    </div>
    <div id="projectbrief">Tools, software frameworks, and work flows for productivity with CMSIS based projects</div>
   </td>
@@ -110,8 +110,8 @@ $(document).ready(function(){initNavTree('CmdLineBuild.html','');});
 <div class="title">Command Line Build </div>  </div>
 </div><!--header-->
 <div class="contents">
-<div class="textblock"><p>The following scripts and tools enable command line build with projects that include software components in CMSIS-Pack format:</p>
-<p>For command line build with software packs, the following tools are provided.</p>
+<div class="textblock"><p>The following bash scripts and command line tools can be used for managing the build of CMSIS Projects from the command line. These scripts can be easily adopted to specific environments and are intended as a minimal reference. CMSIS-Build tools are available for download as an asset of the respective <a href="https://github.com/ARM-software/CMSIS_5/releases/" target="_blank"><b>CMSIS Release Version</b></a> (starting 5.7.0 e/o April 2020).</p>
+<p>For command line build with software packs, the following tools and utilities are provided.</p>
 <table class="doxtable">
 <tr>
 <th align="left">Tool / Script </th><th align="left">Description  </th></tr>
@@ -142,40 +142,37 @@ $(document).ready(function(){initNavTree('CmdLineBuild.html','');});
 </div><!-- fragment --><p>Start the build process for a existing project file: </p>
 <div class="fragment"><div class="line">$ cbuild.sh MyProject.cprj</div>
 </div><!-- fragment --><p>Below is the output that shows a successful build:</p>
-<dl class="todo"><dt><b><a class="el" href="todo.html#_todo000002">Todo:</a></b></dt><dd>update below for final release</dd></dl>
-<pre class="fragment">(cbuild.sh): Build Invocation 0.1.0 (C) 2020 ARM
+<pre class="fragment">(cbuild.sh): Build Invocation 0.9.0 (C) 2020 ARM
 MyProject.cprj validates
-CMSIS Build (cbuildgen) 0.1.1 (Feb 14 2020, 15:03:45)
-Copyright (C) 2020 ARM Ltd and ARM Germany GmbH. All rights reserved.
+(cbuildgen): Build Process Manager 0.9.0 (C) 2020
 M654: URL 'https://www.keil.com/pack/ARM.CMSIS.5.6.0.pack' was added to the list of missing packages.
-M650: Setup run successfully.
-(cp_install.sh): Install Packs 0.1.0 (C) 2020 ARM
+M650: Command completed successfully.
+(cp_install.sh): Install Packs 0.9.0 (C) 2020 ARM
 info: reading file: MyProject.cp_install
 dos2unix: converting file MyProject.cp_install to Unix format...
 https://www.keil.com/pack/ARM.CMSIS.5.6.0.pack
-######################################################################## 100.0%#=#=#
-info: ARM.CMSIS.5.6.0.pack installing into /c/project/MyPackRepo/ARM/CMSIS/5.6.0
+######################################################################## 100.0%
+info: ARM.CMSIS.5.6.0.pack installing into /c/Projects/Packs/ARM/CMSIS/5.6.0
 pack installation completed successfully
-CMSIS Build (cbuildgen) 0.1.1 (Feb 14 2020, 15:03:45)
-Copyright (C) 2020 ARM Ltd and ARM Germany GmbH. All rights reserved.
+(cbuildgen): Build Process Manager 0.9.0 (C) 2020 ARM
 M653: Local config file RTE/Device/ARMCM0/ARMCM0_ac6.sct was not found. Copying default file from package.
 M653: Local config file RTE/Device/ARMCM0/startup_ARMCM0.c was not found. Copying default file from package.
 M653: Local config file RTE/Device/ARMCM0/system_ARMCM0.c was not found. Copying default file from package.
 M651: Generated makefile for merging config files: 'MyProject_cfg.mak'
 M652: Generated makefile for project building:'MyProject.mak'
-mkdir -p "Objects/RTE/Device/Startup/C Startup"
-mkdir -p "Objects/Source"
-"/C/Keil_v5/ARM/ARMCLANG/bin/armclang"  @"Objects/Source/MyMain.o._cc"
-"/C/Keil_v5/ARM/ARMCLANG/bin/armclang"  @"Objects/RTE/Device/Startup/C Startup/startup_ARMCM0.o._cc"
-"/C/Keil_v5/ARM/ARMCLANG/bin/armclang"  @"Objects/RTE/Device/Startup/C Startup/system_ARMCM0.o._cc"
-"/C/Keil_v5/ARM/ARMCLANG/bin/armlink" --via="Objects/MyBinary.axf._ld"
+mkdir -p "/c/Projects/MyProject/Objects/RTE/Device/Startup/C Startup"
+mkdir -p "/c/Projects/MyProject/Objects/Source"
+"/C/Keil_v5/ARM/ARMCLANG/bin/armclang"  @"/c/Projects/MyProject/Objects/Source/MyMain.o._cc"
+"/C/Keil_v5/ARM/ARMCLANG/bin/armclang"  @"/c/Projects/MyProject/Objects/RTE/Device/Startup/C Startup/startup_ARMCM0.o._cc"
+"/C/Keil_v5/ARM/ARMCLANG/bin/armclang"  @"/c/Projects/MyProject/Objects/RTE/Device/Startup/C Startup/system_ARMCM0.o._cc"
+"/C/Keil_v5/ARM/ARMCLANG/bin/armlink" --via="/c/Projects/MyProject/Objects/MyBinary.axf._ld"
 cbuild.sh finished successfully!
 </pre> </div></div><!-- contents -->
 </div><!-- doc-content -->
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Feb 26 2020 09:42:01 for CMSIS-Build Version 0.1.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:55 for CMSIS-Build Version 0.9.0 (beta) by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Build/html/Make.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Build
-   &#160;<span id="projectnumber">Version 0.1.0</span>
+   &#160;<span id="projectnumber">Version 0.9.0 (beta)</span>
    </div>
    <div id="projectbrief">Tools, software frameworks, and work flows for productivity with CMSIS based projects</div>
   </td>
@@ -144,7 +144,7 @@ Usage Example</h1>
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
     <li class="navelem"><a class="el" href="CmdLineBuild.html">Command Line Build</a></li>
-    <li class="footer">Generated on Wed Feb 26 2020 09:42:01 for CMSIS-Build Version 0.1.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:55 for CMSIS-Build Version 0.9.0 (beta) by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Build/html/build_revisionHistory.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Build
-   &#160;<span id="projectnumber">Version 0.1.0</span>
+   &#160;<span id="projectnumber">Version 0.9.0 (beta)</span>
    </div>
    <div id="projectbrief">Tools, software frameworks, and work flows for productivity with CMSIS based projects</div>
   </td>
@@ -114,14 +114,21 @@ $(document).ready(function(){initNavTree('build_revisionHistory.html','');});
 <tr>
 <th>Version </th><th>Description  </th></tr>
 <tr>
-<td>0.10 </td><td>Release for beta review  </td></tr>
+<td>0.9.0 (beta) </td><td>Release for beta review:<ul>
+<li>added layer description to project format specification.</li>
+<li>added support for multiple compilers.</li>
+<li>added commands for layer operations to cbuildgen.   </li>
+</ul>
+</td></tr>
+<tr>
+<td>0.1.0 </td><td>Release for alpha review  </td></tr>
 </table>
 </div></div><!-- contents -->
 </div><!-- doc-content -->
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Feb 26 2020 09:42:01 for CMSIS-Build Version 0.1.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:55 for CMSIS-Build Version 0.9.0 (beta) by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Build/html/cbuild.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Build
-   &#160;<span id="projectnumber">Version 0.1.0</span>
+   &#160;<span id="projectnumber">Version 0.9.0 (beta)</span>
    </div>
    <div id="projectbrief">Tools, software frameworks, and work flows for productivity with CMSIS based projects</div>
   </td>
@@ -122,7 +122,7 @@ $(document).ready(function(){initNavTree('cbuild.html','');});
 <p>The <a class="el" href="cbuild.html">cbuild.sh: Build Invocation</a> script implements the build flow by chaining the utilities <a class="el" href="cbuildgen.html">cbuildgen</a>, <a class="el" href="ccmerge.html">ccmerge</a>, and <b>Make</b>. It replicates the build steps of CMSIS-Pack aware IDEs and also updates configuration files if necessary. The script can be adopted to project specific requirements.</p>
 <p>The build flow of the <a class="el" href="cbuild.html">cbuild.sh: Build Invocation</a> script is:</p>
 <ol type="1">
-<li>Call <a class="el" href="cbuildgen.html">cbuildgen: Build Process Manager</a> with command <b>pack</b> to list the URLs of missing software packs.</li>
+<li>Call <a class="el" href="cbuildgen.html">cbuildgen: Build Process Manager</a> with command <b>packlist</b> to list the URLs of missing software packs.</li>
 <li>Call <a class="el" href="cp_install.html">cp_install.sh: Install Packs</a> to download and install missing software packs.</li>
 <li>Call <a class="el" href="cbuildgen.html">cbuildgen: Build Process Manager</a> with command <b>make</b> to generate Make files.</li>
 <li>Call <a class="el" href="Make.html">make: GNU Make</a> to update configuration files using <a class="el" href="ccmerge.html">ccmerge: Config File Updater</a>.</li>
@@ -131,26 +131,24 @@ $(document).ready(function(){initNavTree('cbuild.html','');});
 <h1><a class="anchor" id="cbuild_example"></a>
 Usage Example</h1>
 <pre class="fragment">$ cbuild.sh Simulation.cprj
-(cbuild.sh): Build Invocation 0.1.0 (C) 2020 ARM
+(cbuild.sh): Build Invocation 0.9.0 (C) 2020 ARM
 Simulation.cprj validates
-CMSIS Build (cbuildgen) 0.1.1 (Feb 14 2020, 15:03:45)
-Copyright (C) 2020 ARM Ltd and ARM Germany GmbH. All rights reserved.
+(cbuildgen): Build Process Manager 0.9.0 (C) 2020 ARM
 M650: Config command completed successfully.
-CMSIS Build (cbuildgen) 0.1.1 (Feb 14 2020, 15:03:45)
-Copyright (C) 2020 ARM Ltd and ARM Germany GmbH. All rights reserved.
+(cbuildgen): Build Process Manager 0.9.0 (C) 2020 ARM
 M651: Generated makefile for merging config files: 'Simulation_cfg.mak'
 M652: Generated makefile for project build:'Simulation.mak'
-mkdir -p "C:/Examples/Blinky/Objects/RTE/CMSIS/RTOS2/Keil RTX5/Library"
-mkdir -p "C:/Examples/Blinky/Objects/RTE/Compiler/IO/STDOUT/ITM"
-mkdir -p "C:/Examples/Blinky/Objects/RTE/Device/Startup/C Startup"
-mkdir -p "C:/Examples/Blinky/Objects/Source Files"
-"/C/Keil_v5/ARM/ARMCLANG/bin/armclang" @"C:/Examples/Blinky/Objects/RTE/CMSIS/RTOS2/Keil RTX5/Library/RTX_Config.o._cc"
-"/C/Keil_v5/ARM/ARMCLANG/bin/armclang" @"C:/Examples/Blinky/Objects/RTE/CMSIS/RTOS2/Keil RTX5/Library/rtx_lib.o._cc"
-"/C/Keil_v5/ARM/ARMCLANG/bin/armclang" @"C:/Examples/Blinky/Objects/RTE/Compiler/IO/STDOUT/ITM/retarget_io.o._cc"
-"/C/Keil_v5/ARM/ARMCLANG/bin/armclang" @"C:/Examples/Blinky/Objects/RTE/Device/Startup/C Startup/startup_ARMCM3.o._cc"
-"/C/Keil_v5/ARM/ARMCLANG/bin/armclang" @"C:/Examples/Blinky/Objects/RTE/Device/Startup/C Startup/system_ARMCM3.o._cc"
-"/C/Keil_v5/ARM/ARMCLANG/bin/armclang" @"C:/Examples/Blinky/Objects/Source Files/Blinky.o._cc"
-"/C/Keil_v5/ARM/ARMCLANG/bin/armlink" --via="C:/Examples/Blinky/Objects/Blinky.axf._ld"
+mkdir -p "/c/Examples/Blinky/Objects/RTE/CMSIS/RTOS2/Keil RTX5/Library"
+mkdir -p "/c/Examples/Blinky/Objects/RTE/Compiler/IO/STDOUT/ITM"
+mkdir -p "/c/Examples/Blinky/Objects/RTE/Device/Startup/C Startup"
+mkdir -p "/c/Examples/Blinky/Objects/Source Files"
+"/C/Keil_v5/ARM/ARMCLANG/bin/armclang" @"/c/Examples/Blinky/Objects/RTE/CMSIS/RTOS2/Keil RTX5/Library/RTX_Config.o._cc"
+"/C/Keil_v5/ARM/ARMCLANG/bin/armclang" @"/c/Examples/Blinky/Objects/RTE/CMSIS/RTOS2/Keil RTX5/Library/rtx_lib.o._cc"
+"/C/Keil_v5/ARM/ARMCLANG/bin/armclang" @"/c/Examples/Blinky/Objects/RTE/Compiler/IO/STDOUT/ITM/retarget_io.o._cc"
+"/C/Keil_v5/ARM/ARMCLANG/bin/armclang" @"/c/Examples/Blinky/Objects/RTE/Device/Startup/C Startup/startup_ARMCM3.o._cc"
+"/C/Keil_v5/ARM/ARMCLANG/bin/armclang" @"/c/Examples/Blinky/Objects/RTE/Device/Startup/C Startup/system_ARMCM3.o._cc"
+"/C/Keil_v5/ARM/ARMCLANG/bin/armclang" @"/c/Examples/Blinky/Objects/Source Files/Blinky.o._cc"
+"/C/Keil_v5/ARM/ARMCLANG/bin/armlink" --via="/c/Examples/Blinky/Objects/Blinky.axf._ld"
 Program Size: Code=7516 RO-data=1264 RW-data=168 ZI-data=9084
 cbuild.sh finished successfully!
 </pre><h1><a class="anchor" id="cbuild_errors"></a>
@@ -175,7 +173,7 @@ Error Messages</h1>
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
     <li class="navelem"><a class="el" href="CmdLineBuild.html">Command Line Build</a></li>
-    <li class="footer">Generated on Wed Feb 26 2020 09:42:01 for CMSIS-Build Version 0.1.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:55 for CMSIS-Build Version 0.9.0 (beta) by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Build/html/cbuild_install.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Build
-   &#160;<span id="projectnumber">Version 0.1.0</span>
+   &#160;<span id="projectnumber">Version 0.9.0 (beta)</span>
    </div>
    <div id="projectbrief">Tools, software frameworks, and work flows for productivity with CMSIS based projects</div>
   </td>
@@ -122,7 +122,7 @@ $(document).ready(function(){initNavTree('cbuild_install.html','');});
 </ul>
 <h1><a class="anchor" id="cbuild_install2"></a>
 cbuild_install.sh: Install Build Tools</h1>
-<dl class="todo"><dt><b><a class="el" href="todo.html#_todo000003">Todo:</a></b></dt><dd>Where to find cbuild_install.sh: CMSIS build tools</dd></dl>
+<p>CMSIS-Build tools are available for download as an asset of the respective <a href="https://github.com/ARM-software/CMSIS_5/releases/" target="_blank"><b>CMSIS Release Version</b></a> (starting 5.7.0 e/o April 2020).</p>
 <p>To install the command line build environment start from the Bash prompt: </p>
 <div class="fragment"><div class="line">$ ./cbuild_install.sh</div>
 </div><!-- fragment --><p>This install script queries for:</p>
@@ -152,13 +152,12 @@ Environment Variables</h1>
 <tr>
 <td align="left"><code>$CMSIS_BUILD_ROOT</code> </td><td align="left">Base directory of the CMSIS command line build tools. </td></tr>
 <tr>
-<td align="left"><code>$MDK_ROOT</code> </td><td align="left">Base directory of the MDK installation. </td></tr>
+<td align="left"><code>$MDK_ROOT</code> </td><td align="left">Base directory of the MDK installation (optional). </td></tr>
 </table>
 <h1><a class="anchor" id="cbuild_compiler_config"></a>
 Compiler Configuration</h1>
-<p>The CMSIS <a class="el" href="cbuildgen.html">cbuildgen: Build Process Manager</a> uses toolchain specific <b>.mak files</b> that map the CMSIS project settings to the toolchain. For each supported toolchain a <b>.mak files</b> is provided in the directory <b>./cbuild/etc</b> and specifies the root directory of the toolchain (TOOLCHAIN_ROOT) The user should update the this setting to reflect the actual installation.</p>
+<p>The CMSIS <a class="el" href="cbuildgen.html">cbuildgen: Build Process Manager</a> uses toolchain specific <b>.mak files</b> that map the CMSIS project settings to the toolchain. For each supported toolchain a <b>.mak files</b> is provided in the directory <b>./cbuild/etc</b> and specifies the base directory of the toolchain installation (TOOLCHAIN_ROOT). In addition other toolchain specific environment variables may be setup here (e.g. license file and product variant). The user is required to update the these settings after installation to reflect the actual installation.</p>
 <p><b>Example file: ./cbuild/etc/ARMCC.6.13.1.mak</b></p>
-<dl class="todo"><dt><b><a class="el" href="todo.html#_todo000004">Todo:</a></b></dt><dd>Joachim: verify licensing</dd></dl>
 <div class="fragment"><div class="line"><span class="preprocessor"># Version: 1.0.0</span></div>
 <div class="line"><span class="preprocessor"></span><span class="preprocessor"># Date: 2020-02-11</span></div>
 <div class="line"><span class="preprocessor"></span><span class="preprocessor"># This file maps the CMSIS project options to toolchain settings.</span></div>
@@ -198,7 +197,7 @@ When <b>xmllint</b> is not installed, the XML schema verification is skipped by
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
     <li class="navelem"><a class="el" href="CmdLineBuild.html">Command Line Build</a></li>
-    <li class="footer">Generated on Wed Feb 26 2020 09:42:01 for CMSIS-Build Version 0.1.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:55 for CMSIS-Build Version 0.9.0 (beta) by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Build/html/cbuild_uv.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Build
-   &#160;<span id="projectnumber">Version 0.1.0</span>
+   &#160;<span id="projectnumber">Version 0.9.0 (beta)</span>
    </div>
    <div id="projectbrief">Tools, software frameworks, and work flows for productivity with CMSIS based projects</div>
   </td>
@@ -120,27 +120,27 @@ $(document).ready(function(){initNavTree('cbuild_uv.html','');});
 Some MDK features are not converted as not all build features of µVision are available in command line build process. For example:<ul>
 <li>User commands pre and post build</li>
 <li><code>fcarm</code> code generator</li>
-<li>Linker script generation</li>
+<li>Linker script generation. Instead the linker script generated by MDK is used by cmsis build.</li>
 </ul>
 </dd></dl>
 <h1><a class="anchor" id="cbuild_uv_example"></a>
 Usage Example</h1>
 <pre class="fragment">$ cbuild_uv.sh FTP_Server.uvprojx
-(cbuild_uv.sh): Build MDK Project 0.1.0 (C) 2020 ARM
+(cbuild_uv.sh): Build MDK Project 0.9.0 (C) 2020 ARM
 uVision has created CPRJ files for the following targets:
-Debug.cprj
-Release.cprj
+FTP_Server.Debug.cprj
+FTP_Server.Release.cprj
  --------------------------------------------------------------------
- calling cbuild.sh for Debug.cprj
+ calling cbuild.sh for FTP_Server.Debug.cprj
  --------------------------------------------------------------------
  ...
  --------------------------------------------------------------------
- calling cbuild.sh for Release.cprj
+ calling cbuild.sh for FTP_Server.Release.cprj
  --------------------------------------------------------------------
  ...
 builds completed for:
-Debug.cprj
-Release.cprj
+FTP_Server.Debug.cprj
+FTP_Server.Release.cprj
 total: 2 failed: 0
 </pre> </div></div><!-- contents -->
 </div><!-- doc-content -->
@@ -148,7 +148,7 @@ total: 2 failed: 0
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
     <li class="navelem"><a class="el" href="CmdLineBuild.html">Command Line Build</a></li>
-    <li class="footer">Generated on Wed Feb 26 2020 09:42:01 for CMSIS-Build Version 0.1.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:55 for CMSIS-Build Version 0.9.0 (beta) by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Build/html/cbuildgen.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Build
-   &#160;<span id="projectnumber">Version 0.1.0</span>
+   &#160;<span id="projectnumber">Version 0.9.0 (beta)</span>
    </div>
    <div id="projectbrief">Tools, software frameworks, and work flows for productivity with CMSIS based projects</div>
   </td>
@@ -111,35 +111,43 @@ $(document).ready(function(){initNavTree('cbuildgen.html','');});
 </div><!--header-->
 <div class="contents">
 <div class="textblock"><p>The <a class="el" href="cbuildgen.html">cbuildgen</a> is the core tool for the build process. It is called from the <b>Bash</b> command line with the following syntax:</p>
-<dl class="todo"><dt><b><a class="el" href="todo.html#_todo000005">Todo:</a></b></dt><dd>is a default extension assumed?<ul>
-<li>[danbro01] The .cprj extension has to be explicitly present in the &lt;<code>ProjectFile&gt;</code>.cprj argument.</li>
-</ul>
-</dd></dl>
 <div class="fragment"><div class="line">cbuildgen &lt;command&gt; &lt;ProjectFile&gt;.cprj [options]</div>
 </div><!-- fragment --><p><b>Where:</b></p>
 <p><code>cbuildgen</code> is the name of tool.</p>
-<p>&lt;<code>command&gt;</code> specifies the operation of <code>cbuildgen</code> (see table below).</p>
-<p>&lt;<code>ProjectFile&gt;</code> is the name of the project file.</p>
-<p>[<code>options</code>] are optional parameters that control the operation (see table below).</p>
+<p>&lt;<code>command&gt;</code> specifies the operation of <code>cbuildgen</code> (see table below). Only one command is permitted per invocation.</p>
+<p>&lt;<code>ProjectFile&gt;</code> is the name of the project file. The file extension (.cprj) is mandatory.</p>
+<p>[<code>options</code>] are additional parameters that control the operation (see table below). Note: available options are specific for each command.</p>
 <p><b>Commands</b> </p>
 <table  class="cmtable" summary="cbuildgen commands">
 <tr>
-<th style="min-width:100px">&lt;command&gt; </th><th style="min-width:175px">Description </th><th style="min-width:175px">Details  </th></tr>
+<th style="min-width:100px">&lt;command&gt; </th><th style="min-width:185px">Description </th><th style="min-width:175px">Details  </th></tr>
+<tr>
+<td>packlist </td><td>List missing packs </td><td>Check the current list of installed packs in the directory <code>$CMSIS_PACK_ROOT</code>. The URLs of missing packs are written to &lt;ProjectFile&gt;.cp_install file.  </td></tr>
+<tr>
+<td>make </td><td>Generate makefile(s) </td><td>Generates &lt;ProjectFile&gt;.mak for <a class="el" href="Make.html">Make</a> required to build the project. When used with option &ndash;merge it generates also &lt;ProjectFile&gt;_cfg.mak for <a class="el" href="Make.html">Make</a> to update configuration files. This command also generates a ASCII log file &lt;ProjectFile&gt;.clog recording location and version of the selected toolchain, packs, components and config files. The option &ndash;output specifies the destination folder of the generated files. The location of the &lt;ProjectFile&gt;.cprj is used if &ndash;output is not specified.   </td></tr>
+<tr>
+<td>extract </td><td>Extract layer from project </td><td>Creates a sub directory named <code></code>./Layer/&lt;layername&gt;/ for each layer described in &lt;ProjectFile&gt;.cprj. These folders contain a layer description file &lt;layername&gt;.clayer and the project and configuration files belonging to the layer. The option &ndash;layer=&lt;layname&gt; selects a specific layer by name. This option can be specified multiple times to select multiple layers.   </td></tr>
 <tr>
-<td>packlist </td><td>List missing packs </td><td>Check the current list of installed packs in the directory <code>$CMSIS_PACK_ROOT</code>. Download URLs of missing packs are written to &lt;ProjectFile&gt;.cp_install file.  </td></tr>
+<td>remove </td><td>Remove layer from project </td><td>Updates the &lt;ProjectFile&gt;.cprj removing the layer description as well as all associated files and components for the layers specified at the command line. The command deletes the associated files from the respecctive project directory. The option &ndash;layer=&lt;layname&gt; selects a specific layer by name and is mandatory. This option can be specified multiple times to remove multiple layers.   </td></tr>
 <tr>
-<td>make </td><td>Generate makefile(s) </td><td>Generates &lt;ProjectFile&gt;.mak for <a class="el" href="Make.html">Make</a> to build the binary image. When used with &ndash;merge it generates also &lt;ProjectFile&gt;_cfg.mak for <a class="el" href="Make.html">Make</a> to update configuration files.  </td></tr>
+<td>compose </td><td>Create new project </td><td>Create new &lt;ProjectFile&gt;.cprj from layer files ([...]&lt;layername&gt;.clayer) as well as copying associated files. One or more clayer files are required.   </td></tr>
+<tr>
+<td>add </td><td>Add layer to project </td><td>Updates the &lt;ProjectFile&gt;.cprj adding the layer description as well as all associated files and components for the clayer files specified at the command line. The command copies the associated files from the layer directory into the project directory. One or more clayer files are required.   </td></tr>
 </table>
 <p><b>Options</b> </p>
 <table  class="cmtable" summary="cbuildgen options">
 <tr>
 <th style="min-width:100px">[option] </th><th style="min-width:175px">Description </th><th style="min-width:175px">Details  </th></tr>
 <tr>
-<td>--merge </td><td>Update configuration files </td><td>When used with the command <code>make</code>, it generates also &lt;ProjectFile&gt;_cfg.mak for <a class="el" href="Make.html">Make</a> to update configuration files using <a class="el" href="ccmerge.html">ccmerge: Config File Updater</a>.   </td></tr>
+<td>--merge </td><td>Update configuration files </td><td>When used with the command <code>make</code>, it generates also &lt;ProjectFile&gt;_cfg.mak for <a class="el" href="Make.html">Make</a> to update configuration files using <a class="el" href="ccmerge.html">ccmerge: Config File Updater</a> (used by command: make).   </td></tr>
+<tr>
+<td>--toolchain=&lt;compiler&gt; </td><td>Specify toolchain </td><td>For projects that can be build with multiple toolchains, it defines the toolchain for the build (used by command: make).  </td></tr>
 <tr>
-<td>--toolchain=&lt;compiler&gt; </td><td>Specify toolchain </td><td>For projects that can be build with multiple toolchains, it defines the toolchain for <a class="el" href="Make.html">Make</a>.  </td></tr>
+<td>--output=&lt;directory&gt; </td><td>Specify output directory </td><td>Specifies the directory for the generated files <b>*.mak</b> files and the base directory for intermediate output from build. (used by command: make).  </td></tr>
 <tr>
-<td>--output=&lt;directory&gt; </td><td>Specify output directory </td><td>Specifies the directory where the <b>*.mak</b> files are generated.  </td></tr>
+<td>--layer=&lt;layername&gt; </td><td>Specify layer name </td><td>Specifies the name of the layer (used by commands: remove and extract).  </td></tr>
+<tr>
+<td>&lt;directory&gt;/&lt;layername&gt;.clayer </td><td>Specify layer file </td><td>Specifies the directory and filename of the project layer (used by commands: add and compose). </td></tr>
 </table>
 <p>The <a class="el" href="cbuildgen.html">cbuildgen: Build Process Manager</a> uses information from the CMSIS project file *.cprj, software packs, and environment variables.</p>
 <ul>
@@ -154,22 +162,18 @@ $(document).ready(function(){initNavTree('cbuildgen.html','');});
 <li>include ${CMSIS_BUILD_ROOT}/etc/Whitespace.mak for handling of white space characters in filenames.</li>
 <li>include ${CMSIS_COMPILER_ROOT}/&lt;name&gt;.&lt;version&gt;.mak that specifies default options for the toolchain.</li>
 </ul>
-<dl class="todo"><dt><b><a class="el" href="todo.html#_todo000006">Todo:</a></b></dt><dd>Question to Daniel: does cbuildgen update the *.cprj file or is that file read-only? How are new configuration files detected?<ul>
-<li>[danbro01] The *.cprj file is never written by cbuildgen. The merge tool overwrites the outdated configuration files with new merged data.</li>
-</ul>
-</dd></dl>
+<p>Note: cbuildgen does not update the *.cprj for commands packlist, make and extract. The merge tool updates the outdated configuration files with new merged data, keeping a copy of the original file.</p>
 <h1><a class="anchor" id="cbuild_example"></a>
 Usage Example</h1>
 <pre class="fragment">$ cbuildgen packlist Simulation.cprj
-CMSIS Build (cbuildgen) 0.1.1 (Feb 14 2020, 15:03:45)
-Copyright (C) 2020 ARM Ltd and ARM Germany GmbH. All rights reserved.
+(cbuildgen): Build Process Manager 0.9.0 (C) 2020 ARM
 M654: URL 'http://www.keil.com/pack/ARM.CMSIS.5.6.0.pack' was added to the list of missing packages.
 M654: URL 'http://www.keil.com/pack/Keil.ARM_Compiler.1.6.1.pack' was added to the list of missing packages.
-M650: Config command completed successfully.
+M650: Command completed successfully.
 
 $ cbuildgen make Simulation.cprj
-CMSIS Build (cbuildgen) 0.1.1 (Feb 14 2020, 15:03:45)
-Copyright (C) 2020 ARM Ltd and ARM Germany GmbH. All rights reserved.
+(cbuildgen): Build Process Manager 0.9.0 (C) 2020 ARM
+M651: Generated makefile for merging config files: 'Simulation_cfg.mak'
 M652: Generated makefile for project build:'Simulation.mak'
 </pre><h1><a class="anchor" id="cbuildgen_errors"></a>
 Error Messages</h1>
@@ -247,7 +251,7 @@ Error Messages</h1>
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
     <li class="navelem"><a class="el" href="CmdLineBuild.html">Command Line Build</a></li>
-    <li class="footer">Generated on Wed Feb 26 2020 09:42:01 for CMSIS-Build Version 0.1.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:55 for CMSIS-Build Version 0.9.0 (beta) by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Build/html/ccmerge.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Build
-   &#160;<span id="projectnumber">Version 0.1.0</span>
+   &#160;<span id="projectnumber">Version 0.9.0 (beta)</span>
    </div>
    <div id="projectbrief">Tools, software frameworks, and work flows for productivity with CMSIS based projects</div>
   </td>
@@ -110,7 +110,8 @@ $(document).ready(function(){initNavTree('ccmerge.html','');});
 <div class="title">ccmerge: Config File Updater </div>  </div>
 </div><!--header-->
 <div class="contents">
-<div class="textblock"><p>The <a class="el" href="ccmerge.html">ccmerge</a> tool supports the update process for configuration files that use <a href="../../Pack/html/configWizard.html"><b>Configuration Wizard Annotations</b></a>. It is called from the <b>Bash</b> command line with the following syntax:</p>
+<div class="textblock"><p>The <a class="el" href="ccmerge.html">ccmerge</a> tool supports the update process for configuration files that use <a href="../../Pack/html/configWizard.html"><b>Configuration Wizard Annotations</b></a>. The tool takes the configuration file located in the CMSIS Pack (pfile) and merges the configuration information extracted from the configuration file located in the current project (cfile). If the merge succeeds the result is written to 'cfile' after a copy of 'cfile' has been stored as 'cfile.nnnn'.</p>
+<p>It is called from the <b>Bash</b> command line with the following syntax:</p>
 <p><b>ccmerge</b> has the following command invocation:</p>
 <div class="fragment"><div class="line">ccmerge -pfile &lt;name_of_pack_cfgfile&gt; -cfile &lt;name_of_current_cfgfile&gt; [-merge] [-details]</div>
 </div><!-- fragment --><p><a class="el" href="ccmerge.html">ccmerge</a> helps to update the setup of software components as it merges options from a previous configuration file version to a new version.</p>
@@ -131,10 +132,6 @@ $(document).ready(function(){initNavTree('ccmerge.html','');});
 <dl class="section note"><dt>Note</dt><dd>A filepath name can be specified without surrounding " characters as long as it does not contain any space or other special characters. It must be enclosed by " characters when the filepath name contains one or more spaces or other special characters.</dd></dl>
 <h1><a class="anchor" id="ccmerge_examples"></a>
 Usage Example</h1>
-<dl class="todo"><dt><b><a class="el" href="todo.html#_todo000007">Todo:</a></b></dt><dd>for me the complete operation of ccmerge is unclear. Does it actually copy files?<ul>
-<li>[danbro01] As described above, when a merge succeeds the current 'cfile' is saved as 'cfile.nnnn' and 'cfile' is overwritten.</li>
-</ul>
-</dd></dl>
 <div class="fragment"><div class="line">ccmerge -pfile $CMSIS_PACK_ROOT/ARM/CMSIS/5.6.0/CMSIS/RTOS2/RTX/Config/RTX_Config.h -cfile RTE/CMSIS/RTX_Config.h -merge</div>
 </div><!-- fragment --><h1><a class="anchor" id="ccmerge_errors"></a>
 Error Messages</h1>
@@ -180,7 +177,7 @@ Error Messages</h1>
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
     <li class="navelem"><a class="el" href="CmdLineBuild.html">Command Line Build</a></li>
-    <li class="footer">Generated on Wed Feb 26 2020 09:42:01 for CMSIS-Build Version 0.1.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:55 for CMSIS-Build Version 0.9.0 (beta) by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Build/html/cp_init.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Build
-   &#160;<span id="projectnumber">Version 0.1.0</span>
+   &#160;<span id="projectnumber">Version 0.9.0 (beta)</span>
    </div>
    <div id="projectbrief">Tools, software frameworks, and work flows for productivity with CMSIS based projects</div>
   </td>
@@ -119,7 +119,7 @@ $(document).ready(function(){initNavTree('cp_init.html','');});
 <h1><a class="anchor" id="cp_init_example"></a>
 Usage Example</h1>
 <pre class="fragment">$ cp_init.sh ./packrepo
-(cp_init.sh): Setup Pack Directory 0.1.0 (C) 2020 ARM
+(cp_init.sh): Setup Pack Directory 0.9.0 (C) 2020 ARM
 info: reading directory: ./packrepo
 downloading package index file from
 ######################################################################## 100.0%
@@ -152,7 +152,7 @@ Error Messages</h1>
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
     <li class="navelem"><a class="el" href="CmdLineBuild.html">Command Line Build</a></li>
-    <li class="footer">Generated on Wed Feb 26 2020 09:42:01 for CMSIS-Build Version 0.1.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:55 for CMSIS-Build Version 0.9.0 (beta) by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Build/html/cp_install.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Build
-   &#160;<span id="projectnumber">Version 0.1.0</span>
+   &#160;<span id="projectnumber">Version 0.9.0 (beta)</span>
    </div>
    <div id="projectbrief">Tools, software frameworks, and work flows for productivity with CMSIS based projects</div>
   </td>
@@ -137,17 +137,17 @@ $(document).ready(function(){initNavTree('cp_install.html','');});
 Usage Example</h1>
 <pre class="fragment">$
 cp_install.sh Simulation.cpinstall
-(cp_install.sh): Install Packs 0.1.0 (C) 2020 ARM
+(cp_install.sh): Install Packs 0.9.0 (C) 2020 ARM
 info: reading file: Simulation.cpinstall
 dos2unix: converting file Simulation.cpinstall to Unix format...
 http://www.keil.com/pack/ARM.CMSIS.5.6.0.pack
 ######################################################################## 100.0%#=#=#
 ######################################################################## 100.0%
-info: ARM.CMSIS.5.6.0.pack installing into C:\WORK\UV\trunk\CMSIS_Build\Installer\cbuild\bin\test\pack/ARM/CMSIS/5.6.0
+info: ARM.CMSIS.5.6.0.pack installing into /c/arm/cbuild/packs/ARM/CMSIS/5.6.0
 http://www.keil.com/pack/Keil.ARM_Compiler.1.6.1.pack
 ######################################################################## 100.0%#=#=#
 ######################################################################## 100.0%
-info: Keil.ARM_Compiler.1.6.1.pack installing into C:\WORK\UV\trunk\CMSIS_Build\Installer\cbuild\bin\test\pack/Keil/ARM_Compiler/1.6.1
+info: Keil.ARM_Compiler.1.6.1.pack installing into /c/arm/cbuild/packs/Keil/ARM_Compiler/1.6.1
 pack installation completed successfully
 </pre><h1><a class="anchor" id="cp_install_errors"></a>
 Error Messages</h1>
@@ -183,7 +183,7 @@ Error Messages</h1>
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
     <li class="navelem"><a class="el" href="CmdLineBuild.html">Command Line Build</a></li>
-    <li class="footer">Generated on Wed Feb 26 2020 09:42:01 for CMSIS-Build Version 0.1.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:55 for CMSIS-Build Version 0.9.0 (beta) by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Build/html/cprjFormat_pg.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Build
-   &#160;<span id="projectnumber">Version 0.1.0</span>
+   &#160;<span id="projectnumber">Version 0.9.0 (beta)</span>
    </div>
    <div id="projectbrief">Tools, software frameworks, and work flows for productivity with CMSIS based projects</div>
   </td>
@@ -136,14 +136,17 @@ Varieties of a build</h1>
 <li>RTE folder containing preconfigured component configuration files.</li>
 </ul>
 <p>Note: additional command line options for the tool-chains are tool-chain specific and are transparently passed onto the command line. Command line options related to the processor and it's features are automatically derived from the device information and must not be specified.</p>
-<p>Refer to CMSIS-Build (ToDo) for further information how to build software based on the CMSIS Project description at the command line and how to create and manage projects using layers.</p>
-<p>See <a class="el" href="element_cprj.html">Project Description Root</a> for details. </p>
+<p>&#160;</p>
+<hr/>
+<p>See <a class="el" href="element_cprj.html">Project Description Root</a> for details about the description format..</p>
+<p>See <a class="el" href="CmdLineBuild.html">CMSIS-Build</a> for further information how to build software based on the CMSIS Project description at the command line and how to create and manage projects using layers.</p>
+<p>See <a class="el" href="projectDescriptionSchema.html">Project Description Schema file</a> for validation of project files. </p>
 </div></div><!-- contents -->
 </div><!-- doc-content -->
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Feb 26 2020 09:42:01 for CMSIS-Build Version 0.1.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:55 for CMSIS-Build Version 0.9.0 (beta) by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Build/html/cprjFormat_pg.js

@@ -3,5 +3,6 @@ var cprjFormat_pg =
     [ "Overview", "cprjFormat_pg.html#section_overview", null ],
     [ "Introduction of Layers", "cprjFormat_pg.html#section_layer", null ],
     [ "Varieties of a build", "cprjFormat_pg.html#section_varieties", null ],
-    [ "/cprj", "element_cprj.html", "element_cprj" ]
+    [ "/cprj", "element_cprj.html", "element_cprj" ],
+    [ "Project Description Schema", "projectDescriptionSchema.html", null ]
 ];

docs/Build/html/cprj_types.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Build
-   &#160;<span id="projectnumber">Version 0.1.0</span>
+   &#160;<span id="projectnumber">Version 0.9.0 (beta)</span>
    </div>
    <div id="projectbrief">Tools, software frameworks, and work flows for productivity with CMSIS based projects</div>
   </td>
@@ -289,9 +289,7 @@ toolOptionType</h1>
 <tr>
 <td class="XML-Token">config </td><td>The file is a configuration file of the component. It is expected that only configuration options are modified. The file is managed as part of the component, as a project-specific file typically copied into the component section of the project.s  </td></tr>
 <tr>
-<td class="XML-Token">template </td><td><p class="starttd">The file is used as a source code template file. It is expected to be edited and extended by the software developer. The file can be copied into a user section of the project. </p>
-<p class="endtd"></p>
-</td></tr>
+<td class="XML-Token">template </td><td>The file is used as a source code template file. It is expected to be edited and extended by the software developer. The file can be copied into a user section of the project.  </td></tr>
 </table>
 <p>&#160;</p>
 <hr/>
@@ -311,7 +309,7 @@ toolOptionType</h1>
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
     <li class="navelem"><a class="el" href="cprjFormat_pg.html">Project Description (*.cprj) Format</a></li><li class="navelem"><a class="el" href="element_cprj.html">/cprj</a></li>
-    <li class="footer">Generated on Wed Feb 26 2020 09:42:02 for CMSIS-Build Version 0.1.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:55 for CMSIS-Build Version 0.9.0 (beta) by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Build/html/element_compilers.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Build
-   &#160;<span id="projectnumber">Version 0.1.0</span>
+   &#160;<span id="projectnumber">Version 0.9.0 (beta)</span>
    </div>
    <div id="projectbrief">Tools, software frameworks, and work flows for productivity with CMSIS based projects</div>
   </td>
@@ -143,7 +143,7 @@ $(document).ready(function(){initNavTree('element_compilers.html','');});
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
     <li class="navelem"><a class="el" href="cprjFormat_pg.html">Project Description (*.cprj) Format</a></li><li class="navelem"><a class="el" href="element_cprj.html">/cprj</a></li>
-    <li class="footer">Generated on Wed Feb 26 2020 09:42:02 for CMSIS-Build Version 0.1.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:55 for CMSIS-Build Version 0.9.0 (beta) by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Build/html/element_components.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Build
-   &#160;<span id="projectnumber">Version 0.1.0</span>
+   &#160;<span id="projectnumber">Version 0.9.0 (beta)</span>
    </div>
    <div id="projectbrief">Tools, software frameworks, and work flows for productivity with CMSIS based projects</div>
   </td>
@@ -331,7 +331,7 @@ $(document).ready(function(){initNavTree('element_components.html','');});
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
     <li class="navelem"><a class="el" href="cprjFormat_pg.html">Project Description (*.cprj) Format</a></li><li class="navelem"><a class="el" href="element_cprj.html">/cprj</a></li>
-    <li class="footer">Generated on Wed Feb 26 2020 09:42:01 for CMSIS-Build Version 0.1.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:55 for CMSIS-Build Version 0.9.0 (beta) by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Build/html/element_cprj.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Build
-   &#160;<span id="projectnumber">Version 0.1.0</span>
+   &#160;<span id="projectnumber">Version 0.9.0 (beta)</span>
    </div>
    <div id="projectbrief">Tools, software frameworks, and work flows for productivity with CMSIS based projects</div>
   </td>
@@ -110,7 +110,7 @@ $(document).ready(function(){initNavTree('element_cprj.html','');});
 <div class="title">/cprj </div>  </div>
 </div><!--header-->
 <div class="contents">
-<div class="textblock"><p>CMSIS project files use the file extension *.cprj and CMSIS project layer files use the file extension *.clayer. Both file types share a single file format which can be validated using the dedicate CPRJ schema file located in CMSIS/Utilities/CPRJ.xsd.</p>
+<div class="textblock"><p>CMSIS project files use the file extension *.cprj and CMSIS project layer files use the file extension *.clayer. Both file types share a single file format which can be validated using the dedicate CPRJ schema file located in <a class="el" href="projectDescriptionSchema.html">CMSIS/Utilities/CPRJ.xsd</a>.</p>
 <p>The location of a project or layer file always marks the root point and all file references are always relative to this root point, unless a file belongs to a component. In the latter case the files are relative to the base directory of the referenced CMSIS Software Pack version.</p>
 <p>The high level structure of a project is constructed from: </p>
 <table  class="cmtable" summary="Top level elements">
@@ -271,7 +271,7 @@ $(document).ready(function(){initNavTree('element_cprj.html','');});
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
     <li class="navelem"><a class="el" href="cprjFormat_pg.html">Project Description (*.cprj) Format</a></li>
-    <li class="footer">Generated on Wed Feb 26 2020 09:42:01 for CMSIS-Build Version 0.1.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:55 for CMSIS-Build Version 0.9.0 (beta) by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Build/html/element_created.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Build
-   &#160;<span id="projectnumber">Version 0.1.0</span>
+   &#160;<span id="projectnumber">Version 0.9.0 (beta)</span>
    </div>
    <div id="projectbrief">Tools, software frameworks, and work flows for productivity with CMSIS based projects</div>
   </td>
@@ -135,7 +135,7 @@ $(document).ready(function(){initNavTree('element_created.html','');});
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
     <li class="navelem"><a class="el" href="cprjFormat_pg.html">Project Description (*.cprj) Format</a></li><li class="navelem"><a class="el" href="element_cprj.html">/cprj</a></li>
-    <li class="footer">Generated on Wed Feb 26 2020 09:42:01 for CMSIS-Build Version 0.1.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:55 for CMSIS-Build Version 0.9.0 (beta) by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Build/html/element_files.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Build
-   &#160;<span id="projectnumber">Version 0.1.0</span>
+   &#160;<span id="projectnumber">Version 0.9.0 (beta)</span>
    </div>
    <div id="projectbrief">Tools, software frameworks, and work flows for productivity with CMSIS based projects</div>
   </td>
@@ -248,7 +248,7 @@ $(document).ready(function(){initNavTree('element_files.html','');});
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
     <li class="navelem"><a class="el" href="cprjFormat_pg.html">Project Description (*.cprj) Format</a></li><li class="navelem"><a class="el" href="element_cprj.html">/cprj</a></li>
-    <li class="footer">Generated on Wed Feb 26 2020 09:42:02 for CMSIS-Build Version 0.1.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:55 for CMSIS-Build Version 0.9.0 (beta) by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Build/html/element_info.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Build
-   &#160;<span id="projectnumber">Version 0.1.0</span>
+   &#160;<span id="projectnumber">Version 0.9.0 (beta)</span>
    </div>
    <div id="projectbrief">Tools, software frameworks, and work flows for productivity with CMSIS based projects</div>
   </td>
@@ -178,7 +178,7 @@ $(document).ready(function(){initNavTree('element_info.html','');});
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
     <li class="navelem"><a class="el" href="cprjFormat_pg.html">Project Description (*.cprj) Format</a></li><li class="navelem"><a class="el" href="element_cprj.html">/cprj</a></li>
-    <li class="footer">Generated on Wed Feb 26 2020 09:42:01 for CMSIS-Build Version 0.1.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:55 for CMSIS-Build Version 0.9.0 (beta) by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Build/html/element_layers.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Build
-   &#160;<span id="projectnumber">Version 0.1.0</span>
+   &#160;<span id="projectnumber">Version 0.9.0 (beta)</span>
    </div>
    <div id="projectbrief">Tools, software frameworks, and work flows for productivity with CMSIS based projects</div>
   </td>
@@ -168,7 +168,7 @@ $(document).ready(function(){initNavTree('element_layers.html','');});
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
     <li class="navelem"><a class="el" href="cprjFormat_pg.html">Project Description (*.cprj) Format</a></li><li class="navelem"><a class="el" href="element_cprj.html">/cprj</a></li>
-    <li class="footer">Generated on Wed Feb 26 2020 09:42:02 for CMSIS-Build Version 0.1.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:55 for CMSIS-Build Version 0.9.0 (beta) by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Build/html/element_packages.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Build
-   &#160;<span id="projectnumber">Version 0.1.0</span>
+   &#160;<span id="projectnumber">Version 0.9.0 (beta)</span>
    </div>
    <div id="projectbrief">Tools, software frameworks, and work flows for productivity with CMSIS based projects</div>
   </td>
@@ -144,7 +144,7 @@ $(document).ready(function(){initNavTree('element_packages.html','');});
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
     <li class="navelem"><a class="el" href="cprjFormat_pg.html">Project Description (*.cprj) Format</a></li><li class="navelem"><a class="el" href="element_cprj.html">/cprj</a></li>
-    <li class="footer">Generated on Wed Feb 26 2020 09:42:02 for CMSIS-Build Version 0.1.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:55 for CMSIS-Build Version 0.9.0 (beta) by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Build/html/element_target.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Build
-   &#160;<span id="projectnumber">Version 0.1.0</span>
+   &#160;<span id="projectnumber">Version 0.9.0 (beta)</span>
    </div>
    <div id="projectbrief">Tools, software frameworks, and work flows for productivity with CMSIS based projects</div>
   </td>
@@ -357,7 +357,7 @@ $(document).ready(function(){initNavTree('element_target.html','');});
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
     <li class="navelem"><a class="el" href="cprjFormat_pg.html">Project Description (*.cprj) Format</a></li><li class="navelem"><a class="el" href="element_cprj.html">/cprj</a></li>
-    <li class="footer">Generated on Wed Feb 26 2020 09:42:01 for CMSIS-Build Version 0.1.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:55 for CMSIS-Build Version 0.9.0 (beta) by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Build/html/index.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Build
-   &#160;<span id="projectnumber">Version 0.1.0</span>
+   &#160;<span id="projectnumber">Version 0.9.0 (beta)</span>
    </div>
    <div id="projectbrief">Tools, software frameworks, and work flows for productivity with CMSIS based projects</div>
   </td>
@@ -112,19 +112,39 @@ $(document).ready(function(){initNavTree('index.html','');});
 <div class="contents">
 <div class="textblock"><p><b>CMSIS-Build</b> is a set of tools, software frameworks, and work flows that improve productivity:</p>
 <ul>
-<li>Continuous Integration (CI) work flow for projects that are based on software components framed in CMSIS-Pack format.</li>
-<li>Software Layers for code reuse across different targets. A software layer is a pre-configured software component selection and user source code.</li>
-<li>Virtual I/O which is a set of generic input/output functions for example and test code. It allows to migrate fast from evaluation boards to production hardware.</li>
+<li><a class="el" href="cprjFormat_pg.html">CPRJ</a> is a generic CMSIS-aware project file format that allows IDEs and command-line build tools to share the same projects.</li>
+<li>A <a class="el" href="CmdLineBuild.html">Continuous Integration (CI) work flow</a> for projects that are based on software components supplied in CMSIS-Pack format.</li>
+<li>Software Layers enable code reuse across different targets. A software layer is a pre-configured software component selection and user source code.</li>
+<li><a href="../../Driver/html/group__vio__interface__gr.html"><b>CMSIS-Driver VIO</b></a> is a set of generic input/output functions for example and test code. It allows to fast migration from evaluation boards to production hardware.</li>
+</ul>
+<p>The figure below shows how the <b>CMSIS-Build</b> components may be used to create a IoT cloud application:</p>
+<ul>
+<li>The <b>Board I/O</b> layer contains the drivers and device configuration for a specific evaluation board.</li>
+<li>The <b>Cloud</b> layer implements the software components that are required to connect to a Cloud Service Provider (CSP).</li>
+<li>The <b>Application Code</b> may start with reference example and is expanded to application specific requirements that access specialized peripherals.</li>
 </ul>
 <div class="image">
 <img src="Layer.png" alt="Layer.png"/>
 <div class="caption">
 Software Layers and Virtual I/O</div></div>
-<dl class="todo"><dt><b><a class="el" href="todo.html#_todo000001">Todo:</a></b></dt><dd>add link to CMSIS-pack for "generic project format"<ul>
-<li><a class="el" href="cprjFormat_pg.html">Project Description (*.cprj) Format</a> describes all XML elements that are available for project descriptions and their usage.</li>
+<p>Software layers and Virtual I/O simplify these use cases:</p>
+<p><b>Port software from evaluation board to custom hardware:</b><br/>
+</p>
+<ul>
+<li>Frequently, the software development starts on an evaluation board, for example because production hardware is not yet available. The <a href="../../Driver/html/group__vio__interface__gr.html"><b>VIO component</b></a> allows you to use the I/O capabilities of an evaluation kit and disconnect it when moving to production hardware. In case the production hardware uses a different device configuration or different I/O drivers, the <b>Board I/O</b> layer may be swapped.</li>
+</ul>
+<p><b>Deliver reference examples for many different evaluation boards:</b><br/>
+</p>
+<ul>
+<li>Reference examples are a great way to demonstrate a software solution. It is however expensive to support many different evaluation boards. The VIO and CMSIS-Driver components give reference examples for a consistent interface to target hardware. When such a consistent set of components is available as a <b>Board I/O</b> layer for many different evaluation boards, it allows to run a <b>Cloud</b> layer together with a reference example. The tools for <a class="el" href="CmdLineBuild.html">Command Line Build</a> allow to combine various different layers and allow in this way to generate several different reference examples on a range of evaluation boards.</li>
+</ul>
+<h1><a class="anchor" id="CB_Components"></a>
+Components of CMSIS-Build</h1>
+<p><b>Specification</b> of a generic project file format:</p>
+<ul>
+<li><a class="el" href="cprjFormat_pg.html">Project Description (*.cprj) Format</a> describes all XML elements that are available for the project description and how to use them.</li>
 </ul>
-</dd></dl>
-<p><b>Tools</b> that support <a class="el" href="CmdLineBuild.html">Command Line Build</a> with software packs and the generic project format:</p>
+<p><b>Tools</b> that support <a class="el" href="CmdLineBuild.html">Command Line Build</a> with software packs and the generic project file format:</p>
 <ul>
 <li><a class="el" href="cbuildgen.html">cbuildgen: Build Process Manager</a> generates a standard MAKE file and allows to manage software layers.</li>
 <li><a class="el" href="ccmerge.html">ccmerge: Config File Updater</a> updates configuration files that are based on <a href="../../Pack/html/configWizard.html"><b>PackConfiguration Wizard Annotations</b></a>. </li>
@@ -134,7 +154,7 @@ Software Layers and Virtual I/O</div></div>
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Feb 26 2020 09:42:02 for CMSIS-Build Version 0.1.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:55 for CMSIS-Build Version 0.9.0 (beta) by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Build/html/navtree.js

@@ -1,11 +1,12 @@
 var NAVTREE =
 [
   [ "CMSIS-Build", "index.html", [
-    [ "Overview", "index.html", null ],
+    [ "Overview", "index.html", [
+      [ "Components of CMSIS-Build", "index.html#CB_Components", null ]
+    ] ],
     [ "Revision history", "build_revisionHistory.html", null ],
     [ "Command Line Build", "CmdLineBuild.html", "CmdLineBuild" ],
-    [ "Project Description (*.cprj) Format", "cprjFormat_pg.html", "cprjFormat_pg" ],
-    [ "Todo List", "todo.html", null ]
+    [ "Project Description (*.cprj) Format", "cprjFormat_pg.html", "cprjFormat_pg" ]
   ] ]
 ];
 

docs/Build/html/navtreeindex0.js

@@ -64,8 +64,9 @@ var NAVTREEINDEX0 =
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 "element_target.html#element_target_cflags":[3,3,5,3],
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-"index.html":[0],
 "index.html":[],
+"index.html":[0],
+"index.html#CB_Components":[0,0],
 "pages.html":[],
-"todo.html":[4]
+"projectDescriptionSchema.html":[3,4]
 };

docs/Build/html/pages.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Build
-   &#160;<span id="projectnumber">Version 0.1.0</span>
+   &#160;<span id="projectnumber">Version 0.9.0 (beta)</span>
    </div>
    <div id="projectbrief">Tools, software frameworks, and work flows for productivity with CMSIS based projects</div>
   </td>
@@ -122,18 +122,18 @@ $(document).ready(function(){initNavTree('pages.html','');});
 <tr id="row_1_5_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="cp_install.html" target="_self">cp_install.sh: Install Packs</a></td><td class="desc"></td></tr>
 <tr id="row_1_6_" class="even"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="ccmerge.html" target="_self">ccmerge: Config File Updater</a></td><td class="desc"></td></tr>
 <tr id="row_1_7_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><a class="el" href="cbuild_uv.html" target="_self">cbuild_uv.sh: Build MDK project</a></td><td class="desc"></td></tr>
-<tr id="row_2_" class="even"><td class="entry"><img id="arr_2_" src="ftv2mnode.png" alt="o" width="16" height="22" onclick="toggleFolder('2_')"/><a class="el" href="cprjFormat_pg.html" target="_self">Project Description (*.cprj) Format</a></td><td class="desc"></td></tr>
-<tr id="row_2_0_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img id="arr_2_0_" src="ftv2mlastnode.png" alt="\" width="16" height="22" onclick="toggleFolder('2_0_')"/><a class="el" href="element_cprj.html" target="_self">/cprj</a></td><td class="desc"></td></tr>
-<tr id="row_2_0_0_" class="even"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2blank.png" alt="&#160;" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="element_created.html" target="_self">/cprj/created</a></td><td class="desc"></td></tr>
-<tr id="row_2_0_1_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2blank.png" alt="&#160;" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="element_info.html" target="_self">/cprj/info</a></td><td class="desc"></td></tr>
-<tr id="row_2_0_2_" class="even"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2blank.png" alt="&#160;" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="element_layers.html" target="_self">/cprj/layers</a></td><td class="desc"></td></tr>
-<tr id="row_2_0_3_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2blank.png" alt="&#160;" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="element_packages.html" target="_self">/cprj/packages</a></td><td class="desc"></td></tr>
-<tr id="row_2_0_4_" class="even"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2blank.png" alt="&#160;" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="element_compilers.html" target="_self">/cprj/compilers</a></td><td class="desc"></td></tr>
-<tr id="row_2_0_5_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2blank.png" alt="&#160;" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="element_target.html" target="_self">/cprj/target</a></td><td class="desc"></td></tr>
-<tr id="row_2_0_6_" class="even"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2blank.png" alt="&#160;" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="element_components.html" target="_self">/cprj/components</a></td><td class="desc"></td></tr>
-<tr id="row_2_0_7_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2blank.png" alt="&#160;" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="element_files.html" target="_self">/cprj/files</a></td><td class="desc"></td></tr>
-<tr id="row_2_0_8_" class="even"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2blank.png" alt="&#160;" width="16" height="22" /><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><a class="el" href="cprj_types.html" target="_self">cprj specific types</a></td><td class="desc"></td></tr>
-<tr id="row_3_"><td class="entry"><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><a class="el" href="todo.html" target="_self">Todo List</a></td><td class="desc"></td></tr>
+<tr id="row_2_" class="even"><td class="entry"><img id="arr_2_" src="ftv2mlastnode.png" alt="\" width="16" height="22" onclick="toggleFolder('2_')"/><a class="el" href="cprjFormat_pg.html" target="_self">Project Description (*.cprj) Format</a></td><td class="desc"></td></tr>
+<tr id="row_2_0_"><td class="entry"><img src="ftv2blank.png" alt="&#160;" width="16" height="22" /><img id="arr_2_0_" src="ftv2mnode.png" alt="o" width="16" height="22" onclick="toggleFolder('2_0_')"/><a class="el" href="element_cprj.html" target="_self">/cprj</a></td><td class="desc"></td></tr>
+<tr id="row_2_0_0_" class="even"><td class="entry"><img src="ftv2blank.png" alt="&#160;" width="16" height="22" /><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="element_created.html" target="_self">/cprj/created</a></td><td class="desc"></td></tr>
+<tr id="row_2_0_1_"><td class="entry"><img src="ftv2blank.png" alt="&#160;" width="16" height="22" /><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="element_info.html" target="_self">/cprj/info</a></td><td class="desc"></td></tr>
+<tr id="row_2_0_2_" class="even"><td class="entry"><img src="ftv2blank.png" alt="&#160;" width="16" height="22" /><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="element_layers.html" target="_self">/cprj/layers</a></td><td class="desc"></td></tr>
+<tr id="row_2_0_3_"><td class="entry"><img src="ftv2blank.png" alt="&#160;" width="16" height="22" /><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="element_packages.html" target="_self">/cprj/packages</a></td><td class="desc"></td></tr>
+<tr id="row_2_0_4_" class="even"><td class="entry"><img src="ftv2blank.png" alt="&#160;" width="16" height="22" /><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="element_compilers.html" target="_self">/cprj/compilers</a></td><td class="desc"></td></tr>
+<tr id="row_2_0_5_"><td class="entry"><img src="ftv2blank.png" alt="&#160;" width="16" height="22" /><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="element_target.html" target="_self">/cprj/target</a></td><td class="desc"></td></tr>
+<tr id="row_2_0_6_" class="even"><td class="entry"><img src="ftv2blank.png" alt="&#160;" width="16" height="22" /><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="element_components.html" target="_self">/cprj/components</a></td><td class="desc"></td></tr>
+<tr id="row_2_0_7_"><td class="entry"><img src="ftv2blank.png" alt="&#160;" width="16" height="22" /><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="element_files.html" target="_self">/cprj/files</a></td><td class="desc"></td></tr>
+<tr id="row_2_0_8_" class="even"><td class="entry"><img src="ftv2blank.png" alt="&#160;" width="16" height="22" /><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><a class="el" href="cprj_types.html" target="_self">cprj specific types</a></td><td class="desc"></td></tr>
+<tr id="row_2_1_"><td class="entry"><img src="ftv2blank.png" alt="&#160;" width="16" height="22" /><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><a class="el" href="projectDescriptionSchema.html" target="_self">Project Description Schema</a></td><td class="desc"></td></tr>
 </table>
 </div><!-- directory -->
 </div><!-- contents -->
@@ -141,7 +141,7 @@ $(document).ready(function(){initNavTree('pages.html','');});
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Feb 26 2020 09:42:02 for CMSIS-Build Version 0.1.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:55 for CMSIS-Build Version 0.9.0 (beta) by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Build/html/projectDescriptionSchema.html

@@ -0,0 +1,621 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<title>Project Description Schema</title>
+<title>CMSIS-Build: Project Description Schema</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<script type="text/javascript" src="printComponentTabs.js"></script>
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+  $(window).load(resizeHeight);
+</script>
+<link href="search/search.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="search/search.js"></script>
+<script type="text/javascript">
+  $(document).ready(function() { searchBox.OnSelectItem(0); });
+</script>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-Build
+   &#160;<span id="projectnumber">Version 0.9.0 (beta)</span>
+   </div>
+   <div id="projectbrief">Tools, software frameworks, and work flows for productivity with CMSIS based projects</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <script type="text/javascript">
+		<!--
+		writeComponentTabs.call(this);
+		//-->
+      </script>
+	  </ul>
+</div>
+<!-- Generated by Doxygen 1.8.6 -->
+<script type="text/javascript">
+var searchBox = new SearchBox("searchBox", "search",false,'Search');
+</script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li class="current"><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li>
+        <div id="MSearchBox" class="MSearchBoxInactive">
+        <span class="left">
+          <img id="MSearchSelect" src="search/mag_sel.png"
+               onmouseover="return searchBox.OnSearchSelectShow()"
+               onmouseout="return searchBox.OnSearchSelectHide()"
+               alt=""/>
+          <input type="text" id="MSearchField" value="Search" accesskey="S"
+               onfocus="searchBox.OnSearchFieldFocus(true)" 
+               onblur="searchBox.OnSearchFieldFocus(false)" 
+               onkeyup="searchBox.OnSearchFieldChange(event)"/>
+          </span><span class="right">
+            <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a>
+          </span>
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+    </ul>
+  </div>
+</div><!-- top -->
+<div id="side-nav" class="ui-resizable side-nav-resizable">
+  <div id="nav-tree">
+    <div id="nav-tree-contents">
+      <div id="nav-sync" class="sync"></div>
+    </div>
+  </div>
+  <div id="splitbar" style="-moz-user-select:none;" 
+       class="ui-resizable-handle">
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+</div>
+<script type="text/javascript">
+$(document).ready(function(){initNavTree('projectDescriptionSchema.html','');});
+</script>
+<div id="doc-content">
+<!-- window showing the filter options -->
+<div id="MSearchSelectWindow"
+     onmouseover="return searchBox.OnSearchSelectShow()"
+     onmouseout="return searchBox.OnSearchSelectHide()"
+     onkeydown="return searchBox.OnSearchSelectKey(event)">
+<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark">&#160;</span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark">&#160;</span>Pages</a></div>
+
+<!-- iframe showing the search results (closed by default) -->
+<div id="MSearchResultsWindow">
+<iframe src="javascript:void(0)" frameborder="0" 
+        name="MSearchResults" id="MSearchResults">
+</iframe>
+</div>
+
+<div class="header">
+  <div class="headertitle">
+<div class="title">Project Description Schema </div>  </div>
+</div><!--header-->
+<div class="contents">
+<div class="textblock"><pre class="fragment">&lt;?xml version="1.0" encoding="UTF-8"?&gt;
+&lt;!--
+
+  Copyright (c) 2020 ARM Limited. All rights reserved.
+
+  SPDX-License-Identifier: Apache-2.0
+
+  Licensed under the Apache License, Version 2.0 (the License); you may
+  not use this file except in compliance with the License.
+  You may obtain a copy of the License at
+
+  www.apache.org/licenses/LICENSE-2.0
+
+  Unless required by applicable law or agreed to in writing, software
+  distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  See the License for the specific language governing permissions and
+  limitations under the License.
+
+  $Date:        03. April 2020
+  $Revision:    0.9.0
+
+  $Project: Schema File for CMSIS Project Description File Format Specification
+
+  SchemaVersion=0.9.0
+
+  0.9.0: (BETA) Specification of CMSIS Project Format, replacing CPDSC based on PACK.xsd.
+
+--&gt;
+
+&lt;xs:schema xmlns:xs="http://www.w3.org/2001/XMLSchema" elementFormDefault="qualified" attributeFormDefault="qualified" version="0.9.0"&gt;
+
+  &lt;xs:simpleType name="RestrictedString"&gt;
+    &lt;xs:restriction base="xs:string"&gt;
+      &lt;xs:pattern value="[\-_A-Za-z0-9]+" /&gt;
+    &lt;/xs:restriction&gt;
+  &lt;/xs:simpleType&gt;
+
+  &lt;xs:simpleType name="SchemaVersionType"&gt;
+    &lt;xs:restriction base="xs:string"&gt;
+      &lt;xs:pattern value="[0-9]+\.[0-9]+((\.[0-9]+)|())" /&gt;
+    &lt;/xs:restriction&gt;
+  &lt;/xs:simpleType&gt;
+
+  &lt;xs:simpleType name="ComponentVersionType"&gt;
+    &lt;xs:restriction base="xs:string"&gt;
+      &lt;xs:pattern value="[0-9]+\.[0-9]+((\.[0-9]+)|())((\-[0-9A-Za-z_\-\.]+)|([_A-Za-z][0-9A-Za-z_\-\.]*)|())((\+[\-\._A-Za-z0-9]+)|())" /&gt;
+    &lt;/xs:restriction&gt;
+  &lt;/xs:simpleType&gt;
+
+  &lt;xs:simpleType name="PackVersionType"&gt;
+    &lt;xs:restriction base="xs:string"&gt;
+      &lt;!-- major . minor . patch [[-]quality] [+build] --&gt;
+      &lt;xs:pattern value="[0-9]+.[0-9]+.[0-9]+((\-[0-9A-Za-z_\-\.]+)|([_A-Za-z][0-9A-Za-z_\-\.]*)|())((\+[\-\._A-Za-z0-9]+)|())" /&gt;
+    &lt;/xs:restriction&gt;
+  &lt;/xs:simpleType&gt;
+
+  &lt;!-- version can contain one or more of alphanumeric characters and symbols '_' '-' '.' 
+       Allows specifing a version range: minVersion : maxVersion
+  --&gt;
+  &lt;xs:simpleType name="VersionRangeType"&gt;
+    &lt;xs:restriction base="xs:string"&gt;
+      &lt;xs:pattern value="[0-9]+.[0-9]+((.[0-9]+)|())((\-[0-9A-Za-z_\-\.]+)|([_A-Za-z][0-9A-Za-z_\-\.]*)|())((\+[\-\._A-Za-z0-9]+)|())((:[0-9]+.[0-9]+((.[0-9]+)|()))|())((\-[0-9A-Za-z_\-\.]+)|([_A-Za-z][0-9A-Za-z_\-\.]*)|())((\+[\-\._A-Za-z0-9]+)|())" /&gt;
+    &lt;/xs:restriction&gt;
+  &lt;/xs:simpleType&gt;
+
+  &lt;!-- Dendian enumeration type --&gt;
+  &lt;xs:simpleType name="DendianEnum"&gt;
+    &lt;xs:restriction base="xs:token"&gt;
+      &lt;xs:enumeration value="Little-endian" /&gt;
+      &lt;xs:enumeration value="Big-endian" /&gt;
+      &lt;xs:enumeration value="Configurable" /&gt;
+      &lt;xs:enumeration value="*" /&gt;
+    &lt;/xs:restriction&gt;
+  &lt;/xs:simpleType&gt;
+
+  &lt;!-- Dfpu enumeration type --&gt;
+  &lt;xs:simpleType name="DfpuEnum"&gt;
+    &lt;xs:restriction base="xs:token"&gt;
+      &lt;!-- core has FPU (type of FPU depends on Dcore) --&gt;
+      &lt;xs:enumeration value="FPU" /&gt;
+      &lt;xs:enumeration value="1" /&gt;
+      &lt;!-- core has no FPU --&gt;
+      &lt;xs:enumeration value="NO_FPU" /&gt;
+      &lt;xs:enumeration value="0" /&gt;
+      &lt;!-- single precision FPU --&gt;
+      &lt;xs:enumeration value="SP_FPU" /&gt;
+      &lt;!-- double precision FPU --&gt;
+      &lt;xs:enumeration value="DP_FPU" /&gt;
+    &lt;/xs:restriction&gt;
+  &lt;/xs:simpleType&gt;
+
+  &lt;!-- Dmpu enumeration type --&gt;
+  &lt;xs:simpleType name="DmpuEnum"&gt;
+    &lt;xs:restriction base="xs:token"&gt;
+      &lt;xs:enumeration value="MPU" /&gt;
+      &lt;xs:enumeration value="NO_MPU" /&gt;
+    &lt;/xs:restriction&gt;
+  &lt;/xs:simpleType&gt;
+
+  &lt;!-- Dtz TrustZone enumeration type --&gt;
+  &lt;xs:simpleType name="DtzEnum"&gt;
+    &lt;xs:restriction base="xs:token"&gt;
+      &lt;xs:enumeration value="TZ" /&gt;
+      &lt;xs:enumeration value="NO_TZ" /&gt;
+    &lt;/xs:restriction&gt;
+  &lt;/xs:simpleType&gt;
+
+  &lt;!-- Dsecure enumeration type --&gt;
+  &lt;xs:simpleType name="DsecureEnum"&gt;
+    &lt;xs:restriction base="xs:token"&gt;
+      &lt;xs:enumeration value="Secure" /&gt;
+      &lt;xs:enumeration value="Non-secure" /&gt;
+      &lt;xs:enumeration value="TZ-disabled" /&gt;
+    &lt;/xs:restriction&gt;
+  &lt;/xs:simpleType&gt;
+
+  &lt;!-- Ddsp DSP extensions enumeration type --&gt;
+  &lt;xs:simpleType name="DdspEnum"&gt;
+    &lt;xs:restriction base="xs:token"&gt;
+      &lt;xs:enumeration value="DSP" /&gt;
+      &lt;xs:enumeration value="NO_DSP" /&gt;
+    &lt;/xs:restriction&gt;
+  &lt;/xs:simpleType&gt;
+
+  &lt;!-- Dmve extension enumeration type --&gt;
+  &lt;xs:simpleType name="DmveEnum"&gt;
+    &lt;xs:restriction base="xs:token"&gt;
+      &lt;xs:enumeration value="NO_MVE"/&gt;
+      &lt;xs:enumeration value="MVE"/&gt;
+      &lt;xs:enumeration value="FP_MVE"/&gt;
+    &lt;/xs:restriction&gt;
+  &lt;/xs:simpleType&gt;
+
+  &lt;!-- file category type --&gt;
+  &lt;xs:simpleType name="FileCategoryType"&gt;
+    &lt;xs:restriction base="xs:token"&gt;
+      &lt;xs:enumeration value="doc" /&gt;
+      &lt;xs:enumeration value="header" /&gt;
+      &lt;xs:enumeration value="library" /&gt;
+      &lt;xs:enumeration value="object" /&gt;
+      &lt;xs:enumeration value="source" /&gt;
+      &lt;xs:enumeration value="sourceC" /&gt;
+      &lt;xs:enumeration value="sourceCpp" /&gt;
+      &lt;xs:enumeration value="sourceAsm" /&gt;
+      &lt;xs:enumeration value="linkerScript" /&gt;
+      &lt;xs:enumeration value="utility" /&gt;
+      &lt;xs:enumeration value="image" /&gt;
+      &lt;xs:enumeration value="other" /&gt;
+      &lt;xs:enumeration value="preIncludeGlobal"/&gt;
+      &lt;xs:enumeration value="preIncludeLocal"/&gt;
+    &lt;/xs:restriction&gt;
+  &lt;/xs:simpleType&gt;
+
+  &lt;!-- file attribute type --&gt;
+  &lt;xs:simpleType name="FileAttributeType"&gt;
+    &lt;xs:restriction base="xs:token"&gt;
+      &lt;xs:enumeration value="config" /&gt;
+    &lt;/xs:restriction&gt;
+  &lt;/xs:simpleType&gt;
+
+  &lt;!-- compiler toolchain enumeration --&gt;
+  &lt;xs:simpleType name="CompilerEnumType"&gt;
+    &lt;xs:restriction base="xs:token"&gt;
+      &lt;xs:enumeration value="GCC" /&gt;
+      &lt;xs:enumeration value="AC5" /&gt;
+      &lt;xs:enumeration value="AC6" /&gt;
+      &lt;xs:enumeration value="IAR" /&gt;
+      &lt;xs:enumeration value="Tasking" /&gt;
+      &lt;xs:enumeration value="GHS" /&gt;
+      &lt;xs:enumeration value="Cosmic" /&gt;
+      &lt;xs:enumeration value="G++"/&gt;
+      &lt;xs:enumeration value="*" /&gt;
+    &lt;/xs:restriction&gt;
+  &lt;/xs:simpleType&gt;
+
+  &lt;!-- compiler output enumeration --&gt;
+  &lt;xs:simpleType name="CompilerOutputType"&gt;
+    &lt;xs:restriction base="xs:token"&gt;
+      &lt;xs:enumeration value="exe" /&gt; &lt;!-- executable --&gt;
+      &lt;xs:enumeration value="lib" /&gt; &lt;!-- library --&gt;
+    &lt;/xs:restriction&gt;
+  &lt;/xs:simpleType&gt;
+
+  &lt;xs:simpleType name="InstancesType"&gt;
+    &lt;xs:restriction base="xs:unsignedInt"&gt;
+      &lt;xs:minInclusive value="1" /&gt;
+    &lt;/xs:restriction&gt;
+  &lt;/xs:simpleType&gt;
+
+  &lt;xs:complexType name="ComponentCategoryType"&gt;
+    &lt;xs:attribute name="Cvendor"     type="xs:string"            use="optional" /&gt;
+    &lt;xs:attribute name="Cbundle"     type="xs:string"            use="optional" /&gt;
+    &lt;xs:attribute name="Cclass"      type="xs:string"            use="required" /&gt;
+    &lt;xs:attribute name="Cgroup"      type="xs:string"            use="optional" /&gt;
+    &lt;xs:attribute name="Csub"        type="xs:string"            use="optional" /&gt;
+    &lt;xs:attribute name="Cvariant"    type="xs:string"            use="optional" /&gt;
+    &lt;xs:attribute name="Cversion"    type="ComponentVersionType" use="optional" /&gt;
+    &lt;xs:attribute name="Capiversion" type="ComponentVersionType" use="optional" /&gt;
+    &lt;xs:attribute name="instances"   type="InstancesType"        use="optional" default="1" /&gt;
+  &lt;/xs:complexType&gt;
+
+  &lt;!-- PackageType creates a unique ID for a package / if no version specified use "latest" --&gt;
+  &lt;xs:complexType name="PackageType"&gt;
+    &lt;!-- vendor of the package --&gt;
+    &lt;xs:attribute name="vendor"  type="xs:string" use="required" /&gt;
+    &lt;!-- name of the package --&gt;
+    &lt;xs:attribute name="name"    type="xs:string" use="required" /&gt;
+    &lt;!-- version of the package (no range supported) --&gt;
+    &lt;xs:attribute name="version" type="PackVersionType" use="optional" /&gt;
+  &lt;/xs:complexType&gt;
+
+  &lt;!-- Package section type --&gt;
+  &lt;xs:complexType name="PackagesType"&gt;
+    &lt;xs:sequence maxOccurs="unbounded"&gt;
+      &lt;xs:element name="package" type="PackageType" /&gt;
+    &lt;/xs:sequence&gt;
+  &lt;/xs:complexType&gt;
+
+  &lt;xs:complexType name="LayerType"&gt;
+    &lt;xs:all&gt;
+      &lt;!-- layer description --&gt;
+      &lt;xs:element name="description" type="xs:string" minOccurs="0" /&gt;
+      &lt;!-- layer intentionally does not have url ! --&gt;
+      &lt;!-- comma separated list of keywords --&gt;
+      &lt;xs:element name="keywords"    type="xs:string" minOccurs="0" /&gt;
+      &lt;!-- comma separated list of pre-defined categories --&gt;
+      &lt;xs:element name="category"    type="xs:string" minOccurs="0" /&gt;
+      &lt;!-- license covering the layer (the license of referenced components is not covered) --&gt;
+      &lt;xs:element name="license"     type="xs:string" minOccurs="0" /&gt;
+    &lt;/xs:all&gt;
+    &lt;!-- layer name is used in file and directory names, hence restricted --&gt;
+    &lt;xs:attribute name="name"        type="RestrictedString"  use="required" /&gt;
+    &lt;xs:attribute name="hasTarget"   type="xs:boolean" use="optional" /&gt;
+  &lt;/xs:complexType&gt;
+
+  &lt;!-- Layers section type --&gt;
+  &lt;xs:complexType name="LayersType"&gt;
+    &lt;xs:sequence maxOccurs="unbounded"&gt;
+      &lt;xs:element name="layer" type="LayerType" /&gt;
+    &lt;/xs:sequence&gt;
+  &lt;/xs:complexType&gt;
+
+  &lt;!-- CompilerType creates a unique toolchain ID, e.g. armcc 5.4.0 --&gt;
+  &lt;xs:complexType name="CompilerType"&gt;
+    &lt;xs:attribute name="name"    type="CompilerEnumType" use="required" /&gt;
+    &lt;xs:attribute name="version" type="VersionRangeType" use="required" /&gt;
+  &lt;/xs:complexType&gt;
+
+  &lt;!-- Compiler section type --&gt;
+  &lt;xs:complexType name="CompilersType"&gt;
+    &lt;xs:sequence maxOccurs="unbounded"&gt;
+      &lt;xs:element name="compiler" type="CompilerType" /&gt;
+    &lt;/xs:sequence&gt;
+  &lt;/xs:complexType&gt;
+
+
+  &lt;!-- Project target specification: --&gt;
+  &lt;xs:complexType name="TargetType"&gt;
+    &lt;xs:choice maxOccurs="unbounded"&gt;
+      &lt;!-- build options --&gt;
+      &lt;xs:element name="output"    type="OutputType" /&gt;
+      &lt;!-- linker command-line --&gt;
+      &lt;xs:element name="ldflags"   type="LinkerFlagsType" /&gt;
+      &lt;!-- C-Compiler command-line --&gt;
+      &lt;xs:element name="cflags"    type="ToolOptionType" /&gt;
+      &lt;!-- C++ Compiler command-line --&gt;
+      &lt;xs:element name="cxxflags"  type="ToolOptionType" /&gt;
+      &lt;!-- Assembler command-line --&gt;
+      &lt;xs:element name="asflags"   type="ToolOptionType" /&gt;
+    &lt;/xs:choice&gt;
+    &lt;!-- Board Vendor --&gt;
+    &lt;xs:attribute name="Bvendor"  type="xs:string"   use="optional" /&gt;
+    &lt;!-- Board Name --&gt;
+    &lt;xs:attribute name="Bname"    type="xs:string"   use="optional" /&gt;
+    &lt;!-- Board Version --&gt;
+    &lt;xs:attribute name="Bversion" type="xs:string"   use="optional" /&gt;
+    &lt;!-- Device Vendor --&gt;
+    &lt;xs:attribute name="Dvendor"  type="xs:string"   use="optional" /&gt;
+    &lt;!-- Device Name --&gt;
+    &lt;xs:attribute name="Dname"    type="xs:string"   use="optional" /&gt;
+    &lt;!-- Processor Instance Name --&gt;
+    &lt;xs:attribute name="Pname"    type="xs:string"   use="optional" /&gt;
+    &lt;!-- FPU used in target build --&gt;
+    &lt;xs:attribute name="Dfpu"     type="DfpuEnum"    use="optional" /&gt;
+    &lt;!-- Endianess used in target build --&gt;
+    &lt;xs:attribute name="Dendian"  type="DendianEnum" use="optional" /&gt;
+    &lt;!-- MPU used in target build --&gt;
+    &lt;xs:attribute name="Dmpu"     type="DmpuEnum"    use="optional" /&gt;
+    &lt;xs:attribute name="Ddsp"     type="DdspEnum"    use="optional" /&gt;
+    &lt;xs:attribute name="Dmve"     type="DmveEnum"    use="optional" /&gt;
+    &lt;xs:attribute name="Dtz"      type="DtzEnum"     use="optional" /&gt;
+    &lt;xs:attribute name="Dsecure"  type="DsecureEnum" use="optional" /&gt;
+  &lt;/xs:complexType&gt;
+
+  &lt;!-- Build settings for the project, setting RTE filter options --&gt;
+  &lt;xs:complexType name="OutputType"&gt;
+    &lt;!-- Project output file name --&gt;
+    &lt;xs:attribute name="name"  type="xs:string"          use="required" /&gt;
+    &lt;xs:attribute name="obj"   type="xs:string"          use="optional" /&gt;
+    &lt;xs:attribute name="list"  type="xs:string"          use="optional" /&gt;
+    &lt;xs:attribute name="type"  type="CompilerOutputType" use="required" /&gt;
+  &lt;/xs:complexType&gt;
+
+  &lt;xs:complexType name="LinkerFlagsType"&gt;
+    &lt;xs:attribute name="compiler"  type="CompilerEnumType" use="required"/&gt;
+    &lt;xs:attribute name="file"      type="xs:string"/&gt;
+    &lt;xs:attribute name="add"       type="xs:string"/&gt;
+    &lt;xs:attribute name="remove"    type="xs:string"/&gt;
+  &lt;/xs:complexType&gt;
+
+  &lt;xs:complexType name="ToolOptionType"&gt;
+    &lt;xs:attribute name="compiler"  type="CompilerEnumType" use="required"/&gt;
+    &lt;xs:attribute name="add"    type="xs:string" /&gt;
+    &lt;xs:attribute name="remove" type="xs:string" /&gt;
+  &lt;/xs:complexType&gt;
+
+  &lt;xs:complexType name="UsedType"&gt;
+    &lt;xs:attribute name="file"      type="xs:string" /&gt;
+    &lt;xs:attribute name="path"      type="xs:string" /&gt;
+    &lt;xs:attribute name="timestamp" type="xs:dateTime" /&gt;
+  &lt;/xs:complexType&gt;
+
+  &lt;!-- Group section contains a list of files and (sub-)groups --&gt;
+  &lt;xs:complexType name="GroupType"&gt;
+    &lt;xs:choice maxOccurs="unbounded"&gt;
+      &lt;xs:element name="cflags"    type="ToolOptionType" /&gt;
+      &lt;xs:element name="cxxflags"  type="ToolOptionType" /&gt;
+      &lt;xs:element name="asflags"   type="ToolOptionType" /&gt;
+      &lt;xs:element name="file"      type="FileType" /&gt;
+      &lt;xs:element name="group"     type="GroupType" /&gt;
+    &lt;/xs:choice&gt;
+    &lt;xs:attribute name="name" use="required" /&gt;
+    &lt;!-- layer reference --&gt;
+    &lt;xs:attribute name="layer" type="RestrictedString" use="optional" /&gt;
+  &lt;/xs:complexType&gt;
+
+  &lt;!-- file type definition --&gt;
+  &lt;xs:complexType name="FileType"&gt;
+    &lt;xs:choice minOccurs="0"&gt;
+      &lt;xs:element name="cflags"   type="ToolOptionType" /&gt;
+      &lt;xs:element name="cxxflags" type="ToolOptionType" /&gt;
+      &lt;xs:element name="asflags"  type="ToolOptionType" /&gt;
+    &lt;/xs:choice&gt;
+    &lt;!-- path + filename + extension --&gt;
+    &lt;xs:attribute name="name"     type="xs:string"        use="required" /&gt;
+    &lt;!-- file item category: source, header, include path, etc.  --&gt;
+    &lt;xs:attribute name="category" type="FileCategoryType" use="required" /&gt;
+    &lt;!-- for category="header" path explicitly specifies the include path added to the commandline.--&gt;
+    &lt;!-- Ignored for all other categories --&gt;
+    &lt;xs:attribute name="path"     type="xs:string"        use="optional" /&gt;
+    &lt;!-- path(s) to find source files for a library, paths are delimited with semicolon (;) --&gt;
+    &lt;xs:attribute name="src"      type="xs:string"        use="optional" /&gt;
+    &lt;!-- reference to layer --&gt;
+    &lt;xs:attribute name="layer"    type="RestrictedString"        use="optional" /&gt;
+  &lt;/xs:complexType&gt;
+
+  &lt;!-- Files section within the project section --&gt;
+  &lt;xs:complexType name="FilesType"&gt;
+    &lt;xs:choice maxOccurs="unbounded"&gt;
+      &lt;!-- C-Compiler command-line --&gt;
+      &lt;xs:element name="cflags"    type="ToolOptionType" /&gt;
+      &lt;!-- C++ Compiler command-line --&gt;
+      &lt;xs:element name="cxxflags"  type="ToolOptionType" /&gt;
+      &lt;!-- Assembler command-line --&gt;
+      &lt;xs:element name="asflags"   type="ToolOptionType" /&gt;
+      &lt;xs:element name="file" type="FileType" /&gt;
+      &lt;xs:element name="group" type="GroupType" /&gt;
+    &lt;/xs:choice&gt;
+  &lt;/xs:complexType&gt;
+
+  &lt;!-- Component selection section --&gt;
+  &lt;xs:complexType name="ComponentsType"&gt;
+    &lt;xs:sequence&gt;
+      &lt;xs:element name="component" maxOccurs="unbounded"&gt;
+        &lt;xs:complexType&gt;
+          &lt;xs:choice minOccurs="0" maxOccurs="unbounded"&gt;
+            &lt;!-- all config files --&gt;
+            &lt;xs:element name="file"&gt;
+              &lt;xs:complexType&gt;
+                &lt;!-- file item category: source, header, include path, etc.  --&gt;
+                &lt;xs:attribute name="category"  type="FileCategoryType"     use="required" /&gt;
+                &lt;!-- file item action attribute : config (copy to project, template, interface)  --&gt;
+                &lt;xs:attribute name="attr"      type="FileAttributeType"    use="optional" /&gt;
+                &lt;!-- path + filename + extension --&gt;
+                &lt;xs:attribute name="name"      type="xs:string"            use="required" /&gt;
+                &lt;!-- configuration file version: to be used by RTE to see whether the file requires updating or not --&gt;
+                &lt;xs:attribute name="version"   type="ComponentVersionType" use="required" /&gt;
+              &lt;/xs:complexType&gt;
+            &lt;/xs:element&gt;
+            &lt;xs:element name="cflags"   type="ToolOptionType" minOccurs="0"/&gt;
+            &lt;xs:element name="cxxflags" type="ToolOptionType" minOccurs="0"/&gt;
+            &lt;xs:element name="asflags"  type="ToolOptionType" minOccurs="0"/&gt;
+          &lt;/xs:choice&gt;
+          &lt;xs:attribute name="Cvendor"     type="xs:string"            use="optional" /&gt;
+          &lt;xs:attribute name="Cbundle"     type="xs:string"            use="optional" /&gt;
+          &lt;xs:attribute name="Cclass"      type="xs:string"            use="required" /&gt;
+          &lt;xs:attribute name="Cgroup"      type="xs:string"            use="required" /&gt;
+          &lt;xs:attribute name="Csub"        type="xs:string"            use="optional" /&gt;
+          &lt;xs:attribute name="Cvariant"    type="xs:string"            use="optional" /&gt;
+          &lt;xs:attribute name="Cversion"    type="ComponentVersionType" use="optional" /&gt;
+          &lt;xs:attribute name="Capiversion" type="ComponentVersionType" use="optional" /&gt;
+          &lt;xs:attribute name="instances"   type="InstancesType"        use="optional" default="1"/&gt;
+          &lt;xs:attribute name="layer"       type="RestrictedString"     use="optional" /&gt;
+        &lt;/xs:complexType&gt;
+      &lt;/xs:element&gt;
+    &lt;/xs:sequence&gt;
+  &lt;/xs:complexType&gt;
+
+  &lt;!-- Creation info --&gt;
+  &lt;xs:complexType name="CreationInfoType"&gt;
+    &lt;xs:sequence&gt;
+      &lt;xs:element name="used" type="UsedType" minOccurs="0"/&gt;
+    &lt;/xs:sequence&gt;
+    &lt;xs:attribute name="tool"        type="xs:string"       use="required" /&gt;
+    &lt;!-- format: YYYY-MM-DDThh:mm:ss[+|-hh:mm] timezone offset --&gt;
+    &lt;xs:attribute name="timestamp"   type="xs:dateTime"     use="required" /&gt;
+  &lt;/xs:complexType&gt;
+
+  &lt;!-- repository types --&gt;
+  &lt;xs:simpleType name="RepositoryTypeEnum"&gt;
+    &lt;xs:restriction base="xs:string"&gt;
+      &lt;xs:enumeration value="git"/&gt;
+      &lt;xs:enumeration value="svn"/&gt;
+      &lt;xs:enumeration value="other"/&gt;
+    &lt;/xs:restriction&gt;
+  &lt;/xs:simpleType&gt;
+
+  &lt;!-- URL type (optionally describes public repository) --&gt;
+  &lt;xs:complexType name="UrlType"&gt;
+    &lt;xs:simpleContent&gt;
+      &lt;xs:extension base="xs:anyURI"&gt;
+        &lt;xs:attribute name="repoType"     type="RepositoryTypeEnum" use="optional" /&gt;
+        &lt;xs:attribute name="repoTag"      type="xs:string"          use="optional" /&gt;
+      &lt;/xs:extension&gt;
+    &lt;/xs:simpleContent&gt;
+  &lt;/xs:complexType&gt;
+
+  &lt;!-- Project/Layer Info --&gt;
+  &lt;xs:complexType name="InfoType"&gt;
+    &lt;xs:all&gt;
+      &lt;!-- use filename as 'name' --&gt;
+      &lt;xs:element name="description" type="xs:string" minOccurs="1" /&gt;
+      &lt;xs:element name="url"         type="UrlType"   minOccurs="0" /&gt;
+      &lt;xs:element name="keywords"    type="xs:string" minOccurs="0" /&gt;
+      &lt;xs:element name="category"    type="xs:string" minOccurs="0" /&gt;
+      &lt;!-- SPDX license ID: https://spdx.org/licenses/ --&gt;
+      &lt;xs:element name="license"     type="xs:string" minOccurs="0" /&gt;
+    &lt;/xs:all&gt;
+    &lt;!-- 'true' if file is a layer description. Default 'false' --&gt;
+    &lt;xs:attribute name="isLayer"      type="xs:boolean"         use="optional" default="false"/&gt;
+  &lt;/xs:complexType&gt;
+
+  &lt;!-- Board Info --&gt;
+  &lt;xs:complexType name="BoardInfoType"&gt;
+    &lt;xs:simpleContent&gt;
+      &lt;xs:extension base="xs:string"&gt;
+        &lt;xs:attribute name="vendor"    type="xs:string"  use="required" /&gt;
+        &lt;xs:attribute name="name"      type="xs:string"  use="required" /&gt;
+        &lt;xs:attribute name="url"       type="xs:anyURI"  use="optional" /&gt;
+        &lt;xs:attribute name="revision"  type="xs:string"  use="optional" /&gt;
+      &lt;/xs:extension&gt;
+    &lt;/xs:simpleContent&gt;
+  &lt;/xs:complexType&gt;
+
+  &lt;!-- package description root point --&gt;
+  &lt;xs:element name="cprj" nillable="true"&gt;
+    &lt;xs:complexType&gt;
+      &lt;xs:all&gt;
+        &lt;!-- project info --&gt;
+        &lt;xs:element name="info"           type="InfoType"         minOccurs="1" /&gt;
+        &lt;!-- board info --&gt;
+        &lt;xs:element name="board"          type="BoardInfoType"    minOccurs="0" /&gt;
+        &lt;!-- tool info --&gt;
+        &lt;xs:element name="created"        type="CreationInfoType" minOccurs="0" /&gt;
+        &lt;!-- optional: project layers --&gt;
+        &lt;xs:element name="layers"         type="LayersType"       minOccurs="0" /&gt;
+        &lt;!-- used CMSIS-Packs --&gt;
+        &lt;xs:element name="packages"       type="PackagesType"     minOccurs="1" /&gt;
+        &lt;!-- supported compilers including version --&gt;
+        &lt;xs:element name="compilers"      type="CompilersType"    minOccurs="0" /&gt;
+        &lt;!-- project build target settings --&gt;
+        &lt;xs:element name="target"         type="TargetType"       minOccurs="0" /&gt;
+        &lt;!-- components used by project --&gt;
+        &lt;xs:element name="components"     type="ComponentsType"   minOccurs="1" /&gt;
+        &lt;!-- project modules/source files not contained in components --&gt;
+        &lt;xs:element name="files"          type="FilesType"        minOccurs="0"/&gt;
+      &lt;/xs:all&gt;
+      &lt;!-- schema version used by writer --&gt;
+      &lt;xs:attribute name="schemaVersion"  type="SchemaVersionType" use="required" /&gt;
+    &lt;/xs:complexType&gt;
+  &lt;/xs:element&gt;
+&lt;/xs:schema&gt;
+</pre> </div></div><!-- contents -->
+</div><!-- doc-content -->
+<!-- start footer part -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="navelem"><a class="el" href="cprjFormat_pg.html">Project Description (*.cprj) Format</a></li>
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:55 for CMSIS-Build Version 0.9.0 (beta) by Arm Ltd. All rights reserved.
+	<!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 
+	-->
+	</li>
+  </ul>
+</div>
+</body>
+</html>

docs/Build/html/search/all_3.js

@@ -1,4 +1,5 @@
 var searchData=
 [
-  ['project_20description_20_28_2a_2ecprj_29_20format',['Project Description (*.cprj) Format',['../cprjFormat_pg.html',1,'']]]
+  ['project_20description_20_28_2a_2ecprj_29_20format',['Project Description (*.cprj) Format',['../cprjFormat_pg.html',1,'']]],
+  ['project_20description_20schema',['Project Description Schema',['../projectDescriptionSchema.html',1,'cprjFormat_pg']]]
 ];

docs/Build/html/search/pages_3.js

@@ -1,4 +1,5 @@
 var searchData=
 [
-  ['project_20description_20_28_2a_2ecprj_29_20format',['Project Description (*.cprj) Format',['../cprjFormat_pg.html',1,'']]]
+  ['project_20description_20_28_2a_2ecprj_29_20format',['Project Description (*.cprj) Format',['../cprjFormat_pg.html',1,'']]],
+  ['project_20description_20schema',['Project Description Schema',['../projectDescriptionSchema.html',1,'cprjFormat_pg']]]
 ];

docs/Build/html/search/pages_6.js

@@ -1,4 +0,0 @@
-var searchData=
-[
-  ['todo_20list',['Todo List',['../todo.html',1,'']]]
-];

docs/Build/html/search/search.js

@@ -7,8 +7,8 @@
 
 var indexSectionsWithContent =
 {
-  0: "cmoprst",
-  1: "cmoprst"
+  0: "cmoprs",
+  1: "cmoprs"
 };
 
 var indexSectionNames =

docs/Core/html/annotated.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
-   &#160;<span id="projectnumber">Version 5.3.0</span>
+   &#160;<span id="projectnumber">Version 5.4.0</span>
    </div>
    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
   </td>
@@ -129,11 +129,12 @@ $(document).ready(function(){initNavTree('annotated.html','');});
 <tr id="row_7_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structITM__Type.html" target="_self">ITM_Type</a></td><td class="desc">Structure type to access the Instrumentation Trace Macrocell Register (ITM) </td></tr>
 <tr id="row_8_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structMPU__Type.html" target="_self">MPU_Type</a></td><td class="desc">Structure type to access the Memory Protection Unit (MPU) </td></tr>
 <tr id="row_9_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structNVIC__Type.html" target="_self">NVIC_Type</a></td><td class="desc">Structure type to access the Nested Vectored Interrupt Controller (NVIC) </td></tr>
-<tr id="row_10_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structSCB__Type.html" target="_self">SCB_Type</a></td><td class="desc">Structure type to access the System Control Block (SCB) </td></tr>
-<tr id="row_11_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structSCnSCB__Type.html" target="_self">SCnSCB_Type</a></td><td class="desc">Structure type to access the System Control and ID Register not in the SCB </td></tr>
-<tr id="row_12_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structSysTick__Type.html" target="_self">SysTick_Type</a></td><td class="desc">Structure type to access the System Timer (SysTick) </td></tr>
-<tr id="row_13_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structTPI__Type.html" target="_self">TPI_Type</a></td><td class="desc">Structure type to access the Trace Port Interface Register (TPI) </td></tr>
-<tr id="row_14_" class="even"><td class="entry"><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="unionxPSR__Type.html" target="_self">xPSR_Type</a></td><td class="desc">Union type to access the Special-Purpose Program Status Registers (xPSR) </td></tr>
+<tr id="row_10_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structPMU__Type.html" target="_self">PMU_Type</a></td><td class="desc">Structure type to access the Performance Monitoring Unit (PMU) </td></tr>
+<tr id="row_11_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structSCB__Type.html" target="_self">SCB_Type</a></td><td class="desc">Structure type to access the System Control Block (SCB) </td></tr>
+<tr id="row_12_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structSCnSCB__Type.html" target="_self">SCnSCB_Type</a></td><td class="desc">Structure type to access the System Control and ID Register not in the SCB </td></tr>
+<tr id="row_13_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structSysTick__Type.html" target="_self">SysTick_Type</a></td><td class="desc">Structure type to access the System Timer (SysTick) </td></tr>
+<tr id="row_14_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structTPI__Type.html" target="_self">TPI_Type</a></td><td class="desc">Structure type to access the Trace Port Interface Register (TPI) </td></tr>
+<tr id="row_15_"><td class="entry"><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="unionxPSR__Type.html" target="_self">xPSR_Type</a></td><td class="desc">Union type to access the Special-Purpose Program Status Registers (xPSR) </td></tr>
 </table>
 </div><!-- directory -->
 </div><!-- contents -->
@@ -141,7 +142,7 @@ $(document).ready(function(){initNavTree('annotated.html','');});
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:26 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Core/html/annotated.js

@@ -10,6 +10,7 @@ var annotated =
     [ "ITM_Type", "structITM__Type.html", "structITM__Type" ],
     [ "MPU_Type", "structMPU__Type.html", "structMPU__Type" ],
     [ "NVIC_Type", "structNVIC__Type.html", "structNVIC__Type" ],
+    [ "PMU_Type", "structPMU__Type.html", "structPMU__Type" ],
     [ "SCB_Type", "structSCB__Type.html", "structSCB__Type" ],
     [ "SCnSCB_Type", "structSCnSCB__Type.html", "structSCnSCB__Type" ],
     [ "SysTick_Type", "structSysTick__Type.html", "structSysTick__Type" ],

docs/Core/html/classes.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
-   &#160;<span id="projectnumber">Version 5.3.0</span>
+   &#160;<span id="projectnumber">Version 5.4.0</span>
    </div>
    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
   </td>
@@ -117,34 +117,38 @@ $(document).ready(function(){initNavTree('classes.html','');});
 <div class="title">Data Structure Index</div>  </div>
 </div><!--header-->
 <div class="contents">
-<div class="qindex"><a class="qindex" href="#letter_A">A</a>&#160;|&#160;<a class="qindex" href="#letter_C">C</a>&#160;|&#160;<a class="qindex" href="#letter_D">D</a>&#160;|&#160;<a class="qindex" href="#letter_F">F</a>&#160;|&#160;<a class="qindex" href="#letter_I">I</a>&#160;|&#160;<a class="qindex" href="#letter_M">M</a>&#160;|&#160;<a class="qindex" href="#letter_N">N</a>&#160;|&#160;<a class="qindex" href="#letter_S">S</a>&#160;|&#160;<a class="qindex" href="#letter_T">T</a>&#160;|&#160;<a class="qindex" href="#letter_X">X</a></div>
+<div class="qindex"><a class="qindex" href="#letter_A">A</a>&#160;|&#160;<a class="qindex" href="#letter_C">C</a>&#160;|&#160;<a class="qindex" href="#letter_D">D</a>&#160;|&#160;<a class="qindex" href="#letter_F">F</a>&#160;|&#160;<a class="qindex" href="#letter_I">I</a>&#160;|&#160;<a class="qindex" href="#letter_M">M</a>&#160;|&#160;<a class="qindex" href="#letter_N">N</a>&#160;|&#160;<a class="qindex" href="#letter_P">P</a>&#160;|&#160;<a class="qindex" href="#letter_S">S</a>&#160;|&#160;<a class="qindex" href="#letter_T">T</a>&#160;|&#160;<a class="qindex" href="#letter_X">X</a></div>
 <table style="margin: 10px; white-space: nowrap;" align="center" width="95%" border="0" cellspacing="0" cellpadding="0">
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+<tr><td valign="top"><a class="el" href="structARM__MPU__Region__t.html">ARM_MPU_Region_t</a>&#160;&#160;&#160;</td><td rowspan="2" valign="bottom"><a name="letter_F"></a><table border="0" cellspacing="0" cellpadding="0"><tr><td><div class="ah">&#160;&#160;F&#160;&#160;</div></td></tr></table>
+</td><td valign="top"><a class="el" href="structMPU__Type.html">MPU_Type</a>&#160;&#160;&#160;</td><td valign="top"><a class="el" href="structSCnSCB__Type.html">SCnSCB_Type</a>&#160;&#160;&#160;</td><td></td></tr>
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+<tr><td valign="top"><a class="el" href="structFPU__Type.html">FPU_Type</a>&#160;&#160;&#160;</td><td rowspan="2" valign="bottom"><a name="letter_T"></a><table border="0" cellspacing="0" cellpadding="0"><tr><td><div class="ah">&#160;&#160;T&#160;&#160;</div></td></tr></table>
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+</td><td valign="top"><a class="el" href="structNVIC__Type.html">NVIC_Type</a>&#160;&#160;&#160;</td><td></td></tr>
+<tr><td valign="top"><a class="el" href="structCoreDebug__Type.html">CoreDebug_Type</a>&#160;&#160;&#160;</td><td rowspan="2" valign="bottom"><a name="letter_P"></a><table border="0" cellspacing="0" cellpadding="0"><tr><td><div class="ah">&#160;&#160;P&#160;&#160;</div></td></tr></table>
+</td><td valign="top"><a class="el" href="structTPI__Type.html">TPI_Type</a>&#160;&#160;&#160;</td><td></td></tr>
+<tr><td></td><td valign="top"><a class="el" href="unionIPSR__Type.html">IPSR_Type</a>&#160;&#160;&#160;</td><td></td><td></td></tr>
+<tr><td></td><td></td><td valign="top"><a class="el" href="structPMU__Type.html">PMU_Type</a>&#160;&#160;&#160;</td><td></td><td></td></tr>
 <tr><td></td><td></td><td></td><td></td><td></td></tr>
 </table>
-<div class="qindex"><a class="qindex" href="#letter_A">A</a>&#160;|&#160;<a class="qindex" href="#letter_C">C</a>&#160;|&#160;<a class="qindex" href="#letter_D">D</a>&#160;|&#160;<a class="qindex" href="#letter_F">F</a>&#160;|&#160;<a class="qindex" href="#letter_I">I</a>&#160;|&#160;<a class="qindex" href="#letter_M">M</a>&#160;|&#160;<a class="qindex" href="#letter_N">N</a>&#160;|&#160;<a class="qindex" href="#letter_S">S</a>&#160;|&#160;<a class="qindex" href="#letter_T">T</a>&#160;|&#160;<a class="qindex" href="#letter_X">X</a></div>
+<div class="qindex"><a class="qindex" href="#letter_A">A</a>&#160;|&#160;<a class="qindex" href="#letter_C">C</a>&#160;|&#160;<a class="qindex" href="#letter_D">D</a>&#160;|&#160;<a class="qindex" href="#letter_F">F</a>&#160;|&#160;<a class="qindex" href="#letter_I">I</a>&#160;|&#160;<a class="qindex" href="#letter_M">M</a>&#160;|&#160;<a class="qindex" href="#letter_N">N</a>&#160;|&#160;<a class="qindex" href="#letter_P">P</a>&#160;|&#160;<a class="qindex" href="#letter_S">S</a>&#160;|&#160;<a class="qindex" href="#letter_T">T</a>&#160;|&#160;<a class="qindex" href="#letter_X">X</a></div>
 </div><!-- contents -->
 </div><!-- doc-content -->
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:26 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Core/html/coreMISRA_Exceptions_pg.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
-   &#160;<span id="projectnumber">Version 5.3.0</span>
+   &#160;<span id="projectnumber">Version 5.4.0</span>
    </div>
    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
   </td>
@@ -117,7 +117,7 @@ $(document).ready(function(){initNavTree('coreMISRA_Exceptions_pg.html','');});
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:25 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:07 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Core/html/core_revisionHistory.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
-   &#160;<span id="projectnumber">Version 5.3.0</span>
+   &#160;<span id="projectnumber">Version 5.4.0</span>
    </div>
    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
   </td>
@@ -115,6 +115,8 @@ $(document).ready(function(){initNavTree('core_revisionHistory.html','');});
 <tr>
 <th>Version </th><th>Description  </th></tr>
 <tr>
+<td>V5.4.0 </td><td>Added: Cortex-M55 cpu support Enhanced: MVE support for Armv8.1-MML Fixed: Device config define checks Added: L1 Cache functions for Armv7-M and later   </td></tr>
+<tr>
 <td>V5.3.0 </td><td>Added: Provisions for compiler-independent C startup code.   </td></tr>
 <tr>
 <td>V5.2.1 </td><td>Fixed: Compilation issue in cmsis_armclang_ltm.h introduced in 5.2.0   </td></tr>
@@ -152,7 +154,7 @@ $(document).ready(function(){initNavTree('core_revisionHistory.html','');});
  Replaced: macro __SAU_PRESENT with __SAU_REGION_PRESENT. <br/>
  Reworked: SAU register and functions. <br/>
  Added: macro <a class="el" href="group__compiler__conntrol__gr.html#ga0c58caa5a273e2c21924509a45f8b849">__ALIGNED</a>. <br/>
- Updated: function <a class="el" href="group__Icache__functions__m7.html#gaf9e7c6c8e16ada1f95e5bf5a03505b68">SCB_EnableICache</a>. <br/>
+ Updated: function <a class="el" href="group__Icache__functions__m7.html#ga980ffe52af778f2535ccc52f25f9a7de">SCB_EnableICache</a>. <br/>
  Added: cmsis_compiler.h with compiler specific CMSIS macros, functions, instructions. <br/>
  Added: macro <a class="el" href="group__compiler__conntrol__gr.html#gabe8996d3d985ee1529475443cc635bf1">__PACKED</a>. <br/>
  Updated: compiler specific include files. <br/>
@@ -178,7 +180,7 @@ Beta 2 </td><td>Changed: ARMv8M SAU regions to 8. <br/>
  Changed: moved function <a class="el" href="group__sau__trustzone__functions.html#ga6093bc5939ea8924fbcfdffb8f0553f1">TZ_SAU_Setup</a> to file partition_&lt;device&gt;.h. <br/>
  Changed: license under Apache-2.0. <br/>
  Added: check if macro is defined before use. <br/>
- Corrected: function <a class="el" href="group__Dcache__functions__m7.html#ga6468170f90d270caab8116e7a4f0b5fe">SCB_DisableDCache</a>. <br/>
+ Corrected: function <a class="el" href="group__Dcache__functions__m7.html#gafe64b44d1a61483a947e44a77a9d3287">SCB_DisableDCache</a>. <br/>
  Corrected: macros <a class="el" href="group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e">_VAL2FLD</a>, <a class="el" href="group__peripheral__gr.html#ga139b6e261c981f014f386927ca4a8444">_FLD2VAL</a>. <br/>
  Added: NVIC function virtualization with macros <a class="el" href="group__NVIC__gr.html#gadc48b4ed09386aab48fa6b9c96d9034c">CMSIS_NVIC_VIRTUAL</a> and <a class="el" href="group__NVIC__gr.html#gad01d3aa220b50ef141b06c93888b268d">CMSIS_VECTAB_VIRTUAL</a>.   </td></tr>
 <tr>
@@ -205,7 +207,7 @@ Beta 1 </td><td>Renamed: cmsis_armcc_V6.h to cmsis_armclang.h.<br/>
  Corrected: intrinsic functions <a class="el" href="group__intrinsic__CPU__gr.html#gacb2a8ca6eae1ba4b31161578b720c199">__DSB</a>, <a class="el" href="group__intrinsic__CPU__gr.html#gab1c9b393641dc2d397b3408fdbe72b96">__DMB</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga93c09b4709394d81977300d5f84950e5">__ISB</a>. <br/>
  Corrected: register definitions for ITCMCR register. <br/>
  Corrected: register definitions for <a class="el" href="unionCONTROL__Type.html">CONTROL_Type</a> register. <br/>
- Added: functions <a class="el" href="group__fpu__functions.html#ga6bcad99ce80a0e7e4ddc6f2379081756">SCB_GetFPUType</a>, <a class="el" href="group__Dcache__functions__m7.html#ga503ef7ef58c0773defd15a82f6336c09">SCB_InvalidateDCache_by_Addr</a> to core_cm7.h. <br/>
+ Added: functions <a class="el" href="group__fpu__functions.html#ga6bcad99ce80a0e7e4ddc6f2379081756">SCB_GetFPUType</a>, <a class="el" href="group__Dcache__functions__m7.html#ga2a6f3706a3ffae4c9349c454d407f762">SCB_InvalidateDCache_by_Addr</a> to core_cm7.h. <br/>
  Added: register definitions for <a class="el" href="unionAPSR__Type.html">APSR_Type</a>, <a class="el" href="unionIPSR__Type.html">IPSR_Type</a>, <a class="el" href="unionxPSR__Type.html">xPSR_Type</a> register. <br/>
  Added: <a class="el" href="group__Core__Register__gr.html#ga62fa63d39cf22df348857d5f44ab64d9">__set_BASEPRI_MAX</a> function to core_cmFunc.h. <br/>
  Added: intrinsic functions <a class="el" href="group__intrinsic__CPU__gr.html#gad6f9f297f6b91a995ee199fbc796b863">__RBIT</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga90884c591ac5d73d6069334eba9d6c02">__CLZ</a> for Cortex-M0/CortexM0+. <br/>
@@ -268,7 +270,7 @@ Beta 1 </td><td>Renamed: cmsis_armcc_V6.h to cmsis_armclang.h.<br/>
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:25 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:07 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Core/html/deprecated.html

@@ -32,7 +32,7 @@
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   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
-   &#160;<span id="projectnumber">Version 5.3.0</span>
+   &#160;<span id="projectnumber">Version 5.4.0</span>
    </div>
    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
   </td>
@@ -122,7 +122,7 @@ $(document).ready(function(){initNavTree('deprecated.html','');});
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:25 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:07 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Core/html/device_h_pg.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
-   &#160;<span id="projectnumber">Version 5.3.0</span>
+   &#160;<span id="projectnumber">Version 5.4.0</span>
    </div>
    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
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@@ -148,234 +148,290 @@ Interrupt Number Definition</h1>
 </div><!-- fragment --><h1><a class="anchor" id="core_config_sect"></a>
 Configuration of the Processor and Core Peripherals</h1>
 <p>The <a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> configures the Cortex-M or SecurCore processor and the core peripherals with <em>#defines</em> that are set prior to including the file <b>core_&lt;cpu&gt;.h</b>.</p>
-<p>The following tables list the <em>#defines</em> along with the possible values for each processor core. If these <em>#defines</em> are missing default values are used.</p>
-<p><b>core_cm0.h</b> </p>
+<p>The following tables list the <em>#defines</em> along with the possible values for each processor core. If these <em>#defines</em> are missing default values are used. <b>core_cm0.h</b> </p>
 <table  class="cmtable">
 <tr>
 <th>#define </th><th>Value Range </th><th>Default </th><th>Description  </th></tr>
 <tr>
-<td>__CM0_REV </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number)  </td></tr>
+<td><a class="el" href="group__device__config.html#ga905517438930a3f13cbc632e52990534">__CM0_REV</a> </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number)  </td></tr>
 <tr>
-<td>__NVIC_PRIO_BITS </td><td>2 </td><td>2 </td><td>Number of priority bits implemented in the NVIC (device specific)  </td></tr>
+<td><a class="el" href="group__device__config.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a> </td><td>2 </td><td>2 </td><td>Number of priority bits implemented in the NVIC (device specific)  </td></tr>
 <tr>
-<td>__Vendor_SysTickConfig </td><td>0 .. 1 </td><td>0 </td><td>If this define is set to 1, then the default <b>SysTick_Config</b> function is excluded. In this case, the file <em><b>device.h</b></em> must contain a vendor specific implementation of this function.  </td></tr>
+<td><a class="el" href="group__device__config.html#gab58771b4ec03f9bdddc84770f7c95c68">__Vendor_SysTickConfig</a> </td><td>0 .. 1 </td><td>0 </td><td>Vendor defined <b>SysTick_Config</b> function.  </td></tr>
 </table>
 <p><b>core_cm0plus.h</b> </p>
 <table  class="cmtable">
 <tr>
 <th>#define </th><th>Value Range </th><th>Default </th><th>Description  </th></tr>
 <tr>
-<td>__CM0PLUS_REV </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number)  </td></tr>
+<td><a class="el" href="group__device__config.html#ga2b7180ed347a0e902c5765deb46e650e">__CM0PLUS_REV</a> </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number)  </td></tr>
+<tr>
+<td><a class="el" href="group__device__config.html#gaddbae1a1b57539f398eb5546a17de8f6">__VTOR_PRESENT</a> </td><td>0 .. 1 </td><td>0 </td><td>Defines if a VTOR register is present or not  </td></tr>
 <tr>
-<td>__NVIC_PRIO_BITS </td><td>2 </td><td>2 </td><td>Number of priority bits implemented in the NVIC (device specific)  </td></tr>
+<td><a class="el" href="group__device__config.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a> </td><td>2 </td><td>2 </td><td>Number of priority bits implemented in the NVIC (device specific)  </td></tr>
 <tr>
-<td>__Vendor_SysTickConfig </td><td>0 .. 1 </td><td>0 </td><td>If this define is set to 1, then the default <b>SysTick_Config</b> function is excluded. In this case, the file <em><b>device.h</b></em> must contain a vendor specific implementation of this function.  </td></tr>
+<td><a class="el" href="group__device__config.html#gab58771b4ec03f9bdddc84770f7c95c68">__Vendor_SysTickConfig</a> </td><td>0 .. 1 </td><td>0 </td><td>Vendor defined <b>SysTick_Config</b> function.  </td></tr>
 </table>
 <p><b>core_cm3.h</b> </p>
 <table  class="cmtable">
 <tr>
 <th>#define </th><th>Value Range </th><th>Default </th><th>Description  </th></tr>
 <tr>
-<td>__CM3_REV </td><td>0x0101 | 0x0200 </td><td>0x0200 </td><td>Core revision number ([15:8] revision number, [7:0] patch number)  </td></tr>
+<td><a class="el" href="group__device__config.html#gac6a3f185c4640e06443c18b3c8d93f53">__CM3_REV</a> </td><td>0x0101 | 0x0200 </td><td>0x0200 </td><td>Core revision number ([15:8] revision number, [7:0] patch number)  </td></tr>
+<tr>
+<td><a class="el" href="group__device__config.html#gaddbae1a1b57539f398eb5546a17de8f6">__VTOR_PRESENT</a> </td><td>0 .. 1 </td><td>1 </td><td>Defines if a VTOR register is present or not  </td></tr>
 <tr>
-<td>__NVIC_PRIO_BITS </td><td>2 .. 8 </td><td>4 </td><td>Number of priority bits implemented in the NVIC (device specific)  </td></tr>
+<td><a class="el" href="group__device__config.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a> </td><td>2 .. 8 </td><td>4 </td><td>Number of priority bits implemented in the NVIC (device specific)  </td></tr>
 <tr>
-<td>__MPU_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not  </td></tr>
+<td><a class="el" href="group__device__config.html#ga4127d1b31aaf336fab3d7329d117f448">__MPU_PRESENT</a> </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not  </td></tr>
 <tr>
-<td>__Vendor_SysTickConfig </td><td>0 .. 1 </td><td>0 </td><td>If this define is set to 1, then the default <b>SysTick_Config</b> function is excluded. In this case, the file <em><b>device.h</b></em> must contain a vendor specific implementation of this function.  </td></tr>
+<td><a class="el" href="group__device__config.html#gab58771b4ec03f9bdddc84770f7c95c68">__Vendor_SysTickConfig</a> </td><td>0 .. 1 </td><td>0 </td><td>Vendor defined <b>SysTick_Config</b> function.  </td></tr>
 </table>
 <p><b>core_cm4.h</b> </p>
 <table  class="cmtable">
 <tr>
 <th>#define </th><th>Value Range </th><th>Default </th><th>Description  </th></tr>
 <tr>
-<td>__CM4_REV </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number)  </td></tr>
+<td><a class="el" href="group__device__config.html#ga45a97e4bb8b6ce7c334acc5f45ace3ba">__CM4_REV</a> </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number)  </td></tr>
 <tr>
-<td>__NVIC_PRIO_BITS </td><td>2 .. 8 </td><td>4 </td><td>Number of priority bits implemented in the NVIC (device specific)  </td></tr>
+<td><a class="el" href="group__device__config.html#gaddbae1a1b57539f398eb5546a17de8f6">__VTOR_PRESENT</a> </td><td>0 .. 1 </td><td>1 </td><td>Defines if a VTOR register is present or not  </td></tr>
 <tr>
-<td>__MPU_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not  </td></tr>
+<td><a class="el" href="group__device__config.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a> </td><td>2 .. 8 </td><td>4 </td><td>Number of priority bits implemented in the NVIC (device specific)  </td></tr>
 <tr>
-<td>__FPU_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a FPU is present or not  </td></tr>
+<td><a class="el" href="group__device__config.html#ga4127d1b31aaf336fab3d7329d117f448">__MPU_PRESENT</a> </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not  </td></tr>
 <tr>
-<td>__Vendor_SysTickConfig </td><td>0 .. 1 </td><td>0 </td><td>If this define is set to 1, then the default <b>SysTick_Config</b> function is excluded. In this case, the file <em><b>device.h</b></em> must contain a vendor specific implementation of this function.  </td></tr>
+<td><a class="el" href="group__device__config.html#gac1ba8a48ca926bddc88be9bfd7d42641">__FPU_PRESENT</a> </td><td>0 .. 1 </td><td>0 </td><td>Defines if a FPU is present or not  </td></tr>
+<tr>
+<td><a class="el" href="group__device__config.html#gab58771b4ec03f9bdddc84770f7c95c68">__Vendor_SysTickConfig</a> </td><td>0 .. 1 </td><td>0 </td><td>Vendor defined <b>SysTick_Config</b> function.  </td></tr>
 </table>
 <p><b>core_cm7.h</b> </p>
 <table  class="cmtable">
 <tr>
 <th>#define </th><th>Value Range </th><th>Default </th><th>Description  </th></tr>
 <tr>
-<td>__CM7_REV </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number)  </td></tr>
+<td><a class="el" href="group__device__config.html#ga8eb40c0d30a09a0ae388e56b21d8f22c">__CM7_REV</a> </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number)  </td></tr>
 <tr>
-<td>__MPU_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not  </td></tr>
+<td><a class="el" href="group__device__config.html#ga4127d1b31aaf336fab3d7329d117f448">__MPU_PRESENT</a> </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not  </td></tr>
 <tr>
-<td>__NVIC_PRIO_BITS </td><td>2 .. 8 </td><td>4 </td><td>Number of priority bits implemented in the NVIC (device specific)  </td></tr>
+<td><a class="el" href="group__device__config.html#gaddbae1a1b57539f398eb5546a17de8f6">__VTOR_PRESENT</a> </td><td>0 .. 1 </td><td>1 </td><td>Defines if a VTOR register is present or not  </td></tr>
 <tr>
-<td>__Vendor_SysTickConfig </td><td>0 .. 1 </td><td>0 </td><td>If this define is set to 1, then the default <b>SysTick_Config</b> function is excluded. In this case, the file <em><b>device.h</b></em> must contain a vendor specific implementation of this function.  </td></tr>
+<td><a class="el" href="group__device__config.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a> </td><td>2 .. 8 </td><td>4 </td><td>Number of priority bits implemented in the NVIC (device specific)  </td></tr>
 <tr>
-<td>__FPU_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a FPU is present or not. See <b>__FPU_DP</b> description below.  </td></tr>
+<td><a class="el" href="group__device__config.html#gab58771b4ec03f9bdddc84770f7c95c68">__Vendor_SysTickConfig</a> </td><td>0 .. 1 </td><td>0 </td><td>If this define is set to 1, then the default <b>SysTick_Config</b> function is excluded. In this case, the file <em><b>device.h</b></em> must contain a vendor specific implementation of this function.   </td></tr>
 <tr>
-<td>__FPU_DP </td><td>0 .. 1 </td><td>0 </td><td>The combination of the defines <b>__FPU_PRESENT</b> and <b>__FPU_DP</b> determine the whether the FPU is with single or double precision as shown in the table below. <br/>
-<br/>
- <table  class="cmtable">
-<tr bgcolor="cyan">
-<td><b>__FPU_PRESENT</b> </td><td><b>__FPU_DP</b> </td><td><b>Description</b>  </td></tr>
+<td><a class="el" href="group__device__config.html#gac1ba8a48ca926bddc88be9bfd7d42641">__FPU_PRESENT</a> </td><td>0 .. 1 </td><td>0 </td><td>Defines if a FPU is present or not.  </td></tr>
 <tr>
-<td align="center">0 </td><td align="center"><em>ignored</em> </td><td>Processor has no FPU. The value set for <b>__FPU_DP</b> has no influence.   </td></tr>
+<td><a class="el" href="group__device__config.html#ga2a528de57b6217f9fc9d4487d0db6328">__FPU_DP</a> </td><td>0 .. 1 </td><td>0 </td><td>The combination of the defines <a class="el" href="group__device__config.html#gac1ba8a48ca926bddc88be9bfd7d42641">__FPU_PRESENT</a> and <a class="el" href="group__device__config.html#ga2a528de57b6217f9fc9d4487d0db6328">__FPU_DP</a> determine whether the FPU is with single or double precision.   </td></tr>
 <tr>
-<td align="center">1 </td><td align="center">0 </td><td>Processor with FPU with single precision. The file <b>ARMCM7_SP.h</b> has preconfigured settings for this combination.  </td></tr>
+<td><a class="el" href="group__device__config.html#ga3580fa1aeb7c2ed580904f8f70f8a919">__ICACHE_PRESENT</a> </td><td>0 .. 1 </td><td>1 </td><td>Instruction Chache present or not  </td></tr>
 <tr>
-<td align="center">1 </td><td align="center">1 </td><td>Processor with FPU with double precision. The file <b>ARMCM7_DP.h</b> has preconfigured settings for this combination.  </td></tr>
-</table>
-</td></tr>
+<td><a class="el" href="group__device__config.html#ga11d3ac679daeb58d0cec0a4e6ca59010">__DCACHE_PRESENT</a> </td><td>0 .. 1 </td><td>1 </td><td>Data Chache present or not  </td></tr>
 <tr>
-<td>__ICACHE_PRESENT </td><td>0 .. 1 </td><td>1 </td><td>Instruction Chache present or not  </td></tr>
-<tr>
-<td>__DCACHE_PRESENT </td><td>0 .. 1 </td><td>1 </td><td>Data Chache present or not  </td></tr>
-<tr>
-<td>__DTCM_PRESENT </td><td>0 .. 1 </td><td>1 </td><td>Data Tightly Coupled Memory is present or not  </td></tr>
+<td><a class="el" href="group__device__config.html#gacbb998663708df6626abb09378303019">__DTCM_PRESENT</a> </td><td>0 .. 1 </td><td>1 </td><td>Data Tightly Coupled Memory is present or not  </td></tr>
 </table>
 <p><b>core_sc000.h</b> </p>
 <table  class="cmtable">
 <tr>
 <th>#define </th><th>Value Range </th><th>Default </th><th>Description  </th></tr>
 <tr>
-<td>__SC000_REV </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number)  </td></tr>
+<td><a class="el" href="group__device__config.html#gaf293b060f9c15592d18e6b0b977194bf">__SC000_REV</a> </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number)  </td></tr>
 <tr>
-<td>__NVIC_PRIO_BITS </td><td>2 </td><td>2 </td><td>Number of priority bits implemented in the NVIC (device specific)  </td></tr>
+<td><a class="el" href="group__device__config.html#gaddbae1a1b57539f398eb5546a17de8f6">__VTOR_PRESENT</a> </td><td>0 .. 1 </td><td>0 </td><td>Defines if a VTOR register is present or not  </td></tr>
 <tr>
-<td>__MPU_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not  </td></tr>
+<td><a class="el" href="group__device__config.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a> </td><td>2 </td><td>2 </td><td>Number of priority bits implemented in the NVIC (device specific)  </td></tr>
 <tr>
-<td>__Vendor_SysTickConfig </td><td>0 .. 1 </td><td>0 </td><td>If this define is set to 1, then the default <b>SysTick_Config</b> function is excluded. In this case, the file <em><b>device.h</b></em> must contain a vendor specific implementation of this function.  </td></tr>
+<td><a class="el" href="group__device__config.html#ga4127d1b31aaf336fab3d7329d117f448">__MPU_PRESENT</a> </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not  </td></tr>
+<tr>
+<td><a class="el" href="group__device__config.html#gab58771b4ec03f9bdddc84770f7c95c68">__Vendor_SysTickConfig</a> </td><td>0 .. 1 </td><td>0 </td><td>Vendor defined <b>SysTick_Config</b> function.  </td></tr>
 </table>
 <p><b>core_sc300.h</b> </p>
 <table  class="cmtable">
 <tr>
 <th>#define </th><th>Value Range </th><th>Default </th><th>Description  </th></tr>
 <tr>
-<td>__SC300_REV </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number)  </td></tr>
+<td><a class="el" href="group__device__config.html#ga3029728b4fc64727b43bcfd853a7180b">__SC300_REV</a> </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number)  </td></tr>
+<tr>
+<td><a class="el" href="group__device__config.html#gaddbae1a1b57539f398eb5546a17de8f6">__VTOR_PRESENT</a> </td><td>0 .. 1 </td><td>1 </td><td>Defines if a VTOR register is present or not  </td></tr>
 <tr>
-<td>__NVIC_PRIO_BITS </td><td>2 .. 8 </td><td>4 </td><td>Number of priority bits implemented in the NVIC (device specific)  </td></tr>
+<td><a class="el" href="group__device__config.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a> </td><td>2 .. 8 </td><td>4 </td><td>Number of priority bits implemented in the NVIC (device specific)  </td></tr>
 <tr>
-<td>__MPU_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not  </td></tr>
+<td><a class="el" href="group__device__config.html#ga4127d1b31aaf336fab3d7329d117f448">__MPU_PRESENT</a> </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not  </td></tr>
 <tr>
-<td>__Vendor_SysTickConfig </td><td>0 .. 1 </td><td>0 </td><td>If this define is set to 1, then the default <b>SysTick_Config</b> function is excluded. In this case, the file <em><b>device.h</b></em> must contain a vendor specific implementation of this function.  </td></tr>
+<td><a class="el" href="group__device__config.html#gab58771b4ec03f9bdddc84770f7c95c68">__Vendor_SysTickConfig</a> </td><td>0 .. 1 </td><td>0 </td><td>Vendor defined <b>SysTick_Config</b> function.  </td></tr>
 </table>
 <p><b>core_CM23.h</b> or <b>core_ARMv8MBL.h</b> </p>
 <table  class="cmtable">
 <tr>
 <th>#define </th><th>Value Range </th><th>Default </th><th>Description  </th></tr>
 <tr>
-<td>__ARMv8MBL_REV </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number)  </td></tr>
+<td><a class="el" href="group__device__config.html#ga645c9be694a2d5b5a5b772a0102c727a">__ARMv8MBL_REV</a> or <a class="el" href="group__device__config.html#ga0f6c2b504ee424a7895fd7a420acdd0e">__CM23_REV</a> </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number)  </td></tr>
 <tr>
-<td>__MPU_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not  </td></tr>
+<td><a class="el" href="group__device__config.html#ga4127d1b31aaf336fab3d7329d117f448">__MPU_PRESENT</a> </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not  </td></tr>
 <tr>
-<td>__SAUREGION_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if SAU regions are present or not  </td></tr>
+<td><a class="el" href="group__device__config.html#gadae9d54c744e525135b097c618bae3c4">__SAUREGION_PRESENT</a> </td><td>0 .. 1 </td><td>0 </td><td>Defines if SAU regions are present or not  </td></tr>
 <tr>
-<td>__VTOR_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a VTOR register is present or not  </td></tr>
+<td><a class="el" href="group__device__config.html#gaddbae1a1b57539f398eb5546a17de8f6">__VTOR_PRESENT</a> </td><td>0 .. 1 </td><td>0 </td><td>Defines if a VTOR register is present or not  </td></tr>
 <tr>
-<td>__NVIC_PRIO_BITS </td><td>2 </td><td>2 </td><td>Number of priority bits implemented in the NVIC (device specific)  </td></tr>
+<td><a class="el" href="group__device__config.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a> </td><td>2 </td><td>2 </td><td>Number of priority bits implemented in the NVIC (device specific)  </td></tr>
 <tr>
-<td>__Vendor_SysTickConfig </td><td>0 .. 1 </td><td>0 </td><td>If this define is set to 1, then the default <b>SysTick_Config</b> function is excluded. In this case, the file <em><b>device.h</b></em> must contain a vendor specific implementation of this function.  </td></tr>
+<td><a class="el" href="group__device__config.html#gab58771b4ec03f9bdddc84770f7c95c68">__Vendor_SysTickConfig</a> </td><td>0 .. 1 </td><td>0 </td><td>Vendor defined <b>SysTick_Config</b> function.  </td></tr>
 </table>
 <p><b>core_CM33.h</b> or <b>core_cm35p.h</b> or <b>core_ARMv8MML.h</b> </p>
 <table  class="cmtable">
 <tr>
 <th>#define </th><th>Value Range </th><th>Default </th><th>Description  </th></tr>
 <tr>
-<td>__ARMv8MML_REV </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number)  </td></tr>
+<td><a class="el" href="group__device__config.html#gadb7d425f5ad0389b0eb1c6a69f8eb214">__ARMv8MML_REV</a> or <a class="el" href="group__device__config.html#ga178e7a57b608f3e20d1c0cf18a2c2ac3">__CM33_REV</a> or <a class="el" href="group__device__config.html#gadd339c07b13a763dda6e83f4c05122f6">__CM35P_REV</a> </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number)  </td></tr>
 <tr>
-<td>__MPU_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not  </td></tr>
+<td><a class="el" href="group__device__config.html#ga4127d1b31aaf336fab3d7329d117f448">__MPU_PRESENT</a> </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not  </td></tr>
 <tr>
-<td>__SAUREGION_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if SAU regions are present or not  </td></tr>
+<td><a class="el" href="group__device__config.html#gadae9d54c744e525135b097c618bae3c4">__SAUREGION_PRESENT</a> </td><td>0 .. 1 </td><td>0 </td><td>Defines if SAU regions are present or not  </td></tr>
 <tr>
-<td>__FPU_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a FPU is present or not  </td></tr>
+<td><a class="el" href="group__device__config.html#gac1ba8a48ca926bddc88be9bfd7d42641">__FPU_PRESENT</a> </td><td>0 .. 1 </td><td>0 </td><td>Defines if a FPU is present or not  </td></tr>
 <tr>
-<td>__NVIC_PRIO_BITS </td><td>2 .. 8 </td><td>3 </td><td>Number of priority bits implemented in the NVIC (device specific)  </td></tr>
+<td><a class="el" href="group__device__config.html#gaddbae1a1b57539f398eb5546a17de8f6">__VTOR_PRESENT</a> </td><td>0 .. 1 </td><td>1 </td><td>Defines if a VTOR register is present or not  </td></tr>
 <tr>
-<td>__Vendor_SysTickConfig </td><td>0 .. 1 </td><td>0 </td><td>If this define is set to 1, then the default <b>SysTick_Config</b> function is excluded. In this case, the file <em><b>device.h</b></em> must contain a vendor specific implementation of this function.  </td></tr>
+<td><a class="el" href="group__device__config.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a> </td><td>2 .. 8 </td><td>3 </td><td>Number of priority bits implemented in the NVIC (device specific)  </td></tr>
+<tr>
+<td><a class="el" href="group__device__config.html#gab58771b4ec03f9bdddc84770f7c95c68">__Vendor_SysTickConfig</a> </td><td>0 .. 1 </td><td>0 </td><td>Vendor defined <b>SysTick_Config</b> function.  </td></tr>
+</table>
+<p><b>core_CM55.h</b> or <b>core_ARMv81MML.h</b> </p>
+<table  class="cmtable">
+<tr>
+<th>#define </th><th>Value Range </th><th>Default </th><th>Description  </th></tr>
+<tr>
+<td><a class="el" href="group__device__config.html#ga4dd7b69d473733e59cd99fc786174cd3">__ARMv81MML_REV</a> or <a class="el" href="group__device__config.html#gaea2d16e963063038cde86cee33c4ef37">__CM55_REV</a> </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number)  </td></tr>
+<tr>
+<td><a class="el" href="group__device__config.html#ga4127d1b31aaf336fab3d7329d117f448">__MPU_PRESENT</a> </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not  </td></tr>
+<tr>
+<td><a class="el" href="group__device__config.html#gadae9d54c744e525135b097c618bae3c4">__SAUREGION_PRESENT</a> </td><td>0 .. 1 </td><td>0 </td><td>Defines if SAU regions are present or not  </td></tr>
+<tr>
+<td><a class="el" href="group__device__config.html#gac1ba8a48ca926bddc88be9bfd7d42641">__FPU_PRESENT</a> </td><td>0 .. 1 </td><td>0 </td><td>Defines if a FPU is present or not  </td></tr>
+<tr>
+<td><a class="el" href="group__device__config.html#ga2a528de57b6217f9fc9d4487d0db6328">__FPU_DP</a> </td><td>0 .. 1 </td><td>0 </td><td>The combination of the defines <a class="el" href="group__device__config.html#gac1ba8a48ca926bddc88be9bfd7d42641">__FPU_PRESENT</a> and <a class="el" href="group__device__config.html#ga2a528de57b6217f9fc9d4487d0db6328">__FPU_DP</a> determine whether the FPU is with single or double precision.   </td></tr>
+<tr>
+<td><a class="el" href="group__device__config.html#ga3580fa1aeb7c2ed580904f8f70f8a919">__ICACHE_PRESENT</a> </td><td>0 .. 1 </td><td>1 </td><td>Instruction Chache present or not  </td></tr>
+<tr>
+<td><a class="el" href="group__device__config.html#ga11d3ac679daeb58d0cec0a4e6ca59010">__DCACHE_PRESENT</a> </td><td>0 .. 1 </td><td>1 </td><td>Data Chache present or not  </td></tr>
+<tr>
+<td><a class="el" href="group__device__config.html#gaddbae1a1b57539f398eb5546a17de8f6">__VTOR_PRESENT</a> </td><td>0 .. 1 </td><td>1 </td><td>Defines if a VTOR register is present or not  </td></tr>
+<tr>
+<td><a class="el" href="group__device__config.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a> </td><td>2 .. 8 </td><td>3 </td><td>Number of priority bits implemented in the NVIC (device specific)  </td></tr>
+<tr>
+<td><a class="el" href="group__device__config.html#gab58771b4ec03f9bdddc84770f7c95c68">__Vendor_SysTickConfig</a> </td><td>0 .. 1 </td><td>0 </td><td>Vendor defined <b>SysTick_Config</b> function.  </td></tr>
 </table>
 <p><b>Example</b> </p>
 <p>The following code exemplifies the configuration of the Cortex-M4 Processor and Core Peripherals.</p>
-<div class="fragment"><div class="line"><span class="preprocessor">#define __CM4_REV                 0x0001    </span><span class="comment">/* Core revision r0p1                                 */</span><span class="preprocessor"></span></div>
-<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __MPU_PRESENT             1         </span><span class="comment">/* MPU present or not                                 */</span><span class="preprocessor"></span></div>
-<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __NVIC_PRIO_BITS          3         </span><span class="comment">/* Number of Bits used for Priority Levels            */</span><span class="preprocessor"></span></div>
-<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __Vendor_SysTickConfig    0         </span><span class="comment">/* Set to 1 if different SysTick Config is used       */</span><span class="preprocessor"></span></div>
-<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __FPU_PRESENT             1         </span><span class="comment">/* FPU present or not                                 */</span><span class="preprocessor"></span></div>
+<div class="fragment"><div class="line"><span class="preprocessor">#define __CM4_REV                 0x0001U   </span><span class="comment">/* Core revision r0p1                                 */</span><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __MPU_PRESENT             1U        </span><span class="comment">/* MPU present or not                                 */</span><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __VTOR_PRESENT            1U        </span><span class="comment">/* VTOR present */</span><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __NVIC_PRIO_BITS          3U        </span><span class="comment">/* Number of Bits used for Priority Levels            */</span><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __Vendor_SysTickConfig    0U        </span><span class="comment">/* Set to 1 if different SysTick Config is used       */</span><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __FPU_PRESENT             1U        </span><span class="comment">/* FPU present or not                                 */</span><span class="preprocessor"></span></div>
 <div class="line"><span class="preprocessor"></span>.</div>
 <div class="line">.</div>
 <div class="line"><span class="preprocessor">#include &lt;core_cm4.h&gt;</span>                       <span class="comment">/* Cortex-M4 processor and core peripherals           */</span></div>
+<div class="line"><span class="preprocessor">#include &quot;system_&lt;device&gt;</span>.h<span class="stringliteral">&quot;                /* Device System Header                               */</span></div>
 </div><!-- fragment --><h1><a class="anchor" id="core_version_sect"></a>
 CMSIS Version and Processor Information</h1>
 <p>Defines in the core_<em>cpu</em>.h file identify the version of the CMSIS-Core (Cortex-M) and the processor used. The following shows the defines in the various core_<em>cpu</em>.h files that may be used in the <a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> to verify a minimum version or ensure that the right processor core is used.</p>
 <p><b>core_cm0.h</b> </p>
-<div class="fragment"><div class="line"><span class="preprocessor">#define __CM0_CMSIS_VERSION_MAIN  (5U)                                 </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div>
-<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM0_CMSIS_VERSION_SUB   (0U)                                 </span><span class="comment">/* [15:0]  CMSIS HAL sub version */</span><span class="preprocessor"></span></div>
+<div class="fragment"><div class="line"><span class="preprocessor">#define __CM0_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                         </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM0_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                          </span><span class="comment">/* [15:0]  CMSIS HAL sub version */</span><span class="preprocessor"></span></div>
 <div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN &lt;&lt; 16U) | \</span></div>
-<div class="line"><span class="preprocessor">                                    __CM0_CMSIS_VERSION_SUB          ) </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div>
-<div class="line"><span class="preprocessor"></span> </div>
-<div class="line"><span class="preprocessor">#define __CORTEX_M                (0U)                                 </span><span class="comment">/* Cortex-M Core */</span><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor">                                    __CM0_CMSIS_VERSION_SUB          )              </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor">#define __CORTEX_M                (0U)                                              </span><span class="comment">/* Cortex-M Core */</span><span class="preprocessor"></span></div>
 </div><!-- fragment --><p><b>core_cm0plus.h</b> </p>
-<div class="fragment"><div class="line"><span class="preprocessor">#define __CM0PLUS_CMSIS_VERSION_MAIN  (5U)                                  </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div>
-<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM0PLUS_CMSIS_VERSION_SUB   (0U)                                  </span><span class="comment">/* [15:0]  CMSIS HAL sub version */</span><span class="preprocessor"></span></div>
+<div class="fragment"><div class="line"><span class="preprocessor">#define __CM0PLUS_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                     </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM0PLUS_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                      </span><span class="comment">/* [15:0]  CMSIS HAL sub version */</span><span class="preprocessor"></span></div>
 <div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM0PLUS_CMSIS_VERSION       ((__CM0P_CMSIS_VERSION_MAIN &lt;&lt; 16U) | \</span></div>
-<div class="line"><span class="preprocessor">                                        __CM0P_CMSIS_VERSION_SUB          ) </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div>
-<div class="line"><span class="preprocessor"></span> </div>
-<div class="line"><span class="preprocessor">#define __CORTEX_M                    (0U)                                  </span><span class="comment">/* Cortex-M Core */</span><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor">                                        __CM0P_CMSIS_VERSION_SUB          )         </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor">#define __CORTEX_M                    (0U)                                          </span><span class="comment">/* Cortex-M Core */</span><span class="preprocessor"></span></div>
 </div><!-- fragment --><p><b>core_cm1.h</b> </p>
-<div class="fragment"><div class="line"><span class="preprocessor">#define __CM1_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              </span></div>
-<div class="line"><span class="preprocessor">#define __CM1_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               </span></div>
+<div class="fragment"><div class="line"><span class="preprocessor">#define __CM1_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                         </span></div>
+<div class="line"><span class="preprocessor">#define __CM1_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                          </span></div>
 <div class="line"><span class="preprocessor">#define __CM1_CMSIS_VERSION       ((__CM1_CMSIS_VERSION_MAIN &lt;&lt; 16U) | \</span></div>
-<div class="line"><span class="preprocessor">                                    __CM1_CMSIS_VERSION_SUB           )  </span></div>
-<div class="line"><span class="preprocessor">#define __CORTEX_M                (1U)                                   </span></div>
+<div class="line"><span class="preprocessor">                                    __CM1_CMSIS_VERSION_SUB           )             </span></div>
+<div class="line"><span class="preprocessor">#define __CORTEX_M                (1U)                                              </span></div>
 </div><!-- fragment --><p><b>core_cm3.h</b> </p>
-<div class="fragment"><div class="line"><span class="preprocessor">#define __CM3_CMSIS_VERSION_MAIN  (5U)                                 </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div>
-<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM3_CMSIS_VERSION_SUB   (0U)                                 </span><span class="comment">/* [15:0]  CMSIS HAL sub version */</span><span class="preprocessor"></span></div>
+<div class="fragment"><div class="line"><span class="preprocessor">#define __CM3_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                         </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM3_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                          </span><span class="comment">/* [15:0]  CMSIS HAL sub version */</span><span class="preprocessor"></span></div>
 <div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN &lt;&lt; 16U) | \</span></div>
-<div class="line"><span class="preprocessor">                                    __CM3_CMSIS_VERSION_SUB          ) </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div>
-<div class="line"><span class="preprocessor"></span> </div>
-<div class="line"><span class="preprocessor">#define __CORTEX_M                (3U)                                 </span><span class="comment">/* Cortex-M Core */</span><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor">                                    __CM3_CMSIS_VERSION_SUB          )              </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor">#define __CORTEX_M                (3U)                                              </span><span class="comment">/* Cortex-M Core */</span><span class="preprocessor"></span></div>
 </div><!-- fragment --><p><b>core_cm4.h</b> </p>
-<div class="fragment"><div class="line"><span class="preprocessor">#define __CM4_CMSIS_VERSION_MAIN  (5U)                                 </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div>
-<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM4_CMSIS_VERSION_SUB   (0U)                                 </span><span class="comment">/* [15:0]  CMSIS HAL sub version */</span><span class="preprocessor"></span></div>
+<div class="fragment"><div class="line"><span class="preprocessor">#define __CM4_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                         </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM4_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                          </span><span class="comment">/* [15:0]  CMSIS HAL sub version */</span><span class="preprocessor"></span></div>
 <div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN &lt;&lt; 16U) | \</span></div>
-<div class="line"><span class="preprocessor">                                    __CM4_CMSIS_VERSION_SUB          ) </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div>
-<div class="line"><span class="preprocessor"></span> </div>
-<div class="line"><span class="preprocessor">#define __CORTEX_M                (4U)                                 </span><span class="comment">/* Cortex-M Core */</span><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor">                                    __CM4_CMSIS_VERSION_SUB          )              </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor">#define __CORTEX_M                (4U)                                              </span><span class="comment">/* Cortex-M Core */</span><span class="preprocessor"></span></div>
 </div><!-- fragment --><p><b>core_cm7.h</b> </p>
-<div class="fragment"><div class="line"><span class="preprocessor">#define __CM7_CMSIS_VERSION_MAIN  (5U)                                 </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div>
-<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM7_CMSIS_VERSION_SUB   (0U)                                 </span><span class="comment">/* [15:0]  CMSIS HAL sub version */</span><span class="preprocessor"></span></div>
+<div class="fragment"><div class="line"><span class="preprocessor">#define __CM7_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN                          </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM7_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                          </span><span class="comment">/* [15:0]  CMSIS HAL sub version */</span><span class="preprocessor"></span></div>
 <div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN &lt;&lt; 16U) | \</span></div>
-<div class="line"><span class="preprocessor">                                    __CM7_CMSIS_VERSION_SUB          ) </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div>
-<div class="line"><span class="preprocessor"></span> </div>
-<div class="line"><span class="preprocessor">#define __CORTEX_M                (7U)                                 </span><span class="comment">/* Cortex-M Core */</span><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor">                                    __CM7_CMSIS_VERSION_SUB          )              </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor">#define __CORTEX_M                (7U)                                              </span><span class="comment">/* Cortex-M Core */</span><span class="preprocessor"></span></div>
+</div><!-- fragment --><p><b>core_cm23.h</b> </p>
+<div class="fragment"><div class="line"><span class="preprocessor">#define __CM23_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                        </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM23_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                         </span><span class="comment">/* [15:0]  CMSIS HAL sub version */</span><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM23_CMSIS_VERSION       ((__CM23_CMSIS_VERSION_MAIN &lt;&lt; 16U) | \</span></div>
+<div class="line"><span class="preprocessor">                                     __CM23_CMSIS_VERSION_SUB          )            </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor">#define __CORTEX_M                (23U)                                             </span><span class="comment">/* Cortex-M Core */</span><span class="preprocessor"></span></div>
+</div><!-- fragment --><p><b>core_cm33.h</b> </p>
+<div class="fragment"><div class="line"><span class="preprocessor">#define __CM33_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                        </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM33_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                         </span><span class="comment">/* [15:0]  CMSIS HAL sub version */</span><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM33_CMSIS_VERSION       ((__CM33_CMSIS_VERSION_MAIN &lt;&lt; 16U) | \</span></div>
+<div class="line"><span class="preprocessor">                                     __CM33_CMSIS_VERSION_SUB          )            </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor">#define __CORTEX_M                (33U)                                             </span><span class="comment">/* Cortex-M Core */</span><span class="preprocessor"></span></div>
+</div><!-- fragment --><p><b>core_cm55.h</b> </p>
+<div class="fragment"><div class="line"><span class="preprocessor">#define __CM55_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                        </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM55_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                         </span><span class="comment">/* [15:0]  CMSIS HAL sub version */</span><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM55_CMSIS_VERSION       ((__CM55_CMSIS_VERSION_MAIN &lt;&lt; 16U) | \</span></div>
+<div class="line"><span class="preprocessor">                                     __CM55_CMSIS_VERSION_SUB          )            </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor">#define __CORTEX_M                (7U)                                              </span><span class="comment">/* Cortex-M Core */</span><span class="preprocessor"></span></div>
 </div><!-- fragment --><p><b>core_sc000.h</b> </p>
-<div class="fragment"><div class="line"><span class="preprocessor">#define __SC000_CMSIS_VERSION_MAIN  (5U)                                   </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div>
-<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __SC000_CMSIS_VERSION_SUB   (0U)                                   </span><span class="comment">/* [15:0]  CMSIS HAL sub version */</span><span class="preprocessor"></span></div>
+<div class="fragment"><div class="line"><span class="preprocessor">#define __SC000_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                       </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __SC000_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                        </span><span class="comment">/* [15:0]  CMSIS HAL sub version */</span><span class="preprocessor"></span></div>
 <div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN &lt;&lt; 16U) | \</span></div>
-<div class="line"><span class="preprocessor">                                      __SC000_CMSIS_VERSION_SUB          ) </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor">                                      __SC000_CMSIS_VERSION_SUB          )          </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div>
 <div class="line"><span class="preprocessor"></span></div>
-<div class="line"><span class="preprocessor">#define __CORTEX_SC                 (0U)                                   </span><span class="comment">/* Cortex secure core */</span><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor">#define __CORTEX_SC                 (0U)                                            </span><span class="comment">/* Cortex secure core */</span><span class="preprocessor"></span></div>
 </div><!-- fragment --><p><b>core_sc300.h</b> </p>
-<div class="fragment"><div class="line"><span class="preprocessor">#define __SC300_CMSIS_VERSION_MAIN  (5U)                                   </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div>
-<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __SC300_CMSIS_VERSION_SUB   (0U)                                   </span><span class="comment">/* [15:0]  CMSIS HAL sub version */</span><span class="preprocessor"></span></div>
+<div class="fragment"><div class="line"><span class="preprocessor">#define __SC300_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                       </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __SC300_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                        </span><span class="comment">/* [15:0]  CMSIS HAL sub version */</span><span class="preprocessor"></span></div>
 <div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN &lt;&lt; 16U) | \</span></div>
-<div class="line"><span class="preprocessor">                                      __SC300_CMSIS_VERSION_SUB          ) </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor">                                      __SC300_CMSIS_VERSION_SUB          )          </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor">#define __CORTEX_SC                 (300U)                                          </span><span class="comment">/* Cortex secure core */</span><span class="preprocessor"></span></div>
+</div><!-- fragment --><p><b>core_cm35p.h</b> </p>
+<div class="fragment"><div class="line"><span class="preprocessor">#define __CM35P_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                       </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM35P_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                        </span><span class="comment">/* [15:0]  CMSIS HAL sub version */</span><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM35P_CMSIS_VERSION       ((__CM35P_CMSIS_VERSION_MAIN &lt;&lt; 16U) | \</span></div>
+<div class="line"><span class="preprocessor">                                      __CM35P_CMSIS_VERSION_SUB          )          </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div>
 <div class="line"><span class="preprocessor"></span></div>
-<div class="line"><span class="preprocessor">#define __CORTEX_SC                 (300U)                                 </span><span class="comment">/* Cortex secure core */</span><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor">#define __CORTEX_M                (35U)                                             </span><span class="comment">/* Cortex-M Core */</span><span class="preprocessor"></span></div>
 </div><!-- fragment --><p><b>core_ARMv8MBL.h</b> </p>
-<div class="fragment"><div class="line"><span class="preprocessor">#define __ARMv8MBL_CMSIS_VERSION_MAIN  (5U)                                       </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div>
-<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __ARMv8MBL_CMSIS_VERSION_SUB   (0U)                                       </span><span class="comment">/* [15:0]  CMSIS HAL sub version */</span><span class="preprocessor"></span></div>
+<div class="fragment"><div class="line"><span class="preprocessor">#define __ARMv8MBL_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                    </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __ARMv8MBL_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                     </span><span class="comment">/* [15:0]  CMSIS HAL sub version */</span><span class="preprocessor"></span></div>
 <div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __ARMv8MBL_CMSIS_VERSION       ((__ARMv8MBL_CMSIS_VERSION_MAIN &lt;&lt; 16U) | \</span></div>
-<div class="line"><span class="preprocessor">                                         __ARMv8MBL_CMSIS_VERSION_SUB           ) </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div>
-<div class="line"><span class="preprocessor"></span> </div>
-<div class="line"><span class="preprocessor">#define __CORTEX_M                     (tbd)                                      </span><span class="comment">/* Cortex secure core */</span><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor">                                         __ARMv8MBL_CMSIS_VERSION_SUB           )   </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor">#define __CORTEX_M                     (2U)                                         </span><span class="comment">/* Cortex secure core */</span><span class="preprocessor"></span></div>
 </div><!-- fragment --><p><b>core_ARMv8MML.h</b> </p>
-<div class="fragment"><div class="line"><span class="preprocessor">#define __ARMv8MML_CMSIS_VERSION_MAIN  (5U)                                       </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div>
-<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __ARMv8MML_CMSIS_VERSION_SUB   (0U)                                       </span><span class="comment">/* [15:0]  CMSIS HAL sub version */</span><span class="preprocessor"></span></div>
+<div class="fragment"><div class="line"><span class="preprocessor">#define __ARMv8MML_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                    </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __ARMv8MML_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                     </span><span class="comment">/* [15:0]  CMSIS HAL sub version */</span><span class="preprocessor"></span></div>
 <div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __ARMv8MML_CMSIS_VERSION       ((__ARMv8MML_CMSIS_VERSION_MAIN &lt;&lt; 16U) | \</span></div>
-<div class="line"><span class="preprocessor">                                         __ARMv8MML_CMSIS_VERSION_SUB           ) </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div>
-<div class="line"><span class="preprocessor"></span> </div>
-<div class="line"><span class="preprocessor">#define __CORTEX_M                     (tbd)                                      </span><span class="comment">/* Cortex secure core */</span><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor">                                         __ARMv8MML_CMSIS_VERSION_SUB           )   </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor"></span></div>
+<div class="line"><span class="preprocessor">#define __CORTEX_M                     (80U)                                        </span><span class="comment">/* Cortex secure core */</span><span class="preprocessor"></span></div>
 </div><!-- fragment --><h1><a class="anchor" id="device_access"></a>
 Device Peripheral Access Layer</h1>
 <p>The <a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> contains for each peripheral:</p>
@@ -649,7 +705,7 @@ typedef struct
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
     <li class="navelem"><a class="el" href="templates_pg.html">CMSIS-Core Device Templates</a></li>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:25 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:07 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Core/html/functions.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
-   &#160;<span id="projectnumber">Version 5.3.0</span>
+   &#160;<span id="projectnumber">Version 5.4.0</span>
    </div>
    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
   </td>
@@ -103,6 +103,7 @@ var searchBox = new SearchBox("searchBox", "search",false,'Search');
       <li><a href="#index_l"><span>l</span></a></li>
       <li><a href="#index_m"><span>m</span></a></li>
       <li><a href="#index_n"><span>n</span></a></li>
+      <li><a href="#index_o"><span>o</span></a></li>
       <li><a href="#index_p"><span>p</span></a></li>
       <li><a href="#index_q"><span>q</span></a></li>
       <li><a href="#index_r"><span>r</span></a></li>
@@ -172,6 +173,9 @@ $(document).ready(function(){initNavTree('functions.html','');});
 <li>AIRCR
 : <a class="el" href="structSCB__Type.html#ad3e5b8934c647eb1b7383c1894f01380">SCB_Type</a>
 </li>
+<li>AUTHSTATUS
+: <a class="el" href="structPMU__Type.html#a60a8296d51236329e79d1604080aa9c1">PMU_Type</a>
+</li>
 </ul>
 
 
@@ -196,6 +200,12 @@ $(document).ready(function(){initNavTree('functions.html','');});
 <li>CALIB
 : <a class="el" href="structSysTick__Type.html#afcadb0c6d35b21cdc0018658a13942de">SysTick_Type</a>
 </li>
+<li>CCFILTR
+: <a class="el" href="structPMU__Type.html#a61fea523ea0f4e9242101cb09fc6f6a8">PMU_Type</a>
+</li>
+<li>CCNTR
+: <a class="el" href="structPMU__Type.html#ada85996bd815d9eff9552794feec6d74">PMU_Type</a>
+</li>
 <li>CCR
 : <a class="el" href="structSCB__Type.html#a2d6653b0b70faac936046a02809b577f">SCB_Type</a>
 </li>
@@ -214,12 +224,30 @@ $(document).ready(function(){initNavTree('functions.html','');});
 <li>CID3
 : <a class="el" href="structITM__Type.html#a43451f43f514108d9eaed5b017f8d921">ITM_Type</a>
 </li>
+<li>CIDR0
+: <a class="el" href="structPMU__Type.html#a54117364a5e8d3af0cc45769bb9b11c7">PMU_Type</a>
+</li>
+<li>CIDR1
+: <a class="el" href="structPMU__Type.html#a0eded5a42f8b81a09df17ce0a9f90897">PMU_Type</a>
+</li>
+<li>CIDR2
+: <a class="el" href="structPMU__Type.html#a94fa4cd97b83324090d6e696f3568415">PMU_Type</a>
+</li>
+<li>CIDR3
+: <a class="el" href="structPMU__Type.html#aff7ed1b5979deb4fb0a536aa477c6830">PMU_Type</a>
+</li>
 <li>CLAIMCLR
 : <a class="el" href="structTPI__Type.html#a0e10e292cb019a832b03ddd055b2f6ac">TPI_Type</a>
 </li>
 <li>CLAIMSET
 : <a class="el" href="structTPI__Type.html#af8b7d15fa5252b733dd4b11fa1b5730a">TPI_Type</a>
 </li>
+<li>CNTENCLR
+: <a class="el" href="structPMU__Type.html#a3c24c882b1679390b1dd957dbd0f0bf6">PMU_Type</a>
+</li>
+<li>CNTENSET
+: <a class="el" href="structPMU__Type.html#a030ee86cd33b72a0c5e66fbaf418d1be">PMU_Type</a>
+</li>
 <li>COMP0
 : <a class="el" href="structDWT__Type.html#a61c2965af5bc0643f9af65620b0e67c9">DWT_Type</a>
 </li>
@@ -247,6 +275,7 @@ $(document).ready(function(){initNavTree('functions.html','');});
 <li>CTRL
 : <a class="el" href="structDWT__Type.html#add790c53410023b3b581919bb681fe2a">DWT_Type</a>
 , <a class="el" href="structMPU__Type.html#a769178ef949f0d5d8f18ddbd9e4e926f">MPU_Type</a>
+, <a class="el" href="structPMU__Type.html#aba9bddd6b49c88e38f4bb79d32002c3c">PMU_Type</a>
 , <a class="el" href="structSysTick__Type.html#a875e7afa5c4fd43997fb544a4ac6e37e">SysTick_Type</a>
 </li>
 <li>CYCCNT
@@ -267,12 +296,14 @@ $(document).ready(function(){initNavTree('functions.html','');});
 </li>
 <li>DEVARCH
 : <a class="el" href="structITM__Type.html#a2372a4ebb63e36d1eb3fcf83a74fd537">ITM_Type</a>
+, <a class="el" href="structPMU__Type.html#a439c7a309f02c41a6581d0819e896fdc">PMU_Type</a>
 </li>
 <li>DEVID
 : <a class="el" href="structTPI__Type.html#abc0ecda8a5446bc754080276bad77514">TPI_Type</a>
 </li>
 <li>DEVTYPE
-: <a class="el" href="structTPI__Type.html#ad98855854a719bbea33061e71529a472">TPI_Type</a>
+: <a class="el" href="structPMU__Type.html#aac8b7bca579afd4969d8bfffa61afbed">PMU_Type</a>
+, <a class="el" href="structTPI__Type.html#ad98855854a719bbea33061e71529a472">TPI_Type</a>
 </li>
 <li>DFR
 : <a class="el" href="structSCB__Type.html#a85dd6fe77aab17e7ea89a52c59da6004">SCB_Type</a>
@@ -287,6 +318,12 @@ $(document).ready(function(){initNavTree('functions.html','');});
 
 
 <h3><a class="anchor" id="index_e"></a>- e -</h3><ul>
+<li>EVCNTR
+: <a class="el" href="structPMU__Type.html#a08f877e8edcb1c19b81ebcf95f85e2f7">PMU_Type</a>
+</li>
+<li>EVTYPER
+: <a class="el" href="structPMU__Type.html#a27682a8d2fe09d2052a4295d5b4a243b">PMU_Type</a>
+</li>
 <li>EXCCNT
 : <a class="el" href="structDWT__Type.html#a9fe20c16c5167ca61486caf6832686d1">DWT_Type</a>
 </li>
@@ -365,6 +402,12 @@ $(document).ready(function(){initNavTree('functions.html','');});
 <li>IMCR
 : <a class="el" href="structITM__Type.html#ae2ce4d3a54df2fd11a197ccac4406cd0">ITM_Type</a>
 </li>
+<li>INTENCLR
+: <a class="el" href="structPMU__Type.html#aaff7d5f3246c641d1f503d74a5adb0ee">PMU_Type</a>
+</li>
+<li>INTENSET
+: <a class="el" href="structPMU__Type.html#a3f5a5872105d9056145e9095bc1c63ac">PMU_Type</a>
+</li>
 <li>IP
 : <a class="el" href="structNVIC__Type.html#a7ff7364a4260df67a2784811e8da4efd">NVIC_Type</a>
 </li>
@@ -457,6 +500,16 @@ $(document).ready(function(){initNavTree('functions.html','');});
 </ul>
 
 
+<h3><a class="anchor" id="index_o"></a>- o -</h3><ul>
+<li>OVSCLR
+: <a class="el" href="structPMU__Type.html#a2acdf96dc7f60ad5a384d1f47e0bb8e0">PMU_Type</a>
+</li>
+<li>OVSSET
+: <a class="el" href="structPMU__Type.html#a153e694a19f845e65a3d2abd4d64faa7">PMU_Type</a>
+</li>
+</ul>
+
+
 <h3><a class="anchor" id="index_p"></a>- p -</h3><ul>
 <li>PCSR
 : <a class="el" href="structDWT__Type.html#a6353ca1d1ad9bc1be05d3b5632960113">DWT_Type</a>
@@ -488,6 +541,21 @@ $(document).ready(function(){initNavTree('functions.html','');});
 <li>PID7
 : <a class="el" href="structITM__Type.html#a2bcec6803f28f30d5baf5e20e3517d3d">ITM_Type</a>
 </li>
+<li>PIDR0
+: <a class="el" href="structPMU__Type.html#afe7c3069b9a30d54e5e30166a2281bd7">PMU_Type</a>
+</li>
+<li>PIDR1
+: <a class="el" href="structPMU__Type.html#a8a764266e9b41e7c100a9853889d94ab">PMU_Type</a>
+</li>
+<li>PIDR2
+: <a class="el" href="structPMU__Type.html#a2f7053542f392f435ad51930d0504622">PMU_Type</a>
+</li>
+<li>PIDR3
+: <a class="el" href="structPMU__Type.html#a831a9b4e2e07eef0b93713beb26a6516">PMU_Type</a>
+</li>
+<li>PIDR4
+: <a class="el" href="structPMU__Type.html#abe4612a6387c5be0e56898bfa6b16902">PMU_Type</a>
+</li>
 <li>PORT
 : <a class="el" href="structITM__Type.html#af95bc1810f9ea802d628cb9dea81e02e">ITM_Type</a>
 </li>
@@ -598,6 +666,9 @@ $(document).ready(function(){initNavTree('functions.html','');});
 <li>STIR
 : <a class="el" href="structNVIC__Type.html#a37de89637466e007171c6b135299bc75">NVIC_Type</a>
 </li>
+<li>SWINC
+: <a class="el" href="structPMU__Type.html#a2add0abae68f27801299d6dd4bfcde66">PMU_Type</a>
+</li>
 </ul>
 
 
@@ -619,6 +690,7 @@ $(document).ready(function(){initNavTree('functions.html','');});
 </li>
 <li>TYPE
 : <a class="el" href="structMPU__Type.html#aba02af87f77577c725cf73879cabb609">MPU_Type</a>
+, <a class="el" href="structPMU__Type.html#a1f2e763ceeeff8ff15c0bd3520b683e8">PMU_Type</a>
 </li>
 </ul>
 
@@ -671,7 +743,7 @@ $(document).ready(function(){initNavTree('functions.html','');});
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:26 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Core/html/functions_vars.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
-   &#160;<span id="projectnumber">Version 5.3.0</span>
+   &#160;<span id="projectnumber">Version 5.4.0</span>
    </div>
    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
   </td>
@@ -103,6 +103,7 @@ var searchBox = new SearchBox("searchBox", "search",false,'Search');
       <li><a href="#index_l"><span>l</span></a></li>
       <li><a href="#index_m"><span>m</span></a></li>
       <li><a href="#index_n"><span>n</span></a></li>
+      <li><a href="#index_o"><span>o</span></a></li>
       <li><a href="#index_p"><span>p</span></a></li>
       <li><a href="#index_q"><span>q</span></a></li>
       <li><a href="#index_r"><span>r</span></a></li>
@@ -172,6 +173,9 @@ $(document).ready(function(){initNavTree('functions_vars.html','');});
 <li>AIRCR
 : <a class="el" href="structSCB__Type.html#ad3e5b8934c647eb1b7383c1894f01380">SCB_Type</a>
 </li>
+<li>AUTHSTATUS
+: <a class="el" href="structPMU__Type.html#a60a8296d51236329e79d1604080aa9c1">PMU_Type</a>
+</li>
 </ul>
 
 
@@ -196,6 +200,12 @@ $(document).ready(function(){initNavTree('functions_vars.html','');});
 <li>CALIB
 : <a class="el" href="structSysTick__Type.html#afcadb0c6d35b21cdc0018658a13942de">SysTick_Type</a>
 </li>
+<li>CCFILTR
+: <a class="el" href="structPMU__Type.html#a61fea523ea0f4e9242101cb09fc6f6a8">PMU_Type</a>
+</li>
+<li>CCNTR
+: <a class="el" href="structPMU__Type.html#ada85996bd815d9eff9552794feec6d74">PMU_Type</a>
+</li>
 <li>CCR
 : <a class="el" href="structSCB__Type.html#a2d6653b0b70faac936046a02809b577f">SCB_Type</a>
 </li>
@@ -214,12 +224,30 @@ $(document).ready(function(){initNavTree('functions_vars.html','');});
 <li>CID3
 : <a class="el" href="structITM__Type.html#a43451f43f514108d9eaed5b017f8d921">ITM_Type</a>
 </li>
+<li>CIDR0
+: <a class="el" href="structPMU__Type.html#a54117364a5e8d3af0cc45769bb9b11c7">PMU_Type</a>
+</li>
+<li>CIDR1
+: <a class="el" href="structPMU__Type.html#a0eded5a42f8b81a09df17ce0a9f90897">PMU_Type</a>
+</li>
+<li>CIDR2
+: <a class="el" href="structPMU__Type.html#a94fa4cd97b83324090d6e696f3568415">PMU_Type</a>
+</li>
+<li>CIDR3
+: <a class="el" href="structPMU__Type.html#aff7ed1b5979deb4fb0a536aa477c6830">PMU_Type</a>
+</li>
 <li>CLAIMCLR
 : <a class="el" href="structTPI__Type.html#a0e10e292cb019a832b03ddd055b2f6ac">TPI_Type</a>
 </li>
 <li>CLAIMSET
 : <a class="el" href="structTPI__Type.html#af8b7d15fa5252b733dd4b11fa1b5730a">TPI_Type</a>
 </li>
+<li>CNTENCLR
+: <a class="el" href="structPMU__Type.html#a3c24c882b1679390b1dd957dbd0f0bf6">PMU_Type</a>
+</li>
+<li>CNTENSET
+: <a class="el" href="structPMU__Type.html#a030ee86cd33b72a0c5e66fbaf418d1be">PMU_Type</a>
+</li>
 <li>COMP0
 : <a class="el" href="structDWT__Type.html#a61c2965af5bc0643f9af65620b0e67c9">DWT_Type</a>
 </li>
@@ -247,6 +275,7 @@ $(document).ready(function(){initNavTree('functions_vars.html','');});
 <li>CTRL
 : <a class="el" href="structDWT__Type.html#add790c53410023b3b581919bb681fe2a">DWT_Type</a>
 , <a class="el" href="structMPU__Type.html#a769178ef949f0d5d8f18ddbd9e4e926f">MPU_Type</a>
+, <a class="el" href="structPMU__Type.html#aba9bddd6b49c88e38f4bb79d32002c3c">PMU_Type</a>
 , <a class="el" href="structSysTick__Type.html#a875e7afa5c4fd43997fb544a4ac6e37e">SysTick_Type</a>
 </li>
 <li>CYCCNT
@@ -267,12 +296,14 @@ $(document).ready(function(){initNavTree('functions_vars.html','');});
 </li>
 <li>DEVARCH
 : <a class="el" href="structITM__Type.html#a2372a4ebb63e36d1eb3fcf83a74fd537">ITM_Type</a>
+, <a class="el" href="structPMU__Type.html#a439c7a309f02c41a6581d0819e896fdc">PMU_Type</a>
 </li>
 <li>DEVID
 : <a class="el" href="structTPI__Type.html#abc0ecda8a5446bc754080276bad77514">TPI_Type</a>
 </li>
 <li>DEVTYPE
-: <a class="el" href="structTPI__Type.html#ad98855854a719bbea33061e71529a472">TPI_Type</a>
+: <a class="el" href="structPMU__Type.html#aac8b7bca579afd4969d8bfffa61afbed">PMU_Type</a>
+, <a class="el" href="structTPI__Type.html#ad98855854a719bbea33061e71529a472">TPI_Type</a>
 </li>
 <li>DFR
 : <a class="el" href="structSCB__Type.html#a85dd6fe77aab17e7ea89a52c59da6004">SCB_Type</a>
@@ -287,6 +318,12 @@ $(document).ready(function(){initNavTree('functions_vars.html','');});
 
 
 <h3><a class="anchor" id="index_e"></a>- e -</h3><ul>
+<li>EVCNTR
+: <a class="el" href="structPMU__Type.html#a08f877e8edcb1c19b81ebcf95f85e2f7">PMU_Type</a>
+</li>
+<li>EVTYPER
+: <a class="el" href="structPMU__Type.html#a27682a8d2fe09d2052a4295d5b4a243b">PMU_Type</a>
+</li>
 <li>EXCCNT
 : <a class="el" href="structDWT__Type.html#a9fe20c16c5167ca61486caf6832686d1">DWT_Type</a>
 </li>
@@ -365,6 +402,12 @@ $(document).ready(function(){initNavTree('functions_vars.html','');});
 <li>IMCR
 : <a class="el" href="structITM__Type.html#ae2ce4d3a54df2fd11a197ccac4406cd0">ITM_Type</a>
 </li>
+<li>INTENCLR
+: <a class="el" href="structPMU__Type.html#aaff7d5f3246c641d1f503d74a5adb0ee">PMU_Type</a>
+</li>
+<li>INTENSET
+: <a class="el" href="structPMU__Type.html#a3f5a5872105d9056145e9095bc1c63ac">PMU_Type</a>
+</li>
 <li>IP
 : <a class="el" href="structNVIC__Type.html#a7ff7364a4260df67a2784811e8da4efd">NVIC_Type</a>
 </li>
@@ -457,6 +500,16 @@ $(document).ready(function(){initNavTree('functions_vars.html','');});
 </ul>
 
 
+<h3><a class="anchor" id="index_o"></a>- o -</h3><ul>
+<li>OVSCLR
+: <a class="el" href="structPMU__Type.html#a2acdf96dc7f60ad5a384d1f47e0bb8e0">PMU_Type</a>
+</li>
+<li>OVSSET
+: <a class="el" href="structPMU__Type.html#a153e694a19f845e65a3d2abd4d64faa7">PMU_Type</a>
+</li>
+</ul>
+
+
 <h3><a class="anchor" id="index_p"></a>- p -</h3><ul>
 <li>PCSR
 : <a class="el" href="structDWT__Type.html#a6353ca1d1ad9bc1be05d3b5632960113">DWT_Type</a>
@@ -488,6 +541,21 @@ $(document).ready(function(){initNavTree('functions_vars.html','');});
 <li>PID7
 : <a class="el" href="structITM__Type.html#a2bcec6803f28f30d5baf5e20e3517d3d">ITM_Type</a>
 </li>
+<li>PIDR0
+: <a class="el" href="structPMU__Type.html#afe7c3069b9a30d54e5e30166a2281bd7">PMU_Type</a>
+</li>
+<li>PIDR1
+: <a class="el" href="structPMU__Type.html#a8a764266e9b41e7c100a9853889d94ab">PMU_Type</a>
+</li>
+<li>PIDR2
+: <a class="el" href="structPMU__Type.html#a2f7053542f392f435ad51930d0504622">PMU_Type</a>
+</li>
+<li>PIDR3
+: <a class="el" href="structPMU__Type.html#a831a9b4e2e07eef0b93713beb26a6516">PMU_Type</a>
+</li>
+<li>PIDR4
+: <a class="el" href="structPMU__Type.html#abe4612a6387c5be0e56898bfa6b16902">PMU_Type</a>
+</li>
 <li>PORT
 : <a class="el" href="structITM__Type.html#af95bc1810f9ea802d628cb9dea81e02e">ITM_Type</a>
 </li>
@@ -598,6 +666,9 @@ $(document).ready(function(){initNavTree('functions_vars.html','');});
 <li>STIR
 : <a class="el" href="structNVIC__Type.html#a37de89637466e007171c6b135299bc75">NVIC_Type</a>
 </li>
+<li>SWINC
+: <a class="el" href="structPMU__Type.html#a2add0abae68f27801299d6dd4bfcde66">PMU_Type</a>
+</li>
 </ul>
 
 
@@ -619,6 +690,7 @@ $(document).ready(function(){initNavTree('functions_vars.html','');});
 </li>
 <li>TYPE
 : <a class="el" href="structMPU__Type.html#aba02af87f77577c725cf73879cabb609">MPU_Type</a>
+, <a class="el" href="structPMU__Type.html#a1f2e763ceeeff8ff15c0bd3520b683e8">PMU_Type</a>
 </li>
 </ul>
 
@@ -671,7 +743,7 @@ $(document).ready(function(){initNavTree('functions_vars.html','');});
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:26 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Core/html/globals.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
-   &#160;<span id="projectnumber">Version 5.3.0</span>
+   &#160;<span id="projectnumber">Version 5.4.0</span>
    </div>
    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
   </td>
@@ -156,6 +156,15 @@ $(document).ready(function(){initNavTree('globals.html','');});
 <li>__ARM_ARCH_8M_MAIN__
 : <a class="el" href="group__compiler__conntrol__gr.html#gad424c7143edd08c982dddad0ff65f4cd">Ref_CompilerControl.txt</a>
 </li>
+<li>__ARMv81MML_REV
+: <a class="el" href="group__device__config.html#ga4dd7b69d473733e59cd99fc786174cd3">Template.txt</a>
+</li>
+<li>__ARMv8MBL_REV
+: <a class="el" href="group__device__config.html#ga645c9be694a2d5b5a5b772a0102c727a">Template.txt</a>
+</li>
+<li>__ARMv8MML_REV
+: <a class="el" href="group__device__config.html#gadb7d425f5ad0389b0eb1c6a69f8eb214">Template.txt</a>
+</li>
 <li>__ASM
 : <a class="el" href="group__compiler__conntrol__gr.html#ga1378040bcf22428955c6e3ce9c2053cd">Ref_CompilerControl.txt</a>
 </li>
@@ -168,6 +177,36 @@ $(document).ready(function(){initNavTree('globals.html','');});
 <li>__CLZ()
 : <a class="el" href="group__intrinsic__CPU__gr.html#ga90884c591ac5d73d6069334eba9d6c02">Ref_cmInstr.txt</a>
 </li>
+<li>__CM0_REV
+: <a class="el" href="group__device__config.html#ga905517438930a3f13cbc632e52990534">Template.txt</a>
+</li>
+<li>__CM0PLUS_REV
+: <a class="el" href="group__device__config.html#ga2b7180ed347a0e902c5765deb46e650e">Template.txt</a>
+</li>
+<li>__CM1_REV
+: <a class="el" href="group__device__config.html#ga71248e1e7db00ff28754b6fd80807654">Template.txt</a>
+</li>
+<li>__CM23_REV
+: <a class="el" href="group__device__config.html#ga0f6c2b504ee424a7895fd7a420acdd0e">Template.txt</a>
+</li>
+<li>__CM33_REV
+: <a class="el" href="group__device__config.html#ga178e7a57b608f3e20d1c0cf18a2c2ac3">Template.txt</a>
+</li>
+<li>__CM35P_REV
+: <a class="el" href="group__device__config.html#gadd339c07b13a763dda6e83f4c05122f6">Template.txt</a>
+</li>
+<li>__CM3_REV
+: <a class="el" href="group__device__config.html#gac6a3f185c4640e06443c18b3c8d93f53">Template.txt</a>
+</li>
+<li>__CM4_REV
+: <a class="el" href="group__device__config.html#ga45a97e4bb8b6ce7c334acc5f45ace3ba">Template.txt</a>
+</li>
+<li>__CM55_REV
+: <a class="el" href="group__device__config.html#gaea2d16e963063038cde86cee33c4ef37">Template.txt</a>
+</li>
+<li>__CM7_REV
+: <a class="el" href="group__device__config.html#ga8eb40c0d30a09a0ae388e56b21d8f22c">Template.txt</a>
+</li>
 <li>__CM_CMSIS_VERSION
 : <a class="el" href="group__version__control__gr.html#ga39f3d64ff95fb58feccc7639e537ff89">Ref_VersionControl.txt</a>
 </li>
@@ -186,6 +225,9 @@ $(document).ready(function(){initNavTree('globals.html','');});
 <li>__CORTEX_SC
 : <a class="el" href="group__version__control__gr.html#gaeaaf66c86e5ae02a0e1fe542cb7f4d8c">Ref_VersionControl.txt</a>
 </li>
+<li>__DCACHE_PRESENT
+: <a class="el" href="group__device__config.html#ga11d3ac679daeb58d0cec0a4e6ca59010">Template.txt</a>
+</li>
 <li>__disable_fault_irq()
 : <a class="el" href="group__Core__Register__gr.html#ga9d174f979b2f76fdb3228a9b338fd939">Ref_CoreReg.txt</a>
 </li>
@@ -198,12 +240,24 @@ $(document).ready(function(){initNavTree('globals.html','');});
 <li>__DSB()
 : <a class="el" href="group__intrinsic__CPU__gr.html#gacb2a8ca6eae1ba4b31161578b720c199">Ref_cmInstr.txt</a>
 </li>
+<li>__DSP_PRESENT
+: <a class="el" href="group__device__config.html#ga165f052f5641898a02bb07096dc177b6">Template.txt</a>
+</li>
+<li>__DTCM_PRESENT
+: <a class="el" href="group__device__config.html#gacbb998663708df6626abb09378303019">Template.txt</a>
+</li>
 <li>__enable_fault_irq()
 : <a class="el" href="group__Core__Register__gr.html#ga6575d37863cec5d334864f93b5b783bf">Ref_CoreReg.txt</a>
 </li>
 <li>__enable_irq()
 : <a class="el" href="group__Core__Register__gr.html#ga0f98dfbd252b89d12564472dbeba9c27">Ref_CoreReg.txt</a>
 </li>
+<li>__FPU_DP
+: <a class="el" href="group__device__config.html#ga2a528de57b6217f9fc9d4487d0db6328">Template.txt</a>
+</li>
+<li>__FPU_PRESENT
+: <a class="el" href="group__device__config.html#gac1ba8a48ca926bddc88be9bfd7d42641">Template.txt</a>
+</li>
 <li>__get_APSR()
 : <a class="el" href="group__Core__Register__gr.html#ga811c0012221ee918a75111ca84c4d5e7">Ref_CoreReg.txt</a>
 </li>
@@ -240,6 +294,9 @@ $(document).ready(function(){initNavTree('globals.html','');});
 <li>__get_xPSR()
 : <a class="el" href="group__Core__Register__gr.html#ga732e08184154f44a617963cc65ff95bd">Ref_CoreReg.txt</a>
 </li>
+<li>__ICACHE_PRESENT
+: <a class="el" href="group__device__config.html#ga3580fa1aeb7c2ed580904f8f70f8a919">Template.txt</a>
+</li>
 <li>__INITIAL_SP
 : <a class="el" href="group__compiler__conntrol__gr.html#ga1002e751427b1189f92787d4e4eef965">Ref_CompilerControl.txt</a>
 </li>
@@ -285,12 +342,18 @@ $(document).ready(function(){initNavTree('globals.html','');});
 <li>__LDRT()
 : <a class="el" href="group__intrinsic__CPU__gr.html#ga616504f5da979ba8a073d428d6e8d5c7">Ref_cmInstr.txt</a>
 </li>
+<li>__MPU_PRESENT
+: <a class="el" href="group__device__config.html#ga4127d1b31aaf336fab3d7329d117f448">Template.txt</a>
+</li>
 <li>__NO_RETURN
 : <a class="el" href="group__compiler__conntrol__gr.html#ga153a4a31b276a9758959580538720a51">Ref_CompilerControl.txt</a>
 </li>
 <li>__NOP()
 : <a class="el" href="group__intrinsic__CPU__gr.html#gac71fad9f0a91980fecafcb450ee0a63e">Ref_cmInstr.txt</a>
 </li>
+<li>__NVIC_PRIO_BITS
+: <a class="el" href="group__device__config.html#gae3fe3587d5100c787e02102ce3944460">Template.txt</a>
+</li>
 <li>__PACKED
 : <a class="el" href="group__compiler__conntrol__gr.html#gabe8996d3d985ee1529475443cc635bf1">Ref_CompilerControl.txt</a>
 </li>
@@ -303,6 +366,12 @@ $(document).ready(function(){initNavTree('globals.html','');});
 <li>__PKHTB()
 : <a class="el" href="group__intrinsic__SIMD__gr.html#gafd8fe4a6d87e947caa81a69ec36c1666">Ref_cm4_simd.txt</a>
 </li>
+<li>__PMU_NUM_EVENTCNT
+: <a class="el" href="group__device__config.html#ga9d4c51d9ca3eae58635d1040a3fb5fd2">Template.txt</a>
+</li>
+<li>__PMU_PRESENT
+: <a class="el" href="group__device__config.html#ga1c6eba273d4d6189eee91c6cbe7ec289">Template.txt</a>
+</li>
 <li>__PROGRAM_START
 : <a class="el" href="group__compiler__conntrol__gr.html#ga72db8b026c5e100254080fefabd9fd88">Ref_CompilerControl.txt</a>
 </li>
@@ -360,6 +429,15 @@ $(document).ready(function(){initNavTree('globals.html','');});
 <li>__SASX()
 : <a class="el" href="group__intrinsic__SIMD__gr.html#ga5845084fd99c872e98cf5553d554de2a">Ref_cm4_simd.txt</a>
 </li>
+<li>__SAUREGION_PRESENT
+: <a class="el" href="group__device__config.html#gadae9d54c744e525135b097c618bae3c4">Template.txt</a>
+</li>
+<li>__SC000_REV
+: <a class="el" href="group__device__config.html#gaf293b060f9c15592d18e6b0b977194bf">Template.txt</a>
+</li>
+<li>__SC300_REV
+: <a class="el" href="group__device__config.html#ga3029728b4fc64727b43bcfd853a7180b">Template.txt</a>
+</li>
 <li>__SEL()
 : <a class="el" href="group__intrinsic__SIMD__gr.html#gaf5448e591fe49161b6759b48aecb08fe">Ref_cm4_simd.txt</a>
 </li>
@@ -519,6 +597,9 @@ $(document).ready(function(){initNavTree('globals.html','');});
 <li>__SXTB16()
 : <a class="el" href="group__intrinsic__SIMD__gr.html#ga38dce3dd13ba212e80ec3cff4abeb11a">Ref_cm4_simd.txt</a>
 </li>
+<li>__SXTB16_RORn()
+: <a class="el" href="group__intrinsic__SIMD__gr.html#gaef7e08ba1dbaaae1efdb76c113155ed1">Ref_cm4_simd.txt</a>
+</li>
 <li>__TZ_get_BASEPRI_NS()
 : <a class="el" href="group__coreregister__trustzone__functions.html#ga624509c924d2583f0d4dca6ab270f051">Ref_Trustzone.txt</a>
 </li>
@@ -669,6 +750,12 @@ $(document).ready(function(){initNavTree('globals.html','');});
 <li>__VECTOR_TABLE_ATTRIBUTE
 : <a class="el" href="group__compiler__conntrol__gr.html#ga4f65c96effa79fbd610fea43ee7d745b">Ref_CompilerControl.txt</a>
 </li>
+<li>__Vendor_SysTickConfig
+: <a class="el" href="group__device__config.html#gab58771b4ec03f9bdddc84770f7c95c68">Template.txt</a>
+</li>
+<li>__VTOR_PRESENT
+: <a class="el" href="group__device__config.html#gaddbae1a1b57539f398eb5546a17de8f6">Template.txt</a>
+</li>
 <li>__WEAK
 : <a class="el" href="group__compiler__conntrol__gr.html#gac607bf387b29162be6a9b77fc7999539">Ref_CompilerControl.txt</a>
 </li>
@@ -690,7 +777,7 @@ $(document).ready(function(){initNavTree('globals.html','');});
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:26 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Core/html/globals_a.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
-   &#160;<span id="projectnumber">Version 5.3.0</span>
+   &#160;<span id="projectnumber">Version 5.4.0</span>
    </div>
    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
   </td>
@@ -257,13 +257,502 @@ $(document).ready(function(){initNavTree('globals_a.html','');});
 <li>ARM_MPU_SH_OUTER
 : <a class="el" href="group__mpu8__functions.html#gac4fddbdb9e1350bce6906de33c1fd500">Ref_MPU8.txt</a>
 </li>
+<li>ARM_PMU_BF_CANCEL
+: <a class="el" href="group__pmu8__events__armv81.html#gaf2e0a38b7c0d63d1194f08478781a3f0">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_BF_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#gab8570f46393e3e44bb118591d33723f4">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_BF_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#ga6b1e4823d8b45678a29a5f54b859d4e3">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_BR_IMMED_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga22bfb189fff7c1ea9f81097a543ed756">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_BR_MIS_PRED
+: <a class="el" href="group__pmu8__events__armv81.html#gabfa921c85a61f0a21c9bee289e63c102">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_BR_MIS_PRED_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#gae12baa616c5f0cdd081231fcf8cdad68">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_BR_PRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga60ccf42eae576e2fde3b9e17a8defeaa">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_BR_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#gab3b505a8bcc2b2885626d2f2cd542b73">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_BR_RETURN_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#gab717347b1c3601cffb9c99b43b2a45c5">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_BUS_ACCESS
+: <a class="el" href="group__pmu8__events__armv81.html#gaa681d3db56b42775093869b8fdf1abb9">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_BUS_CYCLES
+: <a class="el" href="group__pmu8__events__armv81.html#gae4c955416707f44f066ffd2560b9ae4c">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_CHAIN
+: <a class="el" href="group__pmu8__events__armv81.html#gaca14907c5a1e1f9915159bc4cf323cf0">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_CNTR_Disable()
+: <a class="el" href="group__pmu8__functions.html#ga76c6f266544c53d93801cfb614155420">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_CNTR_Enable()
+: <a class="el" href="group__pmu8__functions.html#ga22e481855ab257180e24f01a38623887">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_CNTR_Increment()
+: <a class="el" href="group__pmu8__functions.html#ga27b07d38050a16ce416bfaf151a24944">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_CPU_CYCLES
+: <a class="el" href="group__pmu8__events__armv81.html#ga550d524d435a653b2f46acc1380a5ace">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_CTI_TRIGOUT4
+: <a class="el" href="group__pmu8__events__armv81.html#ga290974d72b8cac214f4e9a152ca64a56">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_CTI_TRIGOUT5
+: <a class="el" href="group__pmu8__events__armv81.html#ga7a05420b7fae6f5c3d35e12a9846c7e2">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_CTI_TRIGOUT6
+: <a class="el" href="group__pmu8__events__armv81.html#gade076a5ee512a14f8882d9aec5d3dc0b">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_CTI_TRIGOUT7
+: <a class="el" href="group__pmu8__events__armv81.html#ga4388c85b636bd71b4ee1a03b6e96c488">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_CYCCNT_Reset()
+: <a class="el" href="group__pmu8__functions.html#ga4288c08039886cd24eb2dd4e743fb97e">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_Disable()
+: <a class="el" href="group__pmu8__functions.html#ga74273d4a47cf1a5e99d857a3e8896f10">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_DTCM_ACCESS
+: <a class="el" href="group__pmu8__events__armv81.html#ga74aaa0fa0571f74168ee9608d5a02403">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_DWT_CMPMATCH0
+: <a class="el" href="group__pmu8__events__armv81.html#ga18d640aa04b97c7d287e8745f6f2b23d">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_DWT_CMPMATCH1
+: <a class="el" href="group__pmu8__events__armv81.html#ga5dc6eb2be1ff1afe9cbd59af4f6078ab">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_DWT_CMPMATCH2
+: <a class="el" href="group__pmu8__events__armv81.html#ga58a4815dba8886088b9cac7b934a332d">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_DWT_CMPMATCH3
+: <a class="el" href="group__pmu8__events__armv81.html#ga594337c6f3c88d8317203a8cd6f9814a">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_Enable()
+: <a class="el" href="group__pmu8__functions.html#ga618e7140a774ac2a31a59db4b7d13abc">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_EVCNTR_ALL_Reset()
+: <a class="el" href="group__pmu8__functions.html#ga90527859e6f0ef980300c86c2916ee79">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_EXC_RETURN
+: <a class="el" href="group__pmu8__events__armv81.html#gaf9424157e9c5dca3a3689d181005c4f8">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_EXC_TAKEN
+: <a class="el" href="group__pmu8__events__armv81.html#gac97858bd621eab4592569444f0a5c37f">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_Get_CCNTR()
+: <a class="el" href="group__pmu8__functions.html#gaaa18c27d39f5a55c1b621f5296b88112">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_Get_CNTR_OVS()
+: <a class="el" href="group__pmu8__functions.html#ga70436b378b75bdfe3fcb47697d309a96">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_Get_EVCNTR()
+: <a class="el" href="group__pmu8__functions.html#ga9768cbaffcf2c0b31febe96db91a85d8">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_INST_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga8a5e60eee460addfc66e275a2c4c4800">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_INST_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#gaf7bad54617ace5c2fb48bc2e8aebf9c7">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_ITCM_ACCESS
+: <a class="el" href="group__pmu8__events__armv81.html#gaf23d758fe1a4cfe6f114cb3e78709237">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_L1D_CACHE
+: <a class="el" href="group__pmu8__events__armv81.html#ga7505ae74c1d905f01b05dd5466c1efc0">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_L1D_CACHE_ALLOCATE
+: <a class="el" href="group__pmu8__events__armv81.html#gab55334c8510cb30c4c750913f6eb6279">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_L1D_CACHE_MISS_RD
+: <a class="el" href="group__pmu8__events__armv81.html#ga4687d5d7efc6f49db2db9acc25b590f6">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_L1D_CACHE_RD
+: <a class="el" href="group__pmu8__events__armv81.html#gaf4236dfbcb4550d3cc98caee837e8e77">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_L1D_CACHE_REFILL
+: <a class="el" href="group__pmu8__events__armv81.html#ga64a3d7bfb7ec9d7bdeb073a4fe1bbc38">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_L1D_CACHE_WB
+: <a class="el" href="group__pmu8__events__armv81.html#ga27d1b8b2c37ae0ae41781880ed3893d0">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_L1I_CACHE
+: <a class="el" href="group__pmu8__events__armv81.html#gaf8e89b2b098e6bec5916517346925ce2">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_L1I_CACHE_REFILL
+: <a class="el" href="group__pmu8__events__armv81.html#gac43e0e0f9e385ea66402bdeebf3fea3e">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_L2D_CACHE
+: <a class="el" href="group__pmu8__events__armv81.html#gafb1e1f86d091ccb735858769c700e289">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_L2D_CACHE_ALLOCATE
+: <a class="el" href="group__pmu8__events__armv81.html#gaad08dcded491bf257d223e4171af41cc">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_L2D_CACHE_REFILL
+: <a class="el" href="group__pmu8__events__armv81.html#gaeb414c1b0375022abc2502ab503a3284">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_L2D_CACHE_WB
+: <a class="el" href="group__pmu8__events__armv81.html#ga1a0c4a1990eeed88edc3e1e0c4b1aca0">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_L2I_CACHE
+: <a class="el" href="group__pmu8__events__armv81.html#ga3406498b2c17ca080ebd68cc40d9630e">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_L2I_CACHE_REFILL
+: <a class="el" href="group__pmu8__events__armv81.html#gaa18cee03802b46076e9ab66fd0a7c61d">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_L3D_CACHE
+: <a class="el" href="group__pmu8__events__armv81.html#ga4e96b5a6fb13c657e78da342a02db200">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_L3D_CACHE_ALLOCATE
+: <a class="el" href="group__pmu8__events__armv81.html#gac11cbc6849dbad7bd8b64ab6e2a3f8d5">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_L3D_CACHE_REFILL
+: <a class="el" href="group__pmu8__events__armv81.html#gafe99db0693125100272247c147fb3b02">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_L3D_CACHE_WB
+: <a class="el" href="group__pmu8__events__armv81.html#gab823f95f7ac8196a208d12381b1b2a11">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_LD_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga2e8725ee07c2b2c75a1b54261bc26cc8">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_LE_CANCEL
+: <a class="el" href="group__pmu8__events__armv81.html#ga8b5641a3cb0e922a2b4e16ec14052861">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_LE_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga345461506c990125b1f2cbc62e3be22f">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_LE_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#ga6a1d9f84bda091e96843665ff3913b50">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_LL_CACHE_MISS_RD
+: <a class="el" href="group__pmu8__events__armv81.html#ga6979efa69af7d0e62cc3e2f88b0155b8">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_LL_CACHE_RD
+: <a class="el" href="group__pmu8__events__armv81.html#ga902562d8161fffd45726dc4cc8727545">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MEM_ACCESS
+: <a class="el" href="group__pmu8__events__armv81.html#gab3852c2b3d59af106b9db7ea2c20c367">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MEMORY_ERROR
+: <a class="el" href="group__pmu8__events__armv81.html#ga2c8d23cc64e87b2044bb39bf8d0bc1b1">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_FP_HP_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#gaa4c408a006a04e95ade26922669b6695">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_FP_HP_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#gaf01d187b0cbf418d1fac55dd0ddd0827">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_FP_MAC_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#gac2dc7d92627b3caa391725a3f080288c">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_FP_MAC_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#gaf5302b3278a862c9264171955328a59a">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_FP_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga268b0bcbd30e8a928bd0f331fdf53ccf">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_FP_SP_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#gab21171c50ebd1f304b11260edd015f52">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_FP_SP_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#gae69e310892661af852ca2d4ec947d18a">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_FP_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#gadf9cfd45b59acfc314ebc814a1bcdccd">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_INST_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga3c1006bed2fb82b0749386261b397727">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_INST_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#ga1e276b6872345eb3b043626a11f235c6">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_INT_MAC_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga9248c93a3f19fddc93d3804a06f7238a">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_INT_MAC_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#ga7036f00faa9183ae450a3e4d9d6f2bbf">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_INT_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga5e3afafa91ebaeac0469a19ebb54719c">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_INT_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#ga16ed0bb1bb4718da93c41238da652d33">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_LD_CONTIG_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga8732a737f2b7adc43e3d1da7b3da92e6">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_LD_CONTIG_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#ga8e58fe07254256fa3bf3d42fa2062141">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_LD_MULTI_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga50fb13c874b3f5e2b9ed9c320a36452c">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_LD_MULTI_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#gaf2d4e3d1f06d97899de7fa791477d62b">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_LD_NONCONTIG_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#gaaf2ce8c0ea4c03c934aac6afc31fc5ff">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_LD_NONCONTIG_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#gadbcb82b7924b7bbee5c0d42a3de38572">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_LD_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#gaa3379a51350a2fda8d8ab6d7795baa7a">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_LD_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#ga78a6f89ab30ed01f7d8388eda697b4f8">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_LD_UNALIGNED_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga26ed05deaa7b993904300069f0ecfac4">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_LD_UNALIGNED_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#gadc3bd0f32e0a08bba2d533479a59bd6e">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_LDST_CONTIG_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga8acf6a66c63798b76608caf52c96658d">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_LDST_CONTIG_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#ga5a83ef6a52739e1d223be503bbdaaab6">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_LDST_MULTI_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga7d669378441408fc21aa551e483866cb">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_LDST_MULTI_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#ga7ea46cde08cb0cc4a46ef23835fb5aac">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_LDST_NONCONTIG_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga7065b7f0aea461858b72912d22c329f2">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_LDST_NONCONTIG_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#ga193605eb52709741d91a64e3ad1a5894">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_LDST_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga7d7d465a6c64400c49f93b6c8152296f">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_LDST_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#gaa98a18c06bd13daf2df6f89219ec68d5">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga627920bebd935709655687d844848934">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#gaf9ebeb1f49dba56d8f90f9bd5d3da58e">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_LDST_UNALIGNED_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#gaf358a9ed5c83a10cb695d9b19b1b3bc1">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_LDST_UNALIGNED_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#gab2264786bed578c89109859b55909c76">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_PRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga01b4792990494b8f084ee00933a1adb0">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_ST_CONTIG_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#gacb3c0b922eae9aac321df97ec889e0ed">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_ST_CONTIG_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#ga02cd64b9444e4babc7b69e8571d39bdd">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_ST_MULTI_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga76057cbda353b4ad6fbc3b6a63c193a5">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_ST_MULTI_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#gaf6a14402c79dba8fa765e8663dd0734d">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_ST_NONCONTIG_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga8271f415ecc7573b57e82a24aec86ef1">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_ST_NONCONTIG_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#ga059327c80f396918a9f8192bcd0fa4a8">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_ST_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#gad8d0079977fa97de4ee263703f1b2908">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_ST_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#gabd3984d299b5416aac8d630722680c55">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_ST_UNALIGNED_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga391afd8cb92cc65161b13ee3a3256d40">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_ST_UNALIGNED_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#ga21bf105499df85196b4137cb075a6fbe">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_STALL
+: <a class="el" href="group__pmu8__events__armv81.html#ga2a45ec75b2011bd8375d89b7562b2de6">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_STALL_BREAK
+: <a class="el" href="group__pmu8__events__armv81.html#ga9a1cfef96ec7cd70acf134e368d8826a">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_STALL_DEPENDENCY
+: <a class="el" href="group__pmu8__events__armv81.html#ga29bc4c2e820914e94e2eb68a6a3352b9">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_STALL_RESOURCE
+: <a class="el" href="group__pmu8__events__armv81.html#ga8f4949084efce03d09bf5ba74cc91edd">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_STALL_RESOURCE_FP
+: <a class="el" href="group__pmu8__events__armv81.html#ga7e76060791618f9b4d49ad493cfb6ba9">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_STALL_RESOURCE_INT
+: <a class="el" href="group__pmu8__events__armv81.html#gaef33b3ff7f12d31238ff4dded5e67a11">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_STALL_RESOURCE_MEM
+: <a class="el" href="group__pmu8__events__armv81.html#gab486f5753edd9f10b0f100ff78944dd3">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_VREDUCE_FP_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga77fad5ad424271ed63fec98af071bb79">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_VREDUCE_FP_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#gaa07c698f58c622d234a0007249717265">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_VREDUCE_INT_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga649e7e81f0fd04ca6611f6a6c4035c57">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_VREDUCE_INT_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#ga5b6f0bcfd63207c7bab03ea20167dd4b">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_VREDUCE_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga9546b924daa3c62e5f117026de58ad94">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_VREDUCE_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#gac714f988ae45871b2865f82c11383b36">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_OP_COMPLETE
+: <a class="el" href="group__pmu8__events__armv81.html#ga2fe9d3ea67ce833bd6323e4ce1a4e894">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_OP_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#ga6c59149e9b1754987b44b62092bc9f09">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_PC_WRITE_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga54fd2c392399221077c67866a395e587">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_SE_CALL_NS
+: <a class="el" href="group__pmu8__events__armv81.html#gaaae2c32a8ecd36b59ac98cf8e23b3cab">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_SE_CALL_S
+: <a class="el" href="group__pmu8__events__armv81.html#gad3ba2effbe303ca3fafdbc022fe206c1">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_Set_CNTR_IRQ_Disable()
+: <a class="el" href="group__pmu8__functions.html#ga731b6cd01c6eaa6f909164602f19d0bc">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_Set_CNTR_IRQ_Enable()
+: <a class="el" href="group__pmu8__functions.html#ga133168437a20566d319c78b751425c44">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_Set_CNTR_OVS()
+: <a class="el" href="group__pmu8__functions.html#ga18376f0e3829e93e99149847667e5864">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_Set_EVTYPER()
+: <a class="el" href="group__pmu8__functions.html#ga77ee08f0b3e77d4559cb79fde30d89e9">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_ST_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga8179d1144f8ec993bd1343e276d7b49b">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_STALL
+: <a class="el" href="group__pmu8__events__armv81.html#ga8bf75efa06a125ee2dfa9a130e7ba9a8">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_STALL_BACKEND
+: <a class="el" href="group__pmu8__events__armv81.html#ga8737bee352820bd7d1bc8e5e4260143c">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_STALL_FRONTEND
+: <a class="el" href="group__pmu8__events__armv81.html#ga5b068593baa831348664dfa7d44f5483">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_STALL_OP
+: <a class="el" href="group__pmu8__events__armv81.html#ga197b491f691110fb52aef4291782b6ab">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_STALL_OP_BACKEND
+: <a class="el" href="group__pmu8__events__armv81.html#ga9700ec74727a9fe3cd4cd40736628a23">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_STALL_OP_FRONTEND
+: <a class="el" href="group__pmu8__events__armv81.html#ga69cfd3558cf6c6f3bb621ee75430427c">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_SW_INCR
+: <a class="el" href="group__pmu8__events__armv81.html#ga6e02b08550d7e9b273ff7913f1b57bea">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_TRCEXTOUT0
+: <a class="el" href="group__pmu8__events__armv81.html#gadaa75dc2ccfbf7a2263da9a9011f1603">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_TRCEXTOUT1
+: <a class="el" href="group__pmu8__events__armv81.html#ga47fe03fe6fe9bfebd98283cb57d94560">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_TRCEXTOUT2
+: <a class="el" href="group__pmu8__events__armv81.html#gab80e47ffebc3ae6ed2952756b020dbb9">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_TRCEXTOUT3
+: <a class="el" href="group__pmu8__events__armv81.html#gad70a3b074efd967485ffbfd3e387051d">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_UNALIGNED_LDST_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga45d5ea86fdc015f4fc100462150c92da">Ref_PMU8.txt</a>
+</li>
+<li>ARMCM55_PMU_DOSTIMEOUT_DOUBLE
+: <a class="el" href="group__pmu8__events__armcm55.html#ga8b005f5e47bc8bf9ee8d84a43b798ca9">Ref_PMU8.txt</a>
+</li>
+<li>ARMCM55_PMU_DOSTIMEOUT_TRIPLE
+: <a class="el" href="group__pmu8__events__armcm55.html#ga6bf0106f269b33afbe3482bab385f152">Ref_PMU8.txt</a>
+</li>
+<li>ARMCM55_PMU_ECC_ERR
+: <a class="el" href="group__pmu8__events__armcm55.html#gab423c79d244d071407afb49dfcfb6e05">Ref_PMU8.txt</a>
+</li>
+<li>ARMCM55_PMU_ECC_ERR_DCACHE
+: <a class="el" href="group__pmu8__events__armcm55.html#gaa644074ec71c49e7e7a45d001bbdfb00">Ref_PMU8.txt</a>
+</li>
+<li>ARMCM55_PMU_ECC_ERR_DTCM
+: <a class="el" href="group__pmu8__events__armcm55.html#gaca4db507dab60fce8df90f1a4bb862ad">Ref_PMU8.txt</a>
+</li>
+<li>ARMCM55_PMU_ECC_ERR_FATAL
+: <a class="el" href="group__pmu8__events__armcm55.html#ga88ab1b9d04cd44c53a92962fad8e3bdc">Ref_PMU8.txt</a>
+</li>
+<li>ARMCM55_PMU_ECC_ERR_FATAL_DCACHE
+: <a class="el" href="group__pmu8__events__armcm55.html#ga45cc9a0330e159e4afbce93e3cb5ef2e">Ref_PMU8.txt</a>
+</li>
+<li>ARMCM55_PMU_ECC_ERR_FATAL_DTCM
+: <a class="el" href="group__pmu8__events__armcm55.html#gad82225c528aa89689684fe5ddbe3c637">Ref_PMU8.txt</a>
+</li>
+<li>ARMCM55_PMU_ECC_ERR_FATAL_ICACHE
+: <a class="el" href="group__pmu8__events__armcm55.html#gabe33023adf35df68a949d13212c379eb">Ref_PMU8.txt</a>
+</li>
+<li>ARMCM55_PMU_ECC_ERR_FATAL_ITCM
+: <a class="el" href="group__pmu8__events__armcm55.html#ga0ed17ac3f8d8865e85d9690cbb51a06b">Ref_PMU8.txt</a>
+</li>
+<li>ARMCM55_PMU_ECC_ERR_ICACHE
+: <a class="el" href="group__pmu8__events__armcm55.html#ga7e31a482a7cf6bf6467487dcf2f89181">Ref_PMU8.txt</a>
+</li>
+<li>ARMCM55_PMU_ECC_ERR_ITCM
+: <a class="el" href="group__pmu8__events__armcm55.html#gafc07c84258939e22cdb3b2e98dee0ac6">Ref_PMU8.txt</a>
+</li>
+<li>ARMCM55_PMU_NWAMODE
+: <a class="el" href="group__pmu8__events__armcm55.html#gab3f4da2771d4ca5edc9822d9a5353994">Ref_PMU8.txt</a>
+</li>
+<li>ARMCM55_PMU_NWAMODE_ENTER
+: <a class="el" href="group__pmu8__events__armcm55.html#gaf3fcaa27702154d0739863b6462b8d73">Ref_PMU8.txt</a>
+</li>
+<li>ARMCM55_PMU_PF_CANCEL
+: <a class="el" href="group__pmu8__events__armcm55.html#gad10f5c84036644353ee2dfb14b8e9f48">Ref_PMU8.txt</a>
+</li>
+<li>ARMCM55_PMU_PF_DROP_LINEFILL
+: <a class="el" href="group__pmu8__events__armcm55.html#ga1fafa33dc3bfb8f717fa04a0b868353c">Ref_PMU8.txt</a>
+</li>
+<li>ARMCM55_PMU_PF_LINEFILL
+: <a class="el" href="group__pmu8__events__armcm55.html#gad433a568f1a7ae448807f9e71173e6c2">Ref_PMU8.txt</a>
+</li>
+<li>ARMCM55_PMU_SAHB_ACCESS
+: <a class="el" href="group__pmu8__events__armcm55.html#gaadf0341d6a67cd30481201e7a3c7e77b">Ref_PMU8.txt</a>
+</li>
 </ul>
 </div><!-- contents -->
 </div><!-- doc-content -->
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:26 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Core/html/globals_b.html

@@ -32,7 +32,7 @@
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   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
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+   &#160;<span id="projectnumber">Version 5.4.0</span>
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    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
   </td>
@@ -147,7 +147,7 @@ $(document).ready(function(){initNavTree('globals_b.html','');});
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:26 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Core/html/globals_c.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
-   &#160;<span id="projectnumber">Version 5.3.0</span>
+   &#160;<span id="projectnumber">Version 5.4.0</span>
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    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
   </td>
@@ -150,7 +150,7 @@ $(document).ready(function(){initNavTree('globals_c.html','');});
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:26 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Core/html/globals_d.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
-   &#160;<span id="projectnumber">Version 5.3.0</span>
+   &#160;<span id="projectnumber">Version 5.4.0</span>
    </div>
    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
   </td>
@@ -147,7 +147,7 @@ $(document).ready(function(){initNavTree('globals_d.html','');});
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:26 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Core/html/globals_defs.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
-   &#160;<span id="projectnumber">Version 5.3.0</span>
+   &#160;<span id="projectnumber">Version 5.4.0</span>
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    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
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@@ -89,9 +89,10 @@ var searchBox = new SearchBox("searchBox", "search",false,'Search');
   </div>
   <div id="navrow4" class="tabs3">
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-      <li><a href="#index__"><span>_</span></a></li>
-      <li><a href="#index_a"><span>a</span></a></li>
-      <li class="current"><a href="#index_c"><span>c</span></a></li>
+      <li class="current"><a href="globals_defs.html#index__"><span>_</span></a></li>
+      <li><a href="globals_defs_a.html#index_a"><span>a</span></a></li>
+      <li><a href="globals_defs_c.html#index_c"><span>c</span></a></li>
+      <li><a href="globals_defs_p.html#index_p"><span>p</span></a></li>
     </ul>
   </div>
 </div><!-- top -->
@@ -145,9 +146,48 @@ $(document).ready(function(){initNavTree('globals_defs.html','');});
 <li>__ARM_ARCH_8M_MAIN__
 : <a class="el" href="group__compiler__conntrol__gr.html#gad424c7143edd08c982dddad0ff65f4cd">Ref_CompilerControl.txt</a>
 </li>
+<li>__ARMv81MML_REV
+: <a class="el" href="group__device__config.html#ga4dd7b69d473733e59cd99fc786174cd3">Template.txt</a>
+</li>
+<li>__ARMv8MBL_REV
+: <a class="el" href="group__device__config.html#ga645c9be694a2d5b5a5b772a0102c727a">Template.txt</a>
+</li>
+<li>__ARMv8MML_REV
+: <a class="el" href="group__device__config.html#gadb7d425f5ad0389b0eb1c6a69f8eb214">Template.txt</a>
+</li>
 <li>__ASM
 : <a class="el" href="group__compiler__conntrol__gr.html#ga1378040bcf22428955c6e3ce9c2053cd">Ref_CompilerControl.txt</a>
 </li>
+<li>__CM0_REV
+: <a class="el" href="group__device__config.html#ga905517438930a3f13cbc632e52990534">Template.txt</a>
+</li>
+<li>__CM0PLUS_REV
+: <a class="el" href="group__device__config.html#ga2b7180ed347a0e902c5765deb46e650e">Template.txt</a>
+</li>
+<li>__CM1_REV
+: <a class="el" href="group__device__config.html#ga71248e1e7db00ff28754b6fd80807654">Template.txt</a>
+</li>
+<li>__CM23_REV
+: <a class="el" href="group__device__config.html#ga0f6c2b504ee424a7895fd7a420acdd0e">Template.txt</a>
+</li>
+<li>__CM33_REV
+: <a class="el" href="group__device__config.html#ga178e7a57b608f3e20d1c0cf18a2c2ac3">Template.txt</a>
+</li>
+<li>__CM35P_REV
+: <a class="el" href="group__device__config.html#gadd339c07b13a763dda6e83f4c05122f6">Template.txt</a>
+</li>
+<li>__CM3_REV
+: <a class="el" href="group__device__config.html#gac6a3f185c4640e06443c18b3c8d93f53">Template.txt</a>
+</li>
+<li>__CM4_REV
+: <a class="el" href="group__device__config.html#ga45a97e4bb8b6ce7c334acc5f45ace3ba">Template.txt</a>
+</li>
+<li>__CM55_REV
+: <a class="el" href="group__device__config.html#gaea2d16e963063038cde86cee33c4ef37">Template.txt</a>
+</li>
+<li>__CM7_REV
+: <a class="el" href="group__device__config.html#ga8eb40c0d30a09a0ae388e56b21d8f22c">Template.txt</a>
+</li>
 <li>__CM_CMSIS_VERSION
 : <a class="el" href="group__version__control__gr.html#ga39f3d64ff95fb58feccc7639e537ff89">Ref_VersionControl.txt</a>
 </li>
@@ -166,27 +206,66 @@ $(document).ready(function(){initNavTree('globals_defs.html','');});
 <li>__CORTEX_SC
 : <a class="el" href="group__version__control__gr.html#gaeaaf66c86e5ae02a0e1fe542cb7f4d8c">Ref_VersionControl.txt</a>
 </li>
+<li>__DCACHE_PRESENT
+: <a class="el" href="group__device__config.html#ga11d3ac679daeb58d0cec0a4e6ca59010">Template.txt</a>
+</li>
+<li>__DSP_PRESENT
+: <a class="el" href="group__device__config.html#ga165f052f5641898a02bb07096dc177b6">Template.txt</a>
+</li>
+<li>__DTCM_PRESENT
+: <a class="el" href="group__device__config.html#gacbb998663708df6626abb09378303019">Template.txt</a>
+</li>
+<li>__FPU_DP
+: <a class="el" href="group__device__config.html#ga2a528de57b6217f9fc9d4487d0db6328">Template.txt</a>
+</li>
+<li>__FPU_PRESENT
+: <a class="el" href="group__device__config.html#gac1ba8a48ca926bddc88be9bfd7d42641">Template.txt</a>
+</li>
+<li>__ICACHE_PRESENT
+: <a class="el" href="group__device__config.html#ga3580fa1aeb7c2ed580904f8f70f8a919">Template.txt</a>
+</li>
 <li>__INITIAL_SP
 : <a class="el" href="group__compiler__conntrol__gr.html#ga1002e751427b1189f92787d4e4eef965">Ref_CompilerControl.txt</a>
 </li>
 <li>__INLINE
 : <a class="el" href="group__compiler__conntrol__gr.html#gade2d8d7118f8ff49547f60aa0c3382bb">Ref_CompilerControl.txt</a>
 </li>
+<li>__MPU_PRESENT
+: <a class="el" href="group__device__config.html#ga4127d1b31aaf336fab3d7329d117f448">Template.txt</a>
+</li>
 <li>__NO_RETURN
 : <a class="el" href="group__compiler__conntrol__gr.html#ga153a4a31b276a9758959580538720a51">Ref_CompilerControl.txt</a>
 </li>
+<li>__NVIC_PRIO_BITS
+: <a class="el" href="group__device__config.html#gae3fe3587d5100c787e02102ce3944460">Template.txt</a>
+</li>
 <li>__PACKED
 : <a class="el" href="group__compiler__conntrol__gr.html#gabe8996d3d985ee1529475443cc635bf1">Ref_CompilerControl.txt</a>
 </li>
 <li>__PACKED_STRUCT
 : <a class="el" href="group__compiler__conntrol__gr.html#ga4dbb70fab85207c27b581ecb6532b314">Ref_CompilerControl.txt</a>
 </li>
+<li>__PMU_NUM_EVENTCNT
+: <a class="el" href="group__device__config.html#ga9d4c51d9ca3eae58635d1040a3fb5fd2">Template.txt</a>
+</li>
+<li>__PMU_PRESENT
+: <a class="el" href="group__device__config.html#ga1c6eba273d4d6189eee91c6cbe7ec289">Template.txt</a>
+</li>
 <li>__PROGRAM_START
 : <a class="el" href="group__compiler__conntrol__gr.html#ga72db8b026c5e100254080fefabd9fd88">Ref_CompilerControl.txt</a>
 </li>
 <li>__RESTRICT
 : <a class="el" href="group__compiler__conntrol__gr.html#ga378ac21329d33f561f90265eef89f564">Ref_CompilerControl.txt</a>
 </li>
+<li>__SAUREGION_PRESENT
+: <a class="el" href="group__device__config.html#gadae9d54c744e525135b097c618bae3c4">Template.txt</a>
+</li>
+<li>__SC000_REV
+: <a class="el" href="group__device__config.html#gaf293b060f9c15592d18e6b0b977194bf">Template.txt</a>
+</li>
+<li>__SC300_REV
+: <a class="el" href="group__device__config.html#ga3029728b4fc64727b43bcfd853a7180b">Template.txt</a>
+</li>
 <li>__STACK_LIMIT
 : <a class="el" href="group__compiler__conntrol__gr.html#ga84b0bad4aa39632d3faea46aa1e102a8">Ref_CompilerControl.txt</a>
 </li>
@@ -220,6 +299,12 @@ $(document).ready(function(){initNavTree('globals_defs.html','');});
 <li>__VECTOR_TABLE_ATTRIBUTE
 : <a class="el" href="group__compiler__conntrol__gr.html#ga4f65c96effa79fbd610fea43ee7d745b">Ref_CompilerControl.txt</a>
 </li>
+<li>__Vendor_SysTickConfig
+: <a class="el" href="group__device__config.html#gab58771b4ec03f9bdddc84770f7c95c68">Template.txt</a>
+</li>
+<li>__VTOR_PRESENT
+: <a class="el" href="group__device__config.html#gaddbae1a1b57539f398eb5546a17de8f6">Template.txt</a>
+</li>
 <li>__WEAK
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@@ -230,87 +315,12 @@ $(document).ready(function(){initNavTree('globals_defs.html','');});
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 </li>
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-
-
-<h3><a class="anchor" id="index_a"></a>- a -</h3><ul>
-<li>ARM_MPU_ACCESS_xxx
-: <a class="el" href="group__mpu__defines.html#ga71d41084e984be70a23cb640fd89d1e2">Ref_MPU.txt</a>
-</li>
-<li>ARM_MPU_AP_
-: <a class="el" href="group__mpu8__functions.html#ga81b2aa3fb55cdd5feadff02da10d391b">Ref_MPU8.txt</a>
-</li>
-<li>ARM_MPU_AP_xxx
-: <a class="el" href="group__mpu__defines.html#gabc4788126d7798469cb862a08d3050cc">Ref_MPU.txt</a>
-</li>
-<li>ARM_MPU_ATTR
-: <a class="el" href="group__mpu8__functions.html#ga2c465cc9429b8233bcb9cd7cbef0e54c">Ref_MPU8.txt</a>
-</li>
-<li>ARM_MPU_ATTR_DEVICE
-: <a class="el" href="group__mpu8__functions.html#gab4bfac6284dc050dc6fa6aeb8e954c2c">Ref_MPU8.txt</a>
-</li>
-<li>ARM_MPU_ATTR_DEVICE_GRE
-: <a class="el" href="group__mpu8__functions.html#ga496bcd6a2bbd038d8935049fec9d0fda">Ref_MPU8.txt</a>
-</li>
-<li>ARM_MPU_ATTR_DEVICE_nGnRE
-: <a class="el" href="group__mpu8__functions.html#ga6e08ae44fab85e03fea96ae6a5fcdfb0">Ref_MPU8.txt</a>
-</li>
-<li>ARM_MPU_ATTR_DEVICE_nGnRnE
-: <a class="el" href="group__mpu8__functions.html#gabfa9ae279357044cf5b74e77af22a686">Ref_MPU8.txt</a>
-</li>
-<li>ARM_MPU_ATTR_DEVICE_nGRE
-: <a class="el" href="group__mpu8__functions.html#gadcc9977aabb4dc7177d30cbbac1b53d1">Ref_MPU8.txt</a>
-</li>
-<li>ARM_MPU_ATTR_MEMORY_
-: <a class="el" href="group__mpu8__functions.html#gac2f1c567950e3785d75773362b525390">Ref_MPU8.txt</a>
-</li>
-<li>ARM_MPU_ATTR_NON_CACHEABLE
-: <a class="el" href="group__mpu8__functions.html#ga03266f9660485693eb1baec6ba255ab2">Ref_MPU8.txt</a>
-</li>
-<li>ARM_MPU_CACHEP_xxx
-: <a class="el" href="group__mpu__defines.html#gab23596306119e7831847bd9683de3934">Ref_MPU.txt</a>
-</li>
-<li>ARM_MPU_RASR
-: <a class="el" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">Ref_MPU.txt</a>
-</li>
-<li>ARM_MPU_RASR_EX
-: <a class="el" href="group__mpu__functions.html#ga332ed5f8969dd4df6b61c6ae32ec36dc">Ref_MPU.txt</a>
-</li>
-<li>ARM_MPU_RBAR
-: <a class="el" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">Ref_MPU.txt</a>
-, <a class="el" href="group__mpu8__functions.html#gafe39c2f98058bcac7e7e0501e64e7a9d">Ref_MPU8.txt</a>
-</li>
-<li>ARM_MPU_REGION_SIZE_xxx
-: <a class="el" href="group__mpu__defines.html#gadb0a92c0928c113120567e85ff1ba05c">Ref_MPU.txt</a>
-</li>
-<li>ARM_MPU_RLAR
-: <a class="el" href="group__mpu8__functions.html#gaeaaa071276ba7956944e6c3dc05d677e">Ref_MPU8.txt</a>
-</li>
-<li>ARM_MPU_SH_INNER
-: <a class="el" href="group__mpu8__functions.html#ga73c70127f24f34781ad463cbe51d8f6b">Ref_MPU8.txt</a>
-</li>
-<li>ARM_MPU_SH_NON
-: <a class="el" href="group__mpu8__functions.html#ga3d0f688198289f72264f73cf72a742e8">Ref_MPU8.txt</a>
-</li>
-<li>ARM_MPU_SH_OUTER
-: <a class="el" href="group__mpu8__functions.html#gac4fddbdb9e1350bce6906de33c1fd500">Ref_MPU8.txt</a>
-</li>
-</ul>
-
-
-<h3><a class="anchor" id="index_c"></a>- c -</h3><ul>
-<li>CMSIS_NVIC_VIRTUAL
-: <a class="el" href="group__NVIC__gr.html#gadc48b4ed09386aab48fa6b9c96d9034c">Ref_NVIC.txt</a>
-</li>
-<li>CMSIS_VECTAB_VIRTUAL
-: <a class="el" href="group__NVIC__gr.html#gad01d3aa220b50ef141b06c93888b268d">Ref_NVIC.txt</a>
-</li>
-</ul>
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-    <li class="footer">Generated on Wed Jul 10 2019 15:20:26 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
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+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-Core (Cortex-M)
+   &#160;<span id="projectnumber">Version 5.4.0</span>
+   </div>
+   <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
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+      <li><a href="globals_vars.html"><span>Variables</span></a></li>
+      <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+      <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+      <li class="current"><a href="globals_defs.html"><span>Macros</span></a></li>
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+     onmouseout="return searchBox.OnSearchSelectHide()"
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+<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark">&#160;</span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark">&#160;</span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark">&#160;</span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark">&#160;</span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark">&#160;</span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark">&#160;</span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark">&#160;</span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark">&#160;</span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark">&#160;</span>Pages</a></div>
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+<div class="contents">
+&#160;
+
+<h3><a class="anchor" id="index_a"></a>- a -</h3><ul>
+<li>ARM_MPU_ACCESS_xxx
+: <a class="el" href="group__mpu__defines.html#ga71d41084e984be70a23cb640fd89d1e2">Ref_MPU.txt</a>
+</li>
+<li>ARM_MPU_AP_
+: <a class="el" href="group__mpu8__functions.html#ga81b2aa3fb55cdd5feadff02da10d391b">Ref_MPU8.txt</a>
+</li>
+<li>ARM_MPU_AP_xxx
+: <a class="el" href="group__mpu__defines.html#gabc4788126d7798469cb862a08d3050cc">Ref_MPU.txt</a>
+</li>
+<li>ARM_MPU_ATTR
+: <a class="el" href="group__mpu8__functions.html#ga2c465cc9429b8233bcb9cd7cbef0e54c">Ref_MPU8.txt</a>
+</li>
+<li>ARM_MPU_ATTR_DEVICE
+: <a class="el" href="group__mpu8__functions.html#gab4bfac6284dc050dc6fa6aeb8e954c2c">Ref_MPU8.txt</a>
+</li>
+<li>ARM_MPU_ATTR_DEVICE_GRE
+: <a class="el" href="group__mpu8__functions.html#ga496bcd6a2bbd038d8935049fec9d0fda">Ref_MPU8.txt</a>
+</li>
+<li>ARM_MPU_ATTR_DEVICE_nGnRE
+: <a class="el" href="group__mpu8__functions.html#ga6e08ae44fab85e03fea96ae6a5fcdfb0">Ref_MPU8.txt</a>
+</li>
+<li>ARM_MPU_ATTR_DEVICE_nGnRnE
+: <a class="el" href="group__mpu8__functions.html#gabfa9ae279357044cf5b74e77af22a686">Ref_MPU8.txt</a>
+</li>
+<li>ARM_MPU_ATTR_DEVICE_nGRE
+: <a class="el" href="group__mpu8__functions.html#gadcc9977aabb4dc7177d30cbbac1b53d1">Ref_MPU8.txt</a>
+</li>
+<li>ARM_MPU_ATTR_MEMORY_
+: <a class="el" href="group__mpu8__functions.html#gac2f1c567950e3785d75773362b525390">Ref_MPU8.txt</a>
+</li>
+<li>ARM_MPU_ATTR_NON_CACHEABLE
+: <a class="el" href="group__mpu8__functions.html#ga03266f9660485693eb1baec6ba255ab2">Ref_MPU8.txt</a>
+</li>
+<li>ARM_MPU_CACHEP_xxx
+: <a class="el" href="group__mpu__defines.html#gab23596306119e7831847bd9683de3934">Ref_MPU.txt</a>
+</li>
+<li>ARM_MPU_RASR
+: <a class="el" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">Ref_MPU.txt</a>
+</li>
+<li>ARM_MPU_RASR_EX
+: <a class="el" href="group__mpu__functions.html#ga332ed5f8969dd4df6b61c6ae32ec36dc">Ref_MPU.txt</a>
+</li>
+<li>ARM_MPU_RBAR
+: <a class="el" href="group__mpu8__functions.html#gafe39c2f98058bcac7e7e0501e64e7a9d">Ref_MPU8.txt</a>
+, <a class="el" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">Ref_MPU.txt</a>
+</li>
+<li>ARM_MPU_REGION_SIZE_xxx
+: <a class="el" href="group__mpu__defines.html#gadb0a92c0928c113120567e85ff1ba05c">Ref_MPU.txt</a>
+</li>
+<li>ARM_MPU_RLAR
+: <a class="el" href="group__mpu8__functions.html#gaeaaa071276ba7956944e6c3dc05d677e">Ref_MPU8.txt</a>
+</li>
+<li>ARM_MPU_SH_INNER
+: <a class="el" href="group__mpu8__functions.html#ga73c70127f24f34781ad463cbe51d8f6b">Ref_MPU8.txt</a>
+</li>
+<li>ARM_MPU_SH_NON
+: <a class="el" href="group__mpu8__functions.html#ga3d0f688198289f72264f73cf72a742e8">Ref_MPU8.txt</a>
+</li>
+<li>ARM_MPU_SH_OUTER
+: <a class="el" href="group__mpu8__functions.html#gac4fddbdb9e1350bce6906de33c1fd500">Ref_MPU8.txt</a>
+</li>
+<li>ARM_PMU_BF_CANCEL
+: <a class="el" href="group__pmu8__events__armv81.html#gaf2e0a38b7c0d63d1194f08478781a3f0">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_BF_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#gab8570f46393e3e44bb118591d33723f4">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_BF_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#ga6b1e4823d8b45678a29a5f54b859d4e3">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_BR_IMMED_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga22bfb189fff7c1ea9f81097a543ed756">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_BR_MIS_PRED
+: <a class="el" href="group__pmu8__events__armv81.html#gabfa921c85a61f0a21c9bee289e63c102">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_BR_MIS_PRED_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#gae12baa616c5f0cdd081231fcf8cdad68">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_BR_PRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga60ccf42eae576e2fde3b9e17a8defeaa">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_BR_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#gab3b505a8bcc2b2885626d2f2cd542b73">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_BR_RETURN_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#gab717347b1c3601cffb9c99b43b2a45c5">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_BUS_ACCESS
+: <a class="el" href="group__pmu8__events__armv81.html#gaa681d3db56b42775093869b8fdf1abb9">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_BUS_CYCLES
+: <a class="el" href="group__pmu8__events__armv81.html#gae4c955416707f44f066ffd2560b9ae4c">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_CHAIN
+: <a class="el" href="group__pmu8__events__armv81.html#gaca14907c5a1e1f9915159bc4cf323cf0">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_CPU_CYCLES
+: <a class="el" href="group__pmu8__events__armv81.html#ga550d524d435a653b2f46acc1380a5ace">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_CTI_TRIGOUT4
+: <a class="el" href="group__pmu8__events__armv81.html#ga290974d72b8cac214f4e9a152ca64a56">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_CTI_TRIGOUT5
+: <a class="el" href="group__pmu8__events__armv81.html#ga7a05420b7fae6f5c3d35e12a9846c7e2">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_CTI_TRIGOUT6
+: <a class="el" href="group__pmu8__events__armv81.html#gade076a5ee512a14f8882d9aec5d3dc0b">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_CTI_TRIGOUT7
+: <a class="el" href="group__pmu8__events__armv81.html#ga4388c85b636bd71b4ee1a03b6e96c488">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_DTCM_ACCESS
+: <a class="el" href="group__pmu8__events__armv81.html#ga74aaa0fa0571f74168ee9608d5a02403">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_DWT_CMPMATCH0
+: <a class="el" href="group__pmu8__events__armv81.html#ga18d640aa04b97c7d287e8745f6f2b23d">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_DWT_CMPMATCH1
+: <a class="el" href="group__pmu8__events__armv81.html#ga5dc6eb2be1ff1afe9cbd59af4f6078ab">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_DWT_CMPMATCH2
+: <a class="el" href="group__pmu8__events__armv81.html#ga58a4815dba8886088b9cac7b934a332d">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_DWT_CMPMATCH3
+: <a class="el" href="group__pmu8__events__armv81.html#ga594337c6f3c88d8317203a8cd6f9814a">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_EXC_RETURN
+: <a class="el" href="group__pmu8__events__armv81.html#gaf9424157e9c5dca3a3689d181005c4f8">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_EXC_TAKEN
+: <a class="el" href="group__pmu8__events__armv81.html#gac97858bd621eab4592569444f0a5c37f">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_INST_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga8a5e60eee460addfc66e275a2c4c4800">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_INST_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#gaf7bad54617ace5c2fb48bc2e8aebf9c7">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_ITCM_ACCESS
+: <a class="el" href="group__pmu8__events__armv81.html#gaf23d758fe1a4cfe6f114cb3e78709237">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_L1D_CACHE
+: <a class="el" href="group__pmu8__events__armv81.html#ga7505ae74c1d905f01b05dd5466c1efc0">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_L1D_CACHE_ALLOCATE
+: <a class="el" href="group__pmu8__events__armv81.html#gab55334c8510cb30c4c750913f6eb6279">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_L1D_CACHE_MISS_RD
+: <a class="el" href="group__pmu8__events__armv81.html#ga4687d5d7efc6f49db2db9acc25b590f6">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_L1D_CACHE_RD
+: <a class="el" href="group__pmu8__events__armv81.html#gaf4236dfbcb4550d3cc98caee837e8e77">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_L1D_CACHE_REFILL
+: <a class="el" href="group__pmu8__events__armv81.html#ga64a3d7bfb7ec9d7bdeb073a4fe1bbc38">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_L1D_CACHE_WB
+: <a class="el" href="group__pmu8__events__armv81.html#ga27d1b8b2c37ae0ae41781880ed3893d0">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_L1I_CACHE
+: <a class="el" href="group__pmu8__events__armv81.html#gaf8e89b2b098e6bec5916517346925ce2">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_L1I_CACHE_REFILL
+: <a class="el" href="group__pmu8__events__armv81.html#gac43e0e0f9e385ea66402bdeebf3fea3e">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_L2D_CACHE
+: <a class="el" href="group__pmu8__events__armv81.html#gafb1e1f86d091ccb735858769c700e289">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_L2D_CACHE_ALLOCATE
+: <a class="el" href="group__pmu8__events__armv81.html#gaad08dcded491bf257d223e4171af41cc">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_L2D_CACHE_REFILL
+: <a class="el" href="group__pmu8__events__armv81.html#gaeb414c1b0375022abc2502ab503a3284">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_L2D_CACHE_WB
+: <a class="el" href="group__pmu8__events__armv81.html#ga1a0c4a1990eeed88edc3e1e0c4b1aca0">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_L2I_CACHE
+: <a class="el" href="group__pmu8__events__armv81.html#ga3406498b2c17ca080ebd68cc40d9630e">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_L2I_CACHE_REFILL
+: <a class="el" href="group__pmu8__events__armv81.html#gaa18cee03802b46076e9ab66fd0a7c61d">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_L3D_CACHE
+: <a class="el" href="group__pmu8__events__armv81.html#ga4e96b5a6fb13c657e78da342a02db200">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_L3D_CACHE_ALLOCATE
+: <a class="el" href="group__pmu8__events__armv81.html#gac11cbc6849dbad7bd8b64ab6e2a3f8d5">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_L3D_CACHE_REFILL
+: <a class="el" href="group__pmu8__events__armv81.html#gafe99db0693125100272247c147fb3b02">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_L3D_CACHE_WB
+: <a class="el" href="group__pmu8__events__armv81.html#gab823f95f7ac8196a208d12381b1b2a11">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_LD_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga2e8725ee07c2b2c75a1b54261bc26cc8">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_LE_CANCEL
+: <a class="el" href="group__pmu8__events__armv81.html#ga8b5641a3cb0e922a2b4e16ec14052861">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_LE_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga345461506c990125b1f2cbc62e3be22f">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_LE_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#ga6a1d9f84bda091e96843665ff3913b50">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_LL_CACHE_MISS_RD
+: <a class="el" href="group__pmu8__events__armv81.html#ga6979efa69af7d0e62cc3e2f88b0155b8">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_LL_CACHE_RD
+: <a class="el" href="group__pmu8__events__armv81.html#ga902562d8161fffd45726dc4cc8727545">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MEM_ACCESS
+: <a class="el" href="group__pmu8__events__armv81.html#gab3852c2b3d59af106b9db7ea2c20c367">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MEMORY_ERROR
+: <a class="el" href="group__pmu8__events__armv81.html#ga2c8d23cc64e87b2044bb39bf8d0bc1b1">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_FP_HP_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#gaa4c408a006a04e95ade26922669b6695">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_FP_HP_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#gaf01d187b0cbf418d1fac55dd0ddd0827">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_FP_MAC_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#gac2dc7d92627b3caa391725a3f080288c">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_FP_MAC_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#gaf5302b3278a862c9264171955328a59a">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_FP_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga268b0bcbd30e8a928bd0f331fdf53ccf">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_FP_SP_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#gab21171c50ebd1f304b11260edd015f52">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_FP_SP_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#gae69e310892661af852ca2d4ec947d18a">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_FP_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#gadf9cfd45b59acfc314ebc814a1bcdccd">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_INST_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga3c1006bed2fb82b0749386261b397727">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_INST_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#ga1e276b6872345eb3b043626a11f235c6">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_INT_MAC_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga9248c93a3f19fddc93d3804a06f7238a">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_INT_MAC_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#ga7036f00faa9183ae450a3e4d9d6f2bbf">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_INT_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga5e3afafa91ebaeac0469a19ebb54719c">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_INT_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#ga16ed0bb1bb4718da93c41238da652d33">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_LD_CONTIG_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga8732a737f2b7adc43e3d1da7b3da92e6">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_LD_CONTIG_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#ga8e58fe07254256fa3bf3d42fa2062141">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_LD_MULTI_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga50fb13c874b3f5e2b9ed9c320a36452c">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_LD_MULTI_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#gaf2d4e3d1f06d97899de7fa791477d62b">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_LD_NONCONTIG_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#gaaf2ce8c0ea4c03c934aac6afc31fc5ff">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_LD_NONCONTIG_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#gadbcb82b7924b7bbee5c0d42a3de38572">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_LD_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#gaa3379a51350a2fda8d8ab6d7795baa7a">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_LD_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#ga78a6f89ab30ed01f7d8388eda697b4f8">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_LD_UNALIGNED_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga26ed05deaa7b993904300069f0ecfac4">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_LD_UNALIGNED_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#gadc3bd0f32e0a08bba2d533479a59bd6e">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_LDST_CONTIG_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga8acf6a66c63798b76608caf52c96658d">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_LDST_CONTIG_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#ga5a83ef6a52739e1d223be503bbdaaab6">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_LDST_MULTI_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga7d669378441408fc21aa551e483866cb">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_LDST_MULTI_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#ga7ea46cde08cb0cc4a46ef23835fb5aac">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_LDST_NONCONTIG_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga7065b7f0aea461858b72912d22c329f2">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_LDST_NONCONTIG_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#ga193605eb52709741d91a64e3ad1a5894">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_LDST_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga7d7d465a6c64400c49f93b6c8152296f">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_LDST_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#gaa98a18c06bd13daf2df6f89219ec68d5">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga627920bebd935709655687d844848934">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#gaf9ebeb1f49dba56d8f90f9bd5d3da58e">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_LDST_UNALIGNED_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#gaf358a9ed5c83a10cb695d9b19b1b3bc1">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_LDST_UNALIGNED_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#gab2264786bed578c89109859b55909c76">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_PRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga01b4792990494b8f084ee00933a1adb0">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_ST_CONTIG_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#gacb3c0b922eae9aac321df97ec889e0ed">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_ST_CONTIG_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#ga02cd64b9444e4babc7b69e8571d39bdd">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_ST_MULTI_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga76057cbda353b4ad6fbc3b6a63c193a5">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_ST_MULTI_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#gaf6a14402c79dba8fa765e8663dd0734d">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_ST_NONCONTIG_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga8271f415ecc7573b57e82a24aec86ef1">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_ST_NONCONTIG_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#ga059327c80f396918a9f8192bcd0fa4a8">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_ST_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#gad8d0079977fa97de4ee263703f1b2908">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_ST_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#gabd3984d299b5416aac8d630722680c55">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_ST_UNALIGNED_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga391afd8cb92cc65161b13ee3a3256d40">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_ST_UNALIGNED_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#ga21bf105499df85196b4137cb075a6fbe">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_STALL
+: <a class="el" href="group__pmu8__events__armv81.html#ga2a45ec75b2011bd8375d89b7562b2de6">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_STALL_BREAK
+: <a class="el" href="group__pmu8__events__armv81.html#ga9a1cfef96ec7cd70acf134e368d8826a">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_STALL_DEPENDENCY
+: <a class="el" href="group__pmu8__events__armv81.html#ga29bc4c2e820914e94e2eb68a6a3352b9">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_STALL_RESOURCE
+: <a class="el" href="group__pmu8__events__armv81.html#ga8f4949084efce03d09bf5ba74cc91edd">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_STALL_RESOURCE_FP
+: <a class="el" href="group__pmu8__events__armv81.html#ga7e76060791618f9b4d49ad493cfb6ba9">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_STALL_RESOURCE_INT
+: <a class="el" href="group__pmu8__events__armv81.html#gaef33b3ff7f12d31238ff4dded5e67a11">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_STALL_RESOURCE_MEM
+: <a class="el" href="group__pmu8__events__armv81.html#gab486f5753edd9f10b0f100ff78944dd3">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_VREDUCE_FP_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga77fad5ad424271ed63fec98af071bb79">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_VREDUCE_FP_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#gaa07c698f58c622d234a0007249717265">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_VREDUCE_INT_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga649e7e81f0fd04ca6611f6a6c4035c57">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_VREDUCE_INT_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#ga5b6f0bcfd63207c7bab03ea20167dd4b">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_VREDUCE_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga9546b924daa3c62e5f117026de58ad94">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_MVE_VREDUCE_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#gac714f988ae45871b2865f82c11383b36">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_OP_COMPLETE
+: <a class="el" href="group__pmu8__events__armv81.html#ga2fe9d3ea67ce833bd6323e4ce1a4e894">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_OP_SPEC
+: <a class="el" href="group__pmu8__events__armv81.html#ga6c59149e9b1754987b44b62092bc9f09">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_PC_WRITE_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga54fd2c392399221077c67866a395e587">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_SE_CALL_NS
+: <a class="el" href="group__pmu8__events__armv81.html#gaaae2c32a8ecd36b59ac98cf8e23b3cab">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_SE_CALL_S
+: <a class="el" href="group__pmu8__events__armv81.html#gad3ba2effbe303ca3fafdbc022fe206c1">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_ST_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga8179d1144f8ec993bd1343e276d7b49b">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_STALL
+: <a class="el" href="group__pmu8__events__armv81.html#ga8bf75efa06a125ee2dfa9a130e7ba9a8">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_STALL_BACKEND
+: <a class="el" href="group__pmu8__events__armv81.html#ga8737bee352820bd7d1bc8e5e4260143c">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_STALL_FRONTEND
+: <a class="el" href="group__pmu8__events__armv81.html#ga5b068593baa831348664dfa7d44f5483">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_STALL_OP
+: <a class="el" href="group__pmu8__events__armv81.html#ga197b491f691110fb52aef4291782b6ab">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_STALL_OP_BACKEND
+: <a class="el" href="group__pmu8__events__armv81.html#ga9700ec74727a9fe3cd4cd40736628a23">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_STALL_OP_FRONTEND
+: <a class="el" href="group__pmu8__events__armv81.html#ga69cfd3558cf6c6f3bb621ee75430427c">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_SW_INCR
+: <a class="el" href="group__pmu8__events__armv81.html#ga6e02b08550d7e9b273ff7913f1b57bea">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_TRCEXTOUT0
+: <a class="el" href="group__pmu8__events__armv81.html#gadaa75dc2ccfbf7a2263da9a9011f1603">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_TRCEXTOUT1
+: <a class="el" href="group__pmu8__events__armv81.html#ga47fe03fe6fe9bfebd98283cb57d94560">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_TRCEXTOUT2
+: <a class="el" href="group__pmu8__events__armv81.html#gab80e47ffebc3ae6ed2952756b020dbb9">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_TRCEXTOUT3
+: <a class="el" href="group__pmu8__events__armv81.html#gad70a3b074efd967485ffbfd3e387051d">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_UNALIGNED_LDST_RETIRED
+: <a class="el" href="group__pmu8__events__armv81.html#ga45d5ea86fdc015f4fc100462150c92da">Ref_PMU8.txt</a>
+</li>
+<li>ARMCM55_PMU_DOSTIMEOUT_DOUBLE
+: <a class="el" href="group__pmu8__events__armcm55.html#ga8b005f5e47bc8bf9ee8d84a43b798ca9">Ref_PMU8.txt</a>
+</li>
+<li>ARMCM55_PMU_DOSTIMEOUT_TRIPLE
+: <a class="el" href="group__pmu8__events__armcm55.html#ga6bf0106f269b33afbe3482bab385f152">Ref_PMU8.txt</a>
+</li>
+<li>ARMCM55_PMU_ECC_ERR
+: <a class="el" href="group__pmu8__events__armcm55.html#gab423c79d244d071407afb49dfcfb6e05">Ref_PMU8.txt</a>
+</li>
+<li>ARMCM55_PMU_ECC_ERR_DCACHE
+: <a class="el" href="group__pmu8__events__armcm55.html#gaa644074ec71c49e7e7a45d001bbdfb00">Ref_PMU8.txt</a>
+</li>
+<li>ARMCM55_PMU_ECC_ERR_DTCM
+: <a class="el" href="group__pmu8__events__armcm55.html#gaca4db507dab60fce8df90f1a4bb862ad">Ref_PMU8.txt</a>
+</li>
+<li>ARMCM55_PMU_ECC_ERR_FATAL
+: <a class="el" href="group__pmu8__events__armcm55.html#ga88ab1b9d04cd44c53a92962fad8e3bdc">Ref_PMU8.txt</a>
+</li>
+<li>ARMCM55_PMU_ECC_ERR_FATAL_DCACHE
+: <a class="el" href="group__pmu8__events__armcm55.html#ga45cc9a0330e159e4afbce93e3cb5ef2e">Ref_PMU8.txt</a>
+</li>
+<li>ARMCM55_PMU_ECC_ERR_FATAL_DTCM
+: <a class="el" href="group__pmu8__events__armcm55.html#gad82225c528aa89689684fe5ddbe3c637">Ref_PMU8.txt</a>
+</li>
+<li>ARMCM55_PMU_ECC_ERR_FATAL_ICACHE
+: <a class="el" href="group__pmu8__events__armcm55.html#gabe33023adf35df68a949d13212c379eb">Ref_PMU8.txt</a>
+</li>
+<li>ARMCM55_PMU_ECC_ERR_FATAL_ITCM
+: <a class="el" href="group__pmu8__events__armcm55.html#ga0ed17ac3f8d8865e85d9690cbb51a06b">Ref_PMU8.txt</a>
+</li>
+<li>ARMCM55_PMU_ECC_ERR_ICACHE
+: <a class="el" href="group__pmu8__events__armcm55.html#ga7e31a482a7cf6bf6467487dcf2f89181">Ref_PMU8.txt</a>
+</li>
+<li>ARMCM55_PMU_ECC_ERR_ITCM
+: <a class="el" href="group__pmu8__events__armcm55.html#gafc07c84258939e22cdb3b2e98dee0ac6">Ref_PMU8.txt</a>
+</li>
+<li>ARMCM55_PMU_NWAMODE
+: <a class="el" href="group__pmu8__events__armcm55.html#gab3f4da2771d4ca5edc9822d9a5353994">Ref_PMU8.txt</a>
+</li>
+<li>ARMCM55_PMU_NWAMODE_ENTER
+: <a class="el" href="group__pmu8__events__armcm55.html#gaf3fcaa27702154d0739863b6462b8d73">Ref_PMU8.txt</a>
+</li>
+<li>ARMCM55_PMU_PF_CANCEL
+: <a class="el" href="group__pmu8__events__armcm55.html#gad10f5c84036644353ee2dfb14b8e9f48">Ref_PMU8.txt</a>
+</li>
+<li>ARMCM55_PMU_PF_DROP_LINEFILL
+: <a class="el" href="group__pmu8__events__armcm55.html#ga1fafa33dc3bfb8f717fa04a0b868353c">Ref_PMU8.txt</a>
+</li>
+<li>ARMCM55_PMU_PF_LINEFILL
+: <a class="el" href="group__pmu8__events__armcm55.html#gad433a568f1a7ae448807f9e71173e6c2">Ref_PMU8.txt</a>
+</li>
+<li>ARMCM55_PMU_SAHB_ACCESS
+: <a class="el" href="group__pmu8__events__armcm55.html#gaadf0341d6a67cd30481201e7a3c7e77b">Ref_PMU8.txt</a>
+</li>
+</ul>
+</div><!-- contents -->
+</div><!-- doc-content -->
+<!-- start footer part -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
+	<!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 
+	-->
+	</li>
+  </ul>
+</div>
+</body>
+</html>

docs/Core/html/globals_defs_c.html

@@ -0,0 +1,152 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<title>Globals</title>
+<title>CMSIS-Core (Cortex-M): Globals</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<script type="text/javascript" src="printComponentTabs.js"></script>
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+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+  $(window).load(resizeHeight);
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+<link href="search/search.css" rel="stylesheet" type="text/css"/>
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+<script type="text/javascript">
+  $(document).ready(function() { searchBox.OnSelectItem(0); });
+</script>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-Core (Cortex-M)
+   &#160;<span id="projectnumber">Version 5.4.0</span>
+   </div>
+   <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <script type="text/javascript">
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+	  </ul>
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+var searchBox = new SearchBox("searchBox", "search",false,'Search');
+</script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+      <li>
+        <div id="MSearchBox" class="MSearchBoxInactive">
+        <span class="left">
+          <img id="MSearchSelect" src="search/mag_sel.png"
+               onmouseover="return searchBox.OnSearchSelectShow()"
+               onmouseout="return searchBox.OnSearchSelectHide()"
+               alt=""/>
+          <input type="text" id="MSearchField" value="Search" accesskey="S"
+               onfocus="searchBox.OnSearchFieldFocus(true)" 
+               onblur="searchBox.OnSearchFieldFocus(false)" 
+               onkeyup="searchBox.OnSearchFieldChange(event)"/>
+          </span><span class="right">
+            <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a>
+          </span>
+        </div>
+      </li>
+    </ul>
+  </div>
+  <div id="navrow3" class="tabs2">
+    <ul class="tablist">
+      <li><a href="globals.html"><span>All</span></a></li>
+      <li><a href="globals_func.html"><span>Functions</span></a></li>
+      <li><a href="globals_vars.html"><span>Variables</span></a></li>
+      <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+      <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+      <li class="current"><a href="globals_defs.html"><span>Macros</span></a></li>
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+  <div id="navrow4" class="tabs3">
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+      <li><a href="globals_defs.html#index__"><span>_</span></a></li>
+      <li><a href="globals_defs_a.html#index_a"><span>a</span></a></li>
+      <li class="current"><a href="globals_defs_c.html#index_c"><span>c</span></a></li>
+      <li><a href="globals_defs_p.html#index_p"><span>p</span></a></li>
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+  </div>
+</div><!-- top -->
+<div id="side-nav" class="ui-resizable side-nav-resizable">
+  <div id="nav-tree">
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+      <div id="nav-sync" class="sync"></div>
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+  <div id="splitbar" style="-moz-user-select:none;" 
+       class="ui-resizable-handle">
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+</div>
+<script type="text/javascript">
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+<div id="doc-content">
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+<div id="MSearchSelectWindow"
+     onmouseover="return searchBox.OnSearchSelectShow()"
+     onmouseout="return searchBox.OnSearchSelectHide()"
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+<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark">&#160;</span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark">&#160;</span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark">&#160;</span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark">&#160;</span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark">&#160;</span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark">&#160;</span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark">&#160;</span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark">&#160;</span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark">&#160;</span>Pages</a></div>
+
+<!-- iframe showing the search results (closed by default) -->
+<div id="MSearchResultsWindow">
+<iframe src="javascript:void(0)" frameborder="0" 
+        name="MSearchResults" id="MSearchResults">
+</iframe>
+</div>
+
+<div class="contents">
+&#160;
+
+<h3><a class="anchor" id="index_c"></a>- c -</h3><ul>
+<li>CMSIS_NVIC_VIRTUAL
+: <a class="el" href="group__NVIC__gr.html#gadc48b4ed09386aab48fa6b9c96d9034c">Ref_NVIC.txt</a>
+</li>
+<li>CMSIS_VECTAB_VIRTUAL
+: <a class="el" href="group__NVIC__gr.html#gad01d3aa220b50ef141b06c93888b268d">Ref_NVIC.txt</a>
+</li>
+</ul>
+</div><!-- contents -->
+</div><!-- doc-content -->
+<!-- start footer part -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
+	<!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 
+	-->
+	</li>
+  </ul>
+</div>
+</body>
+</html>

docs/Core/html/globals_defs_p.html

@@ -0,0 +1,149 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<title>Globals</title>
+<title>CMSIS-Core (Cortex-M): Globals</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<script type="text/javascript" src="printComponentTabs.js"></script>
+<link href="navtree.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+  $(window).load(resizeHeight);
+</script>
+<link href="search/search.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="search/search.js"></script>
+<script type="text/javascript">
+  $(document).ready(function() { searchBox.OnSelectItem(0); });
+</script>
+</head>
+<body>
+<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
+<div id="titlearea">
+<table cellspacing="0" cellpadding="0">
+ <tbody>
+ <tr style="height: 46px;">
+  <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-Core (Cortex-M)
+   &#160;<span id="projectnumber">Version 5.4.0</span>
+   </div>
+   <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <script type="text/javascript">
+		<!--
+		writeComponentTabs.call(this);
+		//-->
+      </script>
+	  </ul>
+</div>
+<!-- Generated by Doxygen 1.8.6 -->
+<script type="text/javascript">
+var searchBox = new SearchBox("searchBox", "search",false,'Search');
+</script>
+  <div id="navrow1" class="tabs">
+    <ul class="tablist">
+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+      <li>
+        <div id="MSearchBox" class="MSearchBoxInactive">
+        <span class="left">
+          <img id="MSearchSelect" src="search/mag_sel.png"
+               onmouseover="return searchBox.OnSearchSelectShow()"
+               onmouseout="return searchBox.OnSearchSelectHide()"
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+          <input type="text" id="MSearchField" value="Search" accesskey="S"
+               onfocus="searchBox.OnSearchFieldFocus(true)" 
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+          </span><span class="right">
+            <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a>
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+      </li>
+    </ul>
+  </div>
+  <div id="navrow3" class="tabs2">
+    <ul class="tablist">
+      <li><a href="globals.html"><span>All</span></a></li>
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+      <li><a href="globals_vars.html"><span>Variables</span></a></li>
+      <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
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+      <li class="current"><a href="globals_defs.html"><span>Macros</span></a></li>
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+  <div id="navrow4" class="tabs3">
+    <ul class="tablist">
+      <li><a href="globals_defs.html#index__"><span>_</span></a></li>
+      <li><a href="globals_defs_a.html#index_a"><span>a</span></a></li>
+      <li><a href="globals_defs_c.html#index_c"><span>c</span></a></li>
+      <li class="current"><a href="globals_defs_p.html#index_p"><span>p</span></a></li>
+    </ul>
+  </div>
+</div><!-- top -->
+<div id="side-nav" class="ui-resizable side-nav-resizable">
+  <div id="nav-tree">
+    <div id="nav-tree-contents">
+      <div id="nav-sync" class="sync"></div>
+    </div>
+  </div>
+  <div id="splitbar" style="-moz-user-select:none;" 
+       class="ui-resizable-handle">
+  </div>
+</div>
+<script type="text/javascript">
+$(document).ready(function(){initNavTree('globals_defs_p.html','');});
+</script>
+<div id="doc-content">
+<!-- window showing the filter options -->
+<div id="MSearchSelectWindow"
+     onmouseover="return searchBox.OnSearchSelectShow()"
+     onmouseout="return searchBox.OnSearchSelectHide()"
+     onkeydown="return searchBox.OnSearchSelectKey(event)">
+<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark">&#160;</span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark">&#160;</span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark">&#160;</span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark">&#160;</span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark">&#160;</span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark">&#160;</span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark">&#160;</span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark">&#160;</span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark">&#160;</span>Pages</a></div>
+
+<!-- iframe showing the search results (closed by default) -->
+<div id="MSearchResultsWindow">
+<iframe src="javascript:void(0)" frameborder="0" 
+        name="MSearchResults" id="MSearchResults">
+</iframe>
+</div>
+
+<div class="contents">
+&#160;
+
+<h3><a class="anchor" id="index_p"></a>- p -</h3><ul>
+<li>PMU
+: <a class="el" href="group__pmu8__functions.html#gad19c25be8565f2791aca1a96d1847516">Ref_PMU8.txt</a>
+</li>
+</ul>
+</div><!-- contents -->
+</div><!-- doc-content -->
+<!-- start footer part -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
+	<!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 
+	-->
+	</li>
+  </ul>
+</div>
+</body>
+</html>

docs/Core/html/globals_enum.html

@@ -32,7 +32,7 @@
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   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
-   &#160;<span id="projectnumber">Version 5.3.0</span>
+   &#160;<span id="projectnumber">Version 5.4.0</span>
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    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
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@@ -127,7 +127,7 @@ $(document).ready(function(){initNavTree('globals_enum.html','');});
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 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:26 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
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docs/Core/html/globals_eval.html

@@ -32,7 +32,7 @@
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   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
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+   &#160;<span id="projectnumber">Version 5.4.0</span>
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@@ -160,7 +160,7 @@ $(document).ready(function(){initNavTree('globals_eval.html','');});
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 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:26 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Core/html/globals_func.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
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+   &#160;<span id="projectnumber">Version 5.4.0</span>
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    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
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@@ -442,6 +442,9 @@ $(document).ready(function(){initNavTree('globals_func.html','');});
 <li>__SXTB16()
 : <a class="el" href="group__intrinsic__SIMD__gr.html#ga38dce3dd13ba212e80ec3cff4abeb11a">Ref_cm4_simd.txt</a>
 </li>
+<li>__SXTB16_RORn()
+: <a class="el" href="group__intrinsic__SIMD__gr.html#gaef7e08ba1dbaaae1efdb76c113155ed1">Ref_cm4_simd.txt</a>
+</li>
 <li>__TZ_get_BASEPRI_NS()
 : <a class="el" href="group__coreregister__trustzone__functions.html#ga624509c924d2583f0d4dca6ab270f051">Ref_Trustzone.txt</a>
 </li>
@@ -580,7 +583,7 @@ $(document).ready(function(){initNavTree('globals_func.html','');});
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:26 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Core/html/globals_func_a.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
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+   &#160;<span id="projectnumber">Version 5.4.0</span>
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@@ -165,8 +165,8 @@ $(document).ready(function(){initNavTree('globals_func_a.html','');});
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 </li>
 <li>ARM_MPU_OrderedMemcpy()
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-, <a class="el" href="group__mpu8__functions.html#gac1a949403bf84eecaf407003fb553ae7">Ref_MPU8.txt</a>
+: <a class="el" href="group__mpu8__functions.html#gac1a949403bf84eecaf407003fb553ae7">Ref_MPU8.txt</a>
+, <a class="el" href="group__mpu__functions.html#gac1a949403bf84eecaf407003fb553ae7">Ref_MPU.txt</a>
 </li>
 <li>ARM_MPU_SetMemAttr()
 : <a class="el" href="group__mpu8__functions.html#gab5b3c0a53d19c09a5550f1d9071ae65c">Ref_MPU8.txt</a>
@@ -178,15 +178,57 @@ $(document).ready(function(){initNavTree('globals_func_a.html','');});
 : <a class="el" href="group__mpu8__functions.html#ga1799413f08a157d636a1491371c15ce2">Ref_MPU8.txt</a>
 </li>
 <li>ARM_MPU_SetRegion()
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-, <a class="el" href="group__mpu__functions.html#ga16931f9ad84d7289e8218e169ae6db5d">Ref_MPU.txt</a>
+: <a class="el" href="group__mpu__functions.html#ga16931f9ad84d7289e8218e169ae6db5d">Ref_MPU.txt</a>
+, <a class="el" href="group__mpu8__functions.html#ga6d7f220015c070c0e469948c1775ee3d">Ref_MPU8.txt</a>
 </li>
 <li>ARM_MPU_SetRegion_NS()
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 </li>
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-, <a class="el" href="group__mpu__functions.html#ga042ba1a6a1a58795231459ac0410b809">Ref_MPU.txt</a>
+: <a class="el" href="group__mpu__functions.html#ga042ba1a6a1a58795231459ac0410b809">Ref_MPU.txt</a>
+, <a class="el" href="group__mpu8__functions.html#ga3d50ba8546252bea959e45c8fdf16993">Ref_MPU8.txt</a>
+</li>
+<li>ARM_PMU_CNTR_Disable()
+: <a class="el" href="group__pmu8__functions.html#ga76c6f266544c53d93801cfb614155420">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_CNTR_Enable()
+: <a class="el" href="group__pmu8__functions.html#ga22e481855ab257180e24f01a38623887">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_CNTR_Increment()
+: <a class="el" href="group__pmu8__functions.html#ga27b07d38050a16ce416bfaf151a24944">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_CYCCNT_Reset()
+: <a class="el" href="group__pmu8__functions.html#ga4288c08039886cd24eb2dd4e743fb97e">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_Disable()
+: <a class="el" href="group__pmu8__functions.html#ga74273d4a47cf1a5e99d857a3e8896f10">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_Enable()
+: <a class="el" href="group__pmu8__functions.html#ga618e7140a774ac2a31a59db4b7d13abc">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_EVCNTR_ALL_Reset()
+: <a class="el" href="group__pmu8__functions.html#ga90527859e6f0ef980300c86c2916ee79">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_Get_CCNTR()
+: <a class="el" href="group__pmu8__functions.html#gaaa18c27d39f5a55c1b621f5296b88112">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_Get_CNTR_OVS()
+: <a class="el" href="group__pmu8__functions.html#ga70436b378b75bdfe3fcb47697d309a96">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_Get_EVCNTR()
+: <a class="el" href="group__pmu8__functions.html#ga9768cbaffcf2c0b31febe96db91a85d8">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_Set_CNTR_IRQ_Disable()
+: <a class="el" href="group__pmu8__functions.html#ga731b6cd01c6eaa6f909164602f19d0bc">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_Set_CNTR_IRQ_Enable()
+: <a class="el" href="group__pmu8__functions.html#ga133168437a20566d319c78b751425c44">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_Set_CNTR_OVS()
+: <a class="el" href="group__pmu8__functions.html#ga18376f0e3829e93e99149847667e5864">Ref_PMU8.txt</a>
+</li>
+<li>ARM_PMU_Set_EVTYPER()
+: <a class="el" href="group__pmu8__functions.html#ga77ee08f0b3e77d4559cb79fde30d89e9">Ref_PMU8.txt</a>
 </li>
 </ul>
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@@ -194,7 +236,7 @@ $(document).ready(function(){initNavTree('globals_func_a.html','');});
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:26 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Core/html/globals_func_i.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
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+   &#160;<span id="projectnumber">Version 5.4.0</span>
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@@ -145,7 +145,7 @@ $(document).ready(function(){initNavTree('globals_func_i.html','');});
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:26 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Core/html/globals_func_n.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
-   &#160;<span id="projectnumber">Version 5.3.0</span>
+   &#160;<span id="projectnumber">Version 5.4.0</span>
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    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
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@@ -193,7 +193,7 @@ $(document).ready(function(){initNavTree('globals_func_n.html','');});
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:26 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Core/html/globals_func_s.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
-   &#160;<span id="projectnumber">Version 5.3.0</span>
+   &#160;<span id="projectnumber">Version 5.4.0</span>
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    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
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@@ -131,40 +131,46 @@ $(document).ready(function(){initNavTree('globals_func_s.html','');});
 
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-: <a class="el" href="group__Dcache__functions__m7.html#ga55583e3065c6eabca204b8b89b121c4c">core_cm7.txt</a>
+: <a class="el" href="group__Dcache__functions__m7.html#gaf5585be5547cc60585d702a6129f4c17">core_cm7.txt</a>
 </li>
 <li>SCB_CleanDCache_by_Addr()
-: <a class="el" href="group__Dcache__functions__m7.html#ga696fadbf7b9cc71dad42fab61873a40d">core_cm7.txt</a>
+: <a class="el" href="group__Dcache__functions__m7.html#gab86b0b49bac2b14b21cc1590009efac5">core_cm7.txt</a>
 </li>
 <li>SCB_CleanInvalidateDCache()
-: <a class="el" href="group__Dcache__functions__m7.html#ga1b741def9e3b2ca97dc9ea49b8ce505c">core_cm7.txt</a>
+: <a class="el" href="group__Dcache__functions__m7.html#ga5b22ca58709fadc326da83197a2f28bb">core_cm7.txt</a>
 </li>
 <li>SCB_CleanInvalidateDCache_by_Addr()
-: <a class="el" href="group__Dcache__functions__m7.html#ga630131b2572eaa16b569ed364dfc895e">core_cm7.txt</a>
+: <a class="el" href="group__Dcache__functions__m7.html#ga853737b61ec075250d5991748fdd0e83">core_cm7.txt</a>
 </li>
 <li>SCB_DisableDCache()
-: <a class="el" href="group__Dcache__functions__m7.html#ga6468170f90d270caab8116e7a4f0b5fe">core_cm7.txt</a>
+: <a class="el" href="group__Dcache__functions__m7.html#gafe64b44d1a61483a947e44a77a9d3287">core_cm7.txt</a>
 </li>
 <li>SCB_DisableICache()
-: <a class="el" href="group__Icache__functions__m7.html#gaba757390852f95b3ac2d8638c717d8d8">core_cm7.txt</a>
+: <a class="el" href="group__Icache__functions__m7.html#ga56baa06298799dea5f207d4c12d9d4a6">core_cm7.txt</a>
 </li>
 <li>SCB_EnableDCache()
-: <a class="el" href="group__Dcache__functions__m7.html#ga63aa640d9006021a796a5dcf9c7180b6">core_cm7.txt</a>
+: <a class="el" href="group__Dcache__functions__m7.html#ga3861db932100ccb53f994e2cc68ed79c">core_cm7.txt</a>
 </li>
 <li>SCB_EnableICache()
-: <a class="el" href="group__Icache__functions__m7.html#gaf9e7c6c8e16ada1f95e5bf5a03505b68">core_cm7.txt</a>
+: <a class="el" href="group__Icache__functions__m7.html#ga980ffe52af778f2535ccc52f25f9a7de">core_cm7.txt</a>
 </li>
 <li>SCB_GetFPUType()
 : <a class="el" href="group__fpu__functions.html#ga6bcad99ce80a0e7e4ddc6f2379081756">Ref_FPU.txt</a>
 </li>
+<li>SCB_GetMVEType()
+: <a class="el" href="group__mve__functions.html#ga9de35f6ff713a3cac7674baf49e22b72">Ref_MVE.txt</a>
+</li>
 <li>SCB_InvalidateDCache()
-: <a class="el" href="group__Dcache__functions__m7.html#gace2d30db08887d0bdb818b8a785a5ce6">core_cm7.txt</a>
+: <a class="el" href="group__Dcache__functions__m7.html#ga99fe43c224644881935de135ceaa2dd9">core_cm7.txt</a>
 </li>
 <li>SCB_InvalidateDCache_by_Addr()
-: <a class="el" href="group__Dcache__functions__m7.html#ga503ef7ef58c0773defd15a82f6336c09">core_cm7.txt</a>
+: <a class="el" href="group__Dcache__functions__m7.html#ga2a6f3706a3ffae4c9349c454d407f762">core_cm7.txt</a>
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 <li>SCB_InvalidateICache()
-: <a class="el" href="group__Icache__functions__m7.html#ga50d373a785edd782c5de5a3b55e30ff3">core_cm7.txt</a>
+: <a class="el" href="group__Icache__functions__m7.html#ga62419cb7e6773e3d9236f14e458c1b05">core_cm7.txt</a>
+</li>
+<li>SCB_InvalidateICache_by_Addr()
+: <a class="el" href="group__Icache__functions__m7.html#gaf6bed290ff6916337b0ce6c09131f699">core_cm7.txt</a>
 </li>
 <li>SystemCoreClockUpdate()
 : <a class="el" href="group__system__init__gr.html#gae0c36a9591fe6e9c45ecb21a794f0f0f">Ref_SystemAndClock.txt</a>
@@ -181,7 +187,7 @@ $(document).ready(function(){initNavTree('globals_func_s.html','');});
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:26 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Core/html/globals_func_t.html

@@ -32,7 +32,7 @@
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   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
-   &#160;<span id="projectnumber">Version 5.3.0</span>
+   &#160;<span id="projectnumber">Version 5.4.0</span>
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    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
   </td>
@@ -196,7 +196,7 @@ $(document).ready(function(){initNavTree('globals_func_t.html','');});
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:26 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Core/html/globals_h.html

@@ -32,7 +32,7 @@
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   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
-   &#160;<span id="projectnumber">Version 5.3.0</span>
+   &#160;<span id="projectnumber">Version 5.4.0</span>
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    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
   </td>
@@ -147,7 +147,7 @@ $(document).ready(function(){initNavTree('globals_h.html','');});
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:26 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Core/html/globals_i.html

@@ -32,7 +32,7 @@
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   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
-   &#160;<span id="projectnumber">Version 5.3.0</span>
+   &#160;<span id="projectnumber">Version 5.4.0</span>
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    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
   </td>
@@ -159,7 +159,7 @@ $(document).ready(function(){initNavTree('globals_i.html','');});
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:26 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Core/html/globals_m.html

@@ -32,7 +32,7 @@
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   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
-   &#160;<span id="projectnumber">Version 5.3.0</span>
+   &#160;<span id="projectnumber">Version 5.4.0</span>
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    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
   </td>
@@ -147,7 +147,7 @@ $(document).ready(function(){initNavTree('globals_m.html','');});
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:26 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Core/html/globals_n.html

@@ -32,7 +32,7 @@
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   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
-   &#160;<span id="projectnumber">Version 5.3.0</span>
+   &#160;<span id="projectnumber">Version 5.4.0</span>
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    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
   </td>
@@ -204,7 +204,7 @@ $(document).ready(function(){initNavTree('globals_n.html','');});
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:26 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Core/html/globals_p.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
-   &#160;<span id="projectnumber">Version 5.3.0</span>
+   &#160;<span id="projectnumber">Version 5.4.0</span>
    </div>
    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
   </td>
@@ -141,6 +141,9 @@ $(document).ready(function(){initNavTree('globals_p.html','');});
 <li>PendSV_IRQn
 : <a class="el" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a03c3cc89984928816d81793fc7bce4a2">Ref_NVIC.txt</a>
 </li>
+<li>PMU
+: <a class="el" href="group__pmu8__functions.html#gad19c25be8565f2791aca1a96d1847516">Ref_PMU8.txt</a>
+</li>
 <li>PVD_STM_IRQn
 : <a class="el" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a853e0f318108110e0527f29733d11f86">Ref_NVIC.txt</a>
 </li>
@@ -150,7 +153,7 @@ $(document).ready(function(){initNavTree('globals_p.html','');});
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:26 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Core/html/globals_s.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
-   &#160;<span id="projectnumber">Version 5.3.0</span>
+   &#160;<span id="projectnumber">Version 5.4.0</span>
    </div>
    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
   </td>
@@ -139,40 +139,46 @@ $(document).ready(function(){initNavTree('globals_s.html','');});
 
 <h3><a class="anchor" id="index_s"></a>- s -</h3><ul>
 <li>SCB_CleanDCache()
-: <a class="el" href="group__Dcache__functions__m7.html#ga55583e3065c6eabca204b8b89b121c4c">core_cm7.txt</a>
+: <a class="el" href="group__Dcache__functions__m7.html#gaf5585be5547cc60585d702a6129f4c17">core_cm7.txt</a>
 </li>
 <li>SCB_CleanDCache_by_Addr()
-: <a class="el" href="group__Dcache__functions__m7.html#ga696fadbf7b9cc71dad42fab61873a40d">core_cm7.txt</a>
+: <a class="el" href="group__Dcache__functions__m7.html#gab86b0b49bac2b14b21cc1590009efac5">core_cm7.txt</a>
 </li>
 <li>SCB_CleanInvalidateDCache()
-: <a class="el" href="group__Dcache__functions__m7.html#ga1b741def9e3b2ca97dc9ea49b8ce505c">core_cm7.txt</a>
+: <a class="el" href="group__Dcache__functions__m7.html#ga5b22ca58709fadc326da83197a2f28bb">core_cm7.txt</a>
 </li>
 <li>SCB_CleanInvalidateDCache_by_Addr()
-: <a class="el" href="group__Dcache__functions__m7.html#ga630131b2572eaa16b569ed364dfc895e">core_cm7.txt</a>
+: <a class="el" href="group__Dcache__functions__m7.html#ga853737b61ec075250d5991748fdd0e83">core_cm7.txt</a>
 </li>
 <li>SCB_DisableDCache()
-: <a class="el" href="group__Dcache__functions__m7.html#ga6468170f90d270caab8116e7a4f0b5fe">core_cm7.txt</a>
+: <a class="el" href="group__Dcache__functions__m7.html#gafe64b44d1a61483a947e44a77a9d3287">core_cm7.txt</a>
 </li>
 <li>SCB_DisableICache()
-: <a class="el" href="group__Icache__functions__m7.html#gaba757390852f95b3ac2d8638c717d8d8">core_cm7.txt</a>
+: <a class="el" href="group__Icache__functions__m7.html#ga56baa06298799dea5f207d4c12d9d4a6">core_cm7.txt</a>
 </li>
 <li>SCB_EnableDCache()
-: <a class="el" href="group__Dcache__functions__m7.html#ga63aa640d9006021a796a5dcf9c7180b6">core_cm7.txt</a>
+: <a class="el" href="group__Dcache__functions__m7.html#ga3861db932100ccb53f994e2cc68ed79c">core_cm7.txt</a>
 </li>
 <li>SCB_EnableICache()
-: <a class="el" href="group__Icache__functions__m7.html#gaf9e7c6c8e16ada1f95e5bf5a03505b68">core_cm7.txt</a>
+: <a class="el" href="group__Icache__functions__m7.html#ga980ffe52af778f2535ccc52f25f9a7de">core_cm7.txt</a>
 </li>
 <li>SCB_GetFPUType()
 : <a class="el" href="group__fpu__functions.html#ga6bcad99ce80a0e7e4ddc6f2379081756">Ref_FPU.txt</a>
 </li>
+<li>SCB_GetMVEType()
+: <a class="el" href="group__mve__functions.html#ga9de35f6ff713a3cac7674baf49e22b72">Ref_MVE.txt</a>
+</li>
 <li>SCB_InvalidateDCache()
-: <a class="el" href="group__Dcache__functions__m7.html#gace2d30db08887d0bdb818b8a785a5ce6">core_cm7.txt</a>
+: <a class="el" href="group__Dcache__functions__m7.html#ga99fe43c224644881935de135ceaa2dd9">core_cm7.txt</a>
 </li>
 <li>SCB_InvalidateDCache_by_Addr()
-: <a class="el" href="group__Dcache__functions__m7.html#ga503ef7ef58c0773defd15a82f6336c09">core_cm7.txt</a>
+: <a class="el" href="group__Dcache__functions__m7.html#ga2a6f3706a3ffae4c9349c454d407f762">core_cm7.txt</a>
 </li>
 <li>SCB_InvalidateICache()
-: <a class="el" href="group__Icache__functions__m7.html#ga50d373a785edd782c5de5a3b55e30ff3">core_cm7.txt</a>
+: <a class="el" href="group__Icache__functions__m7.html#ga62419cb7e6773e3d9236f14e458c1b05">core_cm7.txt</a>
+</li>
+<li>SCB_InvalidateICache_by_Addr()
+: <a class="el" href="group__Icache__functions__m7.html#gaf6bed290ff6916337b0ce6c09131f699">core_cm7.txt</a>
 </li>
 <li>SecureFault_IRQn
 : <a class="el" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a9cda5594d898247bfa9d16ad966724da">Ref_NVIC.txt</a>
@@ -201,7 +207,7 @@ $(document).ready(function(){initNavTree('globals_s.html','');});
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:26 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Core/html/globals_t.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
-   &#160;<span id="projectnumber">Version 5.3.0</span>
+   &#160;<span id="projectnumber">Version 5.4.0</span>
    </div>
    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
   </td>
@@ -204,7 +204,7 @@ $(document).ready(function(){initNavTree('globals_t.html','');});
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:26 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Core/html/globals_u.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
-   &#160;<span id="projectnumber">Version 5.3.0</span>
+   &#160;<span id="projectnumber">Version 5.4.0</span>
    </div>
    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
   </td>
@@ -147,7 +147,7 @@ $(document).ready(function(){initNavTree('globals_u.html','');});
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:26 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Core/html/globals_vars.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
-   &#160;<span id="projectnumber">Version 5.3.0</span>
+   &#160;<span id="projectnumber">Version 5.4.0</span>
    </div>
    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
   </td>
@@ -130,7 +130,7 @@ $(document).ready(function(){initNavTree('globals_vars.html','');});
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:26 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Core/html/globals_w.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
-   &#160;<span id="projectnumber">Version 5.3.0</span>
+   &#160;<span id="projectnumber">Version 5.4.0</span>
    </div>
    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
   </td>
@@ -147,7 +147,7 @@ $(document).ready(function(){initNavTree('globals_w.html','');});
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:26 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Core/html/group__Core__Register__gr.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
-   &#160;<span id="projectnumber">Version 5.3.0</span>
+   &#160;<span id="projectnumber">Version 5.4.0</span>
    </div>
    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
   </td>
@@ -199,6 +199,7 @@ Functions</h2></td></tr>
 <tr class="separator:ga6809a07c5cb7410e361f3fba57f72172"><td class="memSeparator" colspan="2">&#160;</td></tr>
 </table>
 <a name="details" id="details"></a><h2 class="groupheader">Description</h2>
+<p>Functions to access the Cortex-M core registers. </p>
 <p>The following functions provide access to Cortex-M core registers. </p>
 <h2 class="groupheader">Function Documentation</h2>
 <a class="anchor" id="ga9d174f979b2f76fdb3228a9b338fd939"></a>
@@ -214,6 +215,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Disables interrupts and all fault handlers [not for Cortex-M0, Cortex-M0+, or SC000]. </p>
 <p>The function disables interrupts and all fault handlers by setting FAULTMASK. The function uses the instruction <b>CPSID f</b>.</p>
 <dl class="section remark"><dt>Remarks</dt><dd><ul>
 <li>not for Cortex-M0, Cortex-M0+, or SC000.</li>
@@ -241,6 +244,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Globally disables interrupts and configurable fault handlers. </p>
 <p>The function disables interrupts and all configurable fault handlers by setting PRIMASK. The function uses the instruction <b>CPSID i</b>.</p>
 <dl class="section remark"><dt>Remarks</dt><dd><ul>
 <li>Can be executed in privileged mode only.</li>
@@ -267,6 +272,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Enables interrupts and all fault handlers [not for Cortex-M0, Cortex-M0+, or SC000]. </p>
 <p>The function enables interrupts and all fault handlers by clearing FAULTMASK. The function uses the instruction <b>CPSIE f</b>.</p>
 <dl class="section remark"><dt>Remarks</dt><dd><ul>
 <li>not for Cortex-M0, Cortex-M0+, or SC000.</li>
@@ -293,6 +300,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Globally enables interrupts and configurable fault handlers. </p>
 <p>The function enables interrupts and all configurable fault handlers by clearing PRIMASK. The function uses the instruction <b>CPSIE i</b>.</p>
 <dl class="section remark"><dt>Remarks</dt><dd><ul>
 <li>Can be executed in privileged mode only.</li>
@@ -318,6 +327,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Read the APSR register. </p>
 <p>The function reads the Application Program Status Register (APSR) using the instruction <b>MRS</b>. <br/>
 <br/>
 The APSR contains the current state of the condition flags from instructions executed previously. The APSR is essential for controlling conditional branches. The following flags are used:</p>
@@ -390,6 +401,8 @@ The APSR contains the current state of the condition flags from instructions exe
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Read the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000]. </p>
 <p>The function returns the Base Priority Mask register (BASEPRI) using the instruction <b>MRS</b>. <br/>
 <br/>
 BASEPRI defines the minimum priority for exception processing. When BASEPRI is set to a non-zero value, it prevents the activation of all exceptions with the same or lower priority level as the BASEPRI value.</p>
@@ -419,6 +432,8 @@ BASEPRI defines the minimum priority for exception processing. When BASEPRI is s
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Read the CONTROL register. </p>
 <p>The function reads the CONTROL register value using the instruction <b>MRS</b>. <br/>
 <br/>
 The CONTROL register controls the stack used and the privilege level for software execution when the processor is in thread mode and, if implemented, indicates whether the FPU state is active. This register uses the following bits: <br/>
@@ -473,6 +488,8 @@ The CONTROL register controls the stack used and the privilege level for softwar
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Read the FAULTMASK register [not for Cortex-M0, Cortex-M0+, or SC000]. </p>
 <p>The function reads the Fault Mask register (FAULTMASK) value using the instruction <b>MRS</b>. <br/>
 <br/>
 FAULTMASK prevents activation of all exceptions except for the Non-Maskable Interrupt (NMI).</p>
@@ -503,6 +520,8 @@ FAULTMASK prevents activation of all exceptions except for the Non-Maskable Inte
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Read the FPSCR register [only Cortex-M4 and Cortex-M7]. </p>
 <p>The function reads the Floating-Point Status Control Register (FPSCR) value. <br/>
 <br/>
 FPSCR provides all necessary User level controls of the floating-point system.</p>
@@ -536,6 +555,8 @@ FPSCR provides all necessary User level controls of the floating-point system.</
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Read the IPSR register. </p>
 <p>The function reads the Interrupt Program Status Register (IPSR) using the instruction <b>MRS</b>. <br/>
 <br/>
 The ISPR contains the exception type number of the current Interrupt Service Routine (ISR). Each exception has an assocciated unique IRQn number. The following bits are used:</p>
@@ -587,7 +608,9 @@ The ISPR contains the exception type number of the current Interrupt Service Rou
         </tr>
       </table>
 </div><div class="memdoc">
-<p>The function reads the Main Status Pointer (MSP) value using the instruction <b>MRS</b>. <br/>
+
+<p>Read the MSP register. </p>
+<p>The function reads the Main Stack Pointer (MSP) value using the instruction <b>MRS</b>. <br/>
 <br/>
 Physically two different stack pointers (SP) exist:</p>
 <ul>
@@ -627,6 +650,8 @@ Physically two different stack pointers (SP) exist:</p>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Get Main Stack Pointer Limit Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. </p>
 <p>Returns the current value of the Main Stack Pointer Limit (MSPLIM). </p>
 <dl class="section return"><dt>Returns</dt><dd>MSPLIM Register value </dd></dl>
 <dl class="section note"><dt>Note</dt><dd>Only availabe for Armv8-M Architecture. </dd></dl>
@@ -646,6 +671,8 @@ Physically two different stack pointers (SP) exist:</p>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Read the PRIMASK register bit. </p>
 <p>The function reads the Priority Mask register (PRIMASK) value using the instruction <b>MRS</b>. <br/>
 <br/>
 PRIMASK is a 1-bit-wide interrupt mask register. When set, it blocks all interrupts apart from the non-maskable interrupt (NMI) and the hard fault exception. The PRIMASK prevents activation of all exceptions with configurable priority.</p>
@@ -675,7 +702,9 @@ PRIMASK is a 1-bit-wide interrupt mask register. When set, it blocks all interru
         </tr>
       </table>
 </div><div class="memdoc">
-<p>The function reads the Program Status Pointer (PSP) value using the instruction <b>MRS</b>. <br/>
+
+<p>Read the PSP register. </p>
+<p>The function reads the Process Stack Pointer (PSP) value using the instruction <b>MRS</b>. <br/>
 <br/>
 Physically two different stack pointers (SP) exist:</p>
 <ul>
@@ -715,6 +744,8 @@ Physically two different stack pointers (SP) exist:</p>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Get Process Stack Pointer Limit Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. </p>
 <p>Returns the current value of the Process Stack Pointer Limit (PSPLIM). </p>
 <dl class="section return"><dt>Returns</dt><dd>PSPLIM Register value </dd></dl>
 <dl class="section note"><dt>Note</dt><dd>Only availabe for Armv8-M Architecture. </dd></dl>
@@ -734,6 +765,8 @@ Physically two different stack pointers (SP) exist:</p>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Read the xPSR register. </p>
 <p>The function reads the combined Program Status Register (xPSR) using the instruction <b>MRS</b>. <br/>
 <br/>
 xPSR provides information about program execution and the APSR flags. It consists of the following PSRs: </p>
@@ -785,6 +818,8 @@ xPSR provides information about program execution and the APSR flags. It consist
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Set the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000]. </p>
 <p>The function sets the Base Priority Mask register (BASEPRI) value using the instruction <b>MSR</b>. <br/>
 <br/>
 BASEPRI defines the minimum priority for exception processing. When BASEPRI is set to a non-zero value, it prevents the activation of all exceptions with the same or lower priority level as the BASEPRI value.</p>
@@ -821,6 +856,8 @@ BASEPRI defines the minimum priority for exception processing. When BASEPRI is s
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Increase the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000]. </p>
 <p>The function only increases the Base Priority Mask register (BASEPRI) value using the instruction <b>MSR</b>. The value is set only if BASEPRI masking is disabled, or the new value increases the BASEPRI priority level. <br/>
 <br/>
 BASEPRI defines the minimum priority for exception processing.</p>
@@ -859,6 +896,8 @@ BASEPRI defines the minimum priority for exception processing.</p>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Set the CONTROL Register. </p>
 <p>The function sets the CONTROL register value using the instruction <b>MSR</b>. <br/>
 <br/>
 The CONTROL register controls the stack used and the privilege level for software execution when the processor is in thread mode and, if implemented, indicates whether the FPU state is active. This register uses the following bits: <br/>
@@ -922,6 +961,8 @@ The CONTROL register controls the stack used and the privilege level for softwar
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Set the FAULTMASK register [not for Cortex-M0, Cortex-M0+, or SC000]. </p>
 <p>The function sets the Fault Mask register (FAULTMASK) value using the instruction <b>MSR</b>. <br/>
 <br/>
 FAULTMASK prevents activation of all exceptions except for Non-Maskable Interrupt (NMI). FAULTMASK can be used to escalate a configurable fault handler (BusFault, usage fault, or memory management fault) to hard fault level without invoking a hard fault. This allows the fault handler to pretend to be the hard fault handler, whith the ability to:</p>
@@ -964,6 +1005,8 @@ FAULTMASK prevents activation of all exceptions except for Non-Maskable Interrup
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Set the FPSC register [only for Cortex-M4 and Cortex-M7]. </p>
 <p>The function sets the Floating-Point Status Control Register (FPSCR) value. <br/>
 <br/>
 FPSCR provides all necessary User level control of the floating-point system. <br/>
@@ -1103,7 +1146,9 @@ FPSCR provides all necessary User level control of the floating-point system. <b
         </tr>
       </table>
 </div><div class="memdoc">
-<p>The function sets the Main Status Pointer (MSP) value using the instruction <b>MSR</b>. <br/>
+
+<p>Set the MSP register. </p>
+<p>The function sets the Main Stack Pointer (MSP) value using the instruction <b>MSR</b>. <br/>
 <br/>
 Physically two different stack pointers (SP) exist:</p>
 <ul>
@@ -1148,6 +1193,8 @@ Physically two different stack pointers (SP) exist:</p>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Set Main Stack Pointer Limit Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. </p>
 <p>Assigns the given value to the Main Stack Pointer Limit (MSPLIM). </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -1172,6 +1219,8 @@ Physically two different stack pointers (SP) exist:</p>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Set the Priority Mask bit. </p>
 <p>The function sets the Priority Mask register (PRIMASK) value using the instruction <b>MSR</b>. <br/>
 <br/>
 PRIMASK is a 1-bit-wide interrupt mask register. When set, it blocks all interrupts apart from the non-maskable interrupt (NMI) and the hard fault exception. The PRIMASK prevents activation of all exceptions with configurable priority.</p>
@@ -1213,7 +1262,9 @@ PRIMASK is a 1-bit-wide interrupt mask register. When set, it blocks all interru
         </tr>
       </table>
 </div><div class="memdoc">
-<p>The function sets the Program Status Pointer (PSP) value using the instruction <b>MSR</b>. <br/>
+
+<p>Set the PSP register. </p>
+<p>The function sets the Process Stack Pointer (PSP) value using the instruction <b>MSR</b>. <br/>
 <br/>
 Physically two different stack pointers (SP) exist:</p>
 <ul>
@@ -1258,6 +1309,8 @@ Physically two different stack pointers (SP) exist:</p>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Set Process Stack Pointer Limit Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. </p>
 <p>Assigns the given value to the Process Stack Pointer Limit (PSPLIM). </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -1274,7 +1327,7 @@ Physically two different stack pointers (SP) exist:</p>
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:25 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
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docs/Core/html/group__Dcache__functions__m7.html

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    <div id="projectname">CMSIS-Core (Cortex-M)
-   &#160;<span id="projectnumber">Version 5.3.0</span>
+   &#160;<span id="projectnumber">Version 5.4.0</span>
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+<div class="title">D-Cache Functions<div class="ingroups"><a class="el" href="group__cache__functions__m7.html">Cache Functions (Level-1)</a></div></div>  </div>
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 <div class="contents">
 
-<p>Functions for the data cache.  
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 <a href="#details">More...</a></p>
 <table class="memberdecls">
 <tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
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+<tr class="separator:ga3861db932100ccb53f994e2cc68ed79c"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gafe64b44d1a61483a947e44a77a9d3287"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Dcache__functions__m7.html#gafe64b44d1a61483a947e44a77a9d3287">SCB_DisableDCache</a> (void)</td></tr>
+<tr class="memdesc:gafe64b44d1a61483a947e44a77a9d3287"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable D-Cache.  <a href="#gafe64b44d1a61483a947e44a77a9d3287">More...</a><br/></td></tr>
+<tr class="separator:gafe64b44d1a61483a947e44a77a9d3287"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="memdesc:ga99fe43c224644881935de135ceaa2dd9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Invalidate D-Cache.  <a href="#ga99fe43c224644881935de135ceaa2dd9">More...</a><br/></td></tr>
+<tr class="separator:ga99fe43c224644881935de135ceaa2dd9"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="memdesc:gaf5585be5547cc60585d702a6129f4c17"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clean D-Cache.  <a href="#gaf5585be5547cc60585d702a6129f4c17">More...</a><br/></td></tr>
+<tr class="separator:gaf5585be5547cc60585d702a6129f4c17"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="memdesc:ga5b22ca58709fadc326da83197a2f28bb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clean &amp; Invalidate D-Cache.  <a href="#ga5b22ca58709fadc326da83197a2f28bb">More...</a><br/></td></tr>
+<tr class="separator:ga5b22ca58709fadc326da83197a2f28bb"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga2a6f3706a3ffae4c9349c454d407f762"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Dcache__functions__m7.html#ga2a6f3706a3ffae4c9349c454d407f762">SCB_InvalidateDCache_by_Addr</a> (uint32_t *addr, int32_t dsize)</td></tr>
+<tr class="memdesc:ga2a6f3706a3ffae4c9349c454d407f762"><td class="mdescLeft">&#160;</td><td class="mdescRight">D-Cache Invalidate by address.  <a href="#ga2a6f3706a3ffae4c9349c454d407f762">More...</a><br/></td></tr>
+<tr class="separator:ga2a6f3706a3ffae4c9349c454d407f762"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gab86b0b49bac2b14b21cc1590009efac5"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Dcache__functions__m7.html#gab86b0b49bac2b14b21cc1590009efac5">SCB_CleanDCache_by_Addr</a> (uint32_t *addr, int32_t dsize)</td></tr>
+<tr class="memdesc:gab86b0b49bac2b14b21cc1590009efac5"><td class="mdescLeft">&#160;</td><td class="mdescRight">D-Cache Clean by address.  <a href="#gab86b0b49bac2b14b21cc1590009efac5">More...</a><br/></td></tr>
+<tr class="separator:gab86b0b49bac2b14b21cc1590009efac5"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga853737b61ec075250d5991748fdd0e83"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Dcache__functions__m7.html#ga853737b61ec075250d5991748fdd0e83">SCB_CleanInvalidateDCache_by_Addr</a> (uint32_t *addr, int32_t dsize)</td></tr>
+<tr class="memdesc:ga853737b61ec075250d5991748fdd0e83"><td class="mdescLeft">&#160;</td><td class="mdescRight">D-Cache Clean and Invalidate by address.  <a href="#ga853737b61ec075250d5991748fdd0e83">More...</a><br/></td></tr>
+<tr class="separator:ga853737b61ec075250d5991748fdd0e83"><td class="memSeparator" colspan="2">&#160;</td></tr>
 </table>
 <a name="details" id="details"></a><h2 class="groupheader">Description</h2>
+<p>Functions for the level-1 data cache. </p>
 <p>// close ICache functions </p>
 <h2 class="groupheader">Function Documentation</h2>
-<a class="anchor" id="ga55583e3065c6eabca204b8b89b121c4c"></a>
+<a class="anchor" id="gaf5585be5547cc60585d702a6129f4c17"></a>
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-          <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void SCB_CleanDCache </td>
+          <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void SCB_CleanDCache </td>
           <td>(</td>
           <td class="paramtype">void&#160;</td>
           <td class="paramname"></td><td>)</td>
@@ -160,16 +161,18 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Clean D-Cache. </p>
 <p>The function cleans the entire data cache. </p>
 
 </div>
 </div>
-<a class="anchor" id="ga696fadbf7b9cc71dad42fab61873a40d"></a>
+<a class="anchor" id="gab86b0b49bac2b14b21cc1590009efac5"></a>
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+          <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void SCB_CleanDCache_by_Addr </td>
           <td>(</td>
           <td class="paramtype">uint32_t *&#160;</td>
           <td class="paramname"><em>addr</em>, </td>
@@ -187,6 +190,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>D-Cache Clean by address. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
     <tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>address (aligned to 32-byte boundary) </td></tr>
@@ -198,12 +203,12 @@ Functions</h2></td></tr>
 
 </div>
 </div>
-<a class="anchor" id="ga1b741def9e3b2ca97dc9ea49b8ce505c"></a>
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+          <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void SCB_CleanInvalidateDCache </td>
           <td>(</td>
           <td class="paramtype">void&#160;</td>
           <td class="paramname"></td><td>)</td>
@@ -211,16 +216,18 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Clean &amp; Invalidate D-Cache. </p>
 <p>The function cleans and invalidates the entire data cache. </p>
 
 </div>
 </div>
-<a class="anchor" id="ga630131b2572eaa16b569ed364dfc895e"></a>
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+          <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void SCB_CleanInvalidateDCache_by_Addr </td>
           <td>(</td>
           <td class="paramtype">uint32_t *&#160;</td>
           <td class="paramname"><em>addr</em>, </td>
@@ -238,6 +245,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>D-Cache Clean and Invalidate by address. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
     <tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>address (aligned to 32-byte boundary) </td></tr>
@@ -249,12 +258,12 @@ Functions</h2></td></tr>
 
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-<a class="anchor" id="ga6468170f90d270caab8116e7a4f0b5fe"></a>
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-          <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void SCB_DisableDCache </td>
+          <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void SCB_DisableDCache </td>
           <td>(</td>
           <td class="paramtype">void&#160;</td>
           <td class="paramname"></td><td>)</td>
@@ -262,17 +271,19 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Disable D-Cache. </p>
 <p>The function turns off the entire data cache.</p>
-<dl class="section note"><dt>Note</dt><dd>When disabling the data cache, you must clean (<a class="el" href="group__Dcache__functions__m7.html#ga55583e3065c6eabca204b8b89b121c4c">SCB_CleanDCache</a>) the entire cache to ensure that any dirty data is flushed to external memory. </dd></dl>
+<dl class="section note"><dt>Note</dt><dd>When disabling the data cache, you must clean (<a class="el" href="group__Dcache__functions__m7.html#gaf5585be5547cc60585d702a6129f4c17">SCB_CleanDCache</a>) the entire cache to ensure that any dirty data is flushed to external memory. </dd></dl>
 
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-<a class="anchor" id="ga63aa640d9006021a796a5dcf9c7180b6"></a>
+<a class="anchor" id="ga3861db932100ccb53f994e2cc68ed79c"></a>
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+          <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void SCB_EnableDCache </td>
           <td>(</td>
           <td class="paramtype">void&#160;</td>
           <td class="paramname"></td><td>)</td>
@@ -280,19 +291,21 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Enable D-Cache. </p>
 <p>The function turns on the entire data cache. </p>
-<dl class="section note"><dt>Note</dt><dd>Before enabling the data cache, you must invalidate the entire data cache (<a class="el" href="group__Dcache__functions__m7.html#gace2d30db08887d0bdb818b8a785a5ce6">SCB_InvalidateDCache</a>), because external memory might have changed from when the cache was disabled.</dd>
+<dl class="section note"><dt>Note</dt><dd>Before enabling the data cache, you must invalidate the entire data cache (<a class="el" href="group__Dcache__functions__m7.html#ga99fe43c224644881935de135ceaa2dd9">SCB_InvalidateDCache</a>), because external memory might have changed from when the cache was disabled.</dd>
 <dd>
-After reset, you must invalidate (<a class="el" href="group__Dcache__functions__m7.html#gace2d30db08887d0bdb818b8a785a5ce6">SCB_InvalidateDCache</a>) each cache before enabling it. </dd></dl>
+After reset, you must invalidate (<a class="el" href="group__Dcache__functions__m7.html#ga99fe43c224644881935de135ceaa2dd9">SCB_InvalidateDCache</a>) each cache before enabling it. </dd></dl>
 
 </div>
 </div>
-<a class="anchor" id="gace2d30db08887d0bdb818b8a785a5ce6"></a>
+<a class="anchor" id="ga99fe43c224644881935de135ceaa2dd9"></a>
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-          <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void SCB_InvalidateDCache </td>
+          <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void SCB_InvalidateDCache </td>
           <td>(</td>
           <td class="paramtype">void&#160;</td>
           <td class="paramname"></td><td>)</td>
@@ -300,17 +313,19 @@ After reset, you must invalidate (<a class="el" href="group__Dcache__functions__
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+
+<p>Invalidate D-Cache. </p>
 <p>The function invalidates the entire data cache.</p>
-<dl class="section note"><dt>Note</dt><dd>After reset, you must invalidate each cache before enabling (<a class="el" href="group__Dcache__functions__m7.html#ga63aa640d9006021a796a5dcf9c7180b6">SCB_EnableDCache</a>) it. </dd></dl>
+<dl class="section note"><dt>Note</dt><dd>After reset, you must invalidate each cache before enabling (<a class="el" href="group__Dcache__functions__m7.html#ga3861db932100ccb53f994e2cc68ed79c">SCB_EnableDCache</a>) it. </dd></dl>
 
 </div>
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-<a class="anchor" id="ga503ef7ef58c0773defd15a82f6336c09"></a>
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+          <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void SCB_InvalidateDCache_by_Addr </td>
           <td>(</td>
           <td class="paramtype">uint32_t *&#160;</td>
           <td class="paramname"><em>addr</em>, </td>
@@ -328,6 +343,8 @@ After reset, you must invalidate (<a class="el" href="group__Dcache__functions__
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>D-Cache Invalidate by address. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
     <tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>address (aligned to 32-byte boundary) </td></tr>
@@ -344,7 +361,7 @@ After reset, you must invalidate (<a class="el" href="group__Dcache__functions__
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:26 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
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docs/Core/html/group__Dcache__functions__m7.js

@@ -1,11 +1,11 @@
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-    [ "SCB_InvalidateDCache_by_Addr", "group__Dcache__functions__m7.html#ga503ef7ef58c0773defd15a82f6336c09", null ]
+    [ "SCB_CleanDCache", "group__Dcache__functions__m7.html#gaf5585be5547cc60585d702a6129f4c17", null ],
+    [ "SCB_CleanDCache_by_Addr", "group__Dcache__functions__m7.html#gab86b0b49bac2b14b21cc1590009efac5", null ],
+    [ "SCB_CleanInvalidateDCache", "group__Dcache__functions__m7.html#ga5b22ca58709fadc326da83197a2f28bb", null ],
+    [ "SCB_CleanInvalidateDCache_by_Addr", "group__Dcache__functions__m7.html#ga853737b61ec075250d5991748fdd0e83", null ],
+    [ "SCB_DisableDCache", "group__Dcache__functions__m7.html#gafe64b44d1a61483a947e44a77a9d3287", null ],
+    [ "SCB_EnableDCache", "group__Dcache__functions__m7.html#ga3861db932100ccb53f994e2cc68ed79c", null ],
+    [ "SCB_InvalidateDCache", "group__Dcache__functions__m7.html#ga99fe43c224644881935de135ceaa2dd9", null ],
+    [ "SCB_InvalidateDCache_by_Addr", "group__Dcache__functions__m7.html#ga2a6f3706a3ffae4c9349c454d407f762", null ]
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docs/Core/html/group__ITM__Debug__gr.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
-   &#160;<span id="projectnumber">Version 5.3.0</span>
+   &#160;<span id="projectnumber">Version 5.4.0</span>
    </div>
    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
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 <a name="details" id="details"></a><h2 class="groupheader">Description</h2>
+<p>Debug Access to the Instrumented Trace Macrocell (ITM) </p>
 <p>CMSIS provides additional debug functions to enlarge the Debug Access. Data can be transmitted via a certain global buffer variable towards the target system.</p>
 <p>The Cortex-M3 / Cortex-M4 / Cortex-M7 incorporates the <b>Instrumented Trace Macrocell (ITM)</b> that provides together with the <b>Serial Wire Output (SWO)</b> trace capabilities for the microcontroller system. The ITM has 32 communication channels; two ITM communication channels are used by CMSIS to output the following information:</p>
 <ul>
@@ -193,6 +194,8 @@ Example:</h1>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>ITM Check Character. </p>
 <p>This function reads the external variable <a class="el" href="group__ITM__Debug__gr.html#ga12e68e55a7badc271b948d6c7230b2a8">ITM_RxBuffer</a> and checks whether a character is available or not.</p>
 <dl class="section return"><dt>Returns</dt><dd><ul>
 <li>=0 - No character available</li>
@@ -215,6 +218,8 @@ Example:</h1>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>ITM Receive Character. </p>
 <p>This function inputs a character via the external variable <a class="el" href="group__ITM__Debug__gr.html#ga12e68e55a7badc271b948d6c7230b2a8">ITM_RxBuffer</a>. It returns when no debugger is connected that has booked the output. It is blocking when a debugger is connected, but the previously sent character has not been transmitted.</p>
 <dl class="section return"><dt>Returns</dt><dd><ul>
 <li>Received character</li>
@@ -237,6 +242,8 @@ Example:</h1>
         </tr>
       </table>
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+
+<p>Transmits a character via channel 0. </p>
 <p>This function transmits a character via the ITM channel 0. It returns when no debugger is connected that has booked the output. It is blocking when a debugger is connected, but the previously sent character has not been transmitted.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -259,6 +266,8 @@ Example:</h1>
       </table>
 </div><div class="memdoc">
 
+<p>external variable to receive characters </p>
+
 </div>
 </div>
 </div><!-- contents -->
@@ -266,7 +275,7 @@ Example:</h1>
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:25 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
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   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
-   &#160;<span id="projectnumber">Version 5.3.0</span>
+   &#160;<span id="projectnumber">Version 5.4.0</span>
    </div>
    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
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-<div class="title">I-Cache Functions<div class="ingroups"><a class="el" href="group__cache__functions__m7.html">Cache Functions  (only Cortex-M7)</a></div></div>  </div>
+<div class="title">I-Cache Functions<div class="ingroups"><a class="el" href="group__cache__functions__m7.html">Cache Functions (Level-1)</a></div></div>  </div>
 </div><!--header-->
 <div class="contents">
 
-<p>Functions for the instruction cache.  
+<p>Functions for the level-1 instruction cache.  
 <a href="#details">More...</a></p>
 <table class="memberdecls">
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-<tr class="separator:ga50d373a785edd782c5de5a3b55e30ff3"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga980ffe52af778f2535ccc52f25f9a7de"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Icache__functions__m7.html#ga980ffe52af778f2535ccc52f25f9a7de">SCB_EnableICache</a> (void)</td></tr>
+<tr class="memdesc:ga980ffe52af778f2535ccc52f25f9a7de"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable I-Cache.  <a href="#ga980ffe52af778f2535ccc52f25f9a7de">More...</a><br/></td></tr>
+<tr class="separator:ga980ffe52af778f2535ccc52f25f9a7de"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga56baa06298799dea5f207d4c12d9d4a6"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Icache__functions__m7.html#ga56baa06298799dea5f207d4c12d9d4a6">SCB_DisableICache</a> (void)</td></tr>
+<tr class="memdesc:ga56baa06298799dea5f207d4c12d9d4a6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable I-Cache.  <a href="#ga56baa06298799dea5f207d4c12d9d4a6">More...</a><br/></td></tr>
+<tr class="separator:ga56baa06298799dea5f207d4c12d9d4a6"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga62419cb7e6773e3d9236f14e458c1b05"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Icache__functions__m7.html#ga62419cb7e6773e3d9236f14e458c1b05">SCB_InvalidateICache</a> (void)</td></tr>
+<tr class="memdesc:ga62419cb7e6773e3d9236f14e458c1b05"><td class="mdescLeft">&#160;</td><td class="mdescRight">Invalidate I-Cache.  <a href="#ga62419cb7e6773e3d9236f14e458c1b05">More...</a><br/></td></tr>
+<tr class="separator:ga62419cb7e6773e3d9236f14e458c1b05"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gaf6bed290ff6916337b0ce6c09131f699"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Icache__functions__m7.html#gaf6bed290ff6916337b0ce6c09131f699">SCB_InvalidateICache_by_Addr</a> (void *addr, int32_t isize)</td></tr>
+<tr class="memdesc:gaf6bed290ff6916337b0ce6c09131f699"><td class="mdescLeft">&#160;</td><td class="mdescRight">I-Cache Invalidate by address.  <a href="#gaf6bed290ff6916337b0ce6c09131f699">More...</a><br/></td></tr>
+<tr class="separator:gaf6bed290ff6916337b0ce6c09131f699"><td class="memSeparator" colspan="2">&#160;</td></tr>
 </table>
 <a name="details" id="details"></a><h2 class="groupheader">Description</h2>
+<p>Functions for the level-1 instruction cache. </p>
 <h2 class="groupheader">Function Documentation</h2>
-<a class="anchor" id="gaba757390852f95b3ac2d8638c717d8d8"></a>
+<a class="anchor" id="ga56baa06298799dea5f207d4c12d9d4a6"></a>
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+          <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void SCB_DisableICache </td>
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           <td class="paramname"></td><td>)</td>
@@ -144,16 +148,18 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Disable I-Cache. </p>
 <p>The function turns off the instruction cache. </p>
 
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-<a class="anchor" id="gaf9e7c6c8e16ada1f95e5bf5a03505b68"></a>
+<a class="anchor" id="ga980ffe52af778f2535ccc52f25f9a7de"></a>
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+          <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void SCB_EnableICache </td>
           <td>(</td>
           <td class="paramtype">void&#160;</td>
           <td class="paramname"></td><td>)</td>
@@ -161,19 +167,21 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Enable I-Cache. </p>
 <p>The function turns on the instruction cache. </p>
-<dl class="section note"><dt>Note</dt><dd>Before enabling the instruction cache, you must invalidate (<a class="el" href="group__Icache__functions__m7.html#ga50d373a785edd782c5de5a3b55e30ff3">SCB_InvalidateICache</a>) the entire instruction cache if external memory might have changed since the cache was disabled. </dd>
+<dl class="section note"><dt>Note</dt><dd>Before enabling the instruction cache, you must invalidate (<a class="el" href="group__Icache__functions__m7.html#ga62419cb7e6773e3d9236f14e458c1b05">SCB_InvalidateICache</a>) the entire instruction cache if external memory might have changed since the cache was disabled. </dd>
 <dd>
-After reset, you must invalidate (<a class="el" href="group__Icache__functions__m7.html#ga50d373a785edd782c5de5a3b55e30ff3">SCB_InvalidateICache</a>) each cache before enabling it. </dd></dl>
+After reset, you must invalidate (<a class="el" href="group__Icache__functions__m7.html#ga62419cb7e6773e3d9236f14e458c1b05">SCB_InvalidateICache</a>) each cache before enabling it. </dd></dl>
 
 </div>
 </div>
-<a class="anchor" id="ga50d373a785edd782c5de5a3b55e30ff3"></a>
+<a class="anchor" id="ga62419cb7e6773e3d9236f14e458c1b05"></a>
 <div class="memitem">
 <div class="memproto">
       <table class="memname">
         <tr>
-          <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void SCB_InvalidateICache </td>
+          <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void SCB_InvalidateICache </td>
           <td>(</td>
           <td class="paramtype">void&#160;</td>
           <td class="paramname"></td><td>)</td>
@@ -181,8 +189,46 @@ After reset, you must invalidate (<a class="el" href="group__Icache__functions__
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Invalidate I-Cache. </p>
 <p>The function invalidates the instruction cache. The instruction cache is never dirty so cache RAM errors are always recoverable by invalidating the cache and retrying the instruction. </p>
-<dl class="section note"><dt>Note</dt><dd>After reset, you must invalidate each cache before enabling (<a class="el" href="group__Icache__functions__m7.html#gaf9e7c6c8e16ada1f95e5bf5a03505b68">SCB_EnableICache</a>) it. </dd></dl>
+<dl class="section note"><dt>Note</dt><dd>After reset, you must invalidate each cache before enabling (<a class="el" href="group__Icache__functions__m7.html#ga980ffe52af778f2535ccc52f25f9a7de">SCB_EnableICache</a>) it. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gaf6bed290ff6916337b0ce6c09131f699"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void SCB_InvalidateICache_by_Addr </td>
+          <td>(</td>
+          <td class="paramtype">void *&#160;</td>
+          <td class="paramname"><em>addr</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">int32_t&#160;</td>
+          <td class="paramname"><em>isize</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>I-Cache Invalidate by address. </p>
+<p>Invalidates I-Cache for the given address. I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. I-Cache memory blocks which are part of given address + given size are invalidated. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>address </td></tr>
+    <tr><td class="paramdir">[in]</td><td class="paramname">isize</td><td>size of memory block (in number of bytes) </td></tr>
+  </table>
+  </dd>
+</dl>
 
 </div>
 </div>
@@ -191,7 +237,7 @@ After reset, you must invalidate (<a class="el" href="group__Icache__functions__
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:26 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Core/html/group__Icache__functions__m7.js

@@ -1,6 +1,7 @@
 var group__Icache__functions__m7 =
 [
-    [ "SCB_DisableICache", "group__Icache__functions__m7.html#gaba757390852f95b3ac2d8638c717d8d8", null ],
-    [ "SCB_EnableICache", "group__Icache__functions__m7.html#gaf9e7c6c8e16ada1f95e5bf5a03505b68", null ],
-    [ "SCB_InvalidateICache", "group__Icache__functions__m7.html#ga50d373a785edd782c5de5a3b55e30ff3", null ]
+    [ "SCB_DisableICache", "group__Icache__functions__m7.html#ga56baa06298799dea5f207d4c12d9d4a6", null ],
+    [ "SCB_EnableICache", "group__Icache__functions__m7.html#ga980ffe52af778f2535ccc52f25f9a7de", null ],
+    [ "SCB_InvalidateICache", "group__Icache__functions__m7.html#ga62419cb7e6773e3d9236f14e458c1b05", null ],
+    [ "SCB_InvalidateICache_by_Addr", "group__Icache__functions__m7.html#gaf6bed290ff6916337b0ce6c09131f699", null ]
 ];

docs/Core/html/group__NVIC__gr.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
-   &#160;<span id="projectnumber">Version 5.3.0</span>
+   &#160;<span id="projectnumber">Version 5.4.0</span>
    </div>
    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
   </td>
@@ -220,29 +220,23 @@ Functions</h2></td></tr>
 <tr class="separator:ga44b31316872e91bda1af7e17173de24b"><td class="memSeparator" colspan="2">&#160;</td></tr>
 </table>
 <a name="details" id="details"></a><h2 class="groupheader">Description</h2>
+<p>Functions to access the Nested Vector Interrupt Controller (NVIC). </p>
 <p>This section explains how to use interrupts and exceptions and access functions for the Nested Vector Interrupt Controller (NVIC).</p>
 <p>Arm provides a template file <b>startup_<em>device</em></b> for each supported compiler. The file must be adapted by the silicon vendor to include interrupt vectors for all device-specific interrupt handlers. Each interrupt handler is defined as a <b><em>weak</em></b> function to an dummy handler. These interrupt handlers can be used directly in application software without being adapted by the programmer.</p>
 <p>The table below lists the core exception vectors of the various Cortex-M processors.</p>
 <table  class="cmtable" summary="Core Exception Name">
 <tr>
-<th>Exception Vector </th><th>IRQn<br/>
-Value </th><th>M0 </th><th>M0+ </th><th>M3 </th><th>M4 </th><th>M7 </th><th>SC000 </th><th>SC300 </th><th>Armv8-M<br/>
-Baseline </th><th>Armv8-M<br/>
+<th>Exception Vector </th><th>Handler Function </th><th>IRQn<br/>
+Value </th><th title="Cortex-M0/M0+
+and SC000
+      ">Armv6-M </th><th title="Cortex-M3/M4/M7
+and SC300
+      ">Armv7-M </th><th title="Cortex-M23">Armv8-M<br/>
+Baseline </th><th title="Cortex-M33/M35P">Armv8-M<br/>
+Mainline </th><th>Armv8.1-M<br/>
 Mainline </th><th>Description  </th></tr>
 <tr>
-<td><b>NonMaskableInt_IRQn</b> </td><td>-14 </td><td><div class="image">
-<img src="check.png"  alt="available"/>
-</div>
- </td><td><div class="image">
-<img src="check.png"  alt="available"/>
-</div>
- </td><td><div class="image">
-<img src="check.png"  alt="available"/>
-</div>
- </td><td><div class="image">
-<img src="check.png"  alt="available"/>
-</div>
- </td><td><div class="image">
+<td><b>NonMaskableInt_IRQn</b> </td><td>NMI_Handler </td><td>-14 </td><td><div class="image">
 <img src="check.png"  alt="available"/>
 </div>
  </td><td><div class="image">
@@ -259,19 +253,7 @@ Mainline </th><th>Description  </th></tr>
 </div>
  </td><td>Non Maskable Interrupt  </td></tr>
 <tr>
-<td><b>HardFault_IRQn</b> </td><td>-13 </td><td><div class="image">
-<img src="check.png"  alt="available"/>
-</div>
- </td><td><div class="image">
-<img src="check.png"  alt="available"/>
-</div>
- </td><td><div class="image">
-<img src="check.png"  alt="available"/>
-</div>
- </td><td><div class="image">
-<img src="check.png"  alt="available"/>
-</div>
- </td><td><div class="image">
+<td><b>HardFault_IRQn</b> </td><td>HardFault_Handler </td><td>-13 </td><td><div class="image">
 <img src="check.png"  alt="available"/>
 </div>
  </td><td><div class="image">
@@ -288,69 +270,40 @@ Mainline </th><th>Description  </th></tr>
 </div>
  </td><td>Hard Fault Interrupt  </td></tr>
 <tr>
-<td><b>MemoryManagement_IRQn</b> </td><td>-12 </td><td>&#160; </td><td>&#160; </td><td><div class="image">
-<img src="check.png"  alt="available"/>
-</div>
- </td><td><div class="image">
-<img src="check.png"  alt="available"/>
-</div>
- </td><td><div class="image">
+<td><b>MemoryManagement_IRQn</b> </td><td>MemManage_Handler </td><td>-12 </td><td>&#160; </td><td><div class="image">
 <img src="check.png"  alt="available"/>
 </div>
  </td><td>&#160; </td><td><div class="image">
 <img src="check.png"  alt="available"/>
 </div>
- </td><td>&#160; </td><td><div class="image">
+ </td><td><div class="image">
 <img src="check.png"  alt="available"/>
 </div>
  </td><td>Memory Management Interrupt  </td></tr>
 <tr>
-<td><b>BusFault_IRQn</b> </td><td>-11 </td><td>&#160; </td><td>&#160; </td><td><div class="image">
-<img src="check.png"  alt="available"/>
-</div>
- </td><td><div class="image">
-<img src="check.png"  alt="available"/>
-</div>
- </td><td><div class="image">
+<td><b>BusFault_IRQn</b> </td><td>BusFault_Handler </td><td>-11 </td><td>&#160; </td><td><div class="image">
 <img src="check.png"  alt="available"/>
 </div>
  </td><td>&#160; </td><td><div class="image">
 <img src="check.png"  alt="available"/>
 </div>
- </td><td>&#160; </td><td><div class="image">
+ </td><td><div class="image">
 <img src="check.png"  alt="available"/>
 </div>
  </td><td>Bus Fault Interrupt  </td></tr>
 <tr>
-<td><b>UsageFault_IRQn</b> </td><td>-10 </td><td>&#160; </td><td>&#160; </td><td><div class="image">
-<img src="check.png"  alt="available"/>
-</div>
- </td><td><div class="image">
-<img src="check.png"  alt="available"/>
-</div>
- </td><td><div class="image">
+<td><b>UsageFault_IRQn</b> </td><td>UsageFault_Handler </td><td>-10 </td><td>&#160; </td><td><div class="image">
 <img src="check.png"  alt="available"/>
 </div>
  </td><td>&#160; </td><td><div class="image">
 <img src="check.png"  alt="available"/>
-</div>
- </td><td>&#160; </td><td><div class="image">
-<img src="check.png"  alt="available"/>
-</div>
- </td><td>Usage Fault Interrupt  </td></tr>
-<tr>
-<td><b>SecureFault_IRQn</b> </td><td>-9 </td><td>&#160; </td><td>&#160; </td><td>&#160; </td><td>&#160; </td><td>&#160; </td><td>&#160; </td><td>&#160; </td><td><div class="image">
-<img src="check.png"  alt="available"/>
 </div>
  </td><td><div class="image">
 <img src="check.png"  alt="available"/>
 </div>
- </td><td>Secure Fault Interrupt  </td></tr>
+ </td><td>Usage Fault Interrupt  </td></tr>
 <tr>
-<td><b>SVCall_IRQn</b> </td><td>-5 </td><td><div class="image">
-<img src="check.png"  alt="available"/>
-</div>
- </td><td><div class="image">
+<td><b>SecureFault_IRQn</b> </td><td>SecureFault_Handler </td><td>-9 </td><td>&#160; </td><td>&#160; </td><td><div class="image">
 <img src="check.png"  alt="available"/>
 </div>
  </td><td><div class="image">
@@ -359,7 +312,9 @@ Mainline </th><th>Description  </th></tr>
  </td><td><div class="image">
 <img src="check.png"  alt="available"/>
 </div>
- </td><td><div class="image">
+ </td><td>Secure Fault Interrupt  </td></tr>
+<tr>
+<td><b>SVCall_IRQn</b> </td><td>SVC_Handler </td><td>-5 </td><td><div class="image">
 <img src="check.png"  alt="available"/>
 </div>
  </td><td><div class="image">
@@ -376,36 +331,18 @@ Mainline </th><th>Description  </th></tr>
 </div>
  </td><td>SV Call Interrupt   </td></tr>
 <tr>
-<td><b>DebugMonitor_IRQn</b> </td><td>-4 </td><td>&#160; </td><td>&#160; </td><td><div class="image">
-<img src="check.png"  alt="available"/>
-</div>
- </td><td><div class="image">
-<img src="check.png"  alt="available"/>
-</div>
- </td><td><div class="image">
+<td><b>DebugMonitor_IRQn</b> </td><td>DebugMon_Handler </td><td>-4 </td><td>&#160; </td><td><div class="image">
 <img src="check.png"  alt="available"/>
 </div>
  </td><td>&#160; </td><td><div class="image">
 <img src="check.png"  alt="available"/>
 </div>
- </td><td>&#160; </td><td><div class="image">
+ </td><td><div class="image">
 <img src="check.png"  alt="available"/>
 </div>
  </td><td>Debug Monitor Interrupt  </td></tr>
 <tr>
-<td><b>PendSV_IRQn</b> </td><td>-2 </td><td><div class="image">
-<img src="check.png"  alt="available"/>
-</div>
- </td><td><div class="image">
-<img src="check.png"  alt="available"/>
-</div>
- </td><td><div class="image">
-<img src="check.png"  alt="available"/>
-</div>
- </td><td><div class="image">
-<img src="check.png"  alt="available"/>
-</div>
- </td><td><div class="image">
+<td><b>PendSV_IRQn</b> </td><td>PendSV_Handler </td><td>-2 </td><td><div class="image">
 <img src="check.png"  alt="available"/>
 </div>
  </td><td><div class="image">
@@ -422,19 +359,7 @@ Mainline </th><th>Description  </th></tr>
 </div>
  </td><td>Pend SV Interrupt  </td></tr>
 <tr>
-<td><b>SysTick_IRQn</b> </td><td>-1 </td><td><div class="image">
-<img src="check.png"  alt="available"/>
-</div>
- </td><td><div class="image">
-<img src="check.png"  alt="available"/>
-</div>
- </td><td><div class="image">
-<img src="check.png"  alt="available"/>
-</div>
- </td><td><div class="image">
-<img src="check.png"  alt="available"/>
-</div>
- </td><td><div class="image">
+<td><b>SysTick_IRQn</b> </td><td>SysTick_Handler </td><td>-1 </td><td><div class="image">
 <img src="check.png"  alt="available"/>
 </div>
  </td><td><div class="image">
@@ -569,6 +494,8 @@ Mainline </th><th>Description  </th></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Virtualization of the NVIC API. </p>
 <p>When <a class="el" href="group__NVIC__gr.html#gadc48b4ed09386aab48fa6b9c96d9034c">CMSIS_NVIC_VIRTUAL</a> is defined, the NVIC access functions in the table below must be implemented for virtualizing NVIC access. These functions should be implemented in a separate source module. The original CMSIS-Core __NVIC functions are always available independent of <a class="el" href="group__NVIC__gr.html#gadc48b4ed09386aab48fa6b9c96d9034c">CMSIS_NVIC_VIRTUAL</a>.</p>
 <table class="doxtable">
 <tr>
@@ -608,6 +535,8 @@ Mainline </th><th>Description  </th></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Virtualization of interrupt vector table access functions. </p>
 <p>When <a class="el" href="group__NVIC__gr.html#gadc48b4ed09386aab48fa6b9c96d9034c">CMSIS_NVIC_VIRTUAL</a> is defined, the functions in the table below must be replaced to virtualize the API access functions to the interrupt vector table. The NVIC vector table API should be implemented in a separate source module. This allows, for example, alternate implementations to relocate the vector table from flash to RAM on the first vector table update.</p>
 <p>The original CMSIS-Core functions are always available, but prefixed with __NVIC.</p>
 <table class="doxtable">
@@ -631,7 +560,9 @@ Mainline </th><th>Description  </th></tr>
         </tr>
       </table>
 </div><div class="memdoc">
-<p>The core exception enumeration names for IRQn values are defined in the file <b>device.h</b>.</p>
+
+<p>Definition of IRQn numbers. </p>
+<p>The core exception enumeration names for IRQn values are defined in the <a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a>.</p>
 <ul>
 <li>Negative IRQn values represent processor core exceptions (internal interrupts).</li>
 <li>Positive IRQn values represent device-specific exceptions (external interrupts).</li>
@@ -693,6 +624,8 @@ Mainline </th><th>Description  </th></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Clear a device specific interrupt from pending. </p>
 <p>This function removes the pending state of the specified device specific interrupt <em>IRQn</em>. <em>IRQn</em> cannot be a negative number.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -727,6 +660,8 @@ Mainline </th><th>Description  </th></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Clear Interrupt Target State. </p>
 <p>Clears the interrupt target field in the non-secure NVIC when in secure state. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -785,6 +720,8 @@ Mainline </th><th>Description  </th></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Decode the interrupt priority [not for Cortex-M0, Cortex-M0+, or SC000]. </p>
 <p>This function decodes an interrupt priority value with the priority group <em>PriorityGroup</em> to preemptive priority value <em>pPreemptPriority</em> and subpriority value <em>pSubPriority</em>. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -820,6 +757,8 @@ Mainline </th><th>Description  </th></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Disable a device specific interrupt. </p>
 <p>This function disables the specified device specific interrupt <em>IRQn</em>. <em>IRQn</em> cannot be a negative value.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -853,6 +792,8 @@ Mainline </th><th>Description  </th></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Enable a device specific interrupt. </p>
 <p>This function enables the specified device specific interrupt <em>IRQn</em>. <em>IRQn</em> cannot be a negative value.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -909,6 +850,8 @@ Mainline </th><th>Description  </th></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Encodes Priority [not for Cortex-M0, Cortex-M0+, or SC000]. </p>
 <p>This function encodes the priority for an interrupt with the priority group <em>PriorityGroup</em>, preemptive priority value <em>PreemptPriority</em>, and subpriority value <em>SubPriority</em>. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -944,6 +887,8 @@ Mainline </th><th>Description  </th></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Get the device specific interrupt active status [not for Cortex-M0, Cortex-M0+, or SC000]. </p>
 <p>This function reads the Interrupt Active Register (NVIC_IABR0-NVIC_IABR7) in NVIC and returns the active bit of the interrupt <em>IRQn</em>.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -983,6 +928,8 @@ Mainline </th><th>Description  </th></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Get a device specific interrupt enable status. </p>
 <p>This function returns the interrupt enable status for the specified device specific interrupt <em>IRQn</em>. <em>IRQn</em> cannot be a negative value.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -1021,6 +968,8 @@ Mainline </th><th>Description  </th></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Get the pending device specific interrupt. </p>
 <p>This function returns the pending status of the specified device specific interrupt <em>IRQn</em>.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -1059,6 +1008,8 @@ Mainline </th><th>Description  </th></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Get the priority of an interrupt. </p>
 <p>This function reads the priority for the specified interrupt <em>IRQn</em>. <em>IRQn</em> can can specify any device specific interrupt, or processor exception.</p>
 <p>The returned priority value is automatically aligned to the implemented priority bits of the microcontroller.</p>
 <dl class="params"><dt>Parameters</dt><dd>
@@ -1094,6 +1045,8 @@ Mainline </th><th>Description  </th></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Read the priority grouping [not for Cortex-M0, Cortex-M0+, or SC000]. </p>
 <p>This function returns the priority grouping (flag PRIGROUP in AIRCR[10:8]).</p>
 <dl class="section return"><dt>Returns</dt><dd>Priority grouping field</dd></dl>
 <dl class="section remark"><dt>Remarks</dt><dd><ul>
@@ -1122,6 +1075,8 @@ Mainline </th><th>Description  </th></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Get Interrupt Target State. </p>
 <p>Reads the interrupt target field from the non-secure NVIC when in secure state. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -1158,6 +1113,8 @@ Mainline </th><th>Description  </th></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Read Interrupt Vector [not for Cortex-M0, SC000]. </p>
 <p>This function allows to read the address of an interrupt handler function.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -1191,6 +1148,8 @@ Mainline </th><th>Description  </th></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Set a device specific interrupt to pending. </p>
 <p>This function sets the pending bit for the specified device specific interrupt <em>IRQn</em>. <em>IRQn</em> cannot be a negative value.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -1234,6 +1193,8 @@ Mainline </th><th>Description  </th></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Set the priority for an interrupt. </p>
 <p>Sets the priority for the interrupt specified by <em>IRQn</em>.<em>IRQn</em> can can specify any device specific interrupt, or processor exception. The <em>priority</em> specifies the interrupt priority value, whereby lower values indicate a higher priority. The default priority is 0 for every interrupt. This is the highest possible priority.</p>
 <p>The priority cannot be set for every core interrupt. HardFault and NMI have a fixed (negative) priority that is higher than any configurable exception or interrupt.</p>
 <dl class="params"><dt>Parameters</dt><dd>
@@ -1281,6 +1242,8 @@ Mainline </th><th>Description  </th></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Set priority grouping [not for Cortex-M0, Cortex-M0+, or SC000]. </p>
 <p>The function sets the priority grouping <em>PriorityGroup</em> using the required unlock sequence. <em>PriorityGroup</em> is assigned to the field PRIGROUP (register AIRCR[10:8]). This field determines the split of group priority from subpriority. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -1314,6 +1277,8 @@ Mainline </th><th>Description  </th></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Set Interrupt Target State. </p>
 <p>Sets the interrupt target field in the non-secure NVIC when in secure state. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -1360,6 +1325,8 @@ Mainline </th><th>Description  </th></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Modify Interrupt Vector [not for Cortex-M0, SC000]. </p>
 <p>This function allows to change the address of an interrupt handler function.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -1396,6 +1363,8 @@ Mainline </th><th>Description  </th></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Reset the system. </p>
 <p>This function requests a system reset by setting the SYSRESETREQ flag in the AIRCR register.</p>
 <dl class="section remark"><dt>Remarks</dt><dd><ul>
 <li>In most microcontroller designs, setting the SYSRESETREQ flag resets the processor and most parts of the system, but should not affect the debug system.</li>
@@ -1413,7 +1382,7 @@ Mainline </th><th>Description  </th></tr>
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:25 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Core/html/group__SysTick__gr.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
-   &#160;<span id="projectnumber">Version 5.3.0</span>
+   &#160;<span id="projectnumber">Version 5.4.0</span>
    </div>
    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
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@@ -124,6 +124,7 @@ Functions</h2></td></tr>
 <tr class="separator:gabe47de40e9b0ad465b752297a9d9f427"><td class="memSeparator" colspan="2">&#160;</td></tr>
 </table>
 <a name="details" id="details"></a><h2 class="groupheader">Description</h2>
+<p>Initialize and start the SysTick timer. </p>
 <p>The System Tick Time (SysTick) generates interrupt requests on a regular basis. This allows an OS to carry out context switching to support multiple tasking. For applications that do not require an OS, the SysTick can be used for time keeping, time measurement, or as an interrupt source for tasks that need to be executed regularly.</p>
 <h1><a class="anchor" id="SysTick_code_ex_sec"></a>
 Code Example</h1>
@@ -161,6 +162,8 @@ Code Example</h1>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>System Tick Timer Configuration. </p>
 <p>Initialises and starts the System Tick Timer and its interrupt. After this call, the SysTick timer creates interrupts with the specified time interval. Counter is in free running mode to generate periodical interrupts.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -171,7 +174,7 @@ Code Example</h1>
 <dl class="section return"><dt>Returns</dt><dd>0 - success </dd>
 <dd>
 1 - failure</dd></dl>
-<dl class="section note"><dt>Note</dt><dd>When <b>#define __Vendor_SysTickConfig</b> is set to 1, the standard function <b>SysTick_Config</b> is excluded. In this case, the file <b><em>device</em>.h</b> must contain a vendor specific implementation of this function. </dd></dl>
+<dl class="section note"><dt>Note</dt><dd>When <a class="el" href="group__device__config.html#gab58771b4ec03f9bdddc84770f7c95c68">__Vendor_SysTickConfig</a> is defined to 1, the standard function <b>SysTick_Config</b> is excluded. In this case, the <a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> must contain a vendor specific implementation of this function. </dd></dl>
 
 </div>
 </div>
@@ -180,7 +183,7 @@ Code Example</h1>
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:25 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Core/html/group__cache__functions__m7.html

@@ -3,8 +3,8 @@
 <head>
 <meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
 <meta http-equiv="X-UA-Compatible" content="IE=9"/>
-<title>Cache Functions  (only Cortex-M7)</title>
-<title>CMSIS-Core (Cortex-M): Cache Functions  (only Cortex-M7)</title>
+<title>Cache Functions (Level-1)</title>
+<title>CMSIS-Core (Cortex-M): Cache Functions (Level-1)</title>
 <link href="tabs.css" rel="stylesheet" type="text/css"/>
 <link href="cmsis.css" rel="stylesheet" type="text/css" />
 <script type="text/javascript" src="jquery.js"></script>
@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
-   &#160;<span id="projectnumber">Version 5.3.0</span>
+   &#160;<span id="projectnumber">Version 5.4.0</span>
    </div>
    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
   </td>
@@ -110,24 +110,25 @@ $(document).ready(function(){initNavTree('group__cache__functions__m7.html','');
   <div class="summary">
 <a href="#groups">Content</a>  </div>
   <div class="headertitle">
-<div class="title">Cache Functions (only Cortex-M7)</div>  </div>
+<div class="title">Cache Functions (Level-1)</div>  </div>
 </div><!--header-->
 <div class="contents">
 
-<p>Functions for Instruction and Data Cache.  
+<p>Functions for level-1 instruction and data cache.  
 <a href="#details">More...</a></p>
 <table class="memberdecls">
 <tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="groups"></a>
 Content</h2></td></tr>
 <tr class="memitem:group__Icache__functions__m7"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Icache__functions__m7.html">I-Cache Functions</a></td></tr>
-<tr class="memdesc:group__Icache__functions__m7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Functions for the instruction cache. <br/></td></tr>
+<tr class="memdesc:group__Icache__functions__m7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Functions for the level-1 instruction cache. <br/></td></tr>
 <tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
 <tr class="memitem:group__Dcache__functions__m7"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__Dcache__functions__m7.html">D-Cache Functions</a></td></tr>
-<tr class="memdesc:group__Dcache__functions__m7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Functions for the data cache. <br/></td></tr>
+<tr class="memdesc:group__Dcache__functions__m7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Functions for the level-1 data cache. <br/></td></tr>
 <tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
 </table>
 <a name="details" id="details"></a><h2 class="groupheader">Description</h2>
-<p>Cortex-M7 processors include a memory system, which includes an optional MPU and Harvard data and instruction cache with ECC. The optional CPU cache has an instruction and data cache with sizes of <span class="XML-Token">[0;4;8;16;32;64]KB</span>. Both instruction and data cache RAM can be configured at implementation time to have Error Correcting Code (ECC) to protect the data stored in the memory from errors.</p>
+<p>Functions for level-1 instruction and data cache. </p>
+<p>Enhanced Cortex processors (like M7 and M55) include a memory system, which includes an optional Harvard level-1 data and instruction cache with ECC. The optional CPU cache has an instruction and data cache with sizes of <span class="XML-Token">[0;4;8;16;32;64]KB</span>. Both instruction and data cache RAM can be configured at implementation time to have Error Correcting Code (ECC) to protect the data stored in the memory from errors.</p>
 <p>All cache maintenance operations are executed by writing to registers in the memory mapped System Control Space (SCS) region of the internal PPB memory space.</p>
 <dl class="section note"><dt>Note</dt><dd>After reset, you must invalidate each cache before enabling it.</dd></dl>
 <p>The functions are grouped for:</p>
@@ -140,7 +141,7 @@ Content</h2></td></tr>
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:26 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Core/html/group__compiler__conntrol__gr.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
-   &#160;<span id="projectnumber">Version 5.3.0</span>
+   &#160;<span id="projectnumber">Version 5.4.0</span>
    </div>
    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
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@@ -202,6 +202,7 @@ Macros</h2></td></tr>
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 </table>
 <a name="details" id="details"></a><h2 class="groupheader">Description</h2>
+<p>Compiler agnostic #define symbols for generic C/C++ source code. </p>
 <p>The CMSIS-Core provides the header file <b>cmsis_compiler.h</b> with consistent #define symbols for generate C or C++ source files that should be compiler agnostic. Each CMSIS compliant compiler should support the functionality described in this section.</p>
 <p>The header file <b>cmsis_compiler.h</b> is also included by each <a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> so that these definitions are available. </p>
 <h2 class="groupheader">Macro Definition Documentation</h2>
@@ -214,6 +215,8 @@ Macros</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Minimum alignment for a variable. </p>
 <p>Specifies a minimum alignment for a variable or structure field, measured in bytes.</p>
 <p><b>Code Example:</b> </p>
 <div class="fragment"><div class="line">uint32_t stack_space[0x100] <a class="code" href="group__compiler__conntrol__gr.html#ga0c58caa5a273e2c21924509a45f8b849">__ALIGNED</a>(8);   <span class="comment">// 8-byte alignment required</span></div>
@@ -229,6 +232,8 @@ Macros</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Set to 1 when generating code for Armv6-M (Cortex-M0, Cortex-M1) </p>
 <p>The <b>#define <b>ARM_ARCH_6M</b></b> is set to 1 when generating code for the Armv6-M architecture. This architecture is for example used by the Cortex-M0, Cortex-M0+, and Cortex-M1 processor. </p>
 
 </div>
@@ -242,6 +247,8 @@ Macros</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Set to 1 when generating code for Armv7-M (Cortex-M4) with FPU. </p>
 <p>The <b>#define <b>ARM_ARCH_7EM</b></b> is set to 1 when generating code for the Armv7-M architecture with floating point extension. This architecture is for example used by the Cortex-M4 processor with FPU </p>
 
 </div>
@@ -255,6 +262,8 @@ Macros</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Set to 1 when generating code for Armv7-M (Cortex-M3) </p>
 <p>The <b>#define <b>ARM_ARCH_7M</b></b> is set to 1 when generating code for the Armv7-M architecture. This architecture is for example used by the Cortex-M3 processor. </p>
 
 </div>
@@ -268,6 +277,8 @@ Macros</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Set to 1 when generating code for Armv8-M Baseline. </p>
 <p>The <b>#define <b>ARM_ARCH_8M_BASE</b></b> is set to 1 when generating code for the Armv8-M architecture baseline variant. </p>
 
 </div>
@@ -281,6 +292,8 @@ Macros</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Set to 1 when generating code for Armv8-M Mainline. </p>
 <p>The <b>#define <b>ARM_ARCH_8M_MAIN</b></b> is set to 1 when generating code for the Armv8-M architecture mainline variant. </p>
 
 </div>
@@ -294,6 +307,8 @@ Macros</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Pass information from the compiler to the assembler. </p>
 <p>The <b>__ASM</b> keyword can declare or define an embedded assembly function or incorporate inline assembly into a function (shown in the code example below).</p>
 <p><b>Code Example:</b> </p>
 <div class="fragment"><div class="line"><span class="comment">// Reverse bit order of value</span></div>
@@ -317,6 +332,8 @@ Macros</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Barrier to prevent compiler from reordering instructions. </p>
 <p>This barrier limits the compilers reordering optimizations. It prevents the compiler from swapping instructions resulting from code before and after the barrier.</p>
 <p><b>Code Example:</b> The assignments in the example are independent. Hence the compiler could choose a different order of execution, e.g. for a better pipeline utilization. Using the barrier in between prevents this type of reordering.</p>
 <div class="fragment"><div class="line"><span class="keywordtype">void</span> test (uint8_t *ptr) {</div>
@@ -336,6 +353,8 @@ Macros</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Compiler/linker symbol specifiying the location of the main stack (MSP). </p>
 <p>The address of the specified symbol is used to initialize the main stack pointer (MSP) during low level init. This is compiler/linker specific. CMSIS specifies common default for supported compilers.</p>
 <dl class="section note"><dt>Note</dt><dd>This define is only intended to be used by the <a class="el" href="startup_c_pg.html">Startup File startup_&lt;device&gt;.c</a>. </dd></dl>
 
@@ -350,6 +369,8 @@ Macros</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Recommend that function should be inlined by the compiler. </p>
 <p>Inline functions offer a trade-off between code size and performance. By default, the compiler decides during optimization whether to inline code or not. The <b>__INLINE</b> attribute gives the compiler an hint to inline this function. Still, the compiler may decide not to inline the function. As the function is global an callable function is also generated.</p>
 <p><b>Code Example:</b> </p>
 <div class="fragment"><div class="line"><span class="keyword">const</span> uint32_t led_mask[] = {1U &lt;&lt; 4, 1U &lt;&lt; 5, 1U &lt;&lt; 6, 1U &lt;&lt; 7};</div>
@@ -373,6 +394,8 @@ Macros</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Inform the compiler that a function does not return. </p>
 <p>Informs the compiler that the function does not return. The compiler can then perform optimizations by removing code that is never reached.</p>
 <p><b>Code Example:</b> </p>
 <div class="fragment"><div class="line"><span class="comment">// OS idle demon (running when no other thread is ready to run).</span></div>
@@ -390,6 +413,8 @@ Macros</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Request smallest possible alignment. </p>
 <p>Specifies that a type must have the smallest possible alignment.</p>
 <p><b>Code Example:</b> </p>
 <div class="fragment"><div class="line"><span class="keyword">struct </span>foo {</div>
@@ -408,6 +433,8 @@ Macros</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Request smallest possible alignment for a structure. </p>
 <p>Specifies that a structure must have the smallest possible alignment.</p>
 <p><b>Code Example:</b> </p>
 <div class="fragment"><div class="line"><a class="code" href="group__compiler__conntrol__gr.html#ga4dbb70fab85207c27b581ecb6532b314">__PACKED_STRUCT</a> foo {</div>
@@ -427,6 +454,8 @@ Macros</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Entry function into the user application or library startup. </p>
 <p>Gives the function to be jumped into right after low level initialization, i.e. SystemInit. This is compiler and library specific. CMSIS specifies common default for supported compilers.</p>
 <dl class="section note"><dt>Note</dt><dd>This define is only intended to be used by the <a class="el" href="startup_c_pg.html">Startup File startup_&lt;device&gt;.c</a>.</dd></dl>
 <p><b>Code Example:</b> </p>
@@ -447,6 +476,8 @@ Macros</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>restrict pointer qualifier to enable additional optimizations. </p>
 <p>The __RESTRICT keyword corresponds to the <b>restrict</b> pointer qualifier that has been introduced in C99. __RESTRICT is a hint to the compiler that enables additional optimizations. It specifies that for the lifetime of the pointer, only the pointer itself or a value directly derived from it (such as pointer + 1) is used to access the object. The compiler may therefore ignore potential pointer aliasing effects and perform additional optimizations.</p>
 <dl class="section note"><dt>Note</dt><dd>For compilers that do not support the restrict keyword, __RESTRICT is defined as an empty macro and a warning is issued.</dd></dl>
 <p><b>Code Example:</b> </p>
@@ -470,6 +501,8 @@ Macros</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Compiler/linker symbol specifiying the limit of the main stack (MSP). </p>
 <p>The address of the specified symbol is used to initialize the main stack pointer limit (MSPLIM on Armv8-M) during low level init. This is compiler/linker specific. CMSIS specifies common default for supported compilers.</p>
 <dl class="section note"><dt>Note</dt><dd>This define is only intended to be used by the <a class="el" href="startup_c_pg.html">Startup File startup_&lt;device&gt;.c</a>.</dd></dl>
 <p><b>Code Example:</b> </p>
@@ -491,6 +524,8 @@ Macros</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Define a static function that should be always inlined by the compiler. </p>
 <p>Defines a static function that should be always inlined by the compiler.</p>
 <dl class="section note"><dt>Note</dt><dd>For compilers that do not allow to force function inlining, the macro maps to <a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a>.</dd></dl>
 <p><b>Code Example:</b> </p>
@@ -512,6 +547,8 @@ Macros</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Define a static function that may be inlined by the compiler. </p>
 <p>Defines a static function that may be inlined by the compiler. If the compiler generates inline code for all calls to this functions, no additional function implementation is generated which may further optimize space.</p>
 <p><b>Code Example:</b> </p>
 <div class="fragment"><div class="line">\\ Get Interrupt Vector</div>
@@ -532,6 +569,8 @@ Macros</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Pointer for unaligned read of a uint16_t variable. </p>
 <p>Defines a pointer to a uint16_t from an address that does not need to be aligned. This can then be used in read operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm processor core and compiler settings.</p>
 <p><b>Code Example:</b> </p>
 <div class="fragment"><div class="line">uint16_t val16;</div>
@@ -551,6 +590,8 @@ Macros</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Pointer for unaligned write of a uint16_t variable. </p>
 <p>Defines a pointer to a uint16_t from an address that does not need to be aligned. This can then be used in write operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm processor core and compiler settings.</p>
 <p><b>Code Example:</b> </p>
 <div class="fragment"><div class="line">uint16_t val16 = 0U;</div>
@@ -570,6 +611,8 @@ Macros</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Pointer for unaligned access of a uint32_t variable. </p>
 <dl class="deprecated"><dt><b><a class="el" href="deprecated.html#_deprecated000001">Deprecated:</a></b></dt><dd>Do not use this macro. It has been superseded by <a class="el" href="group__compiler__conntrol__gr.html#ga254322c344d954c9f829719a50a88e87">__UNALIGNED_UINT32_READ</a>, <a class="el" href="group__compiler__conntrol__gr.html#gabb2180285c417aa9120a360c51f64b4b">__UNALIGNED_UINT32_WRITE</a> and will be removed in the future.</dd></dl>
 <p>Defines a pointer to a uint32_t from an address that does not need to be aligned. This can then be used in read/write operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm processor core and compiler settings.</p>
 <p><b>Code Example:</b> </p>
@@ -590,6 +633,8 @@ Macros</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Pointer for unaligned read of a uint32_t variable. </p>
 <p>Defines a pointer to a uint32_t from an address that does not need to be aligned. This can then be used in read operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm processor core and compiler settings.</p>
 <p><b>Code Example:</b> </p>
 <div class="fragment"><div class="line">uint32_t val32;</div>
@@ -609,6 +654,8 @@ Macros</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Pointer for unaligned write of a uint32_t variable. </p>
 <p>Defines a pointer to a uint32_t from an address that does not need to be aligned. This can then be used in write operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm processor core and compiler settings.</p>
 <p><b>Code Example:</b> </p>
 <div class="fragment"><div class="line">uint32_t val32 = 0U;</div>
@@ -628,6 +675,8 @@ Macros</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Inform that a variable shall be retained in executable image. </p>
 <p>Definitions tagged with <b>__USED</b> in the source code should be not removed by the linker when detected as unused.</p>
 <p><b>Code Example:</b> </p>
 <div class="fragment"><div class="line"><span class="comment">/* Export following variables for debugging */</span></div>
@@ -647,6 +696,8 @@ Macros</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Symbol name used for the (static) interrupt vector table. </p>
 <p>The given name is used for defining the static (compiler time) interrupt vector table. The name must comply with any compiler/linker conventions, e.g. if used for vector table relocation or debugger awareness. CMSIS specifies common default for supported compilers.</p>
 <dl class="section note"><dt>Note</dt><dd>This define is only intended to be used by the <a class="el" href="startup_c_pg.html">Startup File startup_&lt;device&gt;.c</a>. </dd></dl>
 
@@ -661,6 +712,8 @@ Macros</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Additional decl specs to be used when defining the (static) interrupt vector table. </p>
 <p>The given decl specs are used for defining the static (compiler time) interrupt vector table, e.g. to mark the table as used and force it into a specific linker section. CMSIS specifies common default for supported compilers.</p>
 <dl class="section note"><dt>Note</dt><dd>This define is only intended to be used by the <a class="el" href="startup_c_pg.html">Startup File startup_&lt;device&gt;.c</a>. </dd></dl>
 
@@ -675,6 +728,8 @@ Macros</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Export a function or variable weakly to allow overwrites. </p>
 <p>Functions defined with <b>__WEAK</b> export their symbols weakly. A weakly defined function behaves like a normally defined function unless a non-weakly defined function of the same name is linked into the same image. If both a non-weakly defined function and a weakly defined function exist in the same image then all calls to the function resolve to call the non-weak function.</p>
 <p>Functions declared with <b>__WEAK</b> and then defined without <b>__WEAK</b> behave as non-weak functions.</p>
 <p><b>Code Example:</b> </p>
@@ -691,7 +746,7 @@ Macros</h2></td></tr>
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:25 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:07 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Core/html/group__context__trustzone__functions.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
-   &#160;<span id="projectnumber">Version 5.3.0</span>
+   &#160;<span id="projectnumber">Version 5.4.0</span>
    </div>
    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
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@@ -136,6 +136,7 @@ Functions</h2></td></tr>
 <tr class="separator:gac106570f4905f82922fd335aeb08a1bf"><td class="memSeparator" colspan="2">&#160;</td></tr>
 </table>
 <a name="details" id="details"></a><h2 class="groupheader">Description</h2>
+<p>RTOS Thread Context Management for Armv8-M TrustZone. </p>
 <p>The CMSIS-Core provides the file <b>tz_context.h</b> which defines an API to standardize the context memory system for real-time operating systems. For more information refer to <a class="el" href="using_TrustZone_pg.html#RTOS_TrustZone">RTOS Thread Context Management</a>. </p>
 <h2 class="groupheader">Function Documentation</h2>
 <a class="anchor" id="gacd016f166bee549a0d3e970132e64a90"></a>
@@ -151,6 +152,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Allocate context memory for calling secure software modules in TrustZone. </p>
 <p>Allocates the secure memory regions for thread execution. The parameter <em>module</em> describes the set of secure functions that are called by the non-secure thread. Set <em>module</em> to zero if no secure calls are used/allowed. This leads to no secure memory to be assigned which results in zero being returned as memory id as well. This function should be called by an RTOS kernel at the start of a thread. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -177,6 +180,8 @@ value 0 no memory available or internal error </dd></dl>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Free context memory that was previously allocated with <a class="el" href="group__context__trustzone__functions.html#gacd016f166bee549a0d3e970132e64a90">TZ_AllocModuleContext_S</a>. </p>
 <p>De-allocates the secure memory regions. The parameter <em>id</em> refers to a TrustZone memory slot that has been obtained with <a class="el" href="group__context__trustzone__functions.html#gacd016f166bee549a0d3e970132e64a90">TZ_AllocModuleContext_S</a>. This function should be called by an RTOS kernel at the termination of a thread. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -201,6 +206,8 @@ value 0 no memory available or internal error </dd></dl>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Initialize secure context memory system. </p>
 <p>Initializes the memory allocation management for the secure memory regions. As a minimum the secure thread mode stack will be provided. </p>
 <dl class="section return"><dt>Returns</dt><dd>execution status (1: success, 0: error) </dd></dl>
 
@@ -219,6 +226,8 @@ value 0 no memory available or internal error </dd></dl>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Load secure context (called on RTOS thread context switch) </p>
 <p>Prepare the secure context for execution so that a thread in the non-secure state can call secure library modules. The parameter <em>id</em> refers to a TrustZone memory slot that has been obtained with <a class="el" href="group__context__trustzone__functions.html#gacd016f166bee549a0d3e970132e64a90">TZ_AllocModuleContext_S</a> which might be zero if not used. This function should be called by an RTOS kernel at thread context switch before running a thread. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -243,6 +252,8 @@ value 0 no memory available or internal error </dd></dl>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Store secure context (called on RTOS thread context switch) </p>
 <p>Free the secure context that has been previously loaded with <a class="el" href="group__context__trustzone__functions.html#ga4748f6bcdd5fed279ac5a6cd7eca2689">TZ_LoadContext_S</a>. The parameter <em>id</em> refers to a TrustZone memory slot that has been obtained with <a class="el" href="group__context__trustzone__functions.html#gacd016f166bee549a0d3e970132e64a90">TZ_AllocModuleContext_S</a> which might be zero if not used. This function should be called by an RTOS kernel at thread context switch after running a thread. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -259,7 +270,7 @@ value 0 no memory available or internal error </dd></dl>
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:26 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Core/html/group__coreregister__trustzone__functions.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
-   &#160;<span id="projectnumber">Version 5.3.0</span>
+   &#160;<span id="projectnumber">Version 5.4.0</span>
    </div>
    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
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@@ -175,6 +175,7 @@ Functions</h2></td></tr>
 <tr class="separator:gad2013f4d4311d6db253594a12d192617"><td class="memSeparator" colspan="2">&#160;</td></tr>
 </table>
 <a name="details" id="details"></a><h2 class="groupheader">Description</h2>
+<p>Core register Access functions related to TrustZone for Armv8-M. </p>
 <h2 class="groupheader">Function Documentation</h2>
 <a class="anchor" id="ga624509c924d2583f0d4dca6ab270f051"></a>
 <div class="memitem">
@@ -189,6 +190,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Get Base Priority (non-secure) </p>
 <p>Returns the current value of the non-secure Base Priority register when in secure state. </p>
 <dl class="section return"><dt>Returns</dt><dd>Base Priority register value </dd></dl>
 <dl class="section see"><dt>See Also</dt><dd><ul>
@@ -211,6 +214,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Get Control register (non-secure) </p>
 <p>Returns the content of the non-secure Control register when in secure mode. </p>
 <dl class="section return"><dt>Returns</dt><dd>non-secure Control register value </dd></dl>
 <dl class="section see"><dt>See Also</dt><dd><ul>
@@ -233,6 +238,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Get Fault Mask (non-secure) </p>
 <p>Returns the current value of the non-secure Fault Mask register when in secure state. </p>
 <dl class="section return"><dt>Returns</dt><dd>Fault Mask register value </dd></dl>
 <dl class="section see"><dt>See Also</dt><dd><ul>
@@ -255,6 +262,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Get Main Stack Pointer (non-secure) </p>
 <p>Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. </p>
 <dl class="section return"><dt>Returns</dt><dd>MSP register value </dd></dl>
 <dl class="section see"><dt>See Also</dt><dd><ul>
@@ -277,6 +286,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Get Main Stack Pointer Limit (non-secure) Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always. </p>
 <p>Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. </p>
 <dl class="section return"><dt>Returns</dt><dd>MSPLIM register value </dd></dl>
 
@@ -295,6 +306,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Get Priority Mask (non-secure) </p>
 <p>Returns the current state of the non-secure priority mask bit from the Priority Mask register when in secure state. </p>
 <dl class="section return"><dt>Returns</dt><dd>Priority Mask value </dd></dl>
 <dl class="section see"><dt>See Also</dt><dd><ul>
@@ -317,6 +330,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Get Process Stack Pointer (non-secure) </p>
 <p>Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. </p>
 <dl class="section return"><dt>Returns</dt><dd>PSP register value </dd></dl>
 <dl class="section see"><dt>See Also</dt><dd><ul>
@@ -339,6 +354,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Get Process Stack Pointer Limit (non-secure) Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always. </p>
 <p>Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. </p>
 <dl class="section return"><dt>Returns</dt><dd>PSPLIM register value </dd></dl>
 
@@ -357,6 +374,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Get Stack Pointer (non-secure) </p>
 <p>Returns the current value of the non-secure Stack Pointer (SP) when in secure state. </p>
 <dl class="section return"><dt>Returns</dt><dd>SP register value </dd></dl>
 
@@ -375,6 +394,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Set Base Priority (non-secure) </p>
 <p>Assigns the given value to the non-secure Base Priority register when in secure state. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -402,6 +423,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Set Control register (non-secure) </p>
 <p>Writes the given value to the non-secure Control register when in secure state. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -429,6 +452,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Set Fault Mask (non-secure) </p>
 <p>Assigns the given value to the non-secure Fault Mask register when in secure state. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -456,6 +481,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Set Main Stack Pointer (non-secure) </p>
 <p>Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -483,6 +510,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Set Main Stack Pointer Limit (non-secure) Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always. </p>
 <p>Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -506,6 +535,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Set Priority Mask (non-secure) </p>
 <p>Assigns the given value to the non-secure Priority Mask register when in secure state. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -533,6 +564,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Set Process Stack Pointer (non-secure) </p>
 <p>Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -560,6 +593,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Set Process Stack Pointer (non-secure) Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always. </p>
 <p>Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -583,6 +618,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
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+
+<p>Set Stack Pointer (non-secure) </p>
 <p>Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -598,7 +635,7 @@ Functions</h2></td></tr>
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:25 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
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docs/Core/html/group__device__config.html

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+<title>Device capabilitiy defines</title>
+<title>CMSIS-Core (Cortex-M): Device capabilitiy defines</title>
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+<link href="cmsis.css" rel="stylesheet" type="text/css" />
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+  <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-Core (Cortex-M)
+   &#160;<span id="projectnumber">Version 5.4.0</span>
+   </div>
+   <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
+  </td>
+ </tr>
+ </tbody>
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+        name="MSearchResults" id="MSearchResults">
+</iframe>
+</div>
+
+<div class="header">
+  <div class="summary">
+<a href="#define-members">Macros</a>  </div>
+  <div class="headertitle">
+<div class="title">Device capabilitiy defines</div>  </div>
+</div><!--header-->
+<div class="contents">
+
+<p>Defines to configure and check device capabilities.  
+<a href="#details">More...</a></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
+Macros</h2></td></tr>
+<tr class="memitem:ga905517438930a3f13cbc632e52990534"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__device__config.html#ga905517438930a3f13cbc632e52990534">__CM0_REV</a></td></tr>
+<tr class="memdesc:ga905517438930a3f13cbc632e52990534"><td class="mdescLeft">&#160;</td><td class="mdescRight">Cortex-M0 Core revision r0p1.  <a href="#ga905517438930a3f13cbc632e52990534">More...</a><br/></td></tr>
+<tr class="separator:ga905517438930a3f13cbc632e52990534"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga2b7180ed347a0e902c5765deb46e650e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__device__config.html#ga2b7180ed347a0e902c5765deb46e650e">__CM0PLUS_REV</a></td></tr>
+<tr class="memdesc:ga2b7180ed347a0e902c5765deb46e650e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Cortex-M0+ Core revision r0p1.  <a href="#ga2b7180ed347a0e902c5765deb46e650e">More...</a><br/></td></tr>
+<tr class="separator:ga2b7180ed347a0e902c5765deb46e650e"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga71248e1e7db00ff28754b6fd80807654"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__device__config.html#ga71248e1e7db00ff28754b6fd80807654">__CM1_REV</a></td></tr>
+<tr class="memdesc:ga71248e1e7db00ff28754b6fd80807654"><td class="mdescLeft">&#160;</td><td class="mdescRight">Cortex-M1 Core revision r0p1.  <a href="#ga71248e1e7db00ff28754b6fd80807654">More...</a><br/></td></tr>
+<tr class="separator:ga71248e1e7db00ff28754b6fd80807654"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gac6a3f185c4640e06443c18b3c8d93f53"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__device__config.html#gac6a3f185c4640e06443c18b3c8d93f53">__CM3_REV</a></td></tr>
+<tr class="memdesc:gac6a3f185c4640e06443c18b3c8d93f53"><td class="mdescLeft">&#160;</td><td class="mdescRight">Cortex-M3 Core revision r0p1.  <a href="#gac6a3f185c4640e06443c18b3c8d93f53">More...</a><br/></td></tr>
+<tr class="separator:gac6a3f185c4640e06443c18b3c8d93f53"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga45a97e4bb8b6ce7c334acc5f45ace3ba"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__device__config.html#ga45a97e4bb8b6ce7c334acc5f45ace3ba">__CM4_REV</a></td></tr>
+<tr class="memdesc:ga45a97e4bb8b6ce7c334acc5f45ace3ba"><td class="mdescLeft">&#160;</td><td class="mdescRight">Cortex-M4 Core revision r0p1.  <a href="#ga45a97e4bb8b6ce7c334acc5f45ace3ba">More...</a><br/></td></tr>
+<tr class="separator:ga45a97e4bb8b6ce7c334acc5f45ace3ba"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga8eb40c0d30a09a0ae388e56b21d8f22c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__device__config.html#ga8eb40c0d30a09a0ae388e56b21d8f22c">__CM7_REV</a></td></tr>
+<tr class="memdesc:ga8eb40c0d30a09a0ae388e56b21d8f22c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Cortex-M7 Core revision r0p1.  <a href="#ga8eb40c0d30a09a0ae388e56b21d8f22c">More...</a><br/></td></tr>
+<tr class="separator:ga8eb40c0d30a09a0ae388e56b21d8f22c"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gaf293b060f9c15592d18e6b0b977194bf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__device__config.html#gaf293b060f9c15592d18e6b0b977194bf">__SC000_REV</a></td></tr>
+<tr class="memdesc:gaf293b060f9c15592d18e6b0b977194bf"><td class="mdescLeft">&#160;</td><td class="mdescRight">SC000 Core revision r0p1.  <a href="#gaf293b060f9c15592d18e6b0b977194bf">More...</a><br/></td></tr>
+<tr class="separator:gaf293b060f9c15592d18e6b0b977194bf"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga3029728b4fc64727b43bcfd853a7180b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__device__config.html#ga3029728b4fc64727b43bcfd853a7180b">__SC300_REV</a></td></tr>
+<tr class="memdesc:ga3029728b4fc64727b43bcfd853a7180b"><td class="mdescLeft">&#160;</td><td class="mdescRight">SC300 Core revision r0p1.  <a href="#ga3029728b4fc64727b43bcfd853a7180b">More...</a><br/></td></tr>
+<tr class="separator:ga3029728b4fc64727b43bcfd853a7180b"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga0f6c2b504ee424a7895fd7a420acdd0e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__device__config.html#ga0f6c2b504ee424a7895fd7a420acdd0e">__CM23_REV</a></td></tr>
+<tr class="memdesc:ga0f6c2b504ee424a7895fd7a420acdd0e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Cortex-M23 Core revision r0p1.  <a href="#ga0f6c2b504ee424a7895fd7a420acdd0e">More...</a><br/></td></tr>
+<tr class="separator:ga0f6c2b504ee424a7895fd7a420acdd0e"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga178e7a57b608f3e20d1c0cf18a2c2ac3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__device__config.html#ga178e7a57b608f3e20d1c0cf18a2c2ac3">__CM33_REV</a></td></tr>
+<tr class="memdesc:ga178e7a57b608f3e20d1c0cf18a2c2ac3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Cortex-M33 Core revision r0p1.  <a href="#ga178e7a57b608f3e20d1c0cf18a2c2ac3">More...</a><br/></td></tr>
+<tr class="separator:ga178e7a57b608f3e20d1c0cf18a2c2ac3"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gadd339c07b13a763dda6e83f4c05122f6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__device__config.html#gadd339c07b13a763dda6e83f4c05122f6">__CM35P_REV</a></td></tr>
+<tr class="memdesc:gadd339c07b13a763dda6e83f4c05122f6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Cortex-M35P Core revision r0p1.  <a href="#gadd339c07b13a763dda6e83f4c05122f6">More...</a><br/></td></tr>
+<tr class="separator:gadd339c07b13a763dda6e83f4c05122f6"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gaea2d16e963063038cde86cee33c4ef37"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__device__config.html#gaea2d16e963063038cde86cee33c4ef37">__CM55_REV</a></td></tr>
+<tr class="memdesc:gaea2d16e963063038cde86cee33c4ef37"><td class="mdescLeft">&#160;</td><td class="mdescRight">Cortex-M55 Core revision r0p1.  <a href="#gaea2d16e963063038cde86cee33c4ef37">More...</a><br/></td></tr>
+<tr class="separator:gaea2d16e963063038cde86cee33c4ef37"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga645c9be694a2d5b5a5b772a0102c727a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__device__config.html#ga645c9be694a2d5b5a5b772a0102c727a">__ARMv8MBL_REV</a></td></tr>
+<tr class="memdesc:ga645c9be694a2d5b5a5b772a0102c727a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Armv8-M Baseline device Core revision r0p1.  <a href="#ga645c9be694a2d5b5a5b772a0102c727a">More...</a><br/></td></tr>
+<tr class="separator:ga645c9be694a2d5b5a5b772a0102c727a"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gadb7d425f5ad0389b0eb1c6a69f8eb214"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__device__config.html#gadb7d425f5ad0389b0eb1c6a69f8eb214">__ARMv8MML_REV</a></td></tr>
+<tr class="memdesc:gadb7d425f5ad0389b0eb1c6a69f8eb214"><td class="mdescLeft">&#160;</td><td class="mdescRight">Armv8-M Mainline device Core revision r0p1.  <a href="#gadb7d425f5ad0389b0eb1c6a69f8eb214">More...</a><br/></td></tr>
+<tr class="separator:gadb7d425f5ad0389b0eb1c6a69f8eb214"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga4dd7b69d473733e59cd99fc786174cd3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__device__config.html#ga4dd7b69d473733e59cd99fc786174cd3">__ARMv81MML_REV</a></td></tr>
+<tr class="memdesc:ga4dd7b69d473733e59cd99fc786174cd3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Armv8.1-M Baseline device Core revision r0p1.  <a href="#ga4dd7b69d473733e59cd99fc786174cd3">More...</a><br/></td></tr>
+<tr class="separator:ga4dd7b69d473733e59cd99fc786174cd3"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gae3fe3587d5100c787e02102ce3944460"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__device__config.html#gae3fe3587d5100c787e02102ce3944460">__NVIC_PRIO_BITS</a></td></tr>
+<tr class="memdesc:gae3fe3587d5100c787e02102ce3944460"><td class="mdescLeft">&#160;</td><td class="mdescRight">Number of Bits used for Priority Levels.  <a href="#gae3fe3587d5100c787e02102ce3944460">More...</a><br/></td></tr>
+<tr class="separator:gae3fe3587d5100c787e02102ce3944460"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gab58771b4ec03f9bdddc84770f7c95c68"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__device__config.html#gab58771b4ec03f9bdddc84770f7c95c68">__Vendor_SysTickConfig</a></td></tr>
+<tr class="memdesc:gab58771b4ec03f9bdddc84770f7c95c68"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set to 1 if a venor specfic SysTick configuration is used.  <a href="#gab58771b4ec03f9bdddc84770f7c95c68">More...</a><br/></td></tr>
+<tr class="separator:gab58771b4ec03f9bdddc84770f7c95c68"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gaddbae1a1b57539f398eb5546a17de8f6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__device__config.html#gaddbae1a1b57539f398eb5546a17de8f6">__VTOR_PRESENT</a></td></tr>
+<tr class="memdesc:gaddbae1a1b57539f398eb5546a17de8f6"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTOR present or not.  <a href="#gaddbae1a1b57539f398eb5546a17de8f6">More...</a><br/></td></tr>
+<tr class="separator:gaddbae1a1b57539f398eb5546a17de8f6"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga4127d1b31aaf336fab3d7329d117f448"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__device__config.html#ga4127d1b31aaf336fab3d7329d117f448">__MPU_PRESENT</a></td></tr>
+<tr class="memdesc:ga4127d1b31aaf336fab3d7329d117f448"><td class="mdescLeft">&#160;</td><td class="mdescRight">MPU present or not.  <a href="#ga4127d1b31aaf336fab3d7329d117f448">More...</a><br/></td></tr>
+<tr class="separator:ga4127d1b31aaf336fab3d7329d117f448"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gac1ba8a48ca926bddc88be9bfd7d42641"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__device__config.html#gac1ba8a48ca926bddc88be9bfd7d42641">__FPU_PRESENT</a></td></tr>
+<tr class="memdesc:gac1ba8a48ca926bddc88be9bfd7d42641"><td class="mdescLeft">&#160;</td><td class="mdescRight">FPU present or not.  <a href="#gac1ba8a48ca926bddc88be9bfd7d42641">More...</a><br/></td></tr>
+<tr class="separator:gac1ba8a48ca926bddc88be9bfd7d42641"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga2a528de57b6217f9fc9d4487d0db6328"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__device__config.html#ga2a528de57b6217f9fc9d4487d0db6328">__FPU_DP</a></td></tr>
+<tr class="memdesc:ga2a528de57b6217f9fc9d4487d0db6328"><td class="mdescLeft">&#160;</td><td class="mdescRight">Double precision FPU present.  <a href="#ga2a528de57b6217f9fc9d4487d0db6328">More...</a><br/></td></tr>
+<tr class="separator:ga2a528de57b6217f9fc9d4487d0db6328"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga165f052f5641898a02bb07096dc177b6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__device__config.html#ga165f052f5641898a02bb07096dc177b6">__DSP_PRESENT</a></td></tr>
+<tr class="memdesc:ga165f052f5641898a02bb07096dc177b6"><td class="mdescLeft">&#160;</td><td class="mdescRight">DSP extension present or not.  <a href="#ga165f052f5641898a02bb07096dc177b6">More...</a><br/></td></tr>
+<tr class="separator:ga165f052f5641898a02bb07096dc177b6"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gadae9d54c744e525135b097c618bae3c4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__device__config.html#gadae9d54c744e525135b097c618bae3c4">__SAUREGION_PRESENT</a></td></tr>
+<tr class="memdesc:gadae9d54c744e525135b097c618bae3c4"><td class="mdescLeft">&#160;</td><td class="mdescRight">SAU regions present or not.  <a href="#gadae9d54c744e525135b097c618bae3c4">More...</a><br/></td></tr>
+<tr class="separator:gadae9d54c744e525135b097c618bae3c4"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga1c6eba273d4d6189eee91c6cbe7ec289"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__device__config.html#ga1c6eba273d4d6189eee91c6cbe7ec289">__PMU_PRESENT</a></td></tr>
+<tr class="memdesc:ga1c6eba273d4d6189eee91c6cbe7ec289"><td class="mdescLeft">&#160;</td><td class="mdescRight">PMU present or not.  <a href="#ga1c6eba273d4d6189eee91c6cbe7ec289">More...</a><br/></td></tr>
+<tr class="separator:ga1c6eba273d4d6189eee91c6cbe7ec289"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga9d4c51d9ca3eae58635d1040a3fb5fd2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__device__config.html#ga9d4c51d9ca3eae58635d1040a3fb5fd2">__PMU_NUM_EVENTCNT</a></td></tr>
+<tr class="memdesc:ga9d4c51d9ca3eae58635d1040a3fb5fd2"><td class="mdescLeft">&#160;</td><td class="mdescRight">PMU Event Counters.  <a href="#ga9d4c51d9ca3eae58635d1040a3fb5fd2">More...</a><br/></td></tr>
+<tr class="separator:ga9d4c51d9ca3eae58635d1040a3fb5fd2"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga3580fa1aeb7c2ed580904f8f70f8a919"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__device__config.html#ga3580fa1aeb7c2ed580904f8f70f8a919">__ICACHE_PRESENT</a></td></tr>
+<tr class="memdesc:ga3580fa1aeb7c2ed580904f8f70f8a919"><td class="mdescLeft">&#160;</td><td class="mdescRight">Instruction Cache present or not.  <a href="#ga3580fa1aeb7c2ed580904f8f70f8a919">More...</a><br/></td></tr>
+<tr class="separator:ga3580fa1aeb7c2ed580904f8f70f8a919"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga11d3ac679daeb58d0cec0a4e6ca59010"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__device__config.html#ga11d3ac679daeb58d0cec0a4e6ca59010">__DCACHE_PRESENT</a></td></tr>
+<tr class="memdesc:ga11d3ac679daeb58d0cec0a4e6ca59010"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Cache present or not.  <a href="#ga11d3ac679daeb58d0cec0a4e6ca59010">More...</a><br/></td></tr>
+<tr class="separator:ga11d3ac679daeb58d0cec0a4e6ca59010"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gacbb998663708df6626abb09378303019"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__device__config.html#gacbb998663708df6626abb09378303019">__DTCM_PRESENT</a></td></tr>
+<tr class="memdesc:gacbb998663708df6626abb09378303019"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Tightly Coupled Memory is present or not.  <a href="#gacbb998663708df6626abb09378303019">More...</a><br/></td></tr>
+<tr class="separator:gacbb998663708df6626abb09378303019"><td class="memSeparator" colspan="2">&#160;</td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
+<p>Defines to configure and check device capabilities. </p>
+<p>These defines are used by the <a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> in order to enable or disable functionality provided by CMSIS-Core(M) dependent on the device capabilities. </p>
+<h2 class="groupheader">Macro Definition Documentation</h2>
+<a class="anchor" id="ga4dd7b69d473733e59cd99fc786174cd3"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define __ARMv81MML_REV</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Armv8.1-M Baseline device Core revision r0p1. </p>
+<p>([15:8] revision number, [7:0] patch number) </p>
+
+</div>
+</div>
+<a class="anchor" id="ga645c9be694a2d5b5a5b772a0102c727a"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define __ARMv8MBL_REV</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Armv8-M Baseline device Core revision r0p1. </p>
+<p>([15:8] revision number, [7:0] patch number) </p>
+
+</div>
+</div>
+<a class="anchor" id="gadb7d425f5ad0389b0eb1c6a69f8eb214"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define __ARMv8MML_REV</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Armv8-M Mainline device Core revision r0p1. </p>
+<p>([15:8] revision number, [7:0] patch number) </p>
+
+</div>
+</div>
+<a class="anchor" id="ga905517438930a3f13cbc632e52990534"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define __CM0_REV</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Cortex-M0 Core revision r0p1. </p>
+<p>([15:8] revision number, [7:0] patch number) </p>
+
+</div>
+</div>
+<a class="anchor" id="ga2b7180ed347a0e902c5765deb46e650e"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define __CM0PLUS_REV</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Cortex-M0+ Core revision r0p1. </p>
+<p>([15:8] revision number, [7:0] patch number) </p>
+
+</div>
+</div>
+<a class="anchor" id="ga71248e1e7db00ff28754b6fd80807654"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define __CM1_REV</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Cortex-M1 Core revision r0p1. </p>
+<p>([15:8] revision number, [7:0] patch number) </p>
+
+</div>
+</div>
+<a class="anchor" id="ga0f6c2b504ee424a7895fd7a420acdd0e"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define __CM23_REV</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Cortex-M23 Core revision r0p1. </p>
+<p>([15:8] revision number, [7:0] patch number) </p>
+
+</div>
+</div>
+<a class="anchor" id="ga178e7a57b608f3e20d1c0cf18a2c2ac3"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define __CM33_REV</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Cortex-M33 Core revision r0p1. </p>
+<p>([15:8] revision number, [7:0] patch number) </p>
+
+</div>
+</div>
+<a class="anchor" id="gadd339c07b13a763dda6e83f4c05122f6"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define __CM35P_REV</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Cortex-M35P Core revision r0p1. </p>
+<p>([15:8] revision number, [7:0] patch number) </p>
+
+</div>
+</div>
+<a class="anchor" id="gac6a3f185c4640e06443c18b3c8d93f53"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define __CM3_REV</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Cortex-M3 Core revision r0p1. </p>
+<p>([15:8] revision number, [7:0] patch number) </p>
+
+</div>
+</div>
+<a class="anchor" id="ga45a97e4bb8b6ce7c334acc5f45ace3ba"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define __CM4_REV</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Cortex-M4 Core revision r0p1. </p>
+<p>([15:8] revision number, [7:0] patch number) </p>
+
+</div>
+</div>
+<a class="anchor" id="gaea2d16e963063038cde86cee33c4ef37"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define __CM55_REV</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Cortex-M55 Core revision r0p1. </p>
+<p>([15:8] revision number, [7:0] patch number) </p>
+
+</div>
+</div>
+<a class="anchor" id="ga8eb40c0d30a09a0ae388e56b21d8f22c"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define __CM7_REV</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Cortex-M7 Core revision r0p1. </p>
+<p>([15:8] revision number, [7:0] patch number) </p>
+
+</div>
+</div>
+<a class="anchor" id="ga11d3ac679daeb58d0cec0a4e6ca59010"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define __DCACHE_PRESENT</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Data Cache present or not. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga165f052f5641898a02bb07096dc177b6"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define __DSP_PRESENT</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>DSP extension present or not. </p>
+
+</div>
+</div>
+<a class="anchor" id="gacbb998663708df6626abb09378303019"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define __DTCM_PRESENT</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Data Tightly Coupled Memory is present or not. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga2a528de57b6217f9fc9d4487d0db6328"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define __FPU_DP</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Double precision FPU present. </p>
+<p>The combination of the defines <a class="el" href="group__device__config.html#gac1ba8a48ca926bddc88be9bfd7d42641">__FPU_PRESENT</a> and <a class="el" href="group__device__config.html#ga2a528de57b6217f9fc9d4487d0db6328">__FPU_DP</a> determine the whether the FPU is with single or double precision as shown in the table below. </p>
+<table  class="cmtable">
+<tr bgcolor="cyan">
+<td><a class="el" href="group__device__config.html#gac1ba8a48ca926bddc88be9bfd7d42641">__FPU_PRESENT</a> </td><td><a class="el" href="group__device__config.html#ga2a528de57b6217f9fc9d4487d0db6328">__FPU_DP</a> </td><td><b>Description</b>  </td></tr>
+<tr>
+<td align="center">0 </td><td align="center"><em>ignored</em> </td><td>Processor has no FPU. The value set for <a class="el" href="group__device__config.html#ga2a528de57b6217f9fc9d4487d0db6328">__FPU_DP</a>.   </td></tr>
+<tr>
+<td align="center">1 </td><td align="center">0 </td><td>Processor with FPU with single precision.  </td></tr>
+<tr>
+<td align="center">1 </td><td align="center">1 </td><td>Processor with FPU with double precision.  </td></tr>
+</table>
+
+</div>
+</div>
+<a class="anchor" id="gac1ba8a48ca926bddc88be9bfd7d42641"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define __FPU_PRESENT</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>FPU present or not. </p>
+<p>The combination of the defines <a class="el" href="group__device__config.html#gac1ba8a48ca926bddc88be9bfd7d42641">__FPU_PRESENT</a> and <a class="el" href="group__device__config.html#ga2a528de57b6217f9fc9d4487d0db6328">__FPU_DP</a> determine the whether the FPU is with single or double precision as shown in the table below. </p>
+<table  class="cmtable">
+<tr bgcolor="cyan">
+<td><a class="el" href="group__device__config.html#gac1ba8a48ca926bddc88be9bfd7d42641">__FPU_PRESENT</a> </td><td><a class="el" href="group__device__config.html#ga2a528de57b6217f9fc9d4487d0db6328">__FPU_DP</a> </td><td><b>Description</b>  </td></tr>
+<tr>
+<td align="center">0 </td><td align="center"><em>ignored</em> </td><td>Processor has no FPU. The value set for <a class="el" href="group__device__config.html#ga2a528de57b6217f9fc9d4487d0db6328">__FPU_DP</a>.  </td></tr>
+<tr>
+<td align="center">1 </td><td align="center">0 </td><td>Processor with FPU with single precision.  </td></tr>
+<tr>
+<td align="center">1 </td><td align="center">1 </td><td>Processor with FPU with double precision.  </td></tr>
+</table>
+<p>FPU present</p>
+<p>The </p>
+
+</div>
+</div>
+<a class="anchor" id="ga3580fa1aeb7c2ed580904f8f70f8a919"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define __ICACHE_PRESENT</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Instruction Cache present or not. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga4127d1b31aaf336fab3d7329d117f448"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define __MPU_PRESENT</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MPU present or not. </p>
+
+</div>
+</div>
+<a class="anchor" id="gae3fe3587d5100c787e02102ce3944460"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define __NVIC_PRIO_BITS</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Number of Bits used for Priority Levels. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga9d4c51d9ca3eae58635d1040a3fb5fd2"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define __PMU_NUM_EVENTCNT</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>PMU Event Counters. </p>
+<p>The number of Event counters if PMU is present (see <a class="el" href="group__device__config.html#ga1c6eba273d4d6189eee91c6cbe7ec289">__PMU_PRESENT</a>) </p>
+
+</div>
+</div>
+<a class="anchor" id="ga1c6eba273d4d6189eee91c6cbe7ec289"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define __PMU_PRESENT</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>PMU present or not. </p>
+
+</div>
+</div>
+<a class="anchor" id="gadae9d54c744e525135b097c618bae3c4"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define __SAUREGION_PRESENT</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>SAU regions present or not. </p>
+
+</div>
+</div>
+<a class="anchor" id="gaf293b060f9c15592d18e6b0b977194bf"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define __SC000_REV</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>SC000 Core revision r0p1. </p>
+<p>([15:8] revision number, [7:0] patch number) </p>
+
+</div>
+</div>
+<a class="anchor" id="ga3029728b4fc64727b43bcfd853a7180b"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define __SC300_REV</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>SC300 Core revision r0p1. </p>
+<p>([15:8] revision number, [7:0] patch number) </p>
+
+</div>
+</div>
+<a class="anchor" id="gab58771b4ec03f9bdddc84770f7c95c68"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define __Vendor_SysTickConfig</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Set to 1 if a venor specfic SysTick configuration is used. </p>
+<p>If this define is set to 1, then the default <a class="el" href="group__SysTick__gr.html#gabe47de40e9b0ad465b752297a9d9f427">SysTick_Config</a> function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function. </p>
+
+</div>
+</div>
+<a class="anchor" id="gaddbae1a1b57539f398eb5546a17de8f6"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define __VTOR_PRESENT</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>VTOR present or not. </p>
+<p>See <a class="el" href="structSCB__Type.html#a187a4578e920544ed967f98020fb8170">SCB_Type::VTOR</a> </p>
+
+</div>
+</div>
+</div><!-- contents -->
+</div><!-- doc-content -->
+<!-- start footer part -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:07 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
+	<!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 
+	-->
+	</li>
+  </ul>
+</div>
+</body>
+</html>

docs/Core/html/group__device__config.js

@@ -0,0 +1,31 @@
+var group__device__config =
+[
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+    [ "__ARMv8MBL_REV", "group__device__config.html#ga645c9be694a2d5b5a5b772a0102c727a", null ],
+    [ "__ARMv8MML_REV", "group__device__config.html#gadb7d425f5ad0389b0eb1c6a69f8eb214", null ],
+    [ "__CM0_REV", "group__device__config.html#ga905517438930a3f13cbc632e52990534", null ],
+    [ "__CM0PLUS_REV", "group__device__config.html#ga2b7180ed347a0e902c5765deb46e650e", null ],
+    [ "__CM1_REV", "group__device__config.html#ga71248e1e7db00ff28754b6fd80807654", null ],
+    [ "__CM23_REV", "group__device__config.html#ga0f6c2b504ee424a7895fd7a420acdd0e", null ],
+    [ "__CM33_REV", "group__device__config.html#ga178e7a57b608f3e20d1c0cf18a2c2ac3", null ],
+    [ "__CM35P_REV", "group__device__config.html#gadd339c07b13a763dda6e83f4c05122f6", null ],
+    [ "__CM3_REV", "group__device__config.html#gac6a3f185c4640e06443c18b3c8d93f53", null ],
+    [ "__CM4_REV", "group__device__config.html#ga45a97e4bb8b6ce7c334acc5f45ace3ba", null ],
+    [ "__CM55_REV", "group__device__config.html#gaea2d16e963063038cde86cee33c4ef37", null ],
+    [ "__CM7_REV", "group__device__config.html#ga8eb40c0d30a09a0ae388e56b21d8f22c", null ],
+    [ "__DCACHE_PRESENT", "group__device__config.html#ga11d3ac679daeb58d0cec0a4e6ca59010", null ],
+    [ "__DSP_PRESENT", "group__device__config.html#ga165f052f5641898a02bb07096dc177b6", null ],
+    [ "__DTCM_PRESENT", "group__device__config.html#gacbb998663708df6626abb09378303019", null ],
+    [ "__FPU_DP", "group__device__config.html#ga2a528de57b6217f9fc9d4487d0db6328", null ],
+    [ "__FPU_PRESENT", "group__device__config.html#gac1ba8a48ca926bddc88be9bfd7d42641", null ],
+    [ "__ICACHE_PRESENT", "group__device__config.html#ga3580fa1aeb7c2ed580904f8f70f8a919", null ],
+    [ "__MPU_PRESENT", "group__device__config.html#ga4127d1b31aaf336fab3d7329d117f448", null ],
+    [ "__NVIC_PRIO_BITS", "group__device__config.html#gae3fe3587d5100c787e02102ce3944460", null ],
+    [ "__PMU_NUM_EVENTCNT", "group__device__config.html#ga9d4c51d9ca3eae58635d1040a3fb5fd2", null ],
+    [ "__PMU_PRESENT", "group__device__config.html#ga1c6eba273d4d6189eee91c6cbe7ec289", null ],
+    [ "__SAUREGION_PRESENT", "group__device__config.html#gadae9d54c744e525135b097c618bae3c4", null ],
+    [ "__SC000_REV", "group__device__config.html#gaf293b060f9c15592d18e6b0b977194bf", null ],
+    [ "__SC300_REV", "group__device__config.html#ga3029728b4fc64727b43bcfd853a7180b", null ],
+    [ "__Vendor_SysTickConfig", "group__device__config.html#gab58771b4ec03f9bdddc84770f7c95c68", null ],
+    [ "__VTOR_PRESENT", "group__device__config.html#gaddbae1a1b57539f398eb5546a17de8f6", null ]
+];

docs/Core/html/group__fpu__functions.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
-   &#160;<span id="projectnumber">Version 5.3.0</span>
+   &#160;<span id="projectnumber">Version 5.4.0</span>
    </div>
    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
   </td>
@@ -124,6 +124,7 @@ Functions</h2></td></tr>
 <tr class="separator:ga6bcad99ce80a0e7e4ddc6f2379081756"><td class="memSeparator" colspan="2">&#160;</td></tr>
 </table>
 <a name="details" id="details"></a><h2 class="groupheader">Description</h2>
+<p>Functions that relate to the Floating-Point Arithmetic Unit. </p>
 <p>Some Cortex-M processors include optional floating-point arithmetic functionality, with support for single and double-precision arithmetic. The Cortex-M processor with FPU is an implementation of the single-precision and double-precision variant of the Armv7-M Architecture with Floating-Point Extension (FPv5). </p>
 <h2 class="groupheader">Function Documentation</h2>
 <a class="anchor" id="ga6bcad99ce80a0e7e4ddc6f2379081756"></a>
@@ -139,6 +140,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Get the FPU type. </p>
 <dl class="section return"><dt>Returns</dt><dd><ul>
 <li><b>0</b>: No FPU</li>
 <li><b>1</b>: Single precision FPU</li>
@@ -154,7 +157,7 @@ Functions</h2></td></tr>
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:25 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Core/html/group__intrinsic__CPU__gr.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
-   &#160;<span id="projectnumber">Version 5.3.0</span>
+   &#160;<span id="projectnumber">Version 5.4.0</span>
    </div>
    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
   </td>
@@ -247,6 +247,7 @@ Functions</h2></td></tr>
 <tr class="separator:gae7f955b91595cfd82a03e4b437c59afe"><td class="memSeparator" colspan="2">&#160;</td></tr>
 </table>
 <a name="details" id="details"></a><h2 class="groupheader">Description</h2>
+<p>Functions that generate specific Cortex-M CPU Instructions. </p>
 <p>The following functions generate specific Cortex-M instructions that cannot be directly accessed by the C/C++ Compiler. Refer to the <a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> for detailed information about these Cortex-M instructions.</p>
 <dl class="section note"><dt>Note</dt><dd>When using the <b>Arm Compiler Version 5 Toolchain</b> the following <a class="el" href="group__intrinsic__CPU__gr.html">Intrinsic Functions for CPU Instructions</a> are implemented using the Embedded Assembler. As the Embedded Assembler may cause side effects (Refer to <b>Arm Compiler v5.xx User Guide - Using the Inline and Embedded Assemblers of the Arm Compiler</b> for more information) it is possible to disable the following intrinsic functions and therefore the usage of the Embedded Assembler with the <b><em>define __NO_EMBEDDED_ASM</em></b>:<ul>
 <li><a class="el" href="group__intrinsic__CPU__gr.html#gaeef6f853b6df3a365c838ee5b49a7a26">__REV16</a></li>
@@ -268,6 +269,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Set Breakpoint. </p>
 <p>This function causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -291,6 +294,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Remove the exclusive lock [not for Cortex-M0, Cortex-M0+, or SC000]. </p>
 <p>This function removes the exclusive lock which is created by LDREX [not for Cortex-M0, Cortex-M0+, or SC000]. </p>
 
 </div>
@@ -308,6 +313,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Count leading zeros. </p>
 <p>This function counts the number of leading zeros of a data value.</p>
 <p>On Armv6-M (Cortex-M0, Cortex-M0+, and SC000) this function is not available as a core instruction instruction and thus __CLZ is implemented in software.</p>
 <dl class="params"><dt>Parameters</dt><dd>
@@ -333,6 +340,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Data Memory Barrier. </p>
 <p>This function ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. </p>
 
 </div>
@@ -350,6 +359,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Data Synchronization Barrier. </p>
 <p>This function acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. </p>
 
 </div>
@@ -367,6 +378,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Instruction Synchronization Barrier. </p>
 <p>Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. </p>
 
 </div>
@@ -384,6 +397,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Load-Acquire (32 bit) </p>
 <p>Executes a LDA instruction for 32 bit values. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -409,6 +424,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Load-Acquire (8 bit) </p>
 <p>Executes a LDAB instruction for 8 bit value. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -434,6 +451,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Load-Acquire Exclusive (32 bit) </p>
 <p>Executes a LDA exclusive instruction for 32 bit values. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -459,6 +478,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Load-Acquire Exclusive (8 bit) </p>
 <p>Executes a LDAB exclusive instruction for 8 bit value. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -484,6 +505,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Load-Acquire Exclusive (16 bit) </p>
 <p>Executes a LDAH exclusive instruction for 16 bit values. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -509,6 +532,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Load-Acquire (16 bit) </p>
 <p>Executes a LDAH instruction for 16 bit values. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -534,6 +559,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>LDRT Unprivileged (8 bit) </p>
 <p>This function executed an Unprivileged LDRT command for 8 bit value.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -558,6 +585,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>LDR Exclusive (8 bit) [not for Cortex-M0, Cortex-M0+, or SC000]. </p>
 <p>This function executed an exclusive LDR command for 8 bit value [not for Cortex-M0, Cortex-M0+, or SC000].</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -582,6 +611,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>LDR Exclusive (16 bit) [not for Cortex-M0, Cortex-M0+, or SC000]. </p>
 <p>This function executed an exclusive LDR command for 16 bit values [not for Cortex-M0, Cortex-M0+, or SC000].</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -606,6 +637,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>LDR Exclusive (32 bit) [not for Cortex-M0, Cortex-M0+, or SC000]. </p>
 <p>This function executed an exclusive LDR command for 32 bit values [not for Cortex-M0, Cortex-M0+, or SC000].</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -630,6 +663,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>LDRT Unprivileged (16 bit) </p>
 <p>This function executed an Unprivileged LDRT command for 16 bit values.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -654,6 +689,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>LDRT Unprivileged (32 bit) </p>
 <p>This function executed an Unprivileged LDRT command for 32 bit values.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -678,6 +715,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>No Operation. </p>
 <p>This function does nothing. This instruction can be used for code alignment purposes. </p>
 
 </div>
@@ -695,6 +734,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Reverse bit order of value. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
     <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to reverse </td></tr>
@@ -718,6 +759,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Reverse byte order (32 bit) </p>
 <p>Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -742,6 +785,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Reverse byte order (16 bit) </p>
 <p>Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -766,6 +811,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Reverse byte order (16 bit) </p>
 <p>Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -800,6 +847,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Rotate a value right by a number of bits. </p>
 <p>This function rotates a value right by a specified number of bits.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -825,6 +874,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Rotate Right with Extend (32 bit) </p>
 <p>This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -849,6 +900,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Send Event. </p>
 <p>Send Event is a hint instruction. It causes an event to be signaled to the CPU. </p>
 
 </div>
@@ -876,6 +929,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Signed Saturate [not for Cortex-M0, Cortex-M0+, or SC000]. </p>
 <p>This function saturates a signed value [not for Cortex-M0, Cortex-M0+, or SC000]. The Q bit is set if saturation occurs.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -911,6 +966,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Store-Release (32 bit) </p>
 <p>Executes a STL instruction for 32 bit values. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -946,6 +1003,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Store-Release (8 bit) </p>
 <p>Executes a STLB instruction for 8 bit values. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -981,6 +1040,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Store-Release Exclusive (32 bit) </p>
 <p>Executes a STL exclusive instruction for 32 bit values. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -1019,6 +1080,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Store-Release Exclusive (8 bit) </p>
 <p>Executes a STLB exclusive instruction for 8 bit values. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -1057,6 +1120,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Store-Release Exclusive (16 bit) </p>
 <p>Executes a STLH exclusive instruction for 16 bit values. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -1095,6 +1160,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Store-Release (16 bit) </p>
 <p>Executes a STLH instruction for 16 bit values. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -1130,6 +1197,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>STRT Unprivileged (8 bit) </p>
 <p>This function executed an Unprivileged STRT command for 8 bit values.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -1164,6 +1233,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>STR Exclusive (8 bit) [not for Cortex-M0, Cortex-M0+, or SC000]. </p>
 <p>This function executed an exclusive STR command for 8 bit values [not for Cortex-M0, Cortex-M0+, or SC000].</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -1201,6 +1272,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>STR Exclusive (16 bit) [not for Cortex-M0, Cortex-M0+, or SC000]. </p>
 <p>This function executed an exclusive STR command for 16 bit values [not for Cortex-M0, Cortex-M0+, or SC000].</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -1238,6 +1311,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>STR Exclusive (32 bit) [not for Cortex-M0, Cortex-M0+, or SC000]. </p>
 <p>This function executed an exclusive STR command for 32 bit values [not for Cortex-M0, Cortex-M0+, or SC000].</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -1275,6 +1350,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>STRT Unprivileged (16 bit) </p>
 <p>This function executed an Unprivileged STRT command for 16 bit values.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -1309,6 +1386,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>STRT Unprivileged (32 bit) </p>
 <p>This function executed an Unprivileged STRT command for 32 bit values.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -1343,6 +1422,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Unsigned Saturate [not for Cortex-M0, Cortex-M0+, or SC000]. </p>
 <p>This function saturates an unsigned value [not for Cortex-M0, Cortex-M0+, or SC000]. The Q bit is set if saturation occurs.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -1368,6 +1449,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Wait For Event. </p>
 <p>Wait For Event is a hint instruction that permits the processor to enter a low-power state until an events occurs: </p>
 <ul>
 <li>If the <b>event register is 0</b>, then WFE suspends execution until one of the following events occurs:<ul>
@@ -1397,6 +1480,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Wait For Interrupt. </p>
 <p>WFI is a hint instruction that suspends execution until one of the following events occurs:</p>
 <ul>
 <li>A non-masked interrupt occurs and is taken.</li>
@@ -1411,7 +1496,7 @@ Functions</h2></td></tr>
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:25 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Core/html/group__intrinsic__SIMD__gr.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
-   &#160;<span id="projectnumber">Version 5.3.0</span>
+   &#160;<span id="projectnumber">Version 5.4.0</span>
    </div>
    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
   </td>
@@ -248,6 +248,9 @@ Functions</h2></td></tr>
 <tr class="memitem:ga38dce3dd13ba212e80ec3cff4abeb11a"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga38dce3dd13ba212e80ec3cff4abeb11a">__SXTB16</a> (uint32_t val)</td></tr>
 <tr class="memdesc:ga38dce3dd13ba212e80ec3cff4abeb11a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Dual extract 8-bits and sign extend each to 16-bits.  <a href="#ga38dce3dd13ba212e80ec3cff4abeb11a">More...</a><br/></td></tr>
 <tr class="separator:ga38dce3dd13ba212e80ec3cff4abeb11a"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gaef7e08ba1dbaaae1efdb76c113155ed1"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gaef7e08ba1dbaaae1efdb76c113155ed1">__SXTB16_RORn</a> (uint32_t val, uint32_r rotate)</td></tr>
+<tr class="memdesc:gaef7e08ba1dbaaae1efdb76c113155ed1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Rotate right, dual extract 8-bits and sign extend each to 16-bits.  <a href="#gaef7e08ba1dbaaae1efdb76c113155ed1">More...</a><br/></td></tr>
+<tr class="separator:gaef7e08ba1dbaaae1efdb76c113155ed1"><td class="memSeparator" colspan="2">&#160;</td></tr>
 <tr class="memitem:gac540b4fc41d30778ba102d2a65db5589"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gac540b4fc41d30778ba102d2a65db5589">__SXTAB16</a> (uint32_t val1, uint32_t val2)</td></tr>
 <tr class="memdesc:gac540b4fc41d30778ba102d2a65db5589"><td class="mdescLeft">&#160;</td><td class="mdescRight">Dual extracted 8-bit to 16-bit signed addition.  <a href="#gac540b4fc41d30778ba102d2a65db5589">More...</a><br/></td></tr>
 <tr class="separator:gac540b4fc41d30778ba102d2a65db5589"><td class="memSeparator" colspan="2">&#160;</td></tr>
@@ -307,6 +310,7 @@ Functions</h2></td></tr>
 <tr class="separator:gafd8fe4a6d87e947caa81a69ec36c1666"><td class="memSeparator" colspan="2">&#160;</td></tr>
 </table>
 <a name="details" id="details"></a><h2 class="groupheader">Description</h2>
+<p>Access to dedicated SIMD instructions. </p>
 <p><b>Single Instruction Multiple Data (SIMD)</b> extensions are provided <b>only for Cortex-M4 and Cortex-M7 cores</b> to simplify development of application software. SIMD extensions increase the processing capability without materially increasing the power consumption. The SIMD extensions are completely transparent to the operating system (OS), allowing existing OS ports to be used.</p>
 <p><b>SIMD Features:</b></p>
 <ul>
@@ -364,6 +368,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Halfword packing instruction. Combines bits[15:0] of <em>val1</em> with bits[31:16] of <em>val2</em> levitated with the <em>val3</em>. </p>
 <p>Combine a halfword from one register with a halfword from another register. The second argument can be left-shifted before extraction of the halfword. The registers PC and SP are not allowed as arguments. This instruction does not change the flags.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -409,6 +415,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Halfword packing instruction. Combines bits[31:16] of <em>val1</em> with bits[15:0] of <em>val2</em> right-shifted with the <em>val3</em>. </p>
 <p>Combines a halfword from one register with a halfword from another register. The second argument can be right-shifted before extraction of the halfword. The registers PC and SP are not allowed as arguments. This instruction does not change the flags.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -448,6 +456,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Q setting saturating add. </p>
 <p>This function enables you to obtain the saturating add of two integers.<br/>
  The Q bit is set if the operation saturates.</p>
 <dl class="params"><dt>Parameters</dt><dd>
@@ -486,6 +496,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Q setting dual 16-bit saturating addition. </p>
 <p>This function enables you to perform two 16-bit integer arithmetic additions in parallel, saturating the results to the 16-bit signed integer range -2<sup>15</sup> &lt;= x &lt;= 2<sup>15</sup> - 1.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -529,6 +541,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Q setting quad 8-bit saturating addition. </p>
 <p>This function enables you to perform four 8-bit integer additions, saturating the results to the 8-bit signed integer range -2<sup>7</sup> &lt;= x &lt;= 2<sup>7</sup> - 1. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -576,6 +590,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Q setting dual 16-bit add and subtract with exchange. </p>
 <p>This function enables you to exchange the halfwords of the one operand, then add the high halfwords and subtract the low halfwords, saturating the results to the 16-bit signed integer range -2<sup>15</sup> &lt;= x &lt;= 2<sup>15</sup> - 1.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -619,6 +635,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Q setting dual 16-bit subtract and add with exchange. </p>
 <p>This function enables you to exchange the halfwords of one operand, then subtract the high halfwords and add the low halfwords, saturating the results to the 16-bit signed integer range -2<sup>15</sup> &lt;= x &lt;= 2<sup>15</sup> - 1.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -662,6 +680,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Q setting saturating subtract. </p>
 <p>This function enables you to obtain the saturating subtraction of two integers.<br/>
  The Q bit is set if the operation saturates.</p>
 <dl class="params"><dt>Parameters</dt><dd>
@@ -700,6 +720,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Q setting dual 16-bit saturating subtract. </p>
 <p>This function enables you to perform two 16-bit integer subtractions, saturating the results to the 16-bit signed integer range -2<sup>15</sup> &lt;= x &lt;= 2<sup>15</sup> - 1.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -743,6 +765,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Q setting quad 8-bit saturating subtract. </p>
 <p>This function enables you to perform four 8-bit integer subtractions, saturating the results to the 8-bit signed integer range -2<sup>7</sup> &lt;= x &lt;= 2<sup>7</sup> - 1.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -790,6 +814,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>GE setting dual 16-bit signed addition. </p>
 <p>This function enables you to perform two 16-bit signed integer additions.<br/>
  The GE bits in the APSR are set according to the results of the additions.</p>
 <dl class="params"><dt>Parameters</dt><dd>
@@ -839,6 +865,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>GE setting quad 8-bit signed addition. </p>
 <p>This function performs four 8-bit signed integer additions. The GE bits of the APSR are set according to the results of the additions. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -893,6 +921,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>GE setting dual 16-bit addition and subtraction with exchange. </p>
 <p>This function inserts an SASX instruction into the instruction stream generated by the compiler. It enables you to exchange the halfwords of the second operand, add the high halfwords and subtract the low halfwords.<br/>
  The GE bits in the APRS are set according to the results.</p>
 <dl class="params"><dt>Parameters</dt><dd>
@@ -942,6 +972,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Select bytes based on GE bits. </p>
 <p>This function inserts a SEL instruction into the instruction stream generated by the compiler. It enables you to select bytes from the input parameters, whereby the bytes that are selected depend upon the results of previous SIMD instruction function. The results of previous SIMD instruction function are represented by the Greater than or Equal flags in the Application Program Status Register (APSR). The __SEL function works equally well on both halfword and byte operand function results. This is because halfword operand operations set two (duplicate) GE bits per value.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -983,6 +1015,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Dual 16-bit signed addition with halved results. </p>
 <p>This function enables you to perform two signed 16-bit integer additions, halving the results.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -1025,6 +1059,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Quad 8-bit signed addition with halved results. </p>
 <p>This function enables you to perform four signed 8-bit integer additions, halving the results. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -1071,6 +1107,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Dual 16-bit signed addition and subtraction with halved results. </p>
 <p>This function enables you to exchange the two halfwords of one operand, perform one signed 16-bit integer addition and one signed 16-bit subtraction, and halve the results.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -1113,6 +1151,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Dual 16-bit signed subtraction and addition with halved results. </p>
 <p>This function enables you to exchange the two halfwords of one operand, perform one signed 16-bit integer subtraction and one signed 16-bit addition, and halve the results.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -1155,6 +1195,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Dual 16-bit signed subtraction with halved results. </p>
 <p>This function enables you to perform two signed 16-bit integer subtractions, halving the results.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -1197,6 +1239,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Quad 8-bit signed subtraction with halved results. </p>
 <p>This function enables you to perform four signed 8-bit integer subtractions, halving the results.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -1249,6 +1293,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Q setting dual 16-bit signed multiply with single 32-bit accumulator. </p>
 <p>This function enables you to perform two signed 16-bit multiplications, adding both results to a 32-bit accumulate operand.<br/>
  The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications.</p>
 <dl class="params"><dt>Parameters</dt><dd>
@@ -1296,6 +1342,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Q setting pre-exchanged dual 16-bit signed multiply with single 32-bit accumulator. </p>
 <p>This function enables you to perform two signed 16-bit multiplications with exchanged halfwords of the second operand, adding both results to a 32-bit accumulate operand.<br/>
  The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications.</p>
 <dl class="params"><dt>Parameters</dt><dd>
@@ -1343,6 +1391,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Dual 16-bit signed multiply with single 64-bit accumulator. </p>
 <p>This function enables you to perform two signed 16-bit multiplications, adding both results to a 64-bit accumulate operand. Overflow is only possible as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo2<sup>64</sup>.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -1391,6 +1441,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Dual 16-bit signed multiply with exchange with single 64-bit accumulator. </p>
 <p>This function enables you to exchange the halfwords of the second operand, and perform two signed 16-bit multiplications, adding both results to a 64-bit accumulate operand. Overflow is only possible as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo2<sup>64</sup>.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -1439,6 +1491,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Q setting dual 16-bit signed multiply subtract with 32-bit accumulate. </p>
 <p>This function enables you to perform two 16-bit signed multiplications, take the difference of the products, subtracting the high halfword product from the low halfword product, and add the difference to a 32-bit accumulate operand.<br/>
  The Q bit is set if the accumulation overflows. Overflow cannot occur during the multiplications or the subtraction.</p>
 <dl class="params"><dt>Parameters</dt><dd>
@@ -1486,6 +1540,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Q setting dual 16-bit signed multiply with exchange subtract with 32-bit accumulate. </p>
 <p>This function enables you to exchange the halfwords in the second operand, then perform two 16-bit signed multiplications. The difference of the products is added to a 32-bit accumulate operand.<br/>
  The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications or the subtraction.</p>
 <dl class="params"><dt>Parameters</dt><dd>
@@ -1533,6 +1589,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Q setting dual 16-bit signed multiply subtract with 64-bit accumulate. </p>
 <p>This function It enables you to perform two 16-bit signed multiplications, take the difference of the products, subtracting the high halfword product from the low halfword product, and add the difference to a 64-bit accumulate operand. Overflow cannot occur during the multiplications or the subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow is not detected. Instead, the result wraps round to modulo2<sup>64</sup>.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -1579,6 +1637,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Q setting dual 16-bit signed multiply with exchange subtract with 64-bit accumulate. </p>
 <p>This function enables you to exchange the halfwords of the second operand, perform two 16-bit multiplications, adding the difference of the products to a 64-bit accumulate operand. Overflow cannot occur during the multiplications or the subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow is not detected. Instead, the result wraps round to modulo2<sup>64</sup>.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -1625,6 +1685,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>32-bit signed multiply with 32-bit truncated accumulator. </p>
 <p>This function enables you to perform a signed 32-bit multiplications, adding the most significant 32 bits of the 64-bit result to a 32-bit accumulate operand.<br/>
 </p>
 <dl class="params"><dt>Parameters</dt><dd>
@@ -1665,6 +1727,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Q setting sum of dual 16-bit signed multiply. </p>
 <p>This function enables you to perform two 16-bit signed multiplications, adding the products together.<br/>
  The Q bit is set if the addition overflows.</p>
 <dl class="params"><dt>Parameters</dt><dd>
@@ -1705,6 +1769,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Q setting sum of dual 16-bit signed multiply with exchange. </p>
 <p>This function enables you to perform two 16-bit signed multiplications with exchanged halfwords of the second operand, adding the products together.<br/>
  The Q bit is set if the addition overflows.</p>
 <dl class="params"><dt>Parameters</dt><dd>
@@ -1745,6 +1811,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Dual 16-bit signed multiply returning difference. </p>
 <p>This function enables you to perform two 16-bit signed multiplications, taking the difference of the products by subtracting the high halfword product from the low halfword product.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -1784,6 +1852,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Dual 16-bit signed multiply with exchange returning difference. </p>
 <p>This function enables you to perform two 16-bit signed multiplications, subtracting one of the products from the other. The halfwords of the second operand are exchanged before performing the arithmetic. This produces top * bottom and bottom * top multiplication.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -1823,6 +1893,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Q setting dual 16-bit saturate. </p>
 <p>This function enables you to saturate two signed 16-bit values to a selected signed range.<br/>
  The Q bit is set if either operation saturates.</p>
 <dl class="params"><dt>Parameters</dt><dd>
@@ -1865,6 +1937,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>GE setting dual 16-bit signed subtraction and addition with exchange. </p>
 <p>This function enables you to exchange the two halfwords of one operand and perform one 16-bit integer subtraction and one 16-bit addition.<br/>
  The GE bits in the APSR are set according to the results.</p>
 <dl class="params"><dt>Parameters</dt><dd>
@@ -1914,6 +1988,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>GE setting dual 16-bit signed subtraction. </p>
 <p>This function enables you to perform two 16-bit signed integer subtractions.<br/>
  The GE bits in the APSR are set according to the results.</p>
 <dl class="params"><dt>Parameters</dt><dd>
@@ -1964,6 +2040,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>GE setting quad 8-bit signed subtraction. </p>
 <p>This function enables you to perform four 8-bit signed integer subtractions.<br/>
  The GE bits in the APSR are set according to the results.</p>
 <dl class="params"><dt>Parameters</dt><dd>
@@ -2019,6 +2097,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Dual extracted 8-bit to 16-bit signed addition. </p>
 <p>This function enables you to extract two 8-bit values from the second operand (at bit positions [7:0] and [23:16]), sign-extend them to 16-bits each, and add the results to the first operand.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -2047,6 +2127,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Dual extract 8-bits and sign extend each to 16-bits. </p>
 <p>This function enables you to extract two 8-bit values from an operand and sign-extend them to 16 bits each.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -2063,6 +2145,51 @@ Functions</h2></td></tr>
 <div class="line">res[31:16] = SignExtended(val[23:16]</div>
 </div><!-- fragment --> </dd></dl>
 
+</div>
+</div>
+<a class="anchor" id="gaef7e08ba1dbaaae1efdb76c113155ed1"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">uint32_t __SXTB16_RORn </td>
+          <td>(</td>
+          <td class="paramtype">uint32_t&#160;</td>
+          <td class="paramname"><em>val</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_r&#160;</td>
+          <td class="paramname"><em>rotate</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Rotate right, dual extract 8-bits and sign extend each to 16-bits. </p>
+<p>This function enables you to rotate an operand by 8/16/24 bit, extract two 8-bit values and sign-extend them to 16 bits each.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">val</td><td>two 8-bit values in val[7:0] and val[23:16] to be sign-extended. </td></tr>
+    <tr><td class="paramname">rotate</td><td>number of bits to rotate val. Only 8,16 and 24 are accepted</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>the 8-bit values sign-extended to 16-bit values. <ul>
+<li>sign-extended value of val[7:0] in the low halfword of the return value. </li>
+<li>sign-extended value of val[23:16] in the high halfword of the return value.</li>
+</ul>
+</dd></dl>
+<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">val        = Rotate(val, rotate)</div>
+<div class="line">res[15:0]  = SignExtended(val[7:0])</div>
+<div class="line">res[31:16] = SignExtended(val[23:16])</div>
+</div><!-- fragment --> </dd></dl>
+
 </div>
 </div>
 <a class="anchor" id="gaa1160f0cf76d6aa292fbad54a1aa6b74"></a>
@@ -2088,6 +2215,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>GE setting dual 16-bit unsigned addition. </p>
 <p>This function enables you to perform two 16-bit unsigned integer additions.<br/>
  The GE bits in the APSR are set according to the results.</p>
 <dl class="params"><dt>Parameters</dt><dd>
@@ -2137,6 +2266,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>GE setting quad 8-bit unsigned addition. </p>
 <p>This function enables you to perform four unsigned 8-bit integer additions. The GE bits of the APSR are set according to the results.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -2191,6 +2322,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>GE setting dual 16-bit unsigned addition and subtraction with exchange. </p>
 <p>This function enables you to exchange the two halfwords of the second operand, add the high halfwords and subtract the low halfwords.<br/>
  The GE bits in the APSR are set according to the results.</p>
 <dl class="params"><dt>Parameters</dt><dd>
@@ -2240,6 +2373,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Dual 16-bit unsigned addition with halved results. </p>
 <p>This function enables you to perform two unsigned 16-bit integer additions, halving the results.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -2282,6 +2417,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Quad 8-bit unsigned addition with halved results. </p>
 <p>This function enables you to perform four unsigned 8-bit integer additions, halving the results.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -2328,6 +2465,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Dual 16-bit unsigned addition and subtraction with halved results and exchange. </p>
 <p>This function enables you to exchange the halfwords of the second operand, add the high halfwords and subtract the low halfwords, halving the results.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -2370,6 +2509,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Dual 16-bit unsigned subtraction and addition with halved results and exchange. </p>
 <p>This function enables you to exchange the halfwords of the second operand, subtract the high halfwords and add the low halfwords, halving the results.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -2412,6 +2553,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Dual 16-bit unsigned subtraction with halved results. </p>
 <p>This function enables you to perform two unsigned 16-bit integer subtractions, halving the results.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -2454,6 +2597,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Quad 8-bit unsigned subtraction with halved results. </p>
 <p>This function enables you to perform four unsigned 8-bit integer subtractions, halving the results.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -2500,6 +2645,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Dual 16-bit unsigned saturating addition. </p>
 <p>This function enables you to perform two unsigned 16-bit integer additions, saturating the results to the 16-bit unsigned integer range 0 &lt; x &lt; 2<sup>16</sup> - 1.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -2543,6 +2690,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Quad 8-bit unsigned saturating addition. </p>
 <p>This function enables you to perform four unsigned 8-bit integer additions, saturating the results to the 8-bit unsigned integer range 0 &lt; x &lt; 2<sup>8</sup> - 1.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -2590,6 +2739,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Dual 16-bit unsigned saturating addition and subtraction with exchange. </p>
 <p>This function enables you to exchange the halfwords of the second operand and perform one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, saturating the results to the 16-bit unsigned integer range 0 &lt;= x &lt;= 2<sup>16</sup> - 1.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -2633,6 +2784,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Dual 16-bit unsigned saturating subtraction and addition with exchange. </p>
 <p>This function enables you to exchange the halfwords of the second operand and perform one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, saturating the results to the 16-bit unsigned integer range 0 &lt;= x &lt;= 2<sup>16</sup> - 1.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -2676,6 +2829,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Dual 16-bit unsigned saturating subtraction. </p>
 <p>This function enables you to perform two unsigned 16-bit integer subtractions, saturating the results to the 16-bit unsigned integer range 0 &lt; x &lt; 2<sup>16</sup> - 1.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -2719,6 +2874,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Quad 8-bit unsigned saturating subtraction. </p>
 <p>This function enables you to perform four unsigned 8-bit integer subtractions, saturating the results to the 8-bit unsigned integer range 0 &lt; x &lt; 2<sup>8</sup> - 1.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -2766,6 +2923,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Unsigned sum of quad 8-bit unsigned absolute difference. </p>
 <p>This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values of the differences together, returning the result as a single unsigned integer.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -2820,6 +2979,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Unsigned sum of quad 8-bit unsigned absolute difference with 32-bit accumulate. </p>
 <p>This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values of the differences to a 32-bit accumulate operand.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -2869,6 +3030,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Q setting dual 16-bit unsigned saturate. </p>
 <p>This function enables you to saturate two signed 16-bit values to a selected unsigned range.<br/>
  The Q bit is set if either operation saturates.</p>
 <dl class="params"><dt>Parameters</dt><dd>
@@ -2911,6 +3074,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>GE setting dual 16-bit unsigned subtract and add with exchange. </p>
 <p>This function enables you to exchange the halfwords of the second operand, subtract the high halfwords and add the low halfwords.<br/>
  The GE bits in the APSR are set according to the results.</p>
 <dl class="params"><dt>Parameters</dt><dd>
@@ -2960,6 +3125,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>GE setting dual 16-bit unsigned subtract. </p>
 <p>This function enables you to perform two 16-bit unsigned integer subtractions.<br/>
  The GE bits in the APSR are set according to the results.</p>
 <dl class="params"><dt>Parameters</dt><dd>
@@ -3009,6 +3176,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>GE setting quad 8-bit unsigned subtract. </p>
 <p>This function enables you to perform four 8-bit unsigned integer subtractions. The GE bits in the APSR are set according to the results.</p>
 <dl class="params"><dt>Parameters</dt><dd>
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+<p>Extracted 16-bit to 32-bit unsigned addition. </p>
 <p>This function enables you to extract two 8-bit values from one operand, zero-extend them to 16 bits each, and add the results to two 16-bit values from another operand.</p>
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   <table class="params">
@@ -3091,6 +3262,8 @@ Functions</h2></td></tr>
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+
+<p>Dual extract 8-bits and zero-extend to 16-bits. </p>
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 <dl class="params"><dt>Parameters</dt><dd>
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   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:25 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
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     [ "__SXTB16", "group__intrinsic__SIMD__gr.html#ga38dce3dd13ba212e80ec3cff4abeb11a", null ],
+    [ "__SXTB16_RORn", "group__intrinsic__SIMD__gr.html#gaef7e08ba1dbaaae1efdb76c113155ed1", null ],
     [ "__UADD16", "group__intrinsic__SIMD__gr.html#gaa1160f0cf76d6aa292fbad54a1aa6b74", null ],
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@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
-   &#160;<span id="projectnumber">Version 5.3.0</span>
+   &#160;<span id="projectnumber">Version 5.4.0</span>
    </div>
    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
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 </table>
 <a name="details" id="details"></a><h2 class="groupheader">Description</h2>
+<p>Functions that relate to the Memory Protection Unit. </p>
 <p>The following functions support the optional Memory Protection Unit (MPU) that is available on the Cortex-M23, M33, M35P processor.</p>
 <p>The MPU is used to prevent from illegal memory accesses that are typically caused by errors in an application software.</p>
 <p><b>Example:</b> </p>
@@ -254,6 +255,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Memory access permissions. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
     <tr><td class="paramname">RO</td><td>Read-Only: Set to 1 for read-only memory. </td></tr>
@@ -287,6 +290,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Memory Attribute. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
     <tr><td class="paramname">O</td><td>Outer memory attributes </td></tr>
@@ -307,6 +312,8 @@ Functions</h2></td></tr>
       </table>
 </div><div class="memdoc">
 
+<p>Attribute for device memory (outer only) </p>
+
 </div>
 </div>
 <a class="anchor" id="ga496bcd6a2bbd038d8935049fec9d0fda"></a>
@@ -319,6 +326,8 @@ Functions</h2></td></tr>
       </table>
 </div><div class="memdoc">
 
+<p>Device memory type Gathering, Re-ordering, Early Write Acknowledgement. </p>
+
 </div>
 </div>
 <a class="anchor" id="ga6e08ae44fab85e03fea96ae6a5fcdfb0"></a>
@@ -331,6 +340,8 @@ Functions</h2></td></tr>
       </table>
 </div><div class="memdoc">
 
+<p>Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement. </p>
+
 </div>
 </div>
 <a class="anchor" id="gabfa9ae279357044cf5b74e77af22a686"></a>
@@ -343,6 +354,8 @@ Functions</h2></td></tr>
       </table>
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+<p>Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement. </p>
+
 </div>
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 <a class="anchor" id="gadcc9977aabb4dc7177d30cbbac1b53d1"></a>
@@ -355,6 +368,8 @@ Functions</h2></td></tr>
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+<p>Device memory type non Gathering, Re-ordering, Early Write Acknowledgement. </p>
+
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+
+<p>Attribute for normal memory (outer and inner) </p>
 <dl class="params"><dt>Parameters</dt><dd>
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     <tr><td class="paramname">NT</td><td>Non-Transient: Set to 1 for non-transient data. </td></tr>
@@ -414,6 +431,8 @@ Functions</h2></td></tr>
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+<p>Attribute for non-cacheable, normal memory. </p>
+
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+
+<p>Region Base Address Register value. </p>
 <dl class="params"><dt>Parameters</dt><dd>
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     <tr><td class="paramname">BASE</td><td>The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. </td></tr>
@@ -493,6 +514,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Region Limit Address Register value. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
     <tr><td class="paramname">LIMIT</td><td>The limit address bits [31:5] for this memory region. The value is one extended. </td></tr>
@@ -513,6 +536,8 @@ Functions</h2></td></tr>
       </table>
 </div><div class="memdoc">
 
+<p>Normal memory inner shareable. </p>
+
 </div>
 </div>
 <a class="anchor" id="ga3d0f688198289f72264f73cf72a742e8"></a>
@@ -525,6 +550,8 @@ Functions</h2></td></tr>
       </table>
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+<p>Normal memory non-shareable. </p>
+
 </div>
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 <a class="anchor" id="gac4fddbdb9e1350bce6906de33c1fd500"></a>
@@ -537,6 +564,8 @@ Functions</h2></td></tr>
       </table>
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+<p>Normal memory outer shareable. </p>
+
 </div>
 </div>
 <h2 class="groupheader">Function Documentation</h2>
@@ -1130,7 +1159,7 @@ Functions</h2></td></tr>
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:25 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
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docs/Core/html/group__mpu__defines.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
-   &#160;<span id="projectnumber">Version 5.3.0</span>
+   &#160;<span id="projectnumber">Version 5.4.0</span>
    </div>
    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
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 </table>
 <a name="details" id="details"></a><h2 class="groupheader">Description</h2>
+<p>Define values for MPU region setup. </p>
 <p>The following define values are used with <a class="el" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a> to setup the <a class="el" href="structMPU__Type.html#a8f00c4a5e31b0a8d103ed3b0732c17a3">RASR</a> value field in the MPU region.</p>
 <dl class="section see"><dt>See Also</dt><dd><a class="el" href="structARM__MPU__Region__t.html" title="Setup information of a single MPU Region. ">ARM_MPU_Region_t</a>, <a class="el" href="group__mpu__functions.html#ga16931f9ad84d7289e8218e169ae6db5d">ARM_MPU_SetRegion</a>, <a class="el" href="group__mpu__functions.html#ga042ba1a6a1a58795231459ac0410b809">ARM_MPU_SetRegionEx</a>. </dd></dl>
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@@ -145,6 +146,8 @@ Macros</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Values for MPU region access attributes (in RASR field) </p>
 <p>The following define values are used to compose the access attributes for an MPU region: </p>
 <table class="doxtable">
 <tr>
@@ -168,6 +171,8 @@ Macros</h2></td></tr>
         </tr>
       </table>
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+
+<p>Values for MPU region access permissions (in RASR field) </p>
 <p>The following define values are used to compose the access permission for an MPU region: </p>
 <table class="doxtable">
 <tr>
@@ -197,6 +202,8 @@ Macros</h2></td></tr>
         </tr>
       </table>
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+
+<p>Cache policy values for MPU region access attributes (in RASR field) </p>
 <p>The following define values are used to compose the cacheability flags within the access attributes for an MPU region: </p>
 <table class="doxtable">
 <tr>
@@ -222,6 +229,8 @@ Macros</h2></td></tr>
         </tr>
       </table>
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+
+<p>Size values of a MPU region (in RASR field) </p>
 <p>The following define values are used to compose the size information for an MPU region:</p>
 <table class="doxtable">
 <tr>
@@ -291,7 +300,7 @@ Macros</h2></td></tr>
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:25 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
     <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 

docs/Core/html/group__mpu__functions.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
-   &#160;<span id="projectnumber">Version 5.3.0</span>
+   &#160;<span id="projectnumber">Version 5.4.0</span>
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    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
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 </table>
 <a name="details" id="details"></a><h2 class="groupheader">Description</h2>
+<p>Functions that relate to the Memory Protection Unit. </p>
 <p>The following functions support the optional Memory Protection Unit (MPU) that is available on the Cortex-M0+, M3, M4 and M7 processor.</p>
 <p>The MPU is used to prevent from illegal memory accesses that are typically caused by errors in an application software.</p>
 <p><b>Example:</b> </p>
@@ -240,6 +241,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>MPU Region Attribute and Size Register Value. </p>
 <p>This macro is used to construct a valid <a class="el" href="structMPU__Type.html#a8f00c4a5e31b0a8d103ed3b0732c17a3">RASR</a> value. The ENABLE bit of the RASR value is implicitly set to 1.</p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
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+
+<p>MPU Region Attribute and Size Register Value. </p>
 <p>This macro is used to construct a valid <a class="el" href="structMPU__Type.html#a8f00c4a5e31b0a8d103ed3b0732c17a3">RASR</a> value. The ENABLE bit of the RASR value is implicitly set to 1.</p>
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   <table class="params">
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         </tr>
       </table>
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+
+<p>MPU Region Base Address Register Value. </p>
 <p>This preprocessor function can be used to construct a valid <a class="el" href="structMPU__Type.html#a990c609b26d990b8ba832b110adfd353">RBAR</a> value. The VALID bit is implicitly set to 1.</p>
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   <table class="params">
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+
+<p>Enable the memory protection unit (MPU) and. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
     <tr><td class="paramname">MPU_CTRL</td><td>Additional control settings that configure MPU behaviour</td></tr>
@@ -607,7 +616,7 @@ Functions</h2></td></tr>
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:25 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
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docs/Core/html/group__mve__functions.html

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+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<title>MVE Functions</title>
+<title>CMSIS-Core (Cortex-M): MVE Functions</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<script type="text/javascript" src="jquery.js"></script>
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+  <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-Core (Cortex-M)
+   &#160;<span id="projectnumber">Version 5.4.0</span>
+   </div>
+   <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<div id="CMSISnav" class="tabs1">
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+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
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+<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark">&#160;</span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark">&#160;</span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark">&#160;</span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark">&#160;</span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark">&#160;</span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark">&#160;</span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark">&#160;</span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark">&#160;</span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark">&#160;</span>Pages</a></div>
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+        name="MSearchResults" id="MSearchResults">
+</iframe>
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+
+<div class="header">
+  <div class="summary">
+<a href="#func-members">Functions</a>  </div>
+  <div class="headertitle">
+<div class="title">MVE Functions</div>  </div>
+</div><!--header-->
+<div class="contents">
+
+<p>Functions that relate to the MVE (Cortex-M Vector Extensions) Unit.  
+<a href="#details">More...</a></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
+Functions</h2></td></tr>
+<tr class="memitem:ga9de35f6ff713a3cac7674baf49e22b72"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mve__functions.html#ga9de35f6ff713a3cac7674baf49e22b72">SCB_GetMVEType</a> (void)</td></tr>
+<tr class="memdesc:ga9de35f6ff713a3cac7674baf49e22b72"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get the MVE type.  <a href="#ga9de35f6ff713a3cac7674baf49e22b72">More...</a><br/></td></tr>
+<tr class="separator:ga9de35f6ff713a3cac7674baf49e22b72"><td class="memSeparator" colspan="2">&#160;</td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
+<p>Functions that relate to the MVE (Cortex-M Vector Extensions) Unit. </p>
+<p>Some Cortex-M processors include an optional MVE unit. </p>
+<h2 class="groupheader">Function Documentation</h2>
+<a class="anchor" id="ga9de35f6ff713a3cac7674baf49e22b72"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t SCB_GetMVEType </td>
+          <td>(</td>
+          <td class="paramtype">void&#160;</td>
+          <td class="paramname"></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Get the MVE type. </p>
+<p>Returns the MVE type. </p>
+<dl class="section return"><dt>Returns</dt><dd><ul>
+<li><b>0</b>: No Vector Extension (MVE)</li>
+<li><b>1</b>: Integer Vector Extension (MVE-I)</li>
+<li><b>2</b>: Floating-point Vector Extension (MVE-F) </li>
+</ul>
+</dd></dl>
+
+</div>
+</div>
+</div><!-- contents -->
+</div><!-- doc-content -->
+<!-- start footer part -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
+	<!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 
+	-->
+	</li>
+  </ul>
+</div>
+</body>
+</html>

docs/Core/html/group__mve__functions.js

@@ -0,0 +1,4 @@
+var group__mve__functions =
+[
+    [ "SCB_GetMVEType", "group__mve__functions.html#ga9de35f6ff713a3cac7674baf49e22b72", null ]
+];

docs/Core/html/group__nvic__trustzone__functions.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
-   &#160;<span id="projectnumber">Version 5.3.0</span>
+   &#160;<span id="projectnumber">Version 5.4.0</span>
    </div>
    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
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 </table>
 <a name="details" id="details"></a><h2 class="groupheader">Description</h2>
+<p>Nested Vector Interrupt Controller (NVIC) functions related to TrustZone for Armv8-M. </p>
 <h2 class="groupheader">Function Documentation</h2>
 <a class="anchor" id="ga3b30f8b602b593a806617b671a50731a"></a>
 <div class="memitem">
@@ -168,6 +169,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Clear Pending Interrupt (non-secure) </p>
 <p>Clears the pending bit of an non-secure external interrupt when in secure state. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -195,6 +198,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Disable External Interrupt (non-secure) </p>
 <p>Disables a device-specific interrupt in the non-secure NVIC when in secure state. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -222,6 +227,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Enable External Interrupt (non-secure) </p>
 <p>Enables a device-specific interrupt in the non-secure NVIC when in secure state. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -249,6 +256,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Get Active Interrupt (non-secure) </p>
 <p>Reads the active register in non-secure NVIC when in secure state and returns the active bit. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -279,6 +288,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Get Interrupt Enable status (non-secure) </p>
 <p>Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -309,6 +320,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Get Pending Interrupt (non-secure) </p>
 <p>Reads the pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified interrupt. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -339,6 +352,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Get Interrupt Priority (non-secure) </p>
 <p>Reads the priority of an non-secure interrupt when in secure state. The interrupt number can be positive to specify an external (device specific) interrupt, or negative to specify an internal (core) interrupt. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -367,6 +382,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Get Priority Grouping (non-secure) </p>
 <p>Reads the priority grouping field from the non-secure NVIC when in secure state. </p>
 <dl class="section return"><dt>Returns</dt><dd>Priority grouping field (SCB-&gt;AIRCR [10:8] PRIGROUP field). </dd></dl>
 <dl class="section note"><dt>Note</dt><dd>Only available for Armv8-M Mainline. </dd></dl>
@@ -390,6 +407,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Set Pending Interrupt (non-secure) </p>
 <p>Sets the pending bit of an non-secure external interrupt when in secure state. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -427,6 +446,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Set Interrupt Priority (non-secure) </p>
 <p>Sets the priority of an non-secure interrupt when in secure state. </p>
 <dl class="section note"><dt>Note</dt><dd>The priority cannot be set for every core interrupt. </dd></dl>
 <dl class="params"><dt>Parameters</dt><dd>
@@ -456,6 +477,8 @@ Functions</h2></td></tr>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Set Priority Grouping (non-secure) </p>
 <p>Sets the non-secure priority grouping field when in secure state using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB-&gt;AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
@@ -476,7 +499,7 @@ Functions</h2></td></tr>
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:25 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
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docs/Core/html/group__peripheral__gr.html

@@ -32,7 +32,7 @@
   <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
   <td style="padding-left: 0.5em;">
    <div id="projectname">CMSIS-Core (Cortex-M)
-   &#160;<span id="projectnumber">Version 5.3.0</span>
+   &#160;<span id="projectnumber">Version 5.4.0</span>
    </div>
    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
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 <tr class="separator:ga139b6e261c981f014f386927ca4a8444"><td class="memSeparator" colspan="2">&#160;</td></tr>
 </table>
 <a name="details" id="details"></a><h2 class="groupheader">Description</h2>
+<p>Naming conventions and optional features for accessing peripherals. </p>
 <p>The section below describes the naming conventions, requirements, and optional features for accessing device specific peripherals. Most of the rules also apply to the core peripherals. The <a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> contains typically these definition and also includes the core specific header files.</p>
 <p>The definitions for <a class="el" href="group__peripheral__gr.html">Peripheral Access</a> can be generated using the <a href="../../SVD/html/index.html"><b>CMSIS-SVD</b></a> System View Description for Peripherals. Refer to <a href="../../SVD/html/svd_SVDConv_pg.html"><b>SVDConv.exe</b></a> for more information.</p>
 <p>Each peripheral provides a data type definition with a name that is composed of:</p>
@@ -286,6 +287,8 @@ Register Bit Fields</h1>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Extract from a peripheral register value the a bit field value. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
     <tr><td class="paramname">field</td><td>name of bit field. </td></tr>
@@ -322,6 +325,8 @@ Register Bit Fields</h1>
         </tr>
       </table>
 </div><div class="memdoc">
+
+<p>Mask and shift a bit field value for assigning the result to a peripheral register. </p>
 <dl class="params"><dt>Parameters</dt><dd>
   <table class="params">
     <tr><td class="paramname">field</td><td>name of bit field. </td></tr>
@@ -340,7 +345,7 @@ Register Bit Fields</h1>
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
   <ul>
-    <li class="footer">Generated on Wed Jul 10 2019 15:20:25 for CMSIS-Core (Cortex-M) Version 5.3.0 by Arm Ltd. All rights reserved.
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:07 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
 	<!--
     <a href="http://www.doxygen.org/index.html">
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docs/Core/html/group__pmu8__events__armcm55.html

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+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<title>PMU Events for Cortex-M55</title>
+<title>CMSIS-Core (Cortex-M): PMU Events for Cortex-M55</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<script type="text/javascript" src="jquery.js"></script>
+<script type="text/javascript" src="dynsections.js"></script>
+<script type="text/javascript" src="printComponentTabs.js"></script>
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+<table cellspacing="0" cellpadding="0">
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+ <tr style="height: 46px;">
+  <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-Core (Cortex-M)
+   &#160;<span id="projectnumber">Version 5.4.0</span>
+   </div>
+   <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<div id="CMSISnav" class="tabs1">
+    <ul class="tablist">
+      <script type="text/javascript">
+		<!--
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+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
+      <li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
+      <li><a href="modules.html"><span>Reference</span></a></li>
+      <li>
+        <div id="MSearchBox" class="MSearchBoxInactive">
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+<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark">&#160;</span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark">&#160;</span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark">&#160;</span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark">&#160;</span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark">&#160;</span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark">&#160;</span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark">&#160;</span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark">&#160;</span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark">&#160;</span>Pages</a></div>
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+
+<div class="header">
+  <div class="summary">
+<a href="#define-members">Macros</a>  </div>
+  <div class="headertitle">
+<div class="title">PMU Events for Cortex-M55<div class="ingroups"><a class="el" href="group__pmu8__functions.html">PMU Functions for Armv8.1-M</a></div></div>  </div>
+</div><!--header-->
+<div class="contents">
+
+<p>IDs for additional events defined for Cortex-M55.  
+<a href="#details">More...</a></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
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+<tr class="memitem:gab423c79d244d071407afb49dfcfb6e05"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armcm55.html#gab423c79d244d071407afb49dfcfb6e05">ARMCM55_PMU_ECC_ERR</a>&#160;&#160;&#160;0xC000</td></tr>
+<tr class="memdesc:gab423c79d244d071407afb49dfcfb6e05"><td class="mdescLeft">&#160;</td><td class="mdescRight">Any ECC error.  <a href="#gab423c79d244d071407afb49dfcfb6e05">More...</a><br/></td></tr>
+<tr class="separator:gab423c79d244d071407afb49dfcfb6e05"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga88ab1b9d04cd44c53a92962fad8e3bdc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armcm55.html#ga88ab1b9d04cd44c53a92962fad8e3bdc">ARMCM55_PMU_ECC_ERR_FATAL</a>&#160;&#160;&#160;0xC001</td></tr>
+<tr class="memdesc:ga88ab1b9d04cd44c53a92962fad8e3bdc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Any fatal ECC error.  <a href="#ga88ab1b9d04cd44c53a92962fad8e3bdc">More...</a><br/></td></tr>
+<tr class="separator:ga88ab1b9d04cd44c53a92962fad8e3bdc"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="memdesc:gaa644074ec71c49e7e7a45d001bbdfb00"><td class="mdescLeft">&#160;</td><td class="mdescRight">Any ECC error in the data cache.  <a href="#gaa644074ec71c49e7e7a45d001bbdfb00">More...</a><br/></td></tr>
+<tr class="separator:gaa644074ec71c49e7e7a45d001bbdfb00"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="memdesc:ga7e31a482a7cf6bf6467487dcf2f89181"><td class="mdescLeft">&#160;</td><td class="mdescRight">Any ECC error in the instruction cache.  <a href="#ga7e31a482a7cf6bf6467487dcf2f89181">More...</a><br/></td></tr>
+<tr class="separator:ga7e31a482a7cf6bf6467487dcf2f89181"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga45cc9a0330e159e4afbce93e3cb5ef2e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armcm55.html#ga45cc9a0330e159e4afbce93e3cb5ef2e">ARMCM55_PMU_ECC_ERR_FATAL_DCACHE</a>&#160;&#160;&#160;0xC012</td></tr>
+<tr class="memdesc:ga45cc9a0330e159e4afbce93e3cb5ef2e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Any fatal ECC error in the data cache.  <a href="#ga45cc9a0330e159e4afbce93e3cb5ef2e">More...</a><br/></td></tr>
+<tr class="separator:ga45cc9a0330e159e4afbce93e3cb5ef2e"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gabe33023adf35df68a949d13212c379eb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armcm55.html#gabe33023adf35df68a949d13212c379eb">ARMCM55_PMU_ECC_ERR_FATAL_ICACHE</a>&#160;&#160;&#160;0xC013</td></tr>
+<tr class="memdesc:gabe33023adf35df68a949d13212c379eb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Any fatal ECC error in the instruction cache.  <a href="#gabe33023adf35df68a949d13212c379eb">More...</a><br/></td></tr>
+<tr class="separator:gabe33023adf35df68a949d13212c379eb"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gaca4db507dab60fce8df90f1a4bb862ad"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armcm55.html#gaca4db507dab60fce8df90f1a4bb862ad">ARMCM55_PMU_ECC_ERR_DTCM</a>&#160;&#160;&#160;0xC020</td></tr>
+<tr class="memdesc:gaca4db507dab60fce8df90f1a4bb862ad"><td class="mdescLeft">&#160;</td><td class="mdescRight">Any ECC error in the DTCM.  <a href="#gaca4db507dab60fce8df90f1a4bb862ad">More...</a><br/></td></tr>
+<tr class="separator:gaca4db507dab60fce8df90f1a4bb862ad"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gafc07c84258939e22cdb3b2e98dee0ac6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armcm55.html#gafc07c84258939e22cdb3b2e98dee0ac6">ARMCM55_PMU_ECC_ERR_ITCM</a>&#160;&#160;&#160;0xC021</td></tr>
+<tr class="memdesc:gafc07c84258939e22cdb3b2e98dee0ac6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Any ECC error in the ITCM.  <a href="#gafc07c84258939e22cdb3b2e98dee0ac6">More...</a><br/></td></tr>
+<tr class="separator:gafc07c84258939e22cdb3b2e98dee0ac6"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gad82225c528aa89689684fe5ddbe3c637"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armcm55.html#gad82225c528aa89689684fe5ddbe3c637">ARMCM55_PMU_ECC_ERR_FATAL_DTCM</a>&#160;&#160;&#160;0xC022</td></tr>
+<tr class="memdesc:gad82225c528aa89689684fe5ddbe3c637"><td class="mdescLeft">&#160;</td><td class="mdescRight">Any fatal ECC error in the DTCM.  <a href="#gad82225c528aa89689684fe5ddbe3c637">More...</a><br/></td></tr>
+<tr class="separator:gad82225c528aa89689684fe5ddbe3c637"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga0ed17ac3f8d8865e85d9690cbb51a06b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armcm55.html#ga0ed17ac3f8d8865e85d9690cbb51a06b">ARMCM55_PMU_ECC_ERR_FATAL_ITCM</a>&#160;&#160;&#160;0xC023</td></tr>
+<tr class="memdesc:ga0ed17ac3f8d8865e85d9690cbb51a06b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Any fatal ECC error in the ITCM.  <a href="#ga0ed17ac3f8d8865e85d9690cbb51a06b">More...</a><br/></td></tr>
+<tr class="separator:ga0ed17ac3f8d8865e85d9690cbb51a06b"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gad433a568f1a7ae448807f9e71173e6c2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armcm55.html#gad433a568f1a7ae448807f9e71173e6c2">ARMCM55_PMU_PF_LINEFILL</a>&#160;&#160;&#160;0xC100</td></tr>
+<tr class="memdesc:gad433a568f1a7ae448807f9e71173e6c2"><td class="mdescLeft">&#160;</td><td class="mdescRight">A prefetcher starts a line-fill.  <a href="#gad433a568f1a7ae448807f9e71173e6c2">More...</a><br/></td></tr>
+<tr class="separator:gad433a568f1a7ae448807f9e71173e6c2"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gad10f5c84036644353ee2dfb14b8e9f48"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armcm55.html#gad10f5c84036644353ee2dfb14b8e9f48">ARMCM55_PMU_PF_CANCEL</a>&#160;&#160;&#160;0xC101</td></tr>
+<tr class="memdesc:gad10f5c84036644353ee2dfb14b8e9f48"><td class="mdescLeft">&#160;</td><td class="mdescRight">A prefetcher stops prefetching.  <a href="#gad10f5c84036644353ee2dfb14b8e9f48">More...</a><br/></td></tr>
+<tr class="separator:gad10f5c84036644353ee2dfb14b8e9f48"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga1fafa33dc3bfb8f717fa04a0b868353c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armcm55.html#ga1fafa33dc3bfb8f717fa04a0b868353c">ARMCM55_PMU_PF_DROP_LINEFILL</a>&#160;&#160;&#160;0xC102</td></tr>
+<tr class="memdesc:ga1fafa33dc3bfb8f717fa04a0b868353c"><td class="mdescLeft">&#160;</td><td class="mdescRight">A linefill triggered by a prefetcher has been dropped because of lack of buffering.  <a href="#ga1fafa33dc3bfb8f717fa04a0b868353c">More...</a><br/></td></tr>
+<tr class="separator:ga1fafa33dc3bfb8f717fa04a0b868353c"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gaf3fcaa27702154d0739863b6462b8d73"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armcm55.html#gaf3fcaa27702154d0739863b6462b8d73">ARMCM55_PMU_NWAMODE_ENTER</a>&#160;&#160;&#160;0xC200</td></tr>
+<tr class="memdesc:gaf3fcaa27702154d0739863b6462b8d73"><td class="mdescLeft">&#160;</td><td class="mdescRight">No write-allocate mode entry.  <a href="#gaf3fcaa27702154d0739863b6462b8d73">More...</a><br/></td></tr>
+<tr class="separator:gaf3fcaa27702154d0739863b6462b8d73"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gab3f4da2771d4ca5edc9822d9a5353994"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armcm55.html#gab3f4da2771d4ca5edc9822d9a5353994">ARMCM55_PMU_NWAMODE</a>&#160;&#160;&#160;0xC201</td></tr>
+<tr class="memdesc:gab3f4da2771d4ca5edc9822d9a5353994"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write-allocate store is not allocated into the data cache due to no-write-allocate mode.  <a href="#gab3f4da2771d4ca5edc9822d9a5353994">More...</a><br/></td></tr>
+<tr class="separator:gab3f4da2771d4ca5edc9822d9a5353994"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gaadf0341d6a67cd30481201e7a3c7e77b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armcm55.html#gaadf0341d6a67cd30481201e7a3c7e77b">ARMCM55_PMU_SAHB_ACCESS</a>&#160;&#160;&#160;0xC300</td></tr>
+<tr class="memdesc:gaadf0341d6a67cd30481201e7a3c7e77b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read or write access on the S-AHB interface to the TCM.  <a href="#gaadf0341d6a67cd30481201e7a3c7e77b">More...</a><br/></td></tr>
+<tr class="separator:gaadf0341d6a67cd30481201e7a3c7e77b"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga8b005f5e47bc8bf9ee8d84a43b798ca9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armcm55.html#ga8b005f5e47bc8bf9ee8d84a43b798ca9">ARMCM55_PMU_DOSTIMEOUT_DOUBLE</a>&#160;&#160;&#160;0xC400</td></tr>
+<tr class="memdesc:ga8b005f5e47bc8bf9ee8d84a43b798ca9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress.  <a href="#ga8b005f5e47bc8bf9ee8d84a43b798ca9">More...</a><br/></td></tr>
+<tr class="separator:ga8b005f5e47bc8bf9ee8d84a43b798ca9"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga6bf0106f269b33afbe3482bab385f152"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armcm55.html#ga6bf0106f269b33afbe3482bab385f152">ARMCM55_PMU_DOSTIMEOUT_TRIPLE</a>&#160;&#160;&#160;0xC401</td></tr>
+<tr class="memdesc:ga6bf0106f269b33afbe3482bab385f152"><td class="mdescLeft">&#160;</td><td class="mdescRight">Denial of Service timeout has fired three times and blocked the LSU to force forward progress.  <a href="#ga6bf0106f269b33afbe3482bab385f152">More...</a><br/></td></tr>
+<tr class="separator:ga6bf0106f269b33afbe3482bab385f152"><td class="memSeparator" colspan="2">&#160;</td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
+<p>IDs for additional events defined for Cortex-M55. </p>
+<p>These events are available on a Cortex-M55 device including a PMU. </p>
+<h2 class="groupheader">Macro Definition Documentation</h2>
+<a class="anchor" id="ga8b005f5e47bc8bf9ee8d84a43b798ca9"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARMCM55_PMU_DOSTIMEOUT_DOUBLE&#160;&#160;&#160;0xC400</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga6bf0106f269b33afbe3482bab385f152"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARMCM55_PMU_DOSTIMEOUT_TRIPLE&#160;&#160;&#160;0xC401</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Denial of Service timeout has fired three times and blocked the LSU to force forward progress. </p>
+
+</div>
+</div>
+<a class="anchor" id="gab423c79d244d071407afb49dfcfb6e05"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARMCM55_PMU_ECC_ERR&#160;&#160;&#160;0xC000</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Any ECC error. </p>
+
+</div>
+</div>
+<a class="anchor" id="gaa644074ec71c49e7e7a45d001bbdfb00"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARMCM55_PMU_ECC_ERR_DCACHE&#160;&#160;&#160;0xC010</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Any ECC error in the data cache. </p>
+
+</div>
+</div>
+<a class="anchor" id="gaca4db507dab60fce8df90f1a4bb862ad"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARMCM55_PMU_ECC_ERR_DTCM&#160;&#160;&#160;0xC020</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Any ECC error in the DTCM. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga88ab1b9d04cd44c53a92962fad8e3bdc"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARMCM55_PMU_ECC_ERR_FATAL&#160;&#160;&#160;0xC001</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Any fatal ECC error. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga45cc9a0330e159e4afbce93e3cb5ef2e"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARMCM55_PMU_ECC_ERR_FATAL_DCACHE&#160;&#160;&#160;0xC012</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Any fatal ECC error in the data cache. </p>
+
+</div>
+</div>
+<a class="anchor" id="gad82225c528aa89689684fe5ddbe3c637"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARMCM55_PMU_ECC_ERR_FATAL_DTCM&#160;&#160;&#160;0xC022</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Any fatal ECC error in the DTCM. </p>
+
+</div>
+</div>
+<a class="anchor" id="gabe33023adf35df68a949d13212c379eb"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARMCM55_PMU_ECC_ERR_FATAL_ICACHE&#160;&#160;&#160;0xC013</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Any fatal ECC error in the instruction cache. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga0ed17ac3f8d8865e85d9690cbb51a06b"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARMCM55_PMU_ECC_ERR_FATAL_ITCM&#160;&#160;&#160;0xC023</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Any fatal ECC error in the ITCM. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga7e31a482a7cf6bf6467487dcf2f89181"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARMCM55_PMU_ECC_ERR_ICACHE&#160;&#160;&#160;0xC011</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Any ECC error in the instruction cache. </p>
+
+</div>
+</div>
+<a class="anchor" id="gafc07c84258939e22cdb3b2e98dee0ac6"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARMCM55_PMU_ECC_ERR_ITCM&#160;&#160;&#160;0xC021</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Any ECC error in the ITCM. </p>
+
+</div>
+</div>
+<a class="anchor" id="gab3f4da2771d4ca5edc9822d9a5353994"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARMCM55_PMU_NWAMODE&#160;&#160;&#160;0xC201</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Write-allocate store is not allocated into the data cache due to no-write-allocate mode. </p>
+
+</div>
+</div>
+<a class="anchor" id="gaf3fcaa27702154d0739863b6462b8d73"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARMCM55_PMU_NWAMODE_ENTER&#160;&#160;&#160;0xC200</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>No write-allocate mode entry. </p>
+
+</div>
+</div>
+<a class="anchor" id="gad10f5c84036644353ee2dfb14b8e9f48"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARMCM55_PMU_PF_CANCEL&#160;&#160;&#160;0xC101</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>A prefetcher stops prefetching. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga1fafa33dc3bfb8f717fa04a0b868353c"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARMCM55_PMU_PF_DROP_LINEFILL&#160;&#160;&#160;0xC102</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>A linefill triggered by a prefetcher has been dropped because of lack of buffering. </p>
+
+</div>
+</div>
+<a class="anchor" id="gad433a568f1a7ae448807f9e71173e6c2"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARMCM55_PMU_PF_LINEFILL&#160;&#160;&#160;0xC100</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>A prefetcher starts a line-fill. </p>
+
+</div>
+</div>
+<a class="anchor" id="gaadf0341d6a67cd30481201e7a3c7e77b"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARMCM55_PMU_SAHB_ACCESS&#160;&#160;&#160;0xC300</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Read or write access on the S-AHB interface to the TCM. </p>
+
+</div>
+</div>
+</div><!-- contents -->
+</div><!-- doc-content -->
+<!-- start footer part -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
+	<!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 
+	-->
+	</li>
+  </ul>
+</div>
+</body>
+</html>

docs/Core/html/group__pmu8__events__armcm55.js

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+    [ "ARMCM55_PMU_DOSTIMEOUT_TRIPLE", "group__pmu8__events__armcm55.html#ga6bf0106f269b33afbe3482bab385f152", null ],
+    [ "ARMCM55_PMU_ECC_ERR", "group__pmu8__events__armcm55.html#gab423c79d244d071407afb49dfcfb6e05", null ],
+    [ "ARMCM55_PMU_ECC_ERR_DCACHE", "group__pmu8__events__armcm55.html#gaa644074ec71c49e7e7a45d001bbdfb00", null ],
+    [ "ARMCM55_PMU_ECC_ERR_DTCM", "group__pmu8__events__armcm55.html#gaca4db507dab60fce8df90f1a4bb862ad", null ],
+    [ "ARMCM55_PMU_ECC_ERR_FATAL", "group__pmu8__events__armcm55.html#ga88ab1b9d04cd44c53a92962fad8e3bdc", null ],
+    [ "ARMCM55_PMU_ECC_ERR_FATAL_DCACHE", "group__pmu8__events__armcm55.html#ga45cc9a0330e159e4afbce93e3cb5ef2e", null ],
+    [ "ARMCM55_PMU_ECC_ERR_FATAL_DTCM", "group__pmu8__events__armcm55.html#gad82225c528aa89689684fe5ddbe3c637", null ],
+    [ "ARMCM55_PMU_ECC_ERR_FATAL_ICACHE", "group__pmu8__events__armcm55.html#gabe33023adf35df68a949d13212c379eb", null ],
+    [ "ARMCM55_PMU_ECC_ERR_FATAL_ITCM", "group__pmu8__events__armcm55.html#ga0ed17ac3f8d8865e85d9690cbb51a06b", null ],
+    [ "ARMCM55_PMU_ECC_ERR_ICACHE", "group__pmu8__events__armcm55.html#ga7e31a482a7cf6bf6467487dcf2f89181", null ],
+    [ "ARMCM55_PMU_ECC_ERR_ITCM", "group__pmu8__events__armcm55.html#gafc07c84258939e22cdb3b2e98dee0ac6", null ],
+    [ "ARMCM55_PMU_NWAMODE", "group__pmu8__events__armcm55.html#gab3f4da2771d4ca5edc9822d9a5353994", null ],
+    [ "ARMCM55_PMU_NWAMODE_ENTER", "group__pmu8__events__armcm55.html#gaf3fcaa27702154d0739863b6462b8d73", null ],
+    [ "ARMCM55_PMU_PF_CANCEL", "group__pmu8__events__armcm55.html#gad10f5c84036644353ee2dfb14b8e9f48", null ],
+    [ "ARMCM55_PMU_PF_DROP_LINEFILL", "group__pmu8__events__armcm55.html#ga1fafa33dc3bfb8f717fa04a0b868353c", null ],
+    [ "ARMCM55_PMU_PF_LINEFILL", "group__pmu8__events__armcm55.html#gad433a568f1a7ae448807f9e71173e6c2", null ],
+    [ "ARMCM55_PMU_SAHB_ACCESS", "group__pmu8__events__armcm55.html#gaadf0341d6a67cd30481201e7a3c7e77b", null ]
+];

docs/Core/html/group__pmu8__events__armv81.html

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+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
+<meta http-equiv="X-UA-Compatible" content="IE=9"/>
+<title>PMU Events for Armv8.1-M</title>
+<title>CMSIS-Core (Cortex-M): PMU Events for Armv8.1-M</title>
+<link href="tabs.css" rel="stylesheet" type="text/css"/>
+<link href="cmsis.css" rel="stylesheet" type="text/css" />
+<script type="text/javascript" src="jquery.js"></script>
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+<script type="text/javascript" src="resize.js"></script>
+<script type="text/javascript" src="navtree.js"></script>
+<script type="text/javascript">
+  $(document).ready(initResizable);
+  $(window).load(resizeHeight);
+</script>
+<link href="search/search.css" rel="stylesheet" type="text/css"/>
+<script type="text/javascript" src="search/search.js"></script>
+<script type="text/javascript">
+  $(document).ready(function() { searchBox.OnSelectItem(0); });
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+  <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
+  <td style="padding-left: 0.5em;">
+   <div id="projectname">CMSIS-Core (Cortex-M)
+   &#160;<span id="projectnumber">Version 5.4.0</span>
+   </div>
+   <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
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+      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
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+     onmouseout="return searchBox.OnSearchSelectHide()"
+     onkeydown="return searchBox.OnSearchSelectKey(event)">
+<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark">&#160;</span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark">&#160;</span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark">&#160;</span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark">&#160;</span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark">&#160;</span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark">&#160;</span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark">&#160;</span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark">&#160;</span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark">&#160;</span>Pages</a></div>
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+
+<div class="header">
+  <div class="summary">
+<a href="#define-members">Macros</a>  </div>
+  <div class="headertitle">
+<div class="title">PMU Events for Armv8.1-M<div class="ingroups"><a class="el" href="group__pmu8__functions.html">PMU Functions for Armv8.1-M</a></div></div>  </div>
+</div><!--header-->
+<div class="contents">
+
+<p>IDs for Armv8.1-M architecture defined events.  
+<a href="#details">More...</a></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
+Macros</h2></td></tr>
+<tr class="memitem:ga6e02b08550d7e9b273ff7913f1b57bea"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga6e02b08550d7e9b273ff7913f1b57bea">ARM_PMU_SW_INCR</a>&#160;&#160;&#160;0x0000</td></tr>
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+<tr class="separator:ga6e02b08550d7e9b273ff7913f1b57bea"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gac43e0e0f9e385ea66402bdeebf3fea3e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gac43e0e0f9e385ea66402bdeebf3fea3e">ARM_PMU_L1I_CACHE_REFILL</a>&#160;&#160;&#160;0x0001</td></tr>
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+<tr class="separator:gac43e0e0f9e385ea66402bdeebf3fea3e"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga64a3d7bfb7ec9d7bdeb073a4fe1bbc38"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga64a3d7bfb7ec9d7bdeb073a4fe1bbc38">ARM_PMU_L1D_CACHE_REFILL</a>&#160;&#160;&#160;0x0003</td></tr>
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+<tr class="separator:ga64a3d7bfb7ec9d7bdeb073a4fe1bbc38"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga7505ae74c1d905f01b05dd5466c1efc0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga7505ae74c1d905f01b05dd5466c1efc0">ARM_PMU_L1D_CACHE</a>&#160;&#160;&#160;0x0004</td></tr>
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+<tr class="separator:ga7505ae74c1d905f01b05dd5466c1efc0"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:ga2e8725ee07c2b2c75a1b54261bc26cc8"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga8179d1144f8ec993bd1343e276d7b49b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga8179d1144f8ec993bd1343e276d7b49b">ARM_PMU_ST_RETIRED</a>&#160;&#160;&#160;0x0007</td></tr>
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+<tr class="separator:ga8179d1144f8ec993bd1343e276d7b49b"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga8a5e60eee460addfc66e275a2c4c4800"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga8a5e60eee460addfc66e275a2c4c4800">ARM_PMU_INST_RETIRED</a>&#160;&#160;&#160;0x0008</td></tr>
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+<tr class="separator:ga8a5e60eee460addfc66e275a2c4c4800"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gac97858bd621eab4592569444f0a5c37f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gac97858bd621eab4592569444f0a5c37f">ARM_PMU_EXC_TAKEN</a>&#160;&#160;&#160;0x0009</td></tr>
+<tr class="memdesc:gac97858bd621eab4592569444f0a5c37f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Exception entry.  <a href="#gac97858bd621eab4592569444f0a5c37f">More...</a><br/></td></tr>
+<tr class="separator:gac97858bd621eab4592569444f0a5c37f"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gaf9424157e9c5dca3a3689d181005c4f8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaf9424157e9c5dca3a3689d181005c4f8">ARM_PMU_EXC_RETURN</a>&#160;&#160;&#160;0x000A</td></tr>
+<tr class="memdesc:gaf9424157e9c5dca3a3689d181005c4f8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Exception return instruction architecturally executed and the condition code check pass.  <a href="#gaf9424157e9c5dca3a3689d181005c4f8">More...</a><br/></td></tr>
+<tr class="separator:gaf9424157e9c5dca3a3689d181005c4f8"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga54fd2c392399221077c67866a395e587"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga54fd2c392399221077c67866a395e587">ARM_PMU_PC_WRITE_RETIRED</a>&#160;&#160;&#160;0x000C</td></tr>
+<tr class="memdesc:ga54fd2c392399221077c67866a395e587"><td class="mdescLeft">&#160;</td><td class="mdescRight">Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass.  <a href="#ga54fd2c392399221077c67866a395e587">More...</a><br/></td></tr>
+<tr class="separator:ga54fd2c392399221077c67866a395e587"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga22bfb189fff7c1ea9f81097a543ed756"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga22bfb189fff7c1ea9f81097a543ed756">ARM_PMU_BR_IMMED_RETIRED</a>&#160;&#160;&#160;0x000D</td></tr>
+<tr class="memdesc:ga22bfb189fff7c1ea9f81097a543ed756"><td class="mdescLeft">&#160;</td><td class="mdescRight">Immediate branch architecturally executed.  <a href="#ga22bfb189fff7c1ea9f81097a543ed756">More...</a><br/></td></tr>
+<tr class="separator:ga22bfb189fff7c1ea9f81097a543ed756"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gab717347b1c3601cffb9c99b43b2a45c5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gab717347b1c3601cffb9c99b43b2a45c5">ARM_PMU_BR_RETURN_RETIRED</a>&#160;&#160;&#160;0x000E</td></tr>
+<tr class="memdesc:gab717347b1c3601cffb9c99b43b2a45c5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Function return instruction architecturally executed and the condition code check pass.  <a href="#gab717347b1c3601cffb9c99b43b2a45c5">More...</a><br/></td></tr>
+<tr class="separator:gab717347b1c3601cffb9c99b43b2a45c5"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga45d5ea86fdc015f4fc100462150c92da"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga45d5ea86fdc015f4fc100462150c92da">ARM_PMU_UNALIGNED_LDST_RETIRED</a>&#160;&#160;&#160;0x000F</td></tr>
+<tr class="memdesc:ga45d5ea86fdc015f4fc100462150c92da"><td class="mdescLeft">&#160;</td><td class="mdescRight">Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass.  <a href="#ga45d5ea86fdc015f4fc100462150c92da">More...</a><br/></td></tr>
+<tr class="separator:ga45d5ea86fdc015f4fc100462150c92da"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gabfa921c85a61f0a21c9bee289e63c102"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gabfa921c85a61f0a21c9bee289e63c102">ARM_PMU_BR_MIS_PRED</a>&#160;&#160;&#160;0x0010</td></tr>
+<tr class="memdesc:gabfa921c85a61f0a21c9bee289e63c102"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mispredicted or not predicted branch speculatively executed.  <a href="#gabfa921c85a61f0a21c9bee289e63c102">More...</a><br/></td></tr>
+<tr class="separator:gabfa921c85a61f0a21c9bee289e63c102"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga550d524d435a653b2f46acc1380a5ace"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga550d524d435a653b2f46acc1380a5ace">ARM_PMU_CPU_CYCLES</a>&#160;&#160;&#160;0x0011</td></tr>
+<tr class="memdesc:ga550d524d435a653b2f46acc1380a5ace"><td class="mdescLeft">&#160;</td><td class="mdescRight">Cycle.  <a href="#ga550d524d435a653b2f46acc1380a5ace">More...</a><br/></td></tr>
+<tr class="separator:ga550d524d435a653b2f46acc1380a5ace"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga60ccf42eae576e2fde3b9e17a8defeaa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga60ccf42eae576e2fde3b9e17a8defeaa">ARM_PMU_BR_PRED</a>&#160;&#160;&#160;0x0012</td></tr>
+<tr class="memdesc:ga60ccf42eae576e2fde3b9e17a8defeaa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Predictable branch speculatively executed.  <a href="#ga60ccf42eae576e2fde3b9e17a8defeaa">More...</a><br/></td></tr>
+<tr class="separator:ga60ccf42eae576e2fde3b9e17a8defeaa"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gab3852c2b3d59af106b9db7ea2c20c367"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gab3852c2b3d59af106b9db7ea2c20c367">ARM_PMU_MEM_ACCESS</a>&#160;&#160;&#160;0x0013</td></tr>
+<tr class="memdesc:gab3852c2b3d59af106b9db7ea2c20c367"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data memory access.  <a href="#gab3852c2b3d59af106b9db7ea2c20c367">More...</a><br/></td></tr>
+<tr class="separator:gab3852c2b3d59af106b9db7ea2c20c367"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gaf8e89b2b098e6bec5916517346925ce2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaf8e89b2b098e6bec5916517346925ce2">ARM_PMU_L1I_CACHE</a>&#160;&#160;&#160;0x0014</td></tr>
+<tr class="memdesc:gaf8e89b2b098e6bec5916517346925ce2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Level 1 instruction cache access.  <a href="#gaf8e89b2b098e6bec5916517346925ce2">More...</a><br/></td></tr>
+<tr class="separator:gaf8e89b2b098e6bec5916517346925ce2"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga27d1b8b2c37ae0ae41781880ed3893d0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga27d1b8b2c37ae0ae41781880ed3893d0">ARM_PMU_L1D_CACHE_WB</a>&#160;&#160;&#160;0x0015</td></tr>
+<tr class="memdesc:ga27d1b8b2c37ae0ae41781880ed3893d0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Level 1 data cache write-back.  <a href="#ga27d1b8b2c37ae0ae41781880ed3893d0">More...</a><br/></td></tr>
+<tr class="separator:ga27d1b8b2c37ae0ae41781880ed3893d0"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gafb1e1f86d091ccb735858769c700e289"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gafb1e1f86d091ccb735858769c700e289">ARM_PMU_L2D_CACHE</a>&#160;&#160;&#160;0x0016</td></tr>
+<tr class="memdesc:gafb1e1f86d091ccb735858769c700e289"><td class="mdescLeft">&#160;</td><td class="mdescRight">Level 2 data cache access.  <a href="#gafb1e1f86d091ccb735858769c700e289">More...</a><br/></td></tr>
+<tr class="separator:gafb1e1f86d091ccb735858769c700e289"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gaeb414c1b0375022abc2502ab503a3284"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaeb414c1b0375022abc2502ab503a3284">ARM_PMU_L2D_CACHE_REFILL</a>&#160;&#160;&#160;0x0017</td></tr>
+<tr class="memdesc:gaeb414c1b0375022abc2502ab503a3284"><td class="mdescLeft">&#160;</td><td class="mdescRight">Level 2 data cache refill.  <a href="#gaeb414c1b0375022abc2502ab503a3284">More...</a><br/></td></tr>
+<tr class="separator:gaeb414c1b0375022abc2502ab503a3284"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga1a0c4a1990eeed88edc3e1e0c4b1aca0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga1a0c4a1990eeed88edc3e1e0c4b1aca0">ARM_PMU_L2D_CACHE_WB</a>&#160;&#160;&#160;0x0018</td></tr>
+<tr class="memdesc:ga1a0c4a1990eeed88edc3e1e0c4b1aca0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Level 2 data cache write-back.  <a href="#ga1a0c4a1990eeed88edc3e1e0c4b1aca0">More...</a><br/></td></tr>
+<tr class="separator:ga1a0c4a1990eeed88edc3e1e0c4b1aca0"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gaa681d3db56b42775093869b8fdf1abb9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaa681d3db56b42775093869b8fdf1abb9">ARM_PMU_BUS_ACCESS</a>&#160;&#160;&#160;0x0019</td></tr>
+<tr class="memdesc:gaa681d3db56b42775093869b8fdf1abb9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bus access.  <a href="#gaa681d3db56b42775093869b8fdf1abb9">More...</a><br/></td></tr>
+<tr class="separator:gaa681d3db56b42775093869b8fdf1abb9"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga2c8d23cc64e87b2044bb39bf8d0bc1b1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga2c8d23cc64e87b2044bb39bf8d0bc1b1">ARM_PMU_MEMORY_ERROR</a>&#160;&#160;&#160;0x001A</td></tr>
+<tr class="memdesc:ga2c8d23cc64e87b2044bb39bf8d0bc1b1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Local memory error.  <a href="#ga2c8d23cc64e87b2044bb39bf8d0bc1b1">More...</a><br/></td></tr>
+<tr class="separator:ga2c8d23cc64e87b2044bb39bf8d0bc1b1"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gaf7bad54617ace5c2fb48bc2e8aebf9c7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaf7bad54617ace5c2fb48bc2e8aebf9c7">ARM_PMU_INST_SPEC</a>&#160;&#160;&#160;0x001B</td></tr>
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+<tr class="separator:gaf7bad54617ace5c2fb48bc2e8aebf9c7"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gae4c955416707f44f066ffd2560b9ae4c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gae4c955416707f44f066ffd2560b9ae4c">ARM_PMU_BUS_CYCLES</a>&#160;&#160;&#160;0x001D</td></tr>
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+<tr class="separator:gae4c955416707f44f066ffd2560b9ae4c"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gaca14907c5a1e1f9915159bc4cf323cf0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaca14907c5a1e1f9915159bc4cf323cf0">ARM_PMU_CHAIN</a>&#160;&#160;&#160;0x001E</td></tr>
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+<tr class="separator:gaca14907c5a1e1f9915159bc4cf323cf0"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gab55334c8510cb30c4c750913f6eb6279"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gab55334c8510cb30c4c750913f6eb6279">ARM_PMU_L1D_CACHE_ALLOCATE</a>&#160;&#160;&#160;0x001F</td></tr>
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+<tr class="separator:gab55334c8510cb30c4c750913f6eb6279"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gaad08dcded491bf257d223e4171af41cc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaad08dcded491bf257d223e4171af41cc">ARM_PMU_L2D_CACHE_ALLOCATE</a>&#160;&#160;&#160;0x0020</td></tr>
+<tr class="memdesc:gaad08dcded491bf257d223e4171af41cc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Level 2 data cache allocation without refill.  <a href="#gaad08dcded491bf257d223e4171af41cc">More...</a><br/></td></tr>
+<tr class="separator:gaad08dcded491bf257d223e4171af41cc"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gab3b505a8bcc2b2885626d2f2cd542b73"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gab3b505a8bcc2b2885626d2f2cd542b73">ARM_PMU_BR_RETIRED</a>&#160;&#160;&#160;0x0021</td></tr>
+<tr class="memdesc:gab3b505a8bcc2b2885626d2f2cd542b73"><td class="mdescLeft">&#160;</td><td class="mdescRight">Branch instruction architecturally executed.  <a href="#gab3b505a8bcc2b2885626d2f2cd542b73">More...</a><br/></td></tr>
+<tr class="separator:gab3b505a8bcc2b2885626d2f2cd542b73"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gae12baa616c5f0cdd081231fcf8cdad68"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gae12baa616c5f0cdd081231fcf8cdad68">ARM_PMU_BR_MIS_PRED_RETIRED</a>&#160;&#160;&#160;0x0022</td></tr>
+<tr class="memdesc:gae12baa616c5f0cdd081231fcf8cdad68"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mispredicted branch instruction architecturally executed.  <a href="#gae12baa616c5f0cdd081231fcf8cdad68">More...</a><br/></td></tr>
+<tr class="separator:gae12baa616c5f0cdd081231fcf8cdad68"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga5b068593baa831348664dfa7d44f5483"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga5b068593baa831348664dfa7d44f5483">ARM_PMU_STALL_FRONTEND</a>&#160;&#160;&#160;0x0023</td></tr>
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+<tr class="separator:ga5b068593baa831348664dfa7d44f5483"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga8737bee352820bd7d1bc8e5e4260143c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga8737bee352820bd7d1bc8e5e4260143c">ARM_PMU_STALL_BACKEND</a>&#160;&#160;&#160;0x0024</td></tr>
+<tr class="memdesc:ga8737bee352820bd7d1bc8e5e4260143c"><td class="mdescLeft">&#160;</td><td class="mdescRight">No operation issued because of the backend.  <a href="#ga8737bee352820bd7d1bc8e5e4260143c">More...</a><br/></td></tr>
+<tr class="separator:ga8737bee352820bd7d1bc8e5e4260143c"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga3406498b2c17ca080ebd68cc40d9630e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga3406498b2c17ca080ebd68cc40d9630e">ARM_PMU_L2I_CACHE</a>&#160;&#160;&#160;0x0027</td></tr>
+<tr class="memdesc:ga3406498b2c17ca080ebd68cc40d9630e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Level 2 instruction cache access.  <a href="#ga3406498b2c17ca080ebd68cc40d9630e">More...</a><br/></td></tr>
+<tr class="separator:ga3406498b2c17ca080ebd68cc40d9630e"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gaa18cee03802b46076e9ab66fd0a7c61d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaa18cee03802b46076e9ab66fd0a7c61d">ARM_PMU_L2I_CACHE_REFILL</a>&#160;&#160;&#160;0x0028</td></tr>
+<tr class="memdesc:gaa18cee03802b46076e9ab66fd0a7c61d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Level 2 instruction cache refill.  <a href="#gaa18cee03802b46076e9ab66fd0a7c61d">More...</a><br/></td></tr>
+<tr class="separator:gaa18cee03802b46076e9ab66fd0a7c61d"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gac11cbc6849dbad7bd8b64ab6e2a3f8d5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gac11cbc6849dbad7bd8b64ab6e2a3f8d5">ARM_PMU_L3D_CACHE_ALLOCATE</a>&#160;&#160;&#160;0x0029</td></tr>
+<tr class="memdesc:gac11cbc6849dbad7bd8b64ab6e2a3f8d5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Level 3 data cache allocation without refill.  <a href="#gac11cbc6849dbad7bd8b64ab6e2a3f8d5">More...</a><br/></td></tr>
+<tr class="separator:gac11cbc6849dbad7bd8b64ab6e2a3f8d5"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gafe99db0693125100272247c147fb3b02"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gafe99db0693125100272247c147fb3b02">ARM_PMU_L3D_CACHE_REFILL</a>&#160;&#160;&#160;0x002A</td></tr>
+<tr class="memdesc:gafe99db0693125100272247c147fb3b02"><td class="mdescLeft">&#160;</td><td class="mdescRight">Level 3 data cache refill.  <a href="#gafe99db0693125100272247c147fb3b02">More...</a><br/></td></tr>
+<tr class="separator:gafe99db0693125100272247c147fb3b02"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga4e96b5a6fb13c657e78da342a02db200"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga4e96b5a6fb13c657e78da342a02db200">ARM_PMU_L3D_CACHE</a>&#160;&#160;&#160;0x002B</td></tr>
+<tr class="memdesc:ga4e96b5a6fb13c657e78da342a02db200"><td class="mdescLeft">&#160;</td><td class="mdescRight">Level 3 data cache access.  <a href="#ga4e96b5a6fb13c657e78da342a02db200">More...</a><br/></td></tr>
+<tr class="separator:ga4e96b5a6fb13c657e78da342a02db200"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gab823f95f7ac8196a208d12381b1b2a11"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gab823f95f7ac8196a208d12381b1b2a11">ARM_PMU_L3D_CACHE_WB</a>&#160;&#160;&#160;0x002C</td></tr>
+<tr class="memdesc:gab823f95f7ac8196a208d12381b1b2a11"><td class="mdescLeft">&#160;</td><td class="mdescRight">Level 3 data cache write-back.  <a href="#gab823f95f7ac8196a208d12381b1b2a11">More...</a><br/></td></tr>
+<tr class="separator:gab823f95f7ac8196a208d12381b1b2a11"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga902562d8161fffd45726dc4cc8727545"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga902562d8161fffd45726dc4cc8727545">ARM_PMU_LL_CACHE_RD</a>&#160;&#160;&#160;0x0036</td></tr>
+<tr class="memdesc:ga902562d8161fffd45726dc4cc8727545"><td class="mdescLeft">&#160;</td><td class="mdescRight">Last level data cache read.  <a href="#ga902562d8161fffd45726dc4cc8727545">More...</a><br/></td></tr>
+<tr class="separator:ga902562d8161fffd45726dc4cc8727545"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga6979efa69af7d0e62cc3e2f88b0155b8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga6979efa69af7d0e62cc3e2f88b0155b8">ARM_PMU_LL_CACHE_MISS_RD</a>&#160;&#160;&#160;0x0037</td></tr>
+<tr class="memdesc:ga6979efa69af7d0e62cc3e2f88b0155b8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Last level data cache read miss.  <a href="#ga6979efa69af7d0e62cc3e2f88b0155b8">More...</a><br/></td></tr>
+<tr class="separator:ga6979efa69af7d0e62cc3e2f88b0155b8"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga4687d5d7efc6f49db2db9acc25b590f6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga4687d5d7efc6f49db2db9acc25b590f6">ARM_PMU_L1D_CACHE_MISS_RD</a>&#160;&#160;&#160;0x0039</td></tr>
+<tr class="memdesc:ga4687d5d7efc6f49db2db9acc25b590f6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Level 1 data cache read miss.  <a href="#ga4687d5d7efc6f49db2db9acc25b590f6">More...</a><br/></td></tr>
+<tr class="separator:ga4687d5d7efc6f49db2db9acc25b590f6"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga2fe9d3ea67ce833bd6323e4ce1a4e894"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga2fe9d3ea67ce833bd6323e4ce1a4e894">ARM_PMU_OP_COMPLETE</a>&#160;&#160;&#160;0x003A</td></tr>
+<tr class="memdesc:ga2fe9d3ea67ce833bd6323e4ce1a4e894"><td class="mdescLeft">&#160;</td><td class="mdescRight">Operation retired.  <a href="#ga2fe9d3ea67ce833bd6323e4ce1a4e894">More...</a><br/></td></tr>
+<tr class="separator:ga2fe9d3ea67ce833bd6323e4ce1a4e894"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga6c59149e9b1754987b44b62092bc9f09"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga6c59149e9b1754987b44b62092bc9f09">ARM_PMU_OP_SPEC</a>&#160;&#160;&#160;0x003B</td></tr>
+<tr class="memdesc:ga6c59149e9b1754987b44b62092bc9f09"><td class="mdescLeft">&#160;</td><td class="mdescRight">Operation speculatively executed.  <a href="#ga6c59149e9b1754987b44b62092bc9f09">More...</a><br/></td></tr>
+<tr class="separator:ga6c59149e9b1754987b44b62092bc9f09"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga8bf75efa06a125ee2dfa9a130e7ba9a8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga8bf75efa06a125ee2dfa9a130e7ba9a8">ARM_PMU_STALL</a>&#160;&#160;&#160;0x003C</td></tr>
+<tr class="memdesc:ga8bf75efa06a125ee2dfa9a130e7ba9a8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Stall cycle for instruction or operation not sent for execution.  <a href="#ga8bf75efa06a125ee2dfa9a130e7ba9a8">More...</a><br/></td></tr>
+<tr class="separator:ga8bf75efa06a125ee2dfa9a130e7ba9a8"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga9700ec74727a9fe3cd4cd40736628a23"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga9700ec74727a9fe3cd4cd40736628a23">ARM_PMU_STALL_OP_BACKEND</a>&#160;&#160;&#160;0x003D</td></tr>
+<tr class="memdesc:ga9700ec74727a9fe3cd4cd40736628a23"><td class="mdescLeft">&#160;</td><td class="mdescRight">Stall cycle for instruction or operation not sent for execution due to pipeline backend.  <a href="#ga9700ec74727a9fe3cd4cd40736628a23">More...</a><br/></td></tr>
+<tr class="separator:ga9700ec74727a9fe3cd4cd40736628a23"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga69cfd3558cf6c6f3bb621ee75430427c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga69cfd3558cf6c6f3bb621ee75430427c">ARM_PMU_STALL_OP_FRONTEND</a>&#160;&#160;&#160;0x003E</td></tr>
+<tr class="memdesc:ga69cfd3558cf6c6f3bb621ee75430427c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Stall cycle for instruction or operation not sent for execution due to pipeline frontend.  <a href="#ga69cfd3558cf6c6f3bb621ee75430427c">More...</a><br/></td></tr>
+<tr class="separator:ga69cfd3558cf6c6f3bb621ee75430427c"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga197b491f691110fb52aef4291782b6ab"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga197b491f691110fb52aef4291782b6ab">ARM_PMU_STALL_OP</a>&#160;&#160;&#160;0x003F</td></tr>
+<tr class="memdesc:ga197b491f691110fb52aef4291782b6ab"><td class="mdescLeft">&#160;</td><td class="mdescRight">Instruction or operation slots not occupied each cycle.  <a href="#ga197b491f691110fb52aef4291782b6ab">More...</a><br/></td></tr>
+<tr class="separator:ga197b491f691110fb52aef4291782b6ab"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gaf4236dfbcb4550d3cc98caee837e8e77"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaf4236dfbcb4550d3cc98caee837e8e77">ARM_PMU_L1D_CACHE_RD</a>&#160;&#160;&#160;0x0040</td></tr>
+<tr class="memdesc:gaf4236dfbcb4550d3cc98caee837e8e77"><td class="mdescLeft">&#160;</td><td class="mdescRight">Level 1 data cache read.  <a href="#gaf4236dfbcb4550d3cc98caee837e8e77">More...</a><br/></td></tr>
+<tr class="separator:gaf4236dfbcb4550d3cc98caee837e8e77"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga345461506c990125b1f2cbc62e3be22f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga345461506c990125b1f2cbc62e3be22f">ARM_PMU_LE_RETIRED</a>&#160;&#160;&#160;0x0100</td></tr>
+<tr class="memdesc:ga345461506c990125b1f2cbc62e3be22f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Loop end instruction executed.  <a href="#ga345461506c990125b1f2cbc62e3be22f">More...</a><br/></td></tr>
+<tr class="separator:ga345461506c990125b1f2cbc62e3be22f"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:ga268b0bcbd30e8a928bd0f331fdf53ccf"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:gadf9cfd45b59acfc314ebc814a1bcdccd"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:gaa4c408a006a04e95ade26922669b6695"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:gaf01d187b0cbf418d1fac55dd0ddd0827"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:gab21171c50ebd1f304b11260edd015f52"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:gae69e310892661af852ca2d4ec947d18a"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:gac2dc7d92627b3caa391725a3f080288c"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gaf5302b3278a862c9264171955328a59a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaf5302b3278a862c9264171955328a59a">ARM_PMU_MVE_FP_MAC_SPEC</a>&#160;&#160;&#160;0x0215</td></tr>
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+<tr class="separator:gaf5302b3278a862c9264171955328a59a"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:ga5e3afafa91ebaeac0469a19ebb54719c"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:ga16ed0bb1bb4718da93c41238da652d33"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:ga9248c93a3f19fddc93d3804a06f7238a"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:ga7036f00faa9183ae450a3e4d9d6f2bbf"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:ga7d7d465a6c64400c49f93b6c8152296f"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:gaa98a18c06bd13daf2df6f89219ec68d5"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:ga26ed05deaa7b993904300069f0ecfac4"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:ga391afd8cb92cc65161b13ee3a3256d40"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:ga21bf105499df85196b4137cb075a6fbe"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:ga627920bebd935709655687d844848934"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:ga9546b924daa3c62e5f117026de58ad94"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:gac714f988ae45871b2865f82c11383b36"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:ga77fad5ad424271ed63fec98af071bb79"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:gaa07c698f58c622d234a0007249717265"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:ga649e7e81f0fd04ca6611f6a6c4035c57"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="separator:ga5b6f0bcfd63207c7bab03ea20167dd4b"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga01b4792990494b8f084ee00933a1adb0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga01b4792990494b8f084ee00933a1adb0">ARM_PMU_MVE_PRED</a>&#160;&#160;&#160;0x02B8</td></tr>
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+<tr class="separator:ga01b4792990494b8f084ee00933a1adb0"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga2a45ec75b2011bd8375d89b7562b2de6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga2a45ec75b2011bd8375d89b7562b2de6">ARM_PMU_MVE_STALL</a>&#160;&#160;&#160;0x02CC</td></tr>
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+<tr class="separator:ga2a45ec75b2011bd8375d89b7562b2de6"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga8f4949084efce03d09bf5ba74cc91edd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga8f4949084efce03d09bf5ba74cc91edd">ARM_PMU_MVE_STALL_RESOURCE</a>&#160;&#160;&#160;0x02CD</td></tr>
+<tr class="memdesc:ga8f4949084efce03d09bf5ba74cc91edd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Stall cycles caused by an MVE instruction because of resource conflicts.  <a href="#ga8f4949084efce03d09bf5ba74cc91edd">More...</a><br/></td></tr>
+<tr class="separator:ga8f4949084efce03d09bf5ba74cc91edd"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gab486f5753edd9f10b0f100ff78944dd3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gab486f5753edd9f10b0f100ff78944dd3">ARM_PMU_MVE_STALL_RESOURCE_MEM</a>&#160;&#160;&#160;0x02CE</td></tr>
+<tr class="memdesc:gab486f5753edd9f10b0f100ff78944dd3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Stall cycles caused by an MVE instruction because of memory resource conflicts.  <a href="#gab486f5753edd9f10b0f100ff78944dd3">More...</a><br/></td></tr>
+<tr class="separator:gab486f5753edd9f10b0f100ff78944dd3"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga7e76060791618f9b4d49ad493cfb6ba9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga7e76060791618f9b4d49ad493cfb6ba9">ARM_PMU_MVE_STALL_RESOURCE_FP</a>&#160;&#160;&#160;0x02CF</td></tr>
+<tr class="memdesc:ga7e76060791618f9b4d49ad493cfb6ba9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Stall cycles caused by an MVE instruction because of floating-point resource conflicts.  <a href="#ga7e76060791618f9b4d49ad493cfb6ba9">More...</a><br/></td></tr>
+<tr class="separator:ga7e76060791618f9b4d49ad493cfb6ba9"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gaef33b3ff7f12d31238ff4dded5e67a11"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaef33b3ff7f12d31238ff4dded5e67a11">ARM_PMU_MVE_STALL_RESOURCE_INT</a>&#160;&#160;&#160;0x02D0</td></tr>
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+<tr class="separator:gaef33b3ff7f12d31238ff4dded5e67a11"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga9a1cfef96ec7cd70acf134e368d8826a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga9a1cfef96ec7cd70acf134e368d8826a">ARM_PMU_MVE_STALL_BREAK</a>&#160;&#160;&#160;0x02D3</td></tr>
+<tr class="memdesc:ga9a1cfef96ec7cd70acf134e368d8826a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Stall cycles caused by an MVE chain break.  <a href="#ga9a1cfef96ec7cd70acf134e368d8826a">More...</a><br/></td></tr>
+<tr class="separator:ga9a1cfef96ec7cd70acf134e368d8826a"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga29bc4c2e820914e94e2eb68a6a3352b9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga29bc4c2e820914e94e2eb68a6a3352b9">ARM_PMU_MVE_STALL_DEPENDENCY</a>&#160;&#160;&#160;0x02D4</td></tr>
+<tr class="memdesc:ga29bc4c2e820914e94e2eb68a6a3352b9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Stall cycles caused by MVE register dependency.  <a href="#ga29bc4c2e820914e94e2eb68a6a3352b9">More...</a><br/></td></tr>
+<tr class="separator:ga29bc4c2e820914e94e2eb68a6a3352b9"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gaf23d758fe1a4cfe6f114cb3e78709237"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gaf23d758fe1a4cfe6f114cb3e78709237">ARM_PMU_ITCM_ACCESS</a>&#160;&#160;&#160;0x4007</td></tr>
+<tr class="memdesc:gaf23d758fe1a4cfe6f114cb3e78709237"><td class="mdescLeft">&#160;</td><td class="mdescRight">Instruction TCM access.  <a href="#gaf23d758fe1a4cfe6f114cb3e78709237">More...</a><br/></td></tr>
+<tr class="separator:gaf23d758fe1a4cfe6f114cb3e78709237"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga74aaa0fa0571f74168ee9608d5a02403"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga74aaa0fa0571f74168ee9608d5a02403">ARM_PMU_DTCM_ACCESS</a>&#160;&#160;&#160;0x4008</td></tr>
+<tr class="memdesc:ga74aaa0fa0571f74168ee9608d5a02403"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data TCM access.  <a href="#ga74aaa0fa0571f74168ee9608d5a02403">More...</a><br/></td></tr>
+<tr class="separator:ga74aaa0fa0571f74168ee9608d5a02403"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gadaa75dc2ccfbf7a2263da9a9011f1603"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gadaa75dc2ccfbf7a2263da9a9011f1603">ARM_PMU_TRCEXTOUT0</a>&#160;&#160;&#160;0x4010</td></tr>
+<tr class="memdesc:gadaa75dc2ccfbf7a2263da9a9011f1603"><td class="mdescLeft">&#160;</td><td class="mdescRight">ETM external output 0.  <a href="#gadaa75dc2ccfbf7a2263da9a9011f1603">More...</a><br/></td></tr>
+<tr class="separator:gadaa75dc2ccfbf7a2263da9a9011f1603"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga47fe03fe6fe9bfebd98283cb57d94560"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga47fe03fe6fe9bfebd98283cb57d94560">ARM_PMU_TRCEXTOUT1</a>&#160;&#160;&#160;0x4011</td></tr>
+<tr class="memdesc:ga47fe03fe6fe9bfebd98283cb57d94560"><td class="mdescLeft">&#160;</td><td class="mdescRight">ETM external output 1.  <a href="#ga47fe03fe6fe9bfebd98283cb57d94560">More...</a><br/></td></tr>
+<tr class="separator:ga47fe03fe6fe9bfebd98283cb57d94560"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gab80e47ffebc3ae6ed2952756b020dbb9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gab80e47ffebc3ae6ed2952756b020dbb9">ARM_PMU_TRCEXTOUT2</a>&#160;&#160;&#160;0x4012</td></tr>
+<tr class="memdesc:gab80e47ffebc3ae6ed2952756b020dbb9"><td class="mdescLeft">&#160;</td><td class="mdescRight">ETM external output 2.  <a href="#gab80e47ffebc3ae6ed2952756b020dbb9">More...</a><br/></td></tr>
+<tr class="separator:gab80e47ffebc3ae6ed2952756b020dbb9"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gad70a3b074efd967485ffbfd3e387051d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gad70a3b074efd967485ffbfd3e387051d">ARM_PMU_TRCEXTOUT3</a>&#160;&#160;&#160;0x4013</td></tr>
+<tr class="memdesc:gad70a3b074efd967485ffbfd3e387051d"><td class="mdescLeft">&#160;</td><td class="mdescRight">ETM external output 3.  <a href="#gad70a3b074efd967485ffbfd3e387051d">More...</a><br/></td></tr>
+<tr class="separator:gad70a3b074efd967485ffbfd3e387051d"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga290974d72b8cac214f4e9a152ca64a56"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga290974d72b8cac214f4e9a152ca64a56">ARM_PMU_CTI_TRIGOUT4</a>&#160;&#160;&#160;0x4018</td></tr>
+<tr class="memdesc:ga290974d72b8cac214f4e9a152ca64a56"><td class="mdescLeft">&#160;</td><td class="mdescRight">Cross-trigger Interface output trigger 4.  <a href="#ga290974d72b8cac214f4e9a152ca64a56">More...</a><br/></td></tr>
+<tr class="separator:ga290974d72b8cac214f4e9a152ca64a56"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga7a05420b7fae6f5c3d35e12a9846c7e2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga7a05420b7fae6f5c3d35e12a9846c7e2">ARM_PMU_CTI_TRIGOUT5</a>&#160;&#160;&#160;0x4019</td></tr>
+<tr class="memdesc:ga7a05420b7fae6f5c3d35e12a9846c7e2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Cross-trigger Interface output trigger 5.  <a href="#ga7a05420b7fae6f5c3d35e12a9846c7e2">More...</a><br/></td></tr>
+<tr class="separator:ga7a05420b7fae6f5c3d35e12a9846c7e2"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gade076a5ee512a14f8882d9aec5d3dc0b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#gade076a5ee512a14f8882d9aec5d3dc0b">ARM_PMU_CTI_TRIGOUT6</a>&#160;&#160;&#160;0x401A</td></tr>
+<tr class="memdesc:gade076a5ee512a14f8882d9aec5d3dc0b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Cross-trigger Interface output trigger 6.  <a href="#gade076a5ee512a14f8882d9aec5d3dc0b">More...</a><br/></td></tr>
+<tr class="separator:gade076a5ee512a14f8882d9aec5d3dc0b"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga4388c85b636bd71b4ee1a03b6e96c488"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armv81.html#ga4388c85b636bd71b4ee1a03b6e96c488">ARM_PMU_CTI_TRIGOUT7</a>&#160;&#160;&#160;0x401B</td></tr>
+<tr class="memdesc:ga4388c85b636bd71b4ee1a03b6e96c488"><td class="mdescLeft">&#160;</td><td class="mdescRight">Cross-trigger Interface output trigger 7.  <a href="#ga4388c85b636bd71b4ee1a03b6e96c488">More...</a><br/></td></tr>
+<tr class="separator:ga4388c85b636bd71b4ee1a03b6e96c488"><td class="memSeparator" colspan="2">&#160;</td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
+<p>IDs for Armv8.1-M architecture defined events. </p>
+<p>These events are available on all Armv8.1-M devices including a PMU. </p>
+<h2 class="groupheader">Macro Definition Documentation</h2>
+<a class="anchor" id="gaf2e0a38b7c0d63d1194f08478781a3f0"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_BF_CANCEL&#160;&#160;&#160;0x0109</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Branch future instruction not taken. </p>
+
+</div>
+</div>
+<a class="anchor" id="gab8570f46393e3e44bb118591d33723f4"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_BF_RETIRED&#160;&#160;&#160;0x0104</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Branch future instruction architecturally executed and condition code check pass. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga6b1e4823d8b45678a29a5f54b859d4e3"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_BF_SPEC&#160;&#160;&#160;0x0105</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Branch future instruction speculatively executed and condition code check pass. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga22bfb189fff7c1ea9f81097a543ed756"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_BR_IMMED_RETIRED&#160;&#160;&#160;0x000D</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Immediate branch architecturally executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="gabfa921c85a61f0a21c9bee289e63c102"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_BR_MIS_PRED&#160;&#160;&#160;0x0010</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Mispredicted or not predicted branch speculatively executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="gae12baa616c5f0cdd081231fcf8cdad68"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_BR_MIS_PRED_RETIRED&#160;&#160;&#160;0x0022</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Mispredicted branch instruction architecturally executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga60ccf42eae576e2fde3b9e17a8defeaa"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_BR_PRED&#160;&#160;&#160;0x0012</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Predictable branch speculatively executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="gab3b505a8bcc2b2885626d2f2cd542b73"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_BR_RETIRED&#160;&#160;&#160;0x0021</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Branch instruction architecturally executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="gab717347b1c3601cffb9c99b43b2a45c5"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_BR_RETURN_RETIRED&#160;&#160;&#160;0x000E</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Function return instruction architecturally executed and the condition code check pass. </p>
+
+</div>
+</div>
+<a class="anchor" id="gaa681d3db56b42775093869b8fdf1abb9"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_BUS_ACCESS&#160;&#160;&#160;0x0019</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Bus access. </p>
+
+</div>
+</div>
+<a class="anchor" id="gae4c955416707f44f066ffd2560b9ae4c"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_BUS_CYCLES&#160;&#160;&#160;0x001D</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Bus cycles. </p>
+
+</div>
+</div>
+<a class="anchor" id="gaca14907c5a1e1f9915159bc4cf323cf0"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_CHAIN&#160;&#160;&#160;0x001E</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga550d524d435a653b2f46acc1380a5ace"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_CPU_CYCLES&#160;&#160;&#160;0x0011</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Cycle. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga290974d72b8cac214f4e9a152ca64a56"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_CTI_TRIGOUT4&#160;&#160;&#160;0x4018</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Cross-trigger Interface output trigger 4. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga7a05420b7fae6f5c3d35e12a9846c7e2"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_CTI_TRIGOUT5&#160;&#160;&#160;0x4019</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Cross-trigger Interface output trigger 5. </p>
+
+</div>
+</div>
+<a class="anchor" id="gade076a5ee512a14f8882d9aec5d3dc0b"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_CTI_TRIGOUT6&#160;&#160;&#160;0x401A</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Cross-trigger Interface output trigger 6. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga4388c85b636bd71b4ee1a03b6e96c488"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_CTI_TRIGOUT7&#160;&#160;&#160;0x401B</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Cross-trigger Interface output trigger 7. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga74aaa0fa0571f74168ee9608d5a02403"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_DTCM_ACCESS&#160;&#160;&#160;0x4008</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Data TCM access. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga18d640aa04b97c7d287e8745f6f2b23d"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_DWT_CMPMATCH0&#160;&#160;&#160;0x0118</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>DWT comparator 0 match. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga5dc6eb2be1ff1afe9cbd59af4f6078ab"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_DWT_CMPMATCH1&#160;&#160;&#160;0x0119</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>DWT comparator 1 match. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga58a4815dba8886088b9cac7b934a332d"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_DWT_CMPMATCH2&#160;&#160;&#160;0x011A</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>DWT comparator 2 match. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga594337c6f3c88d8317203a8cd6f9814a"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_DWT_CMPMATCH3&#160;&#160;&#160;0x011B</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>DWT comparator 3 match. </p>
+
+</div>
+</div>
+<a class="anchor" id="gaf9424157e9c5dca3a3689d181005c4f8"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_EXC_RETURN&#160;&#160;&#160;0x000A</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Exception return instruction architecturally executed and the condition code check pass. </p>
+
+</div>
+</div>
+<a class="anchor" id="gac97858bd621eab4592569444f0a5c37f"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_EXC_TAKEN&#160;&#160;&#160;0x0009</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Exception entry. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga8a5e60eee460addfc66e275a2c4c4800"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_INST_RETIRED&#160;&#160;&#160;0x0008</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Instruction architecturally executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="gaf7bad54617ace5c2fb48bc2e8aebf9c7"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_INST_SPEC&#160;&#160;&#160;0x001B</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Instruction speculatively executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="gaf23d758fe1a4cfe6f114cb3e78709237"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_ITCM_ACCESS&#160;&#160;&#160;0x4007</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Instruction TCM access. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga7505ae74c1d905f01b05dd5466c1efc0"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_L1D_CACHE&#160;&#160;&#160;0x0004</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>L1 D-Cache access. </p>
+
+</div>
+</div>
+<a class="anchor" id="gab55334c8510cb30c4c750913f6eb6279"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_L1D_CACHE_ALLOCATE&#160;&#160;&#160;0x001F</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Level 1 data cache allocation without refill. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga4687d5d7efc6f49db2db9acc25b590f6"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_L1D_CACHE_MISS_RD&#160;&#160;&#160;0x0039</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Level 1 data cache read miss. </p>
+
+</div>
+</div>
+<a class="anchor" id="gaf4236dfbcb4550d3cc98caee837e8e77"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_L1D_CACHE_RD&#160;&#160;&#160;0x0040</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Level 1 data cache read. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga64a3d7bfb7ec9d7bdeb073a4fe1bbc38"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_L1D_CACHE_REFILL&#160;&#160;&#160;0x0003</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>L1 D-Cache refill. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga27d1b8b2c37ae0ae41781880ed3893d0"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_L1D_CACHE_WB&#160;&#160;&#160;0x0015</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Level 1 data cache write-back. </p>
+
+</div>
+</div>
+<a class="anchor" id="gaf8e89b2b098e6bec5916517346925ce2"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_L1I_CACHE&#160;&#160;&#160;0x0014</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Level 1 instruction cache access. </p>
+
+</div>
+</div>
+<a class="anchor" id="gac43e0e0f9e385ea66402bdeebf3fea3e"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_L1I_CACHE_REFILL&#160;&#160;&#160;0x0001</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>L1 I-Cache refill. </p>
+
+</div>
+</div>
+<a class="anchor" id="gafb1e1f86d091ccb735858769c700e289"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_L2D_CACHE&#160;&#160;&#160;0x0016</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Level 2 data cache access. </p>
+
+</div>
+</div>
+<a class="anchor" id="gaad08dcded491bf257d223e4171af41cc"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_L2D_CACHE_ALLOCATE&#160;&#160;&#160;0x0020</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Level 2 data cache allocation without refill. </p>
+
+</div>
+</div>
+<a class="anchor" id="gaeb414c1b0375022abc2502ab503a3284"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_L2D_CACHE_REFILL&#160;&#160;&#160;0x0017</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Level 2 data cache refill. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga1a0c4a1990eeed88edc3e1e0c4b1aca0"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_L2D_CACHE_WB&#160;&#160;&#160;0x0018</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Level 2 data cache write-back. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga3406498b2c17ca080ebd68cc40d9630e"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_L2I_CACHE&#160;&#160;&#160;0x0027</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Level 2 instruction cache access. </p>
+
+</div>
+</div>
+<a class="anchor" id="gaa18cee03802b46076e9ab66fd0a7c61d"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_L2I_CACHE_REFILL&#160;&#160;&#160;0x0028</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Level 2 instruction cache refill. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga4e96b5a6fb13c657e78da342a02db200"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_L3D_CACHE&#160;&#160;&#160;0x002B</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Level 3 data cache access. </p>
+
+</div>
+</div>
+<a class="anchor" id="gac11cbc6849dbad7bd8b64ab6e2a3f8d5"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_L3D_CACHE_ALLOCATE&#160;&#160;&#160;0x0029</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Level 3 data cache allocation without refill. </p>
+
+</div>
+</div>
+<a class="anchor" id="gafe99db0693125100272247c147fb3b02"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_L3D_CACHE_REFILL&#160;&#160;&#160;0x002A</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Level 3 data cache refill. </p>
+
+</div>
+</div>
+<a class="anchor" id="gab823f95f7ac8196a208d12381b1b2a11"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_L3D_CACHE_WB&#160;&#160;&#160;0x002C</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Level 3 data cache write-back. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga2e8725ee07c2b2c75a1b54261bc26cc8"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_LD_RETIRED&#160;&#160;&#160;0x0006</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Memory-reading instruction architecturally executed and condition code check pass. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga8b5641a3cb0e922a2b4e16ec14052861"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_LE_CANCEL&#160;&#160;&#160;0x0108</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Loop end instruction not taken. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga345461506c990125b1f2cbc62e3be22f"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_LE_RETIRED&#160;&#160;&#160;0x0100</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Loop end instruction executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga6a1d9f84bda091e96843665ff3913b50"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_LE_SPEC&#160;&#160;&#160;0x0101</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Loop end instruction speculatively executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga6979efa69af7d0e62cc3e2f88b0155b8"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_LL_CACHE_MISS_RD&#160;&#160;&#160;0x0037</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Last level data cache read miss. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga902562d8161fffd45726dc4cc8727545"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_LL_CACHE_RD&#160;&#160;&#160;0x0036</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Last level data cache read. </p>
+
+</div>
+</div>
+<a class="anchor" id="gab3852c2b3d59af106b9db7ea2c20c367"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MEM_ACCESS&#160;&#160;&#160;0x0013</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Data memory access. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga2c8d23cc64e87b2044bb39bf8d0bc1b1"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MEMORY_ERROR&#160;&#160;&#160;0x001A</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Local memory error. </p>
+
+</div>
+</div>
+<a class="anchor" id="gaa4c408a006a04e95ade26922669b6695"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_FP_HP_RETIRED&#160;&#160;&#160;0x0208</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE half-precision floating-point instruction architecturally executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="gaf01d187b0cbf418d1fac55dd0ddd0827"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_FP_HP_SPEC&#160;&#160;&#160;0x0209</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE half-precision floating-point instruction speculatively executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="gac2dc7d92627b3caa391725a3f080288c"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_FP_MAC_RETIRED&#160;&#160;&#160;0x0214</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE floating-point multiply or multiply-accumulate instruction architecturally executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="gaf5302b3278a862c9264171955328a59a"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_FP_MAC_SPEC&#160;&#160;&#160;0x0215</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE floating-point multiply or multiply-accumulate instruction speculatively executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga268b0bcbd30e8a928bd0f331fdf53ccf"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_FP_RETIRED&#160;&#160;&#160;0x0204</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE floating-point instruction architecturally executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="gab21171c50ebd1f304b11260edd015f52"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_FP_SP_RETIRED&#160;&#160;&#160;0x020C</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE single-precision floating-point instruction architecturally executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="gae69e310892661af852ca2d4ec947d18a"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_FP_SP_SPEC&#160;&#160;&#160;0x020D</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE single-precision floating-point instruction speculatively executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="gadf9cfd45b59acfc314ebc814a1bcdccd"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_FP_SPEC&#160;&#160;&#160;0x0205</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE floating-point instruction speculatively executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga3c1006bed2fb82b0749386261b397727"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_INST_RETIRED&#160;&#160;&#160;0x0200</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE instruction architecturally executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga1e276b6872345eb3b043626a11f235c6"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_INST_SPEC&#160;&#160;&#160;0x0201</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE instruction speculatively executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga9248c93a3f19fddc93d3804a06f7238a"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_INT_MAC_RETIRED&#160;&#160;&#160;0x0228</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE multiply or multiply-accumulate instruction architecturally executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga7036f00faa9183ae450a3e4d9d6f2bbf"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_INT_MAC_SPEC&#160;&#160;&#160;0x0229</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE multiply or multiply-accumulate instruction speculatively executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga5e3afafa91ebaeac0469a19ebb54719c"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_INT_RETIRED&#160;&#160;&#160;0x0224</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE integer instruction architecturally executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga16ed0bb1bb4718da93c41238da652d33"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_INT_SPEC&#160;&#160;&#160;0x0225</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE integer instruction speculatively executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga8732a737f2b7adc43e3d1da7b3da92e6"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_LD_CONTIG_RETIRED&#160;&#160;&#160;0x0248</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE contiguous load instruction architecturally executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga8e58fe07254256fa3bf3d42fa2062141"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_LD_CONTIG_SPEC&#160;&#160;&#160;0x0249</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE contiguous load instruction speculatively executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga50fb13c874b3f5e2b9ed9c320a36452c"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_LD_MULTI_RETIRED&#160;&#160;&#160;0x0260</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE memory load instruction targeting multiple registers architecturally executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="gaf2d4e3d1f06d97899de7fa791477d62b"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_LD_MULTI_SPEC&#160;&#160;&#160;0x0261</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE memory load instruction targeting multiple registers speculatively executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="gaaf2ce8c0ea4c03c934aac6afc31fc5ff"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED&#160;&#160;&#160;0x0254</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE non-contiguous load instruction architecturally executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="gadbcb82b7924b7bbee5c0d42a3de38572"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_LD_NONCONTIG_SPEC&#160;&#160;&#160;0x0255</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE non-contiguous load instruction speculatively executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="gaa3379a51350a2fda8d8ab6d7795baa7a"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_LD_RETIRED&#160;&#160;&#160;0x023C</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE load instruction architecturally executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga78a6f89ab30ed01f7d8388eda697b4f8"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_LD_SPEC&#160;&#160;&#160;0x023D</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE load instruction speculatively executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga26ed05deaa7b993904300069f0ecfac4"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED&#160;&#160;&#160;0x0290</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE unaligned load instruction architecturally executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="gadc3bd0f32e0a08bba2d533479a59bd6e"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_LD_UNALIGNED_SPEC&#160;&#160;&#160;0x0291</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE unaligned load instruction speculatively executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga8acf6a66c63798b76608caf52c96658d"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_LDST_CONTIG_RETIRED&#160;&#160;&#160;0x0244</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE contiguous load or store instruction architecturally executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga5a83ef6a52739e1d223be503bbdaaab6"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_LDST_CONTIG_SPEC&#160;&#160;&#160;0x0245</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE contiguous load or store instruction speculatively executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga7d669378441408fc21aa551e483866cb"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_LDST_MULTI_RETIRED&#160;&#160;&#160;0x025C</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE memory instruction targeting multiple registers architecturally executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga7ea46cde08cb0cc4a46ef23835fb5aac"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_LDST_MULTI_SPEC&#160;&#160;&#160;0x025D</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE memory instruction targeting multiple registers speculatively executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga7065b7f0aea461858b72912d22c329f2"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED&#160;&#160;&#160;0x0250</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE non-contiguous load or store instruction architecturally executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga193605eb52709741d91a64e3ad1a5894"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC&#160;&#160;&#160;0x0251</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE non-contiguous load or store instruction speculatively executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga7d7d465a6c64400c49f93b6c8152296f"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_LDST_RETIRED&#160;&#160;&#160;0x0238</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE load or store instruction architecturally executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="gaa98a18c06bd13daf2df6f89219ec68d5"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_LDST_SPEC&#160;&#160;&#160;0x0239</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE load or store instruction speculatively executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga627920bebd935709655687d844848934"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED&#160;&#160;&#160;0x0298</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE unaligned noncontiguous load or store instruction architecturally executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="gaf9ebeb1f49dba56d8f90f9bd5d3da58e"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC&#160;&#160;&#160;0x0299</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE unaligned noncontiguous load or store instruction speculatively executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="gaf358a9ed5c83a10cb695d9b19b1b3bc1"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED&#160;&#160;&#160;0x028C</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE unaligned memory load or store instruction architecturally executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="gab2264786bed578c89109859b55909c76"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC&#160;&#160;&#160;0x028D</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE unaligned memory load or store instruction speculatively executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga01b4792990494b8f084ee00933a1adb0"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_PRED&#160;&#160;&#160;0x02B8</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Cycles where one or more predicated beats architecturally executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="gacb3c0b922eae9aac321df97ec889e0ed"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_ST_CONTIG_RETIRED&#160;&#160;&#160;0x024C</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE contiguous store instruction architecturally executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga02cd64b9444e4babc7b69e8571d39bdd"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_ST_CONTIG_SPEC&#160;&#160;&#160;0x024D</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE contiguous store instruction speculatively executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga76057cbda353b4ad6fbc3b6a63c193a5"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_ST_MULTI_RETIRED&#160;&#160;&#160;0x0261</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE memory store instruction targeting multiple registers architecturally executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="gaf6a14402c79dba8fa765e8663dd0734d"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_ST_MULTI_SPEC&#160;&#160;&#160;0x0265</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE memory store instruction targeting multiple registers speculatively executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga8271f415ecc7573b57e82a24aec86ef1"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED&#160;&#160;&#160;0x0258</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE non-contiguous store instruction architecturally executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga059327c80f396918a9f8192bcd0fa4a8"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_ST_NONCONTIG_SPEC&#160;&#160;&#160;0x0259</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE non-contiguous store instruction speculatively executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="gad8d0079977fa97de4ee263703f1b2908"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_ST_RETIRED&#160;&#160;&#160;0x0240</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE store instruction architecturally executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="gabd3984d299b5416aac8d630722680c55"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_ST_SPEC&#160;&#160;&#160;0x0241</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE store instruction speculatively executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga391afd8cb92cc65161b13ee3a3256d40"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED&#160;&#160;&#160;0x0294</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE unaligned store instruction architecturally executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga21bf105499df85196b4137cb075a6fbe"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_ST_UNALIGNED_SPEC&#160;&#160;&#160;0x0295</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE unaligned store instruction speculatively executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga2a45ec75b2011bd8375d89b7562b2de6"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_STALL&#160;&#160;&#160;0x02CC</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Stall cycles caused by an MVE instruction. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga9a1cfef96ec7cd70acf134e368d8826a"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_STALL_BREAK&#160;&#160;&#160;0x02D3</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Stall cycles caused by an MVE chain break. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga29bc4c2e820914e94e2eb68a6a3352b9"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_STALL_DEPENDENCY&#160;&#160;&#160;0x02D4</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Stall cycles caused by MVE register dependency. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga8f4949084efce03d09bf5ba74cc91edd"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_STALL_RESOURCE&#160;&#160;&#160;0x02CD</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Stall cycles caused by an MVE instruction because of resource conflicts. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga7e76060791618f9b4d49ad493cfb6ba9"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_STALL_RESOURCE_FP&#160;&#160;&#160;0x02CF</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Stall cycles caused by an MVE instruction because of floating-point resource conflicts. </p>
+
+</div>
+</div>
+<a class="anchor" id="gaef33b3ff7f12d31238ff4dded5e67a11"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_STALL_RESOURCE_INT&#160;&#160;&#160;0x02D0</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Stall cycles caused by an MVE instruction because of integer resource conflicts. </p>
+
+</div>
+</div>
+<a class="anchor" id="gab486f5753edd9f10b0f100ff78944dd3"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_STALL_RESOURCE_MEM&#160;&#160;&#160;0x02CE</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Stall cycles caused by an MVE instruction because of memory resource conflicts. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga77fad5ad424271ed63fec98af071bb79"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_VREDUCE_FP_RETIRED&#160;&#160;&#160;0x02A4</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE floating-point vector reduction instruction architecturally executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="gaa07c698f58c622d234a0007249717265"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_VREDUCE_FP_SPEC&#160;&#160;&#160;0x02A5</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE floating-point vector reduction instruction speculatively executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga649e7e81f0fd04ca6611f6a6c4035c57"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_VREDUCE_INT_RETIRED&#160;&#160;&#160;0x02A8</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE integer vector reduction instruction architecturally executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga5b6f0bcfd63207c7bab03ea20167dd4b"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_VREDUCE_INT_SPEC&#160;&#160;&#160;0x02A9</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE integer vector reduction instruction speculatively executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga9546b924daa3c62e5f117026de58ad94"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_VREDUCE_RETIRED&#160;&#160;&#160;0x02A0</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE vector reduction instruction architecturally executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="gac714f988ae45871b2865f82c11383b36"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_MVE_VREDUCE_SPEC&#160;&#160;&#160;0x02A1</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>MVE vector reduction instruction speculatively executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga2fe9d3ea67ce833bd6323e4ce1a4e894"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_OP_COMPLETE&#160;&#160;&#160;0x003A</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Operation retired. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga6c59149e9b1754987b44b62092bc9f09"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_OP_SPEC&#160;&#160;&#160;0x003B</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Operation speculatively executed. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga54fd2c392399221077c67866a395e587"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_PC_WRITE_RETIRED&#160;&#160;&#160;0x000C</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass. </p>
+
+</div>
+</div>
+<a class="anchor" id="gaaae2c32a8ecd36b59ac98cf8e23b3cab"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_SE_CALL_NS&#160;&#160;&#160;0x0115</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Call to non-secure function, resulting in Security state change. </p>
+
+</div>
+</div>
+<a class="anchor" id="gad3ba2effbe303ca3fafdbc022fe206c1"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_SE_CALL_S&#160;&#160;&#160;0x0114</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Call to secure function, resulting in Security state change. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga8179d1144f8ec993bd1343e276d7b49b"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_ST_RETIRED&#160;&#160;&#160;0x0007</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Memory-writing instruction architecturally executed and condition code check pass. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga8bf75efa06a125ee2dfa9a130e7ba9a8"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_STALL&#160;&#160;&#160;0x003C</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Stall cycle for instruction or operation not sent for execution. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga8737bee352820bd7d1bc8e5e4260143c"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_STALL_BACKEND&#160;&#160;&#160;0x0024</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>No operation issued because of the backend. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga5b068593baa831348664dfa7d44f5483"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_STALL_FRONTEND&#160;&#160;&#160;0x0023</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>No operation issued because of the frontend. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga197b491f691110fb52aef4291782b6ab"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_STALL_OP&#160;&#160;&#160;0x003F</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Instruction or operation slots not occupied each cycle. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga9700ec74727a9fe3cd4cd40736628a23"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_STALL_OP_BACKEND&#160;&#160;&#160;0x003D</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Stall cycle for instruction or operation not sent for execution due to pipeline backend. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga69cfd3558cf6c6f3bb621ee75430427c"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_STALL_OP_FRONTEND&#160;&#160;&#160;0x003E</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Stall cycle for instruction or operation not sent for execution due to pipeline frontend. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga6e02b08550d7e9b273ff7913f1b57bea"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_SW_INCR&#160;&#160;&#160;0x0000</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Software update to the PMU_SWINC register, architecturally executed and condition code check pass. </p>
+
+</div>
+</div>
+<a class="anchor" id="gadaa75dc2ccfbf7a2263da9a9011f1603"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_TRCEXTOUT0&#160;&#160;&#160;0x4010</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>ETM external output 0. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga47fe03fe6fe9bfebd98283cb57d94560"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_TRCEXTOUT1&#160;&#160;&#160;0x4011</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>ETM external output 1. </p>
+
+</div>
+</div>
+<a class="anchor" id="gab80e47ffebc3ae6ed2952756b020dbb9"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_TRCEXTOUT2&#160;&#160;&#160;0x4012</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>ETM external output 2. </p>
+
+</div>
+</div>
+<a class="anchor" id="gad70a3b074efd967485ffbfd3e387051d"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_TRCEXTOUT3&#160;&#160;&#160;0x4013</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>ETM external output 3. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga45d5ea86fdc015f4fc100462150c92da"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define ARM_PMU_UNALIGNED_LDST_RETIRED&#160;&#160;&#160;0x000F</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass. </p>
+
+</div>
+</div>
+</div><!-- contents -->
+</div><!-- doc-content -->
+<!-- start footer part -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
+	<!--
+    <a href="http://www.doxygen.org/index.html">
+    <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 
+	-->
+	</li>
+  </ul>
+</div>
+</body>
+</html>

docs/Core/html/group__pmu8__events__armv81.js

@@ -0,0 +1,134 @@
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+    [ "ARM_PMU_BR_IMMED_RETIRED", "group__pmu8__events__armv81.html#ga22bfb189fff7c1ea9f81097a543ed756", null ],
+    [ "ARM_PMU_BR_MIS_PRED", "group__pmu8__events__armv81.html#gabfa921c85a61f0a21c9bee289e63c102", null ],
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+    [ "ARM_PMU_BR_RETURN_RETIRED", "group__pmu8__events__armv81.html#gab717347b1c3601cffb9c99b43b2a45c5", null ],
+    [ "ARM_PMU_BUS_ACCESS", "group__pmu8__events__armv81.html#gaa681d3db56b42775093869b8fdf1abb9", null ],
+    [ "ARM_PMU_BUS_CYCLES", "group__pmu8__events__armv81.html#gae4c955416707f44f066ffd2560b9ae4c", null ],
+    [ "ARM_PMU_CHAIN", "group__pmu8__events__armv81.html#gaca14907c5a1e1f9915159bc4cf323cf0", null ],
+    [ "ARM_PMU_CPU_CYCLES", "group__pmu8__events__armv81.html#ga550d524d435a653b2f46acc1380a5ace", null ],
+    [ "ARM_PMU_CTI_TRIGOUT4", "group__pmu8__events__armv81.html#ga290974d72b8cac214f4e9a152ca64a56", null ],
+    [ "ARM_PMU_CTI_TRIGOUT5", "group__pmu8__events__armv81.html#ga7a05420b7fae6f5c3d35e12a9846c7e2", null ],
+    [ "ARM_PMU_CTI_TRIGOUT6", "group__pmu8__events__armv81.html#gade076a5ee512a14f8882d9aec5d3dc0b", null ],
+    [ "ARM_PMU_CTI_TRIGOUT7", "group__pmu8__events__armv81.html#ga4388c85b636bd71b4ee1a03b6e96c488", null ],
+    [ "ARM_PMU_DTCM_ACCESS", "group__pmu8__events__armv81.html#ga74aaa0fa0571f74168ee9608d5a02403", null ],
+    [ "ARM_PMU_DWT_CMPMATCH0", "group__pmu8__events__armv81.html#ga18d640aa04b97c7d287e8745f6f2b23d", null ],
+    [ "ARM_PMU_DWT_CMPMATCH1", "group__pmu8__events__armv81.html#ga5dc6eb2be1ff1afe9cbd59af4f6078ab", null ],
+    [ "ARM_PMU_DWT_CMPMATCH2", "group__pmu8__events__armv81.html#ga58a4815dba8886088b9cac7b934a332d", null ],
+    [ "ARM_PMU_DWT_CMPMATCH3", "group__pmu8__events__armv81.html#ga594337c6f3c88d8317203a8cd6f9814a", null ],
+    [ "ARM_PMU_EXC_RETURN", "group__pmu8__events__armv81.html#gaf9424157e9c5dca3a3689d181005c4f8", null ],
+    [ "ARM_PMU_EXC_TAKEN", "group__pmu8__events__armv81.html#gac97858bd621eab4592569444f0a5c37f", null ],
+    [ "ARM_PMU_INST_RETIRED", "group__pmu8__events__armv81.html#ga8a5e60eee460addfc66e275a2c4c4800", null ],
+    [ "ARM_PMU_INST_SPEC", "group__pmu8__events__armv81.html#gaf7bad54617ace5c2fb48bc2e8aebf9c7", null ],
+    [ "ARM_PMU_ITCM_ACCESS", "group__pmu8__events__armv81.html#gaf23d758fe1a4cfe6f114cb3e78709237", null ],
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+    [ "ARM_PMU_L1D_CACHE_ALLOCATE", "group__pmu8__events__armv81.html#gab55334c8510cb30c4c750913f6eb6279", null ],
+    [ "ARM_PMU_L1D_CACHE_MISS_RD", "group__pmu8__events__armv81.html#ga4687d5d7efc6f49db2db9acc25b590f6", null ],
+    [ "ARM_PMU_L1D_CACHE_RD", "group__pmu8__events__armv81.html#gaf4236dfbcb4550d3cc98caee837e8e77", null ],
+    [ "ARM_PMU_L1D_CACHE_REFILL", "group__pmu8__events__armv81.html#ga64a3d7bfb7ec9d7bdeb073a4fe1bbc38", null ],
+    [ "ARM_PMU_L1D_CACHE_WB", "group__pmu8__events__armv81.html#ga27d1b8b2c37ae0ae41781880ed3893d0", null ],
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docs/Core/html/group__pmu8__functions.html

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+<title>CMSIS-Core (Cortex-M): PMU Functions for Armv8.1-M</title>
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+   <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
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+<div class="title">PMU Functions for Armv8.1-M</div>  </div>
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+<p>Functions that relate to the Performance Monitoring Unit.  
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+<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:group__pmu8__events__armcm55"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__events__armcm55.html">PMU Events for Cortex-M55</a></td></tr>
+<tr class="memdesc:group__pmu8__events__armcm55"><td class="mdescLeft">&#160;</td><td class="mdescRight">IDs for additional events defined for Cortex-M55. <br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="nested-classes"></a>
+Data Structures</h2></td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structPMU__Type.html">PMU_Type</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Structure type to access the Performance Monitoring Unit (PMU).  <a href="structPMU__Type.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
+Macros</h2></td></tr>
+<tr class="memitem:gad19c25be8565f2791aca1a96d1847516"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__functions.html#gad19c25be8565f2791aca1a96d1847516">PMU</a></td></tr>
+<tr class="memdesc:gad19c25be8565f2791aca1a96d1847516"><td class="mdescLeft">&#160;</td><td class="mdescRight">PMU configuration struct.  <a href="#gad19c25be8565f2791aca1a96d1847516">More...</a><br/></td></tr>
+<tr class="separator:gad19c25be8565f2791aca1a96d1847516"><td class="memSeparator" colspan="2">&#160;</td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
+Functions</h2></td></tr>
+<tr class="memitem:ga618e7140a774ac2a31a59db4b7d13abc"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__functions.html#ga618e7140a774ac2a31a59db4b7d13abc">ARM_PMU_Enable</a> (void)</td></tr>
+<tr class="memdesc:ga618e7140a774ac2a31a59db4b7d13abc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable the PMU.  <a href="#ga618e7140a774ac2a31a59db4b7d13abc">More...</a><br/></td></tr>
+<tr class="separator:ga618e7140a774ac2a31a59db4b7d13abc"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga74273d4a47cf1a5e99d857a3e8896f10"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__functions.html#ga74273d4a47cf1a5e99d857a3e8896f10">ARM_PMU_Disable</a> (void)</td></tr>
+<tr class="memdesc:ga74273d4a47cf1a5e99d857a3e8896f10"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable the PMU.  <a href="#ga74273d4a47cf1a5e99d857a3e8896f10">More...</a><br/></td></tr>
+<tr class="separator:ga74273d4a47cf1a5e99d857a3e8896f10"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga77ee08f0b3e77d4559cb79fde30d89e9"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__functions.html#ga77ee08f0b3e77d4559cb79fde30d89e9">ARM_PMU_Set_EVTYPER</a> (uint32_t num, uint32_t type)</td></tr>
+<tr class="memdesc:ga77ee08f0b3e77d4559cb79fde30d89e9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set event to count for PMU event counter.  <a href="#ga77ee08f0b3e77d4559cb79fde30d89e9">More...</a><br/></td></tr>
+<tr class="separator:ga77ee08f0b3e77d4559cb79fde30d89e9"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga4288c08039886cd24eb2dd4e743fb97e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__functions.html#ga4288c08039886cd24eb2dd4e743fb97e">ARM_PMU_CYCCNT_Reset</a> (void)</td></tr>
+<tr class="memdesc:ga4288c08039886cd24eb2dd4e743fb97e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reset cycle counter.  <a href="#ga4288c08039886cd24eb2dd4e743fb97e">More...</a><br/></td></tr>
+<tr class="separator:ga4288c08039886cd24eb2dd4e743fb97e"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga90527859e6f0ef980300c86c2916ee79"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__functions.html#ga90527859e6f0ef980300c86c2916ee79">ARM_PMU_EVCNTR_ALL_Reset</a> (void)</td></tr>
+<tr class="memdesc:ga90527859e6f0ef980300c86c2916ee79"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reset all event counters.  <a href="#ga90527859e6f0ef980300c86c2916ee79">More...</a><br/></td></tr>
+<tr class="separator:ga90527859e6f0ef980300c86c2916ee79"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga22e481855ab257180e24f01a38623887"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__functions.html#ga22e481855ab257180e24f01a38623887">ARM_PMU_CNTR_Enable</a> (uint32_t mask)</td></tr>
+<tr class="memdesc:ga22e481855ab257180e24f01a38623887"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable counters.  <a href="#ga22e481855ab257180e24f01a38623887">More...</a><br/></td></tr>
+<tr class="separator:ga22e481855ab257180e24f01a38623887"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga76c6f266544c53d93801cfb614155420"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__functions.html#ga76c6f266544c53d93801cfb614155420">ARM_PMU_CNTR_Disable</a> (uint32_t mask)</td></tr>
+<tr class="memdesc:ga76c6f266544c53d93801cfb614155420"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable counters.  <a href="#ga76c6f266544c53d93801cfb614155420">More...</a><br/></td></tr>
+<tr class="separator:ga76c6f266544c53d93801cfb614155420"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gaaa18c27d39f5a55c1b621f5296b88112"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__functions.html#gaaa18c27d39f5a55c1b621f5296b88112">ARM_PMU_Get_CCNTR</a> (void)</td></tr>
+<tr class="memdesc:gaaa18c27d39f5a55c1b621f5296b88112"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read cycle counter.  <a href="#gaaa18c27d39f5a55c1b621f5296b88112">More...</a><br/></td></tr>
+<tr class="separator:gaaa18c27d39f5a55c1b621f5296b88112"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga9768cbaffcf2c0b31febe96db91a85d8"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__functions.html#ga9768cbaffcf2c0b31febe96db91a85d8">ARM_PMU_Get_EVCNTR</a> (uint32_t num)</td></tr>
+<tr class="memdesc:ga9768cbaffcf2c0b31febe96db91a85d8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read event counter.  <a href="#ga9768cbaffcf2c0b31febe96db91a85d8">More...</a><br/></td></tr>
+<tr class="separator:ga9768cbaffcf2c0b31febe96db91a85d8"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga70436b378b75bdfe3fcb47697d309a96"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__functions.html#ga70436b378b75bdfe3fcb47697d309a96">ARM_PMU_Get_CNTR_OVS</a> (void)</td></tr>
+<tr class="memdesc:ga70436b378b75bdfe3fcb47697d309a96"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read counter overflow status.  <a href="#ga70436b378b75bdfe3fcb47697d309a96">More...</a><br/></td></tr>
+<tr class="separator:ga70436b378b75bdfe3fcb47697d309a96"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga18376f0e3829e93e99149847667e5864"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__functions.html#ga18376f0e3829e93e99149847667e5864">ARM_PMU_Set_CNTR_OVS</a> (uint32_t mask)</td></tr>
+<tr class="memdesc:ga18376f0e3829e93e99149847667e5864"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clear counter overflow status.  <a href="#ga18376f0e3829e93e99149847667e5864">More...</a><br/></td></tr>
+<tr class="separator:ga18376f0e3829e93e99149847667e5864"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga133168437a20566d319c78b751425c44"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__functions.html#ga133168437a20566d319c78b751425c44">ARM_PMU_Set_CNTR_IRQ_Enable</a> (uint32_t mask)</td></tr>
+<tr class="memdesc:ga133168437a20566d319c78b751425c44"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable counter overflow interrupt request.  <a href="#ga133168437a20566d319c78b751425c44">More...</a><br/></td></tr>
+<tr class="separator:ga133168437a20566d319c78b751425c44"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga731b6cd01c6eaa6f909164602f19d0bc"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__functions.html#ga731b6cd01c6eaa6f909164602f19d0bc">ARM_PMU_Set_CNTR_IRQ_Disable</a> (uint32_t mask)</td></tr>
+<tr class="memdesc:ga731b6cd01c6eaa6f909164602f19d0bc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable counter overflow interrupt request.  <a href="#ga731b6cd01c6eaa6f909164602f19d0bc">More...</a><br/></td></tr>
+<tr class="separator:ga731b6cd01c6eaa6f909164602f19d0bc"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga27b07d38050a16ce416bfaf151a24944"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__pmu8__functions.html#ga27b07d38050a16ce416bfaf151a24944">ARM_PMU_CNTR_Increment</a> (uint32_t mask)</td></tr>
+<tr class="memdesc:ga27b07d38050a16ce416bfaf151a24944"><td class="mdescLeft">&#160;</td><td class="mdescRight">Software increment event counter.  <a href="#ga27b07d38050a16ce416bfaf151a24944">More...</a><br/></td></tr>
+<tr class="separator:ga27b07d38050a16ce416bfaf151a24944"><td class="memSeparator" colspan="2">&#160;</td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
+<p>Functions that relate to the Performance Monitoring Unit. </p>
+<p>The following functions support the Performance Monitoring Unit (PMU) that is available on the Cortex-M55 processor.</p>
+<p>The PMU is used to monitor events that occur during run-time of an application.</p>
+<p><b>Example:</b> </p>
+<div class="fragment"><div class="line"><span class="comment">// Initialize counter variables</span></div>
+<div class="line"> </div>
+<div class="line"><span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> cycle_count = 0;</div>
+<div class="line"><span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> l1_dcache_miss_count = 0;</div>
+<div class="line"><span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> instructions_retired_count = 0;</div>
+<div class="line"> </div>
+<div class="line"><span class="comment">// Enable the PMU</span></div>
+<div class="line"> </div>
+<div class="line"><a class="code" href="group__pmu8__functions.html#ga618e7140a774ac2a31a59db4b7d13abc">ARM_PMU_Enable</a>();</div>
+<div class="line"> </div>
+<div class="line"><span class="comment">// Configure Event Counter Register 0 to count instructions retired</span></div>
+<div class="line"><span class="comment">// Configure Event Counter Register 1 to count L1 D-Cache misses</span></div>
+<div class="line"> </div>
+<div class="line"><a class="code" href="group__pmu8__functions.html#ga77ee08f0b3e77d4559cb79fde30d89e9">ARM_PMU_Set_EVTYPER</a>(0, <a class="code" href="group__pmu8__events__armv81.html#ga8a5e60eee460addfc66e275a2c4c4800">ARM_PMU_INST_RETIRED</a>);</div>
+<div class="line"><a class="code" href="group__pmu8__functions.html#ga77ee08f0b3e77d4559cb79fde30d89e9">ARM_PMU_Set_EVTYPER</a>(1, <a class="code" href="group__pmu8__events__armv81.html#ga4687d5d7efc6f49db2db9acc25b590f6">ARM_PMU_L1D_CACHE_MISS_RD</a>);</div>
+<div class="line"> </div>
+<div class="line"><span class="comment">// Reset Event Counters and Cycle Counter</span></div>
+<div class="line"> </div>
+<div class="line"><a class="code" href="group__pmu8__functions.html#ga90527859e6f0ef980300c86c2916ee79">ARM_PMU_EVCNTR_ALL_Reset</a>();</div>
+<div class="line"><a class="code" href="group__pmu8__functions.html#ga4288c08039886cd24eb2dd4e743fb97e">ARM_PMU_CYCCNT_Reset</a>();</div>
+<div class="line"> </div>
+<div class="line"><span class="comment">// Start incrementing Cycle Count Register and Event Counter Registers 0 &amp; 1</span></div>
+<div class="line"> </div>
+<div class="line"><a class="code" href="group__pmu8__functions.html#ga22e481855ab257180e24f01a38623887">ARM_PMU_CNTR_Enable</a>(PMU_CNTENSET_CCNTR_ENABLE_Msk|PMU_CNTENSET_CNT0_ENABLE_Msk|PMU_CNTENSET_CNT1_ENABLE_Msk);</div>
+<div class="line"> </div>
+<div class="line"><span class="comment">// Code you want to measure here</span></div>
+<div class="line"> </div>
+<div class="line"><span class="comment">// Stop incrementing Cycle Count Register and Event Counter Registers 0 &amp; 1</span></div>
+<div class="line"> </div>
+<div class="line"><a class="code" href="group__pmu8__functions.html#ga76c6f266544c53d93801cfb614155420">ARM_PMU_CNTR_Disable</a>(PMU_CNTENCLR_CCNTR_ENABLE_Msk|PMU_CNTENCLR_CNT0_ENABLE_Msk|PMU_CNTENCLR_CNT1_ENABLE_Msk);</div>
+<div class="line"> </div>
+<div class="line"><span class="comment">// Get cycle count, number of instructions retired and number of L1 D-Cache misses (on read)</span></div>
+<div class="line"> </div>
+<div class="line">cycle_count = cycle_count + <a class="code" href="group__pmu8__functions.html#gaaa18c27d39f5a55c1b621f5296b88112">ARM_PMU_Get_CCNTR</a>();</div>
+<div class="line">instructions_retired_count = instructions_retired_count + <a class="code" href="group__pmu8__functions.html#ga9768cbaffcf2c0b31febe96db91a85d8">ARM_PMU_Get_EVCNTR</a>(0);</div>
+<div class="line">l1_dcache_miss_count = l1_dcache_miss_count + <a class="code" href="group__pmu8__functions.html#ga9768cbaffcf2c0b31febe96db91a85d8">ARM_PMU_Get_EVCNTR</a>(1);      <span class="comment">// Note: D-Cache must be enabled using</span></div>
+<div class="line">                                                                          <span class="comment">// SCB_EnableDCache() for meaningful result.</span></div>
+</div><!-- fragment --> <h2 class="groupheader">Macro Definition Documentation</h2>
+<a class="anchor" id="gad19c25be8565f2791aca1a96d1847516"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">#define PMU</td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>PMU configuration struct. </p>
+<p>This macro can be used to access the PMU registers, directly. For the common tasks one should prefer using the control functions.</p>
+<p>Example: <b>Example:</b> </p>
+<div class="fragment"><div class="line"><a class="code" href="group__pmu8__functions.html#gad19c25be8565f2791aca1a96d1847516">PMU</a>-&gt;CTRL |= PMU_CTRL_ENABLE_Msk; <span class="comment">// Enable PMU</span></div>
+</div><!-- fragment --> 
+</div>
+</div>
+<h2 class="groupheader">Function Documentation</h2>
+<a class="anchor" id="ga76c6f266544c53d93801cfb614155420"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_PMU_CNTR_Disable </td>
+          <td>(</td>
+          <td class="paramtype">uint32_t&#160;</td>
+          <td class="paramname"><em>mask</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Disable counters. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">mask</td><td>Counters to enable </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section note"><dt>Note</dt><dd>Disables one or more of the following:<ul>
+<li>event counters (0-30)</li>
+<li>cycle counter </li>
+</ul>
+</dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga22e481855ab257180e24f01a38623887"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_PMU_CNTR_Enable </td>
+          <td>(</td>
+          <td class="paramtype">uint32_t&#160;</td>
+          <td class="paramname"><em>mask</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Enable counters. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">mask</td><td>Counters to enable </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section note"><dt>Note</dt><dd>Enables one or more of the following:<ul>
+<li>event counters (0-30)</li>
+<li>cycle counter </li>
+</ul>
+</dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga27b07d38050a16ce416bfaf151a24944"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_PMU_CNTR_Increment </td>
+          <td>(</td>
+          <td class="paramtype">uint32_t&#160;</td>
+          <td class="paramname"><em>mask</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Software increment event counter. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">mask</td><td>Counters to increment </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section note"><dt>Note</dt><dd>Software increment bits for one or more event counters (0-30) </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga4288c08039886cd24eb2dd4e743fb97e"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_PMU_CYCCNT_Reset </td>
+          <td>(</td>
+          <td class="paramtype">void&#160;</td>
+          <td class="paramname"></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Reset cycle counter. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga74273d4a47cf1a5e99d857a3e8896f10"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_PMU_Disable </td>
+          <td>(</td>
+          <td class="paramtype">void&#160;</td>
+          <td class="paramname"></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Disable the PMU. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga618e7140a774ac2a31a59db4b7d13abc"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_PMU_Enable </td>
+          <td>(</td>
+          <td class="paramtype">void&#160;</td>
+          <td class="paramname"></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Enable the PMU. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga90527859e6f0ef980300c86c2916ee79"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_PMU_EVCNTR_ALL_Reset </td>
+          <td>(</td>
+          <td class="paramtype">void&#160;</td>
+          <td class="paramname"></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Reset all event counters. </p>
+
+</div>
+</div>
+<a class="anchor" id="gaaa18c27d39f5a55c1b621f5296b88112"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t ARM_PMU_Get_CCNTR </td>
+          <td>(</td>
+          <td class="paramtype">void&#160;</td>
+          <td class="paramname"></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Read cycle counter. </p>
+<dl class="section return"><dt>Returns</dt><dd>Cycle count </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga70436b378b75bdfe3fcb47697d309a96"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t ARM_PMU_Get_CNTR_OVS </td>
+          <td>(</td>
+          <td class="paramtype">void&#160;</td>
+          <td class="paramname"></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Read counter overflow status. </p>
+<dl class="section return"><dt>Returns</dt><dd>Counter overflow status bits for the following:<ul>
+<li>event counters (0-30)</li>
+<li>cycle counter </li>
+</ul>
+</dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga9768cbaffcf2c0b31febe96db91a85d8"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t ARM_PMU_Get_EVCNTR </td>
+          <td>(</td>
+          <td class="paramtype">uint32_t&#160;</td>
+          <td class="paramname"><em>num</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Read event counter. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">num</td><td>Event counter (0-30) to read </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>Event count </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga731b6cd01c6eaa6f909164602f19d0bc"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_PMU_Set_CNTR_IRQ_Disable </td>
+          <td>(</td>
+          <td class="paramtype">uint32_t&#160;</td>
+          <td class="paramname"><em>mask</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Disable counter overflow interrupt request. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">mask</td><td>Counter overflow interrupt request bits to clear </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section note"><dt>Note</dt><dd>Clears overflow interrupt request bits for one or more of the following:<ul>
+<li>event counters (0-30)</li>
+<li>cycle counter </li>
+</ul>
+</dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga133168437a20566d319c78b751425c44"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_PMU_Set_CNTR_IRQ_Enable </td>
+          <td>(</td>
+          <td class="paramtype">uint32_t&#160;</td>
+          <td class="paramname"><em>mask</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Enable counter overflow interrupt request. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">mask</td><td>Counter overflow interrupt request bits to set </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section note"><dt>Note</dt><dd>Sets overflow interrupt request bits for one or more of the following:<ul>
+<li>event counters (0-30)</li>
+<li>cycle counter </li>
+</ul>
+</dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga18376f0e3829e93e99149847667e5864"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_PMU_Set_CNTR_OVS </td>
+          <td>(</td>
+          <td class="paramtype">uint32_t&#160;</td>
+          <td class="paramname"><em>mask</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Clear counter overflow status. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">mask</td><td>Counter overflow status bits to clear </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section note"><dt>Note</dt><dd>Clears overflow status bits for one or more of the following:<ul>
+<li>event counters (0-30)</li>
+<li>cycle counter </li>
+</ul>
+</dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga77ee08f0b3e77d4559cb79fde30d89e9"></a>
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_PMU_Set_EVTYPER </td>
+          <td>(</td>
+          <td class="paramtype">uint32_t&#160;</td>
+          <td class="paramname"><em>num</em>, </td>
+        </tr>
+        <tr>
+          <td class="paramkey"></td>
+          <td></td>
+          <td class="paramtype">uint32_t&#160;</td>
+          <td class="paramname"><em>type</em>&#160;</td>
+        </tr>
+        <tr>
+          <td></td>
+          <td>)</td>
+          <td></td><td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+
+<p>Set event to count for PMU event counter. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">num</td><td>Event counter (0-30) to configure </td></tr>
+    <tr><td class="paramdir">[in]</td><td class="paramname">type</td><td>Event to count </td></tr>
+  </table>
+  </dd>
+</dl>
+
+</div>
+</div>
+</div><!-- contents -->
+</div><!-- doc-content -->
+<!-- start footer part -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">Generated on Thu Apr 9 2020 15:49:08 for CMSIS-Core (Cortex-M) Version 5.4.0 by Arm Ltd. All rights reserved.
+	<!--
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