CoreValidation: Added test projects for Cortex-M devices.

CMSIS/CoreValidation/Tests/.gitignore

@@ -0,0 +1,7 @@
+result*.xml
+*.log
+*.uvguix*
+*.uvoptx
+/**/Listings/*
+/**/Objects/*
+*.pyc

CMSIS/CoreValidation/Tests/Cortex-M0/AC5/CMSIS_CV.uvprojx

@@ -0,0 +1,490 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>FVP</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pArmCC>5060528::V5.06 update 5 (build 528)::ARMCC</pArmCC>
+      <pCCUsed>5060528::V5.06 update 5 (build 528)::ARMCC</pCCUsed>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>ARMCM0</Device>
+          <Vendor>ARM</Vendor>
+          <PackID>ARM.CMSIS.5.1.2-dev1</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0") CLOCK(12000000) ESEL ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:ARMCM0$Device\ARM\ARMCM0\Include\ARMCM0.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:ARMCM0$Device\ARM\SVD\ARMCM0.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\Objects\</OutputDirectory>
+          <OutputName>CMSIS_CV</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\Listings\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>  </SimDllArguments>
+          <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM0</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> </TargetDllArguments>
+          <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>1</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M0"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>1</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <useXO>0</useXO>
+            <v6Lang>3</v6Lang>
+            <v6LangP>3</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>.\,..\..\..\Include</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <uClangAs>0</uClangAs>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>.\,..\..\..\Include</IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange></TextAddressRange>
+            <DataAddressRange></DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc>--entry=Reset_Handler</Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Test</GroupName>
+          <Files>
+            <File>
+              <FileName>cmsis_cv.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\cmsis_cv.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_CoreFunc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_CoreFunc.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_CoreInstr.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_CoreInstr.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Framework.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_Framework.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Report.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_Report.c</FilePath>
+            </File>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\main.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Config.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\CV_Config.h</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::CMSIS</GroupName>
+        </Group>
+        <Group>
+          <GroupName>::Device</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components>
+      <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.0.2" condition="ARMv6_7_8-M Device">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0 CMSIS">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </component>
+    </components>
+    <files>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM0\Source\ARM\startup_ARMCM0.s" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM0\startup_ARMCM0.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM0\Source\system_ARMCM0.c" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM0\system_ARMCM0.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM3\Source\ARM\startup_ARMCM3.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM3\startup_ARMCM3.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM3\Source\system_ARMCM3.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM3\system_ARMCM3.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM4\Source\ARM\startup_ARMCM4.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM4\startup_ARMCM4.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM4\Source\system_ARMCM4.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM4\system_ARMCM4.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+    </files>
+  </RTE>
+
+</Project>

CMSIS/CoreValidation/Tests/Cortex-M0/AC5/CV_Config.h

@@ -0,0 +1,81 @@
+/*-----------------------------------------------------------------------------
+ *      Name:         CV_Config.h 
+ *      Purpose:      CV Config header
+ *----------------------------------------------------------------------------
+ *      Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+#ifndef __CV_CONFIG_H
+#define __CV_CONFIG_H
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+#define RTE_CV_COREINSTR 1
+#define RTE_CV_COREFUNC  1
+
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h> Common Test Settings
+// <o> Print Output Format <0=> Plain Text <1=> XML
+// <i> Set the test results output format to plain text or XML
+#ifndef PRINT_XML_REPORT
+#define PRINT_XML_REPORT            1
+#endif
+// <o> Buffer size for assertions results
+// <i> Set the buffer size for assertions results buffer
+#define BUFFER_ASSERTIONS           128U
+// </h>
+
+// <h> Disable Test Cases
+// <i> Uncheck to disable an individual test case
+// <q00> TC_CoreInstr_NOP
+// <q01> TC_CoreInstr_REV
+// <q02> TC_CoreInstr_REV16
+// <q03> TC_CoreInstr_REVSH
+// <q04> TC_CoreInstr_ROR
+// <q05> TC_CoreInstr_RBIT
+// <q06> TC_CoreInstr_CLZ
+// <q07> TC_CoreInstr_SSAT
+// <q08> TC_CoreInstr_USAT
+//
+// <q09> TC_CoreFunc_EnDisIRQ
+// <q10> TC_CoreFunc_Control
+// <q11> TC_CoreFunc_IPSR
+// <q12> TC_CoreFunc_APSR
+// <q13> TC_CoreFunc_PSP
+// <q14> TC_CoreFunc_MSP
+// <q15> TC_CoreFunc_PRIMASK
+// <q16> TC_CoreFunc_FAULTMASK
+// <q17> TC_CoreFunc_BASEPRI
+// <q18> TC_CoreFunc_FPSCR
+//
+// <q19> TC_MPU_SetClear
+// <q20> TC_MPU_Load
+#define TC_COREINSTR_NOP_EN         1
+#define TC_COREINSTR_REV_EN         1
+#define TC_COREINSTR_REV16_EN       1
+#define TC_COREINSTR_REVSH_EN       1
+#define TC_COREINSTR_ROR_EN         1
+#define TC_COREINSTR_RBIT_EN        1
+#define TC_COREINSTR_CLZ_EN         1
+#define TC_COREINSTR_SSAT_EN        1
+#define TC_COREINSTR_USAT_EN        1
+
+#define TC_COREFUNC_ENDISIRQ_EN     1
+#define TC_COREFUNC_CONTROL_EN      1
+#define TC_COREFUNC_IPSR_EN         1
+#define TC_COREFUNC_APSR_EN         1
+#define TC_COREFUNC_PSP_EN          1
+#define TC_COREFUNC_MSP_EN          1
+#define TC_COREFUNC_PRIMASK_EN      1
+#define TC_COREFUNC_FAULTMASK_EN    1
+#define TC_COREFUNC_BASEPRI_EN      1
+#define TC_COREFUNC_FPSCR_EN        1
+
+#define TC_MPU_SETCLEAR_EN          1
+#define TC_MPU_LOAD_EN              1
+// </h>
+
+#endif /* __CV_CONFIG_H */
+

CMSIS/CoreValidation/Tests/Cortex-M0/AC5/EventRecorderStub.scvd

@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
+
+<component name="EventRecorderStub" version="1.0.0"/>       <!--name and version of the component-->
+  <events>
+  </events>
+
+</component_viewer>

CMSIS/CoreValidation/Tests/Cortex-M0/AC5/RTE/Device/ARMCM0/startup_ARMCM0.s

@@ -0,0 +1,242 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM0.s
+; * @brief    CMSIS Core Device Startup File for
+; *           ARMCM0 Device Series
+; * @version  V5.00
+; * @date     02. March 2016
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000C00
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
+                DCD     RTC_IRQHandler            ;  1:  Real Time Clock
+                DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
+                DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
+                DCD     MCIA_IRQHandler           ;  4:  MCIa
+                DCD     MCIB_IRQHandler           ;  5:  MCIb
+                DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
+                DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
+                DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
+                DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
+                DCD     AACI_IRQHandler           ; 10: AACI / AC97
+                DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
+                DCD     ENET_IRQHandler           ; 12: Ethernet
+                DCD     USBDC_IRQHandler          ; 13: USB Device
+                DCD     USBHC_IRQHandler          ; 14: USB Host Controller
+                DCD     CHLCD_IRQHandler          ; 15: Character LCD
+                DCD     FLEXRAY_IRQHandler        ; 16: Flexray
+                DCD     CAN_IRQHandler            ; 17: CAN
+                DCD     LIN_IRQHandler            ; 18: LIN
+                DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
+                DCD     0                         ; 20: Reserved
+                DCD     0                         ; 21: Reserved
+                DCD     0                         ; 22: Reserved
+                DCD     0                         ; 23: Reserved
+                DCD     0                         ; 24: Reserved
+                DCD     0                         ; 25: Reserved
+                DCD     0                         ; 26: Reserved
+                DCD     0                         ; 27: Reserved
+                DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
+                DCD     0                         ; 29: Reserved - CPU FPGA
+                DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
+                DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WDT_IRQHandler            [WEAK]
+                EXPORT  RTC_IRQHandler            [WEAK]
+                EXPORT  TIM0_IRQHandler           [WEAK]
+                EXPORT  TIM2_IRQHandler           [WEAK]
+                EXPORT  MCIA_IRQHandler           [WEAK]
+                EXPORT  MCIB_IRQHandler           [WEAK]
+                EXPORT  UART0_IRQHandler          [WEAK]
+                EXPORT  UART1_IRQHandler          [WEAK]
+                EXPORT  UART2_IRQHandler          [WEAK]
+                EXPORT  UART3_IRQHandler          [WEAK]
+                EXPORT  UART4_IRQHandler          [WEAK]
+                EXPORT  AACI_IRQHandler           [WEAK]
+                EXPORT  CLCD_IRQHandler           [WEAK]
+                EXPORT  ENET_IRQHandler           [WEAK]
+                EXPORT  USBDC_IRQHandler          [WEAK]
+                EXPORT  USBHC_IRQHandler          [WEAK]
+                EXPORT  CHLCD_IRQHandler          [WEAK]
+                EXPORT  FLEXRAY_IRQHandler        [WEAK]
+                EXPORT  CAN_IRQHandler            [WEAK]
+                EXPORT  LIN_IRQHandler            [WEAK]
+                EXPORT  I2C_IRQHandler            [WEAK]
+                EXPORT  CPU_CLCD_IRQHandler       [WEAK]
+                EXPORT  SPI_IRQHandler            [WEAK]
+
+WDT_IRQHandler
+RTC_IRQHandler
+TIM0_IRQHandler
+TIM2_IRQHandler
+MCIA_IRQHandler
+MCIB_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+UART4_IRQHandler
+AACI_IRQHandler
+CLCD_IRQHandler
+ENET_IRQHandler
+USBDC_IRQHandler
+USBHC_IRQHandler
+CHLCD_IRQHandler
+FLEXRAY_IRQHandler
+CAN_IRQHandler
+LIN_IRQHandler
+I2C_IRQHandler
+CPU_CLCD_IRQHandler
+SPI_IRQHandler
+                B       .
+
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap PROC
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+                ENDP
+
+                ALIGN
+
+                ENDIF
+
+
+                END

CMSIS/CoreValidation/Tests/Cortex-M0/AC5/RTE/Device/ARMCM0/system_ARMCM0.c

@@ -0,0 +1,56 @@
+/**************************************************************************//**
+ * @file     system_ARMCM0.c
+ * @brief    CMSIS Device System Source File for
+ *           ARMCM0 Device Series
+ * @version  V5.00
+ * @date     07. September 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ARMCM0.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+
+#define  SYSTEM_CLOCK    (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}

CMSIS/CoreValidation/Tests/Cortex-M0/AC5/RTE/_FVP/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'CMSIS_CV' 
+ * Target:  'FVP' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "ARMCM0.h"
+
+
+#endif /* RTE_COMPONENTS_H */

CMSIS/CoreValidation/Tests/Cortex-M0/AC6/CMSIS_CV.uvprojx

@@ -0,0 +1,490 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>FVP</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pArmCC>6070000::V6.7::.\ARMCLANG</pArmCC>
+      <pCCUsed>6070000::V6.7::.\ARMCLANG</pCCUsed>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>ARMCM0</Device>
+          <Vendor>ARM</Vendor>
+          <PackID>ARM.CMSIS.5.1.2-dev1</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0") CLOCK(12000000) ESEL ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:ARMCM0$Device\ARM\ARMCM0\Include\ARMCM0.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:ARMCM0$Device\ARM\SVD\ARMCM0.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\Objects\</OutputDirectory>
+          <OutputName>CMSIS_CV</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\Listings\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>  </SimDllArguments>
+          <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM0</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> </TargetDllArguments>
+          <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>1</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M0"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>1</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <useXO>0</useXO>
+            <v6Lang>3</v6Lang>
+            <v6LangP>3</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls>-Wno-covered-switch-default</MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>.\,..\..\..\Include</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <uClangAs>0</uClangAs>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>.\,..\..\..\Include</IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange></TextAddressRange>
+            <DataAddressRange></DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc>--entry=Reset_Handler</Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Test</GroupName>
+          <Files>
+            <File>
+              <FileName>cmsis_cv.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\cmsis_cv.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_CoreFunc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_CoreFunc.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_CoreInstr.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_CoreInstr.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Framework.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_Framework.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Report.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_Report.c</FilePath>
+            </File>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\main.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Config.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\CV_Config.h</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::CMSIS</GroupName>
+        </Group>
+        <Group>
+          <GroupName>::Device</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components>
+      <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.0.2" condition="ARMv6_7_8-M Device">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0 CMSIS">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </component>
+    </components>
+    <files>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM0\Source\ARM\startup_ARMCM0.s" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM0\startup_ARMCM0.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM0\Source\system_ARMCM0.c" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM0\system_ARMCM0.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM3\Source\ARM\startup_ARMCM3.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM3\startup_ARMCM3.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM3\Source\system_ARMCM3.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM3\system_ARMCM3.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM4\Source\ARM\startup_ARMCM4.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM4\startup_ARMCM4.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM4\Source\system_ARMCM4.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM4\system_ARMCM4.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+    </files>
+  </RTE>
+
+</Project>

CMSIS/CoreValidation/Tests/Cortex-M0/AC6/CV_Config.h

@@ -0,0 +1,81 @@
+/*-----------------------------------------------------------------------------
+ *      Name:         CV_Config.h 
+ *      Purpose:      CV Config header
+ *----------------------------------------------------------------------------
+ *      Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+#ifndef __CV_CONFIG_H
+#define __CV_CONFIG_H
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+#define RTE_CV_COREINSTR 1
+#define RTE_CV_COREFUNC  1
+
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h> Common Test Settings
+// <o> Print Output Format <0=> Plain Text <1=> XML
+// <i> Set the test results output format to plain text or XML
+#ifndef PRINT_XML_REPORT
+#define PRINT_XML_REPORT            1
+#endif
+// <o> Buffer size for assertions results
+// <i> Set the buffer size for assertions results buffer
+#define BUFFER_ASSERTIONS           128U
+// </h>
+
+// <h> Disable Test Cases
+// <i> Uncheck to disable an individual test case
+// <q00> TC_CoreInstr_NOP
+// <q01> TC_CoreInstr_REV
+// <q02> TC_CoreInstr_REV16
+// <q03> TC_CoreInstr_REVSH
+// <q04> TC_CoreInstr_ROR
+// <q05> TC_CoreInstr_RBIT
+// <q06> TC_CoreInstr_CLZ
+// <q07> TC_CoreInstr_SSAT
+// <q08> TC_CoreInstr_USAT
+//
+// <q09> TC_CoreFunc_EnDisIRQ
+// <q10> TC_CoreFunc_Control
+// <q11> TC_CoreFunc_IPSR
+// <q12> TC_CoreFunc_APSR
+// <q13> TC_CoreFunc_PSP
+// <q14> TC_CoreFunc_MSP
+// <q15> TC_CoreFunc_PRIMASK
+// <q16> TC_CoreFunc_FAULTMASK
+// <q17> TC_CoreFunc_BASEPRI
+// <q18> TC_CoreFunc_FPSCR
+//
+// <q19> TC_MPU_SetClear
+// <q20> TC_MPU_Load
+#define TC_COREINSTR_NOP_EN         1
+#define TC_COREINSTR_REV_EN         1
+#define TC_COREINSTR_REV16_EN       1
+#define TC_COREINSTR_REVSH_EN       1
+#define TC_COREINSTR_ROR_EN         1
+#define TC_COREINSTR_RBIT_EN        1
+#define TC_COREINSTR_CLZ_EN         1
+#define TC_COREINSTR_SSAT_EN        1
+#define TC_COREINSTR_USAT_EN        1
+
+#define TC_COREFUNC_ENDISIRQ_EN     1
+#define TC_COREFUNC_CONTROL_EN      1
+#define TC_COREFUNC_IPSR_EN         1
+#define TC_COREFUNC_APSR_EN         1
+#define TC_COREFUNC_PSP_EN          1
+#define TC_COREFUNC_MSP_EN          1
+#define TC_COREFUNC_PRIMASK_EN      1
+#define TC_COREFUNC_FAULTMASK_EN    1
+#define TC_COREFUNC_BASEPRI_EN      1
+#define TC_COREFUNC_FPSCR_EN        1
+
+#define TC_MPU_SETCLEAR_EN          1
+#define TC_MPU_LOAD_EN              1
+// </h>
+
+#endif /* __CV_CONFIG_H */
+

CMSIS/CoreValidation/Tests/Cortex-M0/AC6/EventRecorderStub.scvd

@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
+
+<component name="EventRecorderStub" version="1.0.0"/>       <!--name and version of the component-->
+  <events>
+  </events>
+
+</component_viewer>

CMSIS/CoreValidation/Tests/Cortex-M0/AC6/RTE/Device/ARMCM0/startup_ARMCM0.s

@@ -0,0 +1,242 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM0.s
+; * @brief    CMSIS Core Device Startup File for
+; *           ARMCM0 Device Series
+; * @version  V5.00
+; * @date     02. March 2016
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000C00
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
+                DCD     RTC_IRQHandler            ;  1:  Real Time Clock
+                DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
+                DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
+                DCD     MCIA_IRQHandler           ;  4:  MCIa
+                DCD     MCIB_IRQHandler           ;  5:  MCIb
+                DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
+                DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
+                DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
+                DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
+                DCD     AACI_IRQHandler           ; 10: AACI / AC97
+                DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
+                DCD     ENET_IRQHandler           ; 12: Ethernet
+                DCD     USBDC_IRQHandler          ; 13: USB Device
+                DCD     USBHC_IRQHandler          ; 14: USB Host Controller
+                DCD     CHLCD_IRQHandler          ; 15: Character LCD
+                DCD     FLEXRAY_IRQHandler        ; 16: Flexray
+                DCD     CAN_IRQHandler            ; 17: CAN
+                DCD     LIN_IRQHandler            ; 18: LIN
+                DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
+                DCD     0                         ; 20: Reserved
+                DCD     0                         ; 21: Reserved
+                DCD     0                         ; 22: Reserved
+                DCD     0                         ; 23: Reserved
+                DCD     0                         ; 24: Reserved
+                DCD     0                         ; 25: Reserved
+                DCD     0                         ; 26: Reserved
+                DCD     0                         ; 27: Reserved
+                DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
+                DCD     0                         ; 29: Reserved - CPU FPGA
+                DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
+                DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WDT_IRQHandler            [WEAK]
+                EXPORT  RTC_IRQHandler            [WEAK]
+                EXPORT  TIM0_IRQHandler           [WEAK]
+                EXPORT  TIM2_IRQHandler           [WEAK]
+                EXPORT  MCIA_IRQHandler           [WEAK]
+                EXPORT  MCIB_IRQHandler           [WEAK]
+                EXPORT  UART0_IRQHandler          [WEAK]
+                EXPORT  UART1_IRQHandler          [WEAK]
+                EXPORT  UART2_IRQHandler          [WEAK]
+                EXPORT  UART3_IRQHandler          [WEAK]
+                EXPORT  UART4_IRQHandler          [WEAK]
+                EXPORT  AACI_IRQHandler           [WEAK]
+                EXPORT  CLCD_IRQHandler           [WEAK]
+                EXPORT  ENET_IRQHandler           [WEAK]
+                EXPORT  USBDC_IRQHandler          [WEAK]
+                EXPORT  USBHC_IRQHandler          [WEAK]
+                EXPORT  CHLCD_IRQHandler          [WEAK]
+                EXPORT  FLEXRAY_IRQHandler        [WEAK]
+                EXPORT  CAN_IRQHandler            [WEAK]
+                EXPORT  LIN_IRQHandler            [WEAK]
+                EXPORT  I2C_IRQHandler            [WEAK]
+                EXPORT  CPU_CLCD_IRQHandler       [WEAK]
+                EXPORT  SPI_IRQHandler            [WEAK]
+
+WDT_IRQHandler
+RTC_IRQHandler
+TIM0_IRQHandler
+TIM2_IRQHandler
+MCIA_IRQHandler
+MCIB_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+UART4_IRQHandler
+AACI_IRQHandler
+CLCD_IRQHandler
+ENET_IRQHandler
+USBDC_IRQHandler
+USBHC_IRQHandler
+CHLCD_IRQHandler
+FLEXRAY_IRQHandler
+CAN_IRQHandler
+LIN_IRQHandler
+I2C_IRQHandler
+CPU_CLCD_IRQHandler
+SPI_IRQHandler
+                B       .
+
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap PROC
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+                ENDP
+
+                ALIGN
+
+                ENDIF
+
+
+                END

CMSIS/CoreValidation/Tests/Cortex-M0/AC6/RTE/Device/ARMCM0/system_ARMCM0.c

@@ -0,0 +1,56 @@
+/**************************************************************************//**
+ * @file     system_ARMCM0.c
+ * @brief    CMSIS Device System Source File for
+ *           ARMCM0 Device Series
+ * @version  V5.00
+ * @date     07. September 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ARMCM0.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+
+#define  SYSTEM_CLOCK    (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}

CMSIS/CoreValidation/Tests/Cortex-M0/AC6/RTE/_FVP/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'CMSIS_CV' 
+ * Target:  'FVP' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "ARMCM0.h"
+
+
+#endif /* RTE_COMPONENTS_H */

CMSIS/CoreValidation/Tests/Cortex-M0/GCC/CMSIS_CV.uvprojx

@@ -0,0 +1,423 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>FVP</TargetName>
+      <ToolsetNumber>0x3</ToolsetNumber>
+      <ToolsetName>ARM-GNU</ToolsetName>
+      <pArmCC>6070000::V6.7::.\ARMCLANG</pArmCC>
+      <pCCUsed>6070000::V6.7::.\ARMCLANG</pCCUsed>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>ARMCM0</Device>
+          <Vendor>ARM</Vendor>
+          <PackID>ARM.CMSIS.5.1.2-dev1</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0") CLOCK(12000000) ESEL ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:ARMCM0$Device\ARM\ARMCM0\Include\ARMCM0.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:ARMCM0$Device\ARM\SVD\ARMCM0.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\Objects\</OutputDirectory>
+          <OutputName>CMSIS_CV</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\Listings\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>  </SimDllArguments>
+          <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM0</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> </TargetDllArguments>
+          <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArm>
+          <ArmMisc>
+            <asLst>1</asLst>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>1</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <GCPUTYP>"Cortex-M0"</GCPUTYP>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <IRAM2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </IRAM2>
+              <IROM2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </IROM2>
+            </OnChipMemories>
+          </ArmMisc>
+          <Carm>
+            <arpcs>1</arpcs>
+            <stkchk>0</stkchk>
+            <reentr>0</reentr>
+            <interw>1</interw>
+            <bigend>0</bigend>
+            <Strict>0</Strict>
+            <Optim>1</Optim>
+            <wLevel>3</wLevel>
+            <uThumb>1</uThumb>
+            <VariousControls>
+              <MiscControls>-Wall -Wextra -Wstrict-prototypes -Wshadow</MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>.;..\..\..\Include</IncludePath>
+            </VariousControls>
+          </Carm>
+          <Aarm>
+            <bBE>0</bBE>
+            <interw>1</interw>
+            <VariousControls>
+              <MiscControls>-Wall</MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>.;..\..\..\Include</IncludePath>
+            </VariousControls>
+          </Aarm>
+          <LDarm>
+            <umfTarg>1</umfTarg>
+            <enaGarb>0</enaGarb>
+            <noStart>0</noStart>
+            <noStLib>0</noStLib>
+            <uMathLib>0</uMathLib>
+            <TextAddressRange></TextAddressRange>
+            <DataAddressRange></DataAddressRange>
+            <BSSAddressRange></BSSAddressRange>
+            <IncludeLibs></IncludeLibs>
+            <IncludeDir></IncludeDir>
+            <Misc>--specs=rdimon.specs</Misc>
+            <ScatterFile>.\RTE\Device\ARMCM0\gcc_arm.ld</ScatterFile>
+          </LDarm>
+        </TargetArm>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Test</GroupName>
+          <Files>
+            <File>
+              <FileName>cmsis_cv.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\cmsis_cv.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_CoreFunc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_CoreFunc.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_CoreInstr.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_CoreInstr.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Framework.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_Framework.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Report.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_Report.c</FilePath>
+            </File>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\main.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Config.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\CV_Config.h</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::CMSIS</GroupName>
+        </Group>
+        <Group>
+          <GroupName>::Device</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components>
+      <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.0.2" condition="ARMv6_7_8-M Device">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0 CMSIS GCC">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </component>
+    </components>
+    <files>
+      <file attr="config" category="linkerScript" condition="GCC" name="Device\ARM\ARMCM0\Source\GCC\gcc_arm.ld" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM0\gcc_arm.ld</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0 CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="sourceC" condition="GCC" name="Device\ARM\ARMCM0\Source\GCC\startup_ARMCM0.c" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM0\startup_ARMCM0.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0 CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM0\Source\ARM\startup_ARMCM0.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM0\startup_ARMCM0.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM0\Source\system_ARMCM0.c" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM0\system_ARMCM0.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0 CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="linkerScript" condition="GCC" name="Device\ARM\ARMCM3\Source\GCC\gcc_arm.ld" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM3\gcc_arm.ld</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceAsm" condition="GCC" name="Device\ARM\ARMCM3\Source\GCC\startup_ARMCM3.S" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM3\startup_ARMCM3.S</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" condition="GCC" name="Device\ARM\ARMCM3\Source\GCC\startup_ARMCM3.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM3\startup_ARMCM3.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM3\Source\system_ARMCM3.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM3\system_ARMCM3.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="linkerScript" condition="GCC" name="Device\ARM\ARMCM4\Source\GCC\gcc_arm.ld" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM4\gcc_arm.ld</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" condition="GCC" name="Device\ARM\ARMCM4\Source\GCC\startup_ARMCM4.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM4\startup_ARMCM4.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM4\Source\ARM\startup_ARMCM4.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM4\startup_ARMCM4.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM4\Source\system_ARMCM4.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM4\system_ARMCM4.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+    </files>
+  </RTE>
+
+</Project>

CMSIS/CoreValidation/Tests/Cortex-M0/GCC/CV_Config.h

@@ -0,0 +1,81 @@
+/*-----------------------------------------------------------------------------
+ *      Name:         CV_Config.h 
+ *      Purpose:      CV Config header
+ *----------------------------------------------------------------------------
+ *      Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+#ifndef __CV_CONFIG_H
+#define __CV_CONFIG_H
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+#define RTE_CV_COREINSTR 1
+#define RTE_CV_COREFUNC  1
+
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h> Common Test Settings
+// <o> Print Output Format <0=> Plain Text <1=> XML
+// <i> Set the test results output format to plain text or XML
+#ifndef PRINT_XML_REPORT
+#define PRINT_XML_REPORT            1
+#endif
+// <o> Buffer size for assertions results
+// <i> Set the buffer size for assertions results buffer
+#define BUFFER_ASSERTIONS           128U
+// </h>
+
+// <h> Disable Test Cases
+// <i> Uncheck to disable an individual test case
+// <q00> TC_CoreInstr_NOP
+// <q01> TC_CoreInstr_REV
+// <q02> TC_CoreInstr_REV16
+// <q03> TC_CoreInstr_REVSH
+// <q04> TC_CoreInstr_ROR
+// <q05> TC_CoreInstr_RBIT
+// <q06> TC_CoreInstr_CLZ
+// <q07> TC_CoreInstr_SSAT
+// <q08> TC_CoreInstr_USAT
+//
+// <q09> TC_CoreFunc_EnDisIRQ
+// <q10> TC_CoreFunc_Control
+// <q11> TC_CoreFunc_IPSR
+// <q12> TC_CoreFunc_APSR
+// <q13> TC_CoreFunc_PSP
+// <q14> TC_CoreFunc_MSP
+// <q15> TC_CoreFunc_PRIMASK
+// <q16> TC_CoreFunc_FAULTMASK
+// <q17> TC_CoreFunc_BASEPRI
+// <q18> TC_CoreFunc_FPSCR
+//
+// <q19> TC_MPU_SetClear
+// <q20> TC_MPU_Load
+#define TC_COREINSTR_NOP_EN         1
+#define TC_COREINSTR_REV_EN         1
+#define TC_COREINSTR_REV16_EN       1
+#define TC_COREINSTR_REVSH_EN       1
+#define TC_COREINSTR_ROR_EN         1
+#define TC_COREINSTR_RBIT_EN        1
+#define TC_COREINSTR_CLZ_EN         1
+#define TC_COREINSTR_SSAT_EN        1
+#define TC_COREINSTR_USAT_EN        1
+
+#define TC_COREFUNC_ENDISIRQ_EN     1
+#define TC_COREFUNC_CONTROL_EN      1
+#define TC_COREFUNC_IPSR_EN         1
+#define TC_COREFUNC_APSR_EN         1
+#define TC_COREFUNC_PSP_EN          1
+#define TC_COREFUNC_MSP_EN          1
+#define TC_COREFUNC_PRIMASK_EN      1
+#define TC_COREFUNC_FAULTMASK_EN    1
+#define TC_COREFUNC_BASEPRI_EN      1
+#define TC_COREFUNC_FPSCR_EN        1
+
+#define TC_MPU_SETCLEAR_EN          1
+#define TC_MPU_LOAD_EN              1
+// </h>
+
+#endif /* __CV_CONFIG_H */
+

CMSIS/CoreValidation/Tests/Cortex-M0/GCC/EventRecorderStub.scvd

@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
+
+<component name="EventRecorderStub" version="1.0.0"/>       <!--name and version of the component-->
+  <events>
+  </events>
+
+</component_viewer>

CMSIS/CoreValidation/Tests/Cortex-M0/GCC/RTE/Device/ARMCM0/gcc_arm.ld

@@ -0,0 +1,196 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+  FLASH (rx)  : ORIGIN = 0x00000000, LENGTH = 512K
+  RAM   (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapBase
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __Vectors_End
+ *   __Vectors_Size
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+	.text :
+	{
+		KEEP(*(.vectors))
+		__Vectors_End = .;
+		__Vectors_Size = __Vectors_End - __Vectors;
+		__end__ = .;
+
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+	.ARM.extab :
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	/* To copy multiple ROM to RAM sections,
+	 * uncomment .copy.table section and,
+	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.copy.table :
+	{
+		. = ALIGN(4);
+		__copy_table_start__ = .;
+		LONG (__etext)
+		LONG (__data_start__)
+		LONG (__data_end__ - __data_start__)
+		LONG (__etext2)
+		LONG (__data2_start__)
+		LONG (__data2_end__ - __data2_start__)
+		__copy_table_end__ = .;
+	} > FLASH
+	*/
+
+	/* To clear multiple BSS sections,
+	 * uncomment .zero.table section and,
+	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.zero.table :
+	{
+		. = ALIGN(4);
+		__zero_table_start__ = .;
+		LONG (__bss_start__)
+		LONG (__bss_end__ - __bss_start__)
+		LONG (__bss2_start__)
+		LONG (__bss2_end__ - __bss2_start__)
+		__zero_table_end__ = .;
+	} > FLASH
+	*/
+
+	__etext = .;
+
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		KEEP(*(.jcr*))
+		. = ALIGN(4);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > RAM
+
+	.heap (COPY):
+	{
+		__HeapBase = .;
+		__end__ = .;
+		end = __end__;
+		KEEP(*(.heap*))
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (COPY):
+	{
+		KEEP(*(.stack*))
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM);
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}

CMSIS/CoreValidation/Tests/Cortex-M0/GCC/RTE/Device/ARMCM0/startup_ARMCM0.c

@@ -0,0 +1,291 @@
+/**************************************************************************//**
+ * @file     startup_ARMCM0.s
+ * @brief    CMSIS Core Device Startup File for
+ *           ARMCM0 Device Series
+ * @version  V5.00
+ * @date     26. March 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdint.h>
+
+
+/*----------------------------------------------------------------------------
+  Linker generated Symbols
+ *----------------------------------------------------------------------------*/
+extern uint32_t __etext;
+extern uint32_t __data_start__;
+extern uint32_t __data_end__;
+extern uint32_t __copy_table_start__;
+extern uint32_t __copy_table_end__;
+extern uint32_t __zero_table_start__;
+extern uint32_t __zero_table_end__;
+extern uint32_t __bss_start__;
+extern uint32_t __bss_end__;
+extern uint32_t __StackTop;
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler Function Prototype
+ *----------------------------------------------------------------------------*/
+typedef void( *pFunc )( void );
+
+
+/*----------------------------------------------------------------------------
+  External References
+ *----------------------------------------------------------------------------*/
+#ifndef __START
+extern void  _start(void) __attribute__((noreturn));    /* PreeMain (C library entry point) */
+#else
+extern int  __START(void) __attribute__((noreturn));    /* main entry point */
+#endif
+
+#ifndef __NO_SYSTEM_INIT
+extern void SystemInit (void);            /* CMSIS System Initialization      */
+#endif
+
+
+/*----------------------------------------------------------------------------
+  Internal References
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void);                          /* Default empty handler */
+void Reset_Handler(void);                            /* Reset Handler */
+
+
+/*----------------------------------------------------------------------------
+  User Initial Stack & Heap
+ *----------------------------------------------------------------------------*/
+#ifndef __STACK_SIZE
+  #define	__STACK_SIZE  0x00000400
+#endif
+static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack")));
+
+#ifndef __HEAP_SIZE
+  #define	__HEAP_SIZE   0x00000C00
+#endif
+#if __HEAP_SIZE > 0
+static uint8_t heap[__HEAP_SIZE]   __attribute__ ((aligned(8), used, section(".heap")));
+#endif
+
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Cortex-M0 Processor Exceptions */
+void NMI_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/* ARMCM0 Specific Interrupts */
+void WDT_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void RTC_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void TIM0_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void TIM2_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void MCIA_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void MCIB_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART0_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART1_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART2_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART4_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void AACI_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void CLCD_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void ENET_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void USBDC_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void USBHC_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void CHLCD_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void FLEXRAY_IRQHandler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void CAN_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void LIN_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void I2C_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void CPU_CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART3_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void SPI_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = {
+  /* Cortex-M0 Exceptions Handler */
+  (pFunc)((uint32_t)&__StackTop),           /*      Initial Stack Pointer     */
+  Reset_Handler,                            /*      Reset Handler             */
+  NMI_Handler,                              /*      NMI Handler               */
+  HardFault_Handler,                        /*      Hard Fault Handler        */
+  0,                                        /*      Reserved                  */
+  0,                                        /*      Reserved                  */
+  0,                                        /*      Reserved                  */
+  0,                                        /*      Reserved                  */
+  0,                                        /*      Reserved                  */
+  0,                                        /*      Reserved                  */
+  0,                                        /*      Reserved                  */
+  SVC_Handler,                              /*      SVCall Handler            */
+  0,                                        /*      Reserved                  */
+  0,                                        /*      Reserved                  */
+  PendSV_Handler,                           /*      PendSV Handler            */
+  SysTick_Handler,                          /*      SysTick Handler           */
+
+  /* External interrupts */
+  WDT_IRQHandler,                           /*  0:  Watchdog Timer            */
+  RTC_IRQHandler,                           /*  1:  Real Time Clock           */
+  TIM0_IRQHandler,                          /*  2:  Timer0 / Timer1           */
+  TIM2_IRQHandler,                          /*  3:  Timer2 / Timer3           */
+  MCIA_IRQHandler,                          /*  4:  MCIa                      */
+  MCIB_IRQHandler,                          /*  5:  MCIb                      */
+  UART0_IRQHandler,                         /*  6:  UART0 - DUT FPGA          */
+  UART1_IRQHandler,                         /*  7:  UART1 - DUT FPGA          */
+  UART2_IRQHandler,                         /*  8:  UART2 - DUT FPGA          */
+  UART4_IRQHandler,                         /*  9:  UART4 - not connected     */
+  AACI_IRQHandler,                          /* 10: AACI / AC97                */
+  CLCD_IRQHandler,                          /* 11: CLCD Combined Interrupt    */
+  ENET_IRQHandler,                          /* 12: Ethernet                   */
+  USBDC_IRQHandler,                         /* 13: USB Device                 */
+  USBHC_IRQHandler,                         /* 14: USB Host Controller        */
+  CHLCD_IRQHandler,                         /* 15: Character LCD              */
+  FLEXRAY_IRQHandler,                       /* 16: Flexray                    */
+  CAN_IRQHandler,                           /* 17: CAN                        */
+  LIN_IRQHandler,                           /* 18: LIN                        */
+  I2C_IRQHandler,                           /* 19: I2C ADC/DAC                */
+  0,                                        /* 20: Reserved                   */
+  0,                                        /* 21: Reserved                   */
+  0,                                        /* 22: Reserved                   */
+  0,                                        /* 23: Reserved                   */
+  0,                                        /* 24: Reserved                   */
+  0,                                        /* 25: Reserved                   */
+  0,                                        /* 26: Reserved                   */
+  0,                                        /* 27: Reserved                   */
+  CPU_CLCD_IRQHandler,                      /* 28: Reserved - CPU FPGA CLCD   */
+  0,                                        /* 29: Reserved - CPU FPGA        */
+  UART3_IRQHandler,                         /* 30: UART3    - CPU FPGA        */
+  SPI_IRQHandler                            /* 31: SPI Touchscreen - CPU FPGA */
+};
+
+
+/*----------------------------------------------------------------------------
+  Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+  uint32_t *pSrc, *pDest;
+  uint32_t *pTable __attribute__((unused));
+
+/*  Firstly it copies data from read only memory to RAM. There are two schemes
+ *  to copy. One can copy more than one sections. Another can only copy
+ *  one section.  The former scheme needs more instructions and read-only
+ *  data to implement than the latter.
+ *  Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.  */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/*  Multiple sections scheme.
+ *
+ *  Between symbol address __copy_table_start__ and __copy_table_end__,
+ *  there are array of triplets, each of which specify:
+ *    offset 0: LMA of start of a section to copy from
+ *    offset 4: VMA of start of a section to copy to
+ *    offset 8: size of the section to copy. Must be multiply of 4
+ *
+ *  All addresses must be aligned to 4 bytes boundary.
+ */
+  pTable = &__copy_table_start__;
+
+  for (; pTable < &__copy_table_end__; pTable = pTable + 3) {
+		pSrc  = (uint32_t*)*(pTable + 0);
+		pDest = (uint32_t*)*(pTable + 1);
+		for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
+      *pDest++ = *pSrc++;
+		}
+	}
+#else
+/*  Single section scheme.
+ *
+ *  The ranges of copy from/to are specified by following symbols
+ *    __etext: LMA of start of the section to copy from. Usually end of text
+ *    __data_start__: VMA of start of the section to copy to
+ *    __data_end__: VMA of end of the section to copy to
+ *
+ *  All addresses must be aligned to 4 bytes boundary.
+ */
+  pSrc  = &__etext;
+  pDest = &__data_start__;
+
+  for ( ; pDest < &__data_end__ ; ) {
+    *pDest++ = *pSrc++;
+  }
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/*  This part of work usually is done in C library startup code. Otherwise,
+ *  define this macro to enable it in this startup.
+ *
+ *  There are two schemes too. One can clear multiple BSS sections. Another
+ *  can only clear one section. The former is more size expensive than the
+ *  latter.
+ *
+ *  Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ *  Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/*  Multiple sections scheme.
+ *
+ *  Between symbol address __copy_table_start__ and __copy_table_end__,
+ *  there are array of tuples specifying:
+ *    offset 0: Start of a BSS section
+ *    offset 4: Size of this BSS section. Must be multiply of 4
+ */
+  pTable = &__zero_table_start__;
+
+  for (; pTable < &__zero_table_end__; pTable = pTable + 2) {
+		pDest = (uint32_t*)*(pTable + 0);
+		for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
+      *pDest++ = 0;
+		}
+	}
+#elif defined (__STARTUP_CLEAR_BSS)
+/*  Single BSS section scheme.
+ *
+ *  The BSS section is specified by following symbols
+ *    __bss_start__: start of the BSS section.
+ *    __bss_end__: end of the BSS section.
+ *
+ *  Both addresses must be aligned to 4 bytes boundary.
+ */
+  pDest = &__bss_start__;
+
+  for ( ; pDest < &__bss_end__ ; ) {
+    *pDest++ = 0UL;
+  }
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+#ifndef __NO_SYSTEM_INIT
+	SystemInit();
+#endif
+
+#ifndef __START
+#define __START _start
+#endif
+	__START();
+
+}
+
+
+/*----------------------------------------------------------------------------
+  Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+
+	while(1);
+}

CMSIS/CoreValidation/Tests/Cortex-M0/GCC/RTE/Device/ARMCM0/system_ARMCM0.c

@@ -0,0 +1,56 @@
+/**************************************************************************//**
+ * @file     system_ARMCM0.c
+ * @brief    CMSIS Device System Source File for
+ *           ARMCM0 Device Series
+ * @version  V5.00
+ * @date     07. September 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ARMCM0.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+
+#define  SYSTEM_CLOCK    (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}

CMSIS/CoreValidation/Tests/Cortex-M0/GCC/RTE/_FVP/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'CMSIS_CV' 
+ * Target:  'FVP' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "ARMCM0.h"
+
+
+#endif /* RTE_COMPONENTS_H */

CMSIS/CoreValidation/Tests/Cortex-M0plus/AC5/CMSIS_CV.uvprojx

@@ -0,0 +1,507 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>FVP</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pArmCC>5060528::V5.06 update 5 (build 528)::ARMCC</pArmCC>
+      <pCCUsed>5060528::V5.06 update 5 (build 528)::ARMCC</pCCUsed>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>ARMCM0P</Device>
+          <Vendor>ARM</Vendor>
+          <PackID>ARM.CMSIS.5.1.2-dev1</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ESEL ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:ARMCM0P$Device\ARM\ARMCM0plus\Include\ARMCM0plus.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:ARMCM0P$Device\ARM\SVD\ARMCM0P.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\Objects\</OutputDirectory>
+          <OutputName>CMSIS_CV</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\Listings\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>  </SimDllArguments>
+          <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM0+</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> </TargetDllArguments>
+          <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM0+</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>1</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M0+"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>1</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <useXO>0</useXO>
+            <v6Lang>3</v6Lang>
+            <v6LangP>3</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>.\,..\..\..\Include</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <uClangAs>0</uClangAs>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>.\,..\..\..\Include</IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange></TextAddressRange>
+            <DataAddressRange></DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc>--entry=Reset_Handler</Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Test</GroupName>
+          <Files>
+            <File>
+              <FileName>cmsis_cv.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\cmsis_cv.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_CoreFunc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_CoreFunc.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_CoreInstr.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_CoreInstr.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Framework.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_Framework.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_MPU_ARMv7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_MPU_ARMv7.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Report.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_Report.c</FilePath>
+            </File>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\main.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Config.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\CV_Config.h</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::CMSIS</GroupName>
+        </Group>
+        <Group>
+          <GroupName>::Device</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components>
+      <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.0.2" condition="ARMv6_7_8-M Device">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0+ CMSIS">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </component>
+    </components>
+    <files>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM0plus\Source\ARM\startup_ARMCM0plus.s" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM0P\startup_ARMCM0plus.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0+ CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM0plus\Source\system_ARMCM0plus.c" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM0P\system_ARMCM0plus.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0+ CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM0\Source\ARM\startup_ARMCM0.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM0\startup_ARMCM0.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM0\Source\system_ARMCM0.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM0\system_ARMCM0.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM3\Source\ARM\startup_ARMCM3.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM3\startup_ARMCM3.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM3\Source\system_ARMCM3.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM3\system_ARMCM3.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM4\Source\ARM\startup_ARMCM4.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM4\startup_ARMCM4.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM4\Source\system_ARMCM4.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM4\system_ARMCM4.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+    </files>
+  </RTE>
+
+</Project>

CMSIS/CoreValidation/Tests/Cortex-M0plus/AC5/CV_Config.h

@@ -0,0 +1,82 @@
+/*-----------------------------------------------------------------------------
+ *      Name:         CV_Config.h 
+ *      Purpose:      CV Config header
+ *----------------------------------------------------------------------------
+ *      Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+#ifndef __CV_CONFIG_H
+#define __CV_CONFIG_H
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+#define RTE_CV_COREINSTR 1
+#define RTE_CV_COREFUNC  1
+#define RTE_CV_MPUFUNC   1
+
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h> Common Test Settings
+// <o> Print Output Format <0=> Plain Text <1=> XML
+// <i> Set the test results output format to plain text or XML
+#ifndef PRINT_XML_REPORT
+#define PRINT_XML_REPORT            1
+#endif
+// <o> Buffer size for assertions results
+// <i> Set the buffer size for assertions results buffer
+#define BUFFER_ASSERTIONS           128U
+// </h>
+
+// <h> Disable Test Cases
+// <i> Uncheck to disable an individual test case
+// <q00> TC_CoreInstr_NOP
+// <q01> TC_CoreInstr_REV
+// <q02> TC_CoreInstr_REV16
+// <q03> TC_CoreInstr_REVSH
+// <q04> TC_CoreInstr_ROR
+// <q05> TC_CoreInstr_RBIT
+// <q06> TC_CoreInstr_CLZ
+// <q07> TC_CoreInstr_SSAT
+// <q08> TC_CoreInstr_USAT
+//
+// <q09> TC_CoreFunc_EnDisIRQ
+// <q10> TC_CoreFunc_Control
+// <q11> TC_CoreFunc_IPSR
+// <q12> TC_CoreFunc_APSR
+// <q13> TC_CoreFunc_PSP
+// <q14> TC_CoreFunc_MSP
+// <q15> TC_CoreFunc_PRIMASK
+// <q16> TC_CoreFunc_FAULTMASK
+// <q17> TC_CoreFunc_BASEPRI
+// <q18> TC_CoreFunc_FPSCR
+//
+// <q19> TC_MPU_SetClear
+// <q20> TC_MPU_Load
+#define TC_COREINSTR_NOP_EN         1
+#define TC_COREINSTR_REV_EN         1
+#define TC_COREINSTR_REV16_EN       1
+#define TC_COREINSTR_REVSH_EN       1
+#define TC_COREINSTR_ROR_EN         1
+#define TC_COREINSTR_RBIT_EN        1
+#define TC_COREINSTR_CLZ_EN         1
+#define TC_COREINSTR_SSAT_EN        1
+#define TC_COREINSTR_USAT_EN        1
+
+#define TC_COREFUNC_ENDISIRQ_EN     1
+#define TC_COREFUNC_CONTROL_EN      1
+#define TC_COREFUNC_IPSR_EN         1
+#define TC_COREFUNC_APSR_EN         1
+#define TC_COREFUNC_PSP_EN          1
+#define TC_COREFUNC_MSP_EN          1
+#define TC_COREFUNC_PRIMASK_EN      1
+#define TC_COREFUNC_FAULTMASK_EN    1
+#define TC_COREFUNC_BASEPRI_EN      1
+#define TC_COREFUNC_FPSCR_EN        1
+
+#define TC_MPU_SETCLEAR_EN          1
+#define TC_MPU_LOAD_EN              1
+// </h>
+
+#endif /* __CV_CONFIG_H */
+

CMSIS/CoreValidation/Tests/Cortex-M0plus/AC5/EventRecorderStub.scvd

@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
+
+<component name="EventRecorderStub" version="1.0.0"/>       <!--name and version of the component-->
+  <events>
+  </events>
+
+</component_viewer>

CMSIS/CoreValidation/Tests/Cortex-M0plus/AC5/RTE/Device/ARMCM0P/startup_ARMCM0plus.s

@@ -0,0 +1,242 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM0plus.s
+; * @brief    CMSIS Core Device Startup File for
+; *           ARMCM0plus Device Series
+; * @version  V5.00
+; * @date     02. March 2016
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000C00
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
+                DCD     RTC_IRQHandler            ;  1:  Real Time Clock
+                DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
+                DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
+                DCD     MCIA_IRQHandler           ;  4:  MCIa
+                DCD     MCIB_IRQHandler           ;  5:  MCIb
+                DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
+                DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
+                DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
+                DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
+                DCD     AACI_IRQHandler           ; 10: AACI / AC97
+                DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
+                DCD     ENET_IRQHandler           ; 12: Ethernet
+                DCD     USBDC_IRQHandler          ; 13: USB Device
+                DCD     USBHC_IRQHandler          ; 14: USB Host Controller
+                DCD     CHLCD_IRQHandler          ; 15: Character LCD
+                DCD     FLEXRAY_IRQHandler        ; 16: Flexray
+                DCD     CAN_IRQHandler            ; 17: CAN
+                DCD     LIN_IRQHandler            ; 18: LIN
+                DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
+                DCD     0                         ; 20: Reserved
+                DCD     0                         ; 21: Reserved
+                DCD     0                         ; 22: Reserved
+                DCD     0                         ; 23: Reserved
+                DCD     0                         ; 24: Reserved
+                DCD     0                         ; 25: Reserved
+                DCD     0                         ; 26: Reserved
+                DCD     0                         ; 27: Reserved
+                DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
+                DCD     0                         ; 29: Reserved - CPU FPGA
+                DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
+                DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WDT_IRQHandler            [WEAK]
+                EXPORT  RTC_IRQHandler            [WEAK]
+                EXPORT  TIM0_IRQHandler           [WEAK]
+                EXPORT  TIM2_IRQHandler           [WEAK]
+                EXPORT  MCIA_IRQHandler           [WEAK]
+                EXPORT  MCIB_IRQHandler           [WEAK]
+                EXPORT  UART0_IRQHandler          [WEAK]
+                EXPORT  UART1_IRQHandler          [WEAK]
+                EXPORT  UART2_IRQHandler          [WEAK]
+                EXPORT  UART3_IRQHandler          [WEAK]
+                EXPORT  UART4_IRQHandler          [WEAK]
+                EXPORT  AACI_IRQHandler           [WEAK]
+                EXPORT  CLCD_IRQHandler           [WEAK]
+                EXPORT  ENET_IRQHandler           [WEAK]
+                EXPORT  USBDC_IRQHandler          [WEAK]
+                EXPORT  USBHC_IRQHandler          [WEAK]
+                EXPORT  CHLCD_IRQHandler          [WEAK]
+                EXPORT  FLEXRAY_IRQHandler        [WEAK]
+                EXPORT  CAN_IRQHandler            [WEAK]
+                EXPORT  LIN_IRQHandler            [WEAK]
+                EXPORT  I2C_IRQHandler            [WEAK]
+                EXPORT  CPU_CLCD_IRQHandler       [WEAK]
+                EXPORT  SPI_IRQHandler            [WEAK]
+
+WDT_IRQHandler
+RTC_IRQHandler
+TIM0_IRQHandler
+TIM2_IRQHandler
+MCIA_IRQHandler
+MCIB_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+UART4_IRQHandler
+AACI_IRQHandler
+CLCD_IRQHandler
+ENET_IRQHandler
+USBDC_IRQHandler
+USBHC_IRQHandler
+CHLCD_IRQHandler
+FLEXRAY_IRQHandler
+CAN_IRQHandler
+LIN_IRQHandler
+I2C_IRQHandler
+CPU_CLCD_IRQHandler
+SPI_IRQHandler
+                B       .
+
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap PROC
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+                ENDP
+
+                ALIGN
+
+                ENDIF
+
+
+                END

CMSIS/CoreValidation/Tests/Cortex-M0plus/AC5/RTE/Device/ARMCM0P/system_ARMCM0plus.c

@@ -0,0 +1,68 @@
+/**************************************************************************//**
+ * @file     system_ARMCM0plus.c
+ * @brief    CMSIS Device System Source File for
+ *           ARMCM0plus Device Series
+ * @version  V5.00
+ * @date     07. September 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ARMCM0plus.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+
+#define  SYSTEM_CLOCK    (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+  SystemCoreClock = SYSTEM_CLOCK;
+}

CMSIS/CoreValidation/Tests/Cortex-M0plus/AC5/RTE/_FVP/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'CMSIS_CV' 
+ * Target:  'FVP' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "ARMCM0plus.h"
+
+
+#endif /* RTE_COMPONENTS_H */

CMSIS/CoreValidation/Tests/Cortex-M0plus/AC6/CMSIS_CV.uvprojx

@@ -0,0 +1,507 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>FVP</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pArmCC>6070000::V6.7::.\ARMCLANG</pArmCC>
+      <pCCUsed>6070000::V6.7::.\ARMCLANG</pCCUsed>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>ARMCM0P</Device>
+          <Vendor>ARM</Vendor>
+          <PackID>ARM.CMSIS.5.1.2-dev1</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ESEL ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:ARMCM0P$Device\ARM\ARMCM0plus\Include\ARMCM0plus.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:ARMCM0P$Device\ARM\SVD\ARMCM0P.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\Objects\</OutputDirectory>
+          <OutputName>CMSIS_CV</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\Listings\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>  </SimDllArguments>
+          <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM0+</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> </TargetDllArguments>
+          <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM0+</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>1</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M0+"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>1</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <useXO>0</useXO>
+            <v6Lang>3</v6Lang>
+            <v6LangP>3</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls>-Wno-covered-switch-default</MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>.\,..\..\..\Include</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <uClangAs>0</uClangAs>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>.\,..\..\..\Include</IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange></TextAddressRange>
+            <DataAddressRange></DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc>--entry=Reset_Handler</Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Test</GroupName>
+          <Files>
+            <File>
+              <FileName>cmsis_cv.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\cmsis_cv.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_CoreFunc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_CoreFunc.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_CoreInstr.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_CoreInstr.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Framework.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_Framework.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_MPU_ARMv7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_MPU_ARMv7.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Report.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_Report.c</FilePath>
+            </File>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\main.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Config.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\CV_Config.h</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::CMSIS</GroupName>
+        </Group>
+        <Group>
+          <GroupName>::Device</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components>
+      <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.0.2" condition="ARMv6_7_8-M Device">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0+ CMSIS">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </component>
+    </components>
+    <files>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM0plus\Source\ARM\startup_ARMCM0plus.s" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM0P\startup_ARMCM0plus.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0+ CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM0plus\Source\system_ARMCM0plus.c" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM0P\system_ARMCM0plus.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0+ CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM0\Source\ARM\startup_ARMCM0.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM0\startup_ARMCM0.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM0\Source\system_ARMCM0.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM0\system_ARMCM0.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM3\Source\ARM\startup_ARMCM3.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM3\startup_ARMCM3.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM3\Source\system_ARMCM3.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM3\system_ARMCM3.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM4\Source\ARM\startup_ARMCM4.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM4\startup_ARMCM4.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM4\Source\system_ARMCM4.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM4\system_ARMCM4.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+    </files>
+  </RTE>
+
+</Project>

CMSIS/CoreValidation/Tests/Cortex-M0plus/AC6/CV_Config.h

@@ -0,0 +1,82 @@
+/*-----------------------------------------------------------------------------
+ *      Name:         CV_Config.h 
+ *      Purpose:      CV Config header
+ *----------------------------------------------------------------------------
+ *      Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+#ifndef __CV_CONFIG_H
+#define __CV_CONFIG_H
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+#define RTE_CV_COREINSTR 1
+#define RTE_CV_COREFUNC  1
+#define RTE_CV_MPUFUNC   1
+
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h> Common Test Settings
+// <o> Print Output Format <0=> Plain Text <1=> XML
+// <i> Set the test results output format to plain text or XML
+#ifndef PRINT_XML_REPORT
+#define PRINT_XML_REPORT            1
+#endif
+// <o> Buffer size for assertions results
+// <i> Set the buffer size for assertions results buffer
+#define BUFFER_ASSERTIONS           128U
+// </h>
+
+// <h> Disable Test Cases
+// <i> Uncheck to disable an individual test case
+// <q00> TC_CoreInstr_NOP
+// <q01> TC_CoreInstr_REV
+// <q02> TC_CoreInstr_REV16
+// <q03> TC_CoreInstr_REVSH
+// <q04> TC_CoreInstr_ROR
+// <q05> TC_CoreInstr_RBIT
+// <q06> TC_CoreInstr_CLZ
+// <q07> TC_CoreInstr_SSAT
+// <q08> TC_CoreInstr_USAT
+//
+// <q09> TC_CoreFunc_EnDisIRQ
+// <q10> TC_CoreFunc_Control
+// <q11> TC_CoreFunc_IPSR
+// <q12> TC_CoreFunc_APSR
+// <q13> TC_CoreFunc_PSP
+// <q14> TC_CoreFunc_MSP
+// <q15> TC_CoreFunc_PRIMASK
+// <q16> TC_CoreFunc_FAULTMASK
+// <q17> TC_CoreFunc_BASEPRI
+// <q18> TC_CoreFunc_FPSCR
+//
+// <q19> TC_MPU_SetClear
+// <q20> TC_MPU_Load
+#define TC_COREINSTR_NOP_EN         1
+#define TC_COREINSTR_REV_EN         1
+#define TC_COREINSTR_REV16_EN       1
+#define TC_COREINSTR_REVSH_EN       1
+#define TC_COREINSTR_ROR_EN         1
+#define TC_COREINSTR_RBIT_EN        1
+#define TC_COREINSTR_CLZ_EN         1
+#define TC_COREINSTR_SSAT_EN        1
+#define TC_COREINSTR_USAT_EN        1
+
+#define TC_COREFUNC_ENDISIRQ_EN     1
+#define TC_COREFUNC_CONTROL_EN      1
+#define TC_COREFUNC_IPSR_EN         1
+#define TC_COREFUNC_APSR_EN         1
+#define TC_COREFUNC_PSP_EN          1
+#define TC_COREFUNC_MSP_EN          1
+#define TC_COREFUNC_PRIMASK_EN      1
+#define TC_COREFUNC_FAULTMASK_EN    1
+#define TC_COREFUNC_BASEPRI_EN      1
+#define TC_COREFUNC_FPSCR_EN        1
+
+#define TC_MPU_SETCLEAR_EN          1
+#define TC_MPU_LOAD_EN              1
+// </h>
+
+#endif /* __CV_CONFIG_H */
+

CMSIS/CoreValidation/Tests/Cortex-M0plus/AC6/EventRecorderStub.scvd

@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
+
+<component name="EventRecorderStub" version="1.0.0"/>       <!--name and version of the component-->
+  <events>
+  </events>
+
+</component_viewer>

CMSIS/CoreValidation/Tests/Cortex-M0plus/AC6/RTE/Device/ARMCM0P/startup_ARMCM0plus.s

@@ -0,0 +1,242 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM0plus.s
+; * @brief    CMSIS Core Device Startup File for
+; *           ARMCM0plus Device Series
+; * @version  V5.00
+; * @date     02. March 2016
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000C00
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
+                DCD     RTC_IRQHandler            ;  1:  Real Time Clock
+                DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
+                DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
+                DCD     MCIA_IRQHandler           ;  4:  MCIa
+                DCD     MCIB_IRQHandler           ;  5:  MCIb
+                DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
+                DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
+                DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
+                DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
+                DCD     AACI_IRQHandler           ; 10: AACI / AC97
+                DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
+                DCD     ENET_IRQHandler           ; 12: Ethernet
+                DCD     USBDC_IRQHandler          ; 13: USB Device
+                DCD     USBHC_IRQHandler          ; 14: USB Host Controller
+                DCD     CHLCD_IRQHandler          ; 15: Character LCD
+                DCD     FLEXRAY_IRQHandler        ; 16: Flexray
+                DCD     CAN_IRQHandler            ; 17: CAN
+                DCD     LIN_IRQHandler            ; 18: LIN
+                DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
+                DCD     0                         ; 20: Reserved
+                DCD     0                         ; 21: Reserved
+                DCD     0                         ; 22: Reserved
+                DCD     0                         ; 23: Reserved
+                DCD     0                         ; 24: Reserved
+                DCD     0                         ; 25: Reserved
+                DCD     0                         ; 26: Reserved
+                DCD     0                         ; 27: Reserved
+                DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
+                DCD     0                         ; 29: Reserved - CPU FPGA
+                DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
+                DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WDT_IRQHandler            [WEAK]
+                EXPORT  RTC_IRQHandler            [WEAK]
+                EXPORT  TIM0_IRQHandler           [WEAK]
+                EXPORT  TIM2_IRQHandler           [WEAK]
+                EXPORT  MCIA_IRQHandler           [WEAK]
+                EXPORT  MCIB_IRQHandler           [WEAK]
+                EXPORT  UART0_IRQHandler          [WEAK]
+                EXPORT  UART1_IRQHandler          [WEAK]
+                EXPORT  UART2_IRQHandler          [WEAK]
+                EXPORT  UART3_IRQHandler          [WEAK]
+                EXPORT  UART4_IRQHandler          [WEAK]
+                EXPORT  AACI_IRQHandler           [WEAK]
+                EXPORT  CLCD_IRQHandler           [WEAK]
+                EXPORT  ENET_IRQHandler           [WEAK]
+                EXPORT  USBDC_IRQHandler          [WEAK]
+                EXPORT  USBHC_IRQHandler          [WEAK]
+                EXPORT  CHLCD_IRQHandler          [WEAK]
+                EXPORT  FLEXRAY_IRQHandler        [WEAK]
+                EXPORT  CAN_IRQHandler            [WEAK]
+                EXPORT  LIN_IRQHandler            [WEAK]
+                EXPORT  I2C_IRQHandler            [WEAK]
+                EXPORT  CPU_CLCD_IRQHandler       [WEAK]
+                EXPORT  SPI_IRQHandler            [WEAK]
+
+WDT_IRQHandler
+RTC_IRQHandler
+TIM0_IRQHandler
+TIM2_IRQHandler
+MCIA_IRQHandler
+MCIB_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+UART4_IRQHandler
+AACI_IRQHandler
+CLCD_IRQHandler
+ENET_IRQHandler
+USBDC_IRQHandler
+USBHC_IRQHandler
+CHLCD_IRQHandler
+FLEXRAY_IRQHandler
+CAN_IRQHandler
+LIN_IRQHandler
+I2C_IRQHandler
+CPU_CLCD_IRQHandler
+SPI_IRQHandler
+                B       .
+
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap PROC
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+                ENDP
+
+                ALIGN
+
+                ENDIF
+
+
+                END

CMSIS/CoreValidation/Tests/Cortex-M0plus/AC6/RTE/Device/ARMCM0P/system_ARMCM0plus.c

@@ -0,0 +1,68 @@
+/**************************************************************************//**
+ * @file     system_ARMCM0plus.c
+ * @brief    CMSIS Device System Source File for
+ *           ARMCM0plus Device Series
+ * @version  V5.00
+ * @date     07. September 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ARMCM0plus.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+
+#define  SYSTEM_CLOCK    (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+  SystemCoreClock = SYSTEM_CLOCK;
+}

CMSIS/CoreValidation/Tests/Cortex-M0plus/AC6/RTE/_FVP/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'CMSIS_CV' 
+ * Target:  'FVP' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "ARMCM0plus.h"
+
+
+#endif /* RTE_COMPONENTS_H */

CMSIS/CoreValidation/Tests/Cortex-M0plus/GCC/CMSIS_CV.uvprojx

@@ -0,0 +1,434 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>FVP</TargetName>
+      <ToolsetNumber>0x3</ToolsetNumber>
+      <ToolsetName>ARM-GNU</ToolsetName>
+      <pArmCC>6070000::V6.7::.\ARMCLANG</pArmCC>
+      <pCCUsed>6070000::V6.7::.\ARMCLANG</pCCUsed>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>ARMCM0P</Device>
+          <Vendor>ARM</Vendor>
+          <PackID>ARM.CMSIS.5.1.2-dev1</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ESEL ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:ARMCM0P$Device\ARM\ARMCM0plus\Include\ARMCM0plus.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:ARMCM0P$Device\ARM\SVD\ARMCM0P.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\Objects\</OutputDirectory>
+          <OutputName>CMSIS_CV</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\Listings\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>  </SimDllArguments>
+          <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM0+</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> </TargetDllArguments>
+          <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM0+</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArm>
+          <ArmMisc>
+            <asLst>1</asLst>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>1</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <GCPUTYP>"Cortex-M0+"</GCPUTYP>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <IRAM2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </IRAM2>
+              <IROM2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </IROM2>
+            </OnChipMemories>
+          </ArmMisc>
+          <Carm>
+            <arpcs>1</arpcs>
+            <stkchk>0</stkchk>
+            <reentr>0</reentr>
+            <interw>1</interw>
+            <bigend>0</bigend>
+            <Strict>0</Strict>
+            <Optim>1</Optim>
+            <wLevel>3</wLevel>
+            <uThumb>1</uThumb>
+            <VariousControls>
+              <MiscControls>-mfloat-abi=soft -Wall -Wextra -Wstrict-prototypes -Wshadow</MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>.;..\..\..\Include</IncludePath>
+            </VariousControls>
+          </Carm>
+          <Aarm>
+            <bBE>0</bBE>
+            <interw>1</interw>
+            <VariousControls>
+              <MiscControls>-mfloat-abi=soft -Wall</MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>.;..\..\..\Include</IncludePath>
+            </VariousControls>
+          </Aarm>
+          <LDarm>
+            <umfTarg>1</umfTarg>
+            <enaGarb>0</enaGarb>
+            <noStart>0</noStart>
+            <noStLib>0</noStLib>
+            <uMathLib>0</uMathLib>
+            <TextAddressRange></TextAddressRange>
+            <DataAddressRange></DataAddressRange>
+            <BSSAddressRange></BSSAddressRange>
+            <IncludeLibs></IncludeLibs>
+            <IncludeDir></IncludeDir>
+            <Misc>-mfloat-abi=soft --specs=rdimon.specs</Misc>
+            <ScatterFile>.\RTE\Device\ARMCM0P\gcc_arm.ld</ScatterFile>
+          </LDarm>
+        </TargetArm>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Test</GroupName>
+          <Files>
+            <File>
+              <FileName>cmsis_cv.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\cmsis_cv.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_CoreFunc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_CoreFunc.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_CoreInstr.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_CoreInstr.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Framework.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_Framework.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_MPU_ARMv7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_MPU_ARMv7.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Report.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_Report.c</FilePath>
+            </File>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\main.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Config.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\CV_Config.h</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::CMSIS</GroupName>
+        </Group>
+        <Group>
+          <GroupName>::Device</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components>
+      <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.0.2" condition="ARMv6_7_8-M Device">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0+ CMSIS GCC">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </component>
+    </components>
+    <files>
+      <file attr="config" category="linkerScript" condition="GCC" name="Device\ARM\ARMCM0plus\Source\GCC\gcc_arm.ld" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM0P\gcc_arm.ld</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0+ CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="sourceC" condition="GCC" name="Device\ARM\ARMCM0plus\Source\GCC\startup_ARMCM0plus.c" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM0P\startup_ARMCM0plus.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0+ CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM0plus\Source\system_ARMCM0plus.c" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM0P\system_ARMCM0plus.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0+ CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM0\Source\ARM\startup_ARMCM0.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM0\startup_ARMCM0.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM0\Source\system_ARMCM0.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM0\system_ARMCM0.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="linkerScript" condition="GCC" name="Device\ARM\ARMCM3\Source\GCC\gcc_arm.ld" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM3\gcc_arm.ld</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceAsm" condition="GCC" name="Device\ARM\ARMCM3\Source\GCC\startup_ARMCM3.S" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM3\startup_ARMCM3.S</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" condition="GCC" name="Device\ARM\ARMCM3\Source\GCC\startup_ARMCM3.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM3\startup_ARMCM3.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM3\Source\system_ARMCM3.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM3\system_ARMCM3.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="linkerScript" condition="GCC" name="Device\ARM\ARMCM4\Source\GCC\gcc_arm.ld" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM4\gcc_arm.ld</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" condition="GCC" name="Device\ARM\ARMCM4\Source\GCC\startup_ARMCM4.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM4\startup_ARMCM4.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM4\Source\ARM\startup_ARMCM4.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM4\startup_ARMCM4.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM4\Source\system_ARMCM4.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM4\system_ARMCM4.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+    </files>
+  </RTE>
+
+</Project>

CMSIS/CoreValidation/Tests/Cortex-M0plus/GCC/CV_Config.h

@@ -0,0 +1,82 @@
+/*-----------------------------------------------------------------------------
+ *      Name:         CV_Config.h 
+ *      Purpose:      CV Config header
+ *----------------------------------------------------------------------------
+ *      Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+#ifndef __CV_CONFIG_H
+#define __CV_CONFIG_H
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+#define RTE_CV_COREINSTR 1
+#define RTE_CV_COREFUNC  1
+#define RTE_CV_MPUFUNC   1
+
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h> Common Test Settings
+// <o> Print Output Format <0=> Plain Text <1=> XML
+// <i> Set the test results output format to plain text or XML
+#ifndef PRINT_XML_REPORT
+#define PRINT_XML_REPORT            1
+#endif
+// <o> Buffer size for assertions results
+// <i> Set the buffer size for assertions results buffer
+#define BUFFER_ASSERTIONS           128U
+// </h>
+
+// <h> Disable Test Cases
+// <i> Uncheck to disable an individual test case
+// <q00> TC_CoreInstr_NOP
+// <q01> TC_CoreInstr_REV
+// <q02> TC_CoreInstr_REV16
+// <q03> TC_CoreInstr_REVSH
+// <q04> TC_CoreInstr_ROR
+// <q05> TC_CoreInstr_RBIT
+// <q06> TC_CoreInstr_CLZ
+// <q07> TC_CoreInstr_SSAT
+// <q08> TC_CoreInstr_USAT
+//
+// <q09> TC_CoreFunc_EnDisIRQ
+// <q10> TC_CoreFunc_Control
+// <q11> TC_CoreFunc_IPSR
+// <q12> TC_CoreFunc_APSR
+// <q13> TC_CoreFunc_PSP
+// <q14> TC_CoreFunc_MSP
+// <q15> TC_CoreFunc_PRIMASK
+// <q16> TC_CoreFunc_FAULTMASK
+// <q17> TC_CoreFunc_BASEPRI
+// <q18> TC_CoreFunc_FPSCR
+//
+// <q19> TC_MPU_SetClear
+// <q20> TC_MPU_Load
+#define TC_COREINSTR_NOP_EN         1
+#define TC_COREINSTR_REV_EN         1
+#define TC_COREINSTR_REV16_EN       1
+#define TC_COREINSTR_REVSH_EN       1
+#define TC_COREINSTR_ROR_EN         1
+#define TC_COREINSTR_RBIT_EN        1
+#define TC_COREINSTR_CLZ_EN         1
+#define TC_COREINSTR_SSAT_EN        1
+#define TC_COREINSTR_USAT_EN        1
+
+#define TC_COREFUNC_ENDISIRQ_EN     1
+#define TC_COREFUNC_CONTROL_EN      1
+#define TC_COREFUNC_IPSR_EN         1
+#define TC_COREFUNC_APSR_EN         1
+#define TC_COREFUNC_PSP_EN          1
+#define TC_COREFUNC_MSP_EN          1
+#define TC_COREFUNC_PRIMASK_EN      1
+#define TC_COREFUNC_FAULTMASK_EN    1
+#define TC_COREFUNC_BASEPRI_EN      1
+#define TC_COREFUNC_FPSCR_EN        1
+
+#define TC_MPU_SETCLEAR_EN          1
+#define TC_MPU_LOAD_EN              1
+// </h>
+
+#endif /* __CV_CONFIG_H */
+

CMSIS/CoreValidation/Tests/Cortex-M0plus/GCC/EventRecorderStub.scvd

@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
+
+<component name="EventRecorderStub" version="1.0.0"/>       <!--name and version of the component-->
+  <events>
+  </events>
+
+</component_viewer>

CMSIS/CoreValidation/Tests/Cortex-M0plus/GCC/RTE/Device/ARMCM0P/gcc_arm.ld

@@ -0,0 +1,196 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+  FLASH (rx)  : ORIGIN = 0x00000000, LENGTH = 512K
+  RAM   (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapBase
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __Vectors_End
+ *   __Vectors_Size
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+	.text :
+	{
+		KEEP(*(.vectors))
+		__Vectors_End = .;
+		__Vectors_Size = __Vectors_End - __Vectors;
+		__end__ = .;
+
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+	.ARM.extab :
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	/* To copy multiple ROM to RAM sections,
+	 * uncomment .copy.table section and,
+	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.copy.table :
+	{
+		. = ALIGN(4);
+		__copy_table_start__ = .;
+		LONG (__etext)
+		LONG (__data_start__)
+		LONG (__data_end__ - __data_start__)
+		LONG (__etext2)
+		LONG (__data2_start__)
+		LONG (__data2_end__ - __data2_start__)
+		__copy_table_end__ = .;
+	} > FLASH
+	*/
+
+	/* To clear multiple BSS sections,
+	 * uncomment .zero.table section and,
+	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.zero.table :
+	{
+		. = ALIGN(4);
+		__zero_table_start__ = .;
+		LONG (__bss_start__)
+		LONG (__bss_end__ - __bss_start__)
+		LONG (__bss2_start__)
+		LONG (__bss2_end__ - __bss2_start__)
+		__zero_table_end__ = .;
+	} > FLASH
+	*/
+
+	__etext = .;
+
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		KEEP(*(.jcr*))
+		. = ALIGN(4);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > RAM
+
+	.heap (COPY):
+	{
+		__HeapBase = .;
+		__end__ = .;
+		end = __end__;
+		KEEP(*(.heap*))
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (COPY):
+	{
+		KEEP(*(.stack*))
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM);
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}

CMSIS/CoreValidation/Tests/Cortex-M0plus/GCC/RTE/Device/ARMCM0P/startup_ARMCM0plus.c

@@ -0,0 +1,291 @@
+/**************************************************************************//**
+ * @file     startup_ARMCM0plus.s
+ * @brief    CMSIS Core Device Startup File for
+ *           ARMCM0plus Device Series
+ * @version  V5.00
+ * @date     26. March 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdint.h>
+
+
+/*----------------------------------------------------------------------------
+  Linker generated Symbols
+ *----------------------------------------------------------------------------*/
+extern uint32_t __etext;
+extern uint32_t __data_start__;
+extern uint32_t __data_end__;
+extern uint32_t __copy_table_start__;
+extern uint32_t __copy_table_end__;
+extern uint32_t __zero_table_start__;
+extern uint32_t __zero_table_end__;
+extern uint32_t __bss_start__;
+extern uint32_t __bss_end__;
+extern uint32_t __StackTop;
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler Function Prototype
+ *----------------------------------------------------------------------------*/
+typedef void( *pFunc )( void );
+
+
+/*----------------------------------------------------------------------------
+  External References
+ *----------------------------------------------------------------------------*/
+#ifndef __START
+extern void  _start(void) __attribute__((noreturn));    /* PreeMain (C library entry point) */
+#else
+extern int  __START(void) __attribute__((noreturn));    /* main entry point */
+#endif
+
+#ifndef __NO_SYSTEM_INIT
+extern void SystemInit (void);            /* CMSIS System Initialization      */
+#endif
+
+
+/*----------------------------------------------------------------------------
+  Internal References
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void);                          /* Default empty handler */
+void Reset_Handler(void);                            /* Reset Handler */
+
+
+/*----------------------------------------------------------------------------
+  User Initial Stack & Heap
+ *----------------------------------------------------------------------------*/
+#ifndef __STACK_SIZE
+  #define	__STACK_SIZE  0x00000400
+#endif
+static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack")));
+
+#ifndef __HEAP_SIZE
+  #define	__HEAP_SIZE   0x00000C00
+#endif
+#if __HEAP_SIZE > 0
+static uint8_t heap[__HEAP_SIZE]   __attribute__ ((aligned(8), used, section(".heap")));
+#endif
+
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Cortex-M0+ Processor Exceptions */
+void NMI_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/* ARMCM0plus Specific Interrupts */
+void WDT_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void RTC_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void TIM0_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void TIM2_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void MCIA_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void MCIB_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART0_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART1_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART2_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART4_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void AACI_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void CLCD_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void ENET_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void USBDC_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void USBHC_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void CHLCD_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void FLEXRAY_IRQHandler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void CAN_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void LIN_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void I2C_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void CPU_CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART3_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void SPI_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = {
+  /* Cortex-M0+ Exceptions Handler */
+  (pFunc)((uint32_t)&__StackTop),           /*      Initial Stack Pointer     */
+  Reset_Handler,                            /*      Reset Handler             */
+  NMI_Handler,                              /*      NMI Handler               */
+  HardFault_Handler,                        /*      Hard Fault Handler        */
+  0,                                        /*      Reserved                  */
+  0,                                        /*      Reserved                  */
+  0,                                        /*      Reserved                  */
+  0,                                        /*      Reserved                  */
+  0,                                        /*      Reserved                  */
+  0,                                        /*      Reserved                  */
+  0,                                        /*      Reserved                  */
+  SVC_Handler,                              /*      SVCall Handler            */
+  0,                                        /*      Reserved                  */
+  0,                                        /*      Reserved                  */
+  PendSV_Handler,                           /*      PendSV Handler            */
+  SysTick_Handler,                          /*      SysTick Handler           */
+
+  /* External interrupts */
+  WDT_IRQHandler,                           /*  0:  Watchdog Timer            */
+  RTC_IRQHandler,                           /*  1:  Real Time Clock           */
+  TIM0_IRQHandler,                          /*  2:  Timer0 / Timer1           */
+  TIM2_IRQHandler,                          /*  3:  Timer2 / Timer3           */
+  MCIA_IRQHandler,                          /*  4:  MCIa                      */
+  MCIB_IRQHandler,                          /*  5:  MCIb                      */
+  UART0_IRQHandler,                         /*  6:  UART0 - DUT FPGA          */
+  UART1_IRQHandler,                         /*  7:  UART1 - DUT FPGA          */
+  UART2_IRQHandler,                         /*  8:  UART2 - DUT FPGA          */
+  UART4_IRQHandler,                         /*  9:  UART4 - not connected     */
+  AACI_IRQHandler,                          /* 10: AACI / AC97                */
+  CLCD_IRQHandler,                          /* 11: CLCD Combined Interrupt    */
+  ENET_IRQHandler,                          /* 12: Ethernet                   */
+  USBDC_IRQHandler,                         /* 13: USB Device                 */
+  USBHC_IRQHandler,                         /* 14: USB Host Controller        */
+  CHLCD_IRQHandler,                         /* 15: Character LCD              */
+  FLEXRAY_IRQHandler,                       /* 16: Flexray                    */
+  CAN_IRQHandler,                           /* 17: CAN                        */
+  LIN_IRQHandler,                           /* 18: LIN                        */
+  I2C_IRQHandler,                           /* 19: I2C ADC/DAC                */
+  0,                                        /* 20: Reserved                   */
+  0,                                        /* 21: Reserved                   */
+  0,                                        /* 22: Reserved                   */
+  0,                                        /* 23: Reserved                   */
+  0,                                        /* 24: Reserved                   */
+  0,                                        /* 25: Reserved                   */
+  0,                                        /* 26: Reserved                   */
+  0,                                        /* 27: Reserved                   */
+  CPU_CLCD_IRQHandler,                      /* 28: Reserved - CPU FPGA CLCD   */
+  0,                                        /* 29: Reserved - CPU FPGA        */
+  UART3_IRQHandler,                         /* 30: UART3    - CPU FPGA        */
+  SPI_IRQHandler                            /* 31: SPI Touchscreen - CPU FPGA */
+};
+
+
+/*----------------------------------------------------------------------------
+  Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+  uint32_t *pSrc, *pDest;
+  uint32_t *pTable __attribute__((unused));
+
+/*  Firstly it copies data from read only memory to RAM. There are two schemes
+ *  to copy. One can copy more than one sections. Another can only copy
+ *  one section.  The former scheme needs more instructions and read-only
+ *  data to implement than the latter.
+ *  Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.  */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/*  Multiple sections scheme.
+ *
+ *  Between symbol address __copy_table_start__ and __copy_table_end__,
+ *  there are array of triplets, each of which specify:
+ *    offset 0: LMA of start of a section to copy from
+ *    offset 4: VMA of start of a section to copy to
+ *    offset 8: size of the section to copy. Must be multiply of 4
+ *
+ *  All addresses must be aligned to 4 bytes boundary.
+ */
+  pTable = &__copy_table_start__;
+
+  for (; pTable < &__copy_table_end__; pTable = pTable + 3) {
+		pSrc  = (uint32_t*)*(pTable + 0);
+		pDest = (uint32_t*)*(pTable + 1);
+		for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
+      *pDest++ = *pSrc++;
+		}
+	}
+#else
+/*  Single section scheme.
+ *
+ *  The ranges of copy from/to are specified by following symbols
+ *    __etext: LMA of start of the section to copy from. Usually end of text
+ *    __data_start__: VMA of start of the section to copy to
+ *    __data_end__: VMA of end of the section to copy to
+ *
+ *  All addresses must be aligned to 4 bytes boundary.
+ */
+  pSrc  = &__etext;
+  pDest = &__data_start__;
+
+  for ( ; pDest < &__data_end__ ; ) {
+    *pDest++ = *pSrc++;
+  }
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/*  This part of work usually is done in C library startup code. Otherwise,
+ *  define this macro to enable it in this startup.
+ *
+ *  There are two schemes too. One can clear multiple BSS sections. Another
+ *  can only clear one section. The former is more size expensive than the
+ *  latter.
+ *
+ *  Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ *  Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/*  Multiple sections scheme.
+ *
+ *  Between symbol address __copy_table_start__ and __copy_table_end__,
+ *  there are array of tuples specifying:
+ *    offset 0: Start of a BSS section
+ *    offset 4: Size of this BSS section. Must be multiply of 4
+ */
+  pTable = &__zero_table_start__;
+
+  for (; pTable < &__zero_table_end__; pTable = pTable + 2) {
+		pDest = (uint32_t*)*(pTable + 0);
+		for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
+      *pDest++ = 0;
+		}
+	}
+#elif defined (__STARTUP_CLEAR_BSS)
+/*  Single BSS section scheme.
+ *
+ *  The BSS section is specified by following symbols
+ *    __bss_start__: start of the BSS section.
+ *    __bss_end__: end of the BSS section.
+ *
+ *  Both addresses must be aligned to 4 bytes boundary.
+ */
+  pDest = &__bss_start__;
+
+  for ( ; pDest < &__bss_end__ ; ) {
+    *pDest++ = 0UL;
+  }
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+#ifndef __NO_SYSTEM_INIT
+	SystemInit();
+#endif
+
+#ifndef __START
+#define __START _start
+#endif
+	__START();
+
+}
+
+
+/*----------------------------------------------------------------------------
+  Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+
+	while(1);
+}

CMSIS/CoreValidation/Tests/Cortex-M0plus/GCC/RTE/Device/ARMCM0P/system_ARMCM0plus.c

@@ -0,0 +1,68 @@
+/**************************************************************************//**
+ * @file     system_ARMCM0plus.c
+ * @brief    CMSIS Device System Source File for
+ *           ARMCM0plus Device Series
+ * @version  V5.00
+ * @date     07. September 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ARMCM0plus.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+
+#define  SYSTEM_CLOCK    (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+  SystemCoreClock = SYSTEM_CLOCK;
+}

CMSIS/CoreValidation/Tests/Cortex-M0plus/GCC/RTE/_FVP/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'CMSIS_CV' 
+ * Target:  'FVP' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "ARMCM0plus.h"
+
+
+#endif /* RTE_COMPONENTS_H */

CMSIS/CoreValidation/Tests/Cortex-M4/GCC/CMSIS_CV.uvprojx

@@ -267,7 +267,7 @@
             <IncludeLibs></IncludeLibs>
             <IncludeDir></IncludeDir>
             <Misc>-mfloat-abi=soft --specs=rdimon.specs</Misc>
-            <ScatterFile>.\RTE\Device\ARMCM3\gcc_arm.ld</ScatterFile>
+            <ScatterFile>.\RTE\Device\ARMCM4\gcc_arm.ld</ScatterFile>
           </LDarm>
         </TargetArm>
       </TargetOption>

CMSIS/CoreValidation/Tests/Cortex-M4FP/AC5/CMSIS_CV.uvprojx

@@ -0,0 +1,507 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>FVP</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pArmCC>5060528::V5.06 update 5 (build 528)::ARMCC</pArmCC>
+      <pCCUsed>5060528::V5.06 update 5 (build 528)::ARMCC</pCCUsed>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>ARMCM4_FP</Device>
+          <Vendor>ARM</Vendor>
+          <PackID>ARM.CMSIS.5.1.2-dev1</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
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+          </TargetStatus>
+          <OutputDirectory>.\Objects\</OutputDirectory>
+          <OutputName>CMSIS_CV</OutputName>
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+          </BeforeCompile>
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+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>  -MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> -MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
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+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
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+        <TargetArmAds>
+          <ArmAdsMisc>
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+            <asAsm>1</asAsm>
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+              </OCR_RVCT10>
+            </OnChipMemories>
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+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>.\,..\..\..\Include</IncludePath>
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+          </Cads>
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+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc>--entry=Reset_Handler</Misc>
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+            <DisabledWarnings></DisabledWarnings>
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+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Test</GroupName>
+          <Files>
+            <File>
+              <FileName>cmsis_cv.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\cmsis_cv.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_CoreFunc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_CoreFunc.c</FilePath>
+            </File>
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+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_CoreInstr.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Framework.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_Framework.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_MPU_ARMv7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_MPU_ARMv7.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Report.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_Report.c</FilePath>
+            </File>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\main.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Config.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\CV_Config.h</FilePath>
+            </File>
+          </Files>
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+        <Group>
+          <GroupName>::CMSIS</GroupName>
+        </Group>
+        <Group>
+          <GroupName>::Device</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components>
+      <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.0.2" condition="ARMv6_7_8-M Device">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </component>
+    </components>
+    <files>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM0\Source\ARM\startup_ARMCM0.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM0\startup_ARMCM0.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM0\Source\system_ARMCM0.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM0\system_ARMCM0.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM3\Source\ARM\startup_ARMCM3.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM3\startup_ARMCM3.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM3\Source\system_ARMCM3.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM3\system_ARMCM3.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM4\Source\ARM\startup_ARMCM4.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM4\startup_ARMCM4.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM4\Source\system_ARMCM4.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM4\system_ARMCM4.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM4\Source\ARM\startup_ARMCM4.s" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM4_FP\startup_ARMCM4.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM4\Source\system_ARMCM4.c" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM4_FP\system_ARMCM4.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </file>
+    </files>
+  </RTE>
+
+</Project>

CMSIS/CoreValidation/Tests/Cortex-M4FP/AC5/CV_Config.h

@@ -0,0 +1,82 @@
+/*-----------------------------------------------------------------------------
+ *      Name:         CV_Config.h 
+ *      Purpose:      CV Config header
+ *----------------------------------------------------------------------------
+ *      Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+#ifndef __CV_CONFIG_H
+#define __CV_CONFIG_H
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+#define RTE_CV_COREINSTR 1
+#define RTE_CV_COREFUNC  1
+#define RTE_CV_MPUFUNC   1
+
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h> Common Test Settings
+// <o> Print Output Format <0=> Plain Text <1=> XML
+// <i> Set the test results output format to plain text or XML
+#ifndef PRINT_XML_REPORT
+#define PRINT_XML_REPORT            1
+#endif
+// <o> Buffer size for assertions results
+// <i> Set the buffer size for assertions results buffer
+#define BUFFER_ASSERTIONS           128U
+// </h>
+
+// <h> Disable Test Cases
+// <i> Uncheck to disable an individual test case
+// <q00> TC_CoreInstr_NOP
+// <q01> TC_CoreInstr_REV
+// <q02> TC_CoreInstr_REV16
+// <q03> TC_CoreInstr_REVSH
+// <q04> TC_CoreInstr_ROR
+// <q05> TC_CoreInstr_RBIT
+// <q06> TC_CoreInstr_CLZ
+// <q07> TC_CoreInstr_SSAT
+// <q08> TC_CoreInstr_USAT
+//
+// <q09> TC_CoreFunc_EnDisIRQ
+// <q10> TC_CoreFunc_Control
+// <q11> TC_CoreFunc_IPSR
+// <q12> TC_CoreFunc_APSR
+// <q13> TC_CoreFunc_PSP
+// <q14> TC_CoreFunc_MSP
+// <q15> TC_CoreFunc_PRIMASK
+// <q16> TC_CoreFunc_FAULTMASK
+// <q17> TC_CoreFunc_BASEPRI
+// <q18> TC_CoreFunc_FPSCR
+//
+// <q19> TC_MPU_SetClear
+// <q20> TC_MPU_Load
+#define TC_COREINSTR_NOP_EN         1
+#define TC_COREINSTR_REV_EN         1
+#define TC_COREINSTR_REV16_EN       1
+#define TC_COREINSTR_REVSH_EN       1
+#define TC_COREINSTR_ROR_EN         1
+#define TC_COREINSTR_RBIT_EN        1
+#define TC_COREINSTR_CLZ_EN         1
+#define TC_COREINSTR_SSAT_EN        1
+#define TC_COREINSTR_USAT_EN        1
+
+#define TC_COREFUNC_ENDISIRQ_EN     1
+#define TC_COREFUNC_CONTROL_EN      1
+#define TC_COREFUNC_IPSR_EN         1
+#define TC_COREFUNC_APSR_EN         1
+#define TC_COREFUNC_PSP_EN          1
+#define TC_COREFUNC_MSP_EN          1
+#define TC_COREFUNC_PRIMASK_EN      1
+#define TC_COREFUNC_FAULTMASK_EN    1
+#define TC_COREFUNC_BASEPRI_EN      1
+#define TC_COREFUNC_FPSCR_EN        1
+
+#define TC_MPU_SETCLEAR_EN          1
+#define TC_MPU_LOAD_EN              1
+// </h>
+
+#endif /* __CV_CONFIG_H */
+

CMSIS/CoreValidation/Tests/Cortex-M4FP/AC5/EventRecorderStub.scvd

@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
+
+<component name="EventRecorderStub" version="1.0.0"/>       <!--name and version of the component-->
+  <events>
+  </events>
+
+</component_viewer>

CMSIS/CoreValidation/Tests/Cortex-M4FP/AC5/RTE/Device/ARMCM4_FP/startup_ARMCM4.s

@@ -0,0 +1,262 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM4.s
+; * @brief    CMSIS Core Device Startup File for
+; *           ARMCM4 Device Series
+; * @version  V5.00
+; * @date     02. March 2016
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000C00
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
+                DCD     RTC_IRQHandler            ;  1:  Real Time Clock
+                DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
+                DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
+                DCD     MCIA_IRQHandler           ;  4:  MCIa
+                DCD     MCIB_IRQHandler           ;  5:  MCIb
+                DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
+                DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
+                DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
+                DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
+                DCD     AACI_IRQHandler           ; 10: AACI / AC97
+                DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
+                DCD     ENET_IRQHandler           ; 12: Ethernet
+                DCD     USBDC_IRQHandler          ; 13: USB Device
+                DCD     USBHC_IRQHandler          ; 14: USB Host Controller
+                DCD     CHLCD_IRQHandler          ; 15: Character LCD
+                DCD     FLEXRAY_IRQHandler        ; 16: Flexray
+                DCD     CAN_IRQHandler            ; 17: CAN
+                DCD     LIN_IRQHandler            ; 18: LIN
+                DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
+                DCD     0                         ; 20: Reserved
+                DCD     0                         ; 21: Reserved
+                DCD     0                         ; 22: Reserved
+                DCD     0                         ; 23: Reserved
+                DCD     0                         ; 24: Reserved
+                DCD     0                         ; 25: Reserved
+                DCD     0                         ; 26: Reserved
+                DCD     0                         ; 27: Reserved
+                DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
+                DCD     0                         ; 29: Reserved - CPU FPGA
+                DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
+                DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WDT_IRQHandler            [WEAK]
+                EXPORT  RTC_IRQHandler            [WEAK]
+                EXPORT  TIM0_IRQHandler           [WEAK]
+                EXPORT  TIM2_IRQHandler           [WEAK]
+                EXPORT  MCIA_IRQHandler           [WEAK]
+                EXPORT  MCIB_IRQHandler           [WEAK]
+                EXPORT  UART0_IRQHandler          [WEAK]
+                EXPORT  UART1_IRQHandler          [WEAK]
+                EXPORT  UART2_IRQHandler          [WEAK]
+                EXPORT  UART3_IRQHandler          [WEAK]
+                EXPORT  UART4_IRQHandler          [WEAK]
+                EXPORT  AACI_IRQHandler           [WEAK]
+                EXPORT  CLCD_IRQHandler           [WEAK]
+                EXPORT  ENET_IRQHandler           [WEAK]
+                EXPORT  USBDC_IRQHandler          [WEAK]
+                EXPORT  USBHC_IRQHandler          [WEAK]
+                EXPORT  CHLCD_IRQHandler          [WEAK]
+                EXPORT  FLEXRAY_IRQHandler        [WEAK]
+                EXPORT  CAN_IRQHandler            [WEAK]
+                EXPORT  LIN_IRQHandler            [WEAK]
+                EXPORT  I2C_IRQHandler            [WEAK]
+                EXPORT  CPU_CLCD_IRQHandler       [WEAK]
+                EXPORT  SPI_IRQHandler            [WEAK]
+
+WDT_IRQHandler
+RTC_IRQHandler
+TIM0_IRQHandler
+TIM2_IRQHandler
+MCIA_IRQHandler
+MCIB_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+UART4_IRQHandler
+AACI_IRQHandler
+CLCD_IRQHandler
+ENET_IRQHandler
+USBDC_IRQHandler
+USBHC_IRQHandler
+CHLCD_IRQHandler
+FLEXRAY_IRQHandler
+CAN_IRQHandler
+LIN_IRQHandler
+I2C_IRQHandler
+CPU_CLCD_IRQHandler
+SPI_IRQHandler
+                B       .
+
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap PROC
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+                ENDP
+
+                ALIGN
+
+                ENDIF
+
+
+                END

CMSIS/CoreValidation/Tests/Cortex-M4FP/AC5/RTE/Device/ARMCM4_FP/system_ARMCM4.c

@@ -0,0 +1,83 @@
+/**************************************************************************//**
+ * @file     system_ARMCM4.c
+ * @brief    CMSIS Device System Source File for
+ *           ARMCM4 Device Series
+ * @version  V5.00
+ * @date     07. September 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM4)
+  #include "ARMCM4.h"
+#elif defined (ARMCM4_FP)
+  #include "ARMCM4_FP.h"
+#else
+  #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+
+#define  SYSTEM_CLOCK    (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+#if defined (__FPU_USED) && (__FPU_USED == 1U)
+  SCB->CPACR |= ((3U << 10U*2U) |           /* set CP10 Full Access */
+                 (3U << 11U*2U)  );         /* set CP11 Full Access */
+#endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+  SystemCoreClock = SYSTEM_CLOCK;
+}

CMSIS/CoreValidation/Tests/Cortex-M4FP/AC5/RTE/_FVP/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'CMSIS_CV' 
+ * Target:  'FVP' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "ARMCM4_FP.h"
+
+
+#endif /* RTE_COMPONENTS_H */

CMSIS/CoreValidation/Tests/Cortex-M4FP/AC6/CMSIS_CV.uvprojx

@@ -0,0 +1,507 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>FVP</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pArmCC>6070000::V6.7::.\ARMCLANG</pArmCC>
+      <pCCUsed>6070000::V6.7::.\ARMCLANG</pCCUsed>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>ARMCM4_FP</Device>
+          <Vendor>ARM</Vendor>
+          <PackID>ARM.CMSIS.5.1.2-dev1</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\Objects\</OutputDirectory>
+          <OutputName>CMSIS_CV</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\Listings\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>  -MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> -MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>1</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M4"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>2</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>1</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <useXO>0</useXO>
+            <v6Lang>3</v6Lang>
+            <v6LangP>3</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls>-Wno-covered-switch-default</MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>.\,..\..\..\Include</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <uClangAs>0</uClangAs>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>.\,..\..\..\Include</IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange></TextAddressRange>
+            <DataAddressRange></DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc>--entry=Reset_Handler</Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Test</GroupName>
+          <Files>
+            <File>
+              <FileName>cmsis_cv.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\cmsis_cv.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_CoreFunc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_CoreFunc.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_CoreInstr.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_CoreInstr.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Framework.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_Framework.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_MPU_ARMv7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_MPU_ARMv7.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Report.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_Report.c</FilePath>
+            </File>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\main.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Config.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\CV_Config.h</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::CMSIS</GroupName>
+        </Group>
+        <Group>
+          <GroupName>::Device</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components>
+      <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.0.2" condition="ARMv6_7_8-M Device">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </component>
+    </components>
+    <files>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM0\Source\ARM\startup_ARMCM0.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM0\startup_ARMCM0.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM0\Source\system_ARMCM0.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM0\system_ARMCM0.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM3\Source\ARM\startup_ARMCM3.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM3\startup_ARMCM3.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM3\Source\system_ARMCM3.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM3\system_ARMCM3.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM4\Source\ARM\startup_ARMCM4.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM4\startup_ARMCM4.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM4\Source\system_ARMCM4.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM4\system_ARMCM4.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM4\Source\ARM\startup_ARMCM4.s" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM4_FP\startup_ARMCM4.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM4\Source\system_ARMCM4.c" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM4_FP\system_ARMCM4.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </file>
+    </files>
+  </RTE>
+
+</Project>

CMSIS/CoreValidation/Tests/Cortex-M4FP/AC6/CV_Config.h

@@ -0,0 +1,81 @@
+/*-----------------------------------------------------------------------------
+ *      Name:         CV_Config.h 
+ *      Purpose:      CV Config header
+ *----------------------------------------------------------------------------
+ *      Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+#ifndef __CV_CONFIG_H
+#define __CV_CONFIG_H
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+#define RTE_CV_COREINSTR 1
+#define RTE_CV_COREFUNC  1
+#define RTE_CV_MPUFUNC   1
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h> Common Test Settings
+// <o> Print Output Format <0=> Plain Text <1=> XML
+// <i> Set the test results output format to plain text or XML
+#ifndef PRINT_XML_REPORT
+#define PRINT_XML_REPORT            1
+#endif
+// <o> Buffer size for assertions results
+// <i> Set the buffer size for assertions results buffer
+#define BUFFER_ASSERTIONS           128U
+// </h>
+
+// <h> Disable Test Cases
+// <i> Uncheck to disable an individual test case
+// <q00> TC_CoreInstr_NOP
+// <q01> TC_CoreInstr_REV
+// <q02> TC_CoreInstr_REV16
+// <q03> TC_CoreInstr_REVSH
+// <q04> TC_CoreInstr_ROR
+// <q05> TC_CoreInstr_RBIT
+// <q06> TC_CoreInstr_CLZ
+// <q07> TC_CoreInstr_SSAT
+// <q08> TC_CoreInstr_USAT
+//
+// <q09> TC_CoreFunc_EnDisIRQ
+// <q10> TC_CoreFunc_Control
+// <q11> TC_CoreFunc_IPSR
+// <q12> TC_CoreFunc_APSR
+// <q13> TC_CoreFunc_PSP
+// <q14> TC_CoreFunc_MSP
+// <q15> TC_CoreFunc_PRIMASK
+// <q16> TC_CoreFunc_FAULTMASK
+// <q17> TC_CoreFunc_BASEPRI
+// <q18> TC_CoreFunc_FPSCR
+//
+// <q19> TC_MPU_SetClear
+// <q20> TC_MPU_Load
+#define TC_COREINSTR_NOP_EN         1
+#define TC_COREINSTR_REV_EN         1
+#define TC_COREINSTR_REV16_EN       1
+#define TC_COREINSTR_REVSH_EN       1
+#define TC_COREINSTR_ROR_EN         1
+#define TC_COREINSTR_RBIT_EN        1
+#define TC_COREINSTR_CLZ_EN         1
+#define TC_COREINSTR_SSAT_EN        1
+#define TC_COREINSTR_USAT_EN        1
+
+#define TC_COREFUNC_ENDISIRQ_EN     1
+#define TC_COREFUNC_CONTROL_EN      1
+#define TC_COREFUNC_IPSR_EN         1
+#define TC_COREFUNC_APSR_EN         1
+#define TC_COREFUNC_PSP_EN          1
+#define TC_COREFUNC_MSP_EN          1
+#define TC_COREFUNC_PRIMASK_EN      1
+#define TC_COREFUNC_FAULTMASK_EN    1
+#define TC_COREFUNC_BASEPRI_EN      1
+#define TC_COREFUNC_FPSCR_EN        1
+
+#define TC_MPU_SETCLEAR_EN          1
+#define TC_MPU_LOAD_EN              1
+// </h>
+
+#endif /* __CV_CONFIG_H */
+

CMSIS/CoreValidation/Tests/Cortex-M4FP/AC6/EventRecorderStub.scvd

@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
+
+<component name="EventRecorderStub" version="1.0.0"/>       <!--name and version of the component-->
+  <events>
+  </events>
+
+</component_viewer>

CMSIS/CoreValidation/Tests/Cortex-M4FP/AC6/RTE/Device/ARMCM4_FP/startup_ARMCM4.s

@@ -0,0 +1,262 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM4.s
+; * @brief    CMSIS Core Device Startup File for
+; *           ARMCM4 Device Series
+; * @version  V5.00
+; * @date     02. March 2016
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000C00
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
+                DCD     RTC_IRQHandler            ;  1:  Real Time Clock
+                DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
+                DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
+                DCD     MCIA_IRQHandler           ;  4:  MCIa
+                DCD     MCIB_IRQHandler           ;  5:  MCIb
+                DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
+                DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
+                DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
+                DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
+                DCD     AACI_IRQHandler           ; 10: AACI / AC97
+                DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
+                DCD     ENET_IRQHandler           ; 12: Ethernet
+                DCD     USBDC_IRQHandler          ; 13: USB Device
+                DCD     USBHC_IRQHandler          ; 14: USB Host Controller
+                DCD     CHLCD_IRQHandler          ; 15: Character LCD
+                DCD     FLEXRAY_IRQHandler        ; 16: Flexray
+                DCD     CAN_IRQHandler            ; 17: CAN
+                DCD     LIN_IRQHandler            ; 18: LIN
+                DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
+                DCD     0                         ; 20: Reserved
+                DCD     0                         ; 21: Reserved
+                DCD     0                         ; 22: Reserved
+                DCD     0                         ; 23: Reserved
+                DCD     0                         ; 24: Reserved
+                DCD     0                         ; 25: Reserved
+                DCD     0                         ; 26: Reserved
+                DCD     0                         ; 27: Reserved
+                DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
+                DCD     0                         ; 29: Reserved - CPU FPGA
+                DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
+                DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WDT_IRQHandler            [WEAK]
+                EXPORT  RTC_IRQHandler            [WEAK]
+                EXPORT  TIM0_IRQHandler           [WEAK]
+                EXPORT  TIM2_IRQHandler           [WEAK]
+                EXPORT  MCIA_IRQHandler           [WEAK]
+                EXPORT  MCIB_IRQHandler           [WEAK]
+                EXPORT  UART0_IRQHandler          [WEAK]
+                EXPORT  UART1_IRQHandler          [WEAK]
+                EXPORT  UART2_IRQHandler          [WEAK]
+                EXPORT  UART3_IRQHandler          [WEAK]
+                EXPORT  UART4_IRQHandler          [WEAK]
+                EXPORT  AACI_IRQHandler           [WEAK]
+                EXPORT  CLCD_IRQHandler           [WEAK]
+                EXPORT  ENET_IRQHandler           [WEAK]
+                EXPORT  USBDC_IRQHandler          [WEAK]
+                EXPORT  USBHC_IRQHandler          [WEAK]
+                EXPORT  CHLCD_IRQHandler          [WEAK]
+                EXPORT  FLEXRAY_IRQHandler        [WEAK]
+                EXPORT  CAN_IRQHandler            [WEAK]
+                EXPORT  LIN_IRQHandler            [WEAK]
+                EXPORT  I2C_IRQHandler            [WEAK]
+                EXPORT  CPU_CLCD_IRQHandler       [WEAK]
+                EXPORT  SPI_IRQHandler            [WEAK]
+
+WDT_IRQHandler
+RTC_IRQHandler
+TIM0_IRQHandler
+TIM2_IRQHandler
+MCIA_IRQHandler
+MCIB_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+UART4_IRQHandler
+AACI_IRQHandler
+CLCD_IRQHandler
+ENET_IRQHandler
+USBDC_IRQHandler
+USBHC_IRQHandler
+CHLCD_IRQHandler
+FLEXRAY_IRQHandler
+CAN_IRQHandler
+LIN_IRQHandler
+I2C_IRQHandler
+CPU_CLCD_IRQHandler
+SPI_IRQHandler
+                B       .
+
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap PROC
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+                ENDP
+
+                ALIGN
+
+                ENDIF
+
+
+                END

CMSIS/CoreValidation/Tests/Cortex-M4FP/AC6/RTE/Device/ARMCM4_FP/system_ARMCM4.c

@@ -0,0 +1,83 @@
+/**************************************************************************//**
+ * @file     system_ARMCM4.c
+ * @brief    CMSIS Device System Source File for
+ *           ARMCM4 Device Series
+ * @version  V5.00
+ * @date     07. September 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM4)
+  #include "ARMCM4.h"
+#elif defined (ARMCM4_FP)
+  #include "ARMCM4_FP.h"
+#else
+  #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+
+#define  SYSTEM_CLOCK    (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+#if defined (__FPU_USED) && (__FPU_USED == 1U)
+  SCB->CPACR |= ((3U << 10U*2U) |           /* set CP10 Full Access */
+                 (3U << 11U*2U)  );         /* set CP11 Full Access */
+#endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+  SystemCoreClock = SYSTEM_CLOCK;
+}

CMSIS/CoreValidation/Tests/Cortex-M4FP/AC6/RTE/_FVP/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'CMSIS_CV' 
+ * Target:  'FVP' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "ARMCM4_FP.h"
+
+
+#endif /* RTE_COMPONENTS_H */

CMSIS/CoreValidation/Tests/Cortex-M4FP/GCC/CMSIS_CV.uvprojx

@@ -0,0 +1,434 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>FVP</TargetName>
+      <ToolsetNumber>0x3</ToolsetNumber>
+      <ToolsetName>ARM-GNU</ToolsetName>
+      <pArmCC>6070000::V6.7::.\ARMCLANG</pArmCC>
+      <pCCUsed>6070000::V6.7::.\ARMCLANG</pCCUsed>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>ARMCM4_FP</Device>
+          <Vendor>ARM</Vendor>
+          <PackID>ARM.CMSIS.5.1.2-dev1</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\Objects\</OutputDirectory>
+          <OutputName>CMSIS_CV</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\Listings\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>  -MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> -MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArm>
+          <ArmMisc>
+            <asLst>1</asLst>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>1</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <GCPUTYP>"Cortex-M4"</GCPUTYP>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>2</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <IRAM2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </IRAM2>
+              <IROM2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </IROM2>
+            </OnChipMemories>
+          </ArmMisc>
+          <Carm>
+            <arpcs>1</arpcs>
+            <stkchk>0</stkchk>
+            <reentr>0</reentr>
+            <interw>1</interw>
+            <bigend>0</bigend>
+            <Strict>0</Strict>
+            <Optim>1</Optim>
+            <wLevel>3</wLevel>
+            <uThumb>1</uThumb>
+            <VariousControls>
+              <MiscControls>-mfloat-abi=hard -mfpu=fpv4-sp-d16 -Wall -Wextra -Wstrict-prototypes -Wshadow</MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>.;..\..\..\Include</IncludePath>
+            </VariousControls>
+          </Carm>
+          <Aarm>
+            <bBE>0</bBE>
+            <interw>1</interw>
+            <VariousControls>
+              <MiscControls>-mfloat-abi=hard -mfpu=fpv4-sp-d16 -Wall</MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>.;..\..\..\Include</IncludePath>
+            </VariousControls>
+          </Aarm>
+          <LDarm>
+            <umfTarg>1</umfTarg>
+            <enaGarb>0</enaGarb>
+            <noStart>0</noStart>
+            <noStLib>0</noStLib>
+            <uMathLib>0</uMathLib>
+            <TextAddressRange></TextAddressRange>
+            <DataAddressRange></DataAddressRange>
+            <BSSAddressRange></BSSAddressRange>
+            <IncludeLibs></IncludeLibs>
+            <IncludeDir></IncludeDir>
+            <Misc>-mfloat-abi=hard -mfpu=fpv4-sp-d16 --specs=rdimon.specs</Misc>
+            <ScatterFile>.\RTE\Device\ARMCM4_FP\gcc_arm.ld</ScatterFile>
+          </LDarm>
+        </TargetArm>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Test</GroupName>
+          <Files>
+            <File>
+              <FileName>cmsis_cv.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\cmsis_cv.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_CoreFunc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_CoreFunc.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_CoreInstr.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_CoreInstr.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Framework.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_Framework.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_MPU_ARMv7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_MPU_ARMv7.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Report.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_Report.c</FilePath>
+            </File>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\main.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Config.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\CV_Config.h</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::CMSIS</GroupName>
+        </Group>
+        <Group>
+          <GroupName>::Device</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components>
+      <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.0.2" condition="ARMv6_7_8-M Device">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS GCC">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </component>
+    </components>
+    <files>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM0\Source\ARM\startup_ARMCM0.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM0\startup_ARMCM0.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM0\Source\system_ARMCM0.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM0\system_ARMCM0.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="linkerScript" condition="GCC" name="Device\ARM\ARMCM3\Source\GCC\gcc_arm.ld" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM3\gcc_arm.ld</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceAsm" condition="GCC" name="Device\ARM\ARMCM3\Source\GCC\startup_ARMCM3.S" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM3\startup_ARMCM3.S</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" condition="GCC" name="Device\ARM\ARMCM3\Source\GCC\startup_ARMCM3.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM3\startup_ARMCM3.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM3\Source\system_ARMCM3.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM3\system_ARMCM3.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="linkerScript" condition="GCC" name="Device\ARM\ARMCM4\Source\GCC\gcc_arm.ld" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM4\gcc_arm.ld</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" condition="GCC" name="Device\ARM\ARMCM4\Source\GCC\startup_ARMCM4.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM4\startup_ARMCM4.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM4\Source\ARM\startup_ARMCM4.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM4\startup_ARMCM4.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM4\Source\system_ARMCM4.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM4\system_ARMCM4.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="linkerScript" condition="GCC" name="Device\ARM\ARMCM4\Source\GCC\gcc_arm.ld" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM4_FP\gcc_arm.ld</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="sourceC" condition="GCC" name="Device\ARM\ARMCM4\Source\GCC\startup_ARMCM4.c" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM4_FP\startup_ARMCM4.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM4\Source\system_ARMCM4.c" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM4_FP\system_ARMCM4.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </file>
+    </files>
+  </RTE>
+
+</Project>

CMSIS/CoreValidation/Tests/Cortex-M4FP/GCC/CV_Config.h

@@ -0,0 +1,82 @@
+/*-----------------------------------------------------------------------------
+ *      Name:         CV_Config.h 
+ *      Purpose:      CV Config header
+ *----------------------------------------------------------------------------
+ *      Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+#ifndef __CV_CONFIG_H
+#define __CV_CONFIG_H
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+#define RTE_CV_COREINSTR 1
+#define RTE_CV_COREFUNC  1
+#define RTE_CV_MPUFUNC   1
+
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h> Common Test Settings
+// <o> Print Output Format <0=> Plain Text <1=> XML
+// <i> Set the test results output format to plain text or XML
+#ifndef PRINT_XML_REPORT
+#define PRINT_XML_REPORT            1
+#endif
+// <o> Buffer size for assertions results
+// <i> Set the buffer size for assertions results buffer
+#define BUFFER_ASSERTIONS           128U
+// </h>
+
+// <h> Disable Test Cases
+// <i> Uncheck to disable an individual test case
+// <q00> TC_CoreInstr_NOP
+// <q01> TC_CoreInstr_REV
+// <q02> TC_CoreInstr_REV16
+// <q03> TC_CoreInstr_REVSH
+// <q04> TC_CoreInstr_ROR
+// <q05> TC_CoreInstr_RBIT
+// <q06> TC_CoreInstr_CLZ
+// <q07> TC_CoreInstr_SSAT
+// <q08> TC_CoreInstr_USAT
+//
+// <q09> TC_CoreFunc_EnDisIRQ
+// <q10> TC_CoreFunc_Control
+// <q11> TC_CoreFunc_IPSR
+// <q12> TC_CoreFunc_APSR
+// <q13> TC_CoreFunc_PSP
+// <q14> TC_CoreFunc_MSP
+// <q15> TC_CoreFunc_PRIMASK
+// <q16> TC_CoreFunc_FAULTMASK
+// <q17> TC_CoreFunc_BASEPRI
+// <q18> TC_CoreFunc_FPSCR
+//
+// <q19> TC_MPU_SetClear
+// <q20> TC_MPU_Load
+#define TC_COREINSTR_NOP_EN         1
+#define TC_COREINSTR_REV_EN         1
+#define TC_COREINSTR_REV16_EN       1
+#define TC_COREINSTR_REVSH_EN       1
+#define TC_COREINSTR_ROR_EN         1
+#define TC_COREINSTR_RBIT_EN        1
+#define TC_COREINSTR_CLZ_EN         1
+#define TC_COREINSTR_SSAT_EN        1
+#define TC_COREINSTR_USAT_EN        1
+
+#define TC_COREFUNC_ENDISIRQ_EN     1
+#define TC_COREFUNC_CONTROL_EN      1
+#define TC_COREFUNC_IPSR_EN         1
+#define TC_COREFUNC_APSR_EN         1
+#define TC_COREFUNC_PSP_EN          1
+#define TC_COREFUNC_MSP_EN          1
+#define TC_COREFUNC_PRIMASK_EN      1
+#define TC_COREFUNC_FAULTMASK_EN    1
+#define TC_COREFUNC_BASEPRI_EN      1
+#define TC_COREFUNC_FPSCR_EN        1
+
+#define TC_MPU_SETCLEAR_EN          1
+#define TC_MPU_LOAD_EN              1
+// </h>
+
+#endif /* __CV_CONFIG_H */
+

CMSIS/CoreValidation/Tests/Cortex-M4FP/GCC/EventRecorderStub.scvd

@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
+
+<component name="EventRecorderStub" version="1.0.0"/>       <!--name and version of the component-->
+  <events>
+  </events>
+
+</component_viewer>

CMSIS/CoreValidation/Tests/Cortex-M4FP/GCC/RTE/Device/ARMCM4_FP/gcc_arm.ld

@@ -0,0 +1,196 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+  FLASH (rx)  : ORIGIN = 0x00000000, LENGTH = 512K
+  RAM   (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapBase
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __Vectors_End
+ *   __Vectors_Size
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+	.text :
+	{
+		KEEP(*(.vectors))
+		__Vectors_End = .;
+		__Vectors_Size = __Vectors_End - __Vectors;
+		__end__ = .;
+
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+	.ARM.extab :
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	/* To copy multiple ROM to RAM sections,
+	 * uncomment .copy.table section and,
+	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.copy.table :
+	{
+		. = ALIGN(4);
+		__copy_table_start__ = .;
+		LONG (__etext)
+		LONG (__data_start__)
+		LONG (__data_end__ - __data_start__)
+		LONG (__etext2)
+		LONG (__data2_start__)
+		LONG (__data2_end__ - __data2_start__)
+		__copy_table_end__ = .;
+	} > FLASH
+	*/
+
+	/* To clear multiple BSS sections,
+	 * uncomment .zero.table section and,
+	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.zero.table :
+	{
+		. = ALIGN(4);
+		__zero_table_start__ = .;
+		LONG (__bss_start__)
+		LONG (__bss_end__ - __bss_start__)
+		LONG (__bss2_start__)
+		LONG (__bss2_end__ - __bss2_start__)
+		__zero_table_end__ = .;
+	} > FLASH
+	*/
+
+	__etext = .;
+
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		KEEP(*(.jcr*))
+		. = ALIGN(4);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > RAM
+
+	.heap (COPY):
+	{
+		__HeapBase = .;
+		__end__ = .;
+		end = __end__;
+		KEEP(*(.heap*))
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (COPY):
+	{
+		KEEP(*(.stack*))
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM);
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}

CMSIS/CoreValidation/Tests/Cortex-M4FP/GCC/RTE/Device/ARMCM4_FP/startup_ARMCM4.c

@@ -0,0 +1,295 @@
+/**************************************************************************//**
+ * @file     startup_ARMCM4.s
+ * @brief    CMSIS Core Device Startup File for
+ *           ARMCM4 Device Series
+ * @version  V5.00
+ * @date     26. April 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdint.h>
+
+
+/*----------------------------------------------------------------------------
+  Linker generated Symbols
+ *----------------------------------------------------------------------------*/
+extern uint32_t __etext;
+extern uint32_t __data_start__;
+extern uint32_t __data_end__;
+extern uint32_t __copy_table_start__;
+extern uint32_t __copy_table_end__;
+extern uint32_t __zero_table_start__;
+extern uint32_t __zero_table_end__;
+extern uint32_t __bss_start__;
+extern uint32_t __bss_end__;
+extern uint32_t __StackTop;
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler Function Prototype
+ *----------------------------------------------------------------------------*/
+typedef void( *pFunc )( void );
+
+
+/*----------------------------------------------------------------------------
+  External References
+ *----------------------------------------------------------------------------*/
+#ifndef __START
+extern void  _start(void) __attribute__((noreturn));    /* PreeMain (C library entry point) */
+#else
+extern int  __START(void) __attribute__((noreturn));    /* main entry point */
+#endif
+
+#ifndef __NO_SYSTEM_INIT
+extern void SystemInit (void);            /* CMSIS System Initialization      */
+#endif
+
+
+/*----------------------------------------------------------------------------
+  Internal References
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void);                          /* Default empty handler */
+void Reset_Handler(void);                            /* Reset Handler */
+
+
+/*----------------------------------------------------------------------------
+  User Initial Stack & Heap
+ *----------------------------------------------------------------------------*/
+#ifndef __STACK_SIZE
+  #define	__STACK_SIZE  0x00000400
+#endif
+static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack")));
+
+#ifndef __HEAP_SIZE
+  #define	__HEAP_SIZE   0x00000C00
+#endif
+#if __HEAP_SIZE > 0
+static uint8_t heap[__HEAP_SIZE]   __attribute__ ((aligned(8), used, section(".heap")));
+#endif
+
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Cortex-M4 Processor Exceptions */
+void NMI_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void MemManage_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/* ARMCM4 Specific Interrupts */
+void WDT_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void RTC_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void TIM0_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void TIM2_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void MCIA_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void MCIB_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART0_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART1_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART2_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART4_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void AACI_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void CLCD_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void ENET_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void USBDC_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void USBHC_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void CHLCD_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void FLEXRAY_IRQHandler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void CAN_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void LIN_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void I2C_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void CPU_CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART3_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void SPI_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = {
+  /* Cortex-M4 Exceptions Handler */
+  (pFunc)((uint32_t)&__StackTop),           /*      Initial Stack Pointer     */
+  Reset_Handler,                            /*      Reset Handler             */
+  NMI_Handler,                              /*      NMI Handler               */
+  HardFault_Handler,                        /*      Hard Fault Handler        */
+  MemManage_Handler,                        /*      MPU Fault Handler         */
+  BusFault_Handler,                         /*      Bus Fault Handler         */
+  UsageFault_Handler,                       /*      Usage Fault Handler       */
+  0,                                        /*      Reserved                  */
+  0,                                        /*      Reserved                  */
+  0,                                        /*      Reserved                  */
+  0,                                        /*      Reserved                  */
+  SVC_Handler,                              /*      SVCall Handler            */
+  DebugMon_Handler,                         /*      Debug Monitor Handler     */
+  0,                                        /*      Reserved                  */
+  PendSV_Handler,                           /*      PendSV Handler            */
+  SysTick_Handler,                          /*      SysTick Handler           */
+
+  /* External interrupts */
+  WDT_IRQHandler,                           /*  0:  Watchdog Timer            */
+  RTC_IRQHandler,                           /*  1:  Real Time Clock           */
+  TIM0_IRQHandler,                          /*  2:  Timer0 / Timer1           */
+  TIM2_IRQHandler,                          /*  3:  Timer2 / Timer3           */
+  MCIA_IRQHandler,                          /*  4:  MCIa                      */
+  MCIB_IRQHandler,                          /*  5:  MCIb                      */
+  UART0_IRQHandler,                         /*  6:  UART0 - DUT FPGA          */
+  UART1_IRQHandler,                         /*  7:  UART1 - DUT FPGA          */
+  UART2_IRQHandler,                         /*  8:  UART2 - DUT FPGA          */
+  UART4_IRQHandler,                         /*  9:  UART4 - not connected     */
+  AACI_IRQHandler,                          /* 10: AACI / AC97                */
+  CLCD_IRQHandler,                          /* 11: CLCD Combined Interrupt    */
+  ENET_IRQHandler,                          /* 12: Ethernet                   */
+  USBDC_IRQHandler,                         /* 13: USB Device                 */
+  USBHC_IRQHandler,                         /* 14: USB Host Controller        */
+  CHLCD_IRQHandler,                         /* 15: Character LCD              */
+  FLEXRAY_IRQHandler,                       /* 16: Flexray                    */
+  CAN_IRQHandler,                           /* 17: CAN                        */
+  LIN_IRQHandler,                           /* 18: LIN                        */
+  I2C_IRQHandler,                           /* 19: I2C ADC/DAC                */
+  0,                                        /* 20: Reserved                   */
+  0,                                        /* 21: Reserved                   */
+  0,                                        /* 22: Reserved                   */
+  0,                                        /* 23: Reserved                   */
+  0,                                        /* 24: Reserved                   */
+  0,                                        /* 25: Reserved                   */
+  0,                                        /* 26: Reserved                   */
+  0,                                        /* 27: Reserved                   */
+  CPU_CLCD_IRQHandler,                      /* 28: Reserved - CPU FPGA CLCD   */
+  0,                                        /* 29: Reserved - CPU FPGA        */
+  UART3_IRQHandler,                         /* 30: UART3    - CPU FPGA        */
+  SPI_IRQHandler                            /* 31: SPI Touchscreen - CPU FPGA */
+};
+
+
+/*----------------------------------------------------------------------------
+  Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+  uint32_t *pSrc, *pDest;
+  uint32_t *pTable __attribute__((unused));
+
+/*  Firstly it copies data from read only memory to RAM. There are two schemes
+ *  to copy. One can copy more than one sections. Another can only copy
+ *  one section.  The former scheme needs more instructions and read-only
+ *  data to implement than the latter.
+ *  Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.  */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/*  Multiple sections scheme.
+ *
+ *  Between symbol address __copy_table_start__ and __copy_table_end__,
+ *  there are array of triplets, each of which specify:
+ *    offset 0: LMA of start of a section to copy from
+ *    offset 4: VMA of start of a section to copy to
+ *    offset 8: size of the section to copy. Must be multiply of 4
+ *
+ *  All addresses must be aligned to 4 bytes boundary.
+ */
+  pTable = &__copy_table_start__;
+
+  for (; pTable < &__copy_table_end__; pTable = pTable + 3) {
+		pSrc  = (uint32_t*)*(pTable + 0);
+		pDest = (uint32_t*)*(pTable + 1);
+		for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
+      *pDest++ = *pSrc++;
+		}
+	}
+#else
+/*  Single section scheme.
+ *
+ *  The ranges of copy from/to are specified by following symbols
+ *    __etext: LMA of start of the section to copy from. Usually end of text
+ *    __data_start__: VMA of start of the section to copy to
+ *    __data_end__: VMA of end of the section to copy to
+ *
+ *  All addresses must be aligned to 4 bytes boundary.
+ */
+  pSrc  = &__etext;
+  pDest = &__data_start__;
+
+  for ( ; pDest < &__data_end__ ; ) {
+    *pDest++ = *pSrc++;
+  }
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/*  This part of work usually is done in C library startup code. Otherwise,
+ *  define this macro to enable it in this startup.
+ *
+ *  There are two schemes too. One can clear multiple BSS sections. Another
+ *  can only clear one section. The former is more size expensive than the
+ *  latter.
+ *
+ *  Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ *  Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/*  Multiple sections scheme.
+ *
+ *  Between symbol address __copy_table_start__ and __copy_table_end__,
+ *  there are array of tuples specifying:
+ *    offset 0: Start of a BSS section
+ *    offset 4: Size of this BSS section. Must be multiply of 4
+ */
+  pTable = &__zero_table_start__;
+
+  for (; pTable < &__zero_table_end__; pTable = pTable + 2) {
+		pDest = (uint32_t*)*(pTable + 0);
+		for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
+      *pDest++ = 0;
+		}
+	}
+#elif defined (__STARTUP_CLEAR_BSS)
+/*  Single BSS section scheme.
+ *
+ *  The BSS section is specified by following symbols
+ *    __bss_start__: start of the BSS section.
+ *    __bss_end__: end of the BSS section.
+ *
+ *  Both addresses must be aligned to 4 bytes boundary.
+ */
+  pDest = &__bss_start__;
+
+  for ( ; pDest < &__bss_end__ ; ) {
+    *pDest++ = 0UL;
+  }
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+#ifndef __NO_SYSTEM_INIT
+	SystemInit();
+#endif
+
+#ifndef __START
+#define __START _start
+#endif
+	__START();
+
+}
+
+
+/*----------------------------------------------------------------------------
+  Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+
+	while(1);
+}

CMSIS/CoreValidation/Tests/Cortex-M4FP/GCC/RTE/Device/ARMCM4_FP/system_ARMCM4.c

@@ -0,0 +1,83 @@
+/**************************************************************************//**
+ * @file     system_ARMCM4.c
+ * @brief    CMSIS Device System Source File for
+ *           ARMCM4 Device Series
+ * @version  V5.00
+ * @date     07. September 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM4)
+  #include "ARMCM4.h"
+#elif defined (ARMCM4_FP)
+  #include "ARMCM4_FP.h"
+#else
+  #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+
+#define  SYSTEM_CLOCK    (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+#if defined (__FPU_USED) && (__FPU_USED == 1U)
+  SCB->CPACR |= ((3U << 10U*2U) |           /* set CP10 Full Access */
+                 (3U << 11U*2U)  );         /* set CP11 Full Access */
+#endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+  SystemCoreClock = SYSTEM_CLOCK;
+}

CMSIS/CoreValidation/Tests/Cortex-M4FP/GCC/RTE/_FVP/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'CMSIS_CV' 
+ * Target:  'FVP' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "ARMCM4_FP.h"
+
+
+#endif /* RTE_COMPONENTS_H */

CMSIS/CoreValidation/Tests/Cortex-M7/AC5/CMSIS_CV.uvprojx

@@ -0,0 +1,507 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>FVP</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pArmCC>5060528::V5.06 update 5 (build 528)::ARMCC</pArmCC>
+      <pCCUsed>5060528::V5.06 update 5 (build 528)::ARMCC</pCCUsed>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>ARMCM7</Device>
+          <Vendor>ARM</Vendor>
+          <PackID>ARM.CMSIS.5.1.2-dev1</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M7") CLOCK(12000000) ESEL ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:ARMCM7$Device\ARM\ARMCM7\Include\ARMCM7.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:ARMCM7$Device\ARM\SVD\ARMCM7.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\Objects\</OutputDirectory>
+          <OutputName>CMSIS_CV</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\Listings\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>  -MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM7</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> -MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM7</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>1</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M7"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>1</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <useXO>0</useXO>
+            <v6Lang>3</v6Lang>
+            <v6LangP>3</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>.\,..\..\..\Include</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <uClangAs>0</uClangAs>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>.\,..\..\..\Include</IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange></TextAddressRange>
+            <DataAddressRange></DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc>--entry=Reset_Handler</Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Test</GroupName>
+          <Files>
+            <File>
+              <FileName>cmsis_cv.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\cmsis_cv.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_CoreFunc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_CoreFunc.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_CoreInstr.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_CoreInstr.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Framework.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_Framework.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_MPU_ARMv7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_MPU_ARMv7.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Report.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_Report.c</FilePath>
+            </File>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\main.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Config.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\CV_Config.h</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::CMSIS</GroupName>
+        </Group>
+        <Group>
+          <GroupName>::Device</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components>
+      <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.0.2" condition="ARMv6_7_8-M Device">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM7 CMSIS">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </component>
+    </components>
+    <files>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM0\Source\ARM\startup_ARMCM0.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM0\startup_ARMCM0.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM0\Source\system_ARMCM0.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM0\system_ARMCM0.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM3\Source\ARM\startup_ARMCM3.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM3\startup_ARMCM3.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM3\Source\system_ARMCM3.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM3\system_ARMCM3.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM4\Source\ARM\startup_ARMCM4.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM4\startup_ARMCM4.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM4\Source\system_ARMCM4.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM4\system_ARMCM4.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM7\Source\ARM\startup_ARMCM7.s" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM7\startup_ARMCM7.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM7 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM7\Source\system_ARMCM7.c" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM7\system_ARMCM7.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM7 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </file>
+    </files>
+  </RTE>
+
+</Project>

CMSIS/CoreValidation/Tests/Cortex-M7/AC5/CV_Config.h

@@ -0,0 +1,82 @@
+/*-----------------------------------------------------------------------------
+ *      Name:         CV_Config.h 
+ *      Purpose:      CV Config header
+ *----------------------------------------------------------------------------
+ *      Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+#ifndef __CV_CONFIG_H
+#define __CV_CONFIG_H
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+#define RTE_CV_COREINSTR 1
+#define RTE_CV_COREFUNC  1
+#define RTE_CV_MPUFUNC   1
+
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h> Common Test Settings
+// <o> Print Output Format <0=> Plain Text <1=> XML
+// <i> Set the test results output format to plain text or XML
+#ifndef PRINT_XML_REPORT
+#define PRINT_XML_REPORT            1
+#endif
+// <o> Buffer size for assertions results
+// <i> Set the buffer size for assertions results buffer
+#define BUFFER_ASSERTIONS           128U
+// </h>
+
+// <h> Disable Test Cases
+// <i> Uncheck to disable an individual test case
+// <q00> TC_CoreInstr_NOP
+// <q01> TC_CoreInstr_REV
+// <q02> TC_CoreInstr_REV16
+// <q03> TC_CoreInstr_REVSH
+// <q04> TC_CoreInstr_ROR
+// <q05> TC_CoreInstr_RBIT
+// <q06> TC_CoreInstr_CLZ
+// <q07> TC_CoreInstr_SSAT
+// <q08> TC_CoreInstr_USAT
+//
+// <q09> TC_CoreFunc_EnDisIRQ
+// <q10> TC_CoreFunc_Control
+// <q11> TC_CoreFunc_IPSR
+// <q12> TC_CoreFunc_APSR
+// <q13> TC_CoreFunc_PSP
+// <q14> TC_CoreFunc_MSP
+// <q15> TC_CoreFunc_PRIMASK
+// <q16> TC_CoreFunc_FAULTMASK
+// <q17> TC_CoreFunc_BASEPRI
+// <q18> TC_CoreFunc_FPSCR
+//
+// <q19> TC_MPU_SetClear
+// <q20> TC_MPU_Load
+#define TC_COREINSTR_NOP_EN         1
+#define TC_COREINSTR_REV_EN         1
+#define TC_COREINSTR_REV16_EN       1
+#define TC_COREINSTR_REVSH_EN       1
+#define TC_COREINSTR_ROR_EN         1
+#define TC_COREINSTR_RBIT_EN        1
+#define TC_COREINSTR_CLZ_EN         1
+#define TC_COREINSTR_SSAT_EN        1
+#define TC_COREINSTR_USAT_EN        1
+
+#define TC_COREFUNC_ENDISIRQ_EN     1
+#define TC_COREFUNC_CONTROL_EN      1
+#define TC_COREFUNC_IPSR_EN         1
+#define TC_COREFUNC_APSR_EN         1
+#define TC_COREFUNC_PSP_EN          1
+#define TC_COREFUNC_MSP_EN          1
+#define TC_COREFUNC_PRIMASK_EN      1
+#define TC_COREFUNC_FAULTMASK_EN    1
+#define TC_COREFUNC_BASEPRI_EN      1
+#define TC_COREFUNC_FPSCR_EN        1
+
+#define TC_MPU_SETCLEAR_EN          1
+#define TC_MPU_LOAD_EN              1
+// </h>
+
+#endif /* __CV_CONFIG_H */
+

CMSIS/CoreValidation/Tests/Cortex-M7/AC5/EventRecorderStub.scvd

@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
+
+<component name="EventRecorderStub" version="1.0.0"/>       <!--name and version of the component-->
+  <events>
+  </events>
+
+</component_viewer>

CMSIS/CoreValidation/Tests/Cortex-M7/AC5/RTE/Device/ARMCM7/startup_ARMCM7.s

@@ -0,0 +1,262 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM7.s
+; * @brief    CMSIS Core Device Startup File for
+; *           ARMCM7 Device Series
+; * @version  V5.00
+; * @date     02. March 2016
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000C00
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
+                DCD     RTC_IRQHandler            ;  1:  Real Time Clock
+                DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
+                DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
+                DCD     MCIA_IRQHandler           ;  4:  MCIa
+                DCD     MCIB_IRQHandler           ;  5:  MCIb
+                DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
+                DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
+                DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
+                DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
+                DCD     AACI_IRQHandler           ; 10: AACI / AC97
+                DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
+                DCD     ENET_IRQHandler           ; 12: Ethernet
+                DCD     USBDC_IRQHandler          ; 13: USB Device
+                DCD     USBHC_IRQHandler          ; 14: USB Host Controller
+                DCD     CHLCD_IRQHandler          ; 15: Character LCD
+                DCD     FLEXRAY_IRQHandler        ; 16: Flexray
+                DCD     CAN_IRQHandler            ; 17: CAN
+                DCD     LIN_IRQHandler            ; 18: LIN
+                DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
+                DCD     0                         ; 20: Reserved
+                DCD     0                         ; 21: Reserved
+                DCD     0                         ; 22: Reserved
+                DCD     0                         ; 23: Reserved
+                DCD     0                         ; 24: Reserved
+                DCD     0                         ; 25: Reserved
+                DCD     0                         ; 26: Reserved
+                DCD     0                         ; 27: Reserved
+                DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
+                DCD     0                         ; 29: Reserved - CPU FPGA
+                DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
+                DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WDT_IRQHandler            [WEAK]
+                EXPORT  RTC_IRQHandler            [WEAK]
+                EXPORT  TIM0_IRQHandler           [WEAK]
+                EXPORT  TIM2_IRQHandler           [WEAK]
+                EXPORT  MCIA_IRQHandler           [WEAK]
+                EXPORT  MCIB_IRQHandler           [WEAK]
+                EXPORT  UART0_IRQHandler          [WEAK]
+                EXPORT  UART1_IRQHandler          [WEAK]
+                EXPORT  UART2_IRQHandler          [WEAK]
+                EXPORT  UART3_IRQHandler          [WEAK]
+                EXPORT  UART4_IRQHandler          [WEAK]
+                EXPORT  AACI_IRQHandler           [WEAK]
+                EXPORT  CLCD_IRQHandler           [WEAK]
+                EXPORT  ENET_IRQHandler           [WEAK]
+                EXPORT  USBDC_IRQHandler          [WEAK]
+                EXPORT  USBHC_IRQHandler          [WEAK]
+                EXPORT  CHLCD_IRQHandler          [WEAK]
+                EXPORT  FLEXRAY_IRQHandler        [WEAK]
+                EXPORT  CAN_IRQHandler            [WEAK]
+                EXPORT  LIN_IRQHandler            [WEAK]
+                EXPORT  I2C_IRQHandler            [WEAK]
+                EXPORT  CPU_CLCD_IRQHandler       [WEAK]
+                EXPORT  SPI_IRQHandler            [WEAK]
+
+WDT_IRQHandler
+RTC_IRQHandler
+TIM0_IRQHandler
+TIM2_IRQHandler
+MCIA_IRQHandler
+MCIB_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+UART4_IRQHandler
+AACI_IRQHandler
+CLCD_IRQHandler
+ENET_IRQHandler
+USBDC_IRQHandler
+USBHC_IRQHandler
+CHLCD_IRQHandler
+FLEXRAY_IRQHandler
+CAN_IRQHandler
+LIN_IRQHandler
+I2C_IRQHandler
+CPU_CLCD_IRQHandler
+SPI_IRQHandler
+                B       .
+
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap PROC
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+                ENDP
+
+                ALIGN
+
+                ENDIF
+
+
+                END

CMSIS/CoreValidation/Tests/Cortex-M7/AC5/RTE/Device/ARMCM7/system_ARMCM7.c

@@ -0,0 +1,85 @@
+/**************************************************************************//**
+ * @file     system_ARMCM7.c
+ * @brief    CMSIS Device System Source File for
+ *           ARMCM7 Device Series
+ * @version  V5.00
+ * @date     07. September 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM7)
+  #include "ARMCM7.h"
+#elif defined (ARMCM7_SP)
+  #include "ARMCM7_SP.h"
+#elif defined (ARMCM7_DP)
+  #include "ARMCM7_DP.h"
+#else
+  #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+
+#define  SYSTEM_CLOCK    (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+#if defined (__FPU_USED) && (__FPU_USED == 1U)
+  SCB->CPACR |= ((3U << 10U*2U) |           /* set CP10 Full Access */
+                 (3U << 11U*2U)  );         /* set CP11 Full Access */
+#endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+  SystemCoreClock = SYSTEM_CLOCK;
+}

CMSIS/CoreValidation/Tests/Cortex-M7/AC5/RTE/_FVP/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'CMSIS_CV' 
+ * Target:  'FVP' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "ARMCM7.h"
+
+
+#endif /* RTE_COMPONENTS_H */

CMSIS/CoreValidation/Tests/Cortex-M7/AC6/CMSIS_CV.uvprojx

@@ -0,0 +1,507 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>FVP</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pArmCC>6070000::V6.7::.\ARMCLANG</pArmCC>
+      <pCCUsed>6070000::V6.7::.\ARMCLANG</pCCUsed>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>ARMCM7</Device>
+          <Vendor>ARM</Vendor>
+          <PackID>ARM.CMSIS.5.1.2-dev1</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M7") CLOCK(12000000) ESEL ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:ARMCM7$Device\ARM\ARMCM7\Include\ARMCM7.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:ARMCM7$Device\ARM\SVD\ARMCM7.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\Objects\</OutputDirectory>
+          <OutputName>CMSIS_CV</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\Listings\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>  -MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM7</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> -MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM7</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>1</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M7"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>1</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <useXO>0</useXO>
+            <v6Lang>3</v6Lang>
+            <v6LangP>3</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls>-Wno-covered-switch-default</MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>.\,..\..\..\Include</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <uClangAs>0</uClangAs>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>.\,..\..\..\Include</IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange></TextAddressRange>
+            <DataAddressRange></DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc>--entry=Reset_Handler</Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Test</GroupName>
+          <Files>
+            <File>
+              <FileName>cmsis_cv.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\cmsis_cv.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_CoreFunc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_CoreFunc.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_CoreInstr.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_CoreInstr.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Framework.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_Framework.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_MPU_ARMv7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_MPU_ARMv7.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Report.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_Report.c</FilePath>
+            </File>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\main.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Config.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\CV_Config.h</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::CMSIS</GroupName>
+        </Group>
+        <Group>
+          <GroupName>::Device</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components>
+      <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.0.2" condition="ARMv6_7_8-M Device">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM7 CMSIS">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </component>
+    </components>
+    <files>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM0\Source\ARM\startup_ARMCM0.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM0\startup_ARMCM0.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM0\Source\system_ARMCM0.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM0\system_ARMCM0.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM3\Source\ARM\startup_ARMCM3.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM3\startup_ARMCM3.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM3\Source\system_ARMCM3.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM3\system_ARMCM3.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM4\Source\ARM\startup_ARMCM4.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM4\startup_ARMCM4.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM4\Source\system_ARMCM4.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM4\system_ARMCM4.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM7\Source\ARM\startup_ARMCM7.s" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM7\startup_ARMCM7.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM7 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM7\Source\system_ARMCM7.c" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM7\system_ARMCM7.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM7 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </file>
+    </files>
+  </RTE>
+
+</Project>

CMSIS/CoreValidation/Tests/Cortex-M7/AC6/CV_Config.h

@@ -0,0 +1,82 @@
+/*-----------------------------------------------------------------------------
+ *      Name:         CV_Config.h 
+ *      Purpose:      CV Config header
+ *----------------------------------------------------------------------------
+ *      Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+#ifndef __CV_CONFIG_H
+#define __CV_CONFIG_H
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+#define RTE_CV_COREINSTR 1
+#define RTE_CV_COREFUNC  1
+#define RTE_CV_MPUFUNC   1
+
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h> Common Test Settings
+// <o> Print Output Format <0=> Plain Text <1=> XML
+// <i> Set the test results output format to plain text or XML
+#ifndef PRINT_XML_REPORT
+#define PRINT_XML_REPORT            1
+#endif
+// <o> Buffer size for assertions results
+// <i> Set the buffer size for assertions results buffer
+#define BUFFER_ASSERTIONS           128U
+// </h>
+
+// <h> Disable Test Cases
+// <i> Uncheck to disable an individual test case
+// <q00> TC_CoreInstr_NOP
+// <q01> TC_CoreInstr_REV
+// <q02> TC_CoreInstr_REV16
+// <q03> TC_CoreInstr_REVSH
+// <q04> TC_CoreInstr_ROR
+// <q05> TC_CoreInstr_RBIT
+// <q06> TC_CoreInstr_CLZ
+// <q07> TC_CoreInstr_SSAT
+// <q08> TC_CoreInstr_USAT
+//
+// <q09> TC_CoreFunc_EnDisIRQ
+// <q10> TC_CoreFunc_Control
+// <q11> TC_CoreFunc_IPSR
+// <q12> TC_CoreFunc_APSR
+// <q13> TC_CoreFunc_PSP
+// <q14> TC_CoreFunc_MSP
+// <q15> TC_CoreFunc_PRIMASK
+// <q16> TC_CoreFunc_FAULTMASK
+// <q17> TC_CoreFunc_BASEPRI
+// <q18> TC_CoreFunc_FPSCR
+//
+// <q19> TC_MPU_SetClear
+// <q20> TC_MPU_Load
+#define TC_COREINSTR_NOP_EN         1
+#define TC_COREINSTR_REV_EN         1
+#define TC_COREINSTR_REV16_EN       1
+#define TC_COREINSTR_REVSH_EN       1
+#define TC_COREINSTR_ROR_EN         1
+#define TC_COREINSTR_RBIT_EN        1
+#define TC_COREINSTR_CLZ_EN         1
+#define TC_COREINSTR_SSAT_EN        1
+#define TC_COREINSTR_USAT_EN        1
+
+#define TC_COREFUNC_ENDISIRQ_EN     1
+#define TC_COREFUNC_CONTROL_EN      1
+#define TC_COREFUNC_IPSR_EN         1
+#define TC_COREFUNC_APSR_EN         1
+#define TC_COREFUNC_PSP_EN          1
+#define TC_COREFUNC_MSP_EN          1
+#define TC_COREFUNC_PRIMASK_EN      1
+#define TC_COREFUNC_FAULTMASK_EN    1
+#define TC_COREFUNC_BASEPRI_EN      1
+#define TC_COREFUNC_FPSCR_EN        1
+
+#define TC_MPU_SETCLEAR_EN          1
+#define TC_MPU_LOAD_EN              1
+// </h>
+
+#endif /* __CV_CONFIG_H */
+

CMSIS/CoreValidation/Tests/Cortex-M7/AC6/EventRecorderStub.scvd

@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
+
+<component name="EventRecorderStub" version="1.0.0"/>       <!--name and version of the component-->
+  <events>
+  </events>
+
+</component_viewer>

CMSIS/CoreValidation/Tests/Cortex-M7/AC6/RTE/Device/ARMCM7/startup_ARMCM7.s

@@ -0,0 +1,262 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM7.s
+; * @brief    CMSIS Core Device Startup File for
+; *           ARMCM7 Device Series
+; * @version  V5.00
+; * @date     02. March 2016
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000C00
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
+                DCD     RTC_IRQHandler            ;  1:  Real Time Clock
+                DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
+                DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
+                DCD     MCIA_IRQHandler           ;  4:  MCIa
+                DCD     MCIB_IRQHandler           ;  5:  MCIb
+                DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
+                DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
+                DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
+                DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
+                DCD     AACI_IRQHandler           ; 10: AACI / AC97
+                DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
+                DCD     ENET_IRQHandler           ; 12: Ethernet
+                DCD     USBDC_IRQHandler          ; 13: USB Device
+                DCD     USBHC_IRQHandler          ; 14: USB Host Controller
+                DCD     CHLCD_IRQHandler          ; 15: Character LCD
+                DCD     FLEXRAY_IRQHandler        ; 16: Flexray
+                DCD     CAN_IRQHandler            ; 17: CAN
+                DCD     LIN_IRQHandler            ; 18: LIN
+                DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
+                DCD     0                         ; 20: Reserved
+                DCD     0                         ; 21: Reserved
+                DCD     0                         ; 22: Reserved
+                DCD     0                         ; 23: Reserved
+                DCD     0                         ; 24: Reserved
+                DCD     0                         ; 25: Reserved
+                DCD     0                         ; 26: Reserved
+                DCD     0                         ; 27: Reserved
+                DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
+                DCD     0                         ; 29: Reserved - CPU FPGA
+                DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
+                DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WDT_IRQHandler            [WEAK]
+                EXPORT  RTC_IRQHandler            [WEAK]
+                EXPORT  TIM0_IRQHandler           [WEAK]
+                EXPORT  TIM2_IRQHandler           [WEAK]
+                EXPORT  MCIA_IRQHandler           [WEAK]
+                EXPORT  MCIB_IRQHandler           [WEAK]
+                EXPORT  UART0_IRQHandler          [WEAK]
+                EXPORT  UART1_IRQHandler          [WEAK]
+                EXPORT  UART2_IRQHandler          [WEAK]
+                EXPORT  UART3_IRQHandler          [WEAK]
+                EXPORT  UART4_IRQHandler          [WEAK]
+                EXPORT  AACI_IRQHandler           [WEAK]
+                EXPORT  CLCD_IRQHandler           [WEAK]
+                EXPORT  ENET_IRQHandler           [WEAK]
+                EXPORT  USBDC_IRQHandler          [WEAK]
+                EXPORT  USBHC_IRQHandler          [WEAK]
+                EXPORT  CHLCD_IRQHandler          [WEAK]
+                EXPORT  FLEXRAY_IRQHandler        [WEAK]
+                EXPORT  CAN_IRQHandler            [WEAK]
+                EXPORT  LIN_IRQHandler            [WEAK]
+                EXPORT  I2C_IRQHandler            [WEAK]
+                EXPORT  CPU_CLCD_IRQHandler       [WEAK]
+                EXPORT  SPI_IRQHandler            [WEAK]
+
+WDT_IRQHandler
+RTC_IRQHandler
+TIM0_IRQHandler
+TIM2_IRQHandler
+MCIA_IRQHandler
+MCIB_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+UART4_IRQHandler
+AACI_IRQHandler
+CLCD_IRQHandler
+ENET_IRQHandler
+USBDC_IRQHandler
+USBHC_IRQHandler
+CHLCD_IRQHandler
+FLEXRAY_IRQHandler
+CAN_IRQHandler
+LIN_IRQHandler
+I2C_IRQHandler
+CPU_CLCD_IRQHandler
+SPI_IRQHandler
+                B       .
+
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap PROC
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+                ENDP
+
+                ALIGN
+
+                ENDIF
+
+
+                END

CMSIS/CoreValidation/Tests/Cortex-M7/AC6/RTE/Device/ARMCM7/system_ARMCM7.c

@@ -0,0 +1,85 @@
+/**************************************************************************//**
+ * @file     system_ARMCM7.c
+ * @brief    CMSIS Device System Source File for
+ *           ARMCM7 Device Series
+ * @version  V5.00
+ * @date     07. September 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM7)
+  #include "ARMCM7.h"
+#elif defined (ARMCM7_SP)
+  #include "ARMCM7_SP.h"
+#elif defined (ARMCM7_DP)
+  #include "ARMCM7_DP.h"
+#else
+  #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+
+#define  SYSTEM_CLOCK    (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+#if defined (__FPU_USED) && (__FPU_USED == 1U)
+  SCB->CPACR |= ((3U << 10U*2U) |           /* set CP10 Full Access */
+                 (3U << 11U*2U)  );         /* set CP11 Full Access */
+#endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+  SystemCoreClock = SYSTEM_CLOCK;
+}

CMSIS/CoreValidation/Tests/Cortex-M7/AC6/RTE/_FVP/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'CMSIS_CV' 
+ * Target:  'FVP' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "ARMCM7.h"
+
+
+#endif /* RTE_COMPONENTS_H */

CMSIS/CoreValidation/Tests/Cortex-M7/GCC/CMSIS_CV.uvprojx

@@ -0,0 +1,434 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>FVP</TargetName>
+      <ToolsetNumber>0x3</ToolsetNumber>
+      <ToolsetName>ARM-GNU</ToolsetName>
+      <pArmCC>6070000::V6.7::.\ARMCLANG</pArmCC>
+      <pCCUsed>6070000::V6.7::.\ARMCLANG</pCCUsed>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>ARMCM7</Device>
+          <Vendor>ARM</Vendor>
+          <PackID>ARM.CMSIS.5.1.2-dev1</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M7") CLOCK(12000000) ESEL ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:ARMCM7$Device\ARM\ARMCM7\Include\ARMCM7.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:ARMCM7$Device\ARM\SVD\ARMCM7.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\Objects\</OutputDirectory>
+          <OutputName>CMSIS_CV</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\Listings\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>  -MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM7</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> -MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM7</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArm>
+          <ArmMisc>
+            <asLst>1</asLst>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>1</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <GCPUTYP>"Cortex-M7"</GCPUTYP>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <IRAM2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </IRAM2>
+              <IROM2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </IROM2>
+            </OnChipMemories>
+          </ArmMisc>
+          <Carm>
+            <arpcs>1</arpcs>
+            <stkchk>0</stkchk>
+            <reentr>0</reentr>
+            <interw>1</interw>
+            <bigend>0</bigend>
+            <Strict>0</Strict>
+            <Optim>1</Optim>
+            <wLevel>3</wLevel>
+            <uThumb>1</uThumb>
+            <VariousControls>
+              <MiscControls>-mfloat-abi=soft -Wall -Wextra -Wstrict-prototypes -Wshadow</MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>.;..\..\..\Include</IncludePath>
+            </VariousControls>
+          </Carm>
+          <Aarm>
+            <bBE>0</bBE>
+            <interw>1</interw>
+            <VariousControls>
+              <MiscControls>-mfloat-abi=soft -Wall</MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>.;..\..\..\Include</IncludePath>
+            </VariousControls>
+          </Aarm>
+          <LDarm>
+            <umfTarg>1</umfTarg>
+            <enaGarb>0</enaGarb>
+            <noStart>0</noStart>
+            <noStLib>0</noStLib>
+            <uMathLib>0</uMathLib>
+            <TextAddressRange></TextAddressRange>
+            <DataAddressRange></DataAddressRange>
+            <BSSAddressRange></BSSAddressRange>
+            <IncludeLibs></IncludeLibs>
+            <IncludeDir></IncludeDir>
+            <Misc>-mfloat-abi=soft --specs=rdimon.specs</Misc>
+            <ScatterFile>.\RTE\Device\ARMCM7\gcc_arm.ld</ScatterFile>
+          </LDarm>
+        </TargetArm>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Test</GroupName>
+          <Files>
+            <File>
+              <FileName>cmsis_cv.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\cmsis_cv.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_CoreFunc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_CoreFunc.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_CoreInstr.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_CoreInstr.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Framework.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_Framework.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_MPU_ARMv7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_MPU_ARMv7.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Report.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_Report.c</FilePath>
+            </File>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\main.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Config.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\CV_Config.h</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::CMSIS</GroupName>
+        </Group>
+        <Group>
+          <GroupName>::Device</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components>
+      <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.0.2" condition="ARMv6_7_8-M Device">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM7 CMSIS GCC">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </component>
+    </components>
+    <files>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM0\Source\ARM\startup_ARMCM0.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM0\startup_ARMCM0.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM0\Source\system_ARMCM0.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM0\system_ARMCM0.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="linkerScript" condition="GCC" name="Device\ARM\ARMCM3\Source\GCC\gcc_arm.ld" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM3\gcc_arm.ld</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceAsm" condition="GCC" name="Device\ARM\ARMCM3\Source\GCC\startup_ARMCM3.S" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM3\startup_ARMCM3.S</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" condition="GCC" name="Device\ARM\ARMCM3\Source\GCC\startup_ARMCM3.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM3\startup_ARMCM3.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM3\Source\system_ARMCM3.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM3\system_ARMCM3.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="linkerScript" condition="GCC" name="Device\ARM\ARMCM4\Source\GCC\gcc_arm.ld" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM4\gcc_arm.ld</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" condition="GCC" name="Device\ARM\ARMCM4\Source\GCC\startup_ARMCM4.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM4\startup_ARMCM4.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM4\Source\ARM\startup_ARMCM4.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM4\startup_ARMCM4.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM4\Source\system_ARMCM4.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM4\system_ARMCM4.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="linkerScript" condition="GCC" name="Device\ARM\ARMCM7\Source\GCC\gcc_arm.ld" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM7\gcc_arm.ld</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM7 CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="sourceC" condition="GCC" name="Device\ARM\ARMCM7\Source\GCC\startup_ARMCM7.c" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM7\startup_ARMCM7.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM7 CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM7\Source\system_ARMCM7.c" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM7\system_ARMCM7.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM7 CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </file>
+    </files>
+  </RTE>
+
+</Project>

CMSIS/CoreValidation/Tests/Cortex-M7/GCC/CV_Config.h

@@ -0,0 +1,82 @@
+/*-----------------------------------------------------------------------------
+ *      Name:         CV_Config.h 
+ *      Purpose:      CV Config header
+ *----------------------------------------------------------------------------
+ *      Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+#ifndef __CV_CONFIG_H
+#define __CV_CONFIG_H
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+#define RTE_CV_COREINSTR 1
+#define RTE_CV_COREFUNC  1
+#define RTE_CV_MPUFUNC   1
+
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h> Common Test Settings
+// <o> Print Output Format <0=> Plain Text <1=> XML
+// <i> Set the test results output format to plain text or XML
+#ifndef PRINT_XML_REPORT
+#define PRINT_XML_REPORT            1
+#endif
+// <o> Buffer size for assertions results
+// <i> Set the buffer size for assertions results buffer
+#define BUFFER_ASSERTIONS           128U
+// </h>
+
+// <h> Disable Test Cases
+// <i> Uncheck to disable an individual test case
+// <q00> TC_CoreInstr_NOP
+// <q01> TC_CoreInstr_REV
+// <q02> TC_CoreInstr_REV16
+// <q03> TC_CoreInstr_REVSH
+// <q04> TC_CoreInstr_ROR
+// <q05> TC_CoreInstr_RBIT
+// <q06> TC_CoreInstr_CLZ
+// <q07> TC_CoreInstr_SSAT
+// <q08> TC_CoreInstr_USAT
+//
+// <q09> TC_CoreFunc_EnDisIRQ
+// <q10> TC_CoreFunc_Control
+// <q11> TC_CoreFunc_IPSR
+// <q12> TC_CoreFunc_APSR
+// <q13> TC_CoreFunc_PSP
+// <q14> TC_CoreFunc_MSP
+// <q15> TC_CoreFunc_PRIMASK
+// <q16> TC_CoreFunc_FAULTMASK
+// <q17> TC_CoreFunc_BASEPRI
+// <q18> TC_CoreFunc_FPSCR
+//
+// <q19> TC_MPU_SetClear
+// <q20> TC_MPU_Load
+#define TC_COREINSTR_NOP_EN         1
+#define TC_COREINSTR_REV_EN         1
+#define TC_COREINSTR_REV16_EN       1
+#define TC_COREINSTR_REVSH_EN       1
+#define TC_COREINSTR_ROR_EN         1
+#define TC_COREINSTR_RBIT_EN        1
+#define TC_COREINSTR_CLZ_EN         1
+#define TC_COREINSTR_SSAT_EN        1
+#define TC_COREINSTR_USAT_EN        1
+
+#define TC_COREFUNC_ENDISIRQ_EN     1
+#define TC_COREFUNC_CONTROL_EN      1
+#define TC_COREFUNC_IPSR_EN         1
+#define TC_COREFUNC_APSR_EN         1
+#define TC_COREFUNC_PSP_EN          1
+#define TC_COREFUNC_MSP_EN          1
+#define TC_COREFUNC_PRIMASK_EN      1
+#define TC_COREFUNC_FAULTMASK_EN    1
+#define TC_COREFUNC_BASEPRI_EN      1
+#define TC_COREFUNC_FPSCR_EN        1
+
+#define TC_MPU_SETCLEAR_EN          1
+#define TC_MPU_LOAD_EN              1
+// </h>
+
+#endif /* __CV_CONFIG_H */
+

CMSIS/CoreValidation/Tests/Cortex-M7/GCC/EventRecorderStub.scvd

@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
+
+<component name="EventRecorderStub" version="1.0.0"/>       <!--name and version of the component-->
+  <events>
+  </events>
+
+</component_viewer>

CMSIS/CoreValidation/Tests/Cortex-M7/GCC/RTE/Device/ARMCM7/gcc_arm.ld

@@ -0,0 +1,196 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+  FLASH (rx)  : ORIGIN = 0x00000000, LENGTH = 512K
+  RAM   (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapBase
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __Vectors_End
+ *   __Vectors_Size
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+	.text :
+	{
+		KEEP(*(.vectors))
+		__Vectors_End = .;
+		__Vectors_Size = __Vectors_End - __Vectors;
+		__end__ = .;
+
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+	.ARM.extab :
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	/* To copy multiple ROM to RAM sections,
+	 * uncomment .copy.table section and,
+	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.copy.table :
+	{
+		. = ALIGN(4);
+		__copy_table_start__ = .;
+		LONG (__etext)
+		LONG (__data_start__)
+		LONG (__data_end__ - __data_start__)
+		LONG (__etext2)
+		LONG (__data2_start__)
+		LONG (__data2_end__ - __data2_start__)
+		__copy_table_end__ = .;
+	} > FLASH
+	*/
+
+	/* To clear multiple BSS sections,
+	 * uncomment .zero.table section and,
+	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.zero.table :
+	{
+		. = ALIGN(4);
+		__zero_table_start__ = .;
+		LONG (__bss_start__)
+		LONG (__bss_end__ - __bss_start__)
+		LONG (__bss2_start__)
+		LONG (__bss2_end__ - __bss2_start__)
+		__zero_table_end__ = .;
+	} > FLASH
+	*/
+
+	__etext = .;
+
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		KEEP(*(.jcr*))
+		. = ALIGN(4);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > RAM
+
+	.heap (COPY):
+	{
+		__HeapBase = .;
+		__end__ = .;
+		end = __end__;
+		KEEP(*(.heap*))
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (COPY):
+	{
+		KEEP(*(.stack*))
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM);
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}

CMSIS/CoreValidation/Tests/Cortex-M7/GCC/RTE/Device/ARMCM7/startup_ARMCM7.c

@@ -0,0 +1,295 @@
+/**************************************************************************//**
+ * @file     startup_ARMCM7.s
+ * @brief    CMSIS Core Device Startup File for
+ *           ARMCM7 Device Series
+ * @version  V5.00
+ * @date     26. April 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdint.h>
+
+
+/*----------------------------------------------------------------------------
+  Linker generated Symbols
+ *----------------------------------------------------------------------------*/
+extern uint32_t __etext;
+extern uint32_t __data_start__;
+extern uint32_t __data_end__;
+extern uint32_t __copy_table_start__;
+extern uint32_t __copy_table_end__;
+extern uint32_t __zero_table_start__;
+extern uint32_t __zero_table_end__;
+extern uint32_t __bss_start__;
+extern uint32_t __bss_end__;
+extern uint32_t __StackTop;
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler Function Prototype
+ *----------------------------------------------------------------------------*/
+typedef void( *pFunc )( void );
+
+
+/*----------------------------------------------------------------------------
+  External References
+ *----------------------------------------------------------------------------*/
+#ifndef __START
+extern void  _start(void) __attribute__((noreturn));    /* PreeMain (C library entry point) */
+#else
+extern int  __START(void) __attribute__((noreturn));    /* main entry point */
+#endif
+
+#ifndef __NO_SYSTEM_INIT
+extern void SystemInit (void);            /* CMSIS System Initialization      */
+#endif
+
+
+/*----------------------------------------------------------------------------
+  Internal References
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void);                          /* Default empty handler */
+void Reset_Handler(void);                            /* Reset Handler */
+
+
+/*----------------------------------------------------------------------------
+  User Initial Stack & Heap
+ *----------------------------------------------------------------------------*/
+#ifndef __STACK_SIZE
+  #define	__STACK_SIZE  0x00000400
+#endif
+static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack")));
+
+#ifndef __HEAP_SIZE
+  #define	__HEAP_SIZE   0x00000C00
+#endif
+#if __HEAP_SIZE > 0
+static uint8_t heap[__HEAP_SIZE]   __attribute__ ((aligned(8), used, section(".heap")));
+#endif
+
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Cortex-M7 Processor Exceptions */
+void NMI_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void MemManage_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/* ARMCM7 Specific Interrupts */
+void WDT_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void RTC_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void TIM0_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void TIM2_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void MCIA_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void MCIB_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART0_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART1_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART2_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART4_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void AACI_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void CLCD_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void ENET_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void USBDC_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void USBHC_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void CHLCD_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void FLEXRAY_IRQHandler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void CAN_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void LIN_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void I2C_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void CPU_CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART3_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void SPI_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = {
+  /* Cortex-M7 Exceptions Handler */
+  (pFunc)((uint32_t)&__StackTop),           /*      Initial Stack Pointer     */
+  Reset_Handler,                            /*      Reset Handler             */
+  NMI_Handler,                              /*      NMI Handler               */
+  HardFault_Handler,                        /*      Hard Fault Handler        */
+  MemManage_Handler,                        /*      MPU Fault Handler         */
+  BusFault_Handler,                         /*      Bus Fault Handler         */
+  UsageFault_Handler,                       /*      Usage Fault Handler       */
+  0,                                        /*      Reserved                  */
+  0,                                        /*      Reserved                  */
+  0,                                        /*      Reserved                  */
+  0,                                        /*      Reserved                  */
+  SVC_Handler,                              /*      SVCall Handler            */
+  DebugMon_Handler,                         /*      Debug Monitor Handler     */
+  0,                                        /*      Reserved                  */
+  PendSV_Handler,                           /*      PendSV Handler            */
+  SysTick_Handler,                          /*      SysTick Handler           */
+
+  /* External interrupts */
+  WDT_IRQHandler,                           /*  0:  Watchdog Timer            */
+  RTC_IRQHandler,                           /*  1:  Real Time Clock           */
+  TIM0_IRQHandler,                          /*  2:  Timer0 / Timer1           */
+  TIM2_IRQHandler,                          /*  3:  Timer2 / Timer3           */
+  MCIA_IRQHandler,                          /*  4:  MCIa                      */
+  MCIB_IRQHandler,                          /*  5:  MCIb                      */
+  UART0_IRQHandler,                         /*  6:  UART0 - DUT FPGA          */
+  UART1_IRQHandler,                         /*  7:  UART1 - DUT FPGA          */
+  UART2_IRQHandler,                         /*  8:  UART2 - DUT FPGA          */
+  UART4_IRQHandler,                         /*  9:  UART4 - not connected     */
+  AACI_IRQHandler,                          /* 10: AACI / AC97                */
+  CLCD_IRQHandler,                          /* 11: CLCD Combined Interrupt    */
+  ENET_IRQHandler,                          /* 12: Ethernet                   */
+  USBDC_IRQHandler,                         /* 13: USB Device                 */
+  USBHC_IRQHandler,                         /* 14: USB Host Controller        */
+  CHLCD_IRQHandler,                         /* 15: Character LCD              */
+  FLEXRAY_IRQHandler,                       /* 16: Flexray                    */
+  CAN_IRQHandler,                           /* 17: CAN                        */
+  LIN_IRQHandler,                           /* 18: LIN                        */
+  I2C_IRQHandler,                           /* 19: I2C ADC/DAC                */
+  0,                                        /* 20: Reserved                   */
+  0,                                        /* 21: Reserved                   */
+  0,                                        /* 22: Reserved                   */
+  0,                                        /* 23: Reserved                   */
+  0,                                        /* 24: Reserved                   */
+  0,                                        /* 25: Reserved                   */
+  0,                                        /* 26: Reserved                   */
+  0,                                        /* 27: Reserved                   */
+  CPU_CLCD_IRQHandler,                      /* 28: Reserved - CPU FPGA CLCD   */
+  0,                                        /* 29: Reserved - CPU FPGA        */
+  UART3_IRQHandler,                         /* 30: UART3    - CPU FPGA        */
+  SPI_IRQHandler                            /* 31: SPI Touchscreen - CPU FPGA */
+};
+
+
+/*----------------------------------------------------------------------------
+  Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+  uint32_t *pSrc, *pDest;
+  uint32_t *pTable __attribute__((unused));
+
+/*  Firstly it copies data from read only memory to RAM. There are two schemes
+ *  to copy. One can copy more than one sections. Another can only copy
+ *  one section.  The former scheme needs more instructions and read-only
+ *  data to implement than the latter.
+ *  Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.  */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/*  Multiple sections scheme.
+ *
+ *  Between symbol address __copy_table_start__ and __copy_table_end__,
+ *  there are array of triplets, each of which specify:
+ *    offset 0: LMA of start of a section to copy from
+ *    offset 4: VMA of start of a section to copy to
+ *    offset 8: size of the section to copy. Must be multiply of 4
+ *
+ *  All addresses must be aligned to 4 bytes boundary.
+ */
+  pTable = &__copy_table_start__;
+
+  for (; pTable < &__copy_table_end__; pTable = pTable + 3) {
+		pSrc  = (uint32_t*)*(pTable + 0);
+		pDest = (uint32_t*)*(pTable + 1);
+		for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
+      *pDest++ = *pSrc++;
+		}
+	}
+#else
+/*  Single section scheme.
+ *
+ *  The ranges of copy from/to are specified by following symbols
+ *    __etext: LMA of start of the section to copy from. Usually end of text
+ *    __data_start__: VMA of start of the section to copy to
+ *    __data_end__: VMA of end of the section to copy to
+ *
+ *  All addresses must be aligned to 4 bytes boundary.
+ */
+  pSrc  = &__etext;
+  pDest = &__data_start__;
+
+  for ( ; pDest < &__data_end__ ; ) {
+    *pDest++ = *pSrc++;
+  }
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/*  This part of work usually is done in C library startup code. Otherwise,
+ *  define this macro to enable it in this startup.
+ *
+ *  There are two schemes too. One can clear multiple BSS sections. Another
+ *  can only clear one section. The former is more size expensive than the
+ *  latter.
+ *
+ *  Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ *  Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/*  Multiple sections scheme.
+ *
+ *  Between symbol address __copy_table_start__ and __copy_table_end__,
+ *  there are array of tuples specifying:
+ *    offset 0: Start of a BSS section
+ *    offset 4: Size of this BSS section. Must be multiply of 4
+ */
+  pTable = &__zero_table_start__;
+
+  for (; pTable < &__zero_table_end__; pTable = pTable + 2) {
+		pDest = (uint32_t*)*(pTable + 0);
+		for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
+      *pDest++ = 0;
+		}
+	}
+#elif defined (__STARTUP_CLEAR_BSS)
+/*  Single BSS section scheme.
+ *
+ *  The BSS section is specified by following symbols
+ *    __bss_start__: start of the BSS section.
+ *    __bss_end__: end of the BSS section.
+ *
+ *  Both addresses must be aligned to 4 bytes boundary.
+ */
+  pDest = &__bss_start__;
+
+  for ( ; pDest < &__bss_end__ ; ) {
+    *pDest++ = 0UL;
+  }
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+#ifndef __NO_SYSTEM_INIT
+	SystemInit();
+#endif
+
+#ifndef __START
+#define __START _start
+#endif
+	__START();
+
+}
+
+
+/*----------------------------------------------------------------------------
+  Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+
+	while(1);
+}

CMSIS/CoreValidation/Tests/Cortex-M7/GCC/RTE/Device/ARMCM7/system_ARMCM7.c

@@ -0,0 +1,85 @@
+/**************************************************************************//**
+ * @file     system_ARMCM7.c
+ * @brief    CMSIS Device System Source File for
+ *           ARMCM7 Device Series
+ * @version  V5.00
+ * @date     07. September 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM7)
+  #include "ARMCM7.h"
+#elif defined (ARMCM7_SP)
+  #include "ARMCM7_SP.h"
+#elif defined (ARMCM7_DP)
+  #include "ARMCM7_DP.h"
+#else
+  #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+
+#define  SYSTEM_CLOCK    (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+#if defined (__FPU_USED) && (__FPU_USED == 1U)
+  SCB->CPACR |= ((3U << 10U*2U) |           /* set CP10 Full Access */
+                 (3U << 11U*2U)  );         /* set CP11 Full Access */
+#endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+  SystemCoreClock = SYSTEM_CLOCK;
+}

CMSIS/CoreValidation/Tests/Cortex-M7/GCC/RTE/_FVP/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'CMSIS_CV' 
+ * Target:  'FVP' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "ARMCM7.h"
+
+
+#endif /* RTE_COMPONENTS_H */

CMSIS/CoreValidation/Tests/Cortex-M7DP/AC5/CMSIS_CV.uvprojx

@@ -0,0 +1,507 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>FVP</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pArmCC>5060528::V5.06 update 5 (build 528)::ARMCC</pArmCC>
+      <pCCUsed>5060528::V5.06 update 5 (build 528)::ARMCC</pCCUsed>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>ARMCM7_DP</Device>
+          <Vendor>ARM</Vendor>
+          <PackID>ARM.CMSIS.5.1.2-dev1</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ESEL ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:ARMCM7_DP$Device\ARM\ARMCM7\Include\ARMCM7_DP.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:ARMCM7_DP$Device\ARM\SVD\ARMCM7.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\Objects\</OutputDirectory>
+          <OutputName>CMSIS_CV</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\Listings\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>  -MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM7</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> -MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM7</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>1</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M7"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>3</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>1</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <useXO>0</useXO>
+            <v6Lang>3</v6Lang>
+            <v6LangP>3</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>.\,..\..\..\Include</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <uClangAs>0</uClangAs>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>.\,..\..\..\Include</IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange></TextAddressRange>
+            <DataAddressRange></DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc>--entry=Reset_Handler</Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Test</GroupName>
+          <Files>
+            <File>
+              <FileName>cmsis_cv.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\cmsis_cv.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_CoreFunc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_CoreFunc.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_CoreInstr.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_CoreInstr.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Framework.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_Framework.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_MPU_ARMv7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_MPU_ARMv7.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Report.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_Report.c</FilePath>
+            </File>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\main.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Config.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\CV_Config.h</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::CMSIS</GroupName>
+        </Group>
+        <Group>
+          <GroupName>::Device</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components>
+      <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.0.2" condition="ARMv6_7_8-M Device">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM7 CMSIS">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </component>
+    </components>
+    <files>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM0\Source\ARM\startup_ARMCM0.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM0\startup_ARMCM0.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM0\Source\system_ARMCM0.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM0\system_ARMCM0.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM3\Source\ARM\startup_ARMCM3.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM3\startup_ARMCM3.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM3\Source\system_ARMCM3.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM3\system_ARMCM3.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM4\Source\ARM\startup_ARMCM4.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM4\startup_ARMCM4.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM4\Source\system_ARMCM4.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM4\system_ARMCM4.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM7\Source\ARM\startup_ARMCM7.s" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM7_DP\startup_ARMCM7.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM7 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM7\Source\system_ARMCM7.c" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM7_DP\system_ARMCM7.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM7 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </file>
+    </files>
+  </RTE>
+
+</Project>

CMSIS/CoreValidation/Tests/Cortex-M7DP/AC5/CV_Config.h

@@ -0,0 +1,82 @@
+/*-----------------------------------------------------------------------------
+ *      Name:         CV_Config.h 
+ *      Purpose:      CV Config header
+ *----------------------------------------------------------------------------
+ *      Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+#ifndef __CV_CONFIG_H
+#define __CV_CONFIG_H
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+#define RTE_CV_COREINSTR 1
+#define RTE_CV_COREFUNC  1
+#define RTE_CV_MPUFUNC   1
+
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h> Common Test Settings
+// <o> Print Output Format <0=> Plain Text <1=> XML
+// <i> Set the test results output format to plain text or XML
+#ifndef PRINT_XML_REPORT
+#define PRINT_XML_REPORT            1
+#endif
+// <o> Buffer size for assertions results
+// <i> Set the buffer size for assertions results buffer
+#define BUFFER_ASSERTIONS           128U
+// </h>
+
+// <h> Disable Test Cases
+// <i> Uncheck to disable an individual test case
+// <q00> TC_CoreInstr_NOP
+// <q01> TC_CoreInstr_REV
+// <q02> TC_CoreInstr_REV16
+// <q03> TC_CoreInstr_REVSH
+// <q04> TC_CoreInstr_ROR
+// <q05> TC_CoreInstr_RBIT
+// <q06> TC_CoreInstr_CLZ
+// <q07> TC_CoreInstr_SSAT
+// <q08> TC_CoreInstr_USAT
+//
+// <q09> TC_CoreFunc_EnDisIRQ
+// <q10> TC_CoreFunc_Control
+// <q11> TC_CoreFunc_IPSR
+// <q12> TC_CoreFunc_APSR
+// <q13> TC_CoreFunc_PSP
+// <q14> TC_CoreFunc_MSP
+// <q15> TC_CoreFunc_PRIMASK
+// <q16> TC_CoreFunc_FAULTMASK
+// <q17> TC_CoreFunc_BASEPRI
+// <q18> TC_CoreFunc_FPSCR
+//
+// <q19> TC_MPU_SetClear
+// <q20> TC_MPU_Load
+#define TC_COREINSTR_NOP_EN         1
+#define TC_COREINSTR_REV_EN         1
+#define TC_COREINSTR_REV16_EN       1
+#define TC_COREINSTR_REVSH_EN       1
+#define TC_COREINSTR_ROR_EN         1
+#define TC_COREINSTR_RBIT_EN        1
+#define TC_COREINSTR_CLZ_EN         1
+#define TC_COREINSTR_SSAT_EN        1
+#define TC_COREINSTR_USAT_EN        1
+
+#define TC_COREFUNC_ENDISIRQ_EN     1
+#define TC_COREFUNC_CONTROL_EN      1
+#define TC_COREFUNC_IPSR_EN         1
+#define TC_COREFUNC_APSR_EN         1
+#define TC_COREFUNC_PSP_EN          1
+#define TC_COREFUNC_MSP_EN          1
+#define TC_COREFUNC_PRIMASK_EN      1
+#define TC_COREFUNC_FAULTMASK_EN    1
+#define TC_COREFUNC_BASEPRI_EN      1
+#define TC_COREFUNC_FPSCR_EN        1
+
+#define TC_MPU_SETCLEAR_EN          1
+#define TC_MPU_LOAD_EN              1
+// </h>
+
+#endif /* __CV_CONFIG_H */
+

CMSIS/CoreValidation/Tests/Cortex-M7DP/AC5/EventRecorderStub.scvd

@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
+
+<component name="EventRecorderStub" version="1.0.0"/>       <!--name and version of the component-->
+  <events>
+  </events>
+
+</component_viewer>

CMSIS/CoreValidation/Tests/Cortex-M7DP/AC5/RTE/Device/ARMCM7_DP/startup_ARMCM7.s

@@ -0,0 +1,262 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM7.s
+; * @brief    CMSIS Core Device Startup File for
+; *           ARMCM7 Device Series
+; * @version  V5.00
+; * @date     02. March 2016
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000C00
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
+                DCD     RTC_IRQHandler            ;  1:  Real Time Clock
+                DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
+                DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
+                DCD     MCIA_IRQHandler           ;  4:  MCIa
+                DCD     MCIB_IRQHandler           ;  5:  MCIb
+                DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
+                DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
+                DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
+                DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
+                DCD     AACI_IRQHandler           ; 10: AACI / AC97
+                DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
+                DCD     ENET_IRQHandler           ; 12: Ethernet
+                DCD     USBDC_IRQHandler          ; 13: USB Device
+                DCD     USBHC_IRQHandler          ; 14: USB Host Controller
+                DCD     CHLCD_IRQHandler          ; 15: Character LCD
+                DCD     FLEXRAY_IRQHandler        ; 16: Flexray
+                DCD     CAN_IRQHandler            ; 17: CAN
+                DCD     LIN_IRQHandler            ; 18: LIN
+                DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
+                DCD     0                         ; 20: Reserved
+                DCD     0                         ; 21: Reserved
+                DCD     0                         ; 22: Reserved
+                DCD     0                         ; 23: Reserved
+                DCD     0                         ; 24: Reserved
+                DCD     0                         ; 25: Reserved
+                DCD     0                         ; 26: Reserved
+                DCD     0                         ; 27: Reserved
+                DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
+                DCD     0                         ; 29: Reserved - CPU FPGA
+                DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
+                DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WDT_IRQHandler            [WEAK]
+                EXPORT  RTC_IRQHandler            [WEAK]
+                EXPORT  TIM0_IRQHandler           [WEAK]
+                EXPORT  TIM2_IRQHandler           [WEAK]
+                EXPORT  MCIA_IRQHandler           [WEAK]
+                EXPORT  MCIB_IRQHandler           [WEAK]
+                EXPORT  UART0_IRQHandler          [WEAK]
+                EXPORT  UART1_IRQHandler          [WEAK]
+                EXPORT  UART2_IRQHandler          [WEAK]
+                EXPORT  UART3_IRQHandler          [WEAK]
+                EXPORT  UART4_IRQHandler          [WEAK]
+                EXPORT  AACI_IRQHandler           [WEAK]
+                EXPORT  CLCD_IRQHandler           [WEAK]
+                EXPORT  ENET_IRQHandler           [WEAK]
+                EXPORT  USBDC_IRQHandler          [WEAK]
+                EXPORT  USBHC_IRQHandler          [WEAK]
+                EXPORT  CHLCD_IRQHandler          [WEAK]
+                EXPORT  FLEXRAY_IRQHandler        [WEAK]
+                EXPORT  CAN_IRQHandler            [WEAK]
+                EXPORT  LIN_IRQHandler            [WEAK]
+                EXPORT  I2C_IRQHandler            [WEAK]
+                EXPORT  CPU_CLCD_IRQHandler       [WEAK]
+                EXPORT  SPI_IRQHandler            [WEAK]
+
+WDT_IRQHandler
+RTC_IRQHandler
+TIM0_IRQHandler
+TIM2_IRQHandler
+MCIA_IRQHandler
+MCIB_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+UART4_IRQHandler
+AACI_IRQHandler
+CLCD_IRQHandler
+ENET_IRQHandler
+USBDC_IRQHandler
+USBHC_IRQHandler
+CHLCD_IRQHandler
+FLEXRAY_IRQHandler
+CAN_IRQHandler
+LIN_IRQHandler
+I2C_IRQHandler
+CPU_CLCD_IRQHandler
+SPI_IRQHandler
+                B       .
+
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap PROC
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+                ENDP
+
+                ALIGN
+
+                ENDIF
+
+
+                END

CMSIS/CoreValidation/Tests/Cortex-M7DP/AC5/RTE/Device/ARMCM7_DP/system_ARMCM7.c

@@ -0,0 +1,85 @@
+/**************************************************************************//**
+ * @file     system_ARMCM7.c
+ * @brief    CMSIS Device System Source File for
+ *           ARMCM7 Device Series
+ * @version  V5.00
+ * @date     07. September 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM7)
+  #include "ARMCM7.h"
+#elif defined (ARMCM7_SP)
+  #include "ARMCM7_SP.h"
+#elif defined (ARMCM7_DP)
+  #include "ARMCM7_DP.h"
+#else
+  #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+
+#define  SYSTEM_CLOCK    (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+#if defined (__FPU_USED) && (__FPU_USED == 1U)
+  SCB->CPACR |= ((3U << 10U*2U) |           /* set CP10 Full Access */
+                 (3U << 11U*2U)  );         /* set CP11 Full Access */
+#endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+  SystemCoreClock = SYSTEM_CLOCK;
+}

CMSIS/CoreValidation/Tests/Cortex-M7DP/AC5/RTE/_FVP/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'CMSIS_CV' 
+ * Target:  'FVP' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "ARMCM7_DP.h"
+
+
+#endif /* RTE_COMPONENTS_H */

CMSIS/CoreValidation/Tests/Cortex-M7DP/AC6/CMSIS_CV.uvprojx

@@ -0,0 +1,507 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>FVP</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pArmCC>6070000::V6.7::.\ARMCLANG</pArmCC>
+      <pCCUsed>6070000::V6.7::.\ARMCLANG</pCCUsed>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>ARMCM7_DP</Device>
+          <Vendor>ARM</Vendor>
+          <PackID>ARM.CMSIS.5.1.2-dev1</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ESEL ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:ARMCM7_DP$Device\ARM\ARMCM7\Include\ARMCM7_DP.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:ARMCM7_DP$Device\ARM\SVD\ARMCM7.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\Objects\</OutputDirectory>
+          <OutputName>CMSIS_CV</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\Listings\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>  -MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM7</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> -MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM7</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>1</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M7"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>3</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>1</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <useXO>0</useXO>
+            <v6Lang>3</v6Lang>
+            <v6LangP>3</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls>-Wno-covered-switch-default</MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>.\,..\..\..\Include</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <uClangAs>0</uClangAs>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>.\,..\..\..\Include</IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange></TextAddressRange>
+            <DataAddressRange></DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc>--entry=Reset_Handler</Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Test</GroupName>
+          <Files>
+            <File>
+              <FileName>cmsis_cv.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\cmsis_cv.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_CoreFunc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_CoreFunc.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_CoreInstr.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_CoreInstr.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Framework.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_Framework.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_MPU_ARMv7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_MPU_ARMv7.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Report.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_Report.c</FilePath>
+            </File>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\main.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Config.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\CV_Config.h</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::CMSIS</GroupName>
+        </Group>
+        <Group>
+          <GroupName>::Device</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components>
+      <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.0.2" condition="ARMv6_7_8-M Device">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM7 CMSIS">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </component>
+    </components>
+    <files>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM0\Source\ARM\startup_ARMCM0.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM0\startup_ARMCM0.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM0\Source\system_ARMCM0.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM0\system_ARMCM0.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM3\Source\ARM\startup_ARMCM3.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM3\startup_ARMCM3.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM3\Source\system_ARMCM3.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM3\system_ARMCM3.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM4\Source\ARM\startup_ARMCM4.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM4\startup_ARMCM4.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM4\Source\system_ARMCM4.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM4\system_ARMCM4.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM7\Source\ARM\startup_ARMCM7.s" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM7_DP\startup_ARMCM7.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM7 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM7\Source\system_ARMCM7.c" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM7_DP\system_ARMCM7.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM7 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </file>
+    </files>
+  </RTE>
+
+</Project>

CMSIS/CoreValidation/Tests/Cortex-M7DP/AC6/CV_Config.h

@@ -0,0 +1,82 @@
+/*-----------------------------------------------------------------------------
+ *      Name:         CV_Config.h 
+ *      Purpose:      CV Config header
+ *----------------------------------------------------------------------------
+ *      Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+#ifndef __CV_CONFIG_H
+#define __CV_CONFIG_H
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+#define RTE_CV_COREINSTR 1
+#define RTE_CV_COREFUNC  1
+#define RTE_CV_MPUFUNC   1
+
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h> Common Test Settings
+// <o> Print Output Format <0=> Plain Text <1=> XML
+// <i> Set the test results output format to plain text or XML
+#ifndef PRINT_XML_REPORT
+#define PRINT_XML_REPORT            1
+#endif
+// <o> Buffer size for assertions results
+// <i> Set the buffer size for assertions results buffer
+#define BUFFER_ASSERTIONS           128U
+// </h>
+
+// <h> Disable Test Cases
+// <i> Uncheck to disable an individual test case
+// <q00> TC_CoreInstr_NOP
+// <q01> TC_CoreInstr_REV
+// <q02> TC_CoreInstr_REV16
+// <q03> TC_CoreInstr_REVSH
+// <q04> TC_CoreInstr_ROR
+// <q05> TC_CoreInstr_RBIT
+// <q06> TC_CoreInstr_CLZ
+// <q07> TC_CoreInstr_SSAT
+// <q08> TC_CoreInstr_USAT
+//
+// <q09> TC_CoreFunc_EnDisIRQ
+// <q10> TC_CoreFunc_Control
+// <q11> TC_CoreFunc_IPSR
+// <q12> TC_CoreFunc_APSR
+// <q13> TC_CoreFunc_PSP
+// <q14> TC_CoreFunc_MSP
+// <q15> TC_CoreFunc_PRIMASK
+// <q16> TC_CoreFunc_FAULTMASK
+// <q17> TC_CoreFunc_BASEPRI
+// <q18> TC_CoreFunc_FPSCR
+//
+// <q19> TC_MPU_SetClear
+// <q20> TC_MPU_Load
+#define TC_COREINSTR_NOP_EN         1
+#define TC_COREINSTR_REV_EN         1
+#define TC_COREINSTR_REV16_EN       1
+#define TC_COREINSTR_REVSH_EN       1
+#define TC_COREINSTR_ROR_EN         1
+#define TC_COREINSTR_RBIT_EN        1
+#define TC_COREINSTR_CLZ_EN         1
+#define TC_COREINSTR_SSAT_EN        1
+#define TC_COREINSTR_USAT_EN        1
+
+#define TC_COREFUNC_ENDISIRQ_EN     1
+#define TC_COREFUNC_CONTROL_EN      1
+#define TC_COREFUNC_IPSR_EN         1
+#define TC_COREFUNC_APSR_EN         1
+#define TC_COREFUNC_PSP_EN          1
+#define TC_COREFUNC_MSP_EN          1
+#define TC_COREFUNC_PRIMASK_EN      1
+#define TC_COREFUNC_FAULTMASK_EN    1
+#define TC_COREFUNC_BASEPRI_EN      1
+#define TC_COREFUNC_FPSCR_EN        1
+
+#define TC_MPU_SETCLEAR_EN          1
+#define TC_MPU_LOAD_EN              1
+// </h>
+
+#endif /* __CV_CONFIG_H */
+

CMSIS/CoreValidation/Tests/Cortex-M7DP/AC6/EventRecorderStub.scvd

@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
+
+<component name="EventRecorderStub" version="1.0.0"/>       <!--name and version of the component-->
+  <events>
+  </events>
+
+</component_viewer>

CMSIS/CoreValidation/Tests/Cortex-M7DP/AC6/RTE/Device/ARMCM7_DP/startup_ARMCM7.s

@@ -0,0 +1,262 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM7.s
+; * @brief    CMSIS Core Device Startup File for
+; *           ARMCM7 Device Series
+; * @version  V5.00
+; * @date     02. March 2016
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000C00
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
+                DCD     RTC_IRQHandler            ;  1:  Real Time Clock
+                DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
+                DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
+                DCD     MCIA_IRQHandler           ;  4:  MCIa
+                DCD     MCIB_IRQHandler           ;  5:  MCIb
+                DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
+                DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
+                DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
+                DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
+                DCD     AACI_IRQHandler           ; 10: AACI / AC97
+                DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
+                DCD     ENET_IRQHandler           ; 12: Ethernet
+                DCD     USBDC_IRQHandler          ; 13: USB Device
+                DCD     USBHC_IRQHandler          ; 14: USB Host Controller
+                DCD     CHLCD_IRQHandler          ; 15: Character LCD
+                DCD     FLEXRAY_IRQHandler        ; 16: Flexray
+                DCD     CAN_IRQHandler            ; 17: CAN
+                DCD     LIN_IRQHandler            ; 18: LIN
+                DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
+                DCD     0                         ; 20: Reserved
+                DCD     0                         ; 21: Reserved
+                DCD     0                         ; 22: Reserved
+                DCD     0                         ; 23: Reserved
+                DCD     0                         ; 24: Reserved
+                DCD     0                         ; 25: Reserved
+                DCD     0                         ; 26: Reserved
+                DCD     0                         ; 27: Reserved
+                DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
+                DCD     0                         ; 29: Reserved - CPU FPGA
+                DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
+                DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WDT_IRQHandler            [WEAK]
+                EXPORT  RTC_IRQHandler            [WEAK]
+                EXPORT  TIM0_IRQHandler           [WEAK]
+                EXPORT  TIM2_IRQHandler           [WEAK]
+                EXPORT  MCIA_IRQHandler           [WEAK]
+                EXPORT  MCIB_IRQHandler           [WEAK]
+                EXPORT  UART0_IRQHandler          [WEAK]
+                EXPORT  UART1_IRQHandler          [WEAK]
+                EXPORT  UART2_IRQHandler          [WEAK]
+                EXPORT  UART3_IRQHandler          [WEAK]
+                EXPORT  UART4_IRQHandler          [WEAK]
+                EXPORT  AACI_IRQHandler           [WEAK]
+                EXPORT  CLCD_IRQHandler           [WEAK]
+                EXPORT  ENET_IRQHandler           [WEAK]
+                EXPORT  USBDC_IRQHandler          [WEAK]
+                EXPORT  USBHC_IRQHandler          [WEAK]
+                EXPORT  CHLCD_IRQHandler          [WEAK]
+                EXPORT  FLEXRAY_IRQHandler        [WEAK]
+                EXPORT  CAN_IRQHandler            [WEAK]
+                EXPORT  LIN_IRQHandler            [WEAK]
+                EXPORT  I2C_IRQHandler            [WEAK]
+                EXPORT  CPU_CLCD_IRQHandler       [WEAK]
+                EXPORT  SPI_IRQHandler            [WEAK]
+
+WDT_IRQHandler
+RTC_IRQHandler
+TIM0_IRQHandler
+TIM2_IRQHandler
+MCIA_IRQHandler
+MCIB_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+UART4_IRQHandler
+AACI_IRQHandler
+CLCD_IRQHandler
+ENET_IRQHandler
+USBDC_IRQHandler
+USBHC_IRQHandler
+CHLCD_IRQHandler
+FLEXRAY_IRQHandler
+CAN_IRQHandler
+LIN_IRQHandler
+I2C_IRQHandler
+CPU_CLCD_IRQHandler
+SPI_IRQHandler
+                B       .
+
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap PROC
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+                ENDP
+
+                ALIGN
+
+                ENDIF
+
+
+                END

CMSIS/CoreValidation/Tests/Cortex-M7DP/AC6/RTE/Device/ARMCM7_DP/system_ARMCM7.c

@@ -0,0 +1,85 @@
+/**************************************************************************//**
+ * @file     system_ARMCM7.c
+ * @brief    CMSIS Device System Source File for
+ *           ARMCM7 Device Series
+ * @version  V5.00
+ * @date     07. September 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM7)
+  #include "ARMCM7.h"
+#elif defined (ARMCM7_SP)
+  #include "ARMCM7_SP.h"
+#elif defined (ARMCM7_DP)
+  #include "ARMCM7_DP.h"
+#else
+  #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+
+#define  SYSTEM_CLOCK    (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+#if defined (__FPU_USED) && (__FPU_USED == 1U)
+  SCB->CPACR |= ((3U << 10U*2U) |           /* set CP10 Full Access */
+                 (3U << 11U*2U)  );         /* set CP11 Full Access */
+#endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+  SystemCoreClock = SYSTEM_CLOCK;
+}

CMSIS/CoreValidation/Tests/Cortex-M7DP/AC6/RTE/_FVP/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'CMSIS_CV' 
+ * Target:  'FVP' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "ARMCM7_DP.h"
+
+
+#endif /* RTE_COMPONENTS_H */

CMSIS/CoreValidation/Tests/Cortex-M7DP/GCC/CMSIS_CV.uvprojx

@@ -0,0 +1,434 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>FVP</TargetName>
+      <ToolsetNumber>0x3</ToolsetNumber>
+      <ToolsetName>ARM-GNU</ToolsetName>
+      <pArmCC>6070000::V6.7::.\ARMCLANG</pArmCC>
+      <pCCUsed>6070000::V6.7::.\ARMCLANG</pCCUsed>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>ARMCM7_DP</Device>
+          <Vendor>ARM</Vendor>
+          <PackID>ARM.CMSIS.5.1.2-dev1</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ESEL ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:ARMCM7_DP$Device\ARM\ARMCM7\Include\ARMCM7_DP.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:ARMCM7_DP$Device\ARM\SVD\ARMCM7.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\Objects\</OutputDirectory>
+          <OutputName>CMSIS_CV</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\Listings\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>  -MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM7</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> -MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM7</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArm>
+          <ArmMisc>
+            <asLst>1</asLst>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>1</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <GCPUTYP>"Cortex-M7"</GCPUTYP>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>3</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <IRAM2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </IRAM2>
+              <IROM2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </IROM2>
+            </OnChipMemories>
+          </ArmMisc>
+          <Carm>
+            <arpcs>1</arpcs>
+            <stkchk>0</stkchk>
+            <reentr>0</reentr>
+            <interw>1</interw>
+            <bigend>0</bigend>
+            <Strict>0</Strict>
+            <Optim>1</Optim>
+            <wLevel>3</wLevel>
+            <uThumb>1</uThumb>
+            <VariousControls>
+              <MiscControls>-mfloat-abi=hard -mfpu=fpv5-d16 -Wall -Wextra -Wstrict-prototypes -Wshadow</MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>.;..\..\..\Include</IncludePath>
+            </VariousControls>
+          </Carm>
+          <Aarm>
+            <bBE>0</bBE>
+            <interw>1</interw>
+            <VariousControls>
+              <MiscControls>-mfloat-abi=hard -mfpu=fpv5-d16 -Wall</MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>.;..\..\..\Include</IncludePath>
+            </VariousControls>
+          </Aarm>
+          <LDarm>
+            <umfTarg>1</umfTarg>
+            <enaGarb>0</enaGarb>
+            <noStart>0</noStart>
+            <noStLib>0</noStLib>
+            <uMathLib>0</uMathLib>
+            <TextAddressRange></TextAddressRange>
+            <DataAddressRange></DataAddressRange>
+            <BSSAddressRange></BSSAddressRange>
+            <IncludeLibs></IncludeLibs>
+            <IncludeDir></IncludeDir>
+            <Misc>-mfloat-abi=hard -mfpu=fpv5-d16 --specs=rdimon.specs</Misc>
+            <ScatterFile>.\RTE\Device\ARMCM7_DP\gcc_arm.ld</ScatterFile>
+          </LDarm>
+        </TargetArm>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Test</GroupName>
+          <Files>
+            <File>
+              <FileName>cmsis_cv.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\cmsis_cv.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_CoreFunc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_CoreFunc.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_CoreInstr.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_CoreInstr.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Framework.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_Framework.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_MPU_ARMv7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_MPU_ARMv7.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Report.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_Report.c</FilePath>
+            </File>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\main.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Config.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\CV_Config.h</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::CMSIS</GroupName>
+        </Group>
+        <Group>
+          <GroupName>::Device</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components>
+      <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.0.2" condition="ARMv6_7_8-M Device">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM7 CMSIS GCC">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </component>
+    </components>
+    <files>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM0\Source\ARM\startup_ARMCM0.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM0\startup_ARMCM0.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM0\Source\system_ARMCM0.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM0\system_ARMCM0.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="linkerScript" condition="GCC" name="Device\ARM\ARMCM3\Source\GCC\gcc_arm.ld" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM3\gcc_arm.ld</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceAsm" condition="GCC" name="Device\ARM\ARMCM3\Source\GCC\startup_ARMCM3.S" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM3\startup_ARMCM3.S</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" condition="GCC" name="Device\ARM\ARMCM3\Source\GCC\startup_ARMCM3.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM3\startup_ARMCM3.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM3\Source\system_ARMCM3.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM3\system_ARMCM3.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="linkerScript" condition="GCC" name="Device\ARM\ARMCM4\Source\GCC\gcc_arm.ld" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM4\gcc_arm.ld</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" condition="GCC" name="Device\ARM\ARMCM4\Source\GCC\startup_ARMCM4.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM4\startup_ARMCM4.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM4\Source\ARM\startup_ARMCM4.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM4\startup_ARMCM4.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM4\Source\system_ARMCM4.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM4\system_ARMCM4.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="linkerScript" condition="GCC" name="Device\ARM\ARMCM7\Source\GCC\gcc_arm.ld" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM7_DP\gcc_arm.ld</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM7 CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="sourceC" condition="GCC" name="Device\ARM\ARMCM7\Source\GCC\startup_ARMCM7.c" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM7_DP\startup_ARMCM7.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM7 CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM7\Source\system_ARMCM7.c" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM7_DP\system_ARMCM7.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM7 CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </file>
+    </files>
+  </RTE>
+
+</Project>

CMSIS/CoreValidation/Tests/Cortex-M7DP/GCC/CV_Config.h

@@ -0,0 +1,82 @@
+/*-----------------------------------------------------------------------------
+ *      Name:         CV_Config.h 
+ *      Purpose:      CV Config header
+ *----------------------------------------------------------------------------
+ *      Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+#ifndef __CV_CONFIG_H
+#define __CV_CONFIG_H
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+#define RTE_CV_COREINSTR 1
+#define RTE_CV_COREFUNC  1
+#define RTE_CV_MPUFUNC   1
+
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h> Common Test Settings
+// <o> Print Output Format <0=> Plain Text <1=> XML
+// <i> Set the test results output format to plain text or XML
+#ifndef PRINT_XML_REPORT
+#define PRINT_XML_REPORT            1
+#endif
+// <o> Buffer size for assertions results
+// <i> Set the buffer size for assertions results buffer
+#define BUFFER_ASSERTIONS           128U
+// </h>
+
+// <h> Disable Test Cases
+// <i> Uncheck to disable an individual test case
+// <q00> TC_CoreInstr_NOP
+// <q01> TC_CoreInstr_REV
+// <q02> TC_CoreInstr_REV16
+// <q03> TC_CoreInstr_REVSH
+// <q04> TC_CoreInstr_ROR
+// <q05> TC_CoreInstr_RBIT
+// <q06> TC_CoreInstr_CLZ
+// <q07> TC_CoreInstr_SSAT
+// <q08> TC_CoreInstr_USAT
+//
+// <q09> TC_CoreFunc_EnDisIRQ
+// <q10> TC_CoreFunc_Control
+// <q11> TC_CoreFunc_IPSR
+// <q12> TC_CoreFunc_APSR
+// <q13> TC_CoreFunc_PSP
+// <q14> TC_CoreFunc_MSP
+// <q15> TC_CoreFunc_PRIMASK
+// <q16> TC_CoreFunc_FAULTMASK
+// <q17> TC_CoreFunc_BASEPRI
+// <q18> TC_CoreFunc_FPSCR
+//
+// <q19> TC_MPU_SetClear
+// <q20> TC_MPU_Load
+#define TC_COREINSTR_NOP_EN         1
+#define TC_COREINSTR_REV_EN         1
+#define TC_COREINSTR_REV16_EN       1
+#define TC_COREINSTR_REVSH_EN       1
+#define TC_COREINSTR_ROR_EN         1
+#define TC_COREINSTR_RBIT_EN        1
+#define TC_COREINSTR_CLZ_EN         1
+#define TC_COREINSTR_SSAT_EN        1
+#define TC_COREINSTR_USAT_EN        1
+
+#define TC_COREFUNC_ENDISIRQ_EN     1
+#define TC_COREFUNC_CONTROL_EN      1
+#define TC_COREFUNC_IPSR_EN         1
+#define TC_COREFUNC_APSR_EN         1
+#define TC_COREFUNC_PSP_EN          1
+#define TC_COREFUNC_MSP_EN          1
+#define TC_COREFUNC_PRIMASK_EN      1
+#define TC_COREFUNC_FAULTMASK_EN    1
+#define TC_COREFUNC_BASEPRI_EN      1
+#define TC_COREFUNC_FPSCR_EN        1
+
+#define TC_MPU_SETCLEAR_EN          1
+#define TC_MPU_LOAD_EN              1
+// </h>
+
+#endif /* __CV_CONFIG_H */
+

CMSIS/CoreValidation/Tests/Cortex-M7DP/GCC/EventRecorderStub.scvd

@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
+
+<component name="EventRecorderStub" version="1.0.0"/>       <!--name and version of the component-->
+  <events>
+  </events>
+
+</component_viewer>

CMSIS/CoreValidation/Tests/Cortex-M7DP/GCC/RTE/Device/ARMCM7_DP/gcc_arm.ld

@@ -0,0 +1,196 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+  FLASH (rx)  : ORIGIN = 0x00000000, LENGTH = 512K
+  RAM   (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapBase
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __Vectors_End
+ *   __Vectors_Size
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+	.text :
+	{
+		KEEP(*(.vectors))
+		__Vectors_End = .;
+		__Vectors_Size = __Vectors_End - __Vectors;
+		__end__ = .;
+
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+	.ARM.extab :
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	/* To copy multiple ROM to RAM sections,
+	 * uncomment .copy.table section and,
+	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.copy.table :
+	{
+		. = ALIGN(4);
+		__copy_table_start__ = .;
+		LONG (__etext)
+		LONG (__data_start__)
+		LONG (__data_end__ - __data_start__)
+		LONG (__etext2)
+		LONG (__data2_start__)
+		LONG (__data2_end__ - __data2_start__)
+		__copy_table_end__ = .;
+	} > FLASH
+	*/
+
+	/* To clear multiple BSS sections,
+	 * uncomment .zero.table section and,
+	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.zero.table :
+	{
+		. = ALIGN(4);
+		__zero_table_start__ = .;
+		LONG (__bss_start__)
+		LONG (__bss_end__ - __bss_start__)
+		LONG (__bss2_start__)
+		LONG (__bss2_end__ - __bss2_start__)
+		__zero_table_end__ = .;
+	} > FLASH
+	*/
+
+	__etext = .;
+
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		KEEP(*(.jcr*))
+		. = ALIGN(4);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > RAM
+
+	.heap (COPY):
+	{
+		__HeapBase = .;
+		__end__ = .;
+		end = __end__;
+		KEEP(*(.heap*))
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (COPY):
+	{
+		KEEP(*(.stack*))
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM);
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}

CMSIS/CoreValidation/Tests/Cortex-M7DP/GCC/RTE/Device/ARMCM7_DP/startup_ARMCM7.c

@@ -0,0 +1,295 @@
+/**************************************************************************//**
+ * @file     startup_ARMCM7.s
+ * @brief    CMSIS Core Device Startup File for
+ *           ARMCM7 Device Series
+ * @version  V5.00
+ * @date     26. April 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdint.h>
+
+
+/*----------------------------------------------------------------------------
+  Linker generated Symbols
+ *----------------------------------------------------------------------------*/
+extern uint32_t __etext;
+extern uint32_t __data_start__;
+extern uint32_t __data_end__;
+extern uint32_t __copy_table_start__;
+extern uint32_t __copy_table_end__;
+extern uint32_t __zero_table_start__;
+extern uint32_t __zero_table_end__;
+extern uint32_t __bss_start__;
+extern uint32_t __bss_end__;
+extern uint32_t __StackTop;
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler Function Prototype
+ *----------------------------------------------------------------------------*/
+typedef void( *pFunc )( void );
+
+
+/*----------------------------------------------------------------------------
+  External References
+ *----------------------------------------------------------------------------*/
+#ifndef __START
+extern void  _start(void) __attribute__((noreturn));    /* PreeMain (C library entry point) */
+#else
+extern int  __START(void) __attribute__((noreturn));    /* main entry point */
+#endif
+
+#ifndef __NO_SYSTEM_INIT
+extern void SystemInit (void);            /* CMSIS System Initialization      */
+#endif
+
+
+/*----------------------------------------------------------------------------
+  Internal References
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void);                          /* Default empty handler */
+void Reset_Handler(void);                            /* Reset Handler */
+
+
+/*----------------------------------------------------------------------------
+  User Initial Stack & Heap
+ *----------------------------------------------------------------------------*/
+#ifndef __STACK_SIZE
+  #define	__STACK_SIZE  0x00000400
+#endif
+static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack")));
+
+#ifndef __HEAP_SIZE
+  #define	__HEAP_SIZE   0x00000C00
+#endif
+#if __HEAP_SIZE > 0
+static uint8_t heap[__HEAP_SIZE]   __attribute__ ((aligned(8), used, section(".heap")));
+#endif
+
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Cortex-M7 Processor Exceptions */
+void NMI_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void MemManage_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/* ARMCM7 Specific Interrupts */
+void WDT_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void RTC_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void TIM0_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void TIM2_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void MCIA_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void MCIB_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART0_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART1_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART2_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART4_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void AACI_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void CLCD_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void ENET_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void USBDC_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void USBHC_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void CHLCD_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void FLEXRAY_IRQHandler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void CAN_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void LIN_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void I2C_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void CPU_CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART3_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void SPI_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = {
+  /* Cortex-M7 Exceptions Handler */
+  (pFunc)((uint32_t)&__StackTop),           /*      Initial Stack Pointer     */
+  Reset_Handler,                            /*      Reset Handler             */
+  NMI_Handler,                              /*      NMI Handler               */
+  HardFault_Handler,                        /*      Hard Fault Handler        */
+  MemManage_Handler,                        /*      MPU Fault Handler         */
+  BusFault_Handler,                         /*      Bus Fault Handler         */
+  UsageFault_Handler,                       /*      Usage Fault Handler       */
+  0,                                        /*      Reserved                  */
+  0,                                        /*      Reserved                  */
+  0,                                        /*      Reserved                  */
+  0,                                        /*      Reserved                  */
+  SVC_Handler,                              /*      SVCall Handler            */
+  DebugMon_Handler,                         /*      Debug Monitor Handler     */
+  0,                                        /*      Reserved                  */
+  PendSV_Handler,                           /*      PendSV Handler            */
+  SysTick_Handler,                          /*      SysTick Handler           */
+
+  /* External interrupts */
+  WDT_IRQHandler,                           /*  0:  Watchdog Timer            */
+  RTC_IRQHandler,                           /*  1:  Real Time Clock           */
+  TIM0_IRQHandler,                          /*  2:  Timer0 / Timer1           */
+  TIM2_IRQHandler,                          /*  3:  Timer2 / Timer3           */
+  MCIA_IRQHandler,                          /*  4:  MCIa                      */
+  MCIB_IRQHandler,                          /*  5:  MCIb                      */
+  UART0_IRQHandler,                         /*  6:  UART0 - DUT FPGA          */
+  UART1_IRQHandler,                         /*  7:  UART1 - DUT FPGA          */
+  UART2_IRQHandler,                         /*  8:  UART2 - DUT FPGA          */
+  UART4_IRQHandler,                         /*  9:  UART4 - not connected     */
+  AACI_IRQHandler,                          /* 10: AACI / AC97                */
+  CLCD_IRQHandler,                          /* 11: CLCD Combined Interrupt    */
+  ENET_IRQHandler,                          /* 12: Ethernet                   */
+  USBDC_IRQHandler,                         /* 13: USB Device                 */
+  USBHC_IRQHandler,                         /* 14: USB Host Controller        */
+  CHLCD_IRQHandler,                         /* 15: Character LCD              */
+  FLEXRAY_IRQHandler,                       /* 16: Flexray                    */
+  CAN_IRQHandler,                           /* 17: CAN                        */
+  LIN_IRQHandler,                           /* 18: LIN                        */
+  I2C_IRQHandler,                           /* 19: I2C ADC/DAC                */
+  0,                                        /* 20: Reserved                   */
+  0,                                        /* 21: Reserved                   */
+  0,                                        /* 22: Reserved                   */
+  0,                                        /* 23: Reserved                   */
+  0,                                        /* 24: Reserved                   */
+  0,                                        /* 25: Reserved                   */
+  0,                                        /* 26: Reserved                   */
+  0,                                        /* 27: Reserved                   */
+  CPU_CLCD_IRQHandler,                      /* 28: Reserved - CPU FPGA CLCD   */
+  0,                                        /* 29: Reserved - CPU FPGA        */
+  UART3_IRQHandler,                         /* 30: UART3    - CPU FPGA        */
+  SPI_IRQHandler                            /* 31: SPI Touchscreen - CPU FPGA */
+};
+
+
+/*----------------------------------------------------------------------------
+  Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+  uint32_t *pSrc, *pDest;
+  uint32_t *pTable __attribute__((unused));
+
+/*  Firstly it copies data from read only memory to RAM. There are two schemes
+ *  to copy. One can copy more than one sections. Another can only copy
+ *  one section.  The former scheme needs more instructions and read-only
+ *  data to implement than the latter.
+ *  Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.  */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/*  Multiple sections scheme.
+ *
+ *  Between symbol address __copy_table_start__ and __copy_table_end__,
+ *  there are array of triplets, each of which specify:
+ *    offset 0: LMA of start of a section to copy from
+ *    offset 4: VMA of start of a section to copy to
+ *    offset 8: size of the section to copy. Must be multiply of 4
+ *
+ *  All addresses must be aligned to 4 bytes boundary.
+ */
+  pTable = &__copy_table_start__;
+
+  for (; pTable < &__copy_table_end__; pTable = pTable + 3) {
+		pSrc  = (uint32_t*)*(pTable + 0);
+		pDest = (uint32_t*)*(pTable + 1);
+		for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
+      *pDest++ = *pSrc++;
+		}
+	}
+#else
+/*  Single section scheme.
+ *
+ *  The ranges of copy from/to are specified by following symbols
+ *    __etext: LMA of start of the section to copy from. Usually end of text
+ *    __data_start__: VMA of start of the section to copy to
+ *    __data_end__: VMA of end of the section to copy to
+ *
+ *  All addresses must be aligned to 4 bytes boundary.
+ */
+  pSrc  = &__etext;
+  pDest = &__data_start__;
+
+  for ( ; pDest < &__data_end__ ; ) {
+    *pDest++ = *pSrc++;
+  }
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/*  This part of work usually is done in C library startup code. Otherwise,
+ *  define this macro to enable it in this startup.
+ *
+ *  There are two schemes too. One can clear multiple BSS sections. Another
+ *  can only clear one section. The former is more size expensive than the
+ *  latter.
+ *
+ *  Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ *  Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/*  Multiple sections scheme.
+ *
+ *  Between symbol address __copy_table_start__ and __copy_table_end__,
+ *  there are array of tuples specifying:
+ *    offset 0: Start of a BSS section
+ *    offset 4: Size of this BSS section. Must be multiply of 4
+ */
+  pTable = &__zero_table_start__;
+
+  for (; pTable < &__zero_table_end__; pTable = pTable + 2) {
+		pDest = (uint32_t*)*(pTable + 0);
+		for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
+      *pDest++ = 0;
+		}
+	}
+#elif defined (__STARTUP_CLEAR_BSS)
+/*  Single BSS section scheme.
+ *
+ *  The BSS section is specified by following symbols
+ *    __bss_start__: start of the BSS section.
+ *    __bss_end__: end of the BSS section.
+ *
+ *  Both addresses must be aligned to 4 bytes boundary.
+ */
+  pDest = &__bss_start__;
+
+  for ( ; pDest < &__bss_end__ ; ) {
+    *pDest++ = 0UL;
+  }
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+#ifndef __NO_SYSTEM_INIT
+	SystemInit();
+#endif
+
+#ifndef __START
+#define __START _start
+#endif
+	__START();
+
+}
+
+
+/*----------------------------------------------------------------------------
+  Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+
+	while(1);
+}

CMSIS/CoreValidation/Tests/Cortex-M7DP/GCC/RTE/Device/ARMCM7_DP/system_ARMCM7.c

@@ -0,0 +1,85 @@
+/**************************************************************************//**
+ * @file     system_ARMCM7.c
+ * @brief    CMSIS Device System Source File for
+ *           ARMCM7 Device Series
+ * @version  V5.00
+ * @date     07. September 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM7)
+  #include "ARMCM7.h"
+#elif defined (ARMCM7_SP)
+  #include "ARMCM7_SP.h"
+#elif defined (ARMCM7_DP)
+  #include "ARMCM7_DP.h"
+#else
+  #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+
+#define  SYSTEM_CLOCK    (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+#if defined (__FPU_USED) && (__FPU_USED == 1U)
+  SCB->CPACR |= ((3U << 10U*2U) |           /* set CP10 Full Access */
+                 (3U << 11U*2U)  );         /* set CP11 Full Access */
+#endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+  SystemCoreClock = SYSTEM_CLOCK;
+}

CMSIS/CoreValidation/Tests/Cortex-M7DP/GCC/RTE/_FVP/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'CMSIS_CV' 
+ * Target:  'FVP' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "ARMCM7_DP.h"
+
+
+#endif /* RTE_COMPONENTS_H */

CMSIS/CoreValidation/Tests/Cortex-M7SP/AC5/CMSIS_CV.uvprojx

@@ -0,0 +1,507 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>FVP</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pArmCC>5060528::V5.06 update 5 (build 528)::ARMCC</pArmCC>
+      <pCCUsed>5060528::V5.06 update 5 (build 528)::ARMCC</pCCUsed>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>ARMCM7_SP</Device>
+          <Vendor>ARM</Vendor>
+          <PackID>ARM.CMSIS.5.1.2-dev1</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M7") FPU3(SFPU) CLOCK(12000000) ESEL ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:ARMCM7_SP$Device\ARM\ARMCM7\Include\ARMCM7_SP.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:ARMCM7_SP$Device\ARM\SVD\ARMCM7.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\Objects\</OutputDirectory>
+          <OutputName>CMSIS_CV</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\Listings\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>  -MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM7</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> -MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM7</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>1</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M7"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>2</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>1</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <useXO>0</useXO>
+            <v6Lang>3</v6Lang>
+            <v6LangP>3</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>.\,..\..\..\Include</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <uClangAs>0</uClangAs>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>.\,..\..\..\Include</IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange></TextAddressRange>
+            <DataAddressRange></DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc>--entry=Reset_Handler</Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Test</GroupName>
+          <Files>
+            <File>
+              <FileName>cmsis_cv.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\cmsis_cv.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_CoreFunc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_CoreFunc.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_CoreInstr.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_CoreInstr.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Framework.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_Framework.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_MPU_ARMv7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_MPU_ARMv7.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Report.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_Report.c</FilePath>
+            </File>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\main.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Config.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\CV_Config.h</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::CMSIS</GroupName>
+        </Group>
+        <Group>
+          <GroupName>::Device</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components>
+      <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.0.2" condition="ARMv6_7_8-M Device">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM7 CMSIS">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </component>
+    </components>
+    <files>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM0\Source\ARM\startup_ARMCM0.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM0\startup_ARMCM0.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM0\Source\system_ARMCM0.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM0\system_ARMCM0.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM3\Source\ARM\startup_ARMCM3.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM3\startup_ARMCM3.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM3\Source\system_ARMCM3.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM3\system_ARMCM3.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM4\Source\ARM\startup_ARMCM4.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM4\startup_ARMCM4.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM4\Source\system_ARMCM4.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM4\system_ARMCM4.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM7\Source\ARM\startup_ARMCM7.s" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM7_SP\startup_ARMCM7.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM7 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM7\Source\system_ARMCM7.c" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM7_SP\system_ARMCM7.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM7 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </file>
+    </files>
+  </RTE>
+
+</Project>

CMSIS/CoreValidation/Tests/Cortex-M7SP/AC5/CV_Config.h

@@ -0,0 +1,82 @@
+/*-----------------------------------------------------------------------------
+ *      Name:         CV_Config.h 
+ *      Purpose:      CV Config header
+ *----------------------------------------------------------------------------
+ *      Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+#ifndef __CV_CONFIG_H
+#define __CV_CONFIG_H
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+#define RTE_CV_COREINSTR 1
+#define RTE_CV_COREFUNC  1
+#define RTE_CV_MPUFUNC   1
+
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h> Common Test Settings
+// <o> Print Output Format <0=> Plain Text <1=> XML
+// <i> Set the test results output format to plain text or XML
+#ifndef PRINT_XML_REPORT
+#define PRINT_XML_REPORT            1
+#endif
+// <o> Buffer size for assertions results
+// <i> Set the buffer size for assertions results buffer
+#define BUFFER_ASSERTIONS           128U
+// </h>
+
+// <h> Disable Test Cases
+// <i> Uncheck to disable an individual test case
+// <q00> TC_CoreInstr_NOP
+// <q01> TC_CoreInstr_REV
+// <q02> TC_CoreInstr_REV16
+// <q03> TC_CoreInstr_REVSH
+// <q04> TC_CoreInstr_ROR
+// <q05> TC_CoreInstr_RBIT
+// <q06> TC_CoreInstr_CLZ
+// <q07> TC_CoreInstr_SSAT
+// <q08> TC_CoreInstr_USAT
+//
+// <q09> TC_CoreFunc_EnDisIRQ
+// <q10> TC_CoreFunc_Control
+// <q11> TC_CoreFunc_IPSR
+// <q12> TC_CoreFunc_APSR
+// <q13> TC_CoreFunc_PSP
+// <q14> TC_CoreFunc_MSP
+// <q15> TC_CoreFunc_PRIMASK
+// <q16> TC_CoreFunc_FAULTMASK
+// <q17> TC_CoreFunc_BASEPRI
+// <q18> TC_CoreFunc_FPSCR
+//
+// <q19> TC_MPU_SetClear
+// <q20> TC_MPU_Load
+#define TC_COREINSTR_NOP_EN         1
+#define TC_COREINSTR_REV_EN         1
+#define TC_COREINSTR_REV16_EN       1
+#define TC_COREINSTR_REVSH_EN       1
+#define TC_COREINSTR_ROR_EN         1
+#define TC_COREINSTR_RBIT_EN        1
+#define TC_COREINSTR_CLZ_EN         1
+#define TC_COREINSTR_SSAT_EN        1
+#define TC_COREINSTR_USAT_EN        1
+
+#define TC_COREFUNC_ENDISIRQ_EN     1
+#define TC_COREFUNC_CONTROL_EN      1
+#define TC_COREFUNC_IPSR_EN         1
+#define TC_COREFUNC_APSR_EN         1
+#define TC_COREFUNC_PSP_EN          1
+#define TC_COREFUNC_MSP_EN          1
+#define TC_COREFUNC_PRIMASK_EN      1
+#define TC_COREFUNC_FAULTMASK_EN    1
+#define TC_COREFUNC_BASEPRI_EN      1
+#define TC_COREFUNC_FPSCR_EN        1
+
+#define TC_MPU_SETCLEAR_EN          1
+#define TC_MPU_LOAD_EN              1
+// </h>
+
+#endif /* __CV_CONFIG_H */
+

CMSIS/CoreValidation/Tests/Cortex-M7SP/AC5/EventRecorderStub.scvd

@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
+
+<component name="EventRecorderStub" version="1.0.0"/>       <!--name and version of the component-->
+  <events>
+  </events>
+
+</component_viewer>