CoreValidation: Test projects for Cortex-M3.

CMSIS/CoreValidation/Tests/ARMCM0plus_config.txt

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+# Parameters:
+# instance.parameter=value       #(type, mode) default = 'def value' : description : [min..max]
+#----------------------------------------------------------------------------------------------
+fvp_mps2.SCC_ID.Variant=0x0                           # (int   , init-time) default = '0x0'    : SCC_ID[23:20], X in the FGPA version 'rXpY' : [0x0..0xF]
+fvp_mps2.SCC_ID.Revision=0x1                          # (int   , init-time) default = '0x1'    : SCC_ID[3:0], Y in the FGPA version 'rXpY' : [0x0..0xF]
+fvp_mps2.iotss_systemcontrol.cpu0wait=0               # (bool  , init-time) default = '0'      : Whether to hold cpu0 in reset at boot
+fvp_mps2.iotss_systemcontrol.cpu1wait=1               # (bool  , init-time) default = '1'      : Whether to hold cpu1 in reset at boot
+fvp_mps2.platform_type=0x0                            # (int   , init-time) default = '0x0'    : 0:Original MPS2 ; 1:IoT Kit (cut-down SSE-200) ; 2:Full SSE-200 : [0x0..0x2]
+fvp_mps2.extra_psram=0                                # (bool  , init-time) default = '0'      : Increases PSRAM to 32Mb
+fvp_mps2.DISABLE_GATING=1                             # (bool  , init-time) default = '1'      : Disable Memory gating logic
+fvp_mps2.NSC_CFG_0=0                                  # (bool  , init-time) default = '0'      : Whether 0x10000000..0x1FFFFFFF is non-secure-callable
+fvp_mps2.NSC_CFG_1=0                                  # (bool  , init-time) default = '0'      : Whether 0x30000000..0x3FFFFFFF is non-secure-callable
+fvp_mps2.APBPPCEXP_DIS0=0x0                           # (int   , init-time) default = '0x0'    : Disables support for individual bits on the APBNSPPCEXP0 and APBPPPCEXP0 buses : [0x0..0xFFFF]
+fvp_mps2.APBPPCEXP_DIS1=0x0                           # (int   , init-time) default = '0x0'    : Disables support for individual bits on the APBNSPPCEXP1 and APBPPPCEXP1 buses : [0x0..0xFFFF]
+fvp_mps2.APBPPCEXP_DIS2=0x0                           # (int   , init-time) default = '0x0'    : Disables support for individual bits on the APBNSPPCEXP2 and APBPPPCEXP2 buses : [0x0..0xFFFF]
+fvp_mps2.APBPPCEXP_DIS3=0x0                           # (int   , init-time) default = '0x0'    : Disables support for individual bits on the APBNSPPCEXP3 and APBPPPCEXP3 buses : [0x0..0xFFFF]
+fvp_mps2.AHBPPCEXP_DIS0=0x0                           # (int   , init-time) default = '0x0'    : Disables support for individual bits on the AHBNSPPCEXP0 and AHBPPPCEXP0 buses : [0x0..0xFFFF]
+fvp_mps2.AHBPPCEXP_DIS1=0x0                           # (int   , init-time) default = '0x0'    : Disables support for individual bits on the AHBNSPPCEXP1 and AHBPPPCEXP1 buses : [0x0..0xFFFF]
+fvp_mps2.AHBPPCEXP_DIS2=0x0                           # (int   , init-time) default = '0x0'    : Disables support for individual bits on the AHBNSPPCEXP2 and AHBPPPCEXP2 buses : [0x0..0xFFFF]
+fvp_mps2.AHBPPCEXP_DIS3=0x0                           # (int   , init-time) default = '0x0'    : Disables support for individual bits on the AHBNSPPCEXP3 and AHBPPPCEXP3 buses : [0x0..0xFFFF]
+fvp_mps2.UART2.out_file=""                            # (string, init-time) default = ''       : Output file to hold data written by the UART (use '-' to send all output to stdout)
+fvp_mps2.UART2.in_file=""                             # (string, init-time) default = ''       : Input file for data to be read by the UART
+fvp_mps2.UART2.unbuffered_output=0                    # (bool  , init-time) default = '0'      : Unbuffered output
+fvp_mps2.UART2.in_file_escape_sequence="##"           # (string, init-time) default = '##'     : Input file escape sequence
+fvp_mps2.UART2.shutdown_on_eot=0                      # (bool  , init-time) default = '0'      : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
+fvp_mps2.UART2.shutdown_tag=""                        # (string, run-time ) default = ''       : Shutdown simulation when a string is transmitted
+fvp_mps2.UART1.out_file=""                            # (string, init-time) default = ''       : Output file to hold data written by the UART (use '-' to send all output to stdout)
+fvp_mps2.UART1.in_file=""                             # (string, init-time) default = ''       : Input file for data to be read by the UART
+fvp_mps2.UART1.unbuffered_output=0                    # (bool  , init-time) default = '0'      : Unbuffered output
+fvp_mps2.UART1.in_file_escape_sequence="##"           # (string, init-time) default = '##'     : Input file escape sequence
+fvp_mps2.UART1.shutdown_on_eot=0                      # (bool  , init-time) default = '0'      : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
+fvp_mps2.UART1.shutdown_tag=""                        # (string, run-time ) default = ''       : Shutdown simulation when a string is transmitted
+fvp_mps2.mps2_visualisation.rate_limit-enable=1       # (bool  , init-time) default = '1'      : Rate limit simulation.
+fvp_mps2.mps2_visualisation.disable-visualisation=0   # (bool  , init-time) default = '0'      : Enable/disable visualisation
+fvp_mps2.mps2_visualisation.window_title="CLCD %cpu%"  # (string, init-time) default = 'CLCD %cpu%' : Window title (%cpu% is replaced by cpu_name)
+fvp_mps2.mps2_visualisation.idler.delay_ms=0x32       # (int   , init-time) default = '0x32'   : Determines the period, in milliseconds of real time, between gui_callback() calls.
+fvp_mps2.telnetterminal0.mode="telnet"                # (string, init-time) default = 'telnet' : Terminal initialisation mode
+fvp_mps2.telnetterminal0.start_telnet=1               # (bool  , init-time) default = '1'      : Start telnet if nothing connected
+fvp_mps2.telnetterminal0.start_port=0x1388            # (int   , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]
+fvp_mps2.telnetterminal0.quiet=0                      # (bool  , init-time) default = '0'      : Avoid output on stdout/stderr
+fvp_mps2.telnetterminal0.terminal_command=""          # (string, init-time) default = ''       : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)
+fvp_mps2.telnetterminal1.mode="telnet"                # (string, init-time) default = 'telnet' : Terminal initialisation mode
+fvp_mps2.telnetterminal1.start_telnet=1               # (bool  , init-time) default = '1'      : Start telnet if nothing connected
+fvp_mps2.telnetterminal1.start_port=0x1388            # (int   , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]
+fvp_mps2.telnetterminal1.quiet=0                      # (bool  , init-time) default = '0'      : Avoid output on stdout/stderr
+fvp_mps2.telnetterminal1.terminal_command=""          # (string, init-time) default = ''       : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)
+fvp_mps2.telnetterminal2.mode="telnet"                # (string, init-time) default = 'telnet' : Terminal initialisation mode
+fvp_mps2.telnetterminal2.start_telnet=1               # (bool  , init-time) default = '1'      : Start telnet if nothing connected
+fvp_mps2.telnetterminal2.start_port=0x1388            # (int   , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]
+fvp_mps2.telnetterminal2.quiet=0                      # (bool  , init-time) default = '0'      : Avoid output on stdout/stderr
+fvp_mps2.telnetterminal2.terminal_command=""          # (string, init-time) default = ''       : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)
+fvp_mps2.PSRAM_M7.size=0x100000000                    # (int   , init-time) default = '0x100000000' : Memory Size
+fvp_mps2.PSRAM_M7.fill1=0xDFDFDFCF                    # (int   , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.PSRAM_M7.fill2=0xCFDFDFDF                    # (int   , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.UART0.out_file=""                            # (string, init-time) default = ''       : Output file to hold data written by the UART (use '-' to send all output to stdout)
+fvp_mps2.UART0.in_file=""                             # (string, init-time) default = ''       : Input file for data to be read by the UART
+fvp_mps2.UART0.unbuffered_output=0                    # (bool  , init-time) default = '0'      : Unbuffered output
+fvp_mps2.UART0.in_file_escape_sequence="##"           # (string, init-time) default = '##'     : Input file escape sequence
+fvp_mps2.UART0.shutdown_on_eot=0                      # (bool  , init-time) default = '0'      : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
+fvp_mps2.UART0.shutdown_tag=""                        # (string, run-time ) default = ''       : Shutdown simulation when a string is transmitted
+fvp_mps2.cmsdk_watchdog.simhalt=0                     # (bool  , run-time ) default = '0'      : Halt on reset.
+fvp_mps2.PSRAM.size=0x100000000                       # (int   , init-time) default = '0x100000000' : Memory Size
+fvp_mps2.PSRAM.fill1=0xDFDFDFCF                       # (int   , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.PSRAM.fill2=0xCFDFDFDF                       # (int   , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.ssram2.size=0x100000000                      # (int   , init-time) default = '0x100000000' : Memory Size
+fvp_mps2.ssram2.fill1=0xDFDFDFCF                      # (int   , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.ssram2.fill2=0xCFDFDFDF                      # (int   , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.ssram1.size=0x100000000                      # (int   , init-time) default = '0x100000000' : Memory Size
+fvp_mps2.ssram1.fill1=0xDFDFDFCF                      # (int   , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.ssram1.fill2=0xCFDFDFDF                      # (int   , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.stub0.size=0x100000000                       # (int   , init-time) default = '0x100000000' : Memory Size
+fvp_mps2.stub1.size=0x100000000                       # (int   , init-time) default = '0x100000000' : Memory Size
+fvp_mps2.stub_i2c1.size=0x100000000                   # (int   , init-time) default = '0x100000000' : Memory Size
+fvp_mps2.stub_i2s.size=0x100000000                    # (int   , init-time) default = '0x100000000' : Memory Size
+fvp_mps2.stub_spi0.size=0x100000000                   # (int   , init-time) default = '0x100000000' : Memory Size
+fvp_mps2.stub_spi2.size=0x100000000                   # (int   , init-time) default = '0x100000000' : Memory Size
+fvp_mps2.expansion_warning_memory.abort_on_reads=0    # (bool  , init-time) default = '0'      : Abort on reads (read 0 if false)
+fvp_mps2.expansion_warning_memory.abort_on_writes=0   # (bool  , init-time) default = '0'      : Abort on writes (ignore if false)
+fvp_mps2.expansion_warning_memory.read_data=0x0       # (int   , init-time) default = '0x0'    : Data to return on reads, if not aborting
+fvp_mps2.smsc_91c111.enabled=0                        # (bool  , init-time) default = '0'      : Host interface connection enabled
+fvp_mps2.smsc_91c111.mac_address="00:02:f7:ef:4e:b4"  # (string, init-time) default = '00:02:f7:ef:4e:b4' : Host/model MAC address
+fvp_mps2.smsc_91c111.promiscuous=1                    # (bool  , init-time) default = '1'      : Put host into promiscuous mode
+fvp_mps2.hostbridge.interfaceName="ARM0"              # (string, init-time) default = 'ARM0'   : Host Interface
+fvp_mps2.hostbridge.userNetworking=0                  # (bool  , init-time) default = '0'      : Enable user-mode networking
+fvp_mps2.hostbridge.userNetSubnet="172.20.51.0/24"    # (string, init-time) default = '172.20.51.0/24' : Virtual subnet for user-mode networking
+fvp_mps2.hostbridge.userNetPorts=""                   # (string, init-time) default = ''       : Listening ports to expose in user-mode networking
+fvp_mps2.sse200.secure_watchdog.simhalt=0             # (bool  , run-time ) default = '0'      : Halt on reset.
+fvp_mps2.sse200.nonsecure_watchdog.simhalt=0          # (bool  , run-time ) default = '0'      : Halt on reset.
+fvp_mps2.sse200.secure_control_register_block.FLASH_BLOCK_CFG=0x3  # (int   , init-time) default = '0x3'    : Flash Block size configuration : [0x0..0x31]
+fvp_mps2.sse200.secure_control_register_block.SRAM_BLOCK_CFG=0x3  # (int   , init-time) default = '0x3'    : SRAM Block size configuration : [0x0..0x31]
+fvp_mps2.sse200.secure_control_register_block.FLASH_WATERMARK_SUPPORTED=1  # (bool  , init-time) default = '1'      : Flash Watermark supported
+fvp_mps2.sse200.secure_control_register_block.SRAM_WATERMARK_SUPPORTED=1  # (bool  , init-time) default = '1'      : SRAM Watermark supported
+fvp_mps2.sse200.apb_ppc_iotss_subsystem0.NONSEC_MASK=0x0  # (int   , init-time) default = '0x0'    : 16-bit wide mask for security checking of ports: 0 = check, 1 = mask : [0x0..0x1]
+fvp_mps2.sse200.apb_ppc_iotss_subsystem0.PORTx_ENABLE=0xFFFF  # (int   , init-time) default = '0xFFFF' : Enable (1) or disable (0) port x (where x is between 0-15): enable = 1, disable = 0 : [0x0..0xFFFF]
+fvp_mps2.sse200.apb_ppc_iotss_subsystem1.NONSEC_MASK=0x0  # (int   , init-time) default = '0x0'    : 16-bit wide mask for security checking of ports: 0 = check, 1 = mask : [0x0..0x1]
+fvp_mps2.sse200.apb_ppc_iotss_subsystem1.PORTx_ENABLE=0xFFFF  # (int   , init-time) default = '0xFFFF' : Enable (1) or disable (0) port x (where x is between 0-15): enable = 1, disable = 0 : [0x0..0xFFFF]
+fvp_mps2.sse200.s32k_watchdog.simhalt=0               # (bool  , run-time ) default = '0'      : Halt on reset.
+fvp_mps2.sse200.sys_ppu.use_active_signal=0           # (bool  , init-time) default = '0'      : Use device-active signal
+fvp_mps2.sse200.sys_ppu.revision="r0p0"               # (string, init-time) default = 'r0p0'   : Revision
+fvp_mps2.sse200.cpu0core_ppu.revision="r0p0"          # (string, init-time) default = 'r0p0'   : Revision
+fvp_mps2.sse200.cpu0dbg_ppu.revision="r0p0"           # (string, init-time) default = 'r0p0'   : Revision
+fvp_mps2.sse200.cpu1core_ppu.use_active_signal=0      # (bool  , init-time) default = '0'      : Use device-active signal
+fvp_mps2.sse200.cpu1core_ppu.revision="r0p0"          # (string, init-time) default = 'r0p0'   : Revision
+fvp_mps2.sse200.cpu1dbg_ppu.use_active_signal=0       # (bool  , init-time) default = '0'      : Use device-active signal
+fvp_mps2.sse200.cpu1dbg_ppu.revision="r0p0"           # (string, init-time) default = 'r0p0'   : Revision
+fvp_mps2.sse200.crypto_ppu.use_active_signal=0        # (bool  , init-time) default = '0'      : Use device-active signal
+fvp_mps2.sse200.crypto_ppu.revision="r0p0"            # (string, init-time) default = 'r0p0'   : Revision
+fvp_mps2.sse200.cordio_ppu.use_active_signal=0        # (bool  , init-time) default = '0'      : Use device-active signal
+fvp_mps2.sse200.cordio_ppu.revision="r0p0"            # (string, init-time) default = 'r0p0'   : Revision
+fvp_mps2.sse200.dbg_ppu.use_active_signal=0           # (bool  , init-time) default = '0'      : Use device-active signal
+fvp_mps2.sse200.dbg_ppu.revision="r0p0"               # (string, init-time) default = 'r0p0'   : Revision
+fvp_mps2.sse200.ram0_ppu.use_active_signal=0          # (bool  , init-time) default = '0'      : Use device-active signal
+fvp_mps2.sse200.ram0_ppu.revision="r0p0"              # (string, init-time) default = 'r0p0'   : Revision
+fvp_mps2.sse200.ram1_ppu.use_active_signal=0          # (bool  , init-time) default = '0'      : Use device-active signal
+fvp_mps2.sse200.ram1_ppu.revision="r0p0"              # (string, init-time) default = 'r0p0'   : Revision
+fvp_mps2.sse200.ram2_ppu.use_active_signal=0          # (bool  , init-time) default = '0'      : Use device-active signal
+fvp_mps2.sse200.ram2_ppu.revision="r0p0"              # (string, init-time) default = 'r0p0'   : Revision
+fvp_mps2.sse200.ram3_ppu.use_active_signal=0          # (bool  , init-time) default = '0'      : Use device-active signal
+fvp_mps2.sse200.ram3_ppu.revision="r0p0"              # (string, init-time) default = 'r0p0'   : Revision
+fvp_mps2.sse200.iotss_cpuidentity.debugger_master_id=0xFFFFFFFF  # (int   , init-time) default = '0xFFFFFFFF' :  : [0x0..0xFFFFFFFF]
+fvp_mps2.sse200.iotss_internal_sram0.size=0x100000000  # (int   , init-time) default = '0x100000000' : Memory Size
+fvp_mps2.sse200.iotss_internal_sram0.fill1=0xDFDFDFCF  # (int   , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.sse200.iotss_internal_sram0.fill2=0xCFDFDFDF  # (int   , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.sse200.iotss_internal_sram1.size=0x100000000  # (int   , init-time) default = '0x100000000' : Memory Size
+fvp_mps2.sse200.iotss_internal_sram1.fill1=0xDFDFDFCF  # (int   , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.sse200.iotss_internal_sram1.fill2=0xCFDFDFDF  # (int   , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.sse200.iotss_internal_sram2.size=0x100000000  # (int   , init-time) default = '0x100000000' : Memory Size
+fvp_mps2.sse200.iotss_internal_sram2.fill1=0xDFDFDFCF  # (int   , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.sse200.iotss_internal_sram2.fill2=0xCFDFDFDF  # (int   , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.sse200.iotss_internal_sram3.size=0x100000000  # (int   , init-time) default = '0x100000000' : Memory Size
+fvp_mps2.sse200.iotss_internal_sram3.fill1=0xDFDFDFCF  # (int   , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.sse200.iotss_internal_sram3.fill2=0xCFDFDFDF  # (int   , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
+fvp_mps2.sse200.bus_error_warning_memory.read_data=0x0  # (int   , init-time) default = '0x0'    : Data to return on reads, if not aborting
+fvp_mps2.sse200.exclusive_monitor_iotss_internal_sram.enable_component=1  # (bool  , init-time) default = '1'      : Enable component
+fvp_mps2.sse200.exclusive_monitor_iotss_internal_sram.number_of_monitors=0x8  # (int   , init-time) default = '0x8'    : Number of monitors : [0x1..0xFFFFFFFF]
+fvp_mps2.sse200.exclusive_monitor_iotss_internal_sram.log2_granule_size=0x0  # (int   , init-time) default = '0x0'    : log2 of address granule size : [0x0..0xB]
+fvp_mps2.sse200.exclusive_monitor_iotss_internal_sram.monitor_non_excl_stores=0  # (bool  , init-time) default = '0'      : Monitor non-exclusive stores from the same master
+fvp_mps2.sse200.exclusive_monitor_iotss_internal_sram.match_secure_state=1  # (bool  , init-time) default = '1'      : Treat the secure state like an address bit
+fvp_mps2.sse200.exclusive_monitor_iotss_internal_sram.shareability_domain=0x3  # (int   , init-time) default = '0x3'    : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
+fvp_mps2.sse200.exclusive_monitor_iotss_internal_sram.apply_access_width_criteria_to_non_excl_stores=1  # (bool  , init-time) default = '1'      : Apply the given exclusive store width matching criteria to non-exclusive stores
+fvp_mps2.mps2_secure_control_register_block.FLASH_BLOCK_CFG=0x3  # (int   , init-time) default = '0x3'    : Flash Block size configuration : [0x0..0x31]
+fvp_mps2.mps2_secure_control_register_block.SRAM_BLOCK_CFG=0x3  # (int   , init-time) default = '0x3'    : SRAM Block size configuration : [0x0..0x31]
+fvp_mps2.mps2_secure_control_register_block.FLASH_WATERMARK_SUPPORTED=1  # (bool  , init-time) default = '1'      : Flash Watermark supported
+fvp_mps2.mps2_secure_control_register_block.SRAM_WATERMARK_SUPPORTED=1  # (bool  , init-time) default = '1'      : SRAM Watermark supported
+fvp_mps2.mps2_secure_control_register_block.APBPPCEXP_DIS0=0x0  # (int   , init-time) default = '0x0'    : Disables support for individual bits on the APBNSPPCEXP0 and APBPPPCEXP0 buses : [0x0..0xFFFF]
+fvp_mps2.mps2_secure_control_register_block.APBPPCEXP_DIS1=0x0  # (int   , init-time) default = '0x0'    : Disables support for individual bits on the APBNSPPCEXP1 and APBPPPCEXP1 buses : [0x0..0xFFFF]
+fvp_mps2.mps2_secure_control_register_block.APBPPCEXP_DIS2=0x0  # (int   , init-time) default = '0x0'    : Disables support for individual bits on the APBNSPPCEXP2 and APBPPPCEXP2 buses : [0x0..0xFFFF]
+fvp_mps2.mps2_secure_control_register_block.APBPPCEXP_DIS3=0x0  # (int   , init-time) default = '0x0'    : Disables support for individual bits on the APBNSPPCEXP3 and APBPPPCEXP3 buses : [0x0..0xFFFF]
+fvp_mps2.mps2_secure_control_register_block.AHBPPCEXP_DIS0=0x0  # (int   , init-time) default = '0x0'    : Disables support for individual bits on the AHBNSPPCEXP0 and AHBPPPCEXP0 buses : [0x0..0xFFFF]
+fvp_mps2.mps2_secure_control_register_block.AHBPPCEXP_DIS1=0x0  # (int   , init-time) default = '0x0'    : Disables support for individual bits on the AHBNSPPCEXP1 and AHBPPPCEXP1 buses : [0x0..0xFFFF]
+fvp_mps2.mps2_secure_control_register_block.AHBPPCEXP_DIS2=0x0  # (int   , init-time) default = '0x0'    : Disables support for individual bits on the AHBNSPPCEXP2 and AHBPPPCEXP2 buses : [0x0..0xFFFF]
+fvp_mps2.mps2_secure_control_register_block.AHBPPCEXP_DIS3=0x0  # (int   , init-time) default = '0x0'    : Disables support for individual bits on the AHBNSPPCEXP3 and AHBPPPCEXP3 buses : [0x0..0xFFFF]
+fvp_mps2.ahb_ppc_iotss_expansion0.NONSEC_MASK=0x0     # (int   , init-time) default = '0x0'    : 16-bit wide mask for security checking of ports: 0 = check, 1 = mask : [0x0..0x1]
+fvp_mps2.ahb_ppc_iotss_expansion1.NONSEC_MASK=0x0     # (int   , init-time) default = '0x0'    : 16-bit wide mask for security checking of ports: 0 = check, 1 = mask : [0x0..0x1]
+fvp_mps2.apb_ppc_iotss_expansion0.NONSEC_MASK=0x0     # (int   , init-time) default = '0x0'    : 16-bit wide mask for security checking of ports: 0 = check, 1 = mask : [0x0..0x1]
+fvp_mps2.apb_ppc_iotss_expansion1.NONSEC_MASK=0x0     # (int   , init-time) default = '0x0'    : 16-bit wide mask for security checking of ports: 0 = check, 1 = mask : [0x0..0x1]
+fvp_mps2.apb_ppc_iotss_expansion2.NONSEC_MASK=0x0     # (int   , init-time) default = '0x0'    : 16-bit wide mask for security checking of ports: 0 = check, 1 = mask : [0x0..0x1]
+fvp_mps2.exclusive_monitor_psram.enable_component=1   # (bool  , init-time) default = '1'      : Enable component
+fvp_mps2.exclusive_monitor_psram.number_of_monitors=0x8  # (int   , init-time) default = '0x8'    : Number of monitors : [0x1..0xFFFFFFFF]
+fvp_mps2.exclusive_monitor_psram.log2_granule_size=0x0  # (int   , init-time) default = '0x0'    : log2 of address granule size : [0x0..0xB]
+fvp_mps2.exclusive_monitor_psram.monitor_non_excl_stores=0  # (bool  , init-time) default = '0'      : Monitor non-exclusive stores from the same master
+fvp_mps2.exclusive_monitor_psram.match_secure_state=1  # (bool  , init-time) default = '1'      : Treat the secure state like an address bit
+fvp_mps2.exclusive_monitor_psram.shareability_domain=0x3  # (int   , init-time) default = '0x3'    : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
+fvp_mps2.exclusive_monitor_psram.apply_access_width_criteria_to_non_excl_stores=1  # (bool  , init-time) default = '1'      : Apply the given exclusive store width matching criteria to non-exclusive stores
+fvp_mps2.exclusive_monitor_psram_iotss.enable_component=1  # (bool  , init-time) default = '1'      : Enable component
+fvp_mps2.exclusive_monitor_psram_iotss.number_of_monitors=0x8  # (int   , init-time) default = '0x8'    : Number of monitors : [0x1..0xFFFFFFFF]
+fvp_mps2.exclusive_monitor_psram_iotss.log2_granule_size=0x0  # (int   , init-time) default = '0x0'    : log2 of address granule size : [0x0..0xB]
+fvp_mps2.exclusive_monitor_psram_iotss.monitor_non_excl_stores=0  # (bool  , init-time) default = '0'      : Monitor non-exclusive stores from the same master
+fvp_mps2.exclusive_monitor_psram_iotss.match_secure_state=1  # (bool  , init-time) default = '1'      : Treat the secure state like an address bit
+fvp_mps2.exclusive_monitor_psram_iotss.shareability_domain=0x3  # (int   , init-time) default = '0x3'    : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
+fvp_mps2.exclusive_monitor_psram_iotss.apply_access_width_criteria_to_non_excl_stores=1  # (bool  , init-time) default = '1'      : Apply the given exclusive store width matching criteria to non-exclusive stores
+fvp_mps2.exclusive_monitor_zbtsram1.enable_component=1  # (bool  , init-time) default = '1'      : Enable component
+fvp_mps2.exclusive_monitor_zbtsram1.number_of_monitors=0x8  # (int   , init-time) default = '0x8'    : Number of monitors : [0x1..0xFFFFFFFF]
+fvp_mps2.exclusive_monitor_zbtsram1.log2_granule_size=0x0  # (int   , init-time) default = '0x0'    : log2 of address granule size : [0x0..0xB]
+fvp_mps2.exclusive_monitor_zbtsram1.monitor_non_excl_stores=0  # (bool  , init-time) default = '0'      : Monitor non-exclusive stores from the same master
+fvp_mps2.exclusive_monitor_zbtsram1.match_secure_state=1  # (bool  , init-time) default = '1'      : Treat the secure state like an address bit
+fvp_mps2.exclusive_monitor_zbtsram1.shareability_domain=0x3  # (int   , init-time) default = '0x3'    : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
+fvp_mps2.exclusive_monitor_zbtsram1.apply_access_width_criteria_to_non_excl_stores=1  # (bool  , init-time) default = '1'      : Apply the given exclusive store width matching criteria to non-exclusive stores
+fvp_mps2.exclusive_monitor_zbtsram2.enable_component=1  # (bool  , init-time) default = '1'      : Enable component
+fvp_mps2.exclusive_monitor_zbtsram2.number_of_monitors=0x8  # (int   , init-time) default = '0x8'    : Number of monitors : [0x1..0xFFFFFFFF]
+fvp_mps2.exclusive_monitor_zbtsram2.log2_granule_size=0x0  # (int   , init-time) default = '0x0'    : log2 of address granule size : [0x0..0xB]
+fvp_mps2.exclusive_monitor_zbtsram2.monitor_non_excl_stores=0  # (bool  , init-time) default = '0'      : Monitor non-exclusive stores from the same master
+fvp_mps2.exclusive_monitor_zbtsram2.match_secure_state=1  # (bool  , init-time) default = '1'      : Treat the secure state like an address bit
+fvp_mps2.exclusive_monitor_zbtsram2.shareability_domain=0x3  # (int   , init-time) default = '0x3'    : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
+fvp_mps2.exclusive_monitor_zbtsram2.apply_access_width_criteria_to_non_excl_stores=1  # (bool  , init-time) default = '1'      : Apply the given exclusive store width matching criteria to non-exclusive stores
+fvp_mps2.mps2_exclusive_monitor_zbtsram1.enable_component=1  # (bool  , init-time) default = '1'      : Enable component
+fvp_mps2.mps2_exclusive_monitor_zbtsram1.number_of_monitors=0x8  # (int   , init-time) default = '0x8'    : Number of monitors : [0x1..0xFFFFFFFF]
+fvp_mps2.mps2_exclusive_monitor_zbtsram1.log2_granule_size=0x0  # (int   , init-time) default = '0x0'    : log2 of address granule size : [0x0..0xB]
+fvp_mps2.mps2_exclusive_monitor_zbtsram1.monitor_non_excl_stores=0  # (bool  , init-time) default = '0'      : Monitor non-exclusive stores from the same master
+fvp_mps2.mps2_exclusive_monitor_zbtsram1.match_secure_state=1  # (bool  , init-time) default = '1'      : Treat the secure state like an address bit
+fvp_mps2.mps2_exclusive_monitor_zbtsram1.shareability_domain=0x3  # (int   , init-time) default = '0x3'    : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
+fvp_mps2.mps2_exclusive_monitor_zbtsram1.apply_access_width_criteria_to_non_excl_stores=1  # (bool  , init-time) default = '1'      : Apply the given exclusive store width matching criteria to non-exclusive stores
+fvp_mps2.mps2_exclusive_monitor_zbtsram2.enable_component=1  # (bool  , init-time) default = '1'      : Enable component
+fvp_mps2.mps2_exclusive_monitor_zbtsram2.number_of_monitors=0x8  # (int   , init-time) default = '0x8'    : Number of monitors : [0x1..0xFFFFFFFF]
+fvp_mps2.mps2_exclusive_monitor_zbtsram2.log2_granule_size=0x0  # (int   , init-time) default = '0x0'    : log2 of address granule size : [0x0..0xB]
+fvp_mps2.mps2_exclusive_monitor_zbtsram2.monitor_non_excl_stores=0  # (bool  , init-time) default = '0'      : Monitor non-exclusive stores from the same master
+fvp_mps2.mps2_exclusive_monitor_zbtsram2.match_secure_state=1  # (bool  , init-time) default = '1'      : Treat the secure state like an address bit
+fvp_mps2.mps2_exclusive_monitor_zbtsram2.shareability_domain=0x3  # (int   , init-time) default = '0x3'    : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
+fvp_mps2.mps2_exclusive_monitor_zbtsram2.apply_access_width_criteria_to_non_excl_stores=1  # (bool  , init-time) default = '1'      : Apply the given exclusive store width matching criteria to non-exclusive stores
+fvp_mps2.dma0_securitymodifier.behaviour_ns_to_s=0x0  # (int   , init-time) default = '0x0'    : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
+fvp_mps2.dma1_securitymodifier.behaviour_ns_to_s=0x0  # (int   , init-time) default = '0x0'    : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
+fvp_mps2.dma2_securitymodifier.behaviour_ns_to_s=0x0  # (int   , init-time) default = '0x0'    : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
+fvp_mps2.dma3_securitymodifier.behaviour_ns_to_s=0x0  # (int   , init-time) default = '0x0'    : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
+fvp_mps2.dma0.fifo_size=0x10                          # (int   , init-time) default = '0x10'   : Channel FIFO size in bytes
+fvp_mps2.dma0.max_transfer=0x100                      # (int   , init-time) default = '0x100'  : Largest atomic transfer
+fvp_mps2.dma0.generate_clear=0                        # (bool  , init-time) default = '0'      : Generate clear response
+fvp_mps2.dma0.activate_delay=0x0                      # (int   , init-time) default = '0x0'    : request delay
+fvp_mps2.dma1.fifo_size=0x10                          # (int   , init-time) default = '0x10'   : Channel FIFO size in bytes
+fvp_mps2.dma1.max_transfer=0x100                      # (int   , init-time) default = '0x100'  : Largest atomic transfer
+fvp_mps2.dma1.generate_clear=0                        # (bool  , init-time) default = '0'      : Generate clear response
+fvp_mps2.dma1.activate_delay=0x0                      # (int   , init-time) default = '0x0'    : request delay
+fvp_mps2.dma2.fifo_size=0x10                          # (int   , init-time) default = '0x10'   : Channel FIFO size in bytes
+fvp_mps2.dma2.max_transfer=0x100                      # (int   , init-time) default = '0x100'  : Largest atomic transfer
+fvp_mps2.dma2.generate_clear=0                        # (bool  , init-time) default = '0'      : Generate clear response
+fvp_mps2.dma2.activate_delay=0x0                      # (int   , init-time) default = '0x0'    : request delay
+fvp_mps2.dma3.fifo_size=0x10                          # (int   , init-time) default = '0x10'   : Channel FIFO size in bytes
+fvp_mps2.dma3.max_transfer=0x100                      # (int   , init-time) default = '0x100'  : Largest atomic transfer
+fvp_mps2.dma3.generate_clear=0                        # (bool  , init-time) default = '0'      : Generate clear response
+fvp_mps2.dma3.activate_delay=0x0                      # (int   , init-time) default = '0x0'    : request delay
+armcortexm0ct.semihosting-enable=1                    # (bool  , init-time) default = '1'      : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
+armcortexm0ct.semihosting-Thumb_SVC=0xAB              # (int   , init-time) default = '0xAB'   : T32 SVC number for semihosting : [0x0..0xFF]
+armcortexm0ct.semihosting-cmd_line=""                 # (string, init-time) default = ''       : Command line available to semihosting SVC calls
+armcortexm0ct.semihosting-heap_base=0x0               # (int   , init-time) default = '0x0'    : Virtual address of heap base : [0x0..0xFFFFFFFF]
+armcortexm0ct.semihosting-heap_limit=0x0              # (int   , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]
+armcortexm0ct.semihosting-stack_base=0x0              # (int   , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]
+armcortexm0ct.semihosting-stack_limit=0x0             # (int   , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]
+armcortexm0ct.semihosting-cwd=""                      # (string, init-time) default = ''       : Base directory for semihosting file access.
+armcortexm0ct.NUM_IRQ=0x20                            # (int   , init-time) default = '0x20'   : Number of user interrupts : [0x1..0x20]
+armcortexm0ct.BIGENDINIT=0                            # (bool  , init-time) default = '0'      : Initialize processor to big endian mode
+armcortexm0ct.min_sync_level=0x0                      # (int   , run-time ) default = '0x0'    : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3]
+armcortexm0ct.cpi_mul=0x1                             # (int   , run-time ) default = '0x1'    : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
+armcortexm0ct.cpi_div=0x1                             # (int   , run-time ) default = '0x1'    : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
+armcortexm0ct.master_id=0x0                           # (int   , init-time) default = '0x0'    : Master ID presented in bus transactions : [0x0..0xFFFFFFFF]
+armcortexm0ct.DBG=1                                   # (bool  , init-time) default = '1'      : Set whether debug extensions are implemented
+armcortexm0ct.BKPT=0x4                                # (int   , init-time) default = '0x4'    : Number of breakpoint unit comparators implemented : [0x0..0x4]
+armcortexm0ct.WPT=0x2                                 # (int   , init-time) default = '0x2'    : Number of watchpoint unit comparators implemented : [0x0..0x2]
+armcortexm0ct.SYST=1                                  # (bool  , init-time) default = '1'      : Enable support for SysTick timer functionality
+armcortexm0ct.WIC=1                                   # (bool  , init-time) default = '1'      : Include support for WIC-mode deep sleep
+#----------------------------------------------------------------------------------------------

CMSIS/CoreValidation/Tests/Cortex-M3/AC5/CMSIS_CV.uvprojx

@@ -16,7 +16,7 @@
         <TargetCommonOption>
           <Device>ARMCM3</Device>
           <Vendor>ARM</Vendor>
-          <PackID>ARM.CMSIS.5.1.1</PackID>
+          <PackID>ARM.CMSIS.5.1.2-dev1</PackID>
           <PackURL>http://www.keil.com/pack/</PackURL>
           <Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M3") CLOCK(12000000) ESEL ELITTLE</Cpu>
           <FlashUtilSpec></FlashUtilSpec>
@@ -370,7 +370,7 @@
             <ScatterFile></ScatterFile>
             <IncludeLibs></IncludeLibs>
             <IncludeLibsPath></IncludeLibsPath>
-            <Misc></Misc>
+            <Misc>--entry=Reset_Handler</Misc>
             <LinkerInputFile></LinkerInputFile>
             <DisabledWarnings></DisabledWarnings>
           </LDads>
@@ -464,7 +464,7 @@
       <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM3\Source\ARM\startup_ARMCM3.s" version="1.0.0">
         <instance index="0">RTE\Device\ARMCM3\startup_ARMCM3.s</instance>
         <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS"/>
-        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
         <targetInfos>
           <targetInfo name="FVP"/>
         </targetInfos>
@@ -472,7 +472,7 @@
       <file attr="config" category="sourceC" name="Device\ARM\ARMCM3\Source\system_ARMCM3.c" version="1.0.0">
         <instance index="0">RTE\Device\ARMCM3\system_ARMCM3.c</instance>
         <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS"/>
-        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
         <targetInfos>
           <targetInfo name="FVP"/>
         </targetInfos>

CMSIS/CoreValidation/Tests/Cortex-M3/AC6/CMSIS_CV.uvprojx

@@ -16,7 +16,7 @@
         <TargetCommonOption>
           <Device>ARMCM3</Device>
           <Vendor>ARM</Vendor>
-          <PackID>ARM.CMSIS.5.1.1</PackID>
+          <PackID>ARM.CMSIS.5.1.2-dev1</PackID>
           <PackURL>http://www.keil.com/pack/</PackURL>
           <Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M3") CLOCK(12000000) ESEL ELITTLE</Cpu>
           <FlashUtilSpec></FlashUtilSpec>
@@ -311,7 +311,7 @@
           </ArmAdsMisc>
           <Cads>
             <interw>1</interw>
-            <Optim>2</Optim>
+            <Optim>1</Optim>
             <oTime>0</oTime>
             <SplitLS>0</SplitLS>
             <OneElfS>1</OneElfS>
@@ -333,7 +333,7 @@
             <v6WtE>0</v6WtE>
             <v6Rtti>0</v6Rtti>
             <VariousControls>
-              <MiscControls></MiscControls>
+              <MiscControls>-Wno-covered-switch-default</MiscControls>
               <Define></Define>
               <Undefine></Undefine>
               <IncludePath>.\,..\..\..\Include</IncludePath>
@@ -370,7 +370,7 @@
             <ScatterFile></ScatterFile>
             <IncludeLibs></IncludeLibs>
             <IncludeLibsPath></IncludeLibsPath>
-            <Misc></Misc>
+            <Misc>--entry=Reset_Handler</Misc>
             <LinkerInputFile></LinkerInputFile>
             <DisabledWarnings></DisabledWarnings>
           </LDads>
@@ -464,7 +464,7 @@
       <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM3\Source\ARM\startup_ARMCM3.s" version="1.0.0">
         <instance index="0">RTE\Device\ARMCM3\startup_ARMCM3.s</instance>
         <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS"/>
-        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
         <targetInfos>
           <targetInfo name="FVP"/>
         </targetInfos>
@@ -472,7 +472,7 @@
       <file attr="config" category="sourceC" name="Device\ARM\ARMCM3\Source\system_ARMCM3.c" version="1.0.0">
         <instance index="0">RTE\Device\ARMCM3\system_ARMCM3.c</instance>
         <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS"/>
-        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
         <targetInfos>
           <targetInfo name="FVP"/>
         </targetInfos>

CMSIS/CoreValidation/Tests/Cortex-M3/GCC/CMSIS_CV.uvprojx

@@ -0,0 +1,404 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>FVP</TargetName>
+      <ToolsetNumber>0x3</ToolsetNumber>
+      <ToolsetName>ARM-GNU</ToolsetName>
+      <pArmCC>6070000::V6.7::.\ARMCLANG</pArmCC>
+      <pCCUsed>6070000::V6.7::.\ARMCLANG</pCCUsed>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>ARMCM3</Device>
+          <Vendor>ARM</Vendor>
+          <PackID>ARM.CMSIS.5.1.2-dev1</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M3") CLOCK(12000000) ESEL ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:ARMCM3$Device\ARM\ARMCM3\Include\ARMCM3.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:ARMCM3$Device\ARM\SVD\ARMCM3.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\Objects\</OutputDirectory>
+          <OutputName>CMSIS_CV</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\Listings\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>  -MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> -MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArm>
+          <ArmMisc>
+            <asLst>1</asLst>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>1</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <GCPUTYP>"Cortex-M3"</GCPUTYP>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <IRAM2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </IRAM2>
+              <IROM2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </IROM2>
+            </OnChipMemories>
+          </ArmMisc>
+          <Carm>
+            <arpcs>1</arpcs>
+            <stkchk>0</stkchk>
+            <reentr>0</reentr>
+            <interw>1</interw>
+            <bigend>0</bigend>
+            <Strict>0</Strict>
+            <Optim>1</Optim>
+            <wLevel>3</wLevel>
+            <uThumb>1</uThumb>
+            <VariousControls>
+              <MiscControls>-Wall -Wextra -Wstrict-prototypes -Wshadow</MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>.;..\..\..\Include</IncludePath>
+            </VariousControls>
+          </Carm>
+          <Aarm>
+            <bBE>0</bBE>
+            <interw>1</interw>
+            <VariousControls>
+              <MiscControls>-Wall</MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>.;..\..\..\Include</IncludePath>
+            </VariousControls>
+          </Aarm>
+          <LDarm>
+            <umfTarg>1</umfTarg>
+            <enaGarb>0</enaGarb>
+            <noStart>0</noStart>
+            <noStLib>0</noStLib>
+            <uMathLib>0</uMathLib>
+            <TextAddressRange></TextAddressRange>
+            <DataAddressRange></DataAddressRange>
+            <BSSAddressRange></BSSAddressRange>
+            <IncludeLibs></IncludeLibs>
+            <IncludeDir></IncludeDir>
+            <Misc>--specs=rdimon.specs</Misc>
+            <ScatterFile>.\RTE\Device\ARMCM3\gcc_arm.ld</ScatterFile>
+          </LDarm>
+        </TargetArm>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Test</GroupName>
+          <Files>
+            <File>
+              <FileName>cmsis_cv.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\cmsis_cv.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_CoreFunc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_CoreFunc.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_CoreInstr.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_CoreInstr.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Framework.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_Framework.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_MPU_ARMv7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_MPU_ARMv7.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Report.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_Report.c</FilePath>
+            </File>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\main.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Config.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\CV_Config.h</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::CMSIS</GroupName>
+        </Group>
+        <Group>
+          <GroupName>::Device</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components>
+      <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.0.2" condition="ARMv6_7_8-M Device">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS GCC">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </component>
+    </components>
+    <files>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM0\Source\ARM\startup_ARMCM0.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM0\startup_ARMCM0.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM0\Source\system_ARMCM0.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM0\system_ARMCM0.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="linkerScript" condition="GCC" name="Device\ARM\ARMCM3\Source\GCC\gcc_arm.ld" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM3\gcc_arm.ld</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="sourceAsm" condition="GCC" name="Device\ARM\ARMCM3\Source\GCC\startup_ARMCM3.S" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM3\startup_ARMCM3.S</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" condition="GCC" name="Device\ARM\ARMCM3\Source\GCC\startup_ARMCM3.c" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM3\startup_ARMCM3.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM3\Source\system_ARMCM3.c" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM3\system_ARMCM3.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos>
+          <targetInfo name="FVP"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM4\Source\ARM\startup_ARMCM4.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM4\startup_ARMCM4.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM4\Source\system_ARMCM4.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM4\system_ARMCM4.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <targetInfos/>
+      </file>
+    </files>
+  </RTE>
+
+</Project>

CMSIS/CoreValidation/Tests/Cortex-M3/GCC/CV_Config.h

@@ -0,0 +1,82 @@
+/*-----------------------------------------------------------------------------
+ *      Name:         CV_Config.h 
+ *      Purpose:      CV Config header
+ *----------------------------------------------------------------------------
+ *      Copyright (c) 2017 ARM Limited. All rights reserved.
+ *----------------------------------------------------------------------------*/
+#ifndef __CV_CONFIG_H
+#define __CV_CONFIG_H
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+#define RTE_CV_COREINSTR 1
+#define RTE_CV_COREFUNC  1
+#define RTE_CV_MPUFUNC   1
+
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h> Common Test Settings
+// <o> Print Output Format <0=> Plain Text <1=> XML
+// <i> Set the test results output format to plain text or XML
+#ifndef PRINT_XML_REPORT
+#define PRINT_XML_REPORT            1
+#endif
+// <o> Buffer size for assertions results
+// <i> Set the buffer size for assertions results buffer
+#define BUFFER_ASSERTIONS           128U
+// </h>
+
+// <h> Disable Test Cases
+// <i> Uncheck to disable an individual test case
+// <q00> TC_CoreInstr_NOP
+// <q01> TC_CoreInstr_REV
+// <q02> TC_CoreInstr_REV16
+// <q03> TC_CoreInstr_REVSH
+// <q04> TC_CoreInstr_ROR
+// <q05> TC_CoreInstr_RBIT
+// <q06> TC_CoreInstr_CLZ
+// <q07> TC_CoreInstr_SSAT
+// <q08> TC_CoreInstr_USAT
+//
+// <q09> TC_CoreFunc_EnDisIRQ
+// <q10> TC_CoreFunc_Control
+// <q11> TC_CoreFunc_IPSR
+// <q12> TC_CoreFunc_APSR
+// <q13> TC_CoreFunc_PSP
+// <q14> TC_CoreFunc_MSP
+// <q15> TC_CoreFunc_PRIMASK
+// <q16> TC_CoreFunc_FAULTMASK
+// <q17> TC_CoreFunc_BASEPRI
+// <q18> TC_CoreFunc_FPSCR
+//
+// <q19> TC_MPU_SetClear
+// <q20> TC_MPU_Load
+#define TC_COREINSTR_NOP_EN         1
+#define TC_COREINSTR_REV_EN         1
+#define TC_COREINSTR_REV16_EN       1
+#define TC_COREINSTR_REVSH_EN       1
+#define TC_COREINSTR_ROR_EN         1
+#define TC_COREINSTR_RBIT_EN        1
+#define TC_COREINSTR_CLZ_EN         1
+#define TC_COREINSTR_SSAT_EN        1
+#define TC_COREINSTR_USAT_EN        1
+
+#define TC_COREFUNC_ENDISIRQ_EN     1
+#define TC_COREFUNC_CONTROL_EN      1
+#define TC_COREFUNC_IPSR_EN         1
+#define TC_COREFUNC_APSR_EN         1
+#define TC_COREFUNC_PSP_EN          1
+#define TC_COREFUNC_MSP_EN          1
+#define TC_COREFUNC_PRIMASK_EN      1
+#define TC_COREFUNC_FAULTMASK_EN    1
+#define TC_COREFUNC_BASEPRI_EN      1
+#define TC_COREFUNC_FPSCR_EN        1
+
+#define TC_MPU_SETCLEAR_EN          1
+#define TC_MPU_LOAD_EN              1
+// </h>
+
+#endif /* __CV_CONFIG_H */
+

CMSIS/CoreValidation/Tests/Cortex-M3/GCC/EventRecorderStub.scvd

@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
+
+<component name="EventRecorderStub" version="1.0.0"/>       <!--name and version of the component-->
+  <events>
+  </events>
+
+</component_viewer>

CMSIS/CoreValidation/Tests/Cortex-M3/GCC/RTE/Device/ARMCM3/gcc_arm.ld

@@ -0,0 +1,196 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+  FLASH (rx)  : ORIGIN = 0x00000000, LENGTH = 512K
+  RAM   (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapBase
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __Vectors_End
+ *   __Vectors_Size
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+	.text :
+	{
+		KEEP(*(.vectors))
+		__Vectors_End = .;
+		__Vectors_Size = __Vectors_End - __Vectors;
+		__end__ = .;
+
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+	.ARM.extab :
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	/* To copy multiple ROM to RAM sections,
+	 * uncomment .copy.table section and,
+	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.copy.table :
+	{
+		. = ALIGN(4);
+		__copy_table_start__ = .;
+		LONG (__etext)
+		LONG (__data_start__)
+		LONG (__data_end__ - __data_start__)
+		LONG (__etext2)
+		LONG (__data2_start__)
+		LONG (__data2_end__ - __data2_start__)
+		__copy_table_end__ = .;
+	} > FLASH
+	*/
+
+	/* To clear multiple BSS sections,
+	 * uncomment .zero.table section and,
+	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.zero.table :
+	{
+		. = ALIGN(4);
+		__zero_table_start__ = .;
+		LONG (__bss_start__)
+		LONG (__bss_end__ - __bss_start__)
+		LONG (__bss2_start__)
+		LONG (__bss2_end__ - __bss2_start__)
+		__zero_table_end__ = .;
+	} > FLASH
+	*/
+
+	__etext = .;
+
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		KEEP(*(.jcr*))
+		. = ALIGN(4);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > RAM
+
+	.heap (COPY):
+	{
+		__HeapBase = .;
+		__end__ = .;
+		end = __end__;
+		KEEP(*(.heap*))
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (COPY):
+	{
+		KEEP(*(.stack*))
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM);
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}

CMSIS/CoreValidation/Tests/Cortex-M3/GCC/RTE/Device/ARMCM3/startup_ARMCM3.c

@@ -0,0 +1,295 @@
+/**************************************************************************//**
+ * @file     startup_ARMCM3.s
+ * @brief    CMSIS Core Device Startup File for
+ *           ARMCM3 Device Series
+ * @version  V5.00
+ * @date     26. April 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdint.h>
+
+
+/*----------------------------------------------------------------------------
+  Linker generated Symbols
+ *----------------------------------------------------------------------------*/
+extern uint32_t __etext;
+extern uint32_t __data_start__;
+extern uint32_t __data_end__;
+extern uint32_t __copy_table_start__;
+extern uint32_t __copy_table_end__;
+extern uint32_t __zero_table_start__;
+extern uint32_t __zero_table_end__;
+extern uint32_t __bss_start__;
+extern uint32_t __bss_end__;
+extern uint32_t __StackTop;
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler Function Prototype
+ *----------------------------------------------------------------------------*/
+typedef void( *pFunc )( void );
+
+
+/*----------------------------------------------------------------------------
+  External References
+ *----------------------------------------------------------------------------*/
+#ifndef __START
+extern void  _start(void) __attribute__((noreturn));    /* PreeMain (C library entry point) */
+#else
+extern int  __START(void) __attribute__((noreturn));    /* main entry point */
+#endif
+
+#ifndef __NO_SYSTEM_INIT
+extern void SystemInit (void);            /* CMSIS System Initialization      */
+#endif
+
+
+/*----------------------------------------------------------------------------
+  Internal References
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void);                          /* Default empty handler */
+void Reset_Handler(void);                            /* Reset Handler */
+
+
+/*----------------------------------------------------------------------------
+  User Initial Stack & Heap
+ *----------------------------------------------------------------------------*/
+#ifndef __STACK_SIZE
+  #define	__STACK_SIZE  0x00000400
+#endif
+static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack")));
+
+#ifndef __HEAP_SIZE
+  #define	__HEAP_SIZE   0x00000C00
+#endif
+#if __HEAP_SIZE > 0
+static uint8_t heap[__HEAP_SIZE]   __attribute__ ((aligned(8), used, section(".heap")));
+#endif
+
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Cortex-M3 Processor Exceptions */
+void NMI_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void MemManage_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler     (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/* ARMCM3 Specific Interrupts */
+void WDT_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void RTC_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void TIM0_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void TIM2_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void MCIA_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void MCIB_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART0_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART1_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART2_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART4_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void AACI_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void CLCD_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void ENET_IRQHandler     (void) __attribute__ ((weak, alias("Default_Handler")));
+void USBDC_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void USBHC_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void CHLCD_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void FLEXRAY_IRQHandler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void CAN_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void LIN_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void I2C_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+void CPU_CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UART3_IRQHandler    (void) __attribute__ ((weak, alias("Default_Handler")));
+void SPI_IRQHandler      (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = {
+  /* Cortex-M3 Exceptions Handler */
+  (pFunc)((uint32_t)&__StackTop),           /*      Initial Stack Pointer     */
+  Reset_Handler,                            /*      Reset Handler             */
+  NMI_Handler,                              /*      NMI Handler               */
+  HardFault_Handler,                        /*      Hard Fault Handler        */
+  MemManage_Handler,                        /*      MPU Fault Handler         */
+  BusFault_Handler,                         /*      Bus Fault Handler         */
+  UsageFault_Handler,                       /*      Usage Fault Handler       */
+  0,                                        /*      Reserved                  */
+  0,                                        /*      Reserved                  */
+  0,                                        /*      Reserved                  */
+  0,                                        /*      Reserved                  */
+  SVC_Handler,                              /*      SVCall Handler            */
+  DebugMon_Handler,                         /*      Debug Monitor Handler     */
+  0,                                        /*      Reserved                  */
+  PendSV_Handler,                           /*      PendSV Handler            */
+  SysTick_Handler,                          /*      SysTick Handler           */
+
+  /* External interrupts */
+  WDT_IRQHandler,                           /*  0:  Watchdog Timer            */
+  RTC_IRQHandler,                           /*  1:  Real Time Clock           */
+  TIM0_IRQHandler,                          /*  2:  Timer0 / Timer1           */
+  TIM2_IRQHandler,                          /*  3:  Timer2 / Timer3           */
+  MCIA_IRQHandler,                          /*  4:  MCIa                      */
+  MCIB_IRQHandler,                          /*  5:  MCIb                      */
+  UART0_IRQHandler,                         /*  6:  UART0 - DUT FPGA          */
+  UART1_IRQHandler,                         /*  7:  UART1 - DUT FPGA          */
+  UART2_IRQHandler,                         /*  8:  UART2 - DUT FPGA          */
+  UART4_IRQHandler,                         /*  9:  UART4 - not connected     */
+  AACI_IRQHandler,                          /* 10: AACI / AC97                */
+  CLCD_IRQHandler,                          /* 11: CLCD Combined Interrupt    */
+  ENET_IRQHandler,                          /* 12: Ethernet                   */
+  USBDC_IRQHandler,                         /* 13: USB Device                 */
+  USBHC_IRQHandler,                         /* 14: USB Host Controller        */
+  CHLCD_IRQHandler,                         /* 15: Character LCD              */
+  FLEXRAY_IRQHandler,                       /* 16: Flexray                    */
+  CAN_IRQHandler,                           /* 17: CAN                        */
+  LIN_IRQHandler,                           /* 18: LIN                        */
+  I2C_IRQHandler,                           /* 19: I2C ADC/DAC                */
+  0,                                        /* 20: Reserved                   */
+  0,                                        /* 21: Reserved                   */
+  0,                                        /* 22: Reserved                   */
+  0,                                        /* 23: Reserved                   */
+  0,                                        /* 24: Reserved                   */
+  0,                                        /* 25: Reserved                   */
+  0,                                        /* 26: Reserved                   */
+  0,                                        /* 27: Reserved                   */
+  CPU_CLCD_IRQHandler,                      /* 28: Reserved - CPU FPGA CLCD   */
+  0,                                        /* 29: Reserved - CPU FPGA        */
+  UART3_IRQHandler,                         /* 30: UART3    - CPU FPGA        */
+  SPI_IRQHandler                            /* 31: SPI Touchscreen - CPU FPGA */
+};
+
+
+/*----------------------------------------------------------------------------
+  Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+  uint32_t *pSrc, *pDest;
+  uint32_t *pTable __attribute__((unused));
+
+/*  Firstly it copies data from read only memory to RAM. There are two schemes
+ *  to copy. One can copy more than one sections. Another can only copy
+ *  one section.  The former scheme needs more instructions and read-only
+ *  data to implement than the latter.
+ *  Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.  */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/*  Multiple sections scheme.
+ *
+ *  Between symbol address __copy_table_start__ and __copy_table_end__,
+ *  there are array of triplets, each of which specify:
+ *    offset 0: LMA of start of a section to copy from
+ *    offset 4: VMA of start of a section to copy to
+ *    offset 8: size of the section to copy. Must be multiply of 4
+ *
+ *  All addresses must be aligned to 4 bytes boundary.
+ */
+  pTable = &__copy_table_start__;
+
+  for (; pTable < &__copy_table_end__; pTable = pTable + 3) {
+		pSrc  = (uint32_t*)*(pTable + 0);
+		pDest = (uint32_t*)*(pTable + 1);
+		for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
+      *pDest++ = *pSrc++;
+		}
+	}
+#else
+/*  Single section scheme.
+ *
+ *  The ranges of copy from/to are specified by following symbols
+ *    __etext: LMA of start of the section to copy from. Usually end of text
+ *    __data_start__: VMA of start of the section to copy to
+ *    __data_end__: VMA of end of the section to copy to
+ *
+ *  All addresses must be aligned to 4 bytes boundary.
+ */
+  pSrc  = &__etext;
+  pDest = &__data_start__;
+
+  for ( ; pDest < &__data_end__ ; ) {
+    *pDest++ = *pSrc++;
+  }
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/*  This part of work usually is done in C library startup code. Otherwise,
+ *  define this macro to enable it in this startup.
+ *
+ *  There are two schemes too. One can clear multiple BSS sections. Another
+ *  can only clear one section. The former is more size expensive than the
+ *  latter.
+ *
+ *  Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ *  Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/*  Multiple sections scheme.
+ *
+ *  Between symbol address __copy_table_start__ and __copy_table_end__,
+ *  there are array of tuples specifying:
+ *    offset 0: Start of a BSS section
+ *    offset 4: Size of this BSS section. Must be multiply of 4
+ */
+  pTable = &__zero_table_start__;
+
+  for (; pTable < &__zero_table_end__; pTable = pTable + 2) {
+		pDest = (uint32_t*)*(pTable + 0);
+		for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
+      *pDest++ = 0;
+		}
+	}
+#elif defined (__STARTUP_CLEAR_BSS)
+/*  Single BSS section scheme.
+ *
+ *  The BSS section is specified by following symbols
+ *    __bss_start__: start of the BSS section.
+ *    __bss_end__: end of the BSS section.
+ *
+ *  Both addresses must be aligned to 4 bytes boundary.
+ */
+  pDest = &__bss_start__;
+
+  for ( ; pDest < &__bss_end__ ; ) {
+    *pDest++ = 0UL;
+  }
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+#ifndef __NO_SYSTEM_INIT
+	SystemInit();
+#endif
+
+#ifndef __START
+#define __START _start
+#endif
+	__START();
+
+}
+
+
+/*----------------------------------------------------------------------------
+  Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+
+	while(1);
+}

CMSIS/CoreValidation/Tests/Cortex-M3/GCC/RTE/Device/ARMCM3/system_ARMCM3.c

@@ -0,0 +1,68 @@
+/**************************************************************************//**
+ * @file     system_ARMCM3.c
+ * @brief    CMSIS Device System Source File for
+ *           ARMCM3 Device Series
+ * @version  V5.00
+ * @date     07. September 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ARMCM3.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define  XTAL            ( 5000000UL)      /* Oscillator frequency */
+
+#define  SYSTEM_CLOCK    (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+  SystemCoreClock = SYSTEM_CLOCK;
+}

CMSIS/CoreValidation/Tests/Cortex-M3/GCC/RTE/_FVP/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'CMSIS_CV' 
+ * Target:  'FVP' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "ARMCM3.h"
+
+
+#endif /* RTE_COMPONENTS_H */