Merge branch 'develop' of https://github.com/ARM-software/CMSIS_5 into develop

ARM.CMSIS.pdsc

@@ -13,6 +13,8 @@
       CMSIS-Core(A): 1.0.1 (see revision history for details)
         - Added compiler_iccarm.h.
         - Added additional access functions for physical timer.
+      Devices:
+       - Added device ARMCM0plus_MPU for Cortex-M0+ with MPU.
     </release>
     <release version="5.1.2-dev2">
       CMSIS-Core(M): 5.0.3 (see revision history for details)
@@ -250,6 +252,11 @@ The Cortex-M0+ processor is an entry-level 32-bit ARM Cortex processor designed
         <processor Dcore="Cortex-M0+" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
         <compile header="Device/ARM/ARMCM0plus/Include/ARMCM0plus.h" define="ARMCM0P"/>
       </device>
+
+      <device Dname="ARMCM0P_MPU">
+        <processor Dcore="Cortex-M0+" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
+        <compile header="Device/ARM/ARMCM0plus/Include/ARMCM0plus_MPU.h" define="ARMCM0P_MPU"/>
+      </device>
     </family>
 
     <!-- ******************************  Cortex-M3  ****************************** -->
@@ -1668,7 +1675,7 @@ and 8-bit Java bytecodes in Jazelle state.
 
     <condition id="ARMCM0+ CMSIS">
       <description>Generic ARM Cortex-M0+ device startup and depends on CMSIS Core</description>
-      <require Dvendor="ARM:82" Dname="ARMCM0P"/>
+      <require Dvendor="ARM:82" Dname="ARMCM0P*"/>
       <require Cclass="CMSIS" Cgroup="CORE"/>
     </condition>
     <condition id="ARMCM0+ CMSIS GCC">
@@ -2803,6 +2810,7 @@ and 8-bit Java bytecodes in Jazelle state.
       <description>uVision Simulator</description>
       <mountedDevice    deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM0"/>
       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM0P"/>
+      <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM0P_MPU"/>
       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM3"/>
       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM4"/>
       <compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM4_FP"/>

CMSIS/Core/Include/cmsis_iccarm.h

@@ -436,6 +436,10 @@ __packed struct  __iar_u32 { uint32_t v; };
     #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
   #endif
 
+  #ifdef __INTRINSICS_INCLUDED
+  #error intrinsics.h is already included previously!
+  #endif
+  
   #include <intrinsics.h>
 
   #if __IAR_M0_FAMILY

CMSIS/CoreValidation/Include/CV_Typedefs.h

@@ -38,9 +38,7 @@ typedef unsigned int    BOOL;
 
 #define ARRAY_SIZE(arr) (sizeof(arr)/sizeof((arr)[0]))
 
-#if defined( __GNUC__ )
-static const int PATH_DELIMITER = '/';
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined( __GNUC__ ) || defined ( __clang__ )
 static const int PATH_DELIMITER = '/';
 #else
 static const int PATH_DELIMITER = '\\';

CMSIS/CoreValidation/Source/CV_MPU_ARMv7.c

@@ -8,8 +8,6 @@
 #include "CV_Framework.h"
 #include "cmsis_cv.h"
 
-#if defined(__MPU_PRESENT) && (__MPU_PRESENT != 0)
-
 /*-----------------------------------------------------------------------------
  *      Test implementation
  *----------------------------------------------------------------------------*/
@@ -115,4 +113,3 @@ void TC_MPU_Load(void)
   #undef ASSERT_MPU_REGION
 }
 
-#endif

CMSIS/CoreValidation/Source/cmsis_cv.c

@@ -99,11 +99,9 @@ static TEST_CASE TC_LIST[] = {
   #endif
 #endif
 #ifdef RTE_CV_MPUFUNC
-#if defined(__MPU_PRESENT) && __MPU_PRESENT
   TCD ( TC_MPU_SetClear,       TC_MPU_SETCLEAR_EN       ),
   TCD ( TC_MPU_Load,           TC_MPU_LOAD_EN           ),
 #endif
-#endif
 #ifdef RTE_CV_GENTIMER
   TCD ( TC_GenTimer_CNTFRQ,     TC_GENTIMER_CNTFRQ    ),
   TCD ( TC_GenTimer_CNTP_TVAL,  TC_GENTIMER_CNTP_TVAL ),

CMSIS/CoreValidation/Tests/ARMCM0plus_config.txt

@@ -1,6 +1,30 @@
 # Parameters:
 # instance.parameter=value       #(type, mode) default = 'def value' : description : [min..max]
 #----------------------------------------------------------------------------------------------
+armcortexm0plusct.semihosting-enable=1                # (bool  , init-time) default = '1'      : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
+armcortexm0plusct.semihosting-Thumb_SVC=0xAB          # (int   , init-time) default = '0xAB'   : T32 SVC number for semihosting : [0x0..0xFF]
+armcortexm0plusct.semihosting-cmd_line=""             # (string, init-time) default = ''       : Command line available to semihosting SVC calls
+armcortexm0plusct.semihosting-heap_base=0x0           # (int   , init-time) default = '0x0'    : Virtual address of heap base : [0x0..0xFFFFFFFF]
+armcortexm0plusct.semihosting-heap_limit=0x0          # (int   , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]
+armcortexm0plusct.semihosting-stack_base=0x0          # (int   , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]
+armcortexm0plusct.semihosting-stack_limit=0x0         # (int   , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]
+armcortexm0plusct.semihosting-cwd=""                  # (string, init-time) default = ''       : Base directory for semihosting file access.
+armcortexm0plusct.NUM_MPU_REGION=0x8                  # (int   , init-time) default = '0x0'    : Number of MPU regions : [0x0..0x8]
+armcortexm0plusct.NUM_IRQ=0x20                        # (int   , init-time) default = '0x20'   : Number of user interrupts : [0x0..0x20]
+armcortexm0plusct.BIGENDINIT=0                        # (bool  , init-time) default = '0'      : Initialize processor to big endian mode
+armcortexm0plusct.min_sync_level=0x0                  # (int   , run-time ) default = '0x0'    : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3]
+armcortexm0plusct.cpi_mul=0x1                         # (int   , run-time ) default = '0x1'    : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
+armcortexm0plusct.cpi_div=0x1                         # (int   , run-time ) default = '0x1'    : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
+armcortexm0plusct.master_id=0x0                       # (int   , init-time) default = '0x0'    : Master ID presented in bus transactions : [0x0..0xFFFFFFFF]
+armcortexm0plusct.VTOR=1                              # (bool  , init-time) default = '1'      : Include Vector Table Offset Register
+armcortexm0plusct.DBG=1                               # (bool  , init-time) default = '1'      : Set whether debug extensions are implemented
+armcortexm0plusct.BKPT=0x4                            # (int   , init-time) default = '0x4'    : Number of breakpoint unit comparators implemented : [0x0..0x4]
+armcortexm0plusct.WPT=0x2                             # (int   , init-time) default = '0x2'    : Number of watchpoint unit comparators implemented : [0x0..0x2]
+armcortexm0plusct.USER=1                              # (bool  , init-time) default = '1'      : Enable support for Unprivileged/Privileged Extension
+armcortexm0plusct.SYST=1                              # (bool  , init-time) default = '1'      : Enable support for SysTick timer functionality
+armcortexm0plusct.WIC=1                               # (bool  , init-time) default = '1'      : Include support for WIC-mode deep sleep
+armcortexm0plusct.IRQDIS=0x0                          # (int   , init-time) default = '0x0'    : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n] : [0x0..0xFFFFFFFF]
+armcortexm0plusct.IOP=0                               # (bool  , init-time) default = '0'      : Send all d-side transactions to the port, io_port_out. Transactions which do not match should be returned to the port, io_port_in
 fvp_mps2.SCC_ID.Variant=0x0                           # (int   , init-time) default = '0x0'    : SCC_ID[23:20], X in the FGPA version 'rXpY' : [0x0..0xF]
 fvp_mps2.SCC_ID.Revision=0x1                          # (int   , init-time) default = '0x1'    : SCC_ID[3:0], Y in the FGPA version 'rXpY' : [0x0..0xF]
 fvp_mps2.iotss_systemcontrol.cpu0wait=0               # (bool  , init-time) default = '0'      : Whether to hold cpu0 in reset at boot
@@ -217,23 +241,4 @@ fvp_mps2.dma3.fifo_size=0x10                          # (int   , init-time) defa
 fvp_mps2.dma3.max_transfer=0x100                      # (int   , init-time) default = '0x100'  : Largest atomic transfer
 fvp_mps2.dma3.generate_clear=0                        # (bool  , init-time) default = '0'      : Generate clear response
 fvp_mps2.dma3.activate_delay=0x0                      # (int   , init-time) default = '0x0'    : request delay
-armcortexm0ct.semihosting-enable=1                    # (bool  , init-time) default = '1'      : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
-armcortexm0ct.semihosting-Thumb_SVC=0xAB              # (int   , init-time) default = '0xAB'   : T32 SVC number for semihosting : [0x0..0xFF]
-armcortexm0ct.semihosting-cmd_line=""                 # (string, init-time) default = ''       : Command line available to semihosting SVC calls
-armcortexm0ct.semihosting-heap_base=0x0               # (int   , init-time) default = '0x0'    : Virtual address of heap base : [0x0..0xFFFFFFFF]
-armcortexm0ct.semihosting-heap_limit=0x0              # (int   , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]
-armcortexm0ct.semihosting-stack_base=0x0              # (int   , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]
-armcortexm0ct.semihosting-stack_limit=0x0             # (int   , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]
-armcortexm0ct.semihosting-cwd=""                      # (string, init-time) default = ''       : Base directory for semihosting file access.
-armcortexm0ct.NUM_IRQ=0x20                            # (int   , init-time) default = '0x20'   : Number of user interrupts : [0x1..0x20]
-armcortexm0ct.BIGENDINIT=0                            # (bool  , init-time) default = '0'      : Initialize processor to big endian mode
-armcortexm0ct.min_sync_level=0x0                      # (int   , run-time ) default = '0x0'    : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3]
-armcortexm0ct.cpi_mul=0x1                             # (int   , run-time ) default = '0x1'    : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
-armcortexm0ct.cpi_div=0x1                             # (int   , run-time ) default = '0x1'    : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
-armcortexm0ct.master_id=0x0                           # (int   , init-time) default = '0x0'    : Master ID presented in bus transactions : [0x0..0xFFFFFFFF]
-armcortexm0ct.DBG=1                                   # (bool  , init-time) default = '1'      : Set whether debug extensions are implemented
-armcortexm0ct.BKPT=0x4                                # (int   , init-time) default = '0x4'    : Number of breakpoint unit comparators implemented : [0x0..0x4]
-armcortexm0ct.WPT=0x2                                 # (int   , init-time) default = '0x2'    : Number of watchpoint unit comparators implemented : [0x0..0x2]
-armcortexm0ct.SYST=1                                  # (bool  , init-time) default = '1'      : Enable support for SysTick timer functionality
-armcortexm0ct.WIC=1                                   # (bool  , init-time) default = '1'      : Include support for WIC-mode deep sleep
 #----------------------------------------------------------------------------------------------

CMSIS/CoreValidation/Tests/Cortex-M0plus/AC5/CMSIS_CV.uvprojx

@@ -14,16 +14,16 @@
       <pCCUsed>5060528::V5.06 update 5 (build 528)::ARMCC</pCCUsed>
       <TargetOption>
         <TargetCommonOption>
-          <Device>ARMCM0P</Device>
+          <Device>ARMCM0P_MPU</Device>
           <Vendor>ARM</Vendor>
-          <PackID>ARM.CMSIS.5.1.2-dev1</PackID>
+          <PackID>ARM.CMSIS.5.1.2-dev3</PackID>
           <PackURL>http://www.keil.com/pack/</PackURL>
           <Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ESEL ELITTLE</Cpu>
           <FlashUtilSpec></FlashUtilSpec>
           <StartupFile></StartupFile>
           <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
           <DeviceId>0</DeviceId>
-          <RegisterFile>$$Device:ARMCM0P$Device\ARM\ARMCM0plus\Include\ARMCM0plus.h</RegisterFile>
+          <RegisterFile>$$Device:ARMCM0P_MPU$Device\ARM\ARMCM0plus\Include\ARMCM0plus_MPU.h</RegisterFile>
           <MemoryEnv></MemoryEnv>
           <Cmp></Cmp>
           <Asm></Asm>
@@ -33,7 +33,7 @@
           <SLE66CMisc></SLE66CMisc>
           <SLE66AMisc></SLE66AMisc>
           <SLE66LinkerMisc></SLE66LinkerMisc>
-          <SFDFile>$$Device:ARMCM0P$Device\ARM\SVD\ARMCM0P.svd</SFDFile>
+          <SFDFile>$$Device:ARMCM0P_MPU$Device\ARM\SVD\ARMCM0P.svd</SFDFile>
           <bCustSvd>0</bCustSvd>
           <UseEnv>0</UseEnv>
           <BinPath></BinPath>
@@ -110,11 +110,11 @@
         </CommonProperty>
         <DllOption>
           <SimDllName>SARMCM3.DLL</SimDllName>
-          <SimDllArguments>  </SimDllArguments>
+          <SimDllArguments> -MPU </SimDllArguments>
           <SimDlgDll>DARMCM1.DLL</SimDlgDll>
           <SimDlgDllArguments>-pCM0+</SimDlgDllArguments>
           <TargetDllName>SARMCM3.DLL</TargetDllName>
-          <TargetDllArguments> </TargetDllArguments>
+          <TargetDllArguments>-MPU </TargetDllArguments>
           <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
           <TargetDlgDllArguments>-pCM0+</TargetDlgDllArguments>
         </DllOption>
@@ -450,17 +450,29 @@
     </components>
     <files>
       <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM0plus\Source\ARM\startup_ARMCM0plus.s" version="1.0.0">
-        <instance index="0">RTE\Device\ARMCM0P\startup_ARMCM0plus.s</instance>
+        <instance index="0" removed="1">RTE\Device\ARMCM0P\startup_ARMCM0plus.s</instance>
         <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0+ CMSIS"/>
-        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev3"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM0plus\Source\system_ARMCM0plus.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM0P\system_ARMCM0plus.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0+ CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev3"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM0plus\Source\ARM\startup_ARMCM0plus.s" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM0P_MPU\startup_ARMCM0plus.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0+ CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev3"/>
         <targetInfos>
           <targetInfo name="FVP"/>
         </targetInfos>
       </file>
       <file attr="config" category="sourceC" name="Device\ARM\ARMCM0plus\Source\system_ARMCM0plus.c" version="1.0.0">
-        <instance index="0">RTE\Device\ARMCM0P\system_ARMCM0plus.c</instance>
+        <instance index="0">RTE\Device\ARMCM0P_MPU\system_ARMCM0plus.c</instance>
         <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0+ CMSIS"/>
-        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev3"/>
         <targetInfos>
           <targetInfo name="FVP"/>
         </targetInfos>

CMSIS/CoreValidation/Tests/Cortex-M0plus/AC5/RTE/_FVP/RTE_Components.h

@@ -14,7 +14,7 @@
 /*
  * Define the Device Header File: 
  */
-#define CMSIS_device_header "ARMCM0plus.h"
+#define CMSIS_device_header "ARMCM0plus_MPU.h"
 
 
 #endif /* RTE_COMPONENTS_H */

CMSIS/CoreValidation/Tests/Cortex-M0plus/AC6/CMSIS_CV.uvprojx

@@ -14,16 +14,16 @@
       <pCCUsed>6070000::V6.7::.\ARMCLANG</pCCUsed>
       <TargetOption>
         <TargetCommonOption>
-          <Device>ARMCM0P</Device>
+          <Device>ARMCM0P_MPU</Device>
           <Vendor>ARM</Vendor>
-          <PackID>ARM.CMSIS.5.1.2-dev1</PackID>
+          <PackID>ARM.CMSIS.5.1.2-dev3</PackID>
           <PackURL>http://www.keil.com/pack/</PackURL>
           <Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ESEL ELITTLE</Cpu>
           <FlashUtilSpec></FlashUtilSpec>
           <StartupFile></StartupFile>
           <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
           <DeviceId>0</DeviceId>
-          <RegisterFile>$$Device:ARMCM0P$Device\ARM\ARMCM0plus\Include\ARMCM0plus.h</RegisterFile>
+          <RegisterFile>$$Device:ARMCM0P_MPU$Device\ARM\ARMCM0plus\Include\ARMCM0plus_MPU.h</RegisterFile>
           <MemoryEnv></MemoryEnv>
           <Cmp></Cmp>
           <Asm></Asm>
@@ -33,7 +33,7 @@
           <SLE66CMisc></SLE66CMisc>
           <SLE66AMisc></SLE66AMisc>
           <SLE66LinkerMisc></SLE66LinkerMisc>
-          <SFDFile>$$Device:ARMCM0P$Device\ARM\SVD\ARMCM0P.svd</SFDFile>
+          <SFDFile>$$Device:ARMCM0P_MPU$Device\ARM\SVD\ARMCM0P.svd</SFDFile>
           <bCustSvd>0</bCustSvd>
           <UseEnv>0</UseEnv>
           <BinPath></BinPath>
@@ -110,11 +110,11 @@
         </CommonProperty>
         <DllOption>
           <SimDllName>SARMCM3.DLL</SimDllName>
-          <SimDllArguments>  </SimDllArguments>
+          <SimDllArguments> -MPU </SimDllArguments>
           <SimDlgDll>DARMCM1.DLL</SimDlgDll>
           <SimDlgDllArguments>-pCM0+</SimDlgDllArguments>
           <TargetDllName>SARMCM3.DLL</TargetDllName>
-          <TargetDllArguments> </TargetDllArguments>
+          <TargetDllArguments>-MPU </TargetDllArguments>
           <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
           <TargetDlgDllArguments>-pCM0+</TargetDlgDllArguments>
         </DllOption>
@@ -430,6 +430,430 @@
         </Group>
       </Groups>
     </Target>
+    <Target>
+      <TargetName>STM32L053</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pArmCC>6070000::V6.7::.\ARMCLANG</pArmCC>
+      <pCCUsed>6070000::V6.7::.\ARMCLANG</pCCUsed>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>STM32L053R8Tx</Device>
+          <Vendor>STMicroelectronics</Vendor>
+          <PackID>Keil.STM32L0xx_DFP.1.7.0-dev0</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IRAM(0x20000000,0x00002000) IROM(0x08000000,0x00010000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32L0xx_64 -FS08000000 -FL010000 -FP0($$Device:STM32L053R8Tx$Flash\STM32L0xx_64.FLM))</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:STM32L053R8Tx$Device\Include\stm32l0xx.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:STM32L053R8Tx$SVD\STM32L053x.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\Objects\</OutputDirectory>
+          <OutputName>CMSIS_CV</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\Listings\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments> -REMAP </SimDllArguments>
+          <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM0+</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> -MPU</TargetDllArguments>
+          <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM0+</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>1</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M0+"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x2000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x10000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x2000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <useXO>0</useXO>
+            <v6Lang>3</v6Lang>
+            <v6LangP>3</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls>-Wno-covered-switch-default</MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>.\,..\..\..\Include</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <uClangAs>0</uClangAs>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>.\,..\..\..\Include</IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange></TextAddressRange>
+            <DataAddressRange></DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc>--entry=Reset_Handler</Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Test</GroupName>
+          <Files>
+            <File>
+              <FileName>cmsis_cv.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\cmsis_cv.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_CoreFunc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_CoreFunc.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_CoreInstr.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_CoreInstr.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Framework.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_Framework.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_MPU_ARMv7.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_MPU_ARMv7.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Report.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\Source\CV_Report.c</FilePath>
+            </File>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\main.c</FilePath>
+            </File>
+            <File>
+              <FileName>CV_Config.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\CV_Config.h</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::CMSIS</GroupName>
+        </Group>
+        <Group>
+          <GroupName>::Device</GroupName>
+        </Group>
+      </Groups>
+    </Target>
   </Targets>
 
   <RTE>
@@ -439,6 +863,7 @@
         <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1"/>
         <targetInfos>
           <targetInfo name="FVP"/>
+          <targetInfo name="STM32L053"/>
         </targetInfos>
       </component>
       <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0+ CMSIS">
@@ -447,20 +872,38 @@
           <targetInfo name="FVP"/>
         </targetInfos>
       </component>
+      <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.6.0" condition="STM32L053 CMSIS">
+        <package name="STM32L0xx_DFP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="Keil" version="1.7.0-dev0"/>
+        <targetInfos>
+          <targetInfo name="STM32L053"/>
+        </targetInfos>
+      </component>
     </components>
     <files>
       <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM0plus\Source\ARM\startup_ARMCM0plus.s" version="1.0.0">
-        <instance index="0">RTE\Device\ARMCM0P\startup_ARMCM0plus.s</instance>
+        <instance index="0" removed="1">RTE\Device\ARMCM0P\startup_ARMCM0plus.s</instance>
         <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0+ CMSIS"/>
-        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev3"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM0plus\Source\system_ARMCM0plus.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM0P\system_ARMCM0plus.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0+ CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev3"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM0plus\Source\ARM\startup_ARMCM0plus.s" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM0P_MPU\startup_ARMCM0plus.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0+ CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev3"/>
         <targetInfos>
           <targetInfo name="FVP"/>
         </targetInfos>
       </file>
       <file attr="config" category="sourceC" name="Device\ARM\ARMCM0plus\Source\system_ARMCM0plus.c" version="1.0.0">
-        <instance index="0">RTE\Device\ARMCM0P\system_ARMCM0plus.c</instance>
+        <instance index="0">RTE\Device\ARMCM0P_MPU\system_ARMCM0plus.c</instance>
         <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0+ CMSIS"/>
-        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev3"/>
         <targetInfos>
           <targetInfo name="FVP"/>
         </targetInfos>
@@ -501,6 +944,22 @@
         <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
         <targetInfos/>
       </file>
+      <file attr="config" category="source" condition="Compiler ARMCC" name="Device\Source\ARM\startup_stm32l053xx.s" version="1.6.0">
+        <instance index="0">RTE\Device\STM32L053R8Tx\startup_stm32l053xx.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.6.0" condition="STM32L053 CMSIS"/>
+        <package name="STM32L0xx_DFP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="Keil" version="1.7.0-dev0"/>
+        <targetInfos>
+          <targetInfo name="STM32L053"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="source" name="Device\Source\system_stm32l0xx.c" version="1.6.0">
+        <instance index="0">RTE\Device\STM32L053R8Tx\system_stm32l0xx.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.6.0" condition="STM32L053 CMSIS"/>
+        <package name="STM32L0xx_DFP" schemaVersion="1.2" url="http://www.keil.com/pack/" vendor="Keil" version="1.7.0-dev0"/>
+        <targetInfos>
+          <targetInfo name="STM32L053"/>
+        </targetInfos>
+      </file>
     </files>
   </RTE>
 

CMSIS/CoreValidation/Tests/Cortex-M0plus/AC6/CV_Config.h

@@ -14,6 +14,11 @@
 #define RTE_CV_COREFUNC  1
 #define RTE_CV_MPUFUNC   1
 
+#if defined(STM32L053xx)
+#define WDT_IRQn WWDG_IRQn
+#define WDT_IRQHandler WWDG_IRQHandler
+#define DISABLE_SEMIHOSTING
+#endif 
 
 //-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
 

CMSIS/CoreValidation/Tests/Cortex-M0plus/AC6/RTE/Device/STM32L053R8Tx/startup_stm32l053xx.s

@@ -0,0 +1,261 @@
+;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;* File Name          : startup_stm32l053xx.s
+;* Author             : MCD Application Team
+;* Version            : V1.6.0
+;* Date               : 15-April-2016
+;* Description        : STM32l053xx Devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M0+ processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;*******************************************************************************
+;* 
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;*
+;*******************************************************************************
+;
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                ; Window Watchdog
+                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
+                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
+                DCD     FLASH_IRQHandler               ; FLASH
+                DCD     RCC_CRS_IRQHandler             ; RCC and CRS
+                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
+                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
+                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
+                DCD     TSC_IRQHandler                 ; TSC
+                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
+                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
+                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
+                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
+                DCD     LPTIM1_IRQHandler              ; LPTIM1
+                DCD     0                              ; Reserved
+                DCD     TIM2_IRQHandler                ; TIM2
+                DCD     0                              ; Reserved
+                DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
+                DCD     0                              ; Reserved
+                DCD     0                              ; Reserved
+                DCD     TIM21_IRQHandler               ; TIM21
+                DCD     0                              ; Reserved
+                DCD     TIM22_IRQHandler               ; TIM22
+                DCD     I2C1_IRQHandler                ; I2C1
+                DCD     I2C2_IRQHandler                ; I2C2
+                DCD     SPI1_IRQHandler                ; SPI1
+                DCD     SPI2_IRQHandler                ; SPI2
+                DCD     USART1_IRQHandler              ; USART1
+                DCD     USART2_IRQHandler              ; USART2
+                DCD     RNG_LPUART1_IRQHandler         ; RNG and LPUART1
+                DCD     LCD_IRQHandler                 ; LCD
+                DCD     USB_IRQHandler                 ; USB
+                
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler routine
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  __main
+        IMPORT  SystemInit  
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                [WEAK]
+                EXPORT  PVD_IRQHandler                 [WEAK]
+                EXPORT  RTC_IRQHandler                 [WEAK]
+                EXPORT  FLASH_IRQHandler               [WEAK]
+                EXPORT  RCC_CRS_IRQHandler             [WEAK]
+                EXPORT  EXTI0_1_IRQHandler             [WEAK]
+                EXPORT  EXTI2_3_IRQHandler             [WEAK]
+                EXPORT  EXTI4_15_IRQHandler            [WEAK]
+                EXPORT  TSC_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
+                EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
+                EXPORT  DMA1_Channel4_5_6_7_IRQHandler [WEAK]
+                EXPORT  ADC1_COMP_IRQHandler           [WEAK]
+                EXPORT  LPTIM1_IRQHandler              [WEAK]
+                EXPORT  TIM2_IRQHandler                [WEAK]
+                EXPORT  TIM6_DAC_IRQHandler            [WEAK]
+                EXPORT  TIM21_IRQHandler               [WEAK]
+                EXPORT  TIM22_IRQHandler               [WEAK]
+                EXPORT  I2C1_IRQHandler                [WEAK]
+                EXPORT  I2C2_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                [WEAK]
+                EXPORT  SPI2_IRQHandler                [WEAK]
+                EXPORT  USART1_IRQHandler              [WEAK]
+                EXPORT  USART2_IRQHandler              [WEAK]
+                EXPORT  RNG_LPUART1_IRQHandler         [WEAK]
+                EXPORT  LCD_IRQHandler                 [WEAK]
+                EXPORT  USB_IRQHandler                 [WEAK]
+
+
+WWDG_IRQHandler
+PVD_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_CRS_IRQHandler
+EXTI0_1_IRQHandler
+EXTI2_3_IRQHandler
+EXTI4_15_IRQHandler
+TSC_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_3_IRQHandler
+DMA1_Channel4_5_6_7_IRQHandler
+ADC1_COMP_IRQHandler 
+LPTIM1_IRQHandler
+TIM2_IRQHandler
+TIM6_DAC_IRQHandler
+TIM21_IRQHandler
+TIM22_IRQHandler
+I2C1_IRQHandler
+I2C2_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+RNG_LPUART1_IRQHandler
+LCD_IRQHandler
+USB_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

CMSIS/CoreValidation/Tests/Cortex-M0plus/AC6/RTE/Device/STM32L053R8Tx/system_stm32l0xx.c

@@ -0,0 +1,339 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32l0xx.c
+  * @author  MCD Application Team
+  * @version V1.6.0
+  * @date    15-April-2016
+  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File.
+  *
+  *   This file provides two functions and one global variable to be called from 
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32l0xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * modified by ARM 06.06.2015
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l0xx_system
+  * @{
+  */  
+  
+/** @addtogroup STM32L0xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32l0xx.h"
+
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE    ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)2000000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+   
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L0xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L0xx_System_Private_Defines
+  * @{
+  */
+/************************* Miscellaneous Configuration ************************/
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00U /*!< Vector Table base offset field. 
+                                   This value must be a multiple of 0x100. */
+/******************************************************************************/
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L0xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L0xx_System_Private_Variables
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock = 2000000U;
+  const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
+  const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
+  const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L0xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SystemCoreClockConfigure(void);
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L0xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{    
+/*!< Set MSION bit */
+  RCC->CR |= (uint32_t)0x00000100U;
+
+  /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
+  RCC->CFGR &= (uint32_t) 0x88FF400CU;
+ 
+  /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFF6U;
+  
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+  
+  /*!< Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFFU;
+
+  /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
+  RCC->CFGR &= (uint32_t)0xFF02FFFFU;
+
+  /*!< Disable all interrupts */
+  RCC->CIER = 0x00000000U;
+  
+  /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+  
+  SystemCoreClockConfigure();
+
+}
+
+/**
+  * @brief  Update SystemCoreClock according to Clock Register Values
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI 
+  *             value as defined by the MSI range.
+  *                                   
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32l0xx_hal.h file (default value
+  *             16 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32l0xx_hal.h file (default value
+  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00U:  /* MSI used as system clock */
+      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U;
+      SystemCoreClock = (32768U * (1U << (msirange + 1U)));
+      break;
+    case 0x04U:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+
+      if (RCC->CR & RCC_CR_HSIDIVF) {    /* added by ARM */
+          SystemCoreClock >>= 2U;        /* HSI is divided by 4 */
+      }
+      break;
+    case 0x08U:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x0CU:  /* PLL used as system clock */
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
+      plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
+      pllmul = PLLMulTable[(pllmul >> 18U)];
+      plldiv = (plldiv >> 22U) + 1U;
+      
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+
+      if (pllsource == 0x00U)
+      {
+        /* HSI oscillator clock selected as PLL clock entry */
+        SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
+
+        if (RCC->CR & RCC_CR_HSIDIVF) {    /* added by ARM */
+            SystemCoreClock >>= 2U;        /* HSI is divided by 4 */
+        }
+      }
+      else
+      {
+        /* HSE selected as PLL clock entry */
+        SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
+      }
+      break;
+    default: /* MSI used as system clock */
+      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U;
+      SystemCoreClock = (32768U * (1U << (msirange + 1U)));
+      break;
+  }
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;
+}
+
+/*----------------------------------------------------------------------------
+ * SystemCoreClockConfigure: configure SystemCoreClock using HSI
+                             (HSE is not populated on Discovery board)
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockConfigure(void) {
+
+  RCC->CR |= ((uint32_t)RCC_CR_HSION);                     // Enable HSI
+  while ((RCC->CR & RCC_CR_HSIRDY) == 0);                  // Wait for HSI Ready
+
+  RCC->CFGR = RCC_CFGR_SW_HSI;                             // HSI is system clock
+  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI);  // Wait for HSI used as system clock
+
+  // PLL configuration: PLLCLK = (HSI * 6)/3 = 32 MHz
+  RCC->CFGR &= ~(RCC_CFGR_PLLSRC |
+                 RCC_CFGR_PLLMUL |
+                 RCC_CFGR_PLLDIV  );
+  RCC->CFGR |=  (RCC_CFGR_PLLSRC_HSI |
+                 RCC_CFGR_PLLMUL4    |
+                 RCC_CFGR_PLLDIV2     );
+
+  FLASH->ACR |= FLASH_ACR_PRFTEN;                          // Enable Prefetch Buffer
+  FLASH->ACR |= FLASH_ACR_LATENCY;                         // Flash 1 wait state
+
+  RCC->APB1ENR |= RCC_APB1ENR_PWREN;                       // Enable the PWR APB1 Clock
+  PWR->CR = PWR_CR_VOS_0;                                  // Select the Voltage Range 1 (1.8V)
+  while((PWR->CSR & PWR_CSR_VOSF) != 0);                   // Wait for Voltage Regulator Ready
+
+  RCC->CFGR |= RCC_CFGR_HPRE_DIV1;                         // HCLK = SYSCLK
+  RCC->CFGR |= RCC_CFGR_PPRE1_DIV1;                        // PCLK1 = HCLK
+  RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;                        // PCLK2 = HCLK
+
+  RCC->CR &= ~RCC_CR_PLLON;                                // Disable PLL
+
+  RCC->CR |= RCC_CR_PLLON;                                 // Enable PLL
+  while((RCC->CR & RCC_CR_PLLRDY) == 0) __NOP();           // Wait till PLL is ready
+
+  RCC->CFGR &= ~RCC_CFGR_SW;                               // Select PLL as system clock source
+  RCC->CFGR |=  RCC_CFGR_SW_PLL;
+  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL);  // Wait till PLL is system clock src
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

CMSIS/CoreValidation/Tests/Cortex-M0plus/AC6/RTE/_FVP/RTE_Components.h

@@ -14,7 +14,7 @@
 /*
  * Define the Device Header File: 
  */
-#define CMSIS_device_header "ARMCM0plus.h"
+#define CMSIS_device_header "ARMCM0plus_MPU.h"
 
 
 #endif /* RTE_COMPONENTS_H */

CMSIS/CoreValidation/Tests/Cortex-M0plus/AC6/RTE/_STM32L053/RTE_Components.h

@@ -0,0 +1,20 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'CMSIS_CV' 
+ * Target:  'STM32L053' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "stm32l0xx.h"
+
+
+#endif /* RTE_COMPONENTS_H */

CMSIS/CoreValidation/Tests/Cortex-M0plus/GCC/CMSIS_CV.uvprojx

@@ -14,16 +14,16 @@
       <pCCUsed>6070000::V6.7::.\ARMCLANG</pCCUsed>
       <TargetOption>
         <TargetCommonOption>
-          <Device>ARMCM0P</Device>
+          <Device>ARMCM0P_MPU</Device>
           <Vendor>ARM</Vendor>
-          <PackID>ARM.CMSIS.5.1.2-dev1</PackID>
+          <PackID>ARM.CMSIS.5.1.2-dev3</PackID>
           <PackURL>http://www.keil.com/pack/</PackURL>
           <Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ESEL ELITTLE</Cpu>
           <FlashUtilSpec></FlashUtilSpec>
           <StartupFile></StartupFile>
           <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
           <DeviceId>0</DeviceId>
-          <RegisterFile>$$Device:ARMCM0P$Device\ARM\ARMCM0plus\Include\ARMCM0plus.h</RegisterFile>
+          <RegisterFile>$$Device:ARMCM0P_MPU$Device\ARM\ARMCM0plus\Include\ARMCM0plus_MPU.h</RegisterFile>
           <MemoryEnv></MemoryEnv>
           <Cmp></Cmp>
           <Asm></Asm>
@@ -33,7 +33,7 @@
           <SLE66CMisc></SLE66CMisc>
           <SLE66AMisc></SLE66AMisc>
           <SLE66LinkerMisc></SLE66LinkerMisc>
-          <SFDFile>$$Device:ARMCM0P$Device\ARM\SVD\ARMCM0P.svd</SFDFile>
+          <SFDFile>$$Device:ARMCM0P_MPU$Device\ARM\SVD\ARMCM0P.svd</SFDFile>
           <bCustSvd>0</bCustSvd>
           <UseEnv>0</UseEnv>
           <BinPath></BinPath>
@@ -110,11 +110,11 @@
         </CommonProperty>
         <DllOption>
           <SimDllName>SARMCM3.DLL</SimDllName>
-          <SimDllArguments>  </SimDllArguments>
+          <SimDllArguments> -MPU </SimDllArguments>
           <SimDlgDll>DARMCM1.DLL</SimDlgDll>
           <SimDlgDllArguments>-pCM0+</SimDlgDllArguments>
           <TargetDllName>SARMCM3.DLL</TargetDllName>
-          <TargetDllArguments> </TargetDllArguments>
+          <TargetDllArguments>-MPU </TargetDllArguments>
           <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
           <TargetDlgDllArguments>-pCM0+</TargetDlgDllArguments>
         </DllOption>
@@ -267,7 +267,7 @@
             <IncludeLibs></IncludeLibs>
             <IncludeDir></IncludeDir>
             <Misc>-mfloat-abi=soft --specs=rdimon.specs</Misc>
-            <ScatterFile>.\RTE\Device\ARMCM0P\gcc_arm.ld</ScatterFile>
+            <ScatterFile>.\RTE\Device\ARMCM0P_MPU\gcc_arm.ld</ScatterFile>
           </LDarm>
         </TargetArm>
       </TargetOption>
@@ -345,25 +345,43 @@
     </components>
     <files>
       <file attr="config" category="linkerScript" condition="GCC" name="Device\ARM\ARMCM0plus\Source\GCC\gcc_arm.ld" version="1.0.0">
-        <instance index="0">RTE\Device\ARMCM0P\gcc_arm.ld</instance>
+        <instance index="0" removed="1">RTE\Device\ARMCM0P\gcc_arm.ld</instance>
         <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0+ CMSIS GCC"/>
-        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev3"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" condition="GCC" name="Device\ARM\ARMCM0plus\Source\GCC\startup_ARMCM0plus.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM0P\startup_ARMCM0plus.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0+ CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev3"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM0plus\Source\system_ARMCM0plus.c" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\ARMCM0P\system_ARMCM0plus.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0+ CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev3"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="linkerScript" condition="GCC" name="Device\ARM\ARMCM0plus\Source\GCC\gcc_arm.ld" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM0P_MPU\gcc_arm.ld</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0+ CMSIS GCC"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev3"/>
         <targetInfos>
           <targetInfo name="FVP"/>
         </targetInfos>
       </file>
       <file attr="config" category="sourceC" condition="GCC" name="Device\ARM\ARMCM0plus\Source\GCC\startup_ARMCM0plus.c" version="1.0.0">
-        <instance index="0">RTE\Device\ARMCM0P\startup_ARMCM0plus.c</instance>
+        <instance index="0">RTE\Device\ARMCM0P_MPU\startup_ARMCM0plus.c</instance>
         <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0+ CMSIS GCC"/>
-        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev3"/>
         <targetInfos>
           <targetInfo name="FVP"/>
         </targetInfos>
       </file>
       <file attr="config" category="sourceC" name="Device\ARM\ARMCM0plus\Source\system_ARMCM0plus.c" version="1.0.0">
-        <instance index="0">RTE\Device\ARMCM0P\system_ARMCM0plus.c</instance>
+        <instance index="0">RTE\Device\ARMCM0P_MPU\system_ARMCM0plus.c</instance>
         <component Cclass="Device" Cgroup="Startup" Cvariant="C Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0+ CMSIS GCC"/>
-        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev3"/>
         <targetInfos>
           <targetInfo name="FVP"/>
         </targetInfos>

CMSIS/CoreValidation/Tests/Cortex-M0plus/GCC/RTE/_FVP/RTE_Components.h

@@ -14,7 +14,7 @@
 /*
  * Define the Device Header File: 
  */
-#define CMSIS_device_header "ARMCM0plus.h"
+#define CMSIS_device_header "ARMCM0plus_MPU.h"
 
 
 #endif /* RTE_COMPONENTS_H */

CMSIS/CoreValidation/Tests/Cortex-M0plus/IAR/CMSIS_CV.ewp

@@ -1,1102 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<project>
-    <fileVersion>3</fileVersion>
-    <configuration>
-        <name>FVP</name>
-        <toolchain>
-            <name>ARM</name>
-        </toolchain>
-        <debug>1</debug>
-        <settings>
-            <name>General</name>
-            <archiveVersion>3</archiveVersion>
-            <data>
-                <version>29</version>
-                <wantNonLocal>1</wantNonLocal>
-                <debug>1</debug>
-                <option>
-                    <name>ExePath</name>
-                    <state>FVP\Exe</state>
-                </option>
-                <option>
-                    <name>ObjPath</name>
-                    <state>FVP\Obj</state>
-                </option>
-                <option>
-                    <name>ListPath</name>
-                    <state>FVP\List</state>
-                </option>
-                <option>
-                    <name>GEndianMode</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>Input description</name>
-                    <state>Automatic choice of formatter, without multibyte support.</state>
-                </option>
-                <option>
-                    <name>Output description</name>
-                    <state>Automatic choice of formatter, without multibyte support.</state>
-                </option>
-                <option>
-                    <name>GOutputBinary</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>OGCoreOrChip</name>
-                    <state>2</state>
-                </option>
-                <option>
-                    <name>GRuntimeLibSelect</name>
-                    <version>0</version>
-                    <state>2</state>
-                </option>
-                <option>
-                    <name>GRuntimeLibSelectSlave</name>
-                    <version>0</version>
-                    <state>2</state>
-                </option>
-                <option>
-                    <name>RTDescription</name>
-                    <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
-                </option>
-                <option>
-                    <name>OGProductVersion</name>
-                    <state>8.11.2.13604</state>
-                </option>
-                <option>
-                    <name>OGLastSavedByProductVersion</name>
-                    <state>8.11.2.13604</state>
-                </option>
-                <option>
-                    <name>GeneralEnableMisra</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>GeneralMisraVerbose</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>OGChipSelectEditMenu</name>
-                    <state>Default	None</state>
-                </option>
-                <option>
-                    <name>GenLowLevelInterface</name>
-                    <state>1</state>
-                </option>
-                <option>
-                    <name>GEndianModeBE</name>
-                    <state>1</state>
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-                <option>
-                    <name>OGBufferedTerminalOutput</name>
-                    <state>0</state>
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-                <option>
-                    <name>GenStdoutInterface</name>
-                    <state>0</state>
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-                    <version>0</version>
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-                </option>
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-                    <name>RTConfigPath2</name>
-                    <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
-                </option>
-                <option>
-                    <name>GBECoreSlave</name>
-                    <version>25</version>
-                    <state>35</state>
-                </option>
-                <option>
-                    <name>OGUseCmsis</name>
-                    <state>1</state>
-                </option>
-                <option>
-                    <name>OGUseCmsisDspLib</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>GRuntimeLibThreads</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>CoreVariant</name>
-                    <version>25</version>
-                    <state>35</state>
-                </option>
-                <option>
-                    <name>GFPUDeviceSlave</name>
-                    <state>Default	None</state>
-                </option>
-                <option>
-                    <name>FPU2</name>
-                    <version>0</version>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>NrRegs</name>
-                    <version>0</version>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>NEON</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>GFPUCoreSlave2</name>
-                    <version>25</version>
-                    <state>35</state>
-                </option>
-                <option>
-                    <name>OGCMSISPackSelectDevice</name>
-                </option>
-                <option>
-                    <name>OgLibHeap</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>OGLibAdditionalLocale</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>OGPrintfVariant</name>
-                    <version>0</version>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>OGPrintfMultibyteSupport</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>OGScanfVariant</name>
-                    <version>0</version>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>OGScanfMultibyteSupport</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>GenLocaleTags</name>
-                    <state></state>
-                </option>
-                <option>
-                    <name>GenLocaleDisplayOnly</name>
-                    <state></state>
-                </option>
-                <option>
-                    <name>DSPExtension</name>
-                    <state>0</state>
-                </option>
-            </data>
-        </settings>
-        <settings>
-            <name>ICCARM</name>
-            <archiveVersion>2</archiveVersion>
-            <data>
-                <version>34</version>
-                <wantNonLocal>1</wantNonLocal>
-                <debug>1</debug>
-                <option>
-                    <name>CCDefines</name>
-                    <state>$CMSIS_PACK_DEVICE_DEFINES$</state>
-                    <state>_RTE_</state>
-                </option>
-                <option>
-                    <name>CCPreprocFile</name>
-                    <state>0</state>
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-                    <name>CCPreprocComments</name>
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-                    <name>CCPreprocLine</name>
-                    <state>1</state>
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-                <option>
-                    <name>CCListCMnemonics</name>
-                    <state>1</state>
-                </option>
-                <option>
-                    <name>CCListCMessages</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>CCListAssFile</name>
-                    <state>1</state>
-                </option>
-                <option>
-                    <name>CCListAssSource</name>
-                    <state>1</state>
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-                <option>
-                    <name>CCEnableRemarks</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>CCDiagSuppress</name>
-                    <state></state>
-                </option>
-                <option>
-                    <name>CCDiagRemark</name>
-                    <state></state>
-                </option>
-                <option>
-                    <name>CCDiagWarning</name>
-                    <state></state>
-                </option>
-                <option>
-                    <name>CCDiagError</name>
-                    <state></state>
-                </option>
-                <option>
-                    <name>CCObjPrefix</name>
-                    <state>1</state>
-                </option>
-                <option>
-                    <name>CCAllowList</name>
-                    <version>1</version>
-                    <state>00000000</state>
-                </option>
-                <option>
-                    <name>CCDebugInfo</name>
-                    <state>1</state>
-                </option>
-                <option>
-                    <name>IEndianMode</name>
-                    <state>1</state>
-                </option>
-                <option>
-                    <name>IProcessor</name>
-                    <state>1</state>
-                </option>
-                <option>
-                    <name>IExtraOptionsCheck</name>
-                    <state>0</state>
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-                <option>
-                    <name>IExtraOptions</name>
-                    <state></state>
-                </option>
-                <option>
-                    <name>CCLangConformance</name>
-                    <state>0</state>
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-                <option>
-                    <name>CCSignedPlainChar</name>
-                    <state>1</state>
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-                <option>
-                    <name>CCRequirePrototypes</name>
-                    <state>0</state>
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-                    <name>CCDiagWarnAreErr</name>
-                    <state>0</state>
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-                    <name>CCCompilerRuntimeInfo</name>
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-                </option>
-                <option>
-                    <name>CCIncludePath2</name>
-                    <state>$CMSIS_PACK_DEVICE_INCLUDES$</state>
-                    <state>$CMSIS_PACK_INCLUDES$</state>
-                    <state>$PROJ_DIR$</state>
-                    <state>$PROJ_DIR$\..\..\..\Include</state>
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-                    <state>0</state>
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-                    <state>.text</state>
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-                    <name>CCOptLevel</name>
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-                    <name>CCOptStrategy</name>
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-                    <state>0</state>
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-                <option>
-                    <name>CCPosIndRwpi</name>
-                    <state>0</state>
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-                    <name>CCPosIndNoDynInit</name>
-                    <state>0</state>
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-                    <name>IccLang</name>
-                    <state>0</state>
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-                    <name>IccCDialect</name>
-                    <state>1</state>
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-                <option>
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-                <option>
-                    <name>IccStaticDestr</name>
-                    <state>1</state>
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-                <option>
-                    <name>IccCppInlineSemantics</name>
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-                <option>
-                    <name>IccCmsis</name>
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-                <option>
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-                <option>
-                    <name>CCOptimizationNoSizeConstraints</name>
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-                    <state>0</state>
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-                    <name>CCOptStrategySlave</name>
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-                    <name>IccRTTI2</name>
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-                    <state>0</state>
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-                <option>
-                    <name>AWarnWhat</name>
-                    <state>0</state>
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-                <option>
-                    <name>AWarnOne</name>
-                    <state></state>
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-                    <name>AWarnRange1</name>
-                    <state></state>
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-                <option>
-                    <name>AWarnRange2</name>
-                    <state></state>
-                </option>
-                <option>
-                    <name>ADebug</name>
-                    <state>1</state>
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-            </data>
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-        <settings>
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-            <archiveVersion>0</archiveVersion>
-            <data>
-                <version>1</version>
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-                    <name>OOCOutputFormat</name>
-                    <version>3</version>
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-            <archiveVersion>3</archiveVersion>
-            <data>
-                <extensions></extensions>
-                <cmdline></cmdline>
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-                <prebuild></prebuild>
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-                <option>
-                    <name>XLinkMisraHandler</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>IlinkInputFileSlave</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>IlinkOutputFile</name>
-                    <state>CMSIS_CV.out</state>
-                </option>
-                <option>
-                    <name>IlinkDebugInfoEnable</name>
-                    <state>1</state>
-                </option>
-                <option>
-                    <name>IlinkKeepSymbols</name>
-                    <state></state>
-                </option>
-                <option>
-                    <name>IlinkRawBinaryFile</name>
-                    <state></state>
-                </option>
-                <option>
-                    <name>IlinkRawBinarySymbol</name>
-                    <state></state>
-                </option>
-                <option>
-                    <name>IlinkRawBinarySegment</name>
-                    <state></state>
-                </option>
-                <option>
-                    <name>IlinkRawBinaryAlign</name>
-                    <state></state>
-                </option>
-                <option>
-                    <name>IlinkDefines</name>
-                    <state></state>
-                </option>
-                <option>
-                    <name>IlinkConfigDefines</name>
-                    <state></state>
-                </option>
-                <option>
-                    <name>IlinkMapFile</name>
-                    <state>1</state>
-                </option>
-                <option>
-                    <name>IlinkLogFile</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>IlinkLogInitialization</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>IlinkLogModule</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>IlinkLogSection</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>IlinkLogVeneer</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>IlinkIcfOverride</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>IlinkIcfFile</name>
-                    <state>${CMSIS_PACK_PATH_ARM#CMSIS#5.1.1-dev1}$\.iar\config\linker\ARMCM0.icf</state>
-                </option>
-                <option>
-                    <name>IlinkIcfFileSlave</name>
-                    <state></state>
-                </option>
-                <option>
-                    <name>IlinkEnableRemarks</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>IlinkSuppressDiags</name>
-                    <state></state>
-                </option>
-                <option>
-                    <name>IlinkTreatAsRem</name>
-                    <state></state>
-                </option>
-                <option>
-                    <name>IlinkTreatAsWarn</name>
-                    <state></state>
-                </option>
-                <option>
-                    <name>IlinkTreatAsErr</name>
-                    <state></state>
-                </option>
-                <option>
-                    <name>IlinkWarningsAreErrors</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>IlinkUseExtraOptions</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>IlinkExtraOptions</name>
-                    <state></state>
-                </option>
-                <option>
-                    <name>IlinkLowLevelInterfaceSlave</name>
-                    <state>1</state>
-                </option>
-                <option>
-                    <name>IlinkAutoLibEnable</name>
-                    <state>1</state>
-                </option>
-                <option>
-                    <name>IlinkAdditionalLibs</name>
-                    <state></state>
-                </option>
-                <option>
-                    <name>IlinkOverrideProgramEntryLabel</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>IlinkProgramEntryLabelSelect</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>IlinkProgramEntryLabel</name>
-                    <state>__iar_program_start</state>
-                </option>
-                <option>
-                    <name>DoFill</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>FillerByte</name>
-                    <state>0xFF</state>
-                </option>
-                <option>
-                    <name>FillerStart</name>
-                    <state>0x0</state>
-                </option>
-                <option>
-                    <name>FillerEnd</name>
-                    <state>0x0</state>
-                </option>
-                <option>
-                    <name>CrcSize</name>
-                    <version>0</version>
-                    <state>1</state>
-                </option>
-                <option>
-                    <name>CrcAlign</name>
-                    <state>1</state>
-                </option>
-                <option>
-                    <name>CrcPoly</name>
-                    <state>0x11021</state>
-                </option>
-                <option>
-                    <name>CrcCompl</name>
-                    <version>0</version>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>CrcBitOrder</name>
-                    <version>0</version>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>CrcInitialValue</name>
-                    <state>0x0</state>
-                </option>
-                <option>
-                    <name>DoCrc</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>IlinkBE8Slave</name>
-                    <state>1</state>
-                </option>
-                <option>
-                    <name>IlinkBufferedTerminalOutput</name>
-                    <state>1</state>
-                </option>
-                <option>
-                    <name>IlinkStdoutInterfaceSlave</name>
-                    <state>1</state>
-                </option>
-                <option>
-                    <name>CrcFullSize</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>IlinkIElfToolPostProcess</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>IlinkLogAutoLibSelect</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>IlinkLogRedirSymbols</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>IlinkLogUnusedFragments</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>IlinkCrcReverseByteOrder</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>IlinkCrcUseAsInput</name>
-                    <state>1</state>
-                </option>
-                <option>
-                    <name>IlinkOptInline</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>IlinkOptExceptionsAllow</name>
-                    <state>1</state>
-                </option>
-                <option>
-                    <name>IlinkOptExceptionsForce</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>IlinkCmsis</name>
-                    <state>1</state>
-                </option>
-                <option>
-                    <name>IlinkOptMergeDuplSections</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>IlinkOptUseVfe</name>
-                    <state>1</state>
-                </option>
-                <option>
-                    <name>IlinkOptForceVfe</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>IlinkStackAnalysisEnable</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>IlinkStackControlFile</name>
-                    <state></state>
-                </option>
-                <option>
-                    <name>IlinkStackCallGraphFile</name>
-                    <state></state>
-                </option>
-                <option>
-                    <name>CrcAlgorithm</name>
-                    <version>1</version>
-                    <state>1</state>
-                </option>
-                <option>
-                    <name>CrcUnitSize</name>
-                    <version>0</version>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>IlinkThreadsSlave</name>
-                    <state>1</state>
-                </option>
-                <option>
-                    <name>IlinkLogCallGraph</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>IlinkIcfFile_AltDefault</name>
-                    <state></state>
-                </option>
-                <option>
-                    <name>IlinkEncInput</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>IlinkEncOutput</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>IlinkEncOutputBom</name>
-                    <state>1</state>
-                </option>
-                <option>
-                    <name>IlinkHeapSelect</name>
-                    <state>1</state>
-                </option>
-                <option>
-                    <name>IlinkLocaleSelect</name>
-                    <state>1</state>
-                </option>
-            </data>
-        </settings>
-        <settings>
-            <name>IARCHIVE</name>
-            <archiveVersion>0</archiveVersion>
-            <data>
-                <version>0</version>
-                <wantNonLocal>1</wantNonLocal>
-                <debug>1</debug>
-                <option>
-                    <name>IarchiveInputs</name>
-                    <state></state>
-                </option>
-                <option>
-                    <name>IarchiveOverride</name>
-                    <state>0</state>
-                </option>
-                <option>
-                    <name>IarchiveOutput</name>
-                    <state>###Unitialized###</state>
-                </option>
-            </data>
-        </settings>
-        <settings>
-            <name>BILINK</name>
-            <archiveVersion>0</archiveVersion>
-            <data />
-        </settings>
-    </configuration>
-    <file>
-        <name>$PROJ_DIR$\Abstract.txt</name>
-    </file>
-    <file>
-        <name>$PROJ_DIR$\..\..\..\Source\cmsis_cv.c</name>
-    </file>
-    <file>
-        <name>$PROJ_DIR$\..\..\..\Source\CV_CoreFunc.c</name>
-    </file>
-    <file>
-        <name>$PROJ_DIR$\..\..\..\Source\CV_CoreInstr.c</name>
-    </file>
-    <file>
-        <name>$PROJ_DIR$\..\..\..\Source\CV_Framework.c</name>
-    </file>
-    <file>
-        <name>$PROJ_DIR$\..\..\..\Source\CV_GenTimer.c</name>
-    </file>
-    <file>
-        <name>$PROJ_DIR$\..\..\..\Source\CV_MPU_ARMv7.c</name>
-    </file>
-    <file>
-        <name>$PROJ_DIR$\..\..\..\Source\CV_Report.c</name>
-    </file>
-    <file>
-        <name>$PROJ_DIR$\..\..\main.c</name>
-    </file>
-    <group>
-        <name>CMSIS-Pack</name>
-        <tag>CMSISPack.ComponentGroup</tag>
-        <file>
-            <name>$PROJ_DIR$\RTE\RTE_Components.h</name>
-        </file>
-        <group>
-            <name>CMSIS CORE</name>
-            <tag>CMSISPack.Component</tag>
-            <file>
-                <name>${CMSIS_PACK_PATH_ARM#CMSIS#5.1.1-dev1}$\CMSIS\Documentation\Core\html\index.html</name>
-            </file>
-        </group>
-        <group>
-            <name>Device Startup</name>
-            <tag>CMSISPack.Component</tag>
-            <file>
-                <name>${CMSIS_PACK_PATH_ARM#CMSIS#5.1.1-dev1}$\Device\ARM\ARMCM0plus\Include\ARMCM0plus.h</name>
-            </file>
-            <file>
-                <name>$PROJ_DIR$\RTE\CMSIS\ARM\startup_ARMCM0plus.s</name>
-            </file>
-            <file>
-                <name>$PROJ_DIR$\RTE\CMSIS\ARM\system_ARMCM0plus.c</name>
-            </file>
-        </group>
-    </group>
-    <cmsisPackSettings>
-        <rte>&lt;?xml version="1.0" encoding="UTF-8" standalone="no"?&gt;
-&lt;configuration xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"&gt;
-&lt;toolchain Tcompiler="IAR" Toutput="exe"/&gt;
-&lt;components&gt;
-&lt;component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.0.2"&gt;
-&lt;package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/&gt;
-&lt;file category="doc" name="CMSIS/Documentation/Core/html/index.html"/&gt;
-&lt;file category="include" name="CMSIS/Include/"/&gt;
-&lt;/component&gt;
-&lt;component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" deviceDependent="1"&gt;
-&lt;package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/&gt;
-&lt;file category="header" deviceDependent="1" name="Device/ARM/ARMCM0plus/Include/ARMCM0plus.h"/&gt;
-&lt;file attr="config" category="sourceAsm" condition="IAR" deviceDependent="1" name="Device/ARM/ARMCM0plus/Source/IAR/startup_ARMCM0plus.s" version="1.0.0"/&gt;
-&lt;file attr="config" category="sourceC" deviceDependent="1" name="Device/ARM/ARMCM0plus/Source/system_ARMCM0plus.c" version="1.0.0"/&gt;
-&lt;/component&gt;
-&lt;/components&gt;
-&lt;apis/&gt;
-&lt;device Dclock="10000000" Dcore="Cortex-M0+" DcoreVersion="r0p1" Dendian="Little-endian" Dfamily="ARM Cortex M0 plus" Dfpu="NO_FPU" Dmpu="NO_MPU" Dname="ARMCM0P" Dvendor="ARM:82" Pname=""&gt;
-&lt;url&gt;http://www.keil.com/dd2/arm/armcm0p&lt;/url&gt;
-&lt;package name="CMSIS" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.1-dev1"/&gt;
-&lt;/device&gt;
-&lt;packages useAllLatestPacks="1"/&gt;
-&lt;/configuration&gt;
-</rte>
-    </cmsisPackSettings>
-</project>

CMSIS/CoreValidation/Tests/Cortex-M0plus/IAR/CMSIS_CV.eww

@@ -1,7 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<workspace>
-    <project>
-        <path>$WS_DIR$\CMSIS_CV.ewp</path>
-    </project>
-    <batchBuild />
-</workspace>

CMSIS/CoreValidation/Tests/Cortex-M0plus/IAR/RTE/Device/ARMCM0P_MPU/ARMCM0P_MPU.icf

@@ -0,0 +1,62 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_IROM1_start__ = 0x00000000;
+define symbol __ICFEDIT_region_IROM1_end__   = 0x0007FFFF;
+define symbol __ICFEDIT_region_IROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IROM2_end__   = 0x0;
+define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM1_end__   = 0x0;
+define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
+define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_end__   = 0x0;
+define symbol __ICFEDIT_region_IRAM1_start__ = 0x20000000;
+define symbol __ICFEDIT_region_IRAM1_end__   = 0x2000FFFF;
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IRAM2_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__     = 0x400;
+define symbol __ICFEDIT_size_proc_stack__ = 0x0;
+define symbol __ICFEDIT_size_heap__       = 0x800;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region IROM_region   =   mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]
+                              | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
+define region EROM_region   =   mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]
+                              | mem:[from __ICFEDIT_region_EROM2_start__ to __ICFEDIT_region_EROM2_end__]
+                              | mem:[from __ICFEDIT_region_EROM3_start__ to __ICFEDIT_region_EROM3_end__];
+define region IRAM_region   =   mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
+                              | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
+define region ERAM_region   =   mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__]
+                              | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__]
+                              | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__];
+
+define block CSTACK     with alignment = 8, size = __ICFEDIT_size_cstack__     { };
+define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
+define block HEAP       with alignment = 8, size = __ICFEDIT_size_heap__       { };
+
+do not initialize  { section .noinit };
+initialize by copy { readwrite };
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+  // Required in a multi-threaded application
+  initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in IROM_region  { readonly };
+place in EROM_region  { readonly section application_specific_ro };
+place in IRAM_region  { readwrite, block CSTACK, block PROC_STACK, block HEAP };
+place in ERAM_region  { readwrite section application_specific_rw };

CMSIS/CoreValidation/Tests/Cortex-M0plus/IAR/RTE/RTE_Components.h

@@ -1,15 +0,0 @@
-
-/*
- * This is an auto generated Run-Time-Environment Component Configuration File
- * DO NOT MODIFY!
- *
- * Project: 'CMSIS_CV'
- * Device: 'ARMCM0P' Pack: 'ARM::CMSIS.5.1.1-dev1'
- */
-
-#ifndef RTE_COMPONENTS_H
-#define RTE_COMPONENTS_H
-
-#define CMSIS_device_header "ARMCM0plus.h"
-
-#endif  /* RTE_COMPONENTS_H */

CMSIS/CoreValidation/Tests/Cortex-M0plus/IAR/default.rtebuild

@@ -0,0 +1,14 @@
+import:
+ - ../cortex-m0.rtebuild
+config:
+  FVP:
+    toolchain: ICCARM
+    commonflags : [ "--endian little", "--cpu ${cpu}", "--fpu ${fpu}" ]
+    cflags      : [ "${commonflags}", --debug, -e, "--dlib_config DLib_Config_Full.h" ]
+    asmflags    : [ "${commonflags}" ]
+    linkflags   : [ --semihosting, "--entry __iar_program_start", --vfe, "--text_out locale" ]
+    linkscript: "${basedir}/RTE/Device/${device}/${device}.icf"
+include: 
+ - ./
+source:
+ - RTE/Device/${device}/startup_${device}.s

CMSIS/CoreValidation/Tests/Cortex-M0plus/cortex-m0.rtebuild

@@ -0,0 +1,14 @@
+import:
+ - ../test.rtebuild
+config:
+  default: FVP
+  FVP:
+    cpu   : Cortex-M0+
+    mcpu  : cortex-m0+
+    fpu   : none
+    mfpu  : none
+    target: ARM:82/ARMCM0P_MPU/Cortex-M0+
+source:
+ - ../../Source/CV_CoreFunc.c
+ - ../../Source/CV_CoreInstr.c
+ - ../../Source/CV_MPU_ARMv7.c

CMSIS/CoreValidation/Tests/build.py

@@ -86,26 +86,26 @@ SKIP = [
   ]
   
 FVP_MODELS = { 
-    DEVICE_CM0      : { 'cmd': "FVP_MPS2_Cortex-M0_MDK.exe",  'args': { 'limit': "50000000", 'config': "ARMCM0_config.txt" } },
-    DEVICE_CM0PLUS  : { 'cmd': "FVP_MPS2_Cortex-M0_MDK.exe",  'args': { 'limit': "50000000", 'config': "ARMCM0plus_config.txt" } },
-    DEVICE_CM3      : { 'cmd': "FVP_MPS2_Cortex-M3_MDK.exe",  'args': { 'limit': "50000000", 'config': "ARMCM3_config.txt" } },
-    DEVICE_CM4      : { 'cmd': "FVP_MPS2_Cortex-M4_MDK.exe",  'args': { 'limit': "50000000", 'config': "ARMCM4_config.txt" } },
-    DEVICE_CM4FP    : { 'cmd': "FVP_MPS2_Cortex-M4_MDK.exe",  'args': { 'limit': "50000000", 'config': "ARMCM4FP_config.txt" } },
-    DEVICE_CM7      : { 'cmd': "FVP_MPS2_Cortex-M7_MDK.exe",  'args': { 'limit': "50000000", 'config': "ARMCM7_config.txt" } },
-    DEVICE_CM7SP    : { 'cmd': "FVP_MPS2_Cortex-M7_MDK.exe",  'args': { 'limit': "50000000", 'config': "ARMCM7SP_config.txt" } },
-    DEVICE_CM7DP    : { 'cmd': "FVP_MPS2_Cortex-M7_MDK.exe",  'args': { 'limit': "50000000", 'config': "ARMCM7DP_config.txt" } },
-    DEVICE_CM23     : { 'cmd': "FVP_MPS2_Cortex-M23_MDK.exe", 'args': { 'limit': "50000000", 'config': "ARMCM23_config.txt",           'target': "cpu0" } },
-    DEVICE_CM33     : { 'cmd': "FVP_MPS2_Cortex-M33_MDK.exe", 'args': { 'limit': "50000000", 'config': "ARMCM33_config.txt",           'target': "cpu0" } },
-    DEVICE_CM23NS   : { 'cmd': "FVP_MPS2_Cortex-M23_MDK.exe", 'args': { 'limit': "50000000", 'config': "ARMCM23_TZ_config.txt",        'target': "cpu0" } },
-    DEVICE_CM33NS   : { 'cmd': "FVP_MPS2_Cortex-M33_MDK.exe", 'args': { 'limit': "50000000", 'config': "ARMCM33_DSP_FP_TZ_config.txt", 'target': "cpu0" } },
-    DEVICE_CM23S    : { 'cmd': "FVP_MPS2_Cortex-M23_MDK.exe", 'args': { 'limit': "50000000", 'config': "ARMCM23_TZ_config.txt",        'target': "cpu0" } },
-    DEVICE_CM33S    : { 'cmd': "FVP_MPS2_Cortex-M33_MDK.exe", 'args': { 'limit': "50000000", 'config': "ARMCM33_DSP_FP_TZ_config.txt", 'target': "cpu0" } },
-    DEVICE_CA5      : { 'cmd': "fvp_ve_cortex-a5x1.exe",      'args': { 'limit': "70000000", 'config': "ARMCA5_config.txt" } },
-    DEVICE_CA7      : { 'cmd': "fvp_ve_cortex-a7x1.exe",      'args': { 'limit': "170000000", 'config': "ARMCA7_config.txt" } },
-    DEVICE_CA9      : { 'cmd': "fvp_ve_cortex-a9x1.exe",      'args': { 'limit': "70000000", 'config': "ARMCA9_config.txt" } },
-    DEVICE_CA5NEON  : { 'cmd': "fvp_ve_cortex-a5x1.exe",      'args': { 'limit': "70000000", 'config': "ARMCA5neon_config.txt" } },
-    DEVICE_CA7NEON  : { 'cmd': "fvp_ve_cortex-a7x1.exe",      'args': { 'limit': "170000000", 'config': "ARMCA7neon_config.txt" } },
-    DEVICE_CA9NEON  : { 'cmd': "fvp_ve_cortex-a9x1.exe",      'args': { 'limit': "70000000", 'config': "ARMCA9neon_config.txt" } }
+    DEVICE_CM0      : { 'cmd': "FVP_MPS2_Cortex-M0_MDK.exe",      'args': { 'limit': "50000000", 'config': "ARMCM0_config.txt" } },
+    DEVICE_CM0PLUS  : { 'cmd': "FVP_MPS2_Cortex-M0plus_MDK.exe",  'args': { 'limit': "50000000", 'config': "ARMCM0plus_config.txt" } },
+    DEVICE_CM3      : { 'cmd': "FVP_MPS2_Cortex-M3_MDK.exe",      'args': { 'limit': "50000000", 'config': "ARMCM3_config.txt" } },
+    DEVICE_CM4      : { 'cmd': "FVP_MPS2_Cortex-M4_MDK.exe",      'args': { 'limit': "50000000", 'config': "ARMCM4_config.txt" } },
+    DEVICE_CM4FP    : { 'cmd': "FVP_MPS2_Cortex-M4_MDK.exe",      'args': { 'limit': "50000000", 'config': "ARMCM4FP_config.txt" } },
+    DEVICE_CM7      : { 'cmd': "FVP_MPS2_Cortex-M7_MDK.exe",      'args': { 'limit': "50000000", 'config': "ARMCM7_config.txt" } },
+    DEVICE_CM7SP    : { 'cmd': "FVP_MPS2_Cortex-M7_MDK.exe",      'args': { 'limit': "50000000", 'config': "ARMCM7SP_config.txt" } },
+    DEVICE_CM7DP    : { 'cmd': "FVP_MPS2_Cortex-M7_MDK.exe",      'args': { 'limit': "50000000", 'config': "ARMCM7DP_config.txt" } },
+    DEVICE_CM23     : { 'cmd': "FVP_MPS2_Cortex-M23_MDK.exe",     'args': { 'limit': "50000000", 'config': "ARMCM23_config.txt",           'target': "cpu0" } },
+    DEVICE_CM33     : { 'cmd': "FVP_MPS2_Cortex-M33_MDK.exe",     'args': { 'limit': "50000000", 'config': "ARMCM33_config.txt",           'target': "cpu0" } },
+    DEVICE_CM23NS   : { 'cmd': "FVP_MPS2_Cortex-M23_MDK.exe",     'args': { 'limit': "50000000", 'config': "ARMCM23_TZ_config.txt",        'target': "cpu0" } },
+    DEVICE_CM33NS   : { 'cmd': "FVP_MPS2_Cortex-M33_MDK.exe",     'args': { 'limit': "50000000", 'config': "ARMCM33_DSP_FP_TZ_config.txt", 'target': "cpu0" } },
+    DEVICE_CM23S    : { 'cmd': "FVP_MPS2_Cortex-M23_MDK.exe",     'args': { 'limit': "50000000", 'config': "ARMCM23_TZ_config.txt",        'target': "cpu0" } },
+    DEVICE_CM33S    : { 'cmd': "FVP_MPS2_Cortex-M33_MDK.exe",     'args': { 'limit': "50000000", 'config': "ARMCM33_DSP_FP_TZ_config.txt", 'target': "cpu0" } },
+    DEVICE_CA5      : { 'cmd': "fvp_ve_cortex-a5x1.exe",          'args': { 'limit': "70000000", 'config': "ARMCA5_config.txt" } },
+    DEVICE_CA7      : { 'cmd': "fvp_ve_cortex-a7x1.exe",          'args': { 'limit': "170000000", 'config': "ARMCA7_config.txt" } },
+    DEVICE_CA9      : { 'cmd': "fvp_ve_cortex-a9x1.exe",          'args': { 'limit': "70000000", 'config': "ARMCA9_config.txt" } },
+    DEVICE_CA5NEON  : { 'cmd': "fvp_ve_cortex-a5x1.exe",          'args': { 'limit': "70000000", 'config': "ARMCA5neon_config.txt" } },
+    DEVICE_CA7NEON  : { 'cmd': "fvp_ve_cortex-a7x1.exe",          'args': { 'limit': "170000000", 'config': "ARMCA7neon_config.txt" } },
+    DEVICE_CA9NEON  : { 'cmd': "fvp_ve_cortex-a9x1.exe",          'args': { 'limit': "70000000", 'config': "ARMCA9neon_config.txt" } }
   }
 
 def isSkipped(dev, cc, target):
@@ -118,7 +118,13 @@ def isSkipped(dev, cc, target):
   return False
   
 def testProject(dev, cc, target):
-  if (cc == CC_AC5) or (cc == CC_AC6):
+  rtebuild = "{dev}/{cc}/default.rtebuild".format(dev = dev, cc = cc, target=target)
+  if os.path.exists(rtebuild):
+    return [
+        rtebuild,
+        "{dev}/{cc}/build/{target}.elf".format(dev = dev, cc = cc, target=target)
+      ]
+  elif (cc == CC_AC5) or (cc == CC_AC6):
     if dev in MDK_ENV['DS']:
       return [
           "{dev}/{cc}/.project".format(dev = dev, cc = cc),
@@ -164,7 +170,13 @@ def testProject(dev, cc, target):
   raise "Unknown compiler!"
 
 def bootloaderProject(dev, cc, target):
-  if (cc == CC_AC5) or (cc == CC_AC6):
+  rtebuild = "{dev}/{cc}/Bootloader/default.rtebuild".format(dev = dev, cc = cc, target=target)
+  if os.path.exists(rtebuild):
+    return [
+        rtebuild,
+        "{dev}/{cc}/Bootloader/build/{target}.elf".format(dev = dev, cc = cc, target=target)
+      ]
+  elif (cc == CC_AC5) or (cc == CC_AC6):
     return [
         "{dev}/{cc}/Bootloader/Bootloader.uvprojx".format(dev = dev, cc = cc),
         "{dev}/{cc}/Bootloader/Objects/Bootloader.axf".format(dev = dev, cc = cc)
@@ -182,26 +194,18 @@ def bootloaderProject(dev, cc, target):
   raise "Unknown compiler!"
   
 def buildStep(dev, cc, target, project):
-  if (cc == CC_AC5) or (cc == CC_AC6):
-    if dev in MDK_ENV['DS']:
-      return DsCmd(project, "CMSIS_CV_{adev}_{cc}".format(adev=ADEVICES[dev], cc = cc))
-    elif dev in MDK_ENV['RTE']:
-      return RteCmd(project, target)
-    else:
-      return Uv4Cmd(project, target)
-  elif (cc == CC_GCC):
-    if dev in MDK_ENV['DS']:
-      return DsCmd(project, target)
-    elif dev in MDK_ENV['RTE']:
-      return RteCmd(project, target)
-    else:
-      return Uv4Cmd(project, target)
-  elif (cc == CC_IAR):
-    if dev in MDK_ENV['RTE']:
-      return RteCmd(project, target)
-    else:
-      return IarCmd(project, target)
-  raise "Unknown compiler!"
+  STEP_TYPES = {
+    ".uvprojx"  : Uv4Cmd,
+    ".ewp"      : IarCmd,
+    ".rtebuild" : RteCmd
+  }
+  
+  projectfile, projectext = os.path.splitext(project)
+  
+  if not projectext in STEP_TYPES:
+    raise "Unknown project type '"+projectext+"'!"
+    
+  return STEP_TYPES[projectext](project, target)
   
 def prepare(steps, args):
   for dev in args.devices:

CMSIS/CoreValidation/Tests/buildutils/rtecmd.py

@@ -8,16 +8,17 @@ import mmap
 
 class RteCmd(BuildCmd):
 
-  def __init__(self, project, config):
+  def __init__(self, project, config, subcmd = "build"):
     BuildCmd.__init__(self)
     self._project = project
     self._config = config
+    self._subcmd = subcmd
 
   def getCommand(self):
     return "python.exe"
     
   def getArguments(self):
-    return [ os.path.normpath(shutil.which("rtebuild.py")), "-c", self._config, os.path.abspath(self._project) ]
+    return [ os.path.normpath(shutil.which("rtebuild.py")), "-c", os.path.abspath(self._project), "-t", self._config, self._subcmd ]
 
   def needsShell(self):
     return True

CMSIS/CoreValidation/Tests/lint.py

@@ -0,0 +1,28 @@
+import sys
+import os.path
+from argparse import ArgumentParser
+
+sys.path.append('buildutils') 
+
+from rtecmd import RteCmd 
+
+def main(argv):
+  parser = ArgumentParser()
+  parser.add_argument('-d', '--device', required=True, help = 'Device to be considered.')
+  parser.add_argument('-c', '--compiler', required=True, help = 'Compiler to be considered.')
+  parser.add_argument('-t', '--target', nargs='?', default="default", help = 'Target to be considered.')
+  args = parser.parse_args()
+  
+  rtebuild = os.path.join(args.device, args.compiler, "default.rtebuild")
+  
+  if not os.path.isfile(rtebuild):
+    raise IOError("rtebuild project not available:'"+rtebuild+"'")
+    
+  cmd = RteCmd(rtebuild, args.target, "lint")
+  cmd.run()
+  
+if __name__ == "__main__":
+  try:
+    main(sys.argv[1:])
+  except Exception as e:
+    print(e)

CMSIS/CoreValidation/Tests/test.rtebuild

@@ -1,5 +1,8 @@
 import:
  - ${home}/.rtebuild/toolchain.rtebuild
+config:
+  FVP:
+    lintflags : [ "Config/MISRA_C_2012_Config.lnt", "-wlib(4)", "-wlib(1)", "+ffn", "-width(0)", "-hf1", "-\"format=%f(%l): %t %n: %m (%t <a href=\\q/userContent/LintMsgRef.html#%n\\q>%n</a>)\"" ]
 include: 
  - ../Include
 source:

CMSIS/Core_A/Include/cmsis_armcc.h

@@ -448,19 +448,20 @@ __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
  * Include common core functions to access Coprocessor 15 registers
  */
  
-#define __get_CP(cp, op1, Rt, CRn, CRm, op2) do { register uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); Rt = tmp; } while(0)
-#define __set_CP(cp, op1, Rt, CRn, CRm, op2) do { register uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); tmp = Rt; } while(0)
+#define __get_CP(cp, op1, Rt, CRn, CRm, op2) do { register uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); (Rt) = tmp; } while(0)
+#define __set_CP(cp, op1, Rt, CRn, CRm, op2) do { register uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); tmp = (Rt); } while(0)
 #define __get_CP64(cp, op1, Rt, CRm) \
   do { \
     uint32_t ltmp, htmp; \
     __ASM volatile("MRRC p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \
-    Rt = (((uint64_t)htmp) << 32U) | ((uint64_t)ltmp); \
+    (Rt) = ((((uint64_t)htmp) << 32U) | ((uint64_t)ltmp)); \
   } while(0)
 
 #define __set_CP64(cp, op1, Rt, CRm) \
   do { \
-    const uint32_t ltmp = (uint32_t)Rt; \
-    const uint32_t htmp = (uint32_t)(Rt >> 32); \
+    const uint64_t tmp = (Rt); \
+    const uint32_t ltmp = (uint32_t)(tmp); \
+    const uint32_t htmp = (uint32_t)(tmp >> 32U); \
     __ASM volatile("MCRR p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \
   } while(0)
 
@@ -548,7 +549,7 @@ __STATIC_INLINE __ASM void __FPU_Enable(void)
 
         //Initialise VFP/NEON registers to 0
         MOV     R2,#0
-  IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} >= 16
+
         //Initialise D16 registers to 0
         VMOV    D0, R2,R2
         VMOV    D1, R2,R2
@@ -566,7 +567,7 @@ __STATIC_INLINE __ASM void __FPU_Enable(void)
         VMOV    D13,R2,R2
         VMOV    D14,R2,R2
         VMOV    D15,R2,R2
-  ENDIF
+
   IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
         //Initialise D32 registers to 0
         VMOV    D16,R2,R2

CMSIS/Core_A/Include/cmsis_armclang.h

@@ -495,24 +495,23 @@ __STATIC_INLINE void __L1C_CleanInvalidateCache(uint32_t op)
 __STATIC_INLINE void __FPU_Enable(void)
 {
   __ASM volatile(
-	    //Permit access to VFP/NEON, registers by modifying CPACR
+    //Permit access to VFP/NEON, registers by modifying CPACR
     "        MRC     p15,0,R1,c1,c0,2  \n"
     "        ORR     R1,R1,#0x00F00000 \n"
     "        MCR     p15,0,R1,c1,c0,2  \n"
 
-	    //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
+    //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
     "        ISB                       \n"
 
-	    //Enable VFP/NEON
+    //Enable VFP/NEON
     "        VMRS    R1,FPEXC          \n"
     "        ORR     R1,R1,#0x40000000 \n"
     "        VMSR    FPEXC,R1          \n"
 
-	    //Initialise VFP/NEON registers to 0
+    //Initialise VFP/NEON registers to 0
     "        MOV     R2,#0             \n"
 
-#if TARGET_FEATURE_EXTENSION_REGISTER_COUNT >= 16
-	    //Initialise D16 registers to 0
+    //Initialise D16 registers to 0
     "        VMOV    D0, R2,R2         \n"
     "        VMOV    D1, R2,R2         \n"
     "        VMOV    D2, R2,R2         \n"
@@ -529,10 +528,9 @@ __STATIC_INLINE void __FPU_Enable(void)
     "        VMOV    D13,R2,R2         \n"
     "        VMOV    D14,R2,R2         \n"
     "        VMOV    D15,R2,R2         \n"
-#endif
 
-#if TARGET_FEATURE_EXTENSION_REGISTER_COUNT == 32
-	    //Initialise D32 registers to 0
+#if __ARM_NEON == 1
+    //Initialise D32 registers to 0
     "        VMOV    D16,R2,R2         \n"
     "        VMOV    D17,R2,R2         \n"
     "        VMOV    D18,R2,R2         \n"
@@ -549,9 +547,9 @@ __STATIC_INLINE void __FPU_Enable(void)
     "        VMOV    D29,R2,R2         \n"
     "        VMOV    D30,R2,R2         \n"
     "        VMOV    D31,R2,R2         \n"
-    ".endif                            \n"
 #endif
-	    //Initialise FPSCR to a known state
+
+    //Initialise FPSCR to a known state
     "        VMRS    R2,FPSCR          \n"
     "        LDR     R3,=0x00086060    \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
     "        AND     R2,R2,R3          \n"

CMSIS/Core_A/Include/cmsis_gcc.h

@@ -683,24 +683,23 @@ __STATIC_INLINE void __L1C_CleanInvalidateCache(uint32_t op)
 __STATIC_INLINE void __FPU_Enable(void)
 {
   __ASM volatile(
-        //Permit access to VFP/NEON, registers by modifying CPACR
+    //Permit access to VFP/NEON, registers by modifying CPACR
     "        MRC     p15,0,R1,c1,c0,2  \n"
     "        ORR     R1,R1,#0x00F00000 \n"
     "        MCR     p15,0,R1,c1,c0,2  \n"
 
-        //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
+    //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
     "        ISB                       \n"
 
-        //Enable VFP/NEON
+    //Enable VFP/NEON
     "        VMRS    R1,FPEXC          \n"
     "        ORR     R1,R1,#0x40000000 \n"
     "        VMSR    FPEXC,R1          \n"
 
-        //Initialise VFP/NEON registers to 0
+    //Initialise VFP/NEON registers to 0
     "        MOV     R2,#0             \n"
 
-#if TARGET_FEATURE_EXTENSION_REGISTER_COUNT >= 16
-        //Initialise D16 registers to 0
+    //Initialise D16 registers to 0
     "        VMOV    D0, R2,R2         \n"
     "        VMOV    D1, R2,R2         \n"
     "        VMOV    D2, R2,R2         \n"
@@ -717,10 +716,9 @@ __STATIC_INLINE void __FPU_Enable(void)
     "        VMOV    D13,R2,R2         \n"
     "        VMOV    D14,R2,R2         \n"
     "        VMOV    D15,R2,R2         \n"
-#endif
 
-#if TARGET_FEATURE_EXTENSION_REGISTER_COUNT == 32
-        //Initialise D32 registers to 0
+#if __ARM_NEON == 1
+    //Initialise D32 registers to 0
     "        VMOV    D16,R2,R2         \n"
     "        VMOV    D17,R2,R2         \n"
     "        VMOV    D18,R2,R2         \n"
@@ -738,7 +736,8 @@ __STATIC_INLINE void __FPU_Enable(void)
     "        VMOV    D30,R2,R2         \n"
     "        VMOV    D31,R2,R2         \n"
 #endif
-        //Initialise FPSCR to a known state
+
+    //Initialise FPSCR to a known state
     "        VMRS    R2,FPSCR          \n"
     "        LDR     R3,=0x00086060    \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
     "        AND     R2,R2,R3          \n"

CMSIS/Core_A/Include/cmsis_iccarm.h

@@ -242,16 +242,16 @@
   #define __set_FPEXC(VALUE) 		(__arm_wsr("FPEXC", VALUE))
 
   #define __get_CP(cp, op1, RT, CRn, CRm, op2) \
-    (RT = __arm_rsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2))
+    ((RT) = __arm_rsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2))
 
   #define __set_CP(cp, op1, RT, CRn, CRm, op2) \
-    (__arm_wsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2, RT))
+    (__arm_wsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2, (RT)))
 
   #define __get_CP64(cp, op1, RT, CRm) \
-    (RT = __arm_rsr("p" # cp ":" # op1 ":c" # CRm))
+    ((RT) = __arm_rsr("p" # cp ":" # op1 ":c" # CRm))
 
   #define __set_CP64(cp, op1, RT, CRm) \
-    (__arm_wsr("p" # cp ":" # op1 ":c" # CRm, RT))
+    (__arm_wsr("p" # cp ":" # op1 ":c" # CRm, (RT)))
 
   #include "cmsis_cp15.h"
 
@@ -362,6 +362,10 @@
   #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
   #endif
 
+  #ifdef __INTRINSICS_INCLUDED
+  #error intrinsics.h is already included previously!
+  #endif
+  
   #include <intrinsics.h>
 
   #if !__FPU_PRESENT
@@ -533,24 +537,23 @@ __STATIC_INLINE
 void __FPU_Enable(void)
 {
   __ASM volatile(
-	    //Permit access to VFP/NEON, registers by modifying CPACR
+    //Permit access to VFP/NEON, registers by modifying CPACR
     "        MRC     p15,0,R1,c1,c0,2  \n"
     "        ORR     R1,R1,#0x00F00000 \n"
     "        MCR     p15,0,R1,c1,c0,2  \n"
 
-	    //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
+    //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
     "        ISB                       \n"
 
-	    //Enable VFP/NEON
+    //Enable VFP/NEON
     "        VMRS    R1,FPEXC          \n"
     "        ORR     R1,R1,#0x40000000 \n"
     "        VMSR    FPEXC,R1          \n"
 
-	    //Initialise VFP/NEON registers to 0
+    //Initialise VFP/NEON registers to 0
     "        MOV     R2,#0             \n"
 
-#if TARGET_FEATURE_EXTENSION_REGISTER_COUNT >= 16
-	    //Initialise D16 registers to 0
+    //Initialise D16 registers to 0
     "        VMOV    D0, R2,R2         \n"
     "        VMOV    D1, R2,R2         \n"
     "        VMOV    D2, R2,R2         \n"
@@ -567,10 +570,9 @@ void __FPU_Enable(void)
     "        VMOV    D13,R2,R2         \n"
     "        VMOV    D14,R2,R2         \n"
     "        VMOV    D15,R2,R2         \n"
-#endif
 
-#if TARGET_FEATURE_EXTENSION_REGISTER_COUNT == 32
-	    //Initialise D32 registers to 0
+#ifdef __ARM_ADVANCED_SIMD__
+    //Initialise D32 registers to 0
     "        VMOV    D16,R2,R2         \n"
     "        VMOV    D17,R2,R2         \n"
     "        VMOV    D18,R2,R2         \n"
@@ -587,12 +589,12 @@ void __FPU_Enable(void)
     "        VMOV    D29,R2,R2         \n"
     "        VMOV    D30,R2,R2         \n"
     "        VMOV    D31,R2,R2         \n"
-    ".endif                            \n"
 #endif
-	    //Initialise FPSCR to a known state
+
+    //Initialise FPSCR to a known state
     "        VMRS    R2,FPSCR          \n"
     "        MOV32   R3,#0x00086060    \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
-	"        AND     R2,R2,R3          \n"
+    "        AND     R2,R2,R3          \n"
     "        VMSR    FPSCR,R2          \n");
 }
 

CMSIS/DoxyGen/Driver/src/Driver_MCI.c

@@ -60,14 +60,266 @@ The driver functions are published in the access struct as explained in \ref Dri
   - \ref ARM_DRIVER_MCI : access struct for MCI driver functions
 @{
 */
-/*
+/**
 A typical setup sequence for the driver is shown below:
 
 <b>Example Code:</b>
 
-\todo example
+\code
+ 
+#include "Driver_MCI.h"
+ 
+/* Usage example: ARM_MCI_Initialize ----------------------------------------*/
+ 
+// ARM_MCI_SignalEvent callback function prototype
+void MCI_SignalEvent_Callback (uint32_t event);
+ 
+void init_driver (ARM_DRIVER_MCI *drv) {
+  int32_t status;
+  
+  status = drv->Initialize (&MCI_SignalEvent_Callback);
+  
+  if (status != ARM_DRIVER_OK) {
+    // Initialization and event callback registration failed
+  }
+}
+ 
+/* Usage example: ARM_MCI_Uninitialize --------------------------------------*/
+ 
+void uninit_driver (ARM_DRIVER_MCI *drv) {
+  int32_t status;
+  
+  status = drv->Uninitialize ();
+  
+  if (status == ARM_DRIVER_OK) {
+    // Driver successfully uninitialized
+  }
+}
+ 
+/* Usage example: ARM_MCI_PowerControl --------------------------------------*/
+ 
+void control_driver_power (ARM_DRIVER_MCI *drv, bool enable) {
+  int32_t status;
+  
+  if (enable == true) {
+    status = drv->PowerControl (ARM_POWER_FULL);
+  }
+  else {
+    status = drv->PowerControl (ARM_POWER_OFF);
+  }
+  
+  if (status == ARM_DRIVER_OK) {
+    // Driver power enabled/disabled
+  }
+}
+ 
+/* Usage example: ARM_MCI_CardPower -----------------------------------------*/
+ 
+ARM_MCI_CAPABILITIES drv_capabilities;
+ 
+void set_card_vdd_3v3 (ARM_DRIVER_MCI *drv) {
+  int32_t status;
+  
+  if (drv_capabilities.vdd == 1) {
+    // Power switching to 3.3V supported
+    status = drv->CardPower (ARM_MCI_POWER_VDD_3V3);
+    
+    if (status == ARM_DRIVER_OK) {
+      // Card power set to 3.3V
+    }
+  }
+}
+ 
+/* Usage example: ARM_MCI_ReadCD --------------------------------------------*/
+ 
+void read_card_detect_state (ARM_DRIVER_MCI *drv) {
+  int32_t status;
+  
+  status = drv->ReadCD();
+  
+  if (status == 1) {
+    // Memory card is detected
+  }
+  else {
+    if (status == 0) {
+      // Memory card is not detected
+    }
+    else {
+      // Error reading card detect pin state
+    }
+  }
+}
+ 
+/* Usage example: ARM_MCI_ReadWP --------------------------------------------*/
+ 
+void read_write_protect_state (ARM_DRIVER_MCI *drv) {
+  int32_t status;
+  
+  status = drv->ReadWP();
+  
+  if (status == 1) {
+    // Memory card write protection is enabled
+  }
+  else {
+    if (status == 0) {
+      // Memory card write protection is disabled
+    }
+    else {
+      // Error reading write protect pin state
+    }
+  }
+}
+ 
+/* Usage example: ARM_MCI_SendCommand ---------------------------------------*/
+ 
+volatile uint32_t MCI_Events;
+ 
+void MCI_SignalEvent_Callback (uint32_t event) {
+  // Save current event
+  MCI_Events |= event;
+}
+ 
+void send_CMD0 (ARM_DRIVER_MCI *drv) {
+  int32_t  status;
+  uint32_t cmd;
+ 
+  MCI_Events = 0; //Clear MCI driver event flags
+  cmd = 0;        // Set GO_IDLE_STATE command code
+ 
+  status = drv->SendCommand (cmd, 0, ARM_MCI_CARD_INITIALIZE | ARM_MCI_RESPONSE_NONE, NULL);
+ 
+  if (status == ARM_DRIVER_OK) {
+    /* Wait for event */
+    while ((MCI_Events & ARM_MCI_EVENT_COMMAND_COMPLETE) == 0U);
+    // Command was successfully sent to memory card
+    // ..
+  }
+  else {
+    // Error
+  }
+}
+ 
+/* Usage example: ARM_MCI_SetupTransfer -------------------------------------*/
+ 
+volatile uint32_t MCI_Events;
+ 
+void MCI_SignalEvent_Callback (uint32_t event) {
+  MCI_Events |= event;  // Save current event
+}
+ 
+void read_sector (ARM_DRIVER_MCI *drv, uint8_t *buf, uint32_t sz) {
+  int32_t status;
+  uint32_t cmd, arg;
+  uint32_t resp;
+ 
+  if (sz < 512) {
+    // Invalid buffer size, sector consists of 512 bytes
+    //...
+  } 
+ 
+  status = drv->SetupTransfer (buf, 1, 512, ARM_MCI_TRANSFER_READ | ARM_MCI_TRANSFER_BLOCK);
+ 
+  if (status == ARM_DRIVER_OK) {
+    MCI_Events = 0; //Clear MCI driver event flags
+
+    cmd = 17;       // Set READ_SINGLE_BLOCK command
+    arg = 0;        // Set sector number
+ 
+    status  = drv->SendCommand (cmd, arg, ARM_MCI_RESPONSE_SHORT | ARM_MCI_RESPONSE_CRC | ARM_MCI_TRANSFER_DATA, &resp);
+ 
+    if (status == ARM_DRIVER_OK) {
+      /* Wait for event */
+      while ((MCI_Events & ARM_MCI_EVENT_COMMAND_COMPLETE) == 0U);
+      // Command was successfully sent to memory card
+      if ((resp & 0x03) == 0) {
+        // Sector number is valid, wait until data transfer completes
+        while ((MCI_Events & ARM_MCI_EVENT_TRANSFER_COMPLETE) == 0U);
+        // Data was successfully read from memory card
+        // ...
+      }
+    }
+  }
+}
+ 
+/* Usage example: ARM_MCI_AbortTransfer -------------------------------------*/
+ 
+void abort_data_transfer (ARM_DRIVER_MCI *drv) {
+  ARM_MCI_STATUS drv_status;
 
+  drv_status = drv->GetStatus();
+  
+  if (drv_status.transfer_active == 1U) {
+    // Data transfer is active, abort the transfer
+    if (drv->AbortTransfer() == ARM_DRIVER_OK) {
+      // Transfer aborted
+      // ...
+    }
+  }
+}
+ 
+/* Usage example: ARM_MCI_GetStatus -----------------------------------------*/
+ 
+void check_transfer_status (ARM_DRIVER_MCI *drv) {
+  ARM_MCI_STATUS drv_status;
+
+  drv_status = drv->GetStatus();
 
+  if (drv_status.transfer_active == 1U) {
+    // Data transfer is active
+  }
+  
+  if (drv_status.transfer_timeout == 1U) {
+    // Data not received, timeout expired
+  }
+  
+  if (drv_status.transfer_error == 1U) {
+    // Data transfer ended with error
+  }
+}
+ 
+/* Usage example: ARM_MCI_SignalEvent ---------------------------------------*/
+ 
+void MCI_SignalEvent_Callback (uint32_t event) {
+  if ((event & ARM_MCI_EVENT_CARD_INSERTED) != 0U) {
+    // Memory card was inserted into socket
+  }
+  if ((event & ARM_MCI_EVENT_CARD_REMOVED) != 0U) {
+    // Memory card was removed from socket
+  }
+
+  if ((event & ARM_MCI_EVENT_COMMAND_COMPLETE) != 0U) {
+    // Command was successfully sent to memory card
+  }
+  if ((event & ARM_MCI_EVENT_COMMAND_TIMEOUT) != 0U) {
+    // Command response was not received in time
+  }
+  if ((event & ARM_MCI_EVENT_COMMAND_ERROR) != 0U) {
+    // Command response was invalid
+  }
+
+  if ((event & ARM_MCI_EVENT_TRANSFER_COMPLETE) != 0U) {
+    // Data successfully transferred from/to memory card
+  }
+  if ((event & ARM_MCI_EVENT_TRANSFER_TIMEOUT) != 0U) {
+    // Data not transferred from/to memory card, timeout expired
+  }
+  if ((event & ARM_MCI_EVENT_TRANSFER_ERROR) != 0U) {
+    // Data transfer ended with errors
+  }
+  
+  if ((event & ARM_MCI_EVENT_SDIO_INTERRUPT) != 0U) {
+    // SD I/O card sent interrupt request
+  }
+  
+  if ((event & ARM_MCI_EVENT_CCS) != 0U) {
+    // CE-ATA command completion signal received
+  }
+  if ((event & ARM_MCI_EVENT_CCS_TIMEOUT) != 0U) {
+    // CE-ATA command completion signal wait timeout expired
+  }
+}
+
+\endcode
 
 */
 

CMSIS/RTOS2/RTX/Source/ARM/irq_ca.s

@@ -384,19 +384,18 @@ osRtxContextSave
 
                 VMRS    R2, FPSCR
                 STMDB   R3!, {R2,R12}               ; Push FPSCR, maintain 8-byte alignment
-                IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 16
-                VSTMDB  R3!, {D0-D15}
-                LDRB    R2, [R0, #TCB_SP_FRAME]     ; Record in TCB that VFP/D16 state is stacked
-                ORR     R2, R2, #2
-                STRB    R2, [R0, #TCB_SP_FRAME]
+
+                VSTMDB  R3!, {D0-D15}               ; Save D0-D15
+                IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
+                VSTMDB  R3!, {D16-D31}              ; Save D16-D31
                 ENDIF
+                LDRB    R2, [R0, #TCB_SP_FRAME]
                 IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
-                VSTMDB  R3!, {D0-D15}
-                VSTMDB  R3!, {D16-D31}
-                LDRB    R2, [R0, #TCB_SP_FRAME]     ; Record in TCB that NEON/D32 state is stacked
-                ORR     R2, R2, #4
-                STRB    R2, [R0, #TCB_SP_FRAME]
+                ORR     R2, R2, #4                  ; NEON state
+                ELSE
+                ORR     R2, R2, #2                  ; VFP state
                 ENDIF
+                STRB    R2, [R0, #TCB_SP_FRAME]     ; Record VFP/NEON state
 
 osRtxContextSave1
                 STR     R3, [R0, #TCB_SP_OFS]       ; Store user sp to osRtxInfo.thread.run.curr
@@ -414,11 +413,11 @@ osRtxContextRestore
                 BEQ     osRtxContextRestore1        ; No VFP
                 ISB                                 ; Only sync if we enabled VFP, otherwise we will context switch before next VFP instruction anyway
                 IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
-                VLDMIA  R3!, {D16-D31}
+                VLDMIA  R3!, {D16-D31}              ; Restore D16-D31
                 ENDIF
-                VLDMIA  R3!, {D0-D15}
+                VLDMIA  R3!, {D0-D15}               ; Restore D0-D15
                 LDR     R2, [R3]
-                VMSR    FPSCR, R2
+                VMSR    FPSCR, R2                   ; Restore FPSCR
                 ADD     R3, R3, #8
 
 osRtxContextRestore1

CMSIS/RTOS2/RTX/Source/GCC/irq_ca.S

@@ -361,93 +361,92 @@ osRtxContextSwitch:
 
                 // R0  = osRtxInfo.thread.run.curr
                 // R1  = osRtxInfo.thread.run.next
-                //  R12 = &osRtxInfo.thread.run
+                // R12 = &osRtxInfo.thread.run
 
-                CMP     R0, #0                     // Is osRtxInfo.thread.run.curr == 0
-                ADDEQ   SP, SP, #32                // Equal, curr deleted, adjust current SP
-                BEQ     osRtxContextRestore        // Restore context, run.curr = run.next;
+                CMP     R0, #0                      // Is osRtxInfo.thread.run.curr == 0
+                ADDEQ   SP, SP, #32                 // Equal, curr deleted, adjust current SP
+                BEQ     osRtxContextRestore         // Restore context, run.curr = run.next;
 
 osRtxContextSave:
                 SUB     SP, SP, #4
-                STM     SP, {SP}^                  // Save SP_usr to current stack
-                POP     {R3}                       // Pop SP_usr into R3
+                STM     SP, {SP}^                   // Save SP_usr to current stack
+                POP     {R3}                        // Pop SP_usr into R3
 
-                SUB     R3, R3, #64                // Adjust user sp to end of basic frame (R4)
-                STMIA   R3!, {R4-R11}              // Save R4-R11 to user
-                POP     {R4-R8}                    // Pop current R0-R12 into R4-R8
-                STMIA   R3!, {R4-R8}               // Store them to user stack
-                STM     R3, {LR}^                  // Store LR_usr directly
-                ADD     R3, R3, #4                 // Adjust user sp to PC
-                POP     {R4-R6}                    // Pop current LR, PC, CPSR
-                STMIA   R3!, {R5-R6}               // Restore user PC and CPSR
+                SUB     R3, R3, #64                 // Adjust user sp to end of basic frame (R4)
+                STMIA   R3!, {R4-R11}               // Save R4-R11 to user
+                POP     {R4-R8}                     // Pop current R0-R12 into R4-R8
+                STMIA   R3!, {R4-R8}                // Store them to user stack
+                STM     R3, {LR}^                   // Store LR_usr directly
+                ADD     R3, R3, #4                  // Adjust user sp to PC
+                POP     {R4-R6}                     // Pop current LR, PC, CPSR
+                STMIA   R3!, {R5-R6}                // Restore user PC and CPSR
 
-                SUB     R3, R3, #64                // Adjust user sp to R4
+                SUB     R3, R3, #64                 // Adjust user sp to R4
 
                 // Check if VFP state need to be saved
-                MRC     p15, 0, R2, c1, c0, 2      // VFP/NEON access enabled? (CPACR)
+                MRC     p15, 0, R2, c1, c0, 2       // VFP/NEON access enabled? (CPACR)
                 AND     R2, R2, #0x00F00000
                 CMP     R2, #0x00F00000
-                BNE     osRtxContextSave1          // Continue, no VFP
+                BNE     osRtxContextSave1           // Continue, no VFP
 
                 VMRS    R2, FPSCR
-                STMDB   R3!, {R2,R12}              // Push FPSCR, maintain 8-byte alignment
-                #if TARGET_FEATURE_EXTENSION_REGISTER_COUNT == 16
-                VSTMDB  R3!, {D0-D15}
-                LDRB    R2, [R0, #TCB_SP_FRAME]    // Record in TCB that VFP/D16 state is stacked
-                ORR     R2, R2, #2
-                STRB    R2, [R0, #TCB_SP_FRAME]
+                STMDB   R3!, {R2,R12}               // Push FPSCR, maintain 8-byte alignment
+
+                VSTMDB  R3!, {D0-D15}               // Save D0-D15
+                #if     __ARM_NEON == 1
+                VSTMDB  R3!, {D16-D31}              // Save D16-D31
                 #endif
-                #if TARGET_FEATURE_EXTENSION_REGISTER_COUNT == 32
-                VSTMDB  R3!, {D0-D15}
-                VSTMDB  R3!, {D16-D31}
-                LDRB    R2, [R0, #TCB_SP_FRAME]    // Record in TCB that NEON/D32 state is stacked
-                ORR     R2, R2, #4
-                STRB    R2, [R0, #TCB_SP_FRAME]
+                LDRB    R2, [R0, #TCB_SP_FRAME]
+                #if     __ARM_NEON == 1
+                ORR     R2, R2, #4                  // NEON state
+                #else
+                ORR     R2, R2, #2                  // VFP state
                 #endif
+                STRB    R2, [R0, #TCB_SP_FRAME]     // Record VFP/NEON state
 
 osRtxContextSave1:
-                STR     R3, [R0, #TCB_SP_OFS]      // Store user sp to osRtxInfo.thread.run.curr
+                STR     R3, [R0, #TCB_SP_OFS]       // Store user sp to osRtxInfo.thread.run.curr
 
 osRtxContextRestore:
-                STR     R1, [R12]                  // Store run.next to run.curr
-                LDR     R3, [R1, #TCB_SP_OFS]      // Load next osRtxThread_t.sp
-                LDRB    R2, [R1, #TCB_SP_FRAME]    // Load next osRtxThread_t.stack_frame
-
-                ANDS    R2, R2, #0x6               // Check stack frame for VFP context
-                MRC     p15, 0, R2, c1, c0, 2      // Read CPACR
-                ANDEQ   R2, R2, #0xFF0FFFFF        // Disable VFP/NEON access if incoming task does not have stacked VFP/NEON state
-                ORRNE   R2, R2, #0x00F00000        // Enable VFP/NEON access if incoming task does have stacked VFP/NEON state
-                MCR     p15, 0, R2, c1, c0, 2      // Write CPACR
-                BEQ     osRtxContextRestore1       // No VFP
-                ISB                                // Only sync if we enabled VFP, otherwise we will context switch before next VFP instruction anyway
-                #if TARGET_FEATURE_EXTENSION_REGISTER_COUNT == 32
-                VLDMIA  R3!, {D16-D31}
+                STR     R1, [R12]                   // Store run.next to run.curr
+                LDR     R3, [R1, #TCB_SP_OFS]       // Load next osRtxThread_t.sp
+                LDRB    R2, [R1, #TCB_SP_FRAME]     // Load next osRtxThread_t.stack_frame
+
+                ANDS    R2, R2, #0x6                // Check stack frame for VFP context
+                MRC     p15, 0, R2, c1, c0, 2       // Read CPACR
+                ANDEQ   R2, R2, #0xFF0FFFFF         // Disable VFP/NEON access if incoming task does not have stacked VFP/NEON state
+                ORRNE   R2, R2, #0x00F00000         // Enable VFP/NEON access if incoming task does have stacked VFP/NEON state
+                MCR     p15, 0, R2, c1, c0, 2       // Write CPACR
+                BEQ     osRtxContextRestore1        // No VFP
+                ISB                                 // Only sync if we enabled VFP, otherwise we will context switch before next VFP instruction anyway
+                #if     __ARM_NEON == 1
+                VLDMIA  R3!, {D16-D31}              // Restore D16-D31
                 #endif
-                VLDMIA  R3!, {D0-D15}
+                VLDMIA  R3!, {D0-D15}               // Restore D0-D15
                 LDR     R2, [R3]
-                VMSR    FPSCR, R2
+                VMSR    FPSCR, R2                   // Restore FPSCR
                 ADD     R3, R3, #8
 
 osRtxContextRestore1:
-                LDMIA   R3!, {R4-R11}              // Restore R4-R11
-                MOV     R12, R3                    // Move sp pointer to R12
-                ADD     R3, R3, #32                // Adjust sp
-                PUSH    {R3}                       // Push sp onto stack
-                LDMIA   SP, {SP}^                  // Restore SP_usr
-                ADD     SP, SP, #4                 // Adjust SP_svc
-                LDMIA   R12!, {R0-R3}              // Restore User R0-R3
-                LDR     LR, [R12, #12]             // Load SPSR into LR
-                MSR     SPSR_cxsf, LR              // Restore SPSR
-                ADD     R12, R12, #4               // Adjust pointer to LR
-                LDM     R12, {LR}^                 // Restore LR_usr directly into LR
-                LDR     LR, [R12, #4]              // Restore LR
-                LDR     R12, [R12, #-4]            // Restore R12
-
-                MOVS    PC, LR                     // Return from exception
+                LDMIA   R3!, {R4-R11}               // Restore R4-R11
+                MOV     R12, R3                     // Move sp pointer to R12
+                ADD     R3, R3, #32                 // Adjust sp
+                PUSH    {R3}                        // Push sp onto stack
+                LDMIA   SP, {SP}^                   // Restore SP_usr
+                ADD     SP, SP, #4                  // Adjust SP_svc
+                LDMIA   R12!, {R0-R3}               // Restore User R0-R3
+                LDR     LR, [R12, #12]              // Load SPSR into LR
+                MSR     SPSR_cxsf, LR               // Restore SPSR
+                ADD     R12, R12, #4                // Adjust pointer to LR
+                LDM     R12, {LR}^                  // Restore LR_usr directly into LR
+                LDR     LR, [R12, #4]               // Restore LR
+                LDR     R12, [R12, #-4]             // Restore R12
+
+                MOVS    PC, LR                      // Return from exception
 
 osRtxContextExit:
-                POP     {R0-R3, R12, LR}           // Restore stacked APCS registers
-                RFEFD   SP!                        // Return from exception
+                POP     {R0-R3, R12, LR}            // Restore stacked APCS registers
+                RFEFD   SP!                         // Return from exception
 
                 .fnend
                 .size    osRtxContextSwitch, .-osRtxContextSwitch

CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl.s

@@ -1,4 +1,4 @@
                 NAME    irq_armv8mbl.s
-#define __DOMAIN_NS 0
+                #define __DOMAIN_NS 0
                 INCLUDE irq_armv8mbl_common.s
                 END

CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl_common.s

@@ -24,8 +24,8 @@
 ; */
 
 
-#ifndef __DOMAIN_NS 
-#define __DOMAIN_NS 0
+#ifndef __DOMAIN_NS
+#define __DOMAIN_NS      0
 #endif
 
 I_T_RUN_OFS     EQU      20                     ; osRtxInfo.thread.run offset
@@ -43,8 +43,7 @@ TCB_TZM_OFS     EQU      64                     ; TCB.tz_memory offset
 irqRtxLib       DCB      0                      ; Non weak library reference
 
 
-                SECTION   .text:CODE:NOROOT(2)
-
+                SECTION  .text:CODE:NOROOT(2)
                 THUMB
 
 
@@ -52,10 +51,10 @@ SVC_Handler
                 EXPORT   SVC_Handler
                 IMPORT   osRtxUserSVC
                 IMPORT   osRtxInfo
-#if (__DOMAIN_NS == 1)
+                #if     (__DOMAIN_NS == 1)
                 IMPORT   TZ_LoadContext_S
                 IMPORT   TZ_StoreContext_S
-#endif
+                #endif
 
                 MOV      R0,LR
                 LSRS     R0,R0,#3               ; Determine return stack from EXC_RETURN bit 2
@@ -85,7 +84,7 @@ SVC_Context
                 CBZ      R1,SVC_ContextSwitch   ; Branch if running thread is deleted
 
 SVC_ContextSave
-#if (__DOMAIN_NS == 1)
+                #if     (__DOMAIN_NS == 1)
                 LDR      R0,[R1,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
                 CBZ      R0,SVC_ContextSave1    ; Branch if there is no secure context
                 PUSH     {R1,R2,R3,R7}          ; Save registers
@@ -93,7 +92,7 @@ SVC_ContextSave
                 BL       TZ_StoreContext_S      ; Store secure context
                 MOV      LR,R7                  ; Set EXC_RETURN
                 POP      {R1,R2,R3,R7}          ; Restore registers
-#endif
+                #endif
 
 SVC_ContextSave1
                 MRS      R0,PSP                 ; Get PSP
@@ -116,13 +115,13 @@ SVC_ContextSwitch
                 STR      R2,[R3]                ; osRtxInfo.thread.run: curr = next
 
 SVC_ContextRestore
-#if (__DOMAIN_NS == 1)
+                #if     (__DOMAIN_NS == 1)
                 LDR      R0,[R2,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
                 CBZ      R0,SVC_ContextRestore1 ; Branch if there is no secure context
                 PUSH     {R2,R3}                ; Save registers
                 BL       TZ_LoadContext_S       ; Load secure context
                 POP      {R2,R3}                ; Restore registers
-#endif
+                #endif
 
 SVC_ContextRestore1
                 MOV      R1,R2
@@ -133,16 +132,16 @@ SVC_ContextRestore1
                 ORRS     R0,R1
                 MOV      LR,R0                  ; Set EXC_RETURN
 
-#if (__DOMAIN_NS == 1)
+                #if     (__DOMAIN_NS == 1)
                 LSLS     R0,R0,#25              ; Check domain of interrupted thread
                 BPL      SVC_ContextRestore2    ; Branch if non-secure
                 LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
                 MSR      PSP,R0                 ; Set PSP
                 BX       LR                     ; Exit from handler
-#else
+                #else
                 LDR      R0,[R2,#TCB_SM_OFS]    ; Load stack memory base
                 MSR      PSPLIM,R0              ; Set PSPLIM
-#endif
+                #endif
 
 SVC_ContextRestore2
                 LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
@@ -208,10 +207,10 @@ SysTick_Handler
 Sys_Context
                 EXPORT   Sys_Context
                 IMPORT   osRtxInfo
-#if (__DOMAIN_NS == 1)
+                #if     (__DOMAIN_NS == 1)
                 IMPORT   TZ_LoadContext_S
                 IMPORT   TZ_StoreContext_S
-#endif
+                #endif
 
                 LDR      R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
                 LDM      R3!,{R1,R2}            ; Load osRtxInfo.thread.run: curr & next
@@ -219,7 +218,7 @@ Sys_Context
                 BEQ      Sys_ContextExit        ; Branch when threads are the same
 
 Sys_ContextSave
-#if (__DOMAIN_NS == 1)
+                #if     (__DOMAIN_NS == 1)
                 LDR      R0,[R1,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
                 CBZ      R0,Sys_ContextSave1    ; Branch if there is no secure context
                 PUSH     {R1,R2,R3,R7}          ; Save registers
@@ -232,7 +231,7 @@ Sys_ContextSave
                 MRS      R0,PSP                 ; Get PSP
                 STR      R0,[R1,#TCB_SP_OFS]    ; Store SP
                 B        Sys_ContextSave2
-#endif
+                #endif
 
 Sys_ContextSave1
                 MRS      R0,PSP                 ; Get PSP
@@ -255,13 +254,13 @@ Sys_ContextSwitch
                 STR      R2,[R3]                ; osRtxInfo.run: curr = next
 
 Sys_ContextRestore
-#if (__DOMAIN_NS == 1)
+                #if     (__DOMAIN_NS == 1)
                 LDR      R0,[R2,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
                 CBZ      R0,Sys_ContextRestore1 ; Branch if there is no secure context
                 PUSH     {R2,R3}                ; Save registers
                 BL       TZ_LoadContext_S       ; Load secure context
                 POP      {R2,R3}                ; Restore registers
-#endif
+                #endif
 
 Sys_ContextRestore1
                 MOV      R1,R2
@@ -272,16 +271,16 @@ Sys_ContextRestore1
                 ORRS     R0,R1
                 MOV      LR,R0                  ; Set EXC_RETURN
 
-#if (__DOMAIN_NS == 1)
+                #if     (__DOMAIN_NS == 1)
                 LSLS     R0,R0,#25              ; Check domain of interrupted thread
                 BPL      Sys_ContextRestore2    ; Branch if non-secure
                 LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
                 MSR      PSP,R0                 ; Set PSP
                 BX       LR                     ; Exit from handler
-#else
+                #else
                 LDR      R0,[R2,#TCB_SM_OFS]    ; Load stack memory base
                 MSR      PSPLIM,R0              ; Set PSPLIM
-#endif
+                #endif
 
 Sys_ContextRestore2
                 LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP

CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl_ns.s

@@ -1,4 +1,4 @@
                 NAME    irq_armv8mbl_ns.s
-#define __DOMAIN_NS 1
+                #define __DOMAIN_NS 1
                 INCLUDE irq_armv8mbl_common.s
                 END

CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s

@@ -1,4 +1,4 @@
                 NAME    irq_armv8mml.s
-#define __DOMAIN_NS 0
+                #define __DOMAIN_NS 0
                 INCLUDE irq_armv8mml_common.s
                 END

CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_common.s

@@ -24,9 +24,8 @@
 ; */
 
 
-
 #ifndef __DOMAIN_NS
-#define __DOMAIN_NS 0
+#define __DOMAIN_NS      0
 #endif
 
 #ifdef __ARMVFP__
@@ -45,12 +44,12 @@ TCB_TZM_OFS     EQU      64                     ; TCB.tz_memory offset
                 PRESERVE8
 
 
-                SECTION     .rodata:DATA:NOROOT(2)
+                SECTION  .rodata:DATA:NOROOT(2)
                 EXPORT   irqRtxLib
 irqRtxLib       DCB      0                      ; Non weak library reference
 
 
-                SECTION     .text:CODE:NOROOT(2)
+                SECTION  .text:CODE:NOROOT(2)
                 THUMB
 
 
@@ -58,10 +57,10 @@ SVC_Handler
                 EXPORT   SVC_Handler
                 IMPORT   osRtxUserSVC
                 IMPORT   osRtxInfo
-#if (__DOMAIN_NS == 1)
+                #if     (__DOMAIN_NS == 1)
                 IMPORT   TZ_LoadContext_S
                 IMPORT   TZ_StoreContext_S
-#endif
+                #endif
 
                 TST      LR,#0x04               ; Determine return stack from EXC_RETURN bit 2
                 ITE      EQ
@@ -86,7 +85,7 @@ SVC_Context
                 IT       EQ
                 BXEQ     LR                     ; Exit when threads are the same
 
-#if (__FPU_USED == 1)
+                #if     (__FPU_USED == 1)
                 CBNZ     R1,SVC_ContextSave     ; Branch if running thread is not deleted
                 TST      LR,#0x10               ; Check if extended stack frame
                 BNE      SVC_ContextSwitch
@@ -95,27 +94,27 @@ SVC_Context
                 BIC      R0,R0,#1               ; Clear LSPACT (Lazy state)
                 STR      R0,[R1]                ; Store FPCCR
                 B        SVC_ContextSwitch
-#else
+                #else
                 CBZ      R1,SVC_ContextSwitch   ; Branch if running thread is deleted
-#endif
+                #endif
 
 SVC_ContextSave
-#if (__DOMAIN_NS == 1)
+                #if     (__DOMAIN_NS == 1)
                 LDR      R0,[R1,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
                 CBZ      R0,SVC_ContextSave1    ; Branch if there is no secure context
                 PUSH     {R1,R2,R3,LR}          ; Save registers and EXC_RETURN
                 BL       TZ_StoreContext_S      ; Store secure context
                 POP      {R1,R2,R3,LR}          ; Restore registers and EXC_RETURN
-#endif
+                #endif
 
 SVC_ContextSave1
                 MRS      R0,PSP                 ; Get PSP
                 STMDB    R0!,{R4-R11}           ; Save R4..R11
-#if (__FPU_USED == 1)
+                #if     (__FPU_USED == 1)
                 TST      LR,#0x10               ; Check if extended stack frame
                 IT       EQ
                 VSTMDBEQ R0!,{S16-S31}          ;  Save VFP S16.S31
-#endif
+                #endif
 
 SVC_ContextSave2
                 STR      R0,[R1,#TCB_SP_OFS]    ; Store SP
@@ -125,13 +124,13 @@ SVC_ContextSwitch
                 STR      R2,[R3]                ; osRtxInfo.thread.run: curr = next
 
 SVC_ContextRestore
-#if (__DOMAIN_NS == 1)
+                #if     (__DOMAIN_NS == 1)
                 LDR      R0,[R2,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
                 CBZ      R0,SVC_ContextRestore1 ; Branch if there is no secure context
                 PUSH     {R2,R3}                ; Save registers
                 BL       TZ_LoadContext_S       ; Load secure context
                 POP      {R2,R3}                ; Restore registers
-#endif
+                #endif
 
 SVC_ContextRestore1
                 LDR      R0,[R2,#TCB_SM_OFS]    ; Load stack memory base
@@ -140,16 +139,16 @@ SVC_ContextRestore1
                 LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
                 ORR      LR,R1,#0xFFFFFF00      ; Set EXC_RETURN
 
-#if (__DOMAIN_NS == 1)
+                #if     (__DOMAIN_NS == 1)
                 TST      LR,#0x40               ; Check domain of interrupted thread
                 BNE      SVC_ContextRestore2    ; Branch if secure
-#endif
+                #endif
 
-#if (__FPU_USED == 1)
+                #if     (__FPU_USED == 1)
                 TST      LR,#0x10               ; Check if extended stack frame
                 IT       EQ
                 VLDMIAEQ R0!,{S16-S31}          ;  Restore VFP S16..S31
-#endif
+                #endif
                 LDMIA    R0!,{R4-R11}           ; Restore R4..R11
 
 SVC_ContextRestore2
@@ -198,10 +197,10 @@ SysTick_Handler
 Sys_Context
                 EXPORT   Sys_Context
                 IMPORT   osRtxInfo
-#if (__DOMAIN_NS == 1)
+                #if     (__DOMAIN_NS == 1)
                 IMPORT   TZ_LoadContext_S
                 IMPORT   TZ_StoreContext_S
-#endif
+                #endif
 
                 LDR      R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
                 LDM      R3,{R1,R2}             ; Load osRtxInfo.thread.run: curr & next
@@ -210,7 +209,7 @@ Sys_Context
                 BXEQ     LR                     ; Exit when threads are the same
 
 Sys_ContextSave
-#if (__DOMAIN_NS == 1)
+                #if     (__DOMAIN_NS == 1)
                 LDR      R0,[R1,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
                 CBZ      R0,Sys_ContextSave1    ; Branch if there is no secure context
                 PUSH     {R1,R2,R3,LR}          ; Save registers and EXC_RETURN
@@ -220,16 +219,16 @@ Sys_ContextSave
                 IT       NE
                 MRSNE    R0,PSP                 ; Get PSP
                 BNE      Sys_ContextSave2       ; Branch if secure
-#endif
+                #endif
 
 Sys_ContextSave1
                 MRS      R0,PSP                 ; Get PSP
                 STMDB    R0!,{R4-R11}           ; Save R4..R11
-#if (__FPU_USED == 1)
+                #if     (__FPU_USED == 1)
                 TST      LR,#0x10               ; Check if extended stack frame
                 IT       EQ
                 VSTMDBEQ R0!,{S16-S31}          ;  Save VFP S16.S31
-#endif
+                #endif
 
 Sys_ContextSave2
                 STR      R0,[R1,#TCB_SP_OFS]    ; Store SP
@@ -239,13 +238,13 @@ Sys_ContextSwitch
                 STR      R2,[R3]                ; osRtxInfo.run: curr = next
 
 Sys_ContextRestore
-#if (__DOMAIN_NS == 1)
+                #if     (__DOMAIN_NS == 1)
                 LDR      R0,[R2,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
                 CBZ      R0,Sys_ContextRestore1 ; Branch if there is no secure context
                 PUSH     {R2,R3}                ; Save registers
                 BL       TZ_LoadContext_S       ; Load secure context
                 POP      {R2,R3}                ; Restore registers
-#endif
+                #endif
 
 Sys_ContextRestore1
                 LDR      R0,[R2,#TCB_SM_OFS]    ; Load stack memory base
@@ -254,16 +253,16 @@ Sys_ContextRestore1
                 LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
                 ORR      LR,R1,#0xFFFFFF00      ; Set EXC_RETURN
 
-#if (__DOMAIN_NS == 1)
+                #if     (__DOMAIN_NS == 1)
                 TST      LR,#0x40               ; Check domain of interrupted thread
                 BNE      Sys_ContextRestore2    ; Branch if secure
-#endif
+                #endif
 
-#if (__FPU_USED == 1)
+                #if     (__FPU_USED == 1)
                 TST      LR,#0x10               ; Check if extended stack frame
                 IT       EQ
                 VLDMIAEQ R0!,{S16-S31}          ;  Restore VFP S16..S31
-#endif
+                #endif
                 LDMIA    R0!,{R4-R11}           ; Restore R4..R11
 
 Sys_ContextRestore2

CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_ns.s

@@ -1,4 +1,4 @@
                 NAME    irq_armv8mml_ns.s
-#define __DOMAIN_NS 1
+                #define __DOMAIN_NS 1
                 INCLUDE irq_armv8mml_common.s
                 END

CMSIS/RTOS2/RTX/Source/IAR/irq_ca.s

@@ -369,19 +369,18 @@ osRtxContextSave
 
                 VMRS    R2, FPSCR
                 STMDB   R3!, {R2,R12}               ; Push FPSCR, maintain 8-byte alignment
-#if (TARGET_FEATURE_EXTENSION_REGISTER_COUNT == 16)
-                VSTMDB  R3!, {D0-D15}
-                LDRB    R2, [R0, #TCB_SP_FRAME]     ; Record in TCB that VFP/D16 state is stacked
-                ORR     R2, R2, #2
-                STRB    R2, [R0, #TCB_SP_FRAME]
-#endif
-#if (TARGET_FEATURE_EXTENSION_REGISTER_COUNT == 32)
-                VSTMDB  R3!, {D0-D15}
-                VSTMDB  R3!, {D16-D31}
-                LDRB    R2, [R0, #TCB_SP_FRAME]     ; Record in TCB that NEON/D32 state is stacked
-                ORR     R2, R2, #4
-                STRB    R2, [R0, #TCB_SP_FRAME]
-#endif
+
+                VSTMDB  R3!, {D0-D15}               ; Save D0-D15
+                #ifdef  __ARM_ADVANCED_SIMD__
+                VSTMDB  R3!, {D16-D31}              ; Save D16-D31
+                #endif
+                LDRB    R2, [R0, #TCB_SP_FRAME]
+                #ifdef  __ARM_ADVANCED_SIMD__
+                ORR     R2, R2, #4                  ; NEON state
+                #else
+                ORR     R2, R2, #2                  ; VFP state
+                #endif
+                STRB    R2, [R0, #TCB_SP_FRAME]     ; Record VFP/NEON state
 
 osRtxContextSave1
                 STR     R3, [R0, #TCB_SP_OFS]       ; Store user sp to osRtxInfo.thread.run.curr
@@ -398,12 +397,12 @@ osRtxContextRestore
                 MCR     p15, 0, R2, c1, c0, 2       ; Write CPACR
                 BEQ     osRtxContextRestore1        ; No VFP
                 ISB                                 ; Only sync if we enabled VFP, otherwise we will context switch before next VFP instruction anyway
-#if (TARGET_FEATURE_EXTENSION_REGISTER_COUNT == 32)
-                VLDMIA  R3!, {D16-D31}
-#endif
-                VLDMIA  R3!, {D0-D15}
+                #ifdef  __ARM_ADVANCED_SIMD__
+                VLDMIA  R3!, {D16-D31}              ; Restore D16-D31
+                #endif
+                VLDMIA  R3!, {D0-D15}               ; Restore D0-D15
                 LDR     R2, [R3]
-                VMSR    FPSCR, R2
+                VMSR    FPSCR, R2                   ; Restore FPSCR
                 ADD     R3, R3, #8
 
 osRtxContextRestore1

Device/ARM/ARMCM0plus/Include/ARMCM0plus_MPU.h

@@ -0,0 +1,275 @@
+/**************************************************************************//**
+ * @file     ARMCM0plus.h
+ * @brief    CMSIS Core Peripheral Access Layer Header File for
+ *           ARMCM0plus Device Series
+ * @version  V5.00
+ * @date     07. September 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef ARMCM0plus_H
+#define ARMCM0plus_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* -------------------------  Interrupt Number Definition  ------------------------ */
+
+typedef enum IRQn
+{
+/* -------------------  Cortex-M0+ Processor Exceptions Numbers  ------------------ */
+  NonMaskableInt_IRQn           = -14,      /*  2 Non Maskable Interrupt */
+  HardFault_IRQn                = -13,      /*  3 HardFault Interrupt */
+
+
+
+  SVCall_IRQn                   =  -5,      /* 11 SV Call Interrupt */
+
+  PendSV_IRQn                   =  -2,      /* 14 Pend SV Interrupt */
+  SysTick_IRQn                  =  -1,      /* 15 System Tick Interrupt */
+
+/* ----------------------  ARMCM0 Specific Interrupt Numbers  --------------------- */
+  WDT_IRQn                      =   0,      /* Watchdog Timer Interrupt */
+  RTC_IRQn                      =   1,      /* Real Time Clock Interrupt */
+  TIM0_IRQn                     =   2,      /* Timer0 / Timer1 Interrupt */
+  TIM2_IRQn                     =   3,      /* Timer2 / Timer3 Interrupt */
+  MCIA_IRQn                     =   4,      /* MCIa Interrupt */
+  MCIB_IRQn                     =   5,      /* MCIb Interrupt */
+  UART0_IRQn                    =   6,      /* UART0 Interrupt */
+  UART1_IRQn                    =   7,      /* UART1 Interrupt */
+  UART2_IRQn                    =   8,      /* UART2 Interrupt */
+  UART4_IRQn                    =   9,      /* UART4 Interrupt */
+  AACI_IRQn                     =  10,      /* AACI / AC97 Interrupt */
+  CLCD_IRQn                     =  11,      /* CLCD Combined Interrupt */
+  ENET_IRQn                     =  12,      /* Ethernet Interrupt */
+  USBDC_IRQn                    =  13,      /* USB Device Interrupt */
+  USBHC_IRQn                    =  14,      /* USB Host Controller Interrupt */
+  CHLCD_IRQn                    =  15,      /* Character LCD Interrupt */
+  FLEXRAY_IRQn                  =  16,      /* Flexray Interrupt */
+  CAN_IRQn                      =  17,      /* CAN Interrupt */
+  LIN_IRQn                      =  18,      /* LIN Interrupt */
+  I2C_IRQn                      =  19,      /* I2C ADC/DAC Interrupt */
+  CPU_CLCD_IRQn                 =  28,      /* CPU CLCD Combined Interrupt */
+  UART3_IRQn                    =  30,      /* UART3 Interrupt */
+  SPI_IRQn                      =  31       /* SPI Touchscreen Interrupt */
+} IRQn_Type;
+
+
+/* ================================================================================ */
+/* ================      Processor and Core Peripheral Section     ================ */
+/* ================================================================================ */
+
+/* -------  Start of section using anonymous unions and disabling warnings  ------- */
+#if   defined (__CC_ARM)
+  #pragma push
+  #pragma anon_unions
+#elif defined (__ICCARM__)
+  #pragma language=extended
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wc11-extensions"
+  #pragma clang diagnostic ignored "-Wreserved-id-macro"
+#elif defined (__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+  /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+  #pragma warning 586
+#elif defined (__CSMC__)
+  /* anonymous unions are enabled by default */
+#else
+  #warning Not supported compiler type
+#endif
+
+
+/* --------  Configuration of the Cortex-M0+ Processor and Core Peripherals  ------ */
+#define __CM0PLUS_REV             0x0000U   /* Core revision r0p0 */
+#define __MPU_PRESENT             1U        /* MPU present or not */
+#define __VTOR_PRESENT            0U        /* VTOR present or not */
+#define __NVIC_PRIO_BITS          2U        /* Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */
+
+#include "core_cm0plus.h"                   /* Processor and core peripherals */
+#include "system_ARMCM0plus.h"              /* System Header */
+
+
+/* ================================================================================ */
+/* ================       Device Specific Peripheral Section       ================ */
+/* ================================================================================ */
+
+
+/* ================================================================================ */
+/* ================            CPU FPGA System (CPU_SYS)           ================ */
+/* ================================================================================ */
+typedef struct
+{
+  __IM  uint32_t ID;              /* Offset: 0x000 (R/ )  Board and FPGA Identifier */
+  __IOM uint32_t MEMCFG;          /* Offset: 0x004 (R/W)  Remap and Alias Memory Control */
+  __IM  uint32_t SW;              /* Offset: 0x008 (R/ )  Switch States */
+  __IOM uint32_t LED;             /* Offset: 0x00C (R/W)  LED Output States */
+  __IM  uint32_t TS;              /* Offset: 0x010 (R/ )  Touchscreen Register */
+  __IOM uint32_t CTRL1;           /* Offset: 0x014 (R/W)  Misc Control Functions */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t CLKCFG;          /* Offset: 0x020 (R/W)  System Clock Configuration */
+  __IOM uint32_t WSCFG;           /* Offset: 0x024 (R/W)  Flash Waitstate Configuration */
+  __IOM uint32_t CPUCFG;          /* Offset: 0x028 (R/W)  Processor Configuration */
+        uint32_t RESERVED1[3U];
+  __IOM uint32_t BASE;            /* Offset: 0x038 (R/W)  ROM Table base Address */
+  __IOM uint32_t ID2;             /* Offset: 0x03C (R/W)  Secondary Identification Register */
+} ARM_CPU_SYS_TypeDef;
+
+
+/* ================================================================================ */
+/* ================            DUT FPGA System (DUT_SYS)           ================ */
+/* ================================================================================ */
+typedef struct
+{
+  __IM  uint32_t ID;              /* Offset: 0x000 (R/ )  Board and FPGA Identifier */
+  __IOM uint32_t PERCFG;          /* Offset: 0x004 (R/W)  Peripheral Control Signals */
+  __IM  uint32_t SW;              /* Offset: 0x008 (R/ )  Switch States */
+  __IOM uint32_t LED;             /* Offset: 0x00C (R/W)  LED Output States */
+  __IOM uint32_t SEG7;            /* Offset: 0x010 (R/W)  7-segment LED Output States */
+  __IM  uint32_t CNT25MHz;        /* Offset: 0x014 (R/ )  Freerunning counter incrementing at 25MHz */
+  __IM  uint32_t CNT100Hz;        /* Offset: 0x018 (R/ )  Freerunning counter incrementing at 100Hz */
+} ARM_DUT_SYS_TypeDef;
+
+
+/* ================================================================================ */
+/* ================                   Timer (TIM)                  ================ */
+/* ================================================================================ */
+typedef struct
+{
+  __IOM uint32_t Timer1Load;      /* Offset: 0x000 (R/W)  Timer 1 Load */
+  __IM  uint32_t Timer1Value;     /* Offset: 0x004 (R/ )  Timer 1 Counter Current Value */
+  __IOM uint32_t Timer1Control;   /* Offset: 0x008 (R/W)  Timer 1 Control */
+  __OM  uint32_t Timer1IntClr;    /* Offset: 0x00C ( /W)  Timer 1 Interrupt Clear */
+  __IM  uint32_t Timer1RIS;       /* Offset: 0x010 (R/ )  Timer 1 Raw Interrupt Status */
+  __IM  uint32_t Timer1MIS;       /* Offset: 0x014 (R/ )  Timer 1 Masked Interrupt Status */
+  __IOM uint32_t Timer1BGLoad;    /* Offset: 0x018 (R/W)  Background Load Register */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t Timer2Load;      /* Offset: 0x020 (R/W)  Timer 2 Load */
+  __IM  uint32_t Timer2Value;     /* Offset: 0x024 (R/ )  Timer 2 Counter Current Value */
+  __IOM uint32_t Timer2Control;   /* Offset: 0x028 (R/W)  Timer 2 Control */
+  __OM  uint32_t Timer2IntClr;    /* Offset: 0x02C ( /W)  Timer 2 Interrupt Clear */
+  __IM  uint32_t Timer2RIS;       /* Offset: 0x030 (R/ )  Timer 2 Raw Interrupt Status */
+  __IM  uint32_t Timer2MIS;       /* Offset: 0x034 (R/ )  Timer 2 Masked Interrupt Status */
+  __IOM uint32_t Timer2BGLoad;    /* Offset: 0x038 (R/W)  Background Load Register */
+} ARM_TIM_TypeDef;
+
+
+/* ================================================================================ */
+/* ============== Universal Asyncronous Receiver / Transmitter (UART) ============= */
+/* ================================================================================ */
+typedef struct
+{
+  __IOM uint32_t DR;              /* Offset: 0x000 (R/W)  Data */
+  union {
+  __IM  uint32_t RSR;             /* Offset: 0x000 (R/ )  Receive Status */
+  __OM  uint32_t ECR;             /* Offset: 0x000 ( /W)  Error Clear */
+  };
+        uint32_t RESERVED0[4U];
+  __IOM uint32_t FR;              /* Offset: 0x018 (R/W)  Flags */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t ILPR;            /* Offset: 0x020 (R/W)  IrDA Low-power Counter */
+  __IOM uint32_t IBRD;            /* Offset: 0x024 (R/W)  Interger Baud Rate */
+  __IOM uint32_t FBRD;            /* Offset: 0x028 (R/W)  Fractional Baud Rate */
+  __IOM uint32_t LCR_H;           /* Offset: 0x02C (R/W)  Line Control */
+  __IOM uint32_t CR;              /* Offset: 0x030 (R/W)  Control */
+  __IOM uint32_t IFLS;            /* Offset: 0x034 (R/W)  Interrupt FIFO Level Select */
+  __IOM uint32_t IMSC;            /* Offset: 0x038 (R/W)  Interrupt Mask Set / Clear */
+  __IOM uint32_t RIS;             /* Offset: 0x03C (R/W)  Raw Interrupt Status */
+  __IOM uint32_t MIS;             /* Offset: 0x040 (R/W)  Masked Interrupt Status */
+  __OM  uint32_t ICR;             /* Offset: 0x044 ( /W)  Interrupt Clear */
+  __IOM uint32_t DMACR;           /* Offset: 0x048 (R/W)  DMA Control */
+} ARM_UART_TypeDef;
+
+
+/* --------  End of section using anonymous unions and disabling warnings  -------- */
+#if   defined (__CC_ARM)
+  #pragma pop
+#elif defined (__ICCARM__)
+  /* leave anonymous unions enabled */
+#elif (__ARMCC_VERSION >= 6010050)
+  #pragma clang diagnostic pop
+#elif defined (__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+  /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+  #pragma warning restore
+#elif defined (__CSMC__)
+  /* anonymous unions are enabled by default */
+#else
+  #warning Not supported compiler type
+#endif
+
+
+
+
+/* ================================================================================ */
+/* ================              Peripheral memory map             ================ */
+/* ================================================================================ */
+/* --------------------------  CPU FPGA memory map  ------------------------------- */
+#define ARM_FLASH_BASE            (0x00000000UL)
+#define ARM_RAM_BASE              (0x20000000UL)
+#define ARM_RAM_FPGA_BASE         (0x1EFF0000UL)
+#define ARM_CPU_CFG_BASE          (0xDFFF0000UL)
+
+#define ARM_CPU_SYS_BASE          (ARM_CPU_CFG_BASE  + 0x00000UL)
+#define ARM_UART3_BASE            (ARM_CPU_CFG_BASE  + 0x05000UL)
+
+/* --------------------------  DUT FPGA memory map  ------------------------------- */
+#define ARM_APB_BASE              (0x40000000UL)
+#define ARM_AHB_BASE              (0x4FF00000UL)
+#define ARM_DMC_BASE              (0x60000000UL)
+#define ARM_SMC_BASE              (0xA0000000UL)
+
+#define ARM_TIM0_BASE             (ARM_APB_BASE      + 0x02000UL)
+#define ARM_TIM2_BASE             (ARM_APB_BASE      + 0x03000UL)
+#define ARM_DUT_SYS_BASE          (ARM_APB_BASE      + 0x04000UL)
+#define ARM_UART0_BASE            (ARM_APB_BASE      + 0x06000UL)
+#define ARM_UART1_BASE            (ARM_APB_BASE      + 0x07000UL)
+#define ARM_UART2_BASE            (ARM_APB_BASE      + 0x08000UL)
+#define ARM_UART4_BASE            (ARM_APB_BASE      + 0x09000UL)
+
+
+/* ================================================================================ */
+/* ================             Peripheral declaration             ================ */
+/* ================================================================================ */
+/* --------------------------  CPU FPGA Peripherals  ------------------------------ */
+#define ARM_CPU_SYS               ((ARM_CPU_SYS_TypeDef *)  ARM_CPU_SYS_BASE)
+#define ARM_UART3                 ((   ARM_UART_TypeDef *)    ARM_UART3_BASE)
+
+/* --------------------------  DUT FPGA Peripherals  ------------------------------ */
+#define ARM_DUT_SYS               ((ARM_DUT_SYS_TypeDef *)  ARM_DUT_SYS_BASE)
+#define ARM_TIM0                  ((    ARM_TIM_TypeDef *)     ARM_TIM0_BASE)
+#define ARM_TIM2                  ((    ARM_TIM_TypeDef *)     ARM_TIM2_BASE)
+#define ARM_UART0                 ((   ARM_UART_TypeDef *)    ARM_UART0_BASE)
+#define ARM_UART1                 ((   ARM_UART_TypeDef *)    ARM_UART1_BASE)
+#define ARM_UART2                 ((   ARM_UART_TypeDef *)    ARM_UART2_BASE)
+#define ARM_UART4                 ((   ARM_UART_TypeDef *)    ARM_UART4_BASE)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* ARMCM0plus_H */