Core(A): Fixed pedantic GCC warnings.

CMSIS/Core_A/Include/cmsis_cp15.h

@@ -119,7 +119,7 @@ __STATIC_FORCEINLINE uint32_t __get_ISR(void)
 /** \brief  Get CBAR
     \return               Configuration Base Address register value
  */
-__STATIC_FORCEINLINE uint32_t __get_CBAR()
+__STATIC_FORCEINLINE uint32_t __get_CBAR(void)
 {
   uint32_t result;
 //   __ASM volatile("MRC p15, 4, %0, c15, c0, 0" : "=r"(result) : : "memory");
@@ -133,7 +133,7 @@ __STATIC_FORCEINLINE uint32_t __get_CBAR()
 
     \return               Translation Table Base Register 0 value
  */
-__STATIC_FORCEINLINE uint32_t __get_TTBR0()
+__STATIC_FORCEINLINE uint32_t __get_TTBR0(void)
 {
   uint32_t result;
 //   __ASM volatile("MRC p15, 0, %0, c2, c0, 0" : "=r"(result) : : "memory");
@@ -159,7 +159,7 @@ __STATIC_FORCEINLINE void __set_TTBR0(uint32_t ttbr0)
 
     \return               Domain Access Control Register value
  */
-__STATIC_FORCEINLINE uint32_t __get_DACR()
+__STATIC_FORCEINLINE uint32_t __get_DACR(void)
 {
   uint32_t result;
 //   __ASM volatile("MRC p15, 0, %0, c3, c0, 0" : "=r"(result) : : "memory");
@@ -194,7 +194,7 @@ __STATIC_FORCEINLINE void __set_SCTLR(uint32_t sctlr)
 /** \brief  Get SCTLR
     \return               System Control Register value
  */
-__STATIC_FORCEINLINE uint32_t __get_SCTLR()
+__STATIC_FORCEINLINE uint32_t __get_SCTLR(void)
 {
   uint32_t result;
 //   __ASM volatile("MRC p15, 0, %0, c1, c0, 0" : "=r"(result) : : "memory");
@@ -284,7 +284,7 @@ __STATIC_FORCEINLINE void __set_CNTFRQ(uint32_t value)
 
     \return               CNTFRQ Register value
  */
-__STATIC_FORCEINLINE uint32_t __get_CNTFRQ()
+__STATIC_FORCEINLINE uint32_t __get_CNTFRQ(void)
 {
   uint32_t result;
   // __ASM volatile("MRC p15, 0, %0, c14, c0, 0" : "=r"(result) : : "memory");
@@ -310,7 +310,7 @@ __STATIC_FORCEINLINE void __set_CNTP_TVAL(uint32_t value)
 
     \return               CNTP_TVAL Register value
  */
-__STATIC_FORCEINLINE uint32_t __get_CNTP_TVAL()
+__STATIC_FORCEINLINE uint32_t __get_CNTP_TVAL(void)
 {
   uint32_t result;
   // __ASM volatile("MRC p15, 0, %0, c14, c2, 0" : "=r"(result) : : "memory");
@@ -333,7 +333,7 @@ __STATIC_FORCEINLINE void __set_CNTP_CTL(uint32_t value)
 /** \brief  Get CNTP_CTL register
     \return               CNTP_CTL Register value
  */
-__STATIC_FORCEINLINE uint32_t __get_CNTP_CTL()
+__STATIC_FORCEINLINE uint32_t __get_CNTP_CTL(void)
 {
   uint32_t result;
   // __ASM volatile("MRC p15, 0, %0, c14, c2, 1" : "=r"(result) : : "memory");
@@ -406,7 +406,8 @@ __STATIC_FORCEINLINE void __set_DCCIMVAC(uint32_t value)
 
 /** \brief  Set CCSIDR
  */
-__STATIC_FORCEINLINE void __set_CCSIDR(uint32_t value) {
+__STATIC_FORCEINLINE void __set_CCSIDR(uint32_t value)
+{
 //  __ASM volatile("MCR p15, 2, %0, c0, c0, 0" : : "r"(value) : "memory");
   __set_CP(15, 2, value, 0, 0, 0);
 }
@@ -414,7 +415,8 @@ __STATIC_FORCEINLINE void __set_CCSIDR(uint32_t value) {
 /** \brief  Get CCSIDR
     \return CCSIDR Register value
  */
-__STATIC_FORCEINLINE uint32_t __get_CCSIDR() {
+__STATIC_FORCEINLINE uint32_t __get_CCSIDR(void)
+{
   uint32_t result;
 //  __ASM volatile("MRC p15, 1, %0, c0, c0, 0" : "=r"(result) : : "memory");
   __get_CP(15, 1, result, 0, 0, 0);
@@ -424,7 +426,8 @@ __STATIC_FORCEINLINE uint32_t __get_CCSIDR() {
 /** \brief  Get CLIDR
     \return CLIDR Register value
  */
-__STATIC_FORCEINLINE uint32_t __get_CLIDR() {
+__STATIC_FORCEINLINE uint32_t __get_CLIDR(void)
+{
   uint32_t result;
 //  __ASM volatile("MRC p15, 1, %0, c0, c0, 1" : "=r"(result) : : "memory");
   __get_CP(15, 1, result, 0, 0, 1);

CMSIS/Core_A/Include/cmsis_gcc.h

@@ -387,6 +387,7 @@ __STATIC_FORCEINLINE  void __CLREX(void)
   \return             Saturated value
  */
 #define __SSAT(ARG1,ARG2) \
+__extension__ \
 ({                          \
   int32_t __RES, __ARG1 = (ARG1); \
   __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
@@ -402,6 +403,7 @@ __STATIC_FORCEINLINE  void __CLREX(void)
   \return             Saturated value
  */
 #define __USAT(ARG1,ARG2) \
+__extension__ \
 ({                          \
   uint32_t __RES, __ARG1 = (ARG1); \
   __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
@@ -508,7 +510,7 @@ __STATIC_FORCEINLINE void __set_mode(uint32_t mode) {
 /** \brief  Get Stack Pointer
     \return Stack Pointer value
  */
-__STATIC_FORCEINLINE uint32_t __get_SP()
+__STATIC_FORCEINLINE uint32_t __get_SP(void)
 {
   uint32_t result;
   __ASM volatile("MOV  %0, sp" : "=r" (result) : : "memory");
@@ -526,17 +528,16 @@ __STATIC_FORCEINLINE void __set_SP(uint32_t stack)
 /** \brief  Get USR/SYS Stack Pointer
     \return USR/SYS Stack Pointer value
  */
-__STATIC_FORCEINLINE uint32_t __get_SP_usr()
+__STATIC_FORCEINLINE uint32_t __get_SP_usr(void)
 {
-  uint32_t cpsr;
+  uint32_t cpsr = __get_CPSR();
   uint32_t result;
   __ASM volatile(
-    "MRS     %0, cpsr   \n"
-    "CPS     #0x1F      \n" // no effect in USR mode
-    "MOV     %1, sp     \n"
-    "MSR     cpsr_c, %0 \n" // no effect in USR mode
-    "ISB" :  "+r"(cpsr), "=r"(result) : : "memory"
+    "CPS     #0x1F  \n"
+    "MOV     %0, sp   " : "=r"(result) : : "memory"
    );
+  __set_CPSR(cpsr);
+  __ISB();
   return result;
 }
 
@@ -545,14 +546,13 @@ __STATIC_FORCEINLINE uint32_t __get_SP_usr()
  */
 __STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
 {
-  uint32_t cpsr;
+  uint32_t cpsr = __get_CPSR();
   __ASM volatile(
-    "MRS     %0, cpsr   \n"
-    "CPS     #0x1F      \n" // no effect in USR mode
-    "MOV     sp, %1     \n"
-    "MSR     cpsr_c, %0 \n" // no effect in USR mode
-    "ISB" : "+r"(cpsr) : "r" (topOfProcStack) : "memory"
+    "CPS     #0x1F  \n"
+    "MOV     sp, %0   " : : "r" (topOfProcStack) : "memory"
    );
+  __set_CPSR(cpsr);
+  __ISB();
 }
 
 /** \brief  Get FPEXC

CMSIS/Core_A/Include/core_ca.h

@@ -1459,7 +1459,8 @@ typedef union
 /** \brief Configures the frequency the timer shall run at.
 * \param [in] value The timer frequency in Hz.
 */
-__STATIC_INLINE void PL1_SetCounterFrequency(uint32_t value) {
+__STATIC_INLINE void PL1_SetCounterFrequency(uint32_t value)
+{
   __set_CNTFRQ(value);
   __ISB();
 }
@@ -1467,7 +1468,8 @@ __STATIC_INLINE void PL1_SetCounterFrequency(uint32_t value) {
 /** \brief Sets the reset value of the timer.
 * \param [in] value The value the timer is loaded with.
 */
-__STATIC_INLINE void PL1_SetLoadValue(uint32_t value) {
+__STATIC_INLINE void PL1_SetLoadValue(uint32_t value)
+{
   __set_CNTP_TVAL(value);
   __ISB();
 }
@@ -1475,14 +1477,16 @@ __STATIC_INLINE void PL1_SetLoadValue(uint32_t value) {
 /** \brief Get the current counter value.
 * \return Current counter value.
 */
-__STATIC_INLINE uint32_t PL1_GetCurrentValue() {
+__STATIC_INLINE uint32_t PL1_GetCurrentValue()
+{
   return(__get_CNTP_TVAL());
 }
 
 /** \brief Configure the timer by setting the control value.
 * \param [in] value New timer control value.
 */
-__STATIC_INLINE void PL1_SetControl(uint32_t value) {
+__STATIC_INLINE void PL1_SetControl(uint32_t value)
+{
   __set_CNTP_CTL(value);
   __ISB();
 }
@@ -1490,7 +1494,8 @@ __STATIC_INLINE void PL1_SetControl(uint32_t value) {
 /** \brief Get the control value.
 * \return Control value.
 */
-__STATIC_INLINE uint32_t PL1_GetControl() {
+__STATIC_INLINE uint32_t PL1_GetControl()
+{
   return(__get_CNTP_CTL());
 }
 #endif
@@ -1500,54 +1505,62 @@ __STATIC_INLINE uint32_t PL1_GetControl() {
 /** \brief Set the load value to timers LOAD register.
 * \param [in] value The load value to be set.
 */
-__STATIC_INLINE void PTIM_SetLoadValue(uint32_t value) {
+__STATIC_INLINE void PTIM_SetLoadValue(uint32_t value)
+{
   PTIM->LOAD = value;
 }
 
 /** \brief Get the load value from timers LOAD register.
 * \return Timer_Type::LOAD
 */
-__STATIC_INLINE uint32_t PTIM_GetLoadValue() {
+__STATIC_INLINE uint32_t PTIM_GetLoadValue(void)
+{
   return(PTIM->LOAD);
 }
 
 /** \brief Set current counter value from its COUNTER register.
 */
-__STATIC_INLINE void PTIM_SetCurrentValue(uint32_t value) {
+__STATIC_INLINE void PTIM_SetCurrentValue(uint32_t value)
+{
   PTIM->COUNTER = value;
 }
 
 /** \brief Get current counter value from timers COUNTER register.
 * \result Timer_Type::COUNTER
 */
-__STATIC_INLINE uint32_t PTIM_GetCurrentValue() {
+__STATIC_INLINE uint32_t PTIM_GetCurrentValue(void)
+{
   return(PTIM->COUNTER);
 }
 
 /** \brief Configure the timer using its CONTROL register.
 * \param [in] value The new configuration value to be set.
 */
-__STATIC_INLINE void PTIM_SetControl(uint32_t value) {
+__STATIC_INLINE void PTIM_SetControl(uint32_t value)
+{
   PTIM->CONTROL = value;
 }
 
 /** ref Timer_Type::CONTROL Get the current timer configuration from its CONTROL register.
 * \return Timer_Type::CONTROL
 */
-__STATIC_INLINE uint32_t PTIM_GetControl(void) {
+__STATIC_INLINE uint32_t PTIM_GetControl(void)
+{
   return(PTIM->CONTROL);
 }
 
 /** ref Timer_Type::CONTROL Get the event flag in timers ISR register.
 * \return 0 - flag is not set, 1- flag is set
 */
-__STATIC_INLINE uint32_t PTIM_GetEventFlag(void) {
+__STATIC_INLINE uint32_t PTIM_GetEventFlag(void)
+{
   return (PTIM->ISR & 1UL);
 }
 
 /** ref Timer_Type::CONTROL Clears the event flag in timers ISR register.
 */
-__STATIC_INLINE void PTIM_ClearEventFlag(void) {
+__STATIC_INLINE void PTIM_ClearEventFlag(void)
+{
   PTIM->ISR = 1;
 }
 #endif
@@ -2433,7 +2446,8 @@ __STATIC_INLINE void MMU_TTPage64k(uint32_t *ttb, uint32_t base_address, uint32_
 
 /** \brief  Enable MMU
 */
-__STATIC_INLINE void MMU_Enable(void) {
+__STATIC_INLINE void MMU_Enable(void)
+{
   // Set M bit 0 to enable the MMU
   // Set AFE bit to enable simplified access permissions model
   // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
@@ -2443,7 +2457,8 @@ __STATIC_INLINE void MMU_Enable(void) {
 
 /** \brief  Disable MMU
 */
-__STATIC_INLINE void MMU_Disable(void) {
+__STATIC_INLINE void MMU_Disable(void)
+{
   // Clear M bit 0 to disable the MMU
   __set_SCTLR( __get_SCTLR() & ~1);
   __ISB();
@@ -2452,7 +2467,8 @@ __STATIC_INLINE void MMU_Disable(void) {
 /** \brief  Invalidate entire unified TLB
 */
 
-__STATIC_INLINE void MMU_InvalidateTLB(void) {
+__STATIC_INLINE void MMU_InvalidateTLB(void)
+{
   __set_TLBIALL(0);
   __DSB();     //ensure completion of the invalidation
   __ISB();     //ensure instruction fetch path sees new state

CMSIS/Core_A/Source/irq_ctrl_gic.c

@@ -55,7 +55,7 @@ __WEAK int32_t IRQ_Initialize (void) {
 __WEAK int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler) {
   int32_t status;
 
-  if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
     IRQTable[irqn] = handler;
     status =  0;
   } else {
@@ -70,7 +70,7 @@ __WEAK int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler) {
 __WEAK IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn) {
   IRQHandler_t h;
 
-  if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
     h = IRQTable[irqn];
   } else {
     h = (IRQHandler_t)0;
@@ -84,7 +84,7 @@ __WEAK IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn) {
 __WEAK int32_t IRQ_Enable (IRQn_ID_t irqn) {
   int32_t status;
 
-  if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
     GIC_EnableIRQ ((IRQn_Type)irqn);
     status = 0;
   } else {
@@ -99,7 +99,7 @@ __WEAK int32_t IRQ_Enable (IRQn_ID_t irqn) {
 __WEAK int32_t IRQ_Disable (IRQn_ID_t irqn) {
   int32_t status;
 
-  if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
     GIC_DisableIRQ ((IRQn_Type)irqn);
     status = 0;
   } else {
@@ -114,7 +114,7 @@ __WEAK int32_t IRQ_Disable (IRQn_ID_t irqn) {
 __WEAK uint32_t IRQ_GetEnableState (IRQn_ID_t irqn) {
   uint32_t enable;
 
-  if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
     enable = GIC_GetEnableIRQ((IRQn_Type)irqn);
   } else {
     enable = 0U;
@@ -134,7 +134,7 @@ __WEAK int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode) {
 
   status = 0;
 
-  if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
     // Check triggering mode
     val = (mode & IRQ_MODE_TRIG_Msk);
 
@@ -199,7 +199,7 @@ __WEAK uint32_t IRQ_GetMode (IRQn_ID_t irqn) {
   uint32_t mode;
   uint32_t val;
 
-  if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
     mode = IRQ_MODE_TYPE_IRQ;
 
     // Get trigger mode
@@ -272,7 +272,7 @@ __WEAK IRQn_ID_t IRQ_GetActiveFIQ (void) {
 __WEAK int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn) {
   int32_t status;
 
-  if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
     GIC_EndInterrupt ((IRQn_Type)irqn);
 
     if (irqn == 0) {
@@ -292,7 +292,7 @@ __WEAK int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn) {
 __WEAK int32_t IRQ_SetPending (IRQn_ID_t irqn) {
   int32_t status;
 
-  if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
     GIC_SetPendingIRQ ((IRQn_Type)irqn);
     status = 0;
   } else {
@@ -306,7 +306,7 @@ __WEAK int32_t IRQ_SetPending (IRQn_ID_t irqn) {
 __WEAK uint32_t IRQ_GetPending (IRQn_ID_t irqn) {
   uint32_t pending;
 
-  if ((irqn >= 16) && (irqn < IRQ_GIC_LINE_COUNT)) {
+  if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
     pending = GIC_GetPendingIRQ ((IRQn_Type)irqn);
   } else {
     pending = 0U;
@@ -320,7 +320,7 @@ __WEAK uint32_t IRQ_GetPending (IRQn_ID_t irqn) {
 __WEAK int32_t IRQ_ClearPending (IRQn_ID_t irqn) {
   int32_t status;
 
-  if ((irqn >= 16) && (irqn < IRQ_GIC_LINE_COUNT)) {
+  if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
     GIC_ClearPendingIRQ ((IRQn_Type)irqn);
     status = 0;
   } else {
@@ -335,7 +335,7 @@ __WEAK int32_t IRQ_ClearPending (IRQn_ID_t irqn) {
 __WEAK int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority) {
   int32_t status;
 
-  if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
     GIC_SetPriority ((IRQn_Type)irqn, priority);
     status = 0;
   } else {
@@ -350,7 +350,7 @@ __WEAK int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority) {
 __WEAK uint32_t IRQ_GetPriority (IRQn_ID_t irqn) {
   uint32_t priority;
 
-  if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
+  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
     priority = GIC_GetPriority ((IRQn_Type)irqn);
   } else {
     priority = IRQ_PRIORITY_ERROR;