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@@ -1,8 +1,8 @@
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/**************************************************************************//**
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* @file core_cm7.h
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* @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
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- * @version V5.2.1
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- * @date 06. September 2018
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+ * @version V5.2.3
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+ * @date 12. Oktober 2018
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******************************************************************************/
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/*
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* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
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@@ -2146,6 +2146,7 @@ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
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/*@} end of CMSIS_Core_NVICFunctions */
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+
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/* ########################## MPU functions #################################### */
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#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
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@@ -2154,6 +2155,7 @@ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
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#endif
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+
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/* ########################## FPU functions #################################### */
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/**
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\ingroup CMSIS_Core_FunctionInterface
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@@ -2211,9 +2213,11 @@ __STATIC_INLINE uint32_t SCB_GetFPUType(void)
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\brief Enable I-Cache
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\details Turns on I-Cache
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*/
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-__STATIC_INLINE void SCB_EnableICache (void)
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+__STATIC_FORCEINLINE void SCB_EnableICache (void)
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{
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#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
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+ if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */
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+
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__DSB();
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__ISB();
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SCB->ICIALLU = 0UL; /* invalidate I-Cache */
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@@ -2230,7 +2234,7 @@ __STATIC_INLINE void SCB_EnableICache (void)
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\brief Disable I-Cache
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\details Turns off I-Cache
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*/
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-__STATIC_INLINE void SCB_DisableICache (void)
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+__STATIC_FORCEINLINE void SCB_DisableICache (void)
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{
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#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
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__DSB();
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@@ -2247,7 +2251,7 @@ __STATIC_INLINE void SCB_DisableICache (void)
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\brief Invalidate I-Cache
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\details Invalidates I-Cache
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*/
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-__STATIC_INLINE void SCB_InvalidateICache (void)
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+__STATIC_FORCEINLINE void SCB_InvalidateICache (void)
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{
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#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
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__DSB();
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@@ -2263,14 +2267,16 @@ __STATIC_INLINE void SCB_InvalidateICache (void)
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\brief Enable D-Cache
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\details Turns on D-Cache
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*/
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-__STATIC_INLINE void SCB_EnableDCache (void)
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+__STATIC_FORCEINLINE void SCB_EnableDCache (void)
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{
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#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
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uint32_t ccsidr;
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uint32_t sets;
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uint32_t ways;
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- SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
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+ if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */
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+
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+ SCB->CSSELR = 0U; /* select Level 1 data cache */
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__DSB();
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ccsidr = SCB->CCSIDR;
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@@ -2301,14 +2307,14 @@ __STATIC_INLINE void SCB_EnableDCache (void)
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\brief Disable D-Cache
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\details Turns off D-Cache
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*/
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-__STATIC_INLINE void SCB_DisableDCache (void)
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+__STATIC_FORCEINLINE void SCB_DisableDCache (void)
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{
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#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
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uint32_t ccsidr;
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uint32_t sets;
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uint32_t ways;
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- SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
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+ SCB->CSSELR = 0U; /* select Level 1 data cache */
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__DSB();
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SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
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@@ -2339,14 +2345,14 @@ __STATIC_INLINE void SCB_DisableDCache (void)
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\brief Invalidate D-Cache
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\details Invalidates D-Cache
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*/
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-__STATIC_INLINE void SCB_InvalidateDCache (void)
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+__STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
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{
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#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
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uint32_t ccsidr;
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uint32_t sets;
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uint32_t ways;
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- SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
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+ SCB->CSSELR = 0U; /* select Level 1 data cache */
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__DSB();
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ccsidr = SCB->CCSIDR;
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@@ -2374,15 +2380,15 @@ __STATIC_INLINE void SCB_InvalidateDCache (void)
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\brief Clean D-Cache
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\details Cleans D-Cache
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*/
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-__STATIC_INLINE void SCB_CleanDCache (void)
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+__STATIC_FORCEINLINE void SCB_CleanDCache (void)
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{
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#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
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uint32_t ccsidr;
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uint32_t sets;
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uint32_t ways;
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- SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
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- __DSB();
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+ SCB->CSSELR = 0U; /* select Level 1 data cache */
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+ __DSB();
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ccsidr = SCB->CCSIDR;
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@@ -2409,14 +2415,14 @@ __STATIC_INLINE void SCB_CleanDCache (void)
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\brief Clean & Invalidate D-Cache
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\details Cleans and Invalidates D-Cache
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*/
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-__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
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+__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
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{
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#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
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uint32_t ccsidr;
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uint32_t sets;
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uint32_t ways;
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- SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
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+ SCB->CSSELR = 0U; /* select Level 1 data cache */
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__DSB();
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ccsidr = SCB->CCSIDR;
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@@ -2446,7 +2452,7 @@ __STATIC_INLINE void SCB_CleanInvalidateDCache (void)
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\param[in] addr address (aligned to 32-byte boundary)
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\param[in] dsize size of memory block (in number of bytes)
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*/
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-__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
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+__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
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{
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#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
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int32_t op_size = dsize;
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@@ -2473,7 +2479,7 @@ __STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize
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\param[in] addr address (aligned to 32-byte boundary)
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\param[in] dsize size of memory block (in number of bytes)
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*/
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-__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
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+__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
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{
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#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
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int32_t op_size = dsize;
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@@ -2500,7 +2506,7 @@ __STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
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\param[in] addr address (aligned to 32-byte boundary)
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\param[in] dsize size of memory block (in number of bytes)
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*/
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-__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
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+__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
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{
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#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
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int32_t op_size = dsize;
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