Updated CMSIS core functions.

CMSIS/Core/Include/cmsis_iccarm.h

@@ -1,8 +1,8 @@
 /**************************************************************************//**
  * @file     cmsis_iccarm.h
  * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file
- * @version  V5.0.6
- * @date     02. March 2018
+ * @version  V5.0.7
+ * @date     19. June 2018
  ******************************************************************************/
 
 //------------------------------------------------------------------------------
@@ -340,8 +340,17 @@ __packed struct  __iar_u32 { uint32_t v; };
   #define __TZ_set_BASEPRI_NS(VALUE)  (__arm_wsr("BASEPRI_NS", (VALUE)))
   #define __TZ_get_FAULTMASK_NS()     (__arm_rsr("FAULTMASK_NS"))
   #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
-  #define __TZ_get_PSPLIM_NS()        (__arm_rsr("PSPLIM_NS"))
-  #define __TZ_set_PSPLIM_NS(VALUE)   (__arm_wsr("PSPLIM_NS", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __TZ_get_PSPLIM_NS()      (0U)
+    #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+  #else
+    #define __TZ_get_PSPLIM_NS()      (__arm_rsr("PSPLIM_NS"))
+    #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+  #endif
+
   #define __TZ_get_MSPLIM_NS()        (__arm_rsr("MSPLIM_NS"))
   #define __TZ_set_MSPLIM_NS(VALUE)   (__arm_wsr("MSPLIM_NS", (VALUE)))
 
@@ -716,12 +725,25 @@ __packed struct  __iar_u32 { uint32_t v; };
     __IAR_FT uint32_t   __TZ_get_PSPLIM_NS(void)
     {
       uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
       __asm volatile("MRS      %0,PSPLIM_NS" : "=r" (res));
+    #endif
       return res;
     }
+
     __IAR_FT void   __TZ_set_PSPLIM_NS(uint32_t value)
     {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
       __asm volatile("MSR      PSPLIM_NS,%0" :: "r" (value));
+    #endif
     }
 
     __IAR_FT uint32_t   __TZ_get_MSPLIM_NS(void)
@@ -826,78 +848,78 @@ __packed struct  __iar_u32 { uint32_t v; };
   __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
   {
     uint32_t res;
-    __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
     return ((uint8_t)res);
   }
 
   __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
   {
     uint32_t res;
-    __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
     return ((uint16_t)res);
   }
 
   __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
   {
     uint32_t res;
-    __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
     return res;
   }
 
   __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
   {
-    __ASM volatile ("STLB %1, [%0]" :: "r" (*ptr), "r" (value) : "memory");
+    __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
   }
 
   __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
   {
-    __ASM volatile ("STLH %1, [%0]" :: "r" (*ptr), "r" (value) : "memory");
+    __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
   }
 
   __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
   {
-    __ASM volatile ("STL %1, [%0]" :: "r" (*ptr), "r" (value) : "memory");
+    __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
   }
 
   __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
   {
     uint32_t res;
-    __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
     return ((uint8_t)res);
   }
 
   __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
   {
     uint32_t res;
-    __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
     return ((uint16_t)res);
   }
 
   __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
   {
     uint32_t res;
-    __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
+    __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
     return res;
   }
 
   __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
   {
     uint32_t res;
-    __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory");
+    __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
     return res;
   }
 
   __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
   {
     uint32_t res;
-    __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory");
+    __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
     return res;
   }
 
   __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
   {
     uint32_t res;
-    __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory");
+    __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
     return res;
   }