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@@ -1,12 +1,12 @@
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/**************************************************************************//**
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* @file ARMv81MML_DP.h
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* @brief CMSIS Core Peripheral Access Layer Header File for
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- * Armv8-M Mainline Device Series (configured for Armv8-M Mainline with double precision FPU, with DSP extension, with TrustZone)
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- * @version V5.00
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- * @date 20. June 2018
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+ * Armv8.1-M Mainline Device Series (configured for Armv8.1-M Mainline with double precision FPU, with DSP extension, with TrustZone)
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+ * @version V1.0.0
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+ * @date 25. February 2019
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******************************************************************************/
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/*
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- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
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+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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@@ -35,7 +35,7 @@ extern "C" {
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typedef enum IRQn
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{
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-/* -------------------- Armv8-M Mainline Processor Exceptions Numbers ----------- */
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+/* -------------------- Armv8.1-M Mainline Processor Exceptions Numbers --------- */
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NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
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HardFault_IRQn = -13, /* 3 HardFault Interrupt */
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MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
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@@ -89,7 +89,7 @@ typedef enum IRQn
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#endif
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-/* -------- Configuration of the Cortex-M4 Processor and Core Peripherals ------- */
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+/* --- Configuration of the Armv8.1-M Mainline Processor and Core Peripherals --- */
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#define __ARMv81MML_REV 0x0001U /* Core revision r0p1 */
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#define __SAUREGION_PRESENT 1U /* SAU regions present */
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#define __MPU_PRESENT 1U /* MPU present */
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