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@@ -2,11 +2,11 @@
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* @file system_ARMCM55.c
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* @brief CMSIS Device System Source File for
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* ARMCM55 Device
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- * @version V1.0.0
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- * @date 30. March 2020
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+ * @version V1.0.1
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+ * @date 4. May 2021
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******************************************************************************/
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/*
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- * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
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+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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@@ -75,14 +75,27 @@ void SystemInit (void)
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(defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U))
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SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
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(3U << 11U*2U) ); /* enable CP11 Full Access */
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+
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+ /* Set low-power state for PDEPU */
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+ /* 0b00 | ON, PDEPU is not in low-power state */
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+ /* 0b01 | ON, but the clock is off */
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+ /* 0b10 | RET(ention) */
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+ /* 0b11 | OFF */
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+
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+ /* Clear ELPSTATE, value is 0b11 on Cold reset */
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+ PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos);
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+
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+ /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */
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+ /* PDEPU ON, Clock OFF */
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+ PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos;
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#endif
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#ifdef UNALIGNED_SUPPORT_DISABLE
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SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
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#endif
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-// Enable Loop and branch info cache
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-SCB->CCR |= SCB_CCR_LOB_Msk;
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+ /* Enable Loop and branch info cache */
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+ SCB->CCR |= SCB_CCR_LOB_Msk;
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__ISB();
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#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
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FabKlein