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+/*
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+ * Copyright (C) 2010-2019 Arm Limited or its affiliates. All rights reserved.
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+ *
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+ * SPDX-License-Identifier: Apache-2.0
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+ *
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+ * Licensed under the Apache License, Version 2.0 (the License); you may
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+ * not use this file except in compliance with the License.
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+ * You may obtain a copy of the License at
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+ *
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+ * www.apache.org/licenses/LICENSE-2.0
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+ *
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+ * Unless required by applicable law or agreed to in writing, software
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+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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+ * See the License for the specific language governing permissions and
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+ * limitations under the License.
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+ */
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+
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+/* ----------------------------------------------------------------------
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+ * Project: CMSIS NN Library
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+ * Title: arm_max_pool_s8.c
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+ * Description: Pure C max pool implementation
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+ *
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+ * $Date: August 2019
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+ * $Revision: V.1.0.0
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+ *
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+ * Target Processor: Cortex-M cores
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+ *
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+ * -------------------------------------------------------------------- */
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+
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+#include "arm_nnfunctions.h"
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+#include <arm_math.h>
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+
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+/**
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+ * @ingroup groupNN
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+ */
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+
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+/**
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+ * @addtogroup Pooling
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+ * @{
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+ */
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+
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+void arm_max_pool_s8(const uint16_t input_y,
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+ const uint16_t input_x,
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+ const uint16_t output_y,
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+ const uint16_t output_x,
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+ const uint16_t stride_y,
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+ const uint16_t stride_x,
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+ const uint16_t kernel_y,
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+ const uint16_t kernel_x,
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+ const uint16_t pad_y,
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+ const uint16_t pad_x,
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+ const int8_t act_min,
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+ const int8_t act_max,
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+ const uint16_t channel_in,
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+ int8_t *input,
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+ int16_t *tmp_buffer,
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+ int8_t *output)
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+{
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+ int32_t i_ch_in, i_out_x, i_out_y;
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+ int32_t i_ker_x, i_ker_y;
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+ (void)tmp_buffer;
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+
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+ for (i_out_y = 0; i_out_y < output_y; i_out_y++)
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+ {
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+ for (i_out_x = 0; i_out_x < output_x; i_out_x++)
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+ {
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+ for (i_ch_in = 0; i_ch_in < channel_in; i_ch_in++)
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+ {
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+ /* Native data type for inner loop variables */
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+ int32_t max_val = (int32_t)Q7_MIN;
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+ /* Condition for kernel start dimension: (base_idx_<x,y> + ker_<x,y>_start) >= 0 */
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+ const int32_t base_idx_y = (i_out_y * stride_y) - pad_y;
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+ const int32_t base_idx_x = (i_out_x * stride_x) - pad_x;
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+ const int32_t ker_y_start = MAX(0, -base_idx_y);
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+ const int32_t ker_x_start = MAX(0, -base_idx_x);
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+
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+ /* Condition for kernel end dimension: (base_idx_<x,y> + ker_<x,y>_end) < input_<x,y> */
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+ const int32_t ker_y_end = MIN(kernel_y, input_y - base_idx_y);
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+ const int32_t ker_x_end = MIN(kernel_x, input_x - base_idx_x);
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+
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+ for (i_ker_y = ker_y_start; i_ker_y < ker_y_end; i_ker_y++)
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+ {
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+ for (i_ker_x = ker_x_start; i_ker_x < ker_x_end; i_ker_x++)
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+ {
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+ const int32_t col_idx = base_idx_x + i_ker_x;
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+ const int32_t row_idx = base_idx_y + i_ker_y;
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+
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+ max_val = MAX(input[(row_idx * input_x + col_idx) * channel_in + i_ch_in], max_val);
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+ }
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+ }
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+
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+ /* Activation function */
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+ max_val = MAX(max_val, act_min);
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+ max_val = MIN(max_val, act_max);
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+
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+ output[i_ch_in + channel_in * (i_out_x + i_out_y * output_x)] = (int8_t)max_val;
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+ }
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+ }
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+ }
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+}
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+
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+/**
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+ * @} end of Pooling group
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+ */
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