Core A: cache: instr mva

As documented by ARM at:
    https://developer.arm.com/documentation/ddi0301/h/Babhejba

Co-authored-by: Théophile Ranquet <tranquet@sequans.com>
Co-authored-by: Jonatan Antoni <jonatan.antoni@arm.com>

CMSIS/Core_A/Include/cmsis_cp15.h

@@ -1,8 +1,8 @@
 /**************************************************************************//**
  * @file     cmsis_cp15.h
  * @brief    CMSIS compiler specific macros, functions, instructions
- * @version  V1.0.1
- * @date     07. Sep 2017
+ * @version  V1.0.2
+ * @date     19. December 2022
  ******************************************************************************/
 /*
  * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
@@ -410,6 +410,15 @@ __STATIC_FORCEINLINE void __set_ICIALLU(uint32_t value)
   __set_CP(15, 0, value, 7, 5, 0);
 }
 
+/** \brief  Set ICIMVAC
+
+  Instruction Cache Invalidate
+ */
+__STATIC_FORCEINLINE void __set_ICIMVAC(uint32_t value)
+{
+  __set_CP(15, 0, value, 7, 5, 1);
+}
+
 /** \brief  Set DCCMVAC
 
   Data cache clean

CMSIS/Core_A/Include/core_ca.h

@@ -1197,6 +1197,15 @@ __STATIC_FORCEINLINE void L1C_InvalidateBTAC(void) {
   __ISB();     //ensure instruction fetch path sees new state
 }
 
+/** \brief  Clean instruction cache line by address.
+* \param [in] va Pointer to instructions to clear the cache for.
+*/
+__STATIC_FORCEINLINE void L1C_InvalidateICacheMVA(void *va) {
+  __set_ICIMVAC((uint32_t)va);
+  __DSB();     //ensure completion of the invalidation
+  __ISB();     //ensure instruction fetch path sees new I cache state
+}
+
 /** \brief  Invalidate the whole instruction cache
 */
 __STATIC_FORCEINLINE void L1C_InvalidateICacheAll(void) {