 GuentherMartin
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12bcacdcd4
Updated Cortex-M55 core header
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3 years ago |
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Martin Günther
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4075efea8d
CMSIS-Core(M): Add missing registers to core_cm55.h
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3 years ago |
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Chris Reed
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efd2b93c8d
Core: add missing Secure Fault syndrome registers and fix register name typo. (#1346)
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4 years ago |
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Wilfried Chauveau
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a6aec0c580
Fix PMU_Type in core_m55 and core_armv81mml.
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4 years ago |
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GuentherMartin
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2e1a5d1386
CMSIS-Core(M): incorrect use of SCB_SHCSR_MEMFAULTACT_Pos in MMFSR defines (#1172)
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4 years ago |
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FabKlein
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ae9887cea6
[CMSIS Core] Added CM55 Power Mode Control Registers definition
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4 years ago |
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Edmund Player
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185ed11473
Changed ARM_PMU_Get_EVCNTR() function to mask top 16 bits of result so it's guaranteed to work across any Armv8.1-M implementation (not just Cortex-M55)
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5 years ago |
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Jonatan Antoni
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fa6076b91b
Core(M): Fixed device config checks for missing defines.
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5 years ago |
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Jonatan Antoni
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f0f420b065
Core(M): Fix-up to Armv8.1-M core headers after adding PMU.
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5 years ago |
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Edmund Player
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61ef0a67b0
Updated pmu_armv8.h with PMU functions and event macros.
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5 years ago |
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Jonatan Antoni
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01f1b6be67
Core(M): Removed __MVE_PRESENT and __MVE_USED macros for Armv8.1-M based devices.
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5 years ago |
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Jonatan Antoni
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8ced160cc8
Core(M): Refactored/aligned L1 Cache Functions
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5 years ago |
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GuentherMartin
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bd8a0f1956
Added Cortex-M55 support.
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6 years ago |
