CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_DataStructs.txt

/****************************    Data Structures    ***********************************************/
/** \brief  Union type to access the Application Program Status Register (APSR).
 */
typedef union
{
  struct
  {
#if (__CORTEX_M != 0x04)
    uint32_t _reserved0:27;              ///< bit:  0..26  Reserved
#else
    uint32_t _reserved0:16;              ///< bit:  0..15  Reserved
    uint32_t GE:4;                       ///< bit: 16..19  Greater than or Equal flags
    uint32_t _reserved1:7;               ///< bit: 20..26  Reserved
#endif
    uint32_t Q:1;                        ///< bit:     27  Saturation condition flag
    uint32_t V:1;                        ///< bit:     28  Overflow condition code flag
    uint32_t C:1;                        ///< bit:     29  Carry condition code flag
    uint32_t Z:1;                        ///< bit:     30  Zero condition code flag
    uint32_t N:1;                        ///< bit:     31  Negative condition code flag
  } b;                                   ///< Structure used for bit  access
  uint32_t w;                            ///< Type      used for word access
} APSR_Type;


/**************************************************************************************************/
/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
 */
typedef union
{
  struct
  {
    uint32_t ISR:9;                      ///< bit:  0.. 8  Exception number
    uint32_t _reserved0:23;              ///< bit:  9..31  Reserved
  } b;                                   ///< Structure used for bit  access
  uint32_t w;                            ///< Type      used for word access
} IPSR_Type;


/**************************************************************************************************/
/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
 */
typedef union
{
  struct
  {
    uint32_t ISR:9;                      ///< bit:  0.. 8  Exception number
#if (__CORTEX_M != 0x04)
    uint32_t _reserved0:15;              ///< bit:  9..23  Reserved
#else
    uint32_t _reserved0:7;               ///< bit:  9..15  Reserved
    uint32_t GE:4;                       ///< bit: 16..19  Greater than or Equal flags
    uint32_t _reserved1:4;               ///< bit: 20..23  Reserved
#endif
    uint32_t T:1;                        ///< bit:     24  Thumb bit        (read 0)
    uint32_t IT:2;                       ///< bit: 25..26  saved IT state   (read 0)
    uint32_t Q:1;                        ///< bit:     27  Saturation condition flag
    uint32_t V:1;                        ///< bit:     28  Overflow condition code flag
    uint32_t C:1;                        ///< bit:     29  Carry condition code flag
    uint32_t Z:1;                        ///< bit:     30  Zero condition code flag
    uint32_t N:1;                        ///< bit:     31  Negative condition code flag
  } b;                                   ///< Structure used for bit  access
  uint32_t w;                            ///< Type      used for word access
} xPSR_Type;


/**************************************************************************************************/
/** \brief  Union type to access the Control Registers (CONTROL).
 */
typedef union
{
  struct
  {
    uint32_t nPRIV:1;                    ///< bit:      0  Execution privilege in Thread mode
    uint32_t SPSEL:1;                    ///< bit:      1  Stack to be used
    uint32_t FPCA:1;                     ///< bit:      2  FP extension active flag
    uint32_t _reserved0:29;              ///< bit:  3..31  Reserved
  } b;                                   ///< Structure used for bit  access
  uint32_t w;                            ///< Type      used for word access
} CONTROL_Type;


/**************************************************************************************************/
/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
 */
typedef struct
{
  __IOM uint32_t ISER[8];                ///< Offset: 0x000 (R/W)  Interrupt Set Enable Register
        uint32_t RESERVED0[24];          ///< Reserved
  __IOM uint32_t ICER[8];                ///< Offset: 0x080 (R/W)  Interrupt Clear Enable Register
        uint32_t RSERVED1[24];           ///< Reserved
  __IOM uint32_t ISPR[8];                ///< Offset: 0x100 (R/W)  Interrupt Set Pending Register
        uint32_t RESERVED2[24];          ///< Reserved
  __IOM uint32_t ICPR[8];                ///< Offset: 0x180 (R/W)  Interrupt Clear Pending Register
        uint32_t RESERVED3[24];          ///< Reserved
  __IOM uint32_t IABR[8];                ///< Offset: 0x200 (R/W)  Interrupt Active bit Register
        uint32_t RESERVED4[56];          ///< Reserved
  __IOM uint8_t  IP[240];                ///< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide)
        uint32_t RESERVED5[644];         ///< Reserved
  __OM  uint32_t STIR;                   ///< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register
}  NVIC_Type;


/**************************************************************************************************/
/** \brief  Structure type to access the System Control Block (SCB).
 */
typedef struct
{
  __IM  uint32_t CPUID;                  ///< Offset: 0x000 (R/ )  CPUID Base Register
  __IOM uint32_t ICSR;                   ///< Offset: 0x004 (R/W)  Interrupt Control and State Register
  __IOM uint32_t VTOR;                   ///< Offset: 0x008 (R/W)  Vector Table Offset Register
  __IOM uint32_t AIRCR;                  ///< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register
  __IOM uint32_t SCR;                    ///< Offset: 0x010 (R/W)  System Control Register
  __IOM uint32_t CCR;                    ///< Offset: 0x014 (R/W)  Configuration Control Register
  __IOM uint8_t  SHP[12];                ///< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15)
  __IOM uint32_t SHCSR;                  ///< Offset: 0x024 (R/W)  System Handler Control and State Register
  __IOM uint32_t CFSR;                   ///< Offset: 0x028 (R/W)  Configurable Fault Status Register
  __IOM uint32_t HFSR;                   ///< Offset: 0x02C (R/W)  HardFault Status Register
  __IOM uint32_t DFSR;                   ///< Offset: 0x030 (R/W)  Debug Fault Status Register
  __IOM uint32_t MMFAR;                  ///< Offset: 0x034 (R/W)  MemManage Fault Address Register
  __IOM uint32_t BFAR;                   ///< Offset: 0x038 (R/W)  BusFault Address Register
  __IOM uint32_t AFSR;                   ///< Offset: 0x03C (R/W)  Auxiliary Fault Status Register
  __IM  uint32_t PFR[2];                 ///< Offset: 0x040 (R/ )  Processor Feature Register
  __IM  uint32_t DFR;                    ///< Offset: 0x048 (R/ )  Debug Feature Register
  __IM  uint32_t ADR;                    ///< Offset: 0x04C (R/ )  Auxiliary Feature Register
  __IM  uint32_t MMFR[4];                ///< Offset: 0x050 (R/ )  Memory Model Feature Register
  __IM  uint32_t ISAR[5];                ///< Offset: 0x060 (R/ )  Instruction Set Attributes Register
        uint32_t RESERVED0[5];           ///< Reserved
  __IOM uint32_t CPACR;                  ///< Offset: 0x088 (R/W)  Coprocessor Access Control Register
} SCB_Type;


/**************************************************************************************************/
/** \brief  Structure type to access the System Control and ID Register not in the SCB.
 */
typedef struct
{
        uint32_t RESERVED0[1];           /*!< Reserved */
  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register
                                            \note available for Cortex-M3, Cortex-M4, Cortex-M7, Cortex-M33, Cortex-M33P, SecureCore SC300 */
  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register
                                            \note available for Cortex-M1, Cortex-M3 , Cortex-M4, Cortex-M7, Cortex-M33, Cortex-M33P, SecureCore SC000, SecureCore SC300 */
  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control Register
                                            \note available for Cortex-M33, Cortex-M33P */
} SCnSCB_Type;


/**************************************************************************************************/
/** \brief  Structure type to access the Implementation Control Block Register (ICB).
    \note replaces SCnSCB_Type (only Cortex-M55)
 */
typedef struct
{
        uint32_t RESERVED0[1U];
  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
} ICB_Type;


/**************************************************************************************************/
/** \brief  Structure type to access the System Timer (SysTick).
 */
typedef struct
{
  __IOM uint32_t CTRL;                   ///< Offset: 0x000 (R/W)  SysTick Control and Status Register
  __IOM uint32_t LOAD;                   ///< Offset: 0x004 (R/W)  SysTick Reload Value Register
  __IOM uint32_t VAL;                    ///< Offset: 0x008 (R/W)  SysTick Current Value Register
  __IM  uint32_t CALIB;                  ///< Offset: 0x00C (R/ )  SysTick Calibration Register
} SysTick_Type;


/**************************************************************************************************/
/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
 */
typedef struct
{
  __OM  union
  {
    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
//      uint32_t RESERVED0[864U];
  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
//      uint32_t RESERVED1[15U];
  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
//      uint32_t RESERVED2[15U];
  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
//      uint32_t RESERVED3[29U];
  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
//      uint32_t RESERVED4[43U];
  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
//      uint32_t RESERVED5[1U];
  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register (Cortex-M33 only) */
//      uint32_t RESERVED6[4U];
  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
} ITM_Type;


/**************************************************************************************************/
/** \brief  Structure type to access the Memory Protection Unit (MPU).
 */
typedef struct
{
  __IM  uint32_t TYPE;                   ///< Offset: 0x000 (R/ )  MPU Type Register
  __IOM uint32_t CTRL;                   ///< Offset: 0x004 (R/W)  MPU Control Register
  __IOM uint32_t RNR;                    ///< Offset: 0x008 (R/W)  MPU Region RNRber Register
  __IOM uint32_t RBAR;                   ///< Offset: 0x00C (R/W)  MPU Region Base Address Register
  __IOM uint32_t RASR;                   ///< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register
  __IOM uint32_t RBAR_A1;                ///< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register
  __IOM uint32_t RASR_A1;                ///< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register
  __IOM uint32_t RBAR_A2;                ///< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register
  __IOM uint32_t RASR_A2;                ///< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register
  __IOM uint32_t RBAR_A3;                ///< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register
  __IOM uint32_t RASR_A3;                ///< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register
} MPU_Type;


/**************************************************************************************************/
/** \brief  Structure type to access the Floating Point Unit (FPU).
 */
typedef struct
{
        uint32_t RESERVED0[1];           ///< Reserved
  __IOM uint32_t FPCCR;                  ///< Offset: 0x004 (R/W)  Floating-Point Context Control Register
  __IOM uint32_t FPCAR;                  ///< Offset: 0x008 (R/W)  Floating-Point Context Address Register
  __IOM uint32_t FPDSCR;                 ///< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register
  __IM  uint32_t MVFR0;                  ///< Offset: 0x010 (R/ )  Media and FP Feature Register 0
  __IM  uint32_t MVFR1;                  ///< Offset: 0x014 (R/ )  Media and FP Feature Register 1
} FPU_Type;


/**************************************************************************************************/
/** \brief  Structure type to access the Core Debug Register (CoreDebug).
 */
typedef struct
{
  __IOM uint32_t DHCSR;                  ///< Offset: 0x000 (R/W)  Debug Halting Control and Status Register
  __OM  uint32_t DCRSR;                  ///< Offset: 0x004 ( /W)  Debug Core Register Selector Register
  __IOM uint32_t DCRDR;                  ///< Offset: 0x008 (R/W)  Debug Core Register Data Register
  __IOM uint32_t DEMCR;                  ///< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register
} CoreDebug_Type;


/**************************************************************************************************/
/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
 */
typedef struct
{
  __IOM uint32_t CTRL;                   ///< Offset: 0x000 (R/W)  Control Register
  __IOM uint32_t CYCCNT;                 ///< Offset: 0x004 (R/W)  Cycle Count Register
  __IOM uint32_t CPICNT;                 ///< Offset: 0x008 (R/W)  CPI Count Register
  __IOM uint32_t EXCCNT;                 ///< Offset: 0x00C (R/W)  Exception Overhead Count Register
  __IOM uint32_t SLEEPCNT;               ///< Offset: 0x010 (R/W)  Sleep Count Register
  __IOM uint32_t LSUCNT;                 ///< Offset: 0x014 (R/W)  LSU Count Register
  __IOM uint32_t FOLDCNT;                ///< Offset: 0x018 (R/W)  Folded-instruction Count Register
  __IM  uint32_t PCSR;                   ///< Offset: 0x01C (R/ )  Program Counter Sample Register
  __IOM uint32_t COMP0;                  ///< Offset: 0x020 (R/W)  Comparator Register 0
  __IOM uint32_t MASK0;                  ///< Offset: 0x024 (R/W)  Mask Register 0
  __IOM uint32_t FUNCTION0;              ///< Offset: 0x028 (R/W)  Function Register 0
        uint32_t RESERVED0[1];           ///< Reserved
  __IOM uint32_t COMP1;                  ///< Offset: 0x030 (R/W)  Comparator Register 1
  __IOM uint32_t MASK1;                  ///< Offset: 0x034 (R/W)  Mask Register 1
  __IOM uint32_t FUNCTION1;              ///< Offset: 0x038 (R/W)  Function Register 1
        uint32_t RESERVED1[1];           ///< Reserved
  __IOM uint32_t COMP2;                  ///< Offset: 0x040 (R/W)  Comparator Register 2
  __IOM uint32_t MASK2;                  ///< Offset: 0x044 (R/W)  Mask Register 2
  __IOM uint32_t FUNCTION2;              ///< Offset: 0x048 (R/W)  Function Register 2
        uint32_t RESERVED2[1];           ///< Reserved
  __IOM uint32_t COMP3;                  ///< Offset: 0x050 (R/W)  Comparator Register 3
  __IOM uint32_t MASK3;                  ///< Offset: 0x054 (R/W)  Mask Register 3
  __IOM uint32_t FUNCTION3;              ///< Offset: 0x058 (R/W)  Function Register 3
} DWT_Type;


/**************************************************************************************************/
/** \brief  Structure type to access the Trace Port Interface Register (TPI).
 */
typedef struct
{
  __IOM uint32_t SSPSR;                  ///< Offset: 0x000 (R/ )  Supported Parallel Port Size Register
  __IOM uint32_t CSPSR;                  ///< Offset: 0x004 (R/W)  Current Parallel Port Size Register
        uint32_t RESERVED0[2];           ///< Reserved
  __IOM uint32_t ACPR;                   ///< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register
        uint32_t RESERVED1[55];          ///< Reserved
  __IOM uint32_t SPPR;                   ///< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register
        uint32_t RESERVED2[131];         ///< Reserved
  __IM  uint32_t FFSR;                   ///< Offset: 0x300 (R/ )  Formatter and Flush Status Register
  __IOM uint32_t FFCR;                   ///< Offset: 0x304 (R/W)  Formatter and Flush Control Register
  __IM  uint32_t FSCR;                   ///< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register
        uint32_t RESERVED3[759];         ///< Reserved
  __IM  uint32_t TRIGGER;                ///< Offset: 0xEE8 (R/ )  TRIGGER
  __IM  uint32_t FIFO0;                  ///< Offset: 0xEEC (R/ )  Integration ETM Data
  __IM  uint32_t ITATBCTR2;              ///< Offset: 0xEF0 (R/ )  ITATBCTR2
        uint32_t RESERVED4[1];           ///< Reserved
  __IM  uint32_t ITATBCTR0;              ///< Offset: 0xEF8 (R/ )  ITATBCTR0
  __IM  uint32_t FIFO1;                  ///< Offset: 0xEFC (R/ )  Integration ITM Data
  __IOM uint32_t ITCTRL;                 ///< Offset: 0xF00 (R/W)  Integration Mode Control
        uint32_t RESERVED5[39];          ///< Reserved
  __IOM uint32_t CLAIMSET;               ///< Offset: 0xFA0 (R/W)  Claim tag set
  __IOM uint32_t CLAIMCLR;               ///< Offset: 0xFA4 (R/W)  Claim tag clear
        uint32_t RESERVED7[8];           ///< Reserved
  __IM  uint32_t DEVID;                  ///< Offset: 0xFC8 (R/ )  TPIU_DEVID
  __IM  uint32_t DEVTYPE;                ///< Offset: 0xFCC (R/ )  TPIU_DEVTYPE
} TPI_Type;