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  111. <a href="#define-members">Macros</a>  </div>
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    113. 

  113. <div class="title">Define values<div class="ingroups"><a class="el" href="group__mpu__functions.html">MPU Functions for Armv6-M/v7-M</a></div></div>  </div>
    114. 

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    116. 

  116. 

  117. <p>Define values for MPU region setup.  
    118. 

  118. <a href="#details">More...</a></p>
    119. 

  119. <table class="memberdecls">
    120. 

  120. <tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
    121. 

  121. Macros</h2></td></tr>
    122. 

  122. <tr class="memitem:gadb0a92c0928c113120567e85ff1ba05c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__defines.html#gadb0a92c0928c113120567e85ff1ba05c">ARM_MPU_REGION_SIZE_xxx</a></td></tr>
    123. 

  123. <tr class="memdesc:gadb0a92c0928c113120567e85ff1ba05c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Size values of a MPU region (in RASR field)  <a href="#gadb0a92c0928c113120567e85ff1ba05c">More...</a><br/></td></tr>
    124. 

  124. <tr class="separator:gadb0a92c0928c113120567e85ff1ba05c"><td class="memSeparator" colspan="2">&#160;</td></tr>
    125. 

  125. <tr class="memitem:gabc4788126d7798469cb862a08d3050cc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__defines.html#gabc4788126d7798469cb862a08d3050cc">ARM_MPU_AP_xxx</a></td></tr>
    126. 

  126. <tr class="memdesc:gabc4788126d7798469cb862a08d3050cc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Values for MPU region access permissions (in RASR field)  <a href="#gabc4788126d7798469cb862a08d3050cc">More...</a><br/></td></tr>
    127. 

  127. <tr class="separator:gabc4788126d7798469cb862a08d3050cc"><td class="memSeparator" colspan="2">&#160;</td></tr>
    128. 

  128. <tr class="memitem:ga71d41084e984be70a23cb640fd89d1e2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__defines.html#ga71d41084e984be70a23cb640fd89d1e2">ARM_MPU_ACCESS_xxx</a></td></tr>
    129. 

  129. <tr class="memdesc:ga71d41084e984be70a23cb640fd89d1e2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Values for MPU region access attributes (in RASR field)  <a href="#ga71d41084e984be70a23cb640fd89d1e2">More...</a><br/></td></tr>
    130. 

  130. <tr class="separator:ga71d41084e984be70a23cb640fd89d1e2"><td class="memSeparator" colspan="2">&#160;</td></tr>
    131. 

  131. <tr class="memitem:gab23596306119e7831847bd9683de3934"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__defines.html#gab23596306119e7831847bd9683de3934">ARM_MPU_CACHEP_xxx</a></td></tr>
    132. 

  132. <tr class="memdesc:gab23596306119e7831847bd9683de3934"><td class="mdescLeft">&#160;</td><td class="mdescRight">Cache policy values for MPU region access attributes (in RASR field)  <a href="#gab23596306119e7831847bd9683de3934">More...</a><br/></td></tr>
    133. 

  133. <tr class="separator:gab23596306119e7831847bd9683de3934"><td class="memSeparator" colspan="2">&#160;</td></tr>
    134. 

  134. </table>
    135. 

  135. <a name="details" id="details"></a><h2 class="groupheader">Description</h2>
    136. 

  136. <p>Define values for MPU region setup. </p>
    137. 

  137. <p>The following define values are used with <a class="el" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a> to setup the <a class="el" href="structMPU__Type.html#a8f00c4a5e31b0a8d103ed3b0732c17a3">RASR</a> value field in the MPU region.</p>
    138. 

  138. <dl class="section see"><dt>See Also</dt><dd><a class="el" href="structARM__MPU__Region__t.html" title="Setup information of a single MPU Region. ">ARM_MPU_Region_t</a>, <a class="el" href="group__mpu__functions.html#ga16931f9ad84d7289e8218e169ae6db5d">ARM_MPU_SetRegion</a>, <a class="el" href="group__mpu__functions.html#ga042ba1a6a1a58795231459ac0410b809">ARM_MPU_SetRegionEx</a>. </dd></dl>
    139. 

  139. <h2 class="groupheader">Macro Definition Documentation</h2>
    140. 

  140. <a class="anchor" id="ga71d41084e984be70a23cb640fd89d1e2"></a>
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  141. <div class="memitem">
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    145. 

  145.           <td class="memname">#define ARM_MPU_ACCESS_xxx</td>
    146. 

  146.         </tr>
    147. 

  147.       </table>
    148. 

  148. </div><div class="memdoc">
    149. 

  149. 

  150. <p>Values for MPU region access attributes (in RASR field) </p>
    151. 

  151. <p>The following define values are used to compose the access attributes for an MPU region: </p>
    152. 

  152. <table class="doxtable">
    153. 

  153. <tr>
    154. 

  154. <th align="left">#define </th><th align="left">TEX </th><th align="left">Shareable </th><th align="left">Cacheable </th><th align="left">Bufferable </th><th align="left">Description  </th></tr>
    155. 

  155. <tr>
    156. 

  156. <td align="left">ARM_MPU_ACCESS_ORDERED </td><td align="left">000b </td><td align="left">1 </td><td align="left">0 </td><td align="left">0 </td><td align="left">Strongly ordered memory </td></tr>
    157. 

  157. <tr>
    158. 

  158. <td align="left">ARM_MPU_ACCESS_DEVICE(S) </td><td align="left">0s0b </td><td align="left">S </td><td align="left">0 </td><td align="left">S </td><td align="left">Memory mapped peripheral device, shared (S=1) or non-shared (S=0) </td></tr>
    159. 

  159. <tr>
    160. 

  160. <td align="left">ARM_MPU_ACCESS_NORMAL(O,I,S) </td><td align="left">1BBb </td><td align="left">S </td><td align="left">A </td><td align="left">A </td><td align="left">Normal memory, with outer/inner cache policy (O/I=<a class="el" href="group__mpu__defines.html#gab23596306119e7831847bd9683de3934">ARM_MPU_CACHEP_xxx</a>, shared (S=1) or non-share (S=0) </td></tr>
    161. 

  161. </table>
    162. 

  162. 

  163. </div>
    164. 

  164. </div>
    165. 

  165. <a class="anchor" id="gabc4788126d7798469cb862a08d3050cc"></a>
    166. 

  166. <div class="memitem">
    167. 

  167. <div class="memproto">
    168. 

  168.       <table class="memname">
    169. 

  169.         <tr>
    170. 

  170.           <td class="memname">#define ARM_MPU_AP_xxx</td>
    171. 

  171.         </tr>
    172. 

  172.       </table>
    173. 

  173. </div><div class="memdoc">
    174. 

  174. 

  175. <p>Values for MPU region access permissions (in RASR field) </p>
    176. 

  176. <p>The following define values are used to compose the access permission for an MPU region: </p>
    177. 

  177. <table class="doxtable">
    178. 

  178. <tr>
    179. 

  179. <th align="left">#define </th><th align="left">Value </th><th align="left">Access permissions  </th></tr>
    180. 

  180. <tr>
    181. 

  181. <td align="left">ARM_MPU_AP_NONE </td><td align="left">0x0U </td><td align="left">None: any access generates a permission fault. </td></tr>
    182. 

  182. <tr>
    183. 

  183. <td align="left">ARM_MPU_AP_PRIV </td><td align="left">0x1U </td><td align="left">Privileged Read/Write: privileged access only; any unprivileged access generates a permission fault. </td></tr>
    184. 

  184. <tr>
    185. 

  185. <td align="left">ARM_MPU_AP_URO </td><td align="left">0x2U </td><td align="left">Privileged Read/Write; Unprivileged Read-only: any unprivileged write generates a permission fault. </td></tr>
    186. 

  186. <tr>
    187. 

  187. <td align="left">ARM_MPU_AP_FULL </td><td align="left">0x3U </td><td align="left">Privileged Read/Write. Unprivileged Read/Write: full access, permission faults are never generated. </td></tr>
    188. 

  188. <tr>
    189. 

  189. <td align="left">ARM_MPU_AP_PRO </td><td align="left">0x5U </td><td align="left">Privileged Read-only: any unprivileged access or privileged write generates a permission fault. </td></tr>
    190. 

  190. <tr>
    191. 

  191. <td align="left">ARM_MPU_AP_RO </td><td align="left">0x6U </td><td align="left">Privileged and Unprivileged Read-only: any write generates a permission fault. </td></tr>
    192. 

  192. </table>
    193. 

  193. 

  194. </div>
    195. 

  195. </div>
    196. 

  196. <a class="anchor" id="gab23596306119e7831847bd9683de3934"></a>
    197. 

  197. <div class="memitem">
    198. 

  198. <div class="memproto">
    199. 

  199.       <table class="memname">
    200. 

  200.         <tr>
    201. 

  201.           <td class="memname">#define ARM_MPU_CACHEP_xxx</td>
    202. 

  202.         </tr>
    203. 

  203.       </table>
    204. 

  204. </div><div class="memdoc">
    205. 

  205. 

  206. <p>Cache policy values for MPU region access attributes (in RASR field) </p>
    207. 

  207. <p>The following define values are used to compose the cacheability flags within the access attributes for an MPU region: </p>
    208. 

  208. <table class="doxtable">
    209. 

  209. <tr>
    210. 

  210. <th align="left">#define </th><th align="left">Value </th><th align="left">Cacheability policy  </th></tr>
    211. 

  211. <tr>
    212. 

  212. <td align="left">ARM_MPU_CACHEP_NOCACHE </td><td align="left">00b </td><td align="left">Non-cacheable </td></tr>
    213. 

  213. <tr>
    214. 

  214. <td align="left">ARM_MPU_CACHEP_WB_WRA </td><td align="left">01b </td><td align="left">Write-back, write and read allocate </td></tr>
    215. 

  215. <tr>
    216. 

  216. <td align="left">ARM_MPU_CACHEP_WT_NWA </td><td align="left">10b </td><td align="left">Write-through, no write allocate </td></tr>
    217. 

  217. <tr>
    218. 

  218. <td align="left">ARM_MPU_CACHEP_WB_NWA </td><td align="left">11b </td><td align="left">Write-back, no write allocate </td></tr>
    219. 

  219. </table>
    220. 

  220. 

  221. </div>
    222. 

  222. </div>
    223. 

  223. <a class="anchor" id="gadb0a92c0928c113120567e85ff1ba05c"></a>
    224. 

  224. <div class="memitem">
    225. 

  225. <div class="memproto">
    226. 

  226.       <table class="memname">
    227. 

  227.         <tr>
    228. 

  228.           <td class="memname">#define ARM_MPU_REGION_SIZE_xxx</td>
    229. 

  229.         </tr>
    230. 

  230.       </table>
    231. 

  231. </div><div class="memdoc">
    232. 

  232. 

  233. <p>Size values of a MPU region (in RASR field) </p>
    234. 

  234. <p>The following define values are used to compose the size information for an MPU region:</p>
    235. 

  235. <table class="doxtable">
    236. 

  236. <tr>
    237. 

  237. <th align="left">#define </th><th align="left">Value </th><th align="left">Description  </th></tr>
    238. 

  238. <tr>
    239. 

  239. <td align="left">ARM_MPU_REGION_SIZE_32B </td><td align="left">0x04U </td><td align="left">Region size 32 Bytes </td></tr>
    240. 

  240. <tr>
    241. 

  241. <td align="left">ARM_MPU_REGION_SIZE_64B </td><td align="left">0x05U </td><td align="left">Region size 64 Bytes </td></tr>
    242. 

  242. <tr>
    243. 

  243. <td align="left">ARM_MPU_REGION_SIZE_128B </td><td align="left">0x06U </td><td align="left">Region size 128 Bytes </td></tr>
    244. 

  244. <tr>
    245. 

  245. <td align="left">ARM_MPU_REGION_SIZE_256B </td><td align="left">0x07U </td><td align="left">Region size 256 Bytes </td></tr>
    246. 

  246. <tr>
    247. 

  247. <td align="left">ARM_MPU_REGION_SIZE_512B </td><td align="left">0x08U </td><td align="left">Region size 512 Bytes </td></tr>
    248. 

  248. <tr>
    249. 

  249. <td align="left">ARM_MPU_REGION_SIZE_1KB </td><td align="left">0x09U </td><td align="left">Region size 1 KByte </td></tr>
    250. 

  250. <tr>
    251. 

  251. <td align="left">ARM_MPU_REGION_SIZE_2KB </td><td align="left">0x0AU </td><td align="left">Region size 2 KBytes </td></tr>
    252. 

  252. <tr>
    253. 

  253. <td align="left">ARM_MPU_REGION_SIZE_4KB </td><td align="left">0x0BU </td><td align="left">Region size 4 KBytes </td></tr>
    254. 

  254. <tr>
    255. 

  255. <td align="left">ARM_MPU_REGION_SIZE_8KB </td><td align="left">0x0CU </td><td align="left">Region size 8 KBytes </td></tr>
    256. 

  256. <tr>
    257. 

  257. <td align="left">ARM_MPU_REGION_SIZE_16KB </td><td align="left">0x0DU </td><td align="left">Region size 16 KBytes </td></tr>
    258. 

  258. <tr>
    259. 

  259. <td align="left">ARM_MPU_REGION_SIZE_32KB </td><td align="left">0x0EU </td><td align="left">Region size 32 KBytes </td></tr>
    260. 

  260. <tr>
    261. 

  261. <td align="left">ARM_MPU_REGION_SIZE_64KB </td><td align="left">0x0FU </td><td align="left">Region size 64 KBytes </td></tr>
    262. 

  262. <tr>
    263. 

  263. <td align="left">ARM_MPU_REGION_SIZE_128KB </td><td align="left">0x10U </td><td align="left">Region size 128 KBytes </td></tr>
    264. 

  264. <tr>
    265. 

  265. <td align="left">ARM_MPU_REGION_SIZE_256KB </td><td align="left">0x11U </td><td align="left">Region size 256 KBytes </td></tr>
    266. 

  266. <tr>
    267. 

  267. <td align="left">ARM_MPU_REGION_SIZE_512KB </td><td align="left">0x12U </td><td align="left">Region size 512 KBytes </td></tr>
    268. 

  268. <tr>
    269. 

  269. <td align="left">ARM_MPU_REGION_SIZE_1MB </td><td align="left">0x13U </td><td align="left">Region size 1 MByte </td></tr>
    270. 

  270. <tr>
    271. 

  271. <td align="left">ARM_MPU_REGION_SIZE_2MB </td><td align="left">0x14U </td><td align="left">Region size 2 MBytes </td></tr>
    272. 

  272. <tr>
    273. 

  273. <td align="left">ARM_MPU_REGION_SIZE_4MB </td><td align="left">0x15U </td><td align="left">Region size 4 MBytes </td></tr>
    274. 

  274. <tr>
    275. 

  275. <td align="left">ARM_MPU_REGION_SIZE_8MB </td><td align="left">0x16U </td><td align="left">Region size 8 MBytes </td></tr>
    276. 

  276. <tr>
    277. 

  277. <td align="left">ARM_MPU_REGION_SIZE_16MB </td><td align="left">0x17U </td><td align="left">Region size 16 MBytes </td></tr>
    278. 

  278. <tr>
    279. 

  279. <td align="left">ARM_MPU_REGION_SIZE_32MB </td><td align="left">0x18U </td><td align="left">Region size 32 MBytes </td></tr>
    280. 

  280. <tr>
    281. 

  281. <td align="left">ARM_MPU_REGION_SIZE_64MB </td><td align="left">0x19U </td><td align="left">Region size 64 MBytes </td></tr>
    282. 

  282. <tr>
    283. 

  283. <td align="left">ARM_MPU_REGION_SIZE_128MB </td><td align="left">0x1AU </td><td align="left">Region size 128 MBytes </td></tr>
    284. 

  284. <tr>
    285. 

  285. <td align="left">ARM_MPU_REGION_SIZE_256MB </td><td align="left">0x1BU </td><td align="left">Region size 256 MBytes </td></tr>
    286. 

  286. <tr>
    287. 

  287. <td align="left">ARM_MPU_REGION_SIZE_512MB </td><td align="left">0x1CU </td><td align="left">Region size 512 MBytes </td></tr>
    288. 

  288. <tr>
    289. 

  289. <td align="left">ARM_MPU_REGION_SIZE_1GB </td><td align="left">0x1DU </td><td align="left">Region size 1 GByte </td></tr>
    290. 

  290. <tr>
    291. 

  291. <td align="left">ARM_MPU_REGION_SIZE_2GB </td><td align="left">0x1EU </td><td align="left">Region size 2 GBytes </td></tr>
    292. 

  292. <tr>
    293. 

  293. <td align="left">ARM_MPU_REGION_SIZE_4GB </td><td align="left">0x1FU </td><td align="left">Region size 4 GBytes </td></tr>
    294. 

  294. </table>
    295. 

  295. 

  296. </div>
    297. 

  297. </div>
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