ARM-software
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CMSIS_5
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   <div id="projectname">CMSIS-Driver
   &#160;<span id="projectnumber">Version 2.8.0</span>
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   <div id="projectbrief">Peripheral Interface for Middleware and Application Code</div>
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<div class="title">Driver_NAND.c File Reference</div>  </div>
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Functions</h2></td></tr>
<tr class="memitem:ga01255fd4f15e7fa4751c7ea59648ef5a"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__common__drv__gr.html#structARM__DRIVER__VERSION">ARM_DRIVER_VERSION</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#ga01255fd4f15e7fa4751c7ea59648ef5a">ARM_NAND_GetVersion</a> (void)</td></tr>
<tr class="memdesc:ga01255fd4f15e7fa4751c7ea59648ef5a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get driver version.  <a href="group__nand__interface__gr.html#ga01255fd4f15e7fa4751c7ea59648ef5a">More...</a><br/></td></tr>
<tr class="separator:ga01255fd4f15e7fa4751c7ea59648ef5a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9f2609975c2008d21b9ae28f15daf147"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__nand__interface__gr.html#structARM__NAND__CAPABILITIES">ARM_NAND_CAPABILITIES</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#ga9f2609975c2008d21b9ae28f15daf147">ARM_NAND_GetCapabilities</a> (void)</td></tr>
<tr class="memdesc:ga9f2609975c2008d21b9ae28f15daf147"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get driver capabilities.  <a href="group__nand__interface__gr.html#ga9f2609975c2008d21b9ae28f15daf147">More...</a><br/></td></tr>
<tr class="separator:ga9f2609975c2008d21b9ae28f15daf147"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga74ad34718a595e7a4375b90f33e72750"><td class="memItemLeft" align="right" valign="top">int32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#ga74ad34718a595e7a4375b90f33e72750">ARM_NAND_Initialize</a> (<a class="el" href="group__nand__interface__gr.html#ga09f4cf2f2df0bb690bce38b13d77e50f">ARM_NAND_SignalEvent_t</a> cb_event)</td></tr>
<tr class="memdesc:ga74ad34718a595e7a4375b90f33e72750"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initialize the NAND Interface.  <a href="group__nand__interface__gr.html#ga74ad34718a595e7a4375b90f33e72750">More...</a><br/></td></tr>
<tr class="separator:ga74ad34718a595e7a4375b90f33e72750"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa788b638ab696b166fee2f4a4bc8d97a"><td class="memItemLeft" align="right" valign="top">int32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#gaa788b638ab696b166fee2f4a4bc8d97a">ARM_NAND_Uninitialize</a> (void)</td></tr>
<tr class="memdesc:gaa788b638ab696b166fee2f4a4bc8d97a"><td class="mdescLeft">&#160;</td><td class="mdescRight">De-initialize the NAND Interface.  <a href="group__nand__interface__gr.html#gaa788b638ab696b166fee2f4a4bc8d97a">More...</a><br/></td></tr>
<tr class="separator:gaa788b638ab696b166fee2f4a4bc8d97a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9c9975637980b5d42db7baba0191fda1"><td class="memItemLeft" align="right" valign="top">int32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#ga9c9975637980b5d42db7baba0191fda1">ARM_NAND_PowerControl</a> (<a class="el" href="group__common__drv__gr.html#ga47d6d7c31f88f3b8ae4aaf9d8444afa5">ARM_POWER_STATE</a> state)</td></tr>
<tr class="memdesc:ga9c9975637980b5d42db7baba0191fda1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Control the NAND interface power.  <a href="group__nand__interface__gr.html#ga9c9975637980b5d42db7baba0191fda1">More...</a><br/></td></tr>
<tr class="separator:ga9c9975637980b5d42db7baba0191fda1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga11adcbaaace09746581a36befbd563c9"><td class="memItemLeft" align="right" valign="top">int32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#ga11adcbaaace09746581a36befbd563c9">ARM_NAND_DevicePower</a> (uint32_t voltage)</td></tr>
<tr class="memdesc:ga11adcbaaace09746581a36befbd563c9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set device power supply voltage.  <a href="group__nand__interface__gr.html#ga11adcbaaace09746581a36befbd563c9">More...</a><br/></td></tr>
<tr class="separator:ga11adcbaaace09746581a36befbd563c9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1987e65a4e756d748db86332c9fb1cec"><td class="memItemLeft" align="right" valign="top">int32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#ga1987e65a4e756d748db86332c9fb1cec">ARM_NAND_WriteProtect</a> (uint32_t dev_num, bool enable)</td></tr>
<tr class="memdesc:ga1987e65a4e756d748db86332c9fb1cec"><td class="mdescLeft">&#160;</td><td class="mdescRight">Control WPn (Write Protect).  <a href="group__nand__interface__gr.html#ga1987e65a4e756d748db86332c9fb1cec">More...</a><br/></td></tr>
<tr class="separator:ga1987e65a4e756d748db86332c9fb1cec"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1c0cba87cb7b706ad5986dc67c831ad1"><td class="memItemLeft" align="right" valign="top">int32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#ga1c0cba87cb7b706ad5986dc67c831ad1">ARM_NAND_ChipEnable</a> (uint32_t dev_num, bool enable)</td></tr>
<tr class="memdesc:ga1c0cba87cb7b706ad5986dc67c831ad1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Control CEn (Chip Enable).  <a href="group__nand__interface__gr.html#ga1c0cba87cb7b706ad5986dc67c831ad1">More...</a><br/></td></tr>
<tr class="separator:ga1c0cba87cb7b706ad5986dc67c831ad1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga43011066306bd716b580e6aa9a80cf65"><td class="memItemLeft" align="right" valign="top">int32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#ga43011066306bd716b580e6aa9a80cf65">ARM_NAND_GetDeviceBusy</a> (uint32_t dev_num)</td></tr>
<tr class="memdesc:ga43011066306bd716b580e6aa9a80cf65"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get Device Busy pin state.  <a href="group__nand__interface__gr.html#ga43011066306bd716b580e6aa9a80cf65">More...</a><br/></td></tr>
<tr class="separator:ga43011066306bd716b580e6aa9a80cf65"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9f70b89ba478eadfe7f5dee7453a4fb7"><td class="memItemLeft" align="right" valign="top">int32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#ga9f70b89ba478eadfe7f5dee7453a4fb7">ARM_NAND_SendCommand</a> (uint32_t dev_num, uint8_t cmd)</td></tr>
<tr class="memdesc:ga9f70b89ba478eadfe7f5dee7453a4fb7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Send command to NAND device.  <a href="group__nand__interface__gr.html#ga9f70b89ba478eadfe7f5dee7453a4fb7">More...</a><br/></td></tr>
<tr class="separator:ga9f70b89ba478eadfe7f5dee7453a4fb7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga00e195031e03d364db7595858a7e76f3"><td class="memItemLeft" align="right" valign="top">int32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#ga00e195031e03d364db7595858a7e76f3">ARM_NAND_SendAddress</a> (uint32_t dev_num, uint8_t addr)</td></tr>
<tr class="memdesc:ga00e195031e03d364db7595858a7e76f3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Send address to NAND device.  <a href="group__nand__interface__gr.html#ga00e195031e03d364db7595858a7e76f3">More...</a><br/></td></tr>
<tr class="separator:ga00e195031e03d364db7595858a7e76f3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae1899a20ef107400c8bf84fad477a8ce"><td class="memItemLeft" align="right" valign="top">int32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#gae1899a20ef107400c8bf84fad477a8ce">ARM_NAND_ReadData</a> (uint32_t dev_num, void *data, uint32_t cnt, uint32_t mode)</td></tr>
<tr class="memdesc:gae1899a20ef107400c8bf84fad477a8ce"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read data from NAND device.  <a href="group__nand__interface__gr.html#gae1899a20ef107400c8bf84fad477a8ce">More...</a><br/></td></tr>
<tr class="separator:gae1899a20ef107400c8bf84fad477a8ce"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1fa497dd51a86fc308e946b4419fd006"><td class="memItemLeft" align="right" valign="top">int32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#ga1fa497dd51a86fc308e946b4419fd006">ARM_NAND_WriteData</a> (uint32_t dev_num, const void *data, uint32_t cnt, uint32_t mode)</td></tr>
<tr class="memdesc:ga1fa497dd51a86fc308e946b4419fd006"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write data to NAND device.  <a href="group__nand__interface__gr.html#ga1fa497dd51a86fc308e946b4419fd006">More...</a><br/></td></tr>
<tr class="separator:ga1fa497dd51a86fc308e946b4419fd006"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8a0108dba757a4610475151144b52825"><td class="memItemLeft" align="right" valign="top">int32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#ga8a0108dba757a4610475151144b52825">ARM_NAND_ExecuteSequence</a> (uint32_t dev_num, uint32_t code, uint32_t cmd, uint32_t addr_col, uint32_t addr_row, void *data, uint32_t data_cnt, uint8_t *status, uint32_t *count)</td></tr>
<tr class="memdesc:ga8a0108dba757a4610475151144b52825"><td class="mdescLeft">&#160;</td><td class="mdescRight">Execute sequence of operations.  <a href="group__nand__interface__gr.html#ga8a0108dba757a4610475151144b52825">More...</a><br/></td></tr>
<tr class="separator:ga8a0108dba757a4610475151144b52825"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga00832861f018db0d8368900b099ecd30"><td class="memItemLeft" align="right" valign="top">int32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#ga00832861f018db0d8368900b099ecd30">ARM_NAND_AbortSequence</a> (uint32_t dev_num)</td></tr>
<tr class="memdesc:ga00832861f018db0d8368900b099ecd30"><td class="mdescLeft">&#160;</td><td class="mdescRight">Abort sequence execution.  <a href="group__nand__interface__gr.html#ga00832861f018db0d8368900b099ecd30">More...</a><br/></td></tr>
<tr class="separator:ga00832861f018db0d8368900b099ecd30"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga83061d6d53ffb148853efbc87a864607"><td class="memItemLeft" align="right" valign="top">int32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#ga83061d6d53ffb148853efbc87a864607">ARM_NAND_Control</a> (uint32_t dev_num, uint32_t control, uint32_t arg)</td></tr>
<tr class="memdesc:ga83061d6d53ffb148853efbc87a864607"><td class="mdescLeft">&#160;</td><td class="mdescRight">Control NAND Interface.  <a href="group__nand__interface__gr.html#ga83061d6d53ffb148853efbc87a864607">More...</a><br/></td></tr>
<tr class="separator:ga83061d6d53ffb148853efbc87a864607"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4578642f37a556b58b0bba0ad5d42641"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__nand__interface__gr.html#structARM__NAND__STATUS">ARM_NAND_STATUS</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#ga4578642f37a556b58b0bba0ad5d42641">ARM_NAND_GetStatus</a> (uint32_t dev_num)</td></tr>
<tr class="memdesc:ga4578642f37a556b58b0bba0ad5d42641"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get NAND status.  <a href="group__nand__interface__gr.html#ga4578642f37a556b58b0bba0ad5d42641">More...</a><br/></td></tr>
<tr class="separator:ga4578642f37a556b58b0bba0ad5d42641"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac21425454d586ef48fdfc35e7bd78947"><td class="memItemLeft" align="right" valign="top">int32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#gac21425454d586ef48fdfc35e7bd78947">ARM_NAND_InquireECC</a> (int32_t index, <a class="el" href="group__nand__interface__gr.html#structARM__NAND__ECC__INFO">ARM_NAND_ECC_INFO</a> *info)</td></tr>
<tr class="memdesc:gac21425454d586ef48fdfc35e7bd78947"><td class="mdescLeft">&#160;</td><td class="mdescRight">Inquire about available ECC.  <a href="group__nand__interface__gr.html#gac21425454d586ef48fdfc35e7bd78947">More...</a><br/></td></tr>
<tr class="separator:gac21425454d586ef48fdfc35e7bd78947"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf4ce80b0fd6717de7ddfb1cfaf7dd754"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__interface__gr.html#gaf4ce80b0fd6717de7ddfb1cfaf7dd754">ARM_NAND_SignalEvent</a> (uint32_t dev_num, uint32_t event)</td></tr>
<tr class="memdesc:gaf4ce80b0fd6717de7ddfb1cfaf7dd754"><td class="mdescLeft">&#160;</td><td class="mdescRight">Signal NAND event.  <a href="group__nand__interface__gr.html#gaf4ce80b0fd6717de7ddfb1cfaf7dd754">More...</a><br/></td></tr>
<tr class="separator:gaf4ce80b0fd6717de7ddfb1cfaf7dd754"><td class="memSeparator" colspan="2">&#160;</td></tr>
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