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CMSIS_5
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   <div id="projectname">CMSIS-SVD
   &#160;<span id="projectnumber">Version 1.3.6</span>
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   <div id="projectbrief">CMSIS System View Description</div>
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<div class="title">/device/cpu element </div>  </div>
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<div class="textblock"><p>The CPU section describes the processor included in the microcontroller device. This section is mandatory if the SVD file is used to generate the device header file.</p>
<p><b>Example</b> </p>
<div class="fragment"><div class="line">&lt;device&gt;</div>
<div class="line">  ...</div>
<div class="line">  &lt;cpu&gt;</div>
<div class="line">    &lt;name&gt;CM7&lt;/name&gt; </div>
<div class="line">    &lt;revision&gt;r0p0&lt;/revision&gt;</div>
<div class="line">    &lt;endian&gt;little&lt;/endian&gt;</div>
<div class="line">    &lt;mpuPresent&gt;<span class="keyword">true</span>&lt;/mpuPresent&gt;</div>
<div class="line">    &lt;!-- has <span class="keywordtype">double</span> precision FPU --&gt;</div>
<div class="line">    &lt;fpuPresent&gt;<span class="keyword">true</span>&lt;/fpuPresent&gt;</div>
<div class="line">    &lt;fpuDP&gt;<span class="keyword">true</span>&lt;/fpuDP&gt;</div>
<div class="line">    &lt;!-- has instruction and data cache --&gt;</div>
<div class="line">    &lt;icachePresent&gt;<span class="keyword">true</span>&lt;/icachePresent&gt;</div>
<div class="line">    &lt;dcachePresent&gt;<span class="keyword">true</span>&lt;/dcachePresent&gt;</div>
<div class="line">    &lt;!-- has no instruction nor data tighly coupled memory --&gt;</div>
<div class="line">    &lt;itcmPresent&gt;<span class="keyword">false</span>&lt;/itcmPresent&gt;</div>
<div class="line">    &lt;dtcmPresent&gt;<span class="keyword">false</span>&lt;/dtcmPresent&gt;</div>
<div class="line">    &lt;nvicPrioBits&gt;4&lt;/nvicPrioBits&gt;</div>
<div class="line">    &lt;vendorSystickConfig&gt;<span class="keyword">false</span>&lt;/vendorSystickConfig&gt; </div>
<div class="line">  &lt;/cpu&gt;</div>
<div class="line">  ...</div>
<div class="line">&lt;device&gt;</div>
</div><!-- fragment --><p>This example describes a device based on a <span class="XML-Token">Cortex-M7</span> core of HW revision <span class="XML-Token">r0p0</span>, with fixed <span class="XML-Token">little</span> endian memory scheme, including <span class="XML-Token">Memory Protection Unit</span> and <span class="XML-Token">double precision hardware Floating Point Unit</span>. It has a <span class="XML-Token">data cache</span> and no <span class="XML-Token">instruction</span> nor a tightly coupled memory. The Nested Vectored Interrupt Controller uses <span class="XML-Token">4</span> bits to configure the priority of an interrupt. It is equipped with the standard System Tick Timer as defined by Arm.</p>
<p><a class="anchor" id="elem_cpu_sc"></a><b>/device/cpu</b> </p>
<table  class="cmtable" summary="CPU Section Elements">
<tr>
<th style="white-space:nowrap">Parent Element </th><th colspan="3">Element Chain  </th></tr>
<tr>
<td><a class="el" href="elem_device.html">device</a> </td><td colspan="3"><a class="el" href="elem_device.html">/device</a>  </td></tr>
<tr>
<th style="white-space:nowrap">Child Elements </th><th>Description </th><th>Type </th><th>Occurrence  </th></tr>
<tr>
<td>name </td><td>The predefined tokens are:<ul>
<li><span class="XML-Token">CM0</span>: Arm Cortex-M0</li>
<li><span class="XML-Token">CM0PLUS</span>: Arm Cortex-M0+</li>
<li><span class="XML-Token">CM0+</span>: Arm Cortex-M0+</li>
<li><span class="XML-Token">CM1</span>: Arm Cortex-M1</li>
<li><span class="XML-Token">SC000</span>: Arm Secure Core SC000</li>
<li><span class="XML-Token">CM23</span>: Arm Cortex-M23</li>
<li><span class="XML-Token">CM3</span>: Arm Cortex-M3</li>
<li><span class="XML-Token">CM33</span>: Arm Cortex-M33</li>
<li><span class="XML-Token">CM35P</span>: Arm Cortex-M35P</li>
<li><span class="XML-Token">SC300</span>: Arm Secure Core SC300</li>
<li><span class="XML-Token">CM4</span>: Arm Cortex-M4</li>
<li><span class="XML-Token">CM7</span>: Arm Cortex-M7</li>
<li><span class="XML-Token">CA5</span>: Arm Cortex-A5</li>
<li><span class="XML-Token">CA7</span>: Arm Cortex-A7</li>
<li><span class="XML-Token">CA8</span>: Arm Cortex-A8</li>
<li><span class="XML-Token">CA9</span>: Arm Cortex-A9</li>
<li><span class="XML-Token">CA15</span>: Arm Cortex-A15</li>
<li><span class="XML-Token">CA17</span>: Arm Cortex-A17</li>
<li><span class="XML-Token">CA53</span>: Arm Cortex-A53</li>
<li><span class="XML-Token">CA57</span>: Arm Cortex-A57</li>
<li><span class="XML-Token">CA72</span>: Arm Cortex-A72</li>
<li><span class="XML-Token">other</span>: other processor architectures  </li>
</ul>
</td><td>cpuNameType  </td><td>1..1   </td></tr>
<tr>
<td>revision </td><td>Define the HW revision of the processor. The version format is <span class="XML-Token">r<em>N</em>p<em>M</em></span> (N,M = [0 - 99]).  </td><td>revisionType </td><td>1..1   </td></tr>
<tr>
<td>endian  </td><td>Define the endianness of the processor being one of:<ul>
<li><span class="XML-Token">little</span>: little endian memory (least significant byte gets allocated at the lowest address).</li>
<li><span class="XML-Token">big</span>: byte invariant big endian data organization (most significant byte gets allocated at the lowest address).</li>
<li><span class="XML-Token">selectable</span>: little and big endian are configurable for the device and become active after the next reset.</li>
<li><span class="XML-Token">other</span>: the endianness is neither little nor big endian.  </li>
</ul>
</td><td>endianType  </td><td>1..1   </td></tr>
<tr>
<td>mpuPresent  </td><td>Indicate whether the processor is equipped with a memory protection unit (MPU). This tag is either set to <span class="XML-Token">true</span> or <span class="XML-Token">false</span>, <span class="XML-Token">1</span> or <span class="XML-Token">0</span>. </td><td>boolean  </td><td>1..1   </td></tr>
<tr>
<td>fpuPresent  </td><td>Indicate whether the processor is equipped with a hardware floating point unit (FPU). Cortex-M4, Cortex-M7, Cortex-M33 and Cortex-M35P are the only available Cortex-M processor with an optional FPU. This tag is either set to <span class="XML-Token">true</span> or <span class="XML-Token">false</span>, <span class="XML-Token">1</span> or <span class="XML-Token">0</span>. </td><td>boolean  </td><td>1..1   </td></tr>
<tr>
<td>fpuDP  </td><td>Indicate whether the processor is equipped with a double precision floating point unit. This element is valid only when <em>&lt;fpuPresent&gt;</em> is set to <span class="XML-Token">true</span>. Currently, only Cortex-M7 processors can have a double precision floating point unit. </td><td>boolean </td><td>0..1   </td></tr>
<tr>
<td>dspPresent  </td><td>Indicates whether the processor implements the optional SIMD DSP extensions (DSP). Cortex-M33 and Cortex-M35P are the only available Cortex-M processor with an optional DSP extension. For ARMv7M SIMD DSP extensions are a mandatory part of Cortex-M4 and Cortex-M7. This tag is either set to <span class="XML-Token">true</span> or <span class="XML-Token">false</span>, <span class="XML-Token">1</span> or <span class="XML-Token">0</span>.. This element is mandatory for Cortex-M33, Cortex-M35P and future processors with optional SIMD DSP instruction set. </td><td>boolean  </td><td>0..1   </td></tr>
<tr>
<td>icachePresent </td><td>Indicate whether the processor has an instruction cache. Note: only for Cortex-M7-based devices.  </td><td>boolean  </td><td>0..1   </td></tr>
<tr>
<td>dcachePresent </td><td>Indicate whether the processor has a data cache. Note: only for Cortex-M7-based devices.  </td><td>boolean  </td><td>0..1   </td></tr>
<tr>
<td>itcmPresent </td><td>Indicate whether the processor has an instruction tightly coupled memory. Note: only an option for Cortex-M7-based devices.  </td><td>boolean  </td><td>0..1   </td></tr>
<tr>
<td>dtcmPresent </td><td>Indicate whether the processor has a data tightly coupled memory. Note: only for Cortex-M7-based devices.  </td><td>boolean  </td><td>0..1   </td></tr>
<tr>
<td>vtorPresent  </td><td>Indicate whether the Vector Table Offset Register (VTOR) is implemented in Cortex-M0+ based devices. This tag is either set to <span class="XML-Token">true</span> or <span class="XML-Token">false</span>, <span class="XML-Token">1</span> or <span class="XML-Token">0</span>. If not specified, then VTOR is assumed to be present. </td><td>boolean  </td><td>0..1   </td></tr>
<tr>
<td>nvicPrioBits  </td><td>Define the number of bits available in the Nested Vectored Interrupt Controller (NVIC) for configuring priority. </td><td>scaledNonNegativeInteger  </td><td>1..1   </td></tr>
<tr>
<td>vendorSystickConfig </td><td>Indicate whether the processor implements a vendor-specific System Tick Timer. If <span class="XML-Token">false</span>, then the Arm-defined System Tick Timer is available. If <span class="XML-Token">true</span>, then a vendor-specific System Tick Timer must be implemented. This tag is either set to <span class="XML-Token">true</span> or <span class="XML-Token">false</span>, <span class="XML-Token">1</span> or <span class="XML-Token">0</span>. </td><td>boolean  </td><td>1..1   </td></tr>
<tr>
<td>deviceNumInterrupts </td><td>Add <span class="XML-Token">1</span> to the highest interrupt number and specify this number in here. You can start to enumerate interrupts from <span class="XML-Token">0</span>. Gaps might exist between interrupts. For example, you have defined interrupts with the numbers <span class="XML-Token">1</span>, <span class="XML-Token">2</span>, and <span class="XML-Token">8</span>. Add <span class="XML-Token">9 :(8+1)</span> into this field. </td><td>scaledNonNegativeInteger </td><td>0..1   </td></tr>
<tr>
<td>sauNumRegions </td><td>Indicate the amount of regions in the Security Attribution Unit (SAU). If the value is greater than zero, then the device has a SAU and the number indicates the maximum amount of available address regions.  </td><td>scaledNonNegativeInteger  </td><td>0..1   </td></tr>
<tr>
<td><a class="el" href="elem_cpu.html#elem_sauRegionsConfig">sauRegionsConfig</a> </td><td>If the Secure Attribution Unit is preconfigured by HW or Firmware, then the settings are described here. </td><td>SauRegionsConfigType </td><td>0..1   </td></tr>
</table>
<p>&#160;</p>
<hr/>
<h1><a class="anchor" id="elem_sauRegionsConfig"></a>
/device/cpu/sauRegionsConfig element</h1>
<p>Set the configuration for the Secure Attribution Unit (SAU) when they are preconfigured by HW or Firmware.</p>
<p><b>Example</b> </p>
<div class="fragment"><div class="line">&lt;device&gt;</div>
<div class="line">  ...</div>
<div class="line">  &lt;sauRegionsConfig protectionWhenDisabled=<span class="stringliteral">&quot;n&quot;</span>&gt;</div>
<div class="line">    &lt;region&gt;</div>
<div class="line">      ...</div>
<div class="line">    &lt;/region&gt;</div>
<div class="line">    ...</div>
<div class="line">    &lt;region&gt;</div>
<div class="line">      ...</div>
<div class="line">    &lt;/region&gt;</div>
<div class="line">  &lt;/sauRegionsConfig&gt;</div>
<div class="line">  ...</div>
<div class="line">&lt;/device&gt;</div>
</div><!-- fragment --><p>The example defines two Secure Attribution Units, which are enabled by default. When the SAU regions are disabled, the protection level is non-secure (<span class="XML-Token">n</span>).</p>
<p><a class="anchor" id="elem_sauRegionsConfig_sc"></a><b>/device/cpu/sauRegionsConfig</b> </p>
<table  class="cmtable" summary="sauRegionsConfig tab elements">
<tr>
<th style="white-space:nowrap">Parent Element </th><th colspan="3">Element Chain  </th></tr>
<tr>
<td><a class="el" href="elem_cpu.html">cpu</a> </td><td colspan="3"><a class="el" href="elem_cpu.html">/device/cpu element</a>  </td></tr>
<tr>
<th style="white-space:nowrap">Attributes </th><th>Description </th><th>Type </th><th>Use  </th></tr>
<tr>
<td>enabled </td><td>Specify whether the Secure Attribution Units are enabled. The following values can be used: <span class="XML-Token">true</span>,<span class="XML-Token">false</span>,<span class="XML-Token">1</span>, and <span class="XML-Token">0</span>.  </td><td>xs:boolean </td><td>optional  </td></tr>
<tr>
<td><a class="el" href="elem_special.html#elem_protection">protectionWhenDisabled</a> </td><td>Set the protection mode for disabled regions. When the complete SAU is disabled, the whole memory is treated either <span class="XML-Token">"s"</span>=secure or <span class="XML-Token">"n"</span>=non-secure. This value is inherited by the <em>&lt;region&gt;</em> element. Refer to element <a class="el" href="elem_special.html#elem_protection">protection</a> for details and predefined values.  </td><td>xs:string </td><td>optional  </td></tr>
<tr>
<th style="white-space:nowrap">Child Elements </th><th>Description </th><th>Type </th><th>Occurrence  </th></tr>
<tr>
<td><a class="el" href="elem_cpu.html#elem_region">region</a> </td><td>Group to configure SAU regions. </td><td>xs:string </td><td>0..*  </td></tr>
</table>
<p>&#160;</p>
<hr/>
<h1><a class="anchor" id="elem_region"></a>
/device/cpu/sauRegionsConfig/region element</h1>
<p>Define the regions of the Secure Attribution Unit (SAU). The protection level is inherited from the attribute <em>&lt;protectionWhenDisabled&gt;</em> of the enclosing element <a class="el" href="elem_cpu.html#elem_sauRegionsConfig">sauRegionsConfig</a>.</p>
<p><b>Example:</b> </p>
<div class="fragment"><div class="line">&lt;sauRegionsConfig&gt;</div>
<div class="line">  &lt;region name=<span class="stringliteral">&quot;SAU1&quot;</span>&gt;</div>
<div class="line">    &lt;base&gt;0x10001000&lt;/base&gt;</div>
<div class="line">    &lt;limit&gt;0x10005000&lt;/limit&gt;</div>
<div class="line">    &lt;access&gt;n&lt;/access&gt;</div>
<div class="line">  &lt;/region&gt;</div>
<div class="line">  &lt;region enabled=<span class="stringliteral">&quot;false&quot;</span> name=<span class="stringliteral">&quot;SAU2&quot;</span>&gt;</div>
<div class="line">    &lt;base&gt;0x10006000&lt;/base&gt;</div>
<div class="line">    &lt;limit&gt;0x10008000&lt;/limit&gt;</div>
<div class="line">    &lt;access&gt;c&lt;/access&gt;</div>
<div class="line">  &lt;/region&gt;</div>
<div class="line">&lt;/sauRegionsConfig&gt;</div>
</div><!-- fragment --><p>The example defines two secure regions with the names <em>SAU1</em> and <em>SAU2</em>. SAU1 has the address boundries <span class="XML-Token">0x10001000</span> and <span class="XML-Token">0x10005000</span>. The region has non-secure access rights. SAU2 has the address boundries <span class="XML-Token">0x10006000</span> and <span class="XML-Token">0x10008000</span>. The region has secure callable access rights.</p>
<p><a class="anchor" id="elem_region_sc"></a> <b>/device/cpu/sauRegionsConfig/region</b> </p>
<table  class="cmtable" summary="region tab elements">
<tr>
<th style="white-space:nowrap">Parent Element </th><th colspan="3">Element Chain  </th></tr>
<tr>
<td><a class="el" href="elem_cpu.html#elem_sauRegionsConfig">sauRegionsConfig</a> </td><td colspan="3"><a class="el" href="elem_cpu.html#elem_sauRegionsConfig">/device/cpu/sauRegionsConfig element</a>   </td></tr>
<tr>
<th style="white-space:nowrap">Attributes </th><th>Description </th><th>Type </th><th>Use  </th></tr>
<tr>
<td>enabled </td><td>Specify whether the Secure Attribution Units are enabled. The following values can be used: <span class="XML-Token">true</span> and <span class="XML-Token">false</span>, or <span class="XML-Token">1</span> and <span class="XML-Token">0</span>. Default value is <span class="XML-Token">true</span>. </td><td>xs:boolean </td><td>optional  </td></tr>
<tr>
<td>name </td><td>Identifiy the region with a name.  </td><td>xs:string </td><td>optional  </td></tr>
<tr>
<th style="white-space:nowrap">Child Elements </th><th>Description </th><th>Type </th><th>Occurrence  </th></tr>
<tr>
<td>base </td><td>Base address of the region. </td><td>scaledNonNegativeInteger </td><td>1..1  </td></tr>
<tr>
<td>limit </td><td>Limit address of the region. </td><td>scaledNonNegativeInteger </td><td>1..1  </td></tr>
<tr>
<td>access </td><td>Use one of the following predefined values to define the acces type of a region: <br/>
 - <span class="XML-Token">n</span> : non-secure <br/>
 - <span class="XML-Token">c</span> : secure callable </td><td>xs:string </td><td>1..1  </td></tr>
</table>
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