Keil.LPC1800_DFP.pdsc.txt 67 KB

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  1. <?xml version="1.0" encoding="UTF-8"?>
  2. <package schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="PACK.xsd">
  3. <vendor>Keil</vendor>
  4. <url>http://www.keil.com/pack/</url>
  5. <name>LPC1800_DFP</name>
  6. <description>NXP LPC1800 Series Device Support, Drivers and Examples</description>
  7. <releases>
  8. <release version="2.7.0-rel">
  9. CMSIS device:
  10. - corrected doxy comments is system file
  11. CMSIS driver:
  12. - Updated SSP:
  13. -- corrected PIN Configuration and Unconfiguration
  14. - Updated CAN:
  15. -- corrected receive overrun clearing and signaling
  16. -- corrected interrupt routine (status interrupt could case lockup)
  17. -- corrected functionality when NULL pointer is provided for one or both
  18. signal callbacks in Initialize function call
  19. -- corrected CAN1 IRQ routine
  20. -- corrected MessageSend function to return busy if transmission is in progress
  21. </release>
  22. <release version="2.6.0" date="2016-02-01">
  23. Updated GPDMA driver to transfer data larger than 4k.
  24. CMSIS driver:
  25. - added CAN: driver and configuration options in RTE_Device.h
  26. - updated all: corrected PowerControl function for conditional Power full state (driver must be initialized)
  27. - updated USART, I2S, SSP: interwork with new GPDMA driver
  28. - updated I2C: pending IRQ flag cleared after aborted transfer
  29. - updated USB Device: removed unnecessary __packed specifier for GCC compliance
  30. - updated EMAC: corrected return value of the ReadFrame function
  31. Board examples for Keil MCB1800:
  32. - added CAN Data and CAN RTR MDK projects
  33. </release>
  34. <release version="2.5.0" date="2015-06-19">
  35. Updated CMSIS drivers:
  36. - I2C, MCI, EMAC, I2S, SPI, USART, USB Device, USB Host: Updated initialization, uninitialization and power procedures
  37. - I2S, SPI, USART, USB Device, USB Host: Corrected status bit-field race conditions
  38. - MCI:
  39. -- Interrupt processing optimized
  40. -- Data timeout handling corrected
  41. Updated example for USB device VirtualCOM
  42. </release>
  43. <release version="2.4.0" date="2015-04-24">
  44. Device support:
  45. - added LPC18Sxx series devices
  46. - updated device features
  47. Updated CMSIS Driver:
  48. - I2S: improved fs divider calculation
  49. - MCI: avoid DMA buffer alignment issues
  50. - USART:
  51. -- corrected disabling of receive DMA channel when aborting Receive or Transfer
  52. -- moved fract_div_lookup_table from header file to driver .c file
  53. Updated Example for USB Device Mass Storage
  54. </release>
  55. <release version="2.3.0" date="2015-03-20">
  56. Required PACKs: ARM.CMSIS.4.3.0.pack, Keil.MDK-Middleware.6.3.0.pack, Keil.ARM_Compiler.1.0.0.pack
  57. Updated device support files:
  58. - LPC18xx.h (added FLASHCFGA, FLASHCFGB register)
  59. Updated drivers:
  60. - RTE_Device.h (driver configuration):
  61. -- corrected RTE_USB1_IND0_PIN_EN into RTE_USB1_IND1_PIN_EN
  62. -- removed RTE_USB_USB0_DEV_EP and RTE_USB_USB1_DEV_EP
  63. - EMAC: corrected return value of PHY_Read and PHY_Write functions
  64. - MCI: enabled High speed capability and added block size handling
  65. - SSP: corrected pin handling, ssp->info->mode handling
  66. - USART: improved baudrate calculation
  67. - USB Device:
  68. -- corrected isochronous endpoint configuration
  69. -- corrected transfer procedure
  70. -- corrected CLK_M4_USB1_CFG into CLK_M4_USB0_CFG in USBD_PowerControl function
  71. Added:
  72. - I2S driver
  73. - USB Device Audio example
  74. - Audio Board interface for MCB1800 Evaluation Board
  75. Updated examples:
  76. - Compiler I/O software component is now used for I/O retargeting
  77. </release>
  78. <release version="2.2.0" date="2014-12-11">
  79. Updated for use with MDK-Middleware Version 6.2:
  80. - File_Demo and USB Host MassStorage examples due to new fdelete() API in File System 6.2
  81. - emWin GUIDemo example (corrected JOYSTICK orientation)
  82. Corrected:
  83. - USBD0 driver corrected PORTSC1_D_PFSC into USB_PORTSC1_D_PFSC
  84. - SCU driver SCU_SFSCLKx(clk_pin) and SCU_ENAIOx(n) macros
  85. - USART driver modem lines handling
  86. - SPI0/1 driver avoid stack corruption
  87. - GPDMA driver initialization and uninitialization is done from drivers
  88. - ETH driver implemented GetMacAddress function
  89. Updated SVD file.
  90. </release>
  91. <release version="2.1.0" date="2014-07-15">
  92. Corrected Touch calibration in GUIDemo example (for use with Keil.MDK-Middleware.6.1.0)
  93. Corrected conditions for SPI drivers and ARM Compiler toolchain dependency
  94. Updated USB Device drivers
  95. Updated Flash Programming Algorithm
  96. </release>
  97. <release version="2.0.0" date="2014-06-12">
  98. CMSIS Driver V2 compliant drivers (requires ARM.CMSIS.4.1.0)
  99. - I2C, MCI, SSP, USART, USB Host and Device, Ethernet MAC
  100. Examples for MCB1800 Evaluation Board (requires Keil.MDK-Middleware.6.0.0)
  101. - USB, Network, Graphics and Filesystem
  102. Board Support Interface drivers
  103. - ADC, Buttons, Joystick, Graphic LCD, Touchscreen, EEPROM, Thermometer
  104. </release>
  105. <release version="1.0.6">
  106. Renamed subFamilies to 185x for example.
  107. </release>
  108. <release version="1.0.5">
  109. Updated device description with features, added MCB1800 Board description
  110. </release>
  111. <release version="1.0.4">
  112. Updated I2C driver
  113. USB Device drivers re-implemented
  114. </release>
  115. <release version="1.0.3">
  116. Updated devices list
  117. </release>
  118. <release version="1.0.2">
  119. Updated drivers (namespace prefix ARM_ added)
  120. </release>
  121. <release version="1.0.1">
  122. Synchronized Middleware examples to Keil Middleware version 5.0.1
  123. </release>
  124. <release version="1.0.0">
  125. Beta version of LPC1800 Device Family Pack.
  126. </release>
  127. </releases>
  128. <keywords>
  129. <!-- keywords for indexing -->
  130. <keyword>NXP</keyword>
  131. <keyword>Device Support</keyword>
  132. <keyword>Device Family Package NXP</keyword>
  133. <keyword>LPC1800</keyword>
  134. <keyword>LPC18xx</keyword>
  135. </keywords>
  136. <devices>
  137. <family Dfamily="LPC1800 Series" Dvendor="NXP:11">
  138. <processor Dcore="Cortex-M3" DcoreVersion="r2p1" Dfpu="0" Dmpu="1" Dendian="Little-endian" Dclock="180000000"/>
  139. <debug svd="SVD/LPC18xx.svd">
  140. <!-- Make ETB always visible in ROM Table (otherwise only visible after clearing ETBCFG register) -->
  141. <datapatch address="0xE00FF018" value="0xFFF43003" info="ROM Table Entry: ETB"/>
  142. </debug>
  143. <debugvars configfile="Debug/LPC18xx.dbgconf">
  144. __var VecResetWithPeriph = 1; // Reset peripherals on Vector Reset
  145. // TPIU Pin Routing (TRACECLK fixed on PF_4)
  146. // - Bit 0: TRACEDATA[0]: 0 - PF_5, 1 - P7_4
  147. // - Bit 1: TRACEDATA[1]: 0 - PF_6, 1 - P7_5
  148. // - Bit 2: TRACEDATA[2]: 0 - PF_7, 1 - P7_6
  149. // - Bit 3: TRACEDATA[3]: 0 - PF_8, 1 - P7_7
  150. __var RoutingTPIU = 0x00000000; // Default selection (MCB1800)
  151. </debugvars>
  152. <sequences>
  153. <!-- Pre-defined Debug Access Sequences -->
  154. <!-- Begin: Pre-defined ResetProcessor Sequence -->
  155. <sequence name="ResetSystem">
  156. <!-- Default implementation -->
  157. <block>
  158. // Execute VECTRESET via AIRCR
  159. Write32(0xE000ED0C, 0x05FA0001);
  160. </block>
  161. <control if="VecResetWithPeriph">
  162. <block>
  163. // Reset peripherals
  164. Write32(0x40053100, 0xFFDF0030); // RESET_CTRL0
  165. Write32(0x40053104, 0xFFFFFFFF); // RESET_CTRL1
  166. </block>
  167. </control>
  168. </sequence>
  169. <!-- End: Pre-defined ResetProcessor Sequence -->
  170. <!-- Begin: Pre-defined ResetCatchSet Sequence -->
  171. <sequence name="ResetCatchSet">
  172. <block>
  173. __var chipID = 0;
  174. // Read chip ID
  175. chipID = Read32(0x40043200);
  176. </block>
  177. <control if="chipID == 0x4284E02B">
  178. <!-- LPC1857/53 (parts with on-chip flash) -->
  179. <block>
  180. __var resetVecBankA = 0;
  181. __var resetVecBankB = 0;
  182. // Clear Reset Vector Catch
  183. Write32(0xE000EDFC, Read32(0xE000EDFC) &amp; (~0x00000001));
  184. // Read reset vector from bank A
  185. resetVecBankA = Read32(0x1A000004);
  186. // Read reset vector from bank B
  187. resetVecBankB = Read32(0x1B000004);
  188. </block>
  189. <control if="resetVecBankA &lt; 0x20000000">
  190. <!-- Reset Vector of bank A in HW Breakpoint range-->
  191. <control if="(resetVecBankA &amp; 0x2) == 0">
  192. <block>
  193. // Even Address
  194. Write32(0xE0002008, (resetVecBankA &amp; 0x1FFFFFFC) | 0x40000001); // Write address to FPB Comparator 0
  195. </block>
  196. </control>
  197. <control if="resetVecBankA &amp; 0x2">
  198. <block>
  199. // Odd Address
  200. Write32(0xE0002008, (resetVecBankA &amp; 0x1FFFFFFC) | 0x80000001); // Write address to FPB Comparator 0
  201. </block>
  202. </control>
  203. </control>
  204. <control if="resetVecBankB &lt; 0x20000000">
  205. <!-- Reset Vector of bank B in HW Breakpoint range-->
  206. <control if="(resetVecBankB &amp; 0x2) == 0">
  207. <block>
  208. // Even Address
  209. Write32(0xE000200C, (resetVecBankB &amp; 0x1FFFFFFC) | 0x40000001); // Write address to FPB Comparator 1
  210. </block>
  211. </control>
  212. <control if="resetVecBankA &amp; 0x2">
  213. <block>
  214. // Odd Address
  215. Write32(0xE000200C, (resetVecBankB &amp; 0x1FFFFFFC) | 0x80000001); // Write address to FPB Comparator 1
  216. </block>
  217. </control>
  218. </control>
  219. <block>
  220. // Enable FPB
  221. Write32(0xE0002000, 0x00000003);
  222. </block>
  223. </control>
  224. </sequence>
  225. <!-- End: Pre-defined ResetCatchSet Sequence -->
  226. <!-- Begin: Pre-defined ResetCatchClear Sequence -->
  227. <sequence name="ResetCatchClear">
  228. <block>
  229. // Clear FPB Comparators 0 and 1
  230. Write32(0xE0002008, 0x00000000);
  231. Write32(0xE000200C, 0x00000000);
  232. // Disable FPB
  233. Write32(0xE0002000, 0x00000002);
  234. </block>
  235. </sequence>
  236. <!-- End: Pre-defined ResetCatchClear Sequence -->
  237. <!-- Begin: Pre-defined TraceStart Sequence -->
  238. <sequence name="TraceStart">
  239. <block>
  240. // Nothing required for SWO Trace
  241. __var traceTPIU = (__traceout &amp; 0x2) != 0;
  242. __var traceBuffer = (__traceout &amp; 0x4) != 0;
  243. </block>
  244. <control if="traceTPIU">
  245. <block>
  246. Sequence("EnableTraceTPIU");
  247. </block>
  248. </control>
  249. <control if="traceBuffer">
  250. <block>
  251. Sequence("EnableTraceBuffer");
  252. </block>
  253. </control>
  254. </sequence>
  255. <!-- End: Pre-defined TraceStart Sequence -->
  256. <!-- Begin: Pre-defined TraceStop Sequence -->
  257. <sequence name="TraceStop">
  258. <block>
  259. // Nothing required for SWO Trace
  260. __var traceTPIU = (__traceout &amp; 0x2) != 0;
  261. __var traceBuffer = (__traceout &amp; 0x4) != 0;
  262. </block>
  263. <control if="traceTPIU">
  264. <block>
  265. Sequence("DisableTraceTPIU");
  266. </block>
  267. </control>
  268. <control if="traceBuffer">
  269. <block>
  270. Sequence("DisableTraceBuffer");
  271. </block>
  272. </control>
  273. </sequence>
  274. <!-- End: Pre-defined TraceStop Sequence -->
  275. <!-- User-defined Debug Access Sequences -->
  276. <!-- Begin: User-defined EnableTraceTPIU Sequence -->
  277. <sequence name="EnableTraceTPIU">
  278. <block>
  279. __var tracePortWidth = (__traceout &amp; 0x003F0000) &gt;&gt; 16;
  280. // Setup fixed TRACECLK pin
  281. Write32(0x40086790, 0x000000B2); // LPC_SCU->SFSPF_4 : Func 2, EPD 0, EPUN 1, EHS 1, EZI 0, ZIF 1
  282. </block>
  283. <!-- TRACEDATA[0]-->
  284. <control if="(RoutingTPIU &amp; 0x1) == 0">
  285. <!-- TRACEDATA[0]: PF_5 -->
  286. <block>
  287. Write32(0x40086794, 0x000000B3); // LPC_SCU->SFSPF_5 : Func 3, EPD 0, EPUN 1, EHS 1, EZI 0, ZIF 1
  288. </block>
  289. </control>
  290. <control if="(RoutingTPIU &amp; 0x1)">
  291. <!-- TRACEDATA[0]: P7_4 -->
  292. <block>
  293. Write32(0x40086390, 0x000000B5); // LPC_SCU->SFSP7_4 : Func 5, EPD 0, EPUN 1, EHS 1, EZI 0, ZIF 1
  294. </block>
  295. </control>
  296. <control if="tracePortWidth &gt;= 2">
  297. <!-- TRACEDATA[1]-->
  298. <control if="(RoutingTPIU &amp; 0x1) == 0">
  299. <!-- TRACEDATA[1]: PF_6 -->
  300. <block>
  301. Write32(0x40086798, 0x000000B3); // LPC_SCU->SFSPF_6 : Func 3, EPD 0, EPUN 1, EHS 1, EZI 0, ZIF 1
  302. </block>
  303. </control>
  304. <control if="(RoutingTPIU &amp; 0x1)">
  305. <!-- TRACEDATA[1]: P7_5 -->
  306. <block>
  307. Write32(0x40086394, 0x000000B5); // LPC_SCU->SFSP7_5 : Func 5, EPD 0, EPUN 1, EHS 1, EZI 0, ZIF 1
  308. </block>
  309. </control>
  310. </control>
  311. <control if="tracePortWidth &gt;= 4">
  312. <!-- TRACEDATA[2]-->
  313. <control if="(RoutingTPIU &amp; 0x1) == 0">
  314. <!-- TRACEDATA[2]: PF_7 -->
  315. <block>
  316. Write32(0x4008679C, 0x000000B3); // LPC_SCU->SFSPF_7 : Func 3, EPD 0, EPUN 1, EHS 1, EZI 0, ZIF 1
  317. </block>
  318. </control>
  319. <control if="(RoutingTPIU &amp; 0x1)">
  320. <!-- TRACEDATA[2]: P7_6 -->
  321. <block>
  322. Write32(0x40086398, 0x000000B5); // LPC_SCU->SFSP7_6 : Func 5, EPD 0, EPUN 1, EHS 1, EZI 0, ZIF 1
  323. </block>
  324. </control>
  325. <!-- TRACEDATA[3]-->
  326. <control if="(RoutingTPIU &amp; 0x1) == 0">
  327. <!-- TRACEDATA[3]: PF_8 -->
  328. <block>
  329. Write32(0x400867A0, 0x000000B3); // LPC_SCU->SFSPF_8 : Func 3, EPD 0, EPUN 1, EHS 1, EZI 0, ZIF 1
  330. </block>
  331. </control>
  332. <control if="(RoutingTPIU &amp; 0x1)">
  333. <!-- TRACEDATA[3]: P7_7 -->
  334. <block>
  335. Write32(0x4008639C, 0x000000B5); // LPC_SCU->SFSP7_7 : Func 5, EPD 0, EPUN 1, EHS 1, EZI 0, ZIF 1
  336. </block>
  337. </control>
  338. </control>
  339. </sequence>
  340. <!-- End: User-defined EnableTraceTPIU Sequence -->
  341. <!-- Begin: User-defined EnableTraceBuffer Sequence -->
  342. <sequence name="EnableTraceBuffer">
  343. <block>
  344. // ETB accesses SRAM at 0x2000C000 - 0x2000FFFF
  345. // This memory region is not available to application when using ETB
  346. Write32(0x40043128, 0x00000000); // ETBCFG: ETB bit
  347. </block>
  348. </sequence>
  349. <!-- End: User-defined EnableTraceBuffer Sequence -->
  350. <!-- Begin: User-defined DisableTraceTPIU Sequence -->
  351. <sequence name="DisableTraceTPIU">
  352. <block>
  353. __var tracePortWidth = (__traceout &amp; 0x003F0000) &gt;&gt; 16;
  354. // Setup fixed TRACECLK pin
  355. Write32(0x40086790, 0x00000000); // LPC_SCU->SFSPF_4 : Reset Value 0x00000000
  356. </block>
  357. <!-- TRACEDATA[0]-->
  358. <control if="(RoutingTPIU &amp; 0x1) == 0">
  359. <!-- TRACEDATA[0]: PF_5 -->
  360. <block>
  361. Write32(0x40086794, 0x00000000); // LPC_SCU->SFSPF_5 : Reset Value 0x00000000
  362. </block>
  363. </control>
  364. <control if="(RoutingTPIU &amp; 0x1)">
  365. <!-- TRACEDATA[0]: P7_4 -->
  366. <block>
  367. Write32(0x40086390, 0x00000000); // LPC_SCU->SFSP7_4 : Reset Value 0x00000000
  368. </block>
  369. </control>
  370. <control if="tracePortWidth &gt;= 2">
  371. <!-- TRACEDATA[1]-->
  372. <control if="(RoutingTPIU &amp; 0x1) == 0">
  373. <!-- TRACEDATA[1]: PF_6 -->
  374. <block>
  375. Write32(0x40086798, 0x00000000); // LPC_SCU->SFSPF_6 : Reset Value 0x00000000
  376. </block>
  377. </control>
  378. <control if="(RoutingTPIU &amp; 0x1)">
  379. <!-- TRACEDATA[1]: P7_5 -->
  380. <block>
  381. Write32(0x40086394, 0x00000000); // LPC_SCU->SFSP7_5 : Reset Value 0x00000000
  382. </block>
  383. </control>
  384. </control>
  385. <control if="tracePortWidth &gt;= 4">
  386. <!-- TRACEDATA[2]-->
  387. <control if="(RoutingTPIU &amp; 0x1) == 0">
  388. <!-- TRACEDATA[2]: PF_7 -->
  389. <block>
  390. Write32(0x4008679C, 0x00000000); // LPC_SCU->SFSPF_7 : Reset Value 0x00000000
  391. </block>
  392. </control>
  393. <control if="(RoutingTPIU &amp; 0x1)">
  394. <!-- TRACEDATA[2]: P7_6 -->
  395. <block>
  396. Write32(0x40086398, 0x00000000); // LPC_SCU->SFSP7_6 : Reset Value 0x00000000
  397. </block>
  398. </control>
  399. <!-- TRACEDATA[3]-->
  400. <control if="(RoutingTPIU &amp; 0x1) == 0">
  401. <!-- TRACEDATA[3]: PF_8 -->
  402. <block>
  403. Write32(0x400867A0, 0x00000000); // LPC_SCU->SFSPF_8 : Reset Value 0x00000000
  404. </block>
  405. </control>
  406. <control if="(RoutingTPIU &amp; 0x1)">
  407. <!-- TRACEDATA[3]: P7_7 -->
  408. <block>
  409. Write32(0x4008639C, 0x00000000); // LPC_SCU->SFSP7_7 : Reset Value 0x00000000
  410. </block>
  411. </control>
  412. </control>
  413. </sequence>
  414. <!-- End: User-defined DisableTraceTPIU Sequence -->
  415. <!-- Begin: User-defined DisableTraceBuffer Sequence -->
  416. <sequence name="DisableTraceBuffer">
  417. <block>
  418. // AHB accesses SRAM at 0x2000C000 - 0x2000FFFF
  419. Write32(0x40043128, 0x00000001); // ETBCFG: ETB bit
  420. </block>
  421. </sequence>
  422. <!-- End: User-defined DisableTraceBuffer Sequence -->
  423. </sequences>
  424. <book name="Documents/dui0552a_cortex_m3_dgug.pdf" title="Cortex-M3 Generic User Guide"/>
  425. <description>
  426. NXP LPC1800 devices are high-speed and offer extensive communication peripherals.
  427. Typical applications include Industrial, RFID readers, Consumer, e-Metering and White goods.
  428. - Three PLLs
  429. - Quad SPI Flash interface (SPIFI)
  430. - State Configurable Timer (SCT)
  431. - LCD Controller (1024x768) for STN and TFT
  432. - Motor control PWM for three-phase motor
  433. - Unique ID for each device
  434. </description>
  435. <feature type="USART" n="4"/>
  436. <feature type="I2C" n="2"/>
  437. <feature type="SPI" n="2"/>
  438. <feature type="Timer" n="4" m="32"/>
  439. <feature type="ADC" n="8" m="10"/>
  440. <feature type="CAN" n="2"/>
  441. <!-- ************************ Subfamily 'LPC181x' **************************** -->
  442. <subFamily DsubFamily="LPC181x">
  443. <!-- ************************* Device 'LPC1810' ***************************** -->
  444. <device Dname="LPC1810">
  445. <compile header="Device/Include/LPC18xx.h" define="LPC18xx"/>
  446. <debug svd="SVD/LPC18xx.svd"/>
  447. <memory id="IRAM1" start="0x10000000" size="0x10000" init ="0" default="1"/>
  448. <memory id="IRAM2" start="0x20000000" size="0x4000" init ="0" default="0"/>
  449. <book name="Documents/UM10430.pdf" title="LPC1800 Series Reference Manual"/>
  450. <book name="Documents/LPC1850_30_20_10.pdf" title="LPC1800 Series Datasheet"/>
  451. <book name="Documents/ES_LPC18X0.pdf" title="LPC1800 Series Erratasheet"/>
  452. <feature type="PWM" n="6"/>
  453. </device>
  454. <!-- ************************* Device 'LPC1812' ***************************** -->
  455. <device Dname="LPC1812">
  456. <compile header="Device/Include/LPC18xx.h" define="LPC18xx"/>
  457. <debug svd="SVD/LPC18xx.svd"/>
  458. <memory id="IROM1" start="0x1A000000" size="0x80000" startup="1" default="1"/>
  459. <memory id="IRAM1" start="0x10000000" size="0x8000" init ="0" default="1"/>
  460. <memory id="IRAM2" start="0x20000000" size="0x4000" init ="0" default="0"/>
  461. <algorithm name="Flash/LPC18xx43xx_512_BA.FLM" start="0x1A000000" size="0x80000" RAMstart="0x10000000" RAMsize="0x0FE0" default="1"/>
  462. <book name="Documents/UM10430.pdf" title="LPC1800 Series Reference Manual"/>
  463. <book name="Documents/LPC1850_30_20_10.pdf" title="LPC1800 Series Datasheet"/>
  464. <book name="Documents/ES_LPC18X0.pdf" title="LPC1800 Series Erratasheet"/>
  465. <feature type="PWM" n="6"/>
  466. <environment name="uv">
  467. <postBuild1>$K/ARM/BIN/ElfDwT.exe !L BASEADDRESS(0x1A000000)</postBuild1>
  468. <postRun1> 1 </postRun1>
  469. </environment>
  470. </device>
  471. <!-- ************************* Device 'LPC1813' ***************************** -->
  472. <device Dname="LPC1813">
  473. <compile header="Device/Include/LPC18xx.h" define="LPC18xx"/>
  474. <debug svd="SVD/LPC18xx.svd"/>
  475. <memory id="IROM1" start="0x1A000000" size="0x40000" startup="1" default="1"/>
  476. <memory id="IROM2" start="0x1B000000" size="0x40000" startup="0" default="0"/>
  477. <memory id="IRAM1" start="0x10000000" size="0x8000" init ="0" default="1"/>
  478. <memory id="IRAM2" start="0x20000000" size="0x4000" init ="0" default="0"/>
  479. <algorithm name="Flash/LPC18xx43xx_256_BA.FLM" start="0x1A000000" size="0x40000" RAMstart="0x10000000" RAMsize="0x0FE0" default="1"/>
  480. <algorithm name="Flash/LPC18xx43xx_256_BB.FLM" start="0x1B000000" size="0x40000" RAMstart="0x10000000" RAMsize="0x0FE0" default="1"/>
  481. <book name="Documents/UM10430.pdf" title="LPC1800 Series Reference Manual"/>
  482. <book name="Documents/LPC1850_30_20_10.pdf" title="LPC1800 Series Datasheet"/>
  483. <book name="Documents/ES_LPC18X0.pdf" title="LPC1800 Series Erratasheet"/>
  484. <feature type="PWM" n="6"/>
  485. <environment name="uv">
  486. <postBuild1>$K/ARM/BIN/ElfDwT.exe !L BASEADDRESS(0x1A000000)</postBuild1>
  487. <postRun1> 1 </postRun1>
  488. </environment>
  489. </device>
  490. <!-- ************************* Device 'LPC1815' ***************************** -->
  491. <device Dname="LPC1815">
  492. <compile header="Device/Include/LPC18xx.h" define="LPC18xx"/>
  493. <debug svd="SVD/LPC18xx.svd"/>
  494. <memory id="IROM1" start="0x1A000000" size="0x60000" startup="1" default="1"/>
  495. <memory id="IROM2" start="0x1B000000" size="0x60000" startup="0" default="0"/>
  496. <memory id="IRAM1" start="0x10000000" size="0x8000" init ="0" default="1"/>
  497. <memory id="IRAM2" start="0x20000000" size="0x10000" init ="0" default="0"/>
  498. <algorithm name="Flash/LPC18xx43xx_384_BA.FLM" start="0x1A000000" size="0x60000" RAMstart="0x10000000" RAMsize="0x0FE0" default="1"/>
  499. <algorithm name="Flash/LPC18xx43xx_384_BB.FLM" start="0x1B000000" size="0x60000" RAMstart="0x10000000" RAMsize="0x0FE0" default="1"/>
  500. <book name="Documents/UM10430.pdf" title="LPC1800 Series Reference Manual"/>
  501. <book name="Documents/LPC1850_30_20_10.pdf" title="LPC1800 Series Datasheet"/>
  502. <book name="Documents/ES_LPC18X0.pdf" title="LPC1800 Series Erratasheet"/>
  503. <feature type="PWM" n="6"/>
  504. <environment name="uv">
  505. <postBuild1>$K/ARM/BIN/ElfDwT.exe !L BASEADDRESS(0x1A000000)</postBuild1>
  506. <postRun1> 1 </postRun1>
  507. </environment>
  508. </device>
  509. <!-- ************************* Device 'LPC1817' ***************************** -->
  510. <device Dname="LPC1817">
  511. <compile header="Device/Include/LPC18xx.h" define="LPC18xx"/>
  512. <debug svd="SVD/LPC18xx.svd"/>
  513. <memory id="IROM1" start="0x1A000000" size="0x80000" startup="1" default="1"/>
  514. <memory id="IROM2" start="0x1B000000" size="0x80000" startup="0" default="0"/>
  515. <memory id="IRAM1" start="0x10000000" size="0x8000" init ="0" default="1"/>
  516. <memory id="IRAM2" start="0x20000000" size="0x10000" init ="0" default="0"/>
  517. <algorithm name="Flash/LPC18xx43xx_512_BA.FLM" start="0x1A000000" size="0x80000" RAMstart="0x10000000" RAMsize="0x0FE0" default="1"/>
  518. <algorithm name="Flash/LPC18xx43xx_512_BB.FLM" start="0x1B000000" size="0x80000" RAMstart="0x10000000" RAMsize="0x0FE0" default="1"/>
  519. <book name="Documents/UM10430.pdf" title="LPC1800 Series Reference Manual"/>
  520. <book name="Documents/LPC1850_30_20_10.pdf" title="LPC1800 Series Datasheet"/>
  521. <book name="Documents/ES_LPC18X0.pdf" title="LPC1800 Series Erratasheet"/>
  522. <environment name="uv">
  523. <postBuild1>$K/ARM/BIN/ElfDwT.exe !L BASEADDRESS(0x1A000000)</postBuild1>
  524. <postRun1> 1 </postRun1>
  525. </environment>
  526. </device>
  527. </subFamily>
  528. <!-- ************************ Subfamily 'LPC182x' **************************** -->
  529. <subFamily DsubFamily="LPC182x">
  530. <feature type="PWM" n="6"/>
  531. <feature type="USBD" n="1"/>
  532. <!-- ************************* Device 'LPC1820' ***************************** -->
  533. <device Dname="LPC1820">
  534. <compile header="Device/Include/LPC18xx.h" define="LPC18xx"/>
  535. <debug svd="SVD/LPC18xx.svd"/>
  536. <memory id="IRAM1" start="0x10000000" size="0x18000" init ="0" default="1"/>
  537. <memory id="IRAM2" start="0x20000000" size="0x4000" init ="0" default="0"/>
  538. <book name="Documents/UM10430.pdf" title="LPC1800 Series Reference Manual"/>
  539. <book name="Documents/LPC1850_30_20_10.pdf" title="LPC1800 Series Datasheet"/>
  540. <book name="Documents/ES_LPC18X0.pdf" title="LPC1800 Series Erratasheet"/>
  541. </device>
  542. <!-- ************************* Device 'LPC1822' ***************************** -->
  543. <device Dname="LPC1822">
  544. <compile header="Device/Include/LPC18xx.h" define="LPC18xx"/>
  545. <debug svd="SVD/LPC18xx.svd"/>
  546. <memory id="IROM1" start="0x1A000000" size="0x80000" startup="1" default="1"/>
  547. <memory id="IRAM1" start="0x10000000" size="0x8000" init ="0" default="1"/>
  548. <memory id="IRAM2" start="0x20000000" size="0x4000" init ="0" default="0"/>
  549. <algorithm name="Flash/LPC18xx43xx_512_BA.FLM" start="0x1A000000" size="0x80000" RAMstart="0x10000000" RAMsize="0x0FE0" default="1"/>
  550. <book name="Documents/UM10430.pdf" title="LPC1800 Series Reference Manual"/>
  551. <book name="Documents/LPC1850_30_20_10.pdf" title="LPC1800 Series Datasheet"/>
  552. <book name="Documents/ES_LPC18X0.pdf" title="LPC1800 Series Erratasheet"/>
  553. <environment name="uv">
  554. <postBuild1>$K/ARM/BIN/ElfDwT.exe !L BASEADDRESS(0x1A000000)</postBuild1>
  555. <postRun1> 1 </postRun1>
  556. </environment>
  557. </device>
  558. <!-- ************************* Device 'LPC1823' ***************************** -->
  559. <device Dname="LPC1823">
  560. <compile header="Device/Include/LPC18xx.h" define="LPC18xx"/>
  561. <debug svd="SVD/LPC18xx.svd"/>
  562. <memory id="IROM1" start="0x1A000000" size="0x40000" startup="1" default="1"/>
  563. <memory id="IROM2" start="0x1B000000" size="0x40000" startup="0" default="0"/>
  564. <memory id="IRAM1" start="0x10000000" size="0x8000" init ="0" default="1"/>
  565. <memory id="IRAM2" start="0x20000000" size="0x4000" init ="0" default="0"/>
  566. <algorithm name="Flash/LPC18xx43xx_256_BA.FLM" start="0x1A000000" size="0x40000" RAMstart="0x10000000" RAMsize="0x0FE0" default="1"/>
  567. <algorithm name="Flash/LPC18xx43xx_256_BB.FLM" start="0x1B000000" size="0x40000" RAMstart="0x10000000" RAMsize="0x0FE0" default="1"/>
  568. <book name="Documents/UM10430.pdf" title="LPC1800 Series Reference Manual"/>
  569. <book name="Documents/LPC1850_30_20_10.pdf" title="LPC1800 Series Datasheet"/>
  570. <book name="Documents/ES_LPC18X0.pdf" title="LPC1800 Series Erratasheet"/>
  571. <environment name="uv">
  572. <postBuild1>$K/ARM/BIN/ElfDwT.exe !L BASEADDRESS(0x1A000000)</postBuild1>
  573. <postRun1> 1 </postRun1>
  574. </environment>
  575. </device>
  576. <!-- ************************* Device 'LPC1825' ***************************** -->
  577. <device Dname="LPC1825">
  578. <compile header="Device/Include/LPC18xx.h" define="LPC18xx"/>
  579. <debug svd="SVD/LPC18xx.svd"/>
  580. <memory id="IROM1" start="0x1A000000" size="0x60000" startup="1" default="1"/>
  581. <memory id="IROM2" start="0x1B000000" size="0x60000" startup="0" default="0"/>
  582. <memory id="IRAM1" start="0x10000000" size="0x8000" init ="0" default="1"/>
  583. <memory id="IRAM2" start="0x20000000" size="0x10000" init ="0" default="0"/>
  584. <algorithm name="Flash/LPC18xx43xx_384_BA.FLM" start="0x1A000000" size="0x60000" RAMstart="0x10000000" RAMsize="0x0FE0" default="1"/>
  585. <algorithm name="Flash/LPC18xx43xx_384_BB.FLM" start="0x1B000000" size="0x60000" RAMstart="0x10000000" RAMsize="0x0FE0" default="1"/>
  586. <book name="Documents/UM10430.pdf" title="LPC1800 Series Reference Manual"/>
  587. <book name="Documents/LPC1850_30_20_10.pdf" title="LPC1800 Series Datasheet"/>
  588. <book name="Documents/ES_LPC18X0.pdf" title="LPC1800 Series Erratasheet"/>
  589. <environment name="uv">
  590. <postBuild1>$K/ARM/BIN/ElfDwT.exe !L BASEADDRESS(0x1A000000)</postBuild1>
  591. <postRun1> 1 </postRun1>
  592. </environment>
  593. </device>
  594. <!-- ************************* Device 'LPC1827' ***************************** -->
  595. <device Dname="LPC1827">
  596. <compile header="Device/Include/LPC18xx.h" define="LPC18xx"/>
  597. <debug svd="SVD/LPC18xx.svd"/>
  598. <memory id="IROM1" start="0x1A000000" size="0x80000" startup="1" default="1"/>
  599. <memory id="IROM2" start="0x1B000000" size="0x80000" startup="0" default="0"/>
  600. <memory id="IRAM1" start="0x10000000" size="0x8000" init ="0" default="1"/>
  601. <memory id="IRAM2" start="0x20000000" size="0x10000" init ="0" default="0"/>
  602. <algorithm name="Flash/LPC18xx43xx_512_BA.FLM" start="0x1A000000" size="0x80000" RAMstart="0x10000000" RAMsize="0x0FE0" default="1"/>
  603. <algorithm name="Flash/LPC18xx43xx_512_BB.FLM" start="0x1B000000" size="0x80000" RAMstart="0x10000000" RAMsize="0x0FE0" default="1"/>
  604. <book name="Documents/UM10430.pdf" title="LPC1800 Series Reference Manual"/>
  605. <book name="Documents/LPC1850_30_20_10.pdf" title="LPC1800 Series Datasheet"/>
  606. <book name="Documents/ES_LPC18X0.pdf" title="LPC1800 Series Erratasheet"/>
  607. <environment name="uv">
  608. <postBuild1>$K/ARM/BIN/ElfDwT.exe !L BASEADDRESS(0x1A000000)</postBuild1>
  609. <postRun1> 1 </postRun1>
  610. </environment>
  611. </device>
  612. </subFamily>
  613. <!-- ************************ Subfamily 'LPC183x' **************************** -->
  614. <subFamily DsubFamily="LPC183x">
  615. <feature type="PWM" n="6"/>
  616. <feature type="ETH" n="1" m="100000000"/>
  617. <feature type="USBD" n="2"/>
  618. <!-- ************************* Device 'LPC1830' ***************************** -->
  619. <device Dname="LPC1830">
  620. <compile header="Device/Include/LPC18xx.h" define="LPC18xx"/>
  621. <debug svd="SVD/LPC18xx.svd"/>
  622. <memory id="IRAM1" start="0x10000000" size="0x18000" init ="0" default="1"/>
  623. <memory id="IRAM2" start="0x20000000" size="0x10000" init ="0" default="0"/>
  624. <book name="Documents/UM10430.pdf" title="LPC1800 Series Reference Manual"/>
  625. <book name="Documents/LPC1850_30_20_10.pdf" title="LPC1800 Series Datasheet"/>
  626. <book name="Documents/ES_LPC18X0.pdf" title="LPC1800 Series Erratasheet"/>
  627. </device>
  628. <!-- ************************* Device 'LPC1833' ***************************** -->
  629. <device Dname="LPC1833">
  630. <compile header="Device/Include/LPC18xx.h" define="LPC18xx"/>
  631. <debug svd="SVD/LPC18xx.svd"/>
  632. <memory id="IROM1" start="0x1A000000" size="0x40000" startup="1" default="1"/>
  633. <memory id="IROM2" start="0x1B000000" size="0x40000" startup="0" default="0"/>
  634. <memory id="IRAM1" start="0x10000000" size="0x8000" init ="0" default="1"/>
  635. <memory id="IRAM2" start="0x20000000" size="0x10000" init ="0" default="0"/>
  636. <algorithm name="Flash/LPC18xx43xx_256_BA.FLM" start="0x1A000000" size="0x40000" RAMstart="0x10000000" RAMsize="0x0FE0" default="1"/>
  637. <algorithm name="Flash/LPC18xx43xx_256_BB.FLM" start="0x1B000000" size="0x40000" RAMstart="0x10000000" RAMsize="0x0FE0" default="1"/>
  638. <book name="Documents/UM10430.pdf" title="LPC1800 Series Reference Manual"/>
  639. <book name="Documents/LPC1850_30_20_10.pdf" title="LPC1800 Series Datasheet"/>
  640. <book name="Documents/ES_LPC18X0.pdf" title="LPC1800 Series Erratasheet"/>
  641. <environment name="uv">
  642. <postBuild1>$K/ARM/BIN/ElfDwT.exe !L BASEADDRESS(0x1A000000)</postBuild1>
  643. <postRun1> 1 </postRun1>
  644. </environment>
  645. </device>
  646. <!-- ************************* Device 'LPC1837' ***************************** -->
  647. <device Dname="LPC1837">
  648. <compile header="Device/Include/LPC18xx.h" define="LPC18xx"/>
  649. <debug svd="SVD/LPC18xx.svd"/>
  650. <memory id="IROM1" start="0x1A000000" size="0x80000" startup="1" default="1"/>
  651. <memory id="IROM2" start="0x1B000000" size="0x80000" startup="0" default="0"/>
  652. <memory id="IRAM1" start="0x10000000" size="0x8000" init ="0" default="1"/>
  653. <memory id="IRAM2" start="0x20000000" size="0x10000" init ="0" default="0"/>
  654. <algorithm name="Flash/LPC18xx43xx_512_BA.FLM" start="0x1A000000" size="0x80000" RAMstart="0x10000000" RAMsize="0x0FE0" default="1"/>
  655. <algorithm name="Flash/LPC18xx43xx_512_BB.FLM" start="0x1B000000" size="0x80000" RAMstart="0x10000000" RAMsize="0x0FE0" default="1"/>
  656. <book name="Documents/UM10430.pdf" title="LPC1800 Series Reference Manual"/>
  657. <book name="Documents/LPC1850_30_20_10.pdf" title="LPC1800 Series Datasheet"/>
  658. <book name="Documents/ES_LPC18X0.pdf" title="LPC1800 Series Erratasheet"/>
  659. <environment name="uv">
  660. <postBuild1>$K/ARM/BIN/ElfDwT.exe !L BASEADDRESS(0x1A000000)</postBuild1>
  661. <postRun1> 1 </postRun1>
  662. </environment>
  663. </device>
  664. </subFamily>
  665. <!-- ************************ Subfamily 'LPC185x' **************************** -->
  666. <subFamily DsubFamily="LPC185x">
  667. <feature type="PWM" n="6"/>
  668. <feature type="ETH" n="1" m="100000000"/>
  669. <feature type="USBD" n="2"/>
  670. <feature type="LCD" n="1"/>
  671. <!-- ************************* Device 'LPC1850' ***************************** -->
  672. <device Dname="LPC1850">
  673. <compile header="Device/Include/LPC18xx.h" define="LPC18xx"/>
  674. <debug svd="SVD/LPC18xx.svd"/>
  675. <memory id="IRAM1" start="0x10000000" size="0x18000" init ="0" default="1"/>
  676. <memory id="IRAM2" start="0x20000000" size="0x10000" init ="0" default="0"/>
  677. <book name="Documents/UM10430.pdf" title="LPC1800 Series Reference Manual"/>
  678. <book name="Documents/LPC1850_30_20_10.pdf" title="LPC1800 Series Datasheet"/>
  679. <book name="Documents/ES_LPC18X0.pdf" title="LPC1800 Series Erratasheet"/>
  680. <book name="Documents/mcb1800.chm" title="MCB1800 User's Guide"/>
  681. </device>
  682. <!-- ************************* Device 'LPC1853' ***************************** -->
  683. <device Dname="LPC1853">
  684. <compile header="Device/Include/LPC18xx.h" define="LPC18xx"/>
  685. <debug svd="SVD/LPC18xx.svd"/>
  686. <memory id="IROM1" start="0x1A000000" size="0x40000" startup="1" default="1"/>
  687. <memory id="IROM2" start="0x1B000000" size="0x40000" startup="0" default="0"/>
  688. <memory id="IRAM1" start="0x10000000" size="0x8000" init ="0" default="1"/>
  689. <memory id="IRAM2" start="0x20000000" size="0x10000" init ="0" default="0"/>
  690. <algorithm name="Flash/LPC18xx43xx_256_BA.FLM" start="0x1A000000" size="0x40000" RAMstart="0x10000000" RAMsize="0x0FE0" default="1"/>
  691. <algorithm name="Flash/LPC18xx43xx_256_BB.FLM" start="0x1B000000" size="0x40000" RAMstart="0x10000000" RAMsize="0x0FE0" default="1"/>
  692. <book name="Documents/UM10430.pdf" title="LPC1800 Series Reference Manual"/>
  693. <book name="Documents/LPC1850_30_20_10.pdf" title="LPC1800 Series Datasheet"/>
  694. <book name="Documents/ES_LPC18X0.pdf" title="LPC1800 Series Erratasheet"/>
  695. <environment name="uv">
  696. <postBuild1>$K/ARM/BIN/ElfDwT.exe !L BASEADDRESS(0x1A000000)</postBuild1>
  697. <postRun1> 1 </postRun1>
  698. </environment>
  699. </device>
  700. <!-- ************************* Device 'LPC1857' ***************************** -->
  701. <device Dname="LPC1857">
  702. <compile header="Device/Include/LPC18xx.h" define="LPC18xx"/>
  703. <debug svd="SVD/LPC18xx.svd"/>
  704. <memory id="IROM1" start="0x1A000000" size="0x80000" startup="1" default="1"/>
  705. <memory id="IROM2" start="0x1B000000" size="0x80000" startup="0" default="0"/>
  706. <memory id="IRAM1" start="0x10000000" size="0x8000" init ="0" default="1"/>
  707. <memory id="IRAM2" start="0x20000000" size="0x10000" init ="0" default="0"/>
  708. <algorithm name="Flash/LPC18xx43xx_512_BA.FLM" start="0x1A000000" size="0x80000" RAMstart="0x10000000" RAMsize="0x0FE0" default="1"/>
  709. <algorithm name="Flash/LPC18xx43xx_512_BB.FLM" start="0x1B000000" size="0x80000" RAMstart="0x10000000" RAMsize="0x0FE0" default="1"/>
  710. <book name="Documents/UM10430.pdf" title="LPC1800 Series Reference Manual"/>
  711. <book name="Documents/LPC1850_30_20_10.pdf" title="LPC1800 Series Datasheet"/>
  712. <book name="Documents/ES_LPC18X0.pdf" title="LPC1800 Series Erratasheet"/>
  713. <book name="Documents/mcb1800.chm" title="MCB1800 User's Guide"/>
  714. <environment name="uv">
  715. <postBuild1>$K/ARM/BIN/ElfDwT.exe !L BASEADDRESS(0x1A000000)</postBuild1>
  716. <postRun1> 1 </postRun1>
  717. </environment>
  718. </device>
  719. </subFamily>
  720. <!-- ************************ Subfamily 'LPC18S1x' **************************** -->
  721. <subFamily DsubFamily="LPC18S1x">
  722. <feature type="Crypto" n="128" name="AES engine for encryption and decryption"/>
  723. <!-- ************************* Device 'LPC18S10' ***************************** -->
  724. <device Dname="LPC18S10">
  725. <compile header="Device/Include/LPC18xx.h" define="LPC18xx"/>
  726. <debug svd="SVD/LPC18xx.svd"/>
  727. <memory id="IRAM1" start="0x10000000" size="0x10000" init ="0" default="1"/>
  728. <memory id="IRAM2" start="0x20000000" size="0x4000" init ="0" default="0"/>
  729. <book name="Documents/UM10430.pdf" title="LPC18xx Reference Manual"/>
  730. <book name="Documents/LPC18S50_30_10.pdf" title="LPC18S50/S30/S10 Datasheet"/>
  731. <feature type="PWM" n="6"/>
  732. </device>
  733. </subFamily>
  734. <!-- ************************ Subfamily 'LPC18S3x' **************************** -->
  735. <subFamily DsubFamily="LPC18S3x">
  736. <feature type="PWM" n="6"/>
  737. <feature type="ETH" n="1" m="100000000"/>
  738. <feature type="USBD" n="2"/>
  739. <feature type="Crypto" n="128" name="AES engine for encryption and decryption"/>
  740. <!-- ************************* Device 'LPC18S30' ***************************** -->
  741. <device Dname="LPC18S30">
  742. <compile header="Device/Include/LPC18xx.h" define="LPC18xx"/>
  743. <debug svd="SVD/LPC18xx.svd"/>
  744. <memory id="IRAM1" start="0x10000000" size="0x18000" init ="0" default="1"/>
  745. <memory id="IRAM2" start="0x20000000" size="0x10000" init ="0" default="0"/>
  746. <book name="Documents/UM10430.pdf" title="LPC18xx Reference Manual"/>
  747. <book name="Documents/LPC18S50_30_10.pdf" title="LPC18S50/S30/S10 Datasheet"/>
  748. </device>
  749. <!-- ************************* Device 'LPC18S37' ***************************** -->
  750. <device Dname="LPC18S37">
  751. <compile header="Device/Include/LPC18xx.h" define="LPC18xx"/>
  752. <debug svd="SVD/LPC18xx.svd"/>
  753. <memory id="IROM1" start="0x1A000000" size="0x80000" startup="1" default="1"/>
  754. <memory id="IROM2" start="0x1B000000" size="0x80000" startup="0" default="0"/>
  755. <memory id="IRAM1" start="0x10000000" size="0x8000" init ="0" default="1"/>
  756. <memory id="IRAM2" start="0x20000000" size="0x10000" init ="0" default="0"/>
  757. <algorithm name="Flash/LPC18xx43xx_512_BA.FLM" start="0x1A000000" size="0x80000" RAMstart="0x10000000" RAMsize="0x0FE0" default="1"/>
  758. <algorithm name="Flash/LPC18xx43xx_512_BB.FLM" start="0x1B000000" size="0x80000" RAMstart="0x10000000" RAMsize="0x0FE0" default="1"/>
  759. <book name="Documents/UM10430.pdf" title="LPC18xx Reference Manual"/>
  760. <book name="Documents/LPC18S5X_S3X.pdf" title="LPC18S5x/S3x Series Datasheet"/>
  761. <environment name="uv">
  762. <postBuild1>$K/ARM/BIN/ElfDwT.exe !L BASEADDRESS(0x1A000000)</postBuild1>
  763. <postRun1> 1 </postRun1>
  764. </environment>
  765. </device>
  766. </subFamily>
  767. <!-- ************************ Subfamily 'LPC18S5x' **************************** -->
  768. <subFamily DsubFamily="LPC18S5x">
  769. <feature type="PWM" n="6"/>
  770. <feature type="ETH" n="1" m="100000000"/>
  771. <feature type="USBD" n="2"/>
  772. <feature type="LCD" n="1"/>
  773. <feature type="Crypto" n="128" name="AES engine for encryption and decryption"/>
  774. <!-- ************************* Device 'LPC18S50' ***************************** -->
  775. <device Dname="LPC18S50">
  776. <compile header="Device/Include/LPC18xx.h" define="LPC18xx"/>
  777. <debug svd="SVD/LPC18xx.svd"/>
  778. <memory id="IRAM1" start="0x10000000" size="0x18000" init ="0" default="1"/>
  779. <memory id="IRAM2" start="0x20000000" size="0x10000" init ="0" default="0"/>
  780. <book name="Documents/UM10430.pdf" title="LPC18xx Reference Manual"/>
  781. <book name="Documents/LPC18S50_30_10.pdf" title="LPC18S50/S30/S10 Datasheet"/>
  782. </device>
  783. <!-- ************************* Device 'LPC18S57' ***************************** -->
  784. <device Dname="LPC18S57">
  785. <compile header="Device/Include/LPC18xx.h" define="LPC18xx"/>
  786. <debug svd="SVD/LPC18xx.svd"/>
  787. <memory id="IROM1" start="0x1A000000" size="0x80000" startup="1" default="1"/>
  788. <memory id="IROM2" start="0x1B000000" size="0x80000" startup="0" default="0"/>
  789. <memory id="IRAM1" start="0x10000000" size="0x8000" init ="0" default="1"/>
  790. <memory id="IRAM2" start="0x20000000" size="0x10000" init ="0" default="0"/>
  791. <algorithm name="Flash/LPC18xx43xx_512_BA.FLM" start="0x1A000000" size="0x80000" RAMstart="0x10000000" RAMsize="0x0FE0" default="1"/>
  792. <algorithm name="Flash/LPC18xx43xx_512_BB.FLM" start="0x1B000000" size="0x80000" RAMstart="0x10000000" RAMsize="0x0FE0" default="1"/>
  793. <book name="Documents/UM10430.pdf" title="LPC18xx Reference Manual"/>
  794. <book name="Documents/LPC18S5X_S3X.pdf" title="LPC18S5x/S3x Series Datasheet"/>
  795. <environment name="uv">
  796. <postBuild1>$K/ARM/BIN/ElfDwT.exe !L BASEADDRESS(0x1A000000)</postBuild1>
  797. <postRun1> 1 </postRun1>
  798. </environment>
  799. </device>
  800. </subFamily>
  801. </family>
  802. </devices>
  803. <boards>
  804. <board vendor="Keil" name="MCB1800" revision="Ver 1.3" salesContact="sales.intl@keil.com" orderForm="http://www.keil.com/product/prices.asp?MCB1800=ON">
  805. <description>Keil MCB1800 Development Board</description>
  806. <image small="Images/mcb1800_small.jpg" large="Images/mcb1800_large.jpg"/>
  807. <book category="overview" name="http://www.keil.com/mcb1800/" title="MCB1800 Evaluation Board Web Page"/>
  808. <book category="setup" name="Documents/MCB1800_QSG.pdf" title="Quick Start Guide"/>
  809. <book category="schematic" name="Documents/MCB1800v1-3-schematics.pdf" title="MCB1800 Schematics"/>
  810. <book category="manual" name="Documents/mcb1800.chm" title="User Manual"/>
  811. <mountedDevice deviceIndex="0" Dvendor="NXP:11" Dname="LPC1850"/>
  812. <mountedDevice deviceIndex="0" Dvendor="NXP:11" Dname="LPC1857"/>
  813. <compatibleDevice deviceIndex="0" Dvendor="NXP:11" DsubFamily="LPC185x"/>
  814. <feature type="XTAL" n="12000000"/>
  815. <feature type="PWR" n="5" name="USB Powered"/>
  816. <feature type="PWR" n="8" m="12" name="External Power Supply"/>
  817. <feature type="RAM" n="1" name="16 MB SDRAM"/>
  818. <feature type="ROM" n="1" name="16 MB NOR Flash"/>
  819. <feature type="ROM" n="1" name="4 MB Quad-SPI Flash"/>
  820. <feature type="MemCard" n="1" name="microSD Card Holder"/>
  821. <feature type="Proto" n="2" name="Prototyping areas connected to I/Os"/>
  822. <feature type="USB" n="1" name="USB 2.0 High-speed Host/Device/OTG interface (USB host + Micro USB Device/OTG connectors)"/>
  823. <feature type="USB" n="1" name="USB 2.0 Full-speed Host/Device interface (USB host + micro USB Device connectors)"/>
  824. <feature type="CAN" n="1"/>
  825. <feature type="RS232" n="1"/>
  826. <feature type="ETH" n="1" name="10/100 Ethernet Port"/>
  827. <feature type="GLCD" n="1" m="240.320" name="2.4 inch Color QVGA TFT LCD with resistive touchscreen"/>
  828. <feature type="Poti" n="1" name="Potentiometer for ADC Input"/>
  829. <feature type="LineIn" n="2" name="Audio CODEC with Line-In/Out and Speaker/Microphone"/>
  830. <feature type="LineOut" n="2" name="Audio CODEC with Line-In/Out and Speaker/Microphone"/>
  831. <feature type="Button" n="6" name="Push-Buttons: 3 x GPIO, Reset, ISP, WAKEUP"/>
  832. <feature type="LED" n="8" name="I/O Port LEDs"/>
  833. <feature type="CustomFF" n="124" m="170"/>
  834. <debugInterface adapter="JTAG/SW" connector="20 pin JTAG (0.1 inch connector)"/>
  835. <debugInterface adapter="JTAG/SW" connector="10 pin Cortex debug (0.05 inch connector)"/>
  836. <debugInterface adapter="JTAG/SW" connector="20-pin Cortex debug + ETM Trace (0.05 inch connector)"/>
  837. </board>
  838. </boards>
  839. <conditions>
  840. <!-- conditions are dependency rules that can apply to a component or an individual file -->
  841. <condition id="LPC1800">
  842. <!-- conditions selecting Devices -->
  843. <description>NXP LPC1800 Series devices</description>
  844. <accept Dvendor="NXP:11" Dname="LPC18??"/>
  845. <accept Dvendor="NXP:11" Dname="LPC18S??"/>
  846. </condition>
  847. <condition id="LPC1800 CMSIS">
  848. <description>NXP LPC1800 Series devices and CMSIS-CORE and ARMCC compiler</description>
  849. <require condition="LPC1800"/>
  850. <require Cclass="CMSIS" Cgroup="CORE"/>
  851. </condition>
  852. <condition id="ARM Compiler">
  853. <require Tcompiler="ARMCC"/>
  854. </condition>
  855. <condition id="LPC1800 CMSIS SCU">
  856. <description>NXP LPC1800 with CMSIS and SCU</description>
  857. <require condition="LPC1800 CMSIS"/>
  858. <require Cclass ="Device" Cgroup="SCU" />
  859. </condition>
  860. <condition id="LPC1800 CMSIS RTOS SCU">
  861. <description>NXP LPC1800 with CMSIS, RTOS and SCU</description>
  862. <require condition="LPC1800 CMSIS"/>
  863. <require Cclass="CMSIS" Cgroup="RTOS"/>
  864. <require Cclass="Device" Cgroup="SCU"/>
  865. </condition>
  866. <condition id="LPC1800 CMSIS SCU GPIO">
  867. <description>NXP LPC1800 with CMSIS, SCU and GPIO</description>
  868. <require condition="LPC1800 CMSIS"/>
  869. <require Cclass="Device" Cgroup="SCU"/>
  870. <require Cclass="Device" Cgroup="GPIO"/>
  871. </condition>
  872. <condition id="LPC1800 CMSIS SCU GPDMA">
  873. <description>NXP LPC1800 with CMSIS, SCU and GPDMA</description>
  874. <require condition="LPC1800 CMSIS"/>
  875. <require Cclass="Device" Cgroup="SCU"/>
  876. <require Cclass="Device" Cgroup="GPDMA"/>
  877. </condition>
  878. <condition id="LPC1800 CMSIS SCU GPIO GPDMA">
  879. <description>NXP LPC1800 with CMSIS, SCU, GPIO and GPDMA</description>
  880. <require condition="LPC1800 CMSIS"/>
  881. <require Cclass="Device" Cgroup="SCU"/>
  882. <require Cclass="Device" Cgroup="GPIO"/>
  883. <require Cclass="Device" Cgroup="GPDMA"/>
  884. </condition>
  885. <condition id="LPC1800 CMSIS SCU GPIO SPI">
  886. <description>NXP LPC1800 with CMSIS, SCU, GPIO and SPI</description>
  887. <require condition="LPC1800 CMSIS"/>
  888. <require Cclass="Device" Cgroup="SCU"/>
  889. <require Cclass="Device" Cgroup="GPIO"/>
  890. <require Cclass="CMSIS Driver" Cgroup="SPI" Capiversion="2.01"/>
  891. </condition>
  892. <condition id="LPC1800 CMSIS SCU GPIO SPI Display">
  893. <description>NXP LPC1800 with CMSIS, SCU, GPIO, SPI and Display</description>
  894. <require condition="LPC1800 CMSIS SCU GPIO SPI"/>
  895. <require Cclass="Graphics" Cgroup="Display" Csub="MCBQVGA_LG" Cvariant="RGB IF"/>
  896. </condition>
  897. <condition id="LPC1800 CMSIS I2C Driver">
  898. <description>NXP LPC1800 with CMSIS and I2C Driver</description>
  899. <require condition="LPC1800 CMSIS"/>
  900. <require Cclass="CMSIS Driver" Cgroup="I2C" Capiversion="2.02"/>
  901. </condition>
  902. <condition id="LPC1800 CMSIS RTOS and I2C Driver">
  903. <description>NXP LPC1800 with CMSIS, RTOS and I2C Driver</description>
  904. <require condition="LPC1800 CMSIS"/>
  905. <require Cclass="CMSIS" Cgroup="RTOS"/>
  906. <require Cclass="CMSIS Driver" Cgroup="I2C" Capiversion="2.02"/>
  907. </condition>
  908. <condition id="LPC1800 CMSIS SCU GPIO SAI/I2C Driver">
  909. <description>NXP LPC1800 with CMSIS, SCU, GPIO and SAI/I2C Driver</description>
  910. <require condition="LPC1800 CMSIS"/>
  911. <require Cclass="Device" Cgroup="SCU"/>
  912. <require Cclass="Device" Cgroup="GPIO"/>
  913. <require Cclass="CMSIS Driver" Cgroup="SAI" Capiversion="1.00"/>
  914. <require Cclass="CMSIS Driver" Cgroup="I2C" Capiversion="2.02"/>
  915. </condition>
  916. </conditions>
  917. <examples>
  918. <!-- MCB1800 Development Board -->
  919. <example name="Blinky" doc="Abstract.txt" folder="Boards/Keil/MCB1800/Blinky">
  920. <description>Blinky example</description>
  921. <board name="MCB1800" vendor="Keil"/>
  922. <project>
  923. <environment name="uv" load="Blinky.uvprojx"/>
  924. </project>
  925. <attributes>
  926. <component Cclass="CMSIS" Cgroup="CORE"/>
  927. <component Cclass="Device" Cgroup="Startup"/>
  928. <category>Getting Started</category>
  929. </attributes>
  930. </example>
  931. <example name="Blinky ULp" doc="Abstract.txt" folder="Boards/Keil/MCB1800/Blinky_ULp">
  932. <description>Blinky ULINKpro example</description>
  933. <board name="MCB1800" vendor="Keil"/>
  934. <project>
  935. <environment name="uv" load="Blinky.uvprojx"/>
  936. </project>
  937. <attributes>
  938. <component Cclass="CMSIS" Cgroup="CORE"/>
  939. <component Cclass="Device" Cgroup="Startup"/>
  940. <category>Getting Started</category>
  941. </attributes>
  942. </example>
  943. <example name="CMSIS-RTOS Blinky" doc="Abstract.txt" folder="Boards/Keil/MCB1800/RTX_Blinky">
  944. <description>CMSIS-RTOS based Blinky example</description>
  945. <board name="MCB1800" vendor="Keil"/>
  946. <project>
  947. <environment name="uv" load="Blinky.uvprojx"/>
  948. </project>
  949. <attributes>
  950. <component Cclass="CMSIS" Cgroup="CORE"/>
  951. <component Cclass="Device" Cgroup="Startup"/>
  952. <component Cclass="CMSIS" Cgroup="RTOS"/>
  953. <category>Getting Started</category>
  954. <category>CMSIS-RTX</category>
  955. </attributes>
  956. </example>
  957. </examples>
  958. <components>
  959. <component Cclass="Device" Cgroup="Startup" Cversion="1.0.0" condition="LPC1800 CMSIS">
  960. <description>System Startup for NXP LPC1800 Series</description>
  961. <RTE_Components_h>
  962. <!-- the following content goes into file 'RTE_Components.h' -->
  963. #define RTE_DEVICE_STARTUP_LPC18XX /* Device Startup for NXP18XX */
  964. </RTE_Components_h>
  965. <files>
  966. <file category="include" name="Device/Include/"/>
  967. <file category="source" name="Device/Source/ARM/startup_LPC18xx.s" attr="config" version="1.0.0" condition="ARM Compiler"/>
  968. <file category="source" name="Device/Source/system_LPC18xx.c" attr="config" version="1.0.1"/>
  969. <!-- device configuration required by drivers at the moment -->
  970. <file category="header" name="CMSIS_Driver/Config/RTE_Device.h" attr="config" version="2.00"/>
  971. </files>
  972. </component>
  973. <component Cclass="Device" Cgroup="SCU" Cversion="1.1" condition="LPC1800 CMSIS">
  974. <description>SCU driver used by RTE Drivers for LPC1800 Series</description>
  975. <files>
  976. <file category="header" name="CMSIS_Driver/SCU_LPC18xx.h"/>
  977. <file category="source" name="CMSIS_Driver/SCU_LPC18xx.c"/>
  978. </files>
  979. </component>
  980. <component Cclass="Device" Cgroup="GPIO" Cversion="1.0" condition="LPC1800 CMSIS">
  981. <description>GPIO driver used by RTE Drivers for LPC1800 Series</description>
  982. <files>
  983. <file category="header" name="CMSIS_Driver/GPIO_LPC18xx.h"/>
  984. <file category="source" name="CMSIS_Driver/GPIO_LPC18xx.c"/>
  985. </files>
  986. </component>
  987. <component Cclass="Device" Cgroup="GPDMA" Cversion="1.3" condition="LPC1800 CMSIS">
  988. <description>GPDMA driver used by RTE Drivers for LPC1800 Series</description>
  989. <files>
  990. <file category="header" name="CMSIS_Driver/GPDMA_LPC18xx.h"/>
  991. <file category="source" name="CMSIS_Driver/GPDMA_LPC18xx.c"/>
  992. </files>
  993. </component>
  994. <component Cclass="CMSIS Driver" Cgroup="CAN" Capiversion="1.0" Cversion="1.4" condition="LPC1800 CMSIS SCU">
  995. <description>CAN Driver for LPC1800 series</description>
  996. <RTE_Components_h> <!-- the following content goes into file 'RTE_Components.h' -->
  997. #define RTE_Drivers_CAN0 /* Driver CAN0 */
  998. #define RTE_Drivers_CAN1 /* Driver CAN1 */
  999. </RTE_Components_h>
  1000. <files>
  1001. <file category="source" name="CMSIS_Driver/CAN_LPC18xx.c"/>
  1002. </files>
  1003. </component>
  1004. <component Cclass="CMSIS Driver" Cgroup="USB Device" Csub="USB0" Capiversion="2.1" Cversion="2.9" condition="LPC1800 CMSIS SCU">
  1005. <description>USB0 Device Driver for the LPC1800 series</description>
  1006. <RTE_Components_h> <!-- the following content goes into file 'RTE_Components.h' -->
  1007. #define RTE_Drivers_USBD0 /* Driver USBD0 */
  1008. </RTE_Components_h>
  1009. <files>
  1010. <file category="source" name="CMSIS_Driver/USBD0_LPC18xx.c"/>
  1011. <file category="source" name="CMSIS_Driver/USB0_LPC18xx.c"/>
  1012. </files>
  1013. </component>
  1014. <component Cclass="CMSIS Driver" Cgroup="USB Device" Csub="USB1" Capiversion="2.1" Cversion="2.7" condition="LPC1800 CMSIS SCU">
  1015. <description>USB1 Device Driver for the LPC1800 series</description>
  1016. <RTE_Components_h> <!-- the following content goes into file 'RTE_Components.h' -->
  1017. #define RTE_Drivers_USBD1 /* Driver USBD1 */
  1018. </RTE_Components_h>
  1019. <files>
  1020. <file category="source" name="CMSIS_Driver/USBD1_LPC18xx.c"/>
  1021. <file category="source" name="CMSIS_Driver/USB1_LPC18xx.c"/>
  1022. </files>
  1023. </component>
  1024. <component Cclass="CMSIS Driver" Cgroup="USB Host" Csub="USB0" Capiversion="2.0" Cversion="2.4" condition="LPC1800 CMSIS SCU">
  1025. <description>USB0 EHCI Host Driver for the LPC1800 series</description>
  1026. <RTE_Components_h> <!-- the following content goes into file 'RTE_Components.h' -->
  1027. #define RTE_Drivers_USBH0 /* Driver USBH0 */
  1028. </RTE_Components_h>
  1029. <files>
  1030. <file category="source" name="CMSIS_Driver/USBH0_LPC18xx.c"/>
  1031. <file category="source" name="CMSIS_Driver/USB0_LPC18xx.c"/>
  1032. </files>
  1033. </component>
  1034. <component Cclass="CMSIS Driver" Cgroup="USB Host" Csub="USB1" Capiversion="2.0" Cversion="2.4" condition="LPC1800 CMSIS SCU">
  1035. <description>USB1 EHCI Host Driver for the LPC1800 series</description>
  1036. <RTE_Components_h> <!-- the following content goes into file 'RTE_Components.h' -->
  1037. #define RTE_Drivers_USBH1 /* Driver USBH1 */
  1038. </RTE_Components_h>
  1039. <files>
  1040. <file category="source" name="CMSIS_Driver/USBH1_LPC18xx.c"/>
  1041. <file category="source" name="CMSIS_Driver/USB1_LPC18xx.c"/>
  1042. </files>
  1043. </component>
  1044. <component Cclass="CMSIS Driver" Cgroup="Ethernet MAC" Capiversion="2.1" Cversion="2.6" condition="LPC1800 CMSIS RTOS SCU">
  1045. <description>Ethernet MAC Driver for LPC1800 Series</description>
  1046. <RTE_Components_h> <!-- the following content goes into file 'RTE_Components.h' -->
  1047. #define RTE_Drivers_ETH_MAC0 /* Driver ETH_MAC0 */
  1048. </RTE_Components_h>
  1049. <files>
  1050. <file category="source" name="CMSIS_Driver/EMAC_LPC18xx.c"/>
  1051. </files>
  1052. </component>
  1053. <component Cclass="CMSIS Driver" Cgroup="MCI" Capiversion="2.2" Cversion="2.5" condition="LPC1800 CMSIS SCU">
  1054. <description>MCI Driver for LPC1800 Series</description>
  1055. <RTE_Components_h> <!-- the following content goes into file 'RTE_Components.h' -->
  1056. #define RTE_Drivers_MCI0 /* Driver MCI0 */
  1057. </RTE_Components_h>
  1058. <files>
  1059. <file category="source" name="CMSIS_Driver/MCI_LPC18xx.c"/>
  1060. </files>
  1061. </component>
  1062. <component Cclass="CMSIS Driver" Cgroup="I2C" Capiversion="2.2" Cversion="2.4" condition="LPC1800 CMSIS SCU">
  1063. <description>I2C Driver for LPC1800 Series</description>
  1064. <RTE_Components_h> <!-- the following content goes into file 'RTE_Components.h' -->
  1065. #define RTE_Drivers_I2C0 /* Driver I2C0 */
  1066. #define RTE_Drivers_I2C1 /* Driver I2C1 */
  1067. </RTE_Components_h>
  1068. <files>
  1069. <file category="source" name="CMSIS_Driver/I2C_LPC18xx.c"/>
  1070. </files>
  1071. </component>
  1072. <component Cclass="CMSIS Driver" Cgroup="SPI" Csub="SSP" Capiversion="2.1" Cversion="2.8" condition="LPC1800 CMSIS SCU GPIO GPDMA">
  1073. <description>SPI (SSP) Driver for LPC1800 Series</description>
  1074. <RTE_Components_h> <!-- the following content goes into file 'RTE_Components.h' -->
  1075. #define RTE_Drivers_SPI0 /* Driver SPI0 */
  1076. #define RTE_Drivers_SPI1 /* Driver SPI1 */
  1077. </RTE_Components_h>
  1078. <files>
  1079. <file category="source" name="CMSIS_Driver/SSP_LPC18xx.c"/>
  1080. </files>
  1081. </component>
  1082. <component Cclass="CMSIS Driver" Cgroup="USART" Capiversion="2.1" Cversion="2.9" condition="LPC1800 CMSIS SCU GPDMA">
  1083. <description>USART Driver for LPC1800 Series</description>
  1084. <RTE_Components_h> <!-- the following content goes into file 'RTE_Components.h' -->
  1085. #define RTE_Drivers_USART0 /* Driver USART0 */
  1086. #define RTE_Drivers_USART1 /* Driver USART1 */
  1087. #define RTE_Drivers_USART2 /* Driver USART2 */
  1088. #define RTE_Drivers_USART3 /* Driver USART3 */
  1089. </RTE_Components_h>
  1090. <files>
  1091. <file category="source" name="CMSIS_Driver/USART_LPC18xx.c"/>
  1092. </files>
  1093. </component>
  1094. <component Cclass="CMSIS Driver" Cgroup="SAI" Csub="I2S" Capiversion="1.0" Cversion="1.4" condition="LPC1800 CMSIS SCU GPDMA">
  1095. <description>SAI (I2S) Driver for LPC1800 Series</description>
  1096. <RTE_Components_h> <!-- the following content goes into file 'RTE_Components.h' -->
  1097. #define RTE_Drivers_SAI0 /* Driver SAI0 */
  1098. #define RTE_Drivers_SAI1 /* Driver SAI1 */
  1099. </RTE_Components_h>
  1100. <files>
  1101. <file category="source" name="CMSIS_Driver/I2S_LPC18xx.c"/>
  1102. </files>
  1103. </component>
  1104. <!-- MCB1800 Development Board -->
  1105. <bundle Cbundle="MCB1800" Cclass="Board Support" Cversion="1.0.0">
  1106. <description>Keil Development Board MCB1800</description>
  1107. <doc>Documents/mcb1800.chm</doc>
  1108. <component Cgroup="A/D Converter" Capiversion="1.00" condition="LPC1800 CMSIS SCU">
  1109. <description>A/D Converter interface for Keil MCB1800 Development Board</description>
  1110. <files>
  1111. <file category="source" name="Boards/Keil/MCB1800/Common/ADC_MCB1800.c"/>
  1112. </files>
  1113. </component>
  1114. <component Cgroup="LED" Capiversion="1.00" condition="LPC1800 CMSIS SCU GPIO">
  1115. <description>LED interface for Keil MCB1800 Development Board</description>
  1116. <files>
  1117. <file category="source" name="Boards/Keil/MCB1800/Common/LED_MCB1800.c"/>
  1118. </files>
  1119. </component>
  1120. <component Cgroup="Buttons" Capiversion="1.00" condition="LPC1800 CMSIS SCU GPIO">
  1121. <description>Buttons interface for Keil MCB1800 Development Board</description>
  1122. <files>
  1123. <file category="source" name="Boards/Keil/MCB1800/Common/Buttons_MCB1800.c"/>
  1124. </files>
  1125. </component>
  1126. <component Cgroup="Joystick" Capiversion="1.00" condition="LPC1800 CMSIS SCU GPIO">
  1127. <description>Joystick interface for Keil MCB1800 Development Board</description>
  1128. <files>
  1129. <file category="source" name="Boards/Keil/MCB1800/Common/Joystick_MCB1800.c"/>
  1130. </files>
  1131. </component>
  1132. <component Cgroup="Graphic LCD" Capiversion="1.00" condition="LPC1800 CMSIS SCU GPIO SPI">
  1133. <description>Graphic LCD interface for Keil MCB1800 Development Board</description>
  1134. <files>
  1135. <file category="header" name="Boards/Keil/MCB1800/Common/GLCD_Config.h"/>
  1136. <file category="source" name="Boards/Keil/MCB1800/Common/GLCD_Fonts.c"/>
  1137. <file category="source" name="Boards/Keil/MCB1800/Common/GLCD_MCB1800.c"/>
  1138. </files>
  1139. </component>
  1140. <component Cgroup="Touchscreen" Capiversion="1.00" Csub="STMPE811" condition="LPC1800 CMSIS RTOS and I2C Driver">
  1141. <description>Touchscreen interface for STMPE811</description>
  1142. <files>
  1143. <file category="header" name="Boards/Keil/MCB1800/Common/STMPE811.h"/>
  1144. <file category="source" name="Boards/Keil/MCB1800/Common/Touch_STMPE811.c"/>
  1145. </files>
  1146. </component>
  1147. <component Cgroup="Thermometer" Capiversion="1.00" Csub="LM75" condition="LPC1800 CMSIS I2C Driver">
  1148. <description>Thermometer interface for LM75</description>
  1149. <files>
  1150. <file category="source" name="Boards/Keil/MCB1800/Common/Thermometer_LM75.c"/>
  1151. </files>
  1152. </component>
  1153. <component Cgroup="EEPROM" Capiversion="1.00" Csub="24LC128" condition="LPC1800 CMSIS I2C Driver">
  1154. <description>EEPROM interface for 24LC128</description>
  1155. <files>
  1156. <file category="source" name="Boards/Keil/MCB1800/Common/EEPROM_24LC128.c"/>
  1157. </files>
  1158. </component>
  1159. <component Cgroup="Audio" Capiversion="1.01" condition="LPC1800 CMSIS SCU GPIO SAI/I2C Driver">
  1160. <description>Audio interface for UDA1380</description>
  1161. <files>
  1162. <file category="source" name="Boards/Keil/MCB1800/Common/Audio_UDA1380.c"/>
  1163. </files>
  1164. </component>
  1165. </bundle>
  1166. </components>
  1167. </package>