arm_softmax_s8.c 8.1 KB

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  1. /*
  2. * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved.
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Licensed under the Apache License, Version 2.0 (the License); you may
  7. * not use this file except in compliance with the License.
  8. * You may obtain a copy of the License at
  9. *
  10. * www.apache.org/licenses/LICENSE-2.0
  11. *
  12. * Unless required by applicable law or agreed to in writing, software
  13. * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  14. * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  15. * See the License for the specific language governing permissions and
  16. * limitations under the License.
  17. */
  18. /* ----------------------------------------------------------------------
  19. * Project: CMSIS NN Library
  20. * Title: arm_softmax_s8.c
  21. * Description: S8 softmax function
  22. *
  23. * $Date: 01. March 2021
  24. * $Revision: V.2.0.2
  25. *
  26. * Target Processor: Cortex-M cores
  27. *
  28. * -------------------------------------------------------------------- */
  29. #include "arm_nnfunctions.h"
  30. #include "arm_nnsupportfunctions.h"
  31. #define ACCUM_BITS 12
  32. #ifdef ARM_MATH_MVEI
  33. static int32x4_t arm_exp_on_negative_values_mve_32x4(int32x4_t val)
  34. {
  35. #define SHIFT_START (24)
  36. int32_t shift = SHIFT_START;
  37. int32x4_t mask;
  38. const int32x4_t val_mod_minus_quarter =
  39. vandq_s32(val, vdupq_n_s32((1 << SHIFT_START) - 1)) - vdupq_n_s32(1 << SHIFT_START);
  40. const int32x4_t remainder = vsubq_s32(val_mod_minus_quarter, val);
  41. const int32x4_t x = vaddq_n_s32(val_mod_minus_quarter << 5, 1 << 28);
  42. const int32x4_t x2 = MUL_SAT_MVE(x, x);
  43. const int32x4_t op_1 = DIV_POW2_MVE(MUL_SAT_MVE(x2, x2), 2) + MUL_SAT_MVE(x2, x);
  44. const int32x4_t op_2 = x + DIV_POW2_MVE(MUL_SAT_MVE(op_1, vdupq_n_s32(715827883)) + x2, 1);
  45. int32x4_t result = vdupq_n_s32(1895147668) + MUL_SAT_MVE(vdupq_n_s32(1895147668), op_2);
  46. #define SELECT_IF_NON_ZERO(x) \
  47. { \
  48. mve_pred16_t p = vcmpneq_n_s32(remainder & vdupq_n_s32(1 << shift++), 0); \
  49. mask = vmvnq_m_s32(vdupq_n_s32(0), vdupq_n_s32(0), p); \
  50. result = SELECT_USING_MASK(mask, MUL_SAT_MVE(result, vdupq_n_s32(x)), result); \
  51. }
  52. SELECT_IF_NON_ZERO(1672461947)
  53. SELECT_IF_NON_ZERO(1302514674)
  54. SELECT_IF_NON_ZERO(790015084)
  55. SELECT_IF_NON_ZERO(290630308)
  56. SELECT_IF_NON_ZERO(39332535)
  57. SELECT_IF_NON_ZERO(720401)
  58. SELECT_IF_NON_ZERO(242)
  59. #undef SELECT_IF_NON_ZERO
  60. mve_pred16_t p = vcmpeqq_n_s32(val, 0);
  61. mask = vmvnq_m_s32(vdupq_n_s32(0), vdupq_n_s32(0), p);
  62. result = SELECT_USING_MASK(mask, vdupq_n_s32(Q31_MAX), result);
  63. return result;
  64. }
  65. #endif
  66. /**
  67. * @ingroup groupNN
  68. */
  69. /**
  70. * @addtogroup Softmax
  71. * @{
  72. */
  73. void arm_softmax_s8(const int8_t *input,
  74. const int32_t num_rows,
  75. const int32_t row_size,
  76. const int32_t mult,
  77. const int32_t shift,
  78. const int32_t diff_min,
  79. int8_t *output)
  80. {
  81. #ifdef ARM_MATH_MVEI
  82. #define ACT_MIN ((int8_t)Q7_MIN)
  83. #define ACT_MAX ((int8_t)Q7_MAX)
  84. const int32_t mask = (1 << shift);
  85. for (int i_num_rows = 0; i_num_rows < num_rows; ++i_num_rows)
  86. {
  87. int8_t max = ACT_MIN;
  88. int32_t vec_count = (row_size + 15) / 16;
  89. uint32_t r_count = (uint32_t)row_size;
  90. for (int i = 0; i < vec_count; i++)
  91. {
  92. mve_pred16_t p = vctp8q(r_count);
  93. const int8x16_t ip = vldrbq_z_s8(&input[i * 16], p);
  94. max = vmaxvq_p_s8(max, ip, p);
  95. r_count -= 16;
  96. }
  97. vec_count = row_size / 4;
  98. int32_t idx = 0;
  99. int32_t sum = 0;
  100. while (vec_count)
  101. {
  102. int32x4_t ip = vldrbq_s32(&input[idx * 4]);
  103. ip = vsubq_n_s32(ip, max);
  104. mve_pred16_t p = vcmpgeq_n_s32(ip, diff_min);
  105. if (p != 0)
  106. {
  107. ip = vmulq_n_s32(ip, mask);
  108. int32x4_t res = MUL_SAT_MVE(ip, vdupq_n_s32(mult));
  109. res = arm_exp_on_negative_values_mve_32x4(res);
  110. res = DIV_POW2_MVE(res, ACCUM_BITS);
  111. res = vpselq_s32(res, vdupq_n_s32(0), p);
  112. sum += vaddvq_s32(res);
  113. }
  114. vec_count--;
  115. idx++;
  116. }
  117. const int32_t tail_idx = row_size & ~3;
  118. for (int i = 0; i < (row_size & 3); i++)
  119. {
  120. const int32_t diff = input[tail_idx + i] - max;
  121. if (diff >= diff_min)
  122. {
  123. sum += DIV_POW2(EXP_ON_NEG(MUL_SAT(diff * mask, mult)), ACCUM_BITS);
  124. }
  125. }
  126. const int32_t headroom = __CLZ((uint32_t)sum);
  127. const int32_t bits_over_unit = ACCUM_BITS - headroom + 23;
  128. const int32_t shifted_scale = ONE_OVER1((sum > 0 ? sum << headroom : 0) - (1 << 31));
  129. vec_count = row_size / 4;
  130. idx = 0;
  131. while (vec_count)
  132. {
  133. int32x4_t ip = vldrbq_s32(&input[idx]);
  134. ip = vsubq_n_s32(ip, max);
  135. mve_pred16_t p = vcmpgeq_n_s32(ip, diff_min);
  136. int32x4_t tmp_res;
  137. if (p != 0)
  138. {
  139. ip = vmulq_n_s32(ip, mask);
  140. tmp_res = MUL_SAT_MVE(ip, vdupq_n_s32(mult));
  141. tmp_res = arm_exp_on_negative_values_mve_32x4(tmp_res);
  142. tmp_res = MUL_SAT_MVE(vdupq_n_s32(shifted_scale), tmp_res);
  143. tmp_res = DIV_POW2_MVE(tmp_res, bits_over_unit);
  144. tmp_res += vdupq_n_s32(ACT_MIN);
  145. tmp_res = vmaxq_s32(tmp_res, vdupq_n_s32(ACT_MIN));
  146. tmp_res = vminq_s32(tmp_res, vdupq_n_s32(ACT_MAX));
  147. tmp_res = vpselq_s32(tmp_res, vdupq_n_s32(ACT_MIN), p);
  148. }
  149. else
  150. {
  151. tmp_res = vdupq_n_s32(ACT_MIN);
  152. }
  153. vstrbq_s32(&output[idx], tmp_res);
  154. vec_count--;
  155. idx += 4;
  156. }
  157. for (int i = 0; i < (row_size & 3); i++)
  158. {
  159. int32_t diff = input[tail_idx + i] - max;
  160. if (diff >= diff_min)
  161. {
  162. const int32_t res =
  163. DIV_POW2(MUL_SAT(shifted_scale, EXP_ON_NEG(MUL_SAT(diff * mask, mult))), bits_over_unit) - 128;
  164. output[tail_idx + i] = (int8_t)CLAMP(res, (int32_t)ACT_MAX, (int32_t)ACT_MIN);
  165. }
  166. else
  167. {
  168. output[tail_idx + i] = ACT_MIN;
  169. }
  170. }
  171. input += row_size;
  172. output += row_size;
  173. }
  174. #else
  175. const int32_t mask = (1 << shift);
  176. int32_t col = 0;
  177. int32_t row_idx;
  178. for (row_idx = 0; row_idx < num_rows; ++row_idx)
  179. {
  180. // Find the maximum value in order to ensure numerical stability
  181. int8_t max = *input;
  182. for (col = 1; col < row_size; ++col)
  183. {
  184. max = MAX(max, input[col]);
  185. }
  186. int32_t diff = 0;
  187. int32_t sum = 0;
  188. for (col = 0; col < row_size; ++col)
  189. {
  190. diff = input[col] - max;
  191. if (diff >= diff_min)
  192. {
  193. sum += DIV_POW2(EXP_ON_NEG(MUL_SAT(diff * mask, mult)), ACCUM_BITS);
  194. }
  195. }
  196. const int32_t headroom = __CLZ(sum);
  197. const int32_t bits_over_unit = ACCUM_BITS - headroom + 23;
  198. const int32_t shifted_scale = ONE_OVER1((sum > 0 ? sum << headroom : 0) - (1 << 31));
  199. for (col = 0; col < row_size; ++col)
  200. {
  201. diff = input[col] - max;
  202. if (diff >= diff_min)
  203. {
  204. const int32_t res =
  205. DIV_POW2(MUL_SAT(shifted_scale, EXP_ON_NEG(MUL_SAT(diff * mask, mult))), bits_over_unit) - 128;
  206. output[col] = (int8_t)CLAMP(res, (int32_t)127, (int32_t)-128);
  207. }
  208. else
  209. {
  210. output[col] = -128;
  211. }
  212. }
  213. input += row_size;
  214. output += row_size;
  215. }
  216. #endif
  217. }
  218. /**
  219. * @} end of Softmax group
  220. */