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  113. <div class="title">Peripheral Access</div>  </div>
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    116. 

  116. 

  117. <p>Naming conventions and optional features for accessing peripherals.  
    118. 

  118. <a href="#details">More...</a></p>
    119. 

  119. <table class="memberdecls">
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  120. <tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
    121. 

  121. Macros</h2></td></tr>
    122. 

  122. <tr class="memitem:ga286e3b913dbd236c7f48ea70c8821f4e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e">_VAL2FLD</a>(field, value)</td></tr>
    123. 

  123. <tr class="memdesc:ga286e3b913dbd236c7f48ea70c8821f4e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mask and shift a bit field value for assigning the result to a peripheral register.  <a href="#ga286e3b913dbd236c7f48ea70c8821f4e">More...</a><br/></td></tr>
    124. 

  124. <tr class="separator:ga286e3b913dbd236c7f48ea70c8821f4e"><td class="memSeparator" colspan="2">&#160;</td></tr>
    125. 

  125. <tr class="memitem:ga139b6e261c981f014f386927ca4a8444"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__peripheral__gr.html#ga139b6e261c981f014f386927ca4a8444">_FLD2VAL</a>(field, value)</td></tr>
    126. 

  126. <tr class="memdesc:ga139b6e261c981f014f386927ca4a8444"><td class="mdescLeft">&#160;</td><td class="mdescRight">Extract from a peripheral register value the a bit field value.  <a href="#ga139b6e261c981f014f386927ca4a8444">More...</a><br/></td></tr>
    127. 

  127. <tr class="separator:ga139b6e261c981f014f386927ca4a8444"><td class="memSeparator" colspan="2">&#160;</td></tr>
    128. 

  128. </table>
    129. 

  129. <a name="details" id="details"></a><h2 class="groupheader">Description</h2>
    130. 

  130. <p>The section below describes the naming conventions, requirements, and optional features for accessing device specific peripherals. Most of the rules also apply to the core peripherals. The <a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> contains typically these definition and also includes the core specific header files.</p>
    131. 

  131. <p>The definitions for <a class="el" href="group__peripheral__gr.html">Peripheral Access</a> can be generated using the <a href="../../SVD/html/index.html"><b>CMSIS-SVD</b></a> System View Description for Peripherals. Refer to <a href="../../SVD/html/svd_SVDConv_pg.html"><b>SVDConv.exe</b></a> for more information.</p>
    132. 

  132. <p>Each peripheral provides a data type definition with a name that is composed of:</p>
    133. 

  133. <ul>
    134. 

  134. <li>an optional prefix <b>&lt;<em>device abbreviation&gt;</em>_</b></li>
    135. 

  135. <li><b>&lt;<em>peripheral name</em>&gt;</b></li>
    136. 

  136. <li>postfix <b>_Type</b> or <b>_TypeDef</b> to identify a type definition.</li>
    137. 

  137. </ul>
    138. 

  138. <p>Examples:</p>
    139. 

  139. <ul>
    140. 

  140. <li><b>UART_TypeDef</b> for the peripheral <b>UART</b>.</li>
    141. 

  141. <li><b>LPC_UART_TypeDef</b> for the device family <b>LPC</b> and the peripheral <b>UART</b>.</li>
    142. 

  142. </ul>
    143. 

  143. <p>The data type definition uses standard C data types defined by the ANSI C header file &lt;stdint.h&gt;.</p>
    144. 

  144. <ul>
    145. 

  145. <li>IO Type Qualifiers are used to specify the access to peripheral variables. <table class="doxtable">
    146. 

  146. <tr>
    147. 

  147. <th align="left">IO Type Qualifier </th><th align="left">Type </th><th align="left">Description  </th></tr>
    148. 

  148. <tr>
    149. 

  149. <td align="left"><b>__IM</b> </td><td align="left">Struct member </td><td align="left">Defines 'read only' permissions </td></tr>
    150. 

  150. <tr>
    151. 

  151. <td align="left"><b>__OM</b> </td><td align="left">Struct member </td><td align="left">Defines 'write only' permissions </td></tr>
    152. 

  152. <tr>
    153. 

  153. <td align="left"><b>__IOM</b> </td><td align="left">Struct member </td><td align="left">Defines 'read / write' permissions </td></tr>
    154. 

  154. <tr>
    155. 

  155. <td align="left"><b>__I</b> </td><td align="left">Scalar variable </td><td align="left">Defines 'read only' permissions </td></tr>
    156. 

  156. <tr>
    157. 

  157. <td align="left"><b>__O</b> </td><td align="left">Scalar variable </td><td align="left">Defines 'write only' permissions </td></tr>
    158. 

  158. <tr>
    159. 

  159. <td align="left"><b>__IO</b> </td><td align="left">Scalar variable </td><td align="left">Defines 'read / write' permissions </td></tr>
    160. 

  160. </table>
    161. 

  161. <dl class="section note"><dt>Note</dt><dd><b>__IM</b>, <b>__OM</b>, <b>__IOM</b> are added in CMSIS-Core V4.20 to enhance support for C++. Prior version used <b>__I</b>, <b>__O</b>, <b>__IO</b> also for struct member definitions.</dd></dl>
    162. 

  162. The typedef <b>&lt;<em>device abbreviation</em>&gt;_UART_TypeDef</b> shown below defines the generic register layout for all UART channels in a device.</li>
    163. 

  163. </ul>
    164. 

  164. <div class="fragment"><div class="line"><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
    165. 

  165. <div class="line">{</div>
    166. 

  166. <div class="line">  <span class="keyword">union </span>{</div>
    167. 

  167. <div class="line">  __IM  uint8_t  RBR;                 <span class="comment">/* Offset: 0x000 (R/ )  Receiver Buffer Register            */</span></div>
    168. 

  168. <div class="line">  __OM  uint8_t  THR;                 <span class="comment">/* Offset: 0x000 ( /W)  Transmit Holding Register           */</span></div>
    169. 

  169. <div class="line">  __IOM uint8_t  DLL;                 <span class="comment">/* Offset: 0x000 (R/W)  Divisor Latch LSB                   */</span></div>
    170. 

  170. <div class="line">        uint32_t RESERVED0;</div>
    171. 

  171. <div class="line">  };</div>
    172. 

  172. <div class="line">  <span class="keyword">union </span>{</div>
    173. 

  173. <div class="line">  __IOM uint8_t  DLM;                 <span class="comment">/* Offset: 0x004 (R/W)  Divisor Latch MSB                   */</span></div>
    174. 

  174. <div class="line">  __IOM uint32_t IER;                 <span class="comment">/* Offset: 0x004 (R/W)  Interrupt Enable Register           */</span></div>
    175. 

  175. <div class="line">  };</div>
    176. 

  176. <div class="line">  <span class="keyword">union </span>{</div>
    177. 

  177. <div class="line">  __IM  uint32_t IIR;                 <span class="comment">/* Offset: 0x008 (R/ )  Interrupt ID Register               */</span></div>
    178. 

  178. <div class="line">  __OM  uint8_t  FCR;                 <span class="comment">/* Offset: 0x008 ( /W)  FIFO Control Register               */</span></div>
    179. 

  179. <div class="line">  };</div>
    180. 

  180. <div class="line">  __IOM uint8_t  LCR;                 <span class="comment">/* Offset: 0x00C (R/W)  Line Control Register               */</span></div>
    181. 

  181. <div class="line">        uint8_t  RESERVED1[7];</div>
    182. 

  182. <div class="line">  __IM  uint8_t  LSR;                 <span class="comment">/* Offset: 0x014 (R/ )  Line Status Register                */</span></div>
    183. 

  183. <div class="line">        uint8_t  RESERVED2[7];</div>
    184. 

  184. <div class="line">  __IOM uint8_t  SCR;                 <span class="comment">/* Offset: 0x01C (R/W)  Scratch Pad Register                */</span></div>
    185. 

  185. <div class="line">        uint8_t  RESERVED3[3];</div>
    186. 

  186. <div class="line">  __IOM uint32_t ACR;                 <span class="comment">/* Offset: 0x020 (R/W)  Autobaud Control Register           */</span></div>
    187. 

  187. <div class="line">  __IOM uint8_t  ICR;                 <span class="comment">/* Offset: 0x024 (R/W)  IrDA Control Register               */</span></div>
    188. 

  188. <div class="line">        uint8_t  RESERVED4[3];</div>
    189. 

  189. <div class="line">  __IOM uint8_t  FDR;                 <span class="comment">/* Offset: 0x028 (R/W)  Fractional Divider Register         */</span></div>
    190. 

  190. <div class="line">        uint8_t  RESERVED5[7];</div>
    191. 

  191. <div class="line">  __IOM uint8_t  TER;                 <span class="comment">/* Offset: 0x030 (R/W)  Transmit Enable Register            */</span></div>
    192. 

  192. <div class="line">        uint8_t  RESERVED6[39];</div>
    193. 

  193. <div class="line">  __IM  uint8_t  FIFOLVL;             <span class="comment">/* Offset: 0x058 (R/ )  FIFO Level Register                 */</span></div>
    194. 

  194. <div class="line">} LPC_UART_TypeDef;</div>
    195. 

  195. </div><!-- fragment --><p>To access the registers of the UART defined above, pointers to this register structure are defined. If more instances of a peripheral exist, the variables have a postfix (digit or letter) that identifies the peripheral.</p>
    196. 

  196. <p><b>Example:</b> In this example <b>LPC_UART2</b> and <b>LPC_UART3</b> are two pointers to UARTs defined with above register structure. <br/>
    197. 

  197. </p>
    198. 

  198. <div class="fragment"><div class="line"><span class="preprocessor">#define LPC_UART2             ((LPC_UART_TypeDef      *) LPC_UART2_BASE    )</span></div>
    199. 

  199. <div class="line"><span class="preprocessor">#define LPC_UART3             ((LPC_UART_TypeDef      *) LPC_UART3_BASE    )</span></div>
    200. 

  200. </div><!-- fragment --><dl class="section note"><dt>Note</dt><dd><ul>
    201. 

  201. <li>The prefix <b>LPC</b> is optional.</li>
    202. 

  202. </ul>
    203. 

  203. </dd></dl>
    204. 

  204. <p>The registers in the various UARTs can now be referred in the user code as shown below:<br/>
    205. 

  205. </p>
    206. 

  206. <div class="fragment"><div class="line">val = LPC_UART2-&gt;DR   <span class="comment">// is the data register of UART1.</span></div>
    207. 

  207. </div><!-- fragment --><hr/>
    208. 

  208. <h1><a class="anchor" id="core_cmsis_pal_min_reqs"></a>
    209. 

  209. Minimal Requirements</h1>
    210. 

  210. <p>To access the peripheral registers and related function in a device, the files <b><em>device.h</em></b> and <b>core_cm<em>#</em>.h</b> define as a minimum: <br/>
    211. 

  211. <br/>
    212. 

  212. </p>
    213. 

  213. <ul>
    214. 

  214. <li>The <b>Register Layout Typedef</b> for each peripheral that defines all register names. RESERVED is used to introduce space into the structure for adjusting the addresses of the peripheral registers. <br/>
    215. 

  215. <br/>
    216. 

  216. <b>Example:</b> <div class="fragment"><div class="line"><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
    217. 

  217. <div class="line">{</div>
    218. 

  218. <div class="line">  __IOM uint32_t CTRL;                <span class="comment">/* Offset: 0x000 (R/W)  SysTick Control and Status Register */</span></div>
    219. 

  219. <div class="line">  __IOM uint32_t LOAD;                <span class="comment">/* Offset: 0x004 (R/W)  SysTick Reload Value Register       */</span></div>
    220. 

  220. <div class="line">  __IOM uint32_t VAL;                 <span class="comment">/* Offset: 0x008 (R/W)  SysTick Current Value Register      */</span></div>
    221. 

  221. <div class="line">  __IM  uint32_t CALIB;               <span class="comment">/* Offset: 0x00C (R/ )  SysTick Calibration Register        */</span></div>
    222. 

  222. <div class="line">} <a class="code" href="structSysTick__Type.html">SysTick_Type</a>;</div>
    223. 

  223. </div><!-- fragment --></li>
    224. 

  224. <li><b>Base Address</b> for each peripheral (in case of multiple peripherals that use the same <b>register layout typedef</b> multiple base addresses are defined). <br/>
    225. 

  225. <br/>
    226. 

  226. <b>Example:</b> <div class="fragment"><div class="line"><span class="preprocessor">#define SysTick_BASE (SCS_BASE + 0x0010)            </span><span class="comment">/* SysTick Base Address     */</span><span class="preprocessor"></span></div>
    227. 

  227. </div><!-- fragment --></li>
    228. 

  228. <li><b>Access Definitions</b> for each peripheral. In case of multiple peripherals that are using the same <b>register layout typdef</b>, multiple access definitions exist (LPC_UART0, LPC_UART2). <br/>
    229. 

  229. <br/>
    230. 

  230. <b>Example:</b> <div class="fragment"><div class="line"><span class="preprocessor">#define SysTick ((SysTick_Type *) Systick_BASE)    </span><span class="comment">/* SysTick access definition */</span><span class="preprocessor"></span></div>
    231. 

  231. </div><!-- fragment --></li>
    232. 

  232. </ul>
    233. 

  233. <p>These definitions allow accessing peripheral registers with simple assignments.</p>
    234. 

  234. <ul>
    235. 

  235. <li><b>Example:</b> <br/>
    236. 

  236. <div class="fragment"><div class="line">SysTick-&gt;CTRL = 0;</div>
    237. 

  237. </div><!-- fragment --></li>
    238. 

  238. </ul>
    239. 

  239. <hr/>
    240. 

  240. <h1><a class="anchor" id="core_cmsis_pal_opts"></a>
    241. 

  241. Optional Features</h1>
    242. 

  242. <p>Optionally, the file <b><em>device</em>.h</b> may define:</p>
    243. 

  243. <ul>
    244. 

  244. <li><a class="el" href="group__peripheral__gr.html#core_cmsis_pal_bitfields">Register Bit Fields</a> and #define constants that simplify access to peripheral registers. These constants may define bit-positions or other specific patterns that are required for programming peripheral registers. The identifiers should start with <b>&lt;<em>device abbreviation</em>&gt;_</b> and <b>&lt;<em>peripheral name</em>&gt;_</b>. It is recommended to use CAPITAL letters for #define constants.</li>
    245. 

  245. <li>More complex functions (i.e. status query before a sending register is accessed). Again, these functions start with <b>&lt;<em>device abbreviation</em>&gt;_</b> and <b>&lt;<em>peripheral name</em>&gt;_</b>.</li>
    246. 

  246. </ul>
    247. 

  247. <hr/>
    248. 

  248. <h1><a class="anchor" id="core_cmsis_pal_bitfields"></a>
    249. 

  249. Register Bit Fields</h1>
    250. 

  250. <p>For Core Register, macros define the position and the mask value for a bit field. It is recommended to create such definitions also for other peripheral registers.</p>
    251. 

  251. <p><b>Example:</b></p>
    252. 

  252. <p>Bit field definitions for register CPUID in SCB (System Control Block).</p>
    253. 

  253. <div class="fragment"><div class="line"><span class="comment">/* SCB CPUID Register Definitions */</span></div>
    254. 

  254. <div class="line"><span class="preprocessor">#define SCB_CPUID_IMPLEMENTER_Pos      24U                                       </span></div>
    255. 

  255. <div class="line"><span class="preprocessor">#define SCB_CPUID_IMPLEMENTER_Msk      (0xFFUL &lt;&lt; SCB_CPUID_IMPLEMENTER_Pos)     </span></div>
    256. 

  256. <div class="line"><span class="preprocessor">#define SCB_CPUID_VARIANT_Pos          20U                                       </span></div>
    257. 

  257. <div class="line"><span class="preprocessor">#define SCB_CPUID_VARIANT_Msk          (0xFUL &lt;&lt; SCB_CPUID_VARIANT_Pos)          </span></div>
    258. 

  258. <div class="line"><span class="preprocessor">#define SCB_CPUID_ARCHITECTURE_Pos     16U                                       </span></div>
    259. 

  259. <div class="line"><span class="preprocessor">#define SCB_CPUID_ARCHITECTURE_Msk     (0xFUL &lt;&lt; SCB_CPUID_ARCHITECTURE_Pos)     </span></div>
    260. 

  260. <div class="line"><span class="preprocessor">#define SCB_CPUID_PARTNO_Pos            4U                                       </span></div>
    261. 

  261. <div class="line"><span class="preprocessor">#define SCB_CPUID_PARTNO_Msk           (0xFFFUL &lt;&lt; SCB_CPUID_PARTNO_Pos)         </span></div>
    262. 

  262. <div class="line"><span class="preprocessor">#define SCB_CPUID_REVISION_Pos          0U                                       </span></div>
    263. 

  263. <div class="line"><span class="preprocessor">#define SCB_CPUID_REVISION_Msk         (0xFUL </span><span class="comment">/*&lt;&lt; SCB_CPUID_REVISION_Pos*/</span><span class="preprocessor">)     </span></div>
    264. 

  264. </div><!-- fragment --><p>The macros <b><a class="el" href="group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e" title="Mask and shift a bit field value for assigning the result to a peripheral register. ">_VAL2FLD(field, value)</a></b> and <b><a class="el" href="group__peripheral__gr.html#ga139b6e261c981f014f386927ca4a8444" title="Extract from a peripheral register value the a bit field value. ">_FLD2VAL(field, value)</a></b> enable access to bit fields. </p>
    265. 

  265. <h2 class="groupheader">Macro Definition Documentation</h2>
    266. 

  266. <a class="anchor" id="ga139b6e261c981f014f386927ca4a8444"></a>
    267. 

  267. <div class="memitem">
    268. 

  268. <div class="memproto">
    269. 

  269.       <table class="memname">
    270. 

  270.         <tr>
    271. 

  271.           <td class="memname">#define _FLD2VAL</td>
    272. 

  272.           <td>(</td>
    273. 

  273.           <td class="paramtype">&#160;</td>
    274. 

  274.           <td class="paramname">field, </td>
    275. 

  275.         </tr>
    276. 

  276.         <tr>
    277. 

  277.           <td class="paramkey"></td>
    278. 

  278.           <td></td>
    279. 

  279.           <td class="paramtype">&#160;</td>
    280. 

  280.           <td class="paramname">value&#160;</td>
    281. 

  281.         </tr>
    282. 

  282.         <tr>
    283. 

  283.           <td></td>
    284. 

  284.           <td>)</td>
    285. 

  285.           <td></td><td></td>
    286. 

  286.         </tr>
    287. 

  287.       </table>
    288. 

  288. </div><div class="memdoc">
    289. 

  289. <dl class="params"><dt>Parameters</dt><dd>
    290. 

  290.   <table class="params">
    291. 

  291.     <tr><td class="paramname">field</td><td>name of bit field. </td></tr>
    292. 

  292.     <tr><td class="paramname">value</td><td>value of the register. This parameter is interpreted as an uint32_t type.</td></tr>
    293. 

  293.   </table>
    294. 

  294.   </dd>
    295. 

  295. </dl>
    296. 

  296. <p>The macro <a class="el" href="group__peripheral__gr.html#ga139b6e261c981f014f386927ca4a8444">_FLD2VAL</a> uses the #define's <em>_Pos</em> and <em>_Msk</em> of the related bit field to extract the value of a bit field from a register.</p>
    297. 

  297. <p><b>Example:</b> </p>
    298. 

  298. <div class="fragment"><div class="line"><span class="keywordtype">id</span> = <a class="code" href="group__peripheral__gr.html#ga139b6e261c981f014f386927ca4a8444">_FLD2VAL</a>(SCB_CPUID_REVISION, SCB-&gt;CPUID);</div>
    299. 

  299. </div><!-- fragment --> 
    300. 

  300. </div>
    301. 

  301. </div>
    302. 

  302. <a class="anchor" id="ga286e3b913dbd236c7f48ea70c8821f4e"></a>
    303. 

  303. <div class="memitem">
    304. 

  304. <div class="memproto">
    305. 

  305.       <table class="memname">
    306. 

  306.         <tr>
    307. 

  307.           <td class="memname">#define _VAL2FLD</td>
    308. 

  308.           <td>(</td>
    309. 

  309.           <td class="paramtype">&#160;</td>
    310. 

  310.           <td class="paramname">field, </td>
    311. 

  311.         </tr>
    312. 

  312.         <tr>
    313. 

  313.           <td class="paramkey"></td>
    314. 

  314.           <td></td>
    315. 

  315.           <td class="paramtype">&#160;</td>
    316. 

  316.           <td class="paramname">value&#160;</td>
    317. 

  317.         </tr>
    318. 

  318.         <tr>
    319. 

  319.           <td></td>
    320. 

  320.           <td>)</td>
    321. 

  321.           <td></td><td></td>
    322. 

  322.         </tr>
    323. 

  323.       </table>
    324. 

  324. </div><div class="memdoc">
    325. 

  325. <dl class="params"><dt>Parameters</dt><dd>
    326. 

  326.   <table class="params">
    327. 

  327.     <tr><td class="paramname">field</td><td>name of bit field. </td></tr>
    328. 

  328.     <tr><td class="paramname">value</td><td>value for the bit field. This parameter is interpreted as an uint32_t type.</td></tr>
    329. 

  329.   </table>
    330. 

  330.   </dd>
    331. 

  331. </dl>
    332. 

  332. <p>The macro <a class="el" href="group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e">_VAL2FLD</a> uses the #define's <em>_Pos</em> and <em>_Msk</em> of the related bit field to shift bit-field values for assigning to a register.</p>
    333. 

  333. <p><b>Example:</b> </p>
    334. 

  334. <div class="fragment"><div class="line">SCB-&gt;CPUID = <a class="code" href="group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e">_VAL2FLD</a>(SCB_CPUID_REVISION, 0x3) | <a class="code" href="group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e">_VAL2FLD</a>(SCB_CPUID_VARIANT, 0x3);</div>
    335. 

  335. </div><!-- fragment --> 
    336. 

  336. </div>
    337. 

  337. </div>
    338. 

  338. </div><!-- contents -->
    339. 

  339. </div><!-- doc-content -->
    340. 

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    341. 

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  342.   <ul>
    343. 

  343.     <li class="footer">Generated on Wed Feb 8 2017 10:20:41 for CMSIS-CORE by ARM Ltd. All rights reserved.
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