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<div class="title">TrustZone setup: partition_&lt;device&gt;.h </div>  </div>
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<div class="textblock"><p>The <a class="el" href="partition_h_pg.html">TrustZone setup: partition_&lt;device&gt;.h</a> header file contains the initial setup of the TrustZone hardware in an Armv8-M system.</p>
<p>This file implements the function <a class="el" href="group__sau__trustzone__functions.html#ga6093bc5939ea8924fbcfdffb8f0553f1">TZ_SAU_Setup</a> that is call from <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2">SystemInit</a>. It uses settings in these files:</p>
<ul>
<li><a class="el" href="partition_h_pg.html">partition_&lt;device&gt;.h</a> that defines the initial system configuration and during SystemInit in Secure state.</li>
<li><a class="el" href="partition_h_pg.html#partition_gen_h_pg">partition_gen.h</a> that contains SAU region and interrupt target assignments. This file may be generated using <a href="../../Zone/html/index.html"><b>CMSIS-Zone</b></a>.</li>
</ul>
<dl class="section note"><dt>Note</dt><dd><a class="el" href="partition_h_pg.html#partition_gen_h_pg">partition_gen.h</a> is optional and can be generated using <a href="../../Zone/html/index.html"><b>CMSIS-Zone</b></a>. In previous versions of CMSIS-Core(M) this settings were part of <a class="el" href="partition_h_pg.html">partition_&lt;device&gt;.h</a>.</dd></dl>
<p>&#160;</p>
<p>The <a class="el" href="partition_h_pg.html">partition_&lt;device&gt;.h</a> file contains the following configuration settings for:</p>
<ul>
<li><a class="el" href="partition_h_pg.html#sau_ctrlregister_sec">SAU CTRL register settings</a> provides settings for the SAU CTRL register.</li>
<li><a class="el" href="partition_h_pg.html#sau_sleepexception_sec">Configuration of Sleep and Exception behaviour</a> provides device-specific deep-sleep and exception settings.</li>
<li><a class="el" href="partition_h_pg.html#sau_fpu_sec">Configuration of Floating Point Unit</a> defines the usage of the Floating Point Unit in secure and non-secure state.</li>
</ul>
<p>The <a class="el" href="partition_h_pg.html">partition_&lt;device&gt;.h</a> file includes the <a class="el" href="partition_h_pg.html#partition_gen_h_pg">partition_gen.h</a> file with configuration settings for:</p>
<ul>
<li><a class="el" href="partition_h_pg.html#sau_regions_sect">Configuration of the SAU Address Regions</a> provides configuration of the SAU Address Regions.</li>
<li><a class="el" href="partition_h_pg.html#sau_interrupttarget_sec">Configuration of Interrupt Target settings</a> provides device-specific interrupt target settings.</li>
</ul>
<h1><a class="anchor" id="sau_ctrlregister_sec"></a>
SAU CTRL register settings</h1>
<table  class="cmtable">
<tr>
<th>#define </th><th>Value Range </th><th>Default </th><th>Description  </th></tr>
<tr>
<td>SAU_INIT_CTRL </td><td>0 .. 1 </td><td>0 </td><td>Initialize SAU CTRL register or not<ul>
<li>0: do not initialize SAU CTRL register</li>
<li>1: initialize SAU CTRL register  </li>
</ul>
</td></tr>
<tr>
<td>SAU_INIT_CTRL_ENABLE </td><td>0 .. 1 </td><td>0 </td><td>enable/disable the SAU<ul>
<li>0: disable SAU</li>
<li>1: enable SAU  </li>
</ul>
</td></tr>
<tr>
<td>SAU_INIT_CTRL_ALLNS </td><td>0 .. 1 </td><td>0 </td><td>value for SAU_CTRL register bit ALLNS<ul>
<li>0: all Memory is Secure</li>
<li>1: all Memory is Non-Secure  </li>
</ul>
</td></tr>
</table>
<h1><a class="anchor" id="sau_sleepexception_sec"></a>
Configuration of Sleep and Exception behaviour</h1>
<table  class="cmtable">
<tr>
<th>#define </th><th>Value Range </th><th>Default </th><th>Description  </th></tr>
<tr>
<td>SCB_CSR_AIRCR_INIT </td><td>0 .. 1 </td><td>1 </td><td>Setup behaviour of Sleep and Exception Handling<ul>
<li>0: not setup of CSR and AIRCR registers; the values below are not relevant</li>
<li>1: setup of CSR and AIRCR registers with values below  </li>
</ul>
</td></tr>
<tr>
<td>CSR_INIT_DEEPSLEEPS_VAL </td><td>0 .. 1 </td><td>1 </td><td>value for SCB_CSR register bit DEEPSLEEPS<ul>
<li>0: Deep Sleep can be enabled by Secure and Non-Secure state</li>
<li>1: Deep Sleep can be enabled by Secure state only  </li>
</ul>
</td></tr>
<tr>
<td>AIRCR_INIT_SYSRESETREQS_VAL </td><td>0 .. 1 </td><td>1 </td><td>value for SCB_AIRCR register bit SYSRESETREQS<ul>
<li>0: System reset request accessible from Secure and Non-Secure state</li>
<li>1: System reset request accessible from Secure state only  </li>
</ul>
</td></tr>
<tr>
<td>AIRCR_INIT_PRIS_VAL </td><td>0 .. 1 </td><td>1 </td><td>value for SCB_AIRCR register bit PRIS<ul>
<li>0: Priority of Non-Secure exceptions is Not altered</li>
<li>1: Priority of Non-Secure exceptions is Lowered to 0x80-0xFF  </li>
</ul>
</td></tr>
<tr>
<td>AIRCR_INIT_BFHFNMINS_VAL </td><td>0 .. 1 </td><td>0 </td><td>value for SCB_AIRCR register bit BFHFNMINS<ul>
<li>0: BusFault, HardFault, and NMI target are Secure state</li>
<li>1: BusFault, HardFault, and NMI target are Non-Secure state  </li>
</ul>
</td></tr>
</table>
<h1><a class="anchor" id="sau_fpu_sec"></a>
Configuration of Floating Point Unit</h1>
<table  class="cmtable">
<tr>
<th>#define </th><th>Value Range </th><th>Default </th><th>Description  </th></tr>
<tr>
<td>TZ_FPU_NS_USAGE </td><td>0 .. 1 </td><td>1 </td><td>Setup behaviour of Floating Point Unit<ul>
<li>0: not setup of NSACR and FPCCR registers; the values below are not relevant</li>
<li>1: setup of NSACR and FPCCR registers with values below  </li>
</ul>
</td></tr>
<tr>
<td>SCB_NSACR_CP10_11_VAL </td><td>0 or 3 </td><td>3 </td><td>Floating Point Unit usage (Value for SCB-&gt;NSACR register bits CP10, CP11)<ul>
<li>0: Secure state only</li>
<li>3: Secure and Non-Secure state  </li>
</ul>
</td></tr>
<tr>
<td>FPU_FPCCR_TS_VAL </td><td>0 .. 1 </td><td>0 </td><td>Treat floating-point registers as Secure (value for FPU-&gt;FPCCR register bit TS)<ul>
<li>0: Disable</li>
<li>1: Enabled  </li>
</ul>
</td></tr>
<tr>
<td>FPU_FPCCR_CLRONRETS_VAL </td><td>0 .. 1 </td><td>0 </td><td>Clear on return (CLRONRET) accessibility (Value for FPU-&gt;FPCCR register bit CLRONRETS)<ul>
<li>0: Secure and Non-Secure state</li>
<li>1: Secure state only  </li>
</ul>
</td></tr>
<tr>
<td>FPU_FPCCR_CLRONRET_VAL </td><td>0 .. 1 </td><td>1 </td><td>Clear floating-point caller saved registers on exception return (Value for FPU-&gt;FPCCR register bit CLRONRET)<ul>
<li>0: Disabled</li>
<li>1: Enabled  </li>
</ul>
</td></tr>
</table>
<p>&#160; </p>
<hr/>
<h1><a class="anchor" id="partition_gen_h_pg"></a>
Region/ISR setup: partition_gen.h</h1>
<p>The <a class="el" href="partition_h_pg.html#partition_gen_h_pg">partition_gen.h</a> header file can be generated using <a href="../../Zone/html/index.html"><b>CMSIS-Zone</b></a>.</p>
<p>The <a class="el" href="partition_h_pg.html">partition_&lt;device&gt;.h</a> file includes the <a class="el" href="partition_h_pg.html">partition_gen.h</a> file with configuration settings for:</p>
<ul>
<li><a class="el" href="partition_h_pg.html#sau_regions_sect">Configuration of the SAU Address Regions</a> provides configuration of the SAU Address Regions.</li>
<li><a class="el" href="partition_h_pg.html#sau_interrupttarget_sec">Configuration of Interrupt Target settings</a> provides device-specific interrupt target settings.</li>
</ul>
<dl class="section note"><dt>Note</dt><dd>In previous versions of CMSIS-Core(M) the above settings were part of <a class="el" href="partition_h_pg.html">partition_&lt;device&gt;.h</a></dd></dl>
<h2><a class="anchor" id="sau_regions_sect"></a>
Configuration of the SAU Address Regions</h2>
<table  class="cmtable">
<tr>
<th>#define </th><th>Value Range </th><th>Default </th><th>Description  </th></tr>
<tr>
<td>SAU_REGIONS_MAX </td><td>0 .. tbd </td><td>8 </td><td>maximum number of SAU regions  </td></tr>
<tr>
<td>SAU_INIT_REGION&lt;number&gt; </td><td>0 .. 1 </td><td>0 </td><td>initialize SAU region or not<ul>
<li>0: do not initialize SAU region</li>
<li>1: initialize SAU region  </li>
</ul>
</td></tr>
<tr>
<td>SAU_INIT_START&lt;number&gt; </td><td>0x00000000 .. 0xFFFFFFE0<br/>
 [in steps of 32] </td><td>0x00000000 </td><td>region start address  </td></tr>
<tr>
<td>SAU_INIT_END&lt;number&gt; </td><td>0x00000000 .. 0xFFFFFFE0<br/>
 [in steps of 32] </td><td>0x00000000 </td><td>region start address  </td></tr>
<tr>
<td>SAU_INIT_NSC&lt;number&gt; </td><td>0 .. 1 </td><td>0 </td><td>SAU region attribute<ul>
<li>0: Non-Secure</li>
<li>1: Secure, Non-Secure callable  </li>
</ul>
</td></tr>
</table>
<p>The range of &lt;number&gt; is from 0 .. SAU_REGIONS_MAX. A set of these macros must exist for each &lt;number&gt;.</p>
<p>The following example shows a set of SAU region macros.</p>
<div class="fragment"><div class="line"><span class="preprocessor">#define SAU_REGIONS_MAX   8                 </span><span class="comment">/* Max. number of SAU regions */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor">#define SAU_INIT_REGION0    1</span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_START0     0x00000000      </span><span class="comment">/* start address of SAU region 0 */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_END0       0x001FFFE0      </span><span class="comment">/* end address of SAU region 0 */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_NSC0       1</span></div>
<div class="line"><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor">#define SAU_INIT_REGION1    1</span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_START1     0x00200000      </span><span class="comment">/* start address of SAU region 1 */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_END1       0x003FFFE0      </span><span class="comment">/* end address of SAU region 1 */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_NSC1       0</span></div>
<div class="line"><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor">#define SAU_INIT_REGION2    1</span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_START2     0x20200000      </span><span class="comment">/* start address of SAU region 2 */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_END2       0x203FFFE0      </span><span class="comment">/* end address of SAU region 2 */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_NSC2       0</span></div>
<div class="line"><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor">#define SAU_INIT_REGION3    1</span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_START3     0x40000000      </span><span class="comment">/* start address of SAU region 3 */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_END3       0x40040000      </span><span class="comment">/* end address of SAU region 3 */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_NSC3       0</span></div>
<div class="line"><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor">#define SAU_INIT_REGION4    0</span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_START4     0x00000000      </span><span class="comment">/* start address of SAU region 4 */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_END4       0x00000000      </span><span class="comment">/* end address of SAU region 4 */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_NSC4       0</span></div>
<div class="line"><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor">#define SAU_INIT_REGION5    0</span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_START5     0x00000000      </span><span class="comment">/* start address of SAU region 5 */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_END5       0x00000000      </span><span class="comment">/* end address of SAU region 5 */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_NSC5       0</span></div>
<div class="line"><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor">#define SAU_INIT_REGION6    0</span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_START6     0x00000000      </span><span class="comment">/* start address of SAU region 6 */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_END6       0x00000000      </span><span class="comment">/* end address of SAU region 6 */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_NSC6       0</span></div>
<div class="line"><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor">#define SAU_INIT_REGION7    0</span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_START7     0x00000000      </span><span class="comment">/* start address of SAU region 7 */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_END7       0x00000000      </span><span class="comment">/* end address of SAU region 7 */</span><span class="preprocessor"></span></div>
<div class="line"><span class="preprocessor">#define SAU_INIT_NSC7       0</span></div>
</div><!-- fragment --><h2><a class="anchor" id="sau_interrupttarget_sec"></a>
Configuration of Interrupt Target settings</h2>
<p>Each interrupt has a configuration bit that defines the execution in Secure or Non-secure state. The Non-Secure interrupts have a separate vector table. Refer to <a class="el" href="using_TrustZone_pg.html#Model_TrustZone">Programmers Model with TrustZone</a> for more information.</p>
<table  class="cmtable">
<tr>
<th>#define </th><th>Value Range </th><th>Default </th><th>Description  </th></tr>
<tr>
<td>NVIC_INIT_ITNS&lt;number&gt; </td><td>0x00000000 .. 0xFFFFFFFF<br/>
 [each bit represents an interrupt] </td><td>0x00000000 </td><td>Interrupt vector target<ul>
<li>0: Secure state</li>
<li>1: Non-Secure state  </li>
</ul>
</td></tr>
</table>
<p>The range of &lt;number&gt; is 0 .. (&lt;number of external interrupts&gt; + 31) / 32.</p>
<p>The following example shows the configuration for a maximum of 64 external interrupts.</p>
<div class="fragment"><div class="line"><span class="preprocessor">#define NVIC_INIT_ITNS0      0x0000122B</span></div>
<div class="line"><span class="preprocessor">#define NVIC_INIT_ITNS1      0x0000003A</span></div>
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