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  113. <div class="title">NAND Bus Modes<div class="ingroups"><a class="el" href="group__nand__control__gr.html">NAND Control Codes</a></div></div>  </div>
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  116. 

  117. <p>Specify bus mode of the NAND interface.  
    118. 

  118. <a href="#details">More...</a></p>
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  119. <table class="memberdecls">
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  120. <tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
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  121. Macros</h2></td></tr>
    122. 

  122. <tr class="memitem:gac7743aeb6411b97f9fc6a24b556f4963"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gac7743aeb6411b97f9fc6a24b556f4963">ARM_NAND_BUS_SDR</a>&#160;&#160;&#160;(0x00UL &lt;&lt; ARM_NAND_BUS_INTERFACE_Pos)</td></tr>
    123. 

  123. <tr class="memdesc:gac7743aeb6411b97f9fc6a24b556f4963"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Interface: SDR (Single Data Rate) - Traditional interface (default)  <a href="#gac7743aeb6411b97f9fc6a24b556f4963">More...</a><br/></td></tr>
    124. 

  124. <tr class="separator:gac7743aeb6411b97f9fc6a24b556f4963"><td class="memSeparator" colspan="2">&#160;</td></tr>
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  125. <tr class="memitem:ga82b8261b3d0d85881535adada318a7df"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga82b8261b3d0d85881535adada318a7df">ARM_NAND_BUS_DDR</a>&#160;&#160;&#160;(0x01UL &lt;&lt; ARM_NAND_BUS_INTERFACE_Pos)</td></tr>
    126. 

  126. <tr class="memdesc:ga82b8261b3d0d85881535adada318a7df"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Interface: NV-DDR (Double Data Rate)  <a href="#ga82b8261b3d0d85881535adada318a7df">More...</a><br/></td></tr>
    127. 

  127. <tr class="separator:ga82b8261b3d0d85881535adada318a7df"><td class="memSeparator" colspan="2">&#160;</td></tr>
    128. 

  128. <tr class="memitem:ga13c102201d6021db184a2f068656c518"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga13c102201d6021db184a2f068656c518">ARM_NAND_BUS_DDR2</a>&#160;&#160;&#160;(0x02UL &lt;&lt; ARM_NAND_BUS_INTERFACE_Pos)</td></tr>
    129. 

  129. <tr class="memdesc:ga13c102201d6021db184a2f068656c518"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Interface: NV-DDR2 (Double Data Rate)  <a href="#ga13c102201d6021db184a2f068656c518">More...</a><br/></td></tr>
    130. 

  130. <tr class="separator:ga13c102201d6021db184a2f068656c518"><td class="memSeparator" colspan="2">&#160;</td></tr>
    131. 

  131. <tr class="memitem:ga971e574ac412bbba445055e9afc384ba"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga971e574ac412bbba445055e9afc384ba">ARM_NAND_BUS_TIMING_MODE_0</a>&#160;&#160;&#160;(0x00UL &lt;&lt; ARM_NAND_BUS_TIMING_MODE_Pos)</td></tr>
    132. 

  132. <tr class="memdesc:ga971e574ac412bbba445055e9afc384ba"><td class="mdescLeft">&#160;</td><td class="mdescRight">Timing Mode 0 (default)  <a href="#ga971e574ac412bbba445055e9afc384ba">More...</a><br/></td></tr>
    133. 

  133. <tr class="separator:ga971e574ac412bbba445055e9afc384ba"><td class="memSeparator" colspan="2">&#160;</td></tr>
    134. 

  134. <tr class="memitem:ga475a339e929eca46e11bc8a7b330aa45"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga475a339e929eca46e11bc8a7b330aa45">ARM_NAND_BUS_TIMING_MODE_1</a>&#160;&#160;&#160;(0x01UL &lt;&lt; ARM_NAND_BUS_TIMING_MODE_Pos)</td></tr>
    135. 

  135. <tr class="memdesc:ga475a339e929eca46e11bc8a7b330aa45"><td class="mdescLeft">&#160;</td><td class="mdescRight">Timing Mode 1.  <a href="#ga475a339e929eca46e11bc8a7b330aa45">More...</a><br/></td></tr>
    136. 

  136. <tr class="separator:ga475a339e929eca46e11bc8a7b330aa45"><td class="memSeparator" colspan="2">&#160;</td></tr>
    137. 

  137. <tr class="memitem:gaed6154fb03b5516faf0bfd11d7a46309"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gaed6154fb03b5516faf0bfd11d7a46309">ARM_NAND_BUS_TIMING_MODE_2</a>&#160;&#160;&#160;(0x02UL &lt;&lt; ARM_NAND_BUS_TIMING_MODE_Pos)</td></tr>
    138. 

  138. <tr class="memdesc:gaed6154fb03b5516faf0bfd11d7a46309"><td class="mdescLeft">&#160;</td><td class="mdescRight">Timing Mode 2.  <a href="#gaed6154fb03b5516faf0bfd11d7a46309">More...</a><br/></td></tr>
    139. 

  139. <tr class="separator:gaed6154fb03b5516faf0bfd11d7a46309"><td class="memSeparator" colspan="2">&#160;</td></tr>
    140. 

  140. <tr class="memitem:gacbc4e07e1af6ef0e4c656428e81464a9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gacbc4e07e1af6ef0e4c656428e81464a9">ARM_NAND_BUS_TIMING_MODE_3</a>&#160;&#160;&#160;(0x03UL &lt;&lt; ARM_NAND_BUS_TIMING_MODE_Pos)</td></tr>
    141. 

  141. <tr class="memdesc:gacbc4e07e1af6ef0e4c656428e81464a9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Timing Mode 3.  <a href="#gacbc4e07e1af6ef0e4c656428e81464a9">More...</a><br/></td></tr>
    142. 

  142. <tr class="separator:gacbc4e07e1af6ef0e4c656428e81464a9"><td class="memSeparator" colspan="2">&#160;</td></tr>
    143. 

  143. <tr class="memitem:ga709d51a5215cd23ce2d85aec57141456"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga709d51a5215cd23ce2d85aec57141456">ARM_NAND_BUS_TIMING_MODE_4</a>&#160;&#160;&#160;(0x04UL &lt;&lt; ARM_NAND_BUS_TIMING_MODE_Pos)</td></tr>
    144. 

  144. <tr class="memdesc:ga709d51a5215cd23ce2d85aec57141456"><td class="mdescLeft">&#160;</td><td class="mdescRight">Timing Mode 4 (SDR EDO capable)  <a href="#ga709d51a5215cd23ce2d85aec57141456">More...</a><br/></td></tr>
    145. 

  145. <tr class="separator:ga709d51a5215cd23ce2d85aec57141456"><td class="memSeparator" colspan="2">&#160;</td></tr>
    146. 

  146. <tr class="memitem:gaee3cad14ce2b8b9af69149bf74597791"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gaee3cad14ce2b8b9af69149bf74597791">ARM_NAND_BUS_TIMING_MODE_5</a>&#160;&#160;&#160;(0x05UL &lt;&lt; ARM_NAND_BUS_TIMING_MODE_Pos)</td></tr>
    147. 

  147. <tr class="memdesc:gaee3cad14ce2b8b9af69149bf74597791"><td class="mdescLeft">&#160;</td><td class="mdescRight">Timing Mode 5 (SDR EDO capable)  <a href="#gaee3cad14ce2b8b9af69149bf74597791">More...</a><br/></td></tr>
    148. 

  148. <tr class="separator:gaee3cad14ce2b8b9af69149bf74597791"><td class="memSeparator" colspan="2">&#160;</td></tr>
    149. 

  149. <tr class="memitem:ga4a3524e0eba994b3a66e06cde877f0f6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga4a3524e0eba994b3a66e06cde877f0f6">ARM_NAND_BUS_TIMING_MODE_6</a>&#160;&#160;&#160;(0x06UL &lt;&lt; ARM_NAND_BUS_TIMING_MODE_Pos)</td></tr>
    150. 

  150. <tr class="memdesc:ga4a3524e0eba994b3a66e06cde877f0f6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Timing Mode 6 (NV-DDR2 only)  <a href="#ga4a3524e0eba994b3a66e06cde877f0f6">More...</a><br/></td></tr>
    151. 

  151. <tr class="separator:ga4a3524e0eba994b3a66e06cde877f0f6"><td class="memSeparator" colspan="2">&#160;</td></tr>
    152. 

  152. <tr class="memitem:gaa63d75f5f2b48a7345a066d58de1bd23"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gaa63d75f5f2b48a7345a066d58de1bd23">ARM_NAND_BUS_TIMING_MODE_7</a>&#160;&#160;&#160;(0x07UL &lt;&lt; ARM_NAND_BUS_TIMING_MODE_Pos)</td></tr>
    153. 

  153. <tr class="memdesc:gaa63d75f5f2b48a7345a066d58de1bd23"><td class="mdescLeft">&#160;</td><td class="mdescRight">Timing Mode 7 (NV-DDR2 only)  <a href="#gaa63d75f5f2b48a7345a066d58de1bd23">More...</a><br/></td></tr>
    154. 

  154. <tr class="separator:gaa63d75f5f2b48a7345a066d58de1bd23"><td class="memSeparator" colspan="2">&#160;</td></tr>
    155. 

  155. <tr class="memitem:ga77348df5f5c2c96bcaeec60b6da02c1b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga77348df5f5c2c96bcaeec60b6da02c1b">ARM_NAND_BUS_DDR2_DO_WCYC_0</a>&#160;&#160;&#160;(0x00UL &lt;&lt; ARM_NAND_BUS_DDR2_DO_WCYC_Pos)</td></tr>
    156. 

  156. <tr class="memdesc:ga77348df5f5c2c96bcaeec60b6da02c1b"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDR2 Data Output Warm-up cycles: 0 (default)  <a href="#ga77348df5f5c2c96bcaeec60b6da02c1b">More...</a><br/></td></tr>
    157. 

  157. <tr class="separator:ga77348df5f5c2c96bcaeec60b6da02c1b"><td class="memSeparator" colspan="2">&#160;</td></tr>
    158. 

  158. <tr class="memitem:ga5839be0b4b2eb930ec039a3403b5e89e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga5839be0b4b2eb930ec039a3403b5e89e">ARM_NAND_BUS_DDR2_DO_WCYC_1</a>&#160;&#160;&#160;(0x01UL &lt;&lt; ARM_NAND_BUS_DDR2_DO_WCYC_Pos)</td></tr>
    159. 

  159. <tr class="memdesc:ga5839be0b4b2eb930ec039a3403b5e89e"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDR2 Data Output Warm-up cycles: 1.  <a href="#ga5839be0b4b2eb930ec039a3403b5e89e">More...</a><br/></td></tr>
    160. 

  160. <tr class="separator:ga5839be0b4b2eb930ec039a3403b5e89e"><td class="memSeparator" colspan="2">&#160;</td></tr>
    161. 

  161. <tr class="memitem:ga10a1ef3be69bfa7e6cc657bee751a077"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga10a1ef3be69bfa7e6cc657bee751a077">ARM_NAND_BUS_DDR2_DO_WCYC_2</a>&#160;&#160;&#160;(0x02UL &lt;&lt; ARM_NAND_BUS_DDR2_DO_WCYC_Pos)</td></tr>
    162. 

  162. <tr class="memdesc:ga10a1ef3be69bfa7e6cc657bee751a077"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDR2 Data Output Warm-up cycles: 2.  <a href="#ga10a1ef3be69bfa7e6cc657bee751a077">More...</a><br/></td></tr>
    163. 

  163. <tr class="separator:ga10a1ef3be69bfa7e6cc657bee751a077"><td class="memSeparator" colspan="2">&#160;</td></tr>
    164. 

  164. <tr class="memitem:ga7f9e8416c4a4e20c4a04323e39f2100d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga7f9e8416c4a4e20c4a04323e39f2100d">ARM_NAND_BUS_DDR2_DO_WCYC_4</a>&#160;&#160;&#160;(0x03UL &lt;&lt; ARM_NAND_BUS_DDR2_DO_WCYC_Pos)</td></tr>
    165. 

  165. <tr class="memdesc:ga7f9e8416c4a4e20c4a04323e39f2100d"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDR2 Data Output Warm-up cycles: 4.  <a href="#ga7f9e8416c4a4e20c4a04323e39f2100d">More...</a><br/></td></tr>
    166. 

  166. <tr class="separator:ga7f9e8416c4a4e20c4a04323e39f2100d"><td class="memSeparator" colspan="2">&#160;</td></tr>
    167. 

  167. <tr class="memitem:gaeee1853dea5e96cb19d2596cc0e70169"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gaeee1853dea5e96cb19d2596cc0e70169">ARM_NAND_BUS_DDR2_DI_WCYC_0</a>&#160;&#160;&#160;(0x00UL &lt;&lt; ARM_NAND_BUS_DDR2_DI_WCYC_Pos)</td></tr>
    168. 

  168. <tr class="memdesc:gaeee1853dea5e96cb19d2596cc0e70169"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDR2 Data Input Warm-up cycles: 0 (default)  <a href="#gaeee1853dea5e96cb19d2596cc0e70169">More...</a><br/></td></tr>
    169. 

  169. <tr class="separator:gaeee1853dea5e96cb19d2596cc0e70169"><td class="memSeparator" colspan="2">&#160;</td></tr>
    170. 

  170. <tr class="memitem:ga42560a1f046e20cc4956276156c4ce25"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga42560a1f046e20cc4956276156c4ce25">ARM_NAND_BUS_DDR2_DI_WCYC_1</a>&#160;&#160;&#160;(0x01UL &lt;&lt; ARM_NAND_BUS_DDR2_DI_WCYC_Pos)</td></tr>
    171. 

  171. <tr class="memdesc:ga42560a1f046e20cc4956276156c4ce25"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDR2 Data Input Warm-up cycles: 1.  <a href="#ga42560a1f046e20cc4956276156c4ce25">More...</a><br/></td></tr>
    172. 

  172. <tr class="separator:ga42560a1f046e20cc4956276156c4ce25"><td class="memSeparator" colspan="2">&#160;</td></tr>
    173. 

  173. <tr class="memitem:gaad2e7807292d84a5070143626f5c2756"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gaad2e7807292d84a5070143626f5c2756">ARM_NAND_BUS_DDR2_DI_WCYC_2</a>&#160;&#160;&#160;(0x02UL &lt;&lt; ARM_NAND_BUS_DDR2_DI_WCYC_Pos)</td></tr>
    174. 

  174. <tr class="memdesc:gaad2e7807292d84a5070143626f5c2756"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDR2 Data Input Warm-up cycles: 2.  <a href="#gaad2e7807292d84a5070143626f5c2756">More...</a><br/></td></tr>
    175. 

  175. <tr class="separator:gaad2e7807292d84a5070143626f5c2756"><td class="memSeparator" colspan="2">&#160;</td></tr>
    176. 

  176. <tr class="memitem:ga3ebb54a1ae971cd34f3c8fc9ff3ab6d5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga3ebb54a1ae971cd34f3c8fc9ff3ab6d5">ARM_NAND_BUS_DDR2_DI_WCYC_4</a>&#160;&#160;&#160;(0x03UL &lt;&lt; ARM_NAND_BUS_DDR2_DI_WCYC_Pos)</td></tr>
    177. 

  177. <tr class="memdesc:ga3ebb54a1ae971cd34f3c8fc9ff3ab6d5"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDR2 Data Input Warm-up cycles: 4.  <a href="#ga3ebb54a1ae971cd34f3c8fc9ff3ab6d5">More...</a><br/></td></tr>
    178. 

  178. <tr class="separator:ga3ebb54a1ae971cd34f3c8fc9ff3ab6d5"><td class="memSeparator" colspan="2">&#160;</td></tr>
    179. 

  179. <tr class="memitem:ga465ae06a6e097959620346304182e273"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga465ae06a6e097959620346304182e273">ARM_NAND_BUS_DDR2_VEN</a>&#160;&#160;&#160;(1UL &lt;&lt; 16)</td></tr>
    180. 

  180. <tr class="memdesc:ga465ae06a6e097959620346304182e273"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDR2 Enable external VREFQ as reference.  <a href="#ga465ae06a6e097959620346304182e273">More...</a><br/></td></tr>
    181. 

  181. <tr class="separator:ga465ae06a6e097959620346304182e273"><td class="memSeparator" colspan="2">&#160;</td></tr>
    182. 

  182. <tr class="memitem:gad38354e4a34adbf881afc7f89ff06e89"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gad38354e4a34adbf881afc7f89ff06e89">ARM_NAND_BUS_DDR2_CMPD</a>&#160;&#160;&#160;(1UL &lt;&lt; 17)</td></tr>
    183. 

  183. <tr class="memdesc:gad38354e4a34adbf881afc7f89ff06e89"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDR2 Enable complementary DQS (DQS_c) signal.  <a href="#gad38354e4a34adbf881afc7f89ff06e89">More...</a><br/></td></tr>
    184. 

  184. <tr class="separator:gad38354e4a34adbf881afc7f89ff06e89"><td class="memSeparator" colspan="2">&#160;</td></tr>
    185. 

  185. <tr class="memitem:ga8a2d599082b9fe56cee1c6454bb3c6a1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga8a2d599082b9fe56cee1c6454bb3c6a1">ARM_NAND_BUS_DDR2_CMPR</a>&#160;&#160;&#160;(1UL &lt;&lt; 18)</td></tr>
    186. 

  186. <tr class="memdesc:ga8a2d599082b9fe56cee1c6454bb3c6a1"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDR2 Enable complementary RE_n (RE_c) signal.  <a href="#ga8a2d599082b9fe56cee1c6454bb3c6a1">More...</a><br/></td></tr>
    187. 

  187. <tr class="separator:ga8a2d599082b9fe56cee1c6454bb3c6a1"><td class="memSeparator" colspan="2">&#160;</td></tr>
    188. 

  188. </table>
    189. 

  189. <a name="details" id="details"></a><h2 class="groupheader">Description</h2>
    190. 

  190. <p>Specify bus mode of the NAND interface. </p>
    191. 

  191. <p>The defines can be used in the function <a class="el" href="group__nand__interface__gr.html#ga83061d6d53ffb148853efbc87a864607">ARM_NAND_Control</a> for the parameter <em>arg</em> and with the <a class="el" href="group__nand__control__codes.html#ga9b063c3078e86b50d4aa892518b2e2d8">ARM_NAND_BUS_MODE</a> as the <em>control</em> code. </p>
    192. 

  192. <h2 class="groupheader">Macro Definition Documentation</h2>
    193. 

  193. <a class="anchor" id="gac7743aeb6411b97f9fc6a24b556f4963"></a>
    194. 

  194. <div class="memitem">
    195. 

  195. <div class="memproto">
    196. 

  196.       <table class="memname">
    197. 

  197.         <tr>
    198. 

  198.           <td class="memname">#define ARM_NAND_BUS_SDR&#160;&#160;&#160;(0x00UL &lt;&lt; ARM_NAND_BUS_INTERFACE_Pos)</td>
    199. 

  199.         </tr>
    200. 

  200.       </table>
    201. 

  201. </div><div class="memdoc">
    202. 

  202. 

  203. <p>Data Interface: SDR (Single Data Rate) - Traditional interface (default) </p>
    204. 

  204. 

  205. </div>
    206. 

  206. </div>
    207. 

  207. <a class="anchor" id="ga82b8261b3d0d85881535adada318a7df"></a>
    208. 

  208. <div class="memitem">
    209. 

  209. <div class="memproto">
    210. 

  210.       <table class="memname">
    211. 

  211.         <tr>
    212. 

  212.           <td class="memname">#define ARM_NAND_BUS_DDR&#160;&#160;&#160;(0x01UL &lt;&lt; ARM_NAND_BUS_INTERFACE_Pos)</td>
    213. 

  213.         </tr>
    214. 

  214.       </table>
    215. 

  215. </div><div class="memdoc">
    216. 

  216. 

  217. <p>Data Interface: NV-DDR (Double Data Rate) </p>
    218. 

  218. 

  219. </div>
    220. 

  220. </div>
    221. 

  221. <a class="anchor" id="ga13c102201d6021db184a2f068656c518"></a>
    222. 

  222. <div class="memitem">
    223. 

  223. <div class="memproto">
    224. 

  224.       <table class="memname">
    225. 

  225.         <tr>
    226. 

  226.           <td class="memname">#define ARM_NAND_BUS_DDR2&#160;&#160;&#160;(0x02UL &lt;&lt; ARM_NAND_BUS_INTERFACE_Pos)</td>
    227. 

  227.         </tr>
    228. 

  228.       </table>
    229. 

  229. </div><div class="memdoc">
    230. 

  230. 

  231. <p>Data Interface: NV-DDR2 (Double Data Rate) </p>
    232. 

  232. 

  233. </div>
    234. 

  234. </div>
    235. 

  235. <a class="anchor" id="ga971e574ac412bbba445055e9afc384ba"></a>
    236. 

  236. <div class="memitem">
    237. 

  237. <div class="memproto">
    238. 

  238.       <table class="memname">
    239. 

  239.         <tr>
    240. 

  240.           <td class="memname">#define ARM_NAND_BUS_TIMING_MODE_0&#160;&#160;&#160;(0x00UL &lt;&lt; ARM_NAND_BUS_TIMING_MODE_Pos)</td>
    241. 

  241.         </tr>
    242. 

  242.       </table>
    243. 

  243. </div><div class="memdoc">
    244. 

  244. 

  245. <p>Timing Mode 0 (default) </p>
    246. 

  246. 

  247. </div>
    248. 

  248. </div>
    249. 

  249. <a class="anchor" id="ga475a339e929eca46e11bc8a7b330aa45"></a>
    250. 

  250. <div class="memitem">
    251. 

  251. <div class="memproto">
    252. 

  252.       <table class="memname">
    253. 

  253.         <tr>
    254. 

  254.           <td class="memname">#define ARM_NAND_BUS_TIMING_MODE_1&#160;&#160;&#160;(0x01UL &lt;&lt; ARM_NAND_BUS_TIMING_MODE_Pos)</td>
    255. 

  255.         </tr>
    256. 

  256.       </table>
    257. 

  257. </div><div class="memdoc">
    258. 

  258. 

  259. <p>Timing Mode 1. </p>
    260. 

  260. 

  261. </div>
    262. 

  262. </div>
    263. 

  263. <a class="anchor" id="gaed6154fb03b5516faf0bfd11d7a46309"></a>
    264. 

  264. <div class="memitem">
    265. 

  265. <div class="memproto">
    266. 

  266.       <table class="memname">
    267. 

  267.         <tr>
    268. 

  268.           <td class="memname">#define ARM_NAND_BUS_TIMING_MODE_2&#160;&#160;&#160;(0x02UL &lt;&lt; ARM_NAND_BUS_TIMING_MODE_Pos)</td>
    269. 

  269.         </tr>
    270. 

  270.       </table>
    271. 

  271. </div><div class="memdoc">
    272. 

  272. 

  273. <p>Timing Mode 2. </p>
    274. 

  274. 

  275. </div>
    276. 

  276. </div>
    277. 

  277. <a class="anchor" id="gacbc4e07e1af6ef0e4c656428e81464a9"></a>
    278. 

  278. <div class="memitem">
    279. 

  279. <div class="memproto">
    280. 

  280.       <table class="memname">
    281. 

  281.         <tr>
    282. 

  282.           <td class="memname">#define ARM_NAND_BUS_TIMING_MODE_3&#160;&#160;&#160;(0x03UL &lt;&lt; ARM_NAND_BUS_TIMING_MODE_Pos)</td>
    283. 

  283.         </tr>
    284. 

  284.       </table>
    285. 

  285. </div><div class="memdoc">
    286. 

  286. 

  287. <p>Timing Mode 3. </p>
    288. 

  288. 

  289. </div>
    290. 

  290. </div>
    291. 

  291. <a class="anchor" id="ga709d51a5215cd23ce2d85aec57141456"></a>
    292. 

  292. <div class="memitem">
    293. 

  293. <div class="memproto">
    294. 

  294.       <table class="memname">
    295. 

  295.         <tr>
    296. 

  296.           <td class="memname">#define ARM_NAND_BUS_TIMING_MODE_4&#160;&#160;&#160;(0x04UL &lt;&lt; ARM_NAND_BUS_TIMING_MODE_Pos)</td>
    297. 

  297.         </tr>
    298. 

  298.       </table>
    299. 

  299. </div><div class="memdoc">
    300. 

  300. 

  301. <p>Timing Mode 4 (SDR EDO capable) </p>
    302. 

  302. 

  303. </div>
    304. 

  304. </div>
    305. 

  305. <a class="anchor" id="gaee3cad14ce2b8b9af69149bf74597791"></a>
    306. 

  306. <div class="memitem">
    307. 

  307. <div class="memproto">
    308. 

  308.       <table class="memname">
    309. 

  309.         <tr>
    310. 

  310.           <td class="memname">#define ARM_NAND_BUS_TIMING_MODE_5&#160;&#160;&#160;(0x05UL &lt;&lt; ARM_NAND_BUS_TIMING_MODE_Pos)</td>
    311. 

  311.         </tr>
    312. 

  312.       </table>
    313. 

  313. </div><div class="memdoc">
    314. 

  314. 

  315. <p>Timing Mode 5 (SDR EDO capable) </p>
    316. 

  316. 

  317. </div>
    318. 

  318. </div>
    319. 

  319. <a class="anchor" id="ga4a3524e0eba994b3a66e06cde877f0f6"></a>
    320. 

  320. <div class="memitem">
    321. 

  321. <div class="memproto">
    322. 

  322.       <table class="memname">
    323. 

  323.         <tr>
    324. 

  324.           <td class="memname">#define ARM_NAND_BUS_TIMING_MODE_6&#160;&#160;&#160;(0x06UL &lt;&lt; ARM_NAND_BUS_TIMING_MODE_Pos)</td>
    325. 

  325.         </tr>
    326. 

  326.       </table>
    327. 

  327. </div><div class="memdoc">
    328. 

  328. 

  329. <p>Timing Mode 6 (NV-DDR2 only) </p>
    330. 

  330. 

  331. </div>
    332. 

  332. </div>
    333. 

  333. <a class="anchor" id="gaa63d75f5f2b48a7345a066d58de1bd23"></a>
    334. 

  334. <div class="memitem">
    335. 

  335. <div class="memproto">
    336. 

  336.       <table class="memname">
    337. 

  337.         <tr>
    338. 

  338.           <td class="memname">#define ARM_NAND_BUS_TIMING_MODE_7&#160;&#160;&#160;(0x07UL &lt;&lt; ARM_NAND_BUS_TIMING_MODE_Pos)</td>
    339. 

  339.         </tr>
    340. 

  340.       </table>
    341. 

  341. </div><div class="memdoc">
    342. 

  342. 

  343. <p>Timing Mode 7 (NV-DDR2 only) </p>
    344. 

  344. 

  345. </div>
    346. 

  346. </div>
    347. 

  347. <a class="anchor" id="ga77348df5f5c2c96bcaeec60b6da02c1b"></a>
    348. 

  348. <div class="memitem">
    349. 

  349. <div class="memproto">
    350. 

  350.       <table class="memname">
    351. 

  351.         <tr>
    352. 

  352.           <td class="memname">#define ARM_NAND_BUS_DDR2_DO_WCYC_0&#160;&#160;&#160;(0x00UL &lt;&lt; ARM_NAND_BUS_DDR2_DO_WCYC_Pos)</td>
    353. 

  353.         </tr>
    354. 

  354.       </table>
    355. 

  355. </div><div class="memdoc">
    356. 

  356. 

  357. <p>DDR2 Data Output Warm-up cycles: 0 (default) </p>
    358. 

  358. 

  359. </div>
    360. 

  360. </div>
    361. 

  361. <a class="anchor" id="ga5839be0b4b2eb930ec039a3403b5e89e"></a>
    362. 

  362. <div class="memitem">
    363. 

  363. <div class="memproto">
    364. 

  364.       <table class="memname">
    365. 

  365.         <tr>
    366. 

  366.           <td class="memname">#define ARM_NAND_BUS_DDR2_DO_WCYC_1&#160;&#160;&#160;(0x01UL &lt;&lt; ARM_NAND_BUS_DDR2_DO_WCYC_Pos)</td>
    367. 

  367.         </tr>
    368. 

  368.       </table>
    369. 

  369. </div><div class="memdoc">
    370. 

  370. 

  371. <p>DDR2 Data Output Warm-up cycles: 1. </p>
    372. 

  372. 

  373. </div>
    374. 

  374. </div>
    375. 

  375. <a class="anchor" id="ga10a1ef3be69bfa7e6cc657bee751a077"></a>
    376. 

  376. <div class="memitem">
    377. 

  377. <div class="memproto">
    378. 

  378.       <table class="memname">
    379. 

  379.         <tr>
    380. 

  380.           <td class="memname">#define ARM_NAND_BUS_DDR2_DO_WCYC_2&#160;&#160;&#160;(0x02UL &lt;&lt; ARM_NAND_BUS_DDR2_DO_WCYC_Pos)</td>
    381. 

  381.         </tr>
    382. 

  382.       </table>
    383. 

  383. </div><div class="memdoc">
    384. 

  384. 

  385. <p>DDR2 Data Output Warm-up cycles: 2. </p>
    386. 

  386. 

  387. </div>
    388. 

  388. </div>
    389. 

  389. <a class="anchor" id="ga7f9e8416c4a4e20c4a04323e39f2100d"></a>
    390. 

  390. <div class="memitem">
    391. 

  391. <div class="memproto">
    392. 

  392.       <table class="memname">
    393. 

  393.         <tr>
    394. 

  394.           <td class="memname">#define ARM_NAND_BUS_DDR2_DO_WCYC_4&#160;&#160;&#160;(0x03UL &lt;&lt; ARM_NAND_BUS_DDR2_DO_WCYC_Pos)</td>
    395. 

  395.         </tr>
    396. 

  396.       </table>
    397. 

  397. </div><div class="memdoc">
    398. 

  398. 

  399. <p>DDR2 Data Output Warm-up cycles: 4. </p>
    400. 

  400. 

  401. </div>
    402. 

  402. </div>
    403. 

  403. <a class="anchor" id="gaeee1853dea5e96cb19d2596cc0e70169"></a>
    404. 

  404. <div class="memitem">
    405. 

  405. <div class="memproto">
    406. 

  406.       <table class="memname">
    407. 

  407.         <tr>
    408. 

  408.           <td class="memname">#define ARM_NAND_BUS_DDR2_DI_WCYC_0&#160;&#160;&#160;(0x00UL &lt;&lt; ARM_NAND_BUS_DDR2_DI_WCYC_Pos)</td>
    409. 

  409.         </tr>
    410. 

  410.       </table>
    411. 

  411. </div><div class="memdoc">
    412. 

  412. 

  413. <p>DDR2 Data Input Warm-up cycles: 0 (default) </p>
    414. 

  414. 

  415. </div>
    416. 

  416. </div>
    417. 

  417. <a class="anchor" id="ga42560a1f046e20cc4956276156c4ce25"></a>
    418. 

  418. <div class="memitem">
    419. 

  419. <div class="memproto">
    420. 

  420.       <table class="memname">
    421. 

  421.         <tr>
    422. 

  422.           <td class="memname">#define ARM_NAND_BUS_DDR2_DI_WCYC_1&#160;&#160;&#160;(0x01UL &lt;&lt; ARM_NAND_BUS_DDR2_DI_WCYC_Pos)</td>
    423. 

  423.         </tr>
    424. 

  424.       </table>
    425. 

  425. </div><div class="memdoc">
    426. 

  426. 

  427. <p>DDR2 Data Input Warm-up cycles: 1. </p>
    428. 

  428. 

  429. </div>
    430. 

  430. </div>
    431. 

  431. <a class="anchor" id="gaad2e7807292d84a5070143626f5c2756"></a>
    432. 

  432. <div class="memitem">
    433. 

  433. <div class="memproto">
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  435.         <tr>
    436. 

  436.           <td class="memname">#define ARM_NAND_BUS_DDR2_DI_WCYC_2&#160;&#160;&#160;(0x02UL &lt;&lt; ARM_NAND_BUS_DDR2_DI_WCYC_Pos)</td>
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  438.       </table>
    439. 

  439. </div><div class="memdoc">
    440. 

  440. 

  441. <p>DDR2 Data Input Warm-up cycles: 2. </p>
    442. 

  442. 

  443. </div>
    444. 

  444. </div>
    445. 

  445. <a class="anchor" id="ga3ebb54a1ae971cd34f3c8fc9ff3ab6d5"></a>
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  447. <div class="memproto">
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  448.       <table class="memname">
    449. 

  449.         <tr>
    450. 

  450.           <td class="memname">#define ARM_NAND_BUS_DDR2_DI_WCYC_4&#160;&#160;&#160;(0x03UL &lt;&lt; ARM_NAND_BUS_DDR2_DI_WCYC_Pos)</td>
    451. 

  451.         </tr>
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  452.       </table>
    453. 

  453. </div><div class="memdoc">
    454. 

  454. 

  455. <p>DDR2 Data Input Warm-up cycles: 4. </p>
    456. 

  456. 

  457. </div>
    458. 

  458. </div>
    459. 

  459. <a class="anchor" id="ga465ae06a6e097959620346304182e273"></a>
    460. 

  460. <div class="memitem">
    461. 

  461. <div class="memproto">
    462. 

  462.       <table class="memname">
    463. 

  463.         <tr>
    464. 

  464.           <td class="memname">#define ARM_NAND_BUS_DDR2_VEN&#160;&#160;&#160;(1UL &lt;&lt; 16)</td>
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  465.         </tr>
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  466.       </table>
    467. 

  467. </div><div class="memdoc">
    468. 

  468. 

  469. <p>DDR2 Enable external VREFQ as reference. </p>
    470. 

  470. 

  471. </div>
    472. 

  472. </div>
    473. 

  473. <a class="anchor" id="gad38354e4a34adbf881afc7f89ff06e89"></a>
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  474. <div class="memitem">
    475. 

  475. <div class="memproto">
    476. 

  476.       <table class="memname">
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  477.         <tr>
    478. 

  478.           <td class="memname">#define ARM_NAND_BUS_DDR2_CMPD&#160;&#160;&#160;(1UL &lt;&lt; 17)</td>
    479. 

  479.         </tr>
    480. 

  480.       </table>
    481. 

  481. </div><div class="memdoc">
    482. 

  482. 

  483. <p>DDR2 Enable complementary DQS (DQS_c) signal. </p>
    484. 

  484. 

  485. </div>
    486. 

  486. </div>
    487. 

  487. <a class="anchor" id="ga8a2d599082b9fe56cee1c6454bb3c6a1"></a>
    488. 

  488. <div class="memitem">
    489. 

  489. <div class="memproto">
    490. 

  490.       <table class="memname">
    491. 

  491.         <tr>
    492. 

  492.           <td class="memname">#define ARM_NAND_BUS_DDR2_CMPR&#160;&#160;&#160;(1UL &lt;&lt; 18)</td>
    493. 

  493.         </tr>
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  494.       </table>
    495. 

  495. </div><div class="memdoc">
    496. 

  496. 

  497. <p>DDR2 Enable complementary RE_n (RE_c) signal. </p>
    498. 

  498. 

  499. </div>
    500. 

  500. </div>
    501. 

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  506.     <li class="footer">Generated on Thu Apr 9 2020 15:49:15 for CMSIS-Driver Version 2.8.0 by Arm Ltd. All rights reserved.
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