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  35. &#160;<span id="projectnumber">Version 1.3.0</span>
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  37. <div id="projectbrief">CMSIS NN Software Library</div>
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  109. <div class="title">CMSIS NN Software Library </div> </div>
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  111. <div class="contents">
  112. <div class="textblock"><h2>Introduction </h2>
  113. <p>This user manual describes the CMSIS NN software library, a collection of efficient neural network kernels developed to maximize the performance and minimize the memory footprint of neural networks on Cortex-M processor cores.</p>
  114. <p>The library is divided into a number of functions each covering a specific category:</p>
  115. <ul>
  116. <li>Convolution Functions</li>
  117. <li>Activation Functions</li>
  118. <li>Fully-connected Layer Functions</li>
  119. <li>Pooling Functions</li>
  120. <li>Softmax Functions</li>
  121. <li>Basic math Functions</li>
  122. </ul>
  123. <p>The library has separate functions for operating on different weight and activation data types including 8-bit integers (q7_t) and 16-bit integers (q15_t). The descrition of the kernels are included in the function description. The implementation details are also described in this paper [1].</p>
  124. <h2>Function Classification </h2>
  125. <p>The functions can be classified into two segments</p>
  126. <ul>
  127. <li>Legacy functions supporting ARM's internal symmetric quantization(8 bits).</li>
  128. <li>Functions that support TensorFlow Lite framework with symmetric quantization(8 bits).</li>
  129. </ul>
  130. <p>The legacy functions can be identified with their suffix of _q7 or _q15 and are no new development is done there. The article in [2] describes in detail how to run a network using the legacy functions.</p>
  131. <p>The functions supporting TensorFlow Lite framework is identified by the _s8 suffix and can be invoked from TFL micro. The functions are bit exact to TensorFlow Lite. Refer to the TensorFlow's documentation in [3] on how to run a TensorFlow Lite model using optimized CMSIS-NN kernels.</p>
  132. <h2>Block Diagram </h2>
  133. <div class="image">
  134. <img src="CMSIS-NN-OVERVIEW.PNG" alt="CMSIS-NN-OVERVIEW.PNG"/>
  135. </div>
  136. <h2>Examples </h2>
  137. <p>The library ships with a number of examples which demonstrate how to use the library functions.</p>
  138. <h2>Pre-processor Macros </h2>
  139. <p>Each library project have different pre-processor macros.</p>
  140. <ul>
  141. <li>ARM_MATH_DSP:</li>
  142. </ul>
  143. <p>Define macro ARM_MATH_DSP, If the silicon supports DSP instructions(DSP extension).</p>
  144. <ul>
  145. <li>ARM_MATH_MVEI:</li>
  146. </ul>
  147. <p>Define macro ARM_MATH_MVEI, If the silicon supports M-Profile Vector Extension.</p>
  148. <ul>
  149. <li>ARM_MATH_AUTOVECTORIZE Used in conjucture with ARM_MATH_MVEI to let the compiler auto vectorize for the functions that uses inline assembly. It does not affect functions that use C or intrinsics.</li>
  150. <li>ARM_MATH_BIG_ENDIAN:</li>
  151. </ul>
  152. <p>Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. This is supported only for the legacy functions i.e, functions targetted at TensorFlow Lite do not support big endianness. By default library builds for little endian targets.</p>
  153. <ul>
  154. <li>ARM_NN_TRUNCATE:</li>
  155. </ul>
  156. <p>Define macro ARM_NN_TRUNCATE to use floor instead of round-to-the-nearest-int for the computation.</p>
  157. <h2>Upcoming Interface Change </h2>
  158. <p>Starting from the 1.4.0 next release, CMSIS-NN will gradually switch to a new API interface to:</p>
  159. <ol type="1">
  160. <li>have a stable API</li>
  161. <li>avoid passing many variables by value</li>
  162. <li>improve security</li>
  163. <li>improve validation</li>
  164. <li>improve code readability</li>
  165. </ol>
  166. <p>The upcoming API interface change will be based on "struct" and only affect the TensorFlowLite micro compliant APIs [4] (functions with _s8 suffix)</p>
  167. <p>Below you can find a snapshot of how the new API interface will look like (names can change)</p>
  168. <p>i.e. arm_convolve_1x1_s8_fast</p>
  169. <table class="doxtable">
  170. <tr>
  171. <th>Current API interface </th><th>New API interface proposal </th></tr>
  172. <tr>
  173. <td>const q7_t *input </td><td>const cmsis_nn_context &amp;ctx </td></tr>
  174. <tr>
  175. <td>const uint16_t input_x </td><td>const cmsis_nn_conv_params &amp;params </td></tr>
  176. <tr>
  177. <td>const uint16_t input_y </td><td>const cmsis_nn_dims &amp;input_dims </td></tr>
  178. <tr>
  179. <td>const uint16_t input_ch </td><td>const q7_t *input_data </td></tr>
  180. <tr>
  181. <td>const uint16_t input_batches </td><td>const cmsis_nn_dims &amp;filter_dims </td></tr>
  182. <tr>
  183. <td>const q7_t *kernel </td><td>const q7_t *filter_data </td></tr>
  184. <tr>
  185. <td>const uint16_t output_ch </td><td>const cmsis_nn_dims &amp;bias_dims </td></tr>
  186. <tr>
  187. <td>const uint16_t pad_x </td><td>const q31_t *bias_data </td></tr>
  188. <tr>
  189. <td>const uint16_t pad_y </td><td>const cmsis_nn_dims &amp;output_dims </td></tr>
  190. <tr>
  191. <td>const uint16_t stride_x </td><td>q7_t *output_data </td></tr>
  192. <tr>
  193. <td>const uint16_t stride_y </td><td><br/>
  194. </td></tr>
  195. <tr>
  196. <td>const int32_t *bias </td><td><br/>
  197. </td></tr>
  198. <tr>
  199. <td>q7_t *output </td><td><br/>
  200. </td></tr>
  201. <tr>
  202. <td>const int32_t *output_shift </td><td><br/>
  203. </td></tr>
  204. <tr>
  205. <td>const int32_t *output_mult </td><td><br/>
  206. </td></tr>
  207. <tr>
  208. <td>const int32_t out_offset </td><td><br/>
  209. </td></tr>
  210. <tr>
  211. <td>const int32_t input_offset </td><td><br/>
  212. </td></tr>
  213. <tr>
  214. <td>const int32_t out_activation_min </td><td><br/>
  215. </td></tr>
  216. <tr>
  217. <td>const int32_t out_activation_max </td><td><br/>
  218. </td></tr>
  219. <tr>
  220. <td>const uint16_t output_x </td><td><br/>
  221. </td></tr>
  222. <tr>
  223. <td>const uint16_t output_y </td><td><br/>
  224. </td></tr>
  225. <tr>
  226. <td>q15_t *buffer_a </td><td><br/>
  227. </td></tr>
  228. </table>
  229. <h2>Copyright Notice </h2>
  230. <p>Copyright (C) 2010-2019 Arm Limited. All rights reserved.</p>
  231. <p>[1] CMSIS-NN: Efficient Neural Network Kernels for Arm Cortex-M CPUs <a href="https://arxiv.org/abs/1801.06601">https://arxiv.org/abs/1801.06601</a></p>
  232. <p>[2] Converting a Neural Network for Arm Cortex-M with CMSIS-NN <a href="https://developer.arm.com/solutions/machine-learning-on-arm/developer-material/how-to-guides/converting-a-neural-network-for-arm-cortex-m-with-cmsis-nn/single-page">https://developer.arm.com/solutions/machine-learning-on-arm/developer-material/how-to-guides/converting-a-neural-network-for-arm-cortex-m-with-cmsis-nn/single-page</a> [3] <a href="https://www.tensorflow.org/lite/microcontrollers/library">https://www.tensorflow.org/lite/microcontrollers/library</a></p>
  233. <p>[4] <a href="https://github.com/ARM-software/CMSIS_5/tree/develop/CMSIS/NN#legacy-vs-tfl-micro-compliant-apis">https://github.com/ARM-software/CMSIS_5/tree/develop/CMSIS/NN#legacy-vs-tfl-micro-compliant-apis</a> </p>
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