CV_MPU_ARMv8.c 3.7 KB

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  1. /*-----------------------------------------------------------------------------
  2. * Name: CV_MPU_ARMv7.c
  3. * Purpose: CMSIS CORE validation tests implementation
  4. *-----------------------------------------------------------------------------
  5. * Copyright (c) 2017 ARM Limited. All rights reserved.
  6. *----------------------------------------------------------------------------*/
  7. #include "CV_Framework.h"
  8. #include "cmsis_cv.h"
  9. /*-----------------------------------------------------------------------------
  10. * Test implementation
  11. *----------------------------------------------------------------------------*/
  12. #if defined(__MPU_PRESENT) && __MPU_PRESENT
  13. static void ClearMpu(void) {
  14. for(uint32_t i = 0U; i < 8U; ++i) {
  15. MPU->RNR = i;
  16. MPU->RBAR = 0U;
  17. MPU->RLAR = 0U;
  18. }
  19. }
  20. #endif
  21. /*-----------------------------------------------------------------------------
  22. * Test cases
  23. *----------------------------------------------------------------------------*/
  24. /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
  25. /**
  26. \brief Test case: TC_MPU_SetClear
  27. \details
  28. - Check if ARM_MPU_Load correctly loads MPU table to registers.
  29. */
  30. void TC_MPU_SetClear(void)
  31. {
  32. #if defined(__MPU_PRESENT) && __MPU_PRESENT
  33. static const ARM_MPU_Region_t table[] = {
  34. { .RBAR = 0U, .RLAR = 0U },
  35. { .RBAR = ARM_MPU_RBAR(0x30000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x38000000U, 0U) }
  36. };
  37. #define ASSERT_MPU_REGION(rnr, region) \
  38. MPU->RNR = rnr; \
  39. ASSERT_TRUE(MPU->RBAR == region.RBAR); \
  40. ASSERT_TRUE(MPU->RLAR == region.RLAR)
  41. ClearMpu();
  42. ARM_MPU_SetRegion(2U, table[1].RBAR, table[1].RLAR);
  43. ASSERT_MPU_REGION(1U, table[0]);
  44. ASSERT_MPU_REGION(2U, table[1]);
  45. ASSERT_MPU_REGION(3U, table[0]);
  46. ARM_MPU_ClrRegion(2U);
  47. MPU->RNR = 2U;
  48. ASSERT_TRUE((MPU->RLAR & MPU_RLAR_EN_Msk) == 0U);
  49. #undef ASSERT_MPU_REGION
  50. #endif
  51. }
  52. /*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
  53. /**
  54. \brief Test case: TC_MPU_Load
  55. \details
  56. - Check if ARM_MPU_Load correctly loads MPU table to registers.
  57. */
  58. void TC_MPU_Load(void)
  59. {
  60. #if defined(__MPU_PRESENT) && __MPU_PRESENT
  61. static const ARM_MPU_Region_t table[] = {
  62. { .RBAR = ARM_MPU_RBAR(0x10000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x18000000U, 0U) },
  63. { .RBAR = ARM_MPU_RBAR(0x20000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x27000000U, 0U) },
  64. { .RBAR = ARM_MPU_RBAR(0x30000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x36000000U, 0U) },
  65. { .RBAR = ARM_MPU_RBAR(0x40000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x45000000U, 0U) },
  66. { .RBAR = ARM_MPU_RBAR(0x50000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x54000000U, 0U) },
  67. { .RBAR = ARM_MPU_RBAR(0x60000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x63000000U, 0U) },
  68. { .RBAR = ARM_MPU_RBAR(0x70000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x72000000U, 0U) },
  69. { .RBAR = ARM_MPU_RBAR(0x80000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x31000000U, 0U) }
  70. };
  71. #define ASSERT_MPU_REGION(rnr, table) \
  72. MPU->RNR = rnr; \
  73. ASSERT_TRUE(MPU->RBAR == table[rnr].RBAR); \
  74. ASSERT_TRUE(MPU->RLAR == table[rnr].RLAR)
  75. ClearMpu();
  76. ARM_MPU_Load(0U, &(table[0]), 1U);
  77. ASSERT_MPU_REGION(0U, table);
  78. ARM_MPU_Load(1U, &(table[1]), 5U);
  79. ASSERT_MPU_REGION(0U, table);
  80. ASSERT_MPU_REGION(1U, table);
  81. ASSERT_MPU_REGION(2U, table);
  82. ASSERT_MPU_REGION(3U, table);
  83. ASSERT_MPU_REGION(4U, table);
  84. ASSERT_MPU_REGION(5U, table);
  85. ARM_MPU_Load(6U, &(table[6]), 2U);
  86. ASSERT_MPU_REGION(5U, table);
  87. ASSERT_MPU_REGION(6U, table);
  88. ASSERT_MPU_REGION(7U, table);
  89. #undef ASSERT_MPU_REGION
  90. #endif
  91. }