HAL_CM0.c 8.6 KB

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  1. /*----------------------------------------------------------------------------
  2. * CMSIS-RTOS - RTX
  3. *----------------------------------------------------------------------------
  4. * Name: HAL_CM0.C
  5. * Purpose: Hardware Abstraction Layer for Cortex-M0
  6. * Rev.: V4.70
  7. *----------------------------------------------------------------------------
  8. *
  9. * Copyright (c) 1999-2009 KEIL, 2009-2017 ARM Germany GmbH. All rights reserved.
  10. *
  11. * SPDX-License-Identifier: Apache-2.0
  12. *
  13. * Licensed under the Apache License, Version 2.0 (the License); you may
  14. * not use this file except in compliance with the License.
  15. * You may obtain a copy of the License at
  16. *
  17. * www.apache.org/licenses/LICENSE-2.0
  18. *
  19. * Unless required by applicable law or agreed to in writing, software
  20. * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  21. * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  22. * See the License for the specific language governing permissions and
  23. * limitations under the License.
  24. *---------------------------------------------------------------------------*/
  25. #include "rt_TypeDef.h"
  26. #include "RTX_Config.h"
  27. #include "rt_System.h"
  28. #include "rt_HAL_CM.h"
  29. #include "rt_Task.h"
  30. #include "rt_MemBox.h"
  31. /*----------------------------------------------------------------------------
  32. * Functions
  33. *---------------------------------------------------------------------------*/
  34. /*--------------------------- rt_set_PSP ------------------------------------*/
  35. __asm void rt_set_PSP (U32 stack) {
  36. MSR PSP,R0
  37. BX LR
  38. }
  39. /*--------------------------- rt_get_PSP ------------------------------------*/
  40. __asm U32 rt_get_PSP (void) {
  41. MRS R0,PSP
  42. BX LR
  43. }
  44. /*--------------------------- os_set_env ------------------------------------*/
  45. __asm void os_set_env (void) {
  46. /* Switch to Unprivileged/Privileged Thread mode, use PSP. */
  47. MOV R0,SP ; PSP = MSP
  48. MSR PSP,R0
  49. LDR R0,=__cpp(&os_flags)
  50. LDRB R0,[R0]
  51. LSLS R0,#31
  52. BNE PrivilegedE
  53. MOVS R0,#0x03 ; Unprivileged Thread mode, use PSP
  54. MSR CONTROL,R0
  55. BX LR
  56. PrivilegedE
  57. MOVS R0,#0x02 ; Privileged Thread mode, use PSP
  58. MSR CONTROL,R0
  59. BX LR
  60. ALIGN
  61. }
  62. /*--------------------------- _alloc_box ------------------------------------*/
  63. __asm void *_alloc_box (void *box_mem) {
  64. /* Function wrapper for Unprivileged/Privileged mode. */
  65. LDR R3,=__cpp(rt_alloc_box)
  66. MOV R12,R3
  67. MRS R3,IPSR
  68. LSLS R3,#24
  69. BNE PrivilegedA
  70. MRS R3,CONTROL
  71. LSLS R3,#31
  72. BEQ PrivilegedA
  73. SVC 0
  74. BX LR
  75. PrivilegedA
  76. BX R12
  77. ALIGN
  78. }
  79. /*--------------------------- _free_box -------------------------------------*/
  80. __asm U32 _free_box (void *box_mem, void *box) {
  81. /* Function wrapper for Unprivileged/Privileged mode. */
  82. LDR R3,=__cpp(rt_free_box)
  83. MOV R12,R3
  84. MRS R3,IPSR
  85. LSLS R3,#24
  86. BNE PrivilegedF
  87. MRS R3,CONTROL
  88. LSLS R3,#31
  89. BEQ PrivilegedF
  90. SVC 0
  91. BX LR
  92. PrivilegedF
  93. BX R12
  94. ALIGN
  95. }
  96. /*-------------------------- SVC_Handler ------------------------------------*/
  97. __asm void SVC_Handler (void) {
  98. PRESERVE8
  99. IMPORT SVC_Count
  100. IMPORT SVC_Table
  101. IMPORT rt_stk_check
  102. MRS R0,PSP ; Read PSP
  103. LDR R1,[R0,#24] ; Read Saved PC from Stack
  104. SUBS R1,R1,#2 ; Point to SVC Instruction
  105. LDRB R1,[R1] ; Load SVC Number
  106. CMP R1,#0
  107. BNE SVC_User ; User SVC Number > 0
  108. MOV LR,R4
  109. LDMIA R0,{R0-R3,R4} ; Read R0-R3,R12 from stack
  110. MOV R12,R4
  111. MOV R4,LR
  112. BLX R12 ; Call SVC Function
  113. MRS R3,PSP ; Read PSP
  114. STMIA R3!,{R0-R2} ; Store return values
  115. LDR R3,=__cpp(&os_tsk)
  116. LDMIA R3!,{R1,R2} ; os_tsk.run, os_tsk.next
  117. CMP R1,R2
  118. BEQ SVC_Exit ; no task switch
  119. SUBS R3,#8
  120. CMP R1,#0 ; Runtask deleted?
  121. BEQ SVC_Next
  122. MRS R0,PSP ; Read PSP
  123. SUBS R0,R0,#32 ; Adjust Start Address
  124. STR R0,[R1,#TCB_TSTACK] ; Update os_tsk.run->tsk_stack
  125. STMIA R0!,{R4-R7} ; Save old context (R4-R7)
  126. MOV R4,R8
  127. MOV R5,R9
  128. MOV R6,R10
  129. MOV R7,R11
  130. STMIA R0!,{R4-R7} ; Save old context (R8-R11)
  131. PUSH {R2,R3}
  132. BL rt_stk_check ; Check for Stack overflow
  133. POP {R2,R3}
  134. SVC_Next
  135. STR R2,[R3] ; os_tsk.run = os_tsk.next
  136. LDR R0,[R2,#TCB_TSTACK] ; os_tsk.next->tsk_stack
  137. ADDS R0,R0,#16 ; Adjust Start Address
  138. LDMIA R0!,{R4-R7} ; Restore new Context (R8-R11)
  139. MOV R8,R4
  140. MOV R9,R5
  141. MOV R10,R6
  142. MOV R11,R7
  143. MSR PSP,R0 ; Write PSP
  144. SUBS R0,R0,#32 ; Adjust Start Address
  145. LDMIA R0!,{R4-R7} ; Restore new Context (R4-R7)
  146. SVC_Exit
  147. MOVS R0,#:NOT:0xFFFFFFFD ; Set EXC_RETURN value
  148. MVNS R0,R0
  149. BX R0 ; RETI to Thread Mode, use PSP
  150. /*------------------- User SVC ------------------------------*/
  151. SVC_User
  152. PUSH {R4,LR} ; Save Registers
  153. LDR R2,=SVC_Count
  154. LDR R2,[R2]
  155. CMP R1,R2
  156. BHI SVC_Done ; Overflow
  157. LDR R4,=SVC_Table-4
  158. LSLS R1,R1,#2
  159. LDR R4,[R4,R1] ; Load SVC Function Address
  160. MOV LR,R4
  161. LDMIA R0,{R0-R3,R4} ; Read R0-R3,R12 from stack
  162. MOV R12,R4
  163. BLX LR ; Call SVC Function
  164. MRS R4,PSP ; Read PSP
  165. STMIA R4!,{R0-R3} ; Function return values
  166. SVC_Done
  167. POP {R4,PC} ; RETI
  168. ALIGN
  169. }
  170. /*-------------------------- PendSV_Handler ---------------------------------*/
  171. __asm void PendSV_Handler (void) {
  172. PRESERVE8
  173. BL __cpp(rt_pop_req)
  174. Sys_Switch
  175. LDR R3,=__cpp(&os_tsk)
  176. LDMIA R3!,{R1,R2} ; os_tsk.run, os_tsk.next
  177. CMP R1,R2
  178. BEQ Sys_Exit ; no task switch
  179. SUBS R3,#8
  180. MRS R0,PSP ; Read PSP
  181. SUBS R0,R0,#32 ; Adjust Start Address
  182. STR R0,[R1,#TCB_TSTACK] ; Update os_tsk.run->tsk_stack
  183. STMIA R0!,{R4-R7} ; Save old context (R4-R7)
  184. MOV R4,R8
  185. MOV R5,R9
  186. MOV R6,R10
  187. MOV R7,R11
  188. STMIA R0!,{R4-R7} ; Save old context (R8-R11)
  189. PUSH {R2,R3}
  190. BL rt_stk_check ; Check for Stack overflow
  191. POP {R2,R3}
  192. STR R2,[R3] ; os_tsk.run = os_tsk.next
  193. LDR R0,[R2,#TCB_TSTACK] ; os_tsk.next->tsk_stack
  194. ADDS R0,R0,#16 ; Adjust Start Address
  195. LDMIA R0!,{R4-R7} ; Restore new Context (R8-R11)
  196. MOV R8,R4
  197. MOV R9,R5
  198. MOV R10,R6
  199. MOV R11,R7
  200. MSR PSP,R0 ; Write PSP
  201. SUBS R0,R0,#32 ; Adjust Start Address
  202. LDMIA R0!,{R4-R7} ; Restore new Context (R4-R7)
  203. Sys_Exit
  204. MOVS R0,#:NOT:0xFFFFFFFD ; Set EXC_RETURN value
  205. MVNS R0,R0
  206. BX R0 ; RETI to Thread Mode, use PSP
  207. ALIGN
  208. }
  209. /*-------------------------- SysTick_Handler --------------------------------*/
  210. __asm void SysTick_Handler (void) {
  211. PRESERVE8
  212. BL __cpp(rt_systick)
  213. B Sys_Switch
  214. ALIGN
  215. }
  216. /*-------------------------- OS_Tick_Handler --------------------------------*/
  217. __asm void OS_Tick_Handler (void) {
  218. PRESERVE8
  219. BL __cpp(os_tick_irqack)
  220. BL __cpp(rt_systick)
  221. B Sys_Switch
  222. ALIGN
  223. }
  224. /*----------------------------------------------------------------------------
  225. * end of file
  226. *---------------------------------------------------------------------------*/