application: rename `csrs` to `cpuinfo` in cpuinfo

Signed-off-by: qiujiandong <qiujiandong@nucleisys.com>

application/baremetal/cpuinfo/cpuinfo.c

@@ -53,13 +53,13 @@
 
 static void show_isa(CIF_XLEN_Type xlen, U32_CSR_MISA_Type misa,
                      U32_CSR_MCFG_INFO_Type mcfg);
-static void show_mcfg(const CPU_INFO_Group *csrs);
+static void show_mcfg(const CPU_INFO_Group *cpuinfo);
 static void show_micfg_mdcfg(U32_CSR_MCFG_INFO_Type mcfg,
                              U32_CSR_MICFG_INFO_Type micfg,
                              U32_CSR_MDCFG_INFO_Type mdcfg);
 static void show_mtlbcfg(U32_CSR_MCFG_INFO_Type mcfg,
                          U32_CSR_MTLBCFG_INFO_Type mtlbcfg);
-static void show_iregion(const CPU_INFO_Group *csrs);
+static void show_iregion(const CPU_INFO_Group *cpuinfo);
 static void show_mfiocfg(U32_CSR_MCFG_INFO_Type mcfg,
                          U64_CSR_MFIOCFG_INFO_Type mfiocfg);
 static void show_mppicfg(U32_CSR_MCFG_INFO_Type mcfg,
@@ -85,34 +85,34 @@ static char *cvt_size_opt(uint32_t size, int lite);
 static void show_cache_info(uint32_t set, uint32_t way, uint32_t lsize,
                             uint32_t ecc);
 
-void show_cpuinfo(CIF_XLEN_Type xlen, const CPU_INFO_Group *csrs)
+void show_cpuinfo(CIF_XLEN_Type xlen, const CPU_INFO_Group *cpuinfo)
 {
     CIF_PRINTF("\r\n-----Nuclei RISC-V CPU Configuration Information-----\r\n");
 
     /* ID and version */
-    CIF_PRINTF("         MARCHID: 0x%04x\r\n", csrs->marchid.d);
-    CIF_PRINTF("         MHARTID: 0x%x\r\n", csrs->mhartid);
-    CIF_PRINTF("          MIMPID: 0x%06x\r\n", csrs->mimpid.d);
+    CIF_PRINTF("         MARCHID: 0x%04x\r\n", cpuinfo->marchid.d);
+    CIF_PRINTF("         MHARTID: 0x%x\r\n", cpuinfo->mhartid);
+    CIF_PRINTF("          MIMPID: 0x%06x\r\n", cpuinfo->mimpid.d);
 
     /* ISA */
-    show_isa(xlen, csrs->misa, csrs->mcfginfo);
+    show_isa(xlen, cpuinfo->misa, cpuinfo->mcfginfo);
     /* Support */
-    show_mcfg(csrs);
+    show_mcfg(cpuinfo);
     /* ILM, DLM, I/D Cache */
-    show_micfg_mdcfg(csrs->mcfginfo, csrs->micfginfo, csrs->mdcfginfo);
+    show_micfg_mdcfg(cpuinfo->mcfginfo, cpuinfo->micfginfo, cpuinfo->mdcfginfo);
     /* TLB */
-    show_mtlbcfg(csrs->mcfginfo, csrs->mtlbcfginfo);
+    show_mtlbcfg(cpuinfo->mcfginfo, cpuinfo->mtlbcfginfo);
     /* FIO */
-    show_mfiocfg(csrs->mcfginfo, csrs->mfiocfginfo);
+    show_mfiocfg(cpuinfo->mcfginfo, cpuinfo->mfiocfginfo);
     /* PPI */
-    show_mppicfg(csrs->mcfginfo, csrs->mppicfginfo);
+    show_mppicfg(cpuinfo->mcfginfo, cpuinfo->mppicfginfo);
     /* IREGION */
-    show_iregion(csrs);
+    show_iregion(cpuinfo);
 
     CIF_PRINTF("-----End of Nuclei CPU INFO-----\r\n");
 }
 
-int get_basic_cpuinfo(const CPU_INFO_Group *csrs, char *str, unsigned long len)
+int get_basic_cpuinfo(const CPU_INFO_Group *cpuinfo, char *str, unsigned long len)
 {
     if (str == NULL) {
         return -1;
@@ -125,20 +125,20 @@ int get_basic_cpuinfo(const CPU_INFO_Group *csrs, char *str, unsigned long len)
     /* construct ISA string */
     int pos = 0;
     for (int i = 0; i < EXTENSION_NUM; ++i) {
-        if (csrs->misa.d & BIT(i)) {
+        if (cpuinfo->misa.d & BIT(i)) {
             isa[pos++] = 'A' + i;
         }
     }
     isa[pos] = '\0';
 
-    if (!csrs->mcfg_exist) {
-        return snprintf(str, len, BASIC_CPUINFO_FMT, csrs->mhartid, csrs->marchid.d,
-                        csrs->mimpid.b.first_vernum, csrs->mimpid.b.mid_vernum,
-                        csrs->mimpid.b.last_vernum, isa);
+    if (!cpuinfo->mcfg_exist) {
+        return snprintf(str, len, BASIC_CPUINFO_FMT, cpuinfo->mhartid, cpuinfo->marchid.d,
+                        cpuinfo->mimpid.b.first_vernum, cpuinfo->mimpid.b.mid_vernum,
+                        cpuinfo->mimpid.b.last_vernum, isa);
     }
 
     /* construct features string */
-    U32_CSR_MCFG_INFO_Type mcfg = csrs->mcfginfo;
+    U32_CSR_MCFG_INFO_Type mcfg = cpuinfo->mcfginfo;
     CHECK_STRCAT_BUF(mcfg, plic, buf, "MMU, PLIC, ");
     CHECK_STRCAT_BUF(mcfg, eclic, buf, "ECLIC, ");
     CHECK_STRCAT_BUF(mcfg, fio, buf, "FIO, ");
@@ -151,21 +151,21 @@ int get_basic_cpuinfo(const CPU_INFO_Group *csrs, char *str, unsigned long len)
     CHECK_STRCAT_BUF(mcfg, sec_mode, buf, "SMWG, ");
 
     IINFO_ISA_SUPPORT0_Type isa_support0;
-    isa_support0.d = csrs->iinfo->isa_support0;
+    isa_support0.d = cpuinfo->iinfo->isa_support0;
     CHECK_STRCAT_BUF(isa_support0, svpbmt, buf, "Svpbmt, ");
 
     IINFO_MCMO_INFO_Type cmo;
-    cmo.d = csrs->iinfo->cmo_info;
+    cmo.d = cpuinfo->iinfo->cmo_info;
     CHECK_STRCAT_BUF(cmo, cmo_cfg, buf, "CMO, ");
 
     if (mcfg.b.smp) {
-        unsigned long iregion_base = csrs->mirgbinfo.d & (~0x3FF);
-        STRCAT_BUF(buf, "SMPx%d, ", csrs->smpcfg.b.smp_core_num + 1);
+        unsigned long iregion_base = cpuinfo->mirgbinfo.d & (~0x3FF);
+        STRCAT_BUF(buf, "SMPx%d, ", cpuinfo->smpcfg.b.smp_core_num + 1);
     }
 
     /* show local memory and cache info */
-    U32_CSR_MICFG_INFO_Type micfg = csrs->micfginfo;
-    U32_CSR_MDCFG_INFO_Type mdcfg = csrs->mdcfginfo;
+    U32_CSR_MICFG_INFO_Type micfg = cpuinfo->micfginfo;
+    U32_CSR_MDCFG_INFO_Type mdcfg = cpuinfo->mdcfginfo;
     CHECK_STRCAT_BUF(mcfg, ilm, buf, "ILM-%s, ",
                      cvt_size_opt(POW2(micfg.b.lm_size + 7), 1));
     CHECK_STRCAT_BUF(mcfg, dlm, buf, "DLM-%s, ",
@@ -186,9 +186,9 @@ int get_basic_cpuinfo(const CPU_INFO_Group *csrs, char *str, unsigned long len)
         buf[strlen(buf) - 2] = '\0';
     }
 
-    return snprintf(str, len, BASIC_CPUINFO_FMT ", Feature: %s", csrs->mhartid,
-                    csrs->marchid.d, csrs->mimpid.b.first_vernum,
-                    csrs->mimpid.b.mid_vernum, csrs->mimpid.b.last_vernum, isa,
+    return snprintf(str, len, BASIC_CPUINFO_FMT ", Feature: %s", cpuinfo->mhartid,
+                    cpuinfo->marchid.d, cpuinfo->mimpid.b.first_vernum,
+                    cpuinfo->mimpid.b.mid_vernum, cpuinfo->mimpid.b.last_vernum, isa,
                     buf);
 }
 
@@ -226,13 +226,13 @@ static void show_isa(CIF_XLEN_Type xlen, U32_CSR_MISA_Type misa,
     CIF_PRINTF("\r\n");
 }
 
-static void show_mcfg(const CPU_INFO_Group *csrs)
+static void show_mcfg(const CPU_INFO_Group *cpuinfo)
 {
-    if (!csrs->mcfg_exist) {
+    if (!cpuinfo->mcfg_exist) {
         return;
     }
 
-    U32_CSR_MCFG_INFO_Type mcfg = csrs->mcfginfo;
+    U32_CSR_MCFG_INFO_Type mcfg = cpuinfo->mcfginfo;
     CIF_PRINTF("            MCFG:");
     CHECK_FIELD(mcfg, tee, "TEE")
     CHECK_FIELD(mcfg, ecc, "ECC")
@@ -267,7 +267,7 @@ static void show_mcfg(const CPU_INFO_Group *csrs)
         default:
             break;
     }
-    if (csrs->misa.b.V) {
+    if (cpuinfo->misa.b.V) {
         switch (mcfg.b.vpu_degree) {
             case 0b00:
                 CIF_PRINTF(" DLEN=VLEN/2");
@@ -338,15 +338,15 @@ static void show_mtlbcfg(U32_CSR_MCFG_INFO_Type mcfg,
     }
 }
 
-static void show_iregion(const CPU_INFO_Group *csrs)
+static void show_iregion(const CPU_INFO_Group *cpuinfo)
 {
-    U32_CSR_MCFG_INFO_Type mcfg = csrs->mcfginfo;
+    U32_CSR_MCFG_INFO_Type mcfg = cpuinfo->mcfginfo;
     if (!mcfg.b.iregion) {
         return;
     }
 
     CIF_PRINTF("         IREGION:");
-    U64_CSR_MIRGB_INFO_Type mirgb = csrs->mirgbinfo;
+    U64_CSR_MIRGB_INFO_Type mirgb = cpuinfo->mirgbinfo;
     unsigned long iregion_base = mirgb.d & (~0x3FF);
     CIF_PRINTF(" %#lx", iregion_base);
     CIF_PRINTF(" %s\r\n", cvt_size(POW2(mirgb.b.iregion_size + 9)));
@@ -365,7 +365,7 @@ static void show_iregion(const CPU_INFO_Group *csrs)
         CIF_PRINTF("                  SMP         64KB        %#lx\r\n",
                    iregion_base + IREGION_SMP_OFS);
     }
-    U32_SMP_CFG_Type smp_cfg = csrs->smpcfg;
+    U32_SMP_CFG_Type smp_cfg = cpuinfo->smpcfg;
     /* If has eclic and has equal or more than 1 core, CIDU will present
      * The actual core number is `smp_core_num + 1` */
     if (mcfg.b.eclic && (smp_cfg.b.smp_core_num >= 1)) {
@@ -387,7 +387,7 @@ static void show_iregion(const CPU_INFO_Group *csrs)
     }
     /* ECLIC */
     if (mcfg.b.eclic) {
-        ECLIC_Type *eclic = csrs->eclic;
+        ECLIC_Type *eclic = cpuinfo->eclic;
         U32_ECLIC_INFO_Type eclic_info = eclic->info;
         CIF_PRINTF("           ECLIC:");
         CIF_PRINTF(" VERSION=0x%x", eclic_info.b.version);
@@ -399,7 +399,7 @@ static void show_iregion(const CPU_INFO_Group *csrs)
     }
     /* L2CACHE */
     if (smp_cfg.b.cc) {
-        U32_CC_CFG_Type cc_cfg = csrs->cccfg;
+        U32_CC_CFG_Type cc_cfg = cpuinfo->cccfg;
         CIF_PRINTF("         L2CACHE:");
         show_cache_info(POW2(cc_cfg.b.set), cc_cfg.b.way + 1,
                         POW2(cc_cfg.b.lsize + 2), cc_cfg.b.ecc);
@@ -408,26 +408,26 @@ static void show_iregion(const CPU_INFO_Group *csrs)
     unsigned long iinfo_base = iregion_base + IREGION_IINFO_OFS;
     CIF_PRINTF("     INFO-Detail:\r\n");
     /* MPASIZE */
-    uint32_t mpasize = csrs->iinfo->mpasize;
+    uint32_t mpasize = cpuinfo->iinfo->mpasize;
     CIF_PRINTF("                  mpasize : %u\r\n", mpasize);
     /* prefetch related registers */
-    show_prefetch_cfg(csrs->iinfo);
+    show_prefetch_cfg(cpuinfo->iinfo);
     /* ISA_SUPPORT VPU_CFG_INFO */
-    show_isa_support(csrs->iinfo);
+    show_isa_support(cpuinfo->iinfo);
     /* MVLM_CFG */
-    show_mvlm_cfg(csrs->iinfo);
+    show_mvlm_cfg(cpuinfo->iinfo);
     /* FLASH_BASE_ADDR */
-    show_flash_bus(csrs->iinfo);
+    show_flash_bus(cpuinfo->iinfo);
     /* MEM_REGION_CFG */
-    show_mem_region_cfg(csrs->iinfo);
+    show_mem_region_cfg(cpuinfo->iinfo);
     /* MCPPI_CFG */
-    show_mcppi_cfg(csrs->iinfo);
+    show_mcppi_cfg(cpuinfo->iinfo);
     /* CMO_INFO */
-    show_cmo(csrs->iinfo);
+    show_cmo(cpuinfo->iinfo);
     /* PERFORMANCE_CFG */
-    show_performance_cfg(csrs->iinfo);
+    show_performance_cfg(cpuinfo->iinfo);
     /* MERGEL1DCTRL and ACCESS_CTRL */
-    show_misc_cfg(csrs->iinfo);
+    show_misc_cfg(cpuinfo->iinfo);
 }
 
 static void show_mfiocfg(U32_CSR_MCFG_INFO_Type mcfg,

application/baremetal/cpuinfo/cpuinfo.h

@@ -626,21 +626,21 @@ typedef uint32_t IINFO_MCPPI_CFG_HI_Type;
 /**
  * \brief Show full CPU information about ISA, ILD/DLM, I/D cache, etc.
  * \param xlen: XLEN
- * \param csrs: pointer to CPU_CSR_Group
+ * \param cpuinfo: pointer to CPU_INFO_Group
  */
-void show_cpuinfo(CIF_XLEN_Type xlen, const CPU_INFO_Group *csrs);
+void show_cpuinfo(CIF_XLEN_Type xlen, const CPU_INFO_Group *cpuinfo);
 
 /**
  * \brief Get basic CPU information in a single line.
  *        This function is **not reentrant** because it uses
  *        a shared static buffer.
- * \param csrs: pointer to CPU_CSR_Group
+ * \param cpuinfo: pointer to CPU_INFO_Group
  * \param str: pointer to string buffer
  * \param len: length of string buffer
  * \return actual length of result string or '-1' for `str == NULL`,
  *         it is same as the return value of `snprintf`
  */
-int get_basic_cpuinfo(const CPU_INFO_Group *csrs, char *str, unsigned long len);
+int get_basic_cpuinfo(const CPU_INFO_Group *cpuinfo, char *str, unsigned long len);
 
 #ifdef __cplusplus
 }

application/baremetal/cpuinfo/main.c

@@ -17,17 +17,17 @@ int main(void)
 #endif
 
     CIF_XLEN_Type xlen;
-    CPU_INFO_Group csrs;
-    memset(&csrs, 0, sizeof(csrs)); // clear the struct
+    CPU_INFO_Group cpuinfo;
+    memset(&cpuinfo, 0, sizeof(cpuinfo)); // clear the struct
 
-    csrs.marchid.d = (uint32_t)__RV_CSR_READ(CSR_MARCHID);
-    csrs.mhartid = (uint32_t)__RV_CSR_READ(CSR_MHARTID);
-    csrs.mimpid.d = (uint32_t)__RV_CSR_READ(CSR_MIMPID);
-    csrs.misa.d = (uint32_t)__RV_CSR_READ(CSR_MISA);
+    cpuinfo.marchid.d = (uint32_t)__RV_CSR_READ(CSR_MARCHID);
+    cpuinfo.mhartid = (uint32_t)__RV_CSR_READ(CSR_MHARTID);
+    cpuinfo.mimpid.d = (uint32_t)__RV_CSR_READ(CSR_MIMPID);
+    cpuinfo.misa.d = (uint32_t)__RV_CSR_READ(CSR_MISA);
     U32_CSR_MCFG_INFO_Type mcfg;
     mcfg.d = (uint32_t)__RV_CSR_READ(CSR_MCFG_INFO);
-    csrs.mcfg_exist = 1;
-    csrs.mcfginfo = mcfg; 
+    cpuinfo.mcfg_exist = 1;
+    cpuinfo.mcfginfo = mcfg;
 
     /**
      * mtlbcfginfo has a `mapping` field at the highest bit.
@@ -37,45 +37,47 @@ int main(void)
     if (__RISCV_XLEN == 32) {
         xlen = CIF_XLEN_32;
         if (mcfg.b.plic) {
-            csrs.mtlbcfginfo.d = (uint32_t)__RV_CSR_READ(CSR_MTLBCFG_INFO);
+            cpuinfo.mtlbcfginfo.d = (uint32_t)__RV_CSR_READ(CSR_MTLBCFG_INFO);
         }
     } else {
         xlen = CIF_XLEN_64;
         if (mcfg.b.plic) {
             uint64_t mtlbcfginfo = __RV_CSR_READ(CSR_MTLBCFG_INFO);
-            csrs.mtlbcfginfo.d =
+            cpuinfo.mtlbcfginfo.d =
                 (uint32_t)mtlbcfginfo | (uint32_t)((mtlbcfginfo >> 63) << 31);
         }
     }
 
     if (mcfg.b.icache || mcfg.b.ilm) {
-        csrs.micfginfo.d = (uint32_t)__RV_CSR_READ(CSR_MICFG_INFO);
+        cpuinfo.micfginfo.d = (uint32_t)__RV_CSR_READ(CSR_MICFG_INFO);
     }
     if (mcfg.b.dcache || mcfg.b.dlm) {
-        csrs.mdcfginfo.d = (uint32_t)__RV_CSR_READ(CSR_MDCFG_INFO);
+        cpuinfo.mdcfginfo.d = (uint32_t)__RV_CSR_READ(CSR_MDCFG_INFO);
     }
     if (mcfg.b.iregion) {
-        csrs.mirgbinfo.d = (uint64_t)__RV_CSR_READ(CSR_MIRGB_INFO);
-        unsigned long iregion_base = csrs.mirgbinfo.d & (~0x3FF);
-        csrs.iinfo = (IINFO_Type *)iregion_base;
+        cpuinfo.mirgbinfo.d = (uint64_t)__RV_CSR_READ(CSR_MIRGB_INFO);
+        unsigned long iregion_base = cpuinfo.mirgbinfo.d & (~0x3FF);
+        cpuinfo.iinfo = (IINFO_Type *)iregion_base;
         if (mcfg.b.smp) {
-            csrs.smpcfg.d = *(uint32_t *)(iregion_base + IREGION_SMP_OFS + 0x4);
+            cpuinfo.smpcfg.d =
+                *(uint32_t *)(iregion_base + IREGION_SMP_OFS + 0x4);
         }
-        if (csrs.smpcfg.b.cc) {
-            csrs.cccfg.d = *(uint32_t *)(iregion_base + IREGION_SMP_OFS + 0x8);
+        if (cpuinfo.smpcfg.b.cc) {
+            cpuinfo.cccfg.d =
+                *(uint32_t *)(iregion_base + IREGION_SMP_OFS + 0x8);
         }
         if (mcfg.b.eclic) {
-            csrs.eclic = (ECLIC_Type *)(iregion_base + IREGION_ECLIC_OFS);
+            cpuinfo.eclic = (ECLIC_Type *)(iregion_base + IREGION_ECLIC_OFS);
         }
     }
     if (mcfg.b.ppi) {
-        csrs.mppicfginfo.d = (uint64_t)__RV_CSR_READ(CSR_MPPICFG_INFO);
+        cpuinfo.mppicfginfo.d = (uint64_t)__RV_CSR_READ(CSR_MPPICFG_INFO);
     }
     if (mcfg.b.fio) {
-        csrs.mfiocfginfo.d = (uint64_t)__RV_CSR_READ(CSR_MFIOCFG_INFO);
+        cpuinfo.mfiocfginfo.d = (uint64_t)__RV_CSR_READ(CSR_MFIOCFG_INFO);
     }
 
-    show_cpuinfo(xlen, &csrs);
+    show_cpuinfo(xlen, &cpuinfo);
 
     return 0;
 }