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@@ -1,5 +1,5 @@
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/******************************************************************************
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- * @file hbird.h
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+ * @file demosoc.h
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* @brief NMSIS Core Peripheral Access Layer Header File for
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* Nuclei HummingBird evaluation SoC which support Nuclei N/NX class cores
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* @version V1.00
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@@ -23,8 +23,8 @@
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* limitations under the License.
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*/
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-#ifndef __HBIRD_H__
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-#define __HBIRD_H__
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+#ifndef __DEMOSOC_H__
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+#define __DEMOSOC_H__
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#include <stddef.h>
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@@ -37,7 +37,7 @@ extern "C" {
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*/
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-/** @addtogroup hbird
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+/** @addtogroup demosoc
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* @{
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*/
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@@ -76,7 +76,7 @@ typedef enum IRQn
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Reserved15_IRQn = 17, /*!< Internal reserved */
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Reserved16_IRQn = 18, /*!< Internal reserved */
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-/* =========================================== hbird Specific Interrupt Numbers ========================================= */
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+/* =========================================== demosoc Specific Interrupt Numbers ========================================= */
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/* ToDo: add here your device specific external interrupt numbers. 19~1023 is reserved number for user. Maxmum interrupt supported
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could get from clicinfo.NUM_INTERRUPT. According the interrupt handlers defined in startup_Device.s
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eg.: Interrupt for Timer#1 eclic_tim1_handler -> TIM1_IRQn */
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@@ -158,7 +158,7 @@ typedef enum EXCn {
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#endif /* __riscv_xlen == 64 */
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-/* ToDo: define the correct core features for the hbird */
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+/* ToDo: define the correct core features for the demosoc */
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#define __ECLIC_PRESENT 1 /*!< Set to 1 if ECLIC is present */
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#define __ECLIC_BASEADDR 0x0C000000UL /*!< Set to ECLIC baseaddr of your device */
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@@ -188,9 +188,9 @@ typedef enum EXCn {
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#include <nmsis_core.h> /*!< Nuclei N/NX class processor and core peripherals */
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-/* ToDo: include your system_hbird.h file
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+/* ToDo: include your system_demosoc.h file
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replace 'Device' with your device name */
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-#include "system_hbird.h" /*!< hbird System */
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+#include "system_demosoc.h" /*!< demosoc System */
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/* ======================================== Start of section using anonymous unions ======================================== */
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@@ -359,7 +359,7 @@ typedef struct {
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__IOM uint8_t CSR; /* CR and SR in same address */
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} I2C_TypeDef;
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-/*@}*/ /* end of group hbird_Peripherals */
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+/*@}*/ /* end of group demosoc_Peripherals */
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/* ========================================= End of section using anonymous unions ========================================= */
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@@ -385,21 +385,21 @@ typedef struct {
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#define ONCHIP_ROM_BASE (0x00001000UL) /*!< (ROM ) Base Address */
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#define ONCHIP_ILM_BASE (0x80000000UL) /*!< (ILM ) Base Address */
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#define ONCHIP_DLM_BASE (0x90000000UL) /*!< (DLM ) Base Address */
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-#define HBIRD_PERIPH_BASE (0x10000000UL) /*!< (Peripheral) Base Address */
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+#define DEMOSOC_PERIPH_BASE (0x10000000UL) /*!< (Peripheral) Base Address */
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/* Peripheral memory map */
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/* Fast-IO Interfaced IP */
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-#define GPIO_BASE (HBIRD_PERIPH_BASE + 0x12000) /*!< (GPIO) Base Address */
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+#define GPIO_BASE (DEMOSOC_PERIPH_BASE + 0x12000) /*!< (GPIO) Base Address */
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/* PPI Interfaced IP */
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-#define UART0_BASE (HBIRD_PERIPH_BASE + 0x13000) /*!< (UART0) Base Address */
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-#define QSPI0_BASE (HBIRD_PERIPH_BASE + 0x14000) /*!< (QSPI0) Base Address */
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-#define PWM0_BASE (HBIRD_PERIPH_BASE + 0x15000) /*!< (PWM0) Base Address */
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-#define UART1_BASE (HBIRD_PERIPH_BASE + 0x23000) /*!< (UART1) Base Address */
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-#define QSPI1_BASE (HBIRD_PERIPH_BASE + 0x24000) /*!< (QSPI1) Base Address */
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-#define PWM1_BASE (HBIRD_PERIPH_BASE + 0x25000) /*!< (PWM1) Base Address */
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-#define QSPI2_BASE (HBIRD_PERIPH_BASE + 0x34000) /*!< (QSPI2) Base Address */
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-#define PWM2_BASE (HBIRD_PERIPH_BASE + 0x35000) /*!< (PWM2) Base Address */
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-#define I2C_BASE (HBIRD_PERIPH_BASE + 0x42000) /*!< (I2C Master) Base Address */
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+#define UART0_BASE (DEMOSOC_PERIPH_BASE + 0x13000) /*!< (UART0) Base Address */
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+#define QSPI0_BASE (DEMOSOC_PERIPH_BASE + 0x14000) /*!< (QSPI0) Base Address */
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+#define PWM0_BASE (DEMOSOC_PERIPH_BASE + 0x15000) /*!< (PWM0) Base Address */
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+#define UART1_BASE (DEMOSOC_PERIPH_BASE + 0x23000) /*!< (UART1) Base Address */
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+#define QSPI1_BASE (DEMOSOC_PERIPH_BASE + 0x24000) /*!< (QSPI1) Base Address */
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+#define PWM1_BASE (DEMOSOC_PERIPH_BASE + 0x25000) /*!< (PWM1) Base Address */
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+#define QSPI2_BASE (DEMOSOC_PERIPH_BASE + 0x34000) /*!< (QSPI2) Base Address */
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+#define PWM2_BASE (DEMOSOC_PERIPH_BASE + 0x35000) /*!< (PWM2) Base Address */
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+#define I2C_BASE (DEMOSOC_PERIPH_BASE + 0x42000) /*!< (I2C Master) Base Address */
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/** @} */ /* End of group Device_Peripheral_peripheralAddr */
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@@ -448,7 +448,7 @@ typedef struct {
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uint32_t get_cpu_freq();
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void delay_1ms(uint32_t count);
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-/** @} */ /* End of group hbird */
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+/** @} */ /* End of group demosoc */
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/** @} */ /* End of group Nuclei */
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@@ -456,4 +456,4 @@ void delay_1ms(uint32_t count);
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}
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#endif
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-#endif /* __HBIRD_H__ */
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+#endif /* __DEMOSOC_H__ */
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