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@@ -0,0 +1,675 @@
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+/* NOTE: Predefine macro `CIF_PRINTF` before include `cpuinfo.h`
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+ * to replace the default `CIF_PRINTF` function.
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+ */
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+#include "cpuinfo.h"
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+
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+#define BIT(ofs) (0x1U << (ofs))
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+#define EXTENSION_NUM (26)
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+#define POW2(n) (1U << (n))
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+#define LINESZ(n) ((n) > 0U ? POW2((n) - 1) : 0)
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+
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+/* IREGION Offsets */
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+#define IREGION_IINFO_OFS (0x0)
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+#define IREGION_DEBUG_OFS (0x10000)
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+#define IREGION_ECLIC_OFS (0x20000)
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+#define IREGION_TIMER_OFS (0x30000)
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+#define IREGION_SMP_OFS (0x40000)
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+#define IREGION_IDU_OFS (0x50000)
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+#define IREGION_PL2_OFS (0x60000)
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+#define IREGION_DPREFETCH_OFS (0x70000)
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+#define IREGION_PLIC_OFS (0x4000000)
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+
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+/* Check register field with default field name print */
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+#define CHECK_FIELD_DFT(reg, field) \
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+ if (reg.b.field) { \
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+ CIF_PRINTF(" %s", #field); \
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+ }
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+/* Check register field with string specified */
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+#define CHECK_FIELD(reg, field, str) \
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+ if (reg.b.field) { \
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+ CIF_PRINTF(" %s", str); \
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+ }
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+/* Show register value */
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+#define SHOW_VALUE(reg, field) \
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+ CIF_PRINTF(" %s=%u\r\n", #field, reg.b.field);
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+
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+static void show_isa(CIF_XLEN_Type xlen, U32_CSR_MISA_Type misa,
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+ U32_CSR_MCFG_INFO_Type mcfg);
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+static void show_mcfg(const CPU_CSR_Group *csrs);
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+static void show_micfg_mdcfg(U32_CSR_MCFG_INFO_Type mcfg,
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+ U32_CSR_MICFG_INFO_Type micfg,
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+ U32_CSR_MDCFG_INFO_Type mdcfg);
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+static void show_mtlbcfg(U32_CSR_MCFG_INFO_Type mcfg,
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+ U32_CSR_MTLBCFG_INFO_Type mtlbcfg);
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+static void show_iregion(const CPU_CSR_Group *csrs);
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+static void show_mfiocfg(U32_CSR_MCFG_INFO_Type mcfg,
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+ U64_CSR_MFIOCFG_INFO_Type mfiocfg);
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+static void show_mppicfg(U32_CSR_MCFG_INFO_Type mcfg,
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+ U64_CSR_MPPICFG_INFO_Type mppicfg);
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+
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+static void show_prefetch_cfg(IINFO_Type *iinfo);
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+static void show_isa_support(IINFO_Type *iinfo);
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+static void show_mvlm_cfg(IINFO_Type *iinfo);
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+static void show_flash_bus(IINFO_Type *iinfo);
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+static void show_mem_region_cfg(IINFO_Type *iinfo);
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+static void show_mcppi_cfg(IINFO_Type *iinfo);
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+static void show_cmo(IINFO_Type *iinfo);
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+static void show_performance_cfg(IINFO_Type *iinfo);
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+static void show_misc_cfg(IINFO_Type *iinfo);
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+
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+static char *cvt_size(uint32_t size);
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+static void show_cache_info(uint32_t set, uint32_t way, uint32_t lsize,
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+ uint32_t ecc);
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+
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+void show_cpuinfo(CIF_XLEN_Type xlen, const CPU_CSR_Group *csrs)
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+{
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+ CIF_PRINTF("\r\n-----Nuclei RISC-V CPU Configuration Information-----\r\n");
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+
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+ /* ID and version */
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+ CIF_PRINTF(" MARCHID: 0x%04x\r\n", csrs->marchid.d);
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+ CIF_PRINTF(" MIMPID: 0x%06x\r\n", csrs->mimpid.d);
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+
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+ /* ISA */
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+ show_isa(xlen, csrs->misa, csrs->mcfginfo);
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+ /* Support */
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+ show_mcfg(csrs);
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+ /* ILM, DLM, I/D Cache */
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+ show_micfg_mdcfg(csrs->mcfginfo, csrs->micfginfo, csrs->mdcfginfo);
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+ /* TLB */
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+ show_mtlbcfg(csrs->mcfginfo, csrs->mtlbcfginfo);
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+ /* FIO */
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+ show_mfiocfg(csrs->mcfginfo, csrs->mfiocfginfo);
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+ /* PPI */
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+ show_mppicfg(csrs->mcfginfo, csrs->mppicfginfo);
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+ /* IREGION */
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+ show_iregion(csrs);
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+
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+ CIF_PRINTF("-----End of Nuclei CPU INFO-----\r\n");
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+}
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+
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+static void show_isa(CIF_XLEN_Type xlen, U32_CSR_MISA_Type misa,
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+ U32_CSR_MCFG_INFO_Type mcfg)
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+{
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+ CIF_PRINTF(" ISA:");
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+ if (xlen == CIF_XLEN_32) {
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+ CIF_PRINTF(" RV32");
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+ } else if (xlen == CIF_XLEN_64) {
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+ CIF_PRINTF(" RV64");
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+ } else {
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+ CIF_PRINTF(" Unknown");
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+ }
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+ for (int i = 0; i < EXTENSION_NUM; i++) {
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+ if (misa.d & BIT(i)) {
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+ if ('X' == ('A' + i)) {
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+ CIF_PRINTF(" NICE");
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+ } else {
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+ CIF_PRINTF(" %c", 'A' + i);
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+ }
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+ }
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+ }
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+ CHECK_FIELD(mcfg, dsp_n1, "Xxldspn1x");
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+ CHECK_FIELD(mcfg, dsp_n2, "Xxldspn2x");
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+ CHECK_FIELD(mcfg, dsp_n3, "Xxldspn3x");
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+ if (mcfg.b.zc_xlcz) {
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+ if (mcfg.b.xlcz == 0) {
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+ CIF_PRINTF(" Zc Xxlcz");
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+ } else {
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+ CIF_PRINTF(" Zc");
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+ }
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+ }
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+ CHECK_FIELD(mcfg, zilsd, "Zilsd");
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+ CIF_PRINTF("\r\n");
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+}
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+
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+static void show_mcfg(const CPU_CSR_Group *csrs)
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+{
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+ if (!csrs->mcfg_exist) {
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+ return;
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+ }
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+
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+ U32_CSR_MCFG_INFO_Type mcfg = csrs->mcfginfo;
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+ CIF_PRINTF(" MCFG:");
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+ CHECK_FIELD(mcfg, tee, "TEE")
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+ CHECK_FIELD(mcfg, ecc, "ECC")
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+ CHECK_FIELD(mcfg, eclic, "ECLIC")
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+ CHECK_FIELD(mcfg, plic, "PLIC")
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+ CHECK_FIELD(mcfg, fio, "FIO")
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+ CHECK_FIELD(mcfg, ppi, "PPI")
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+ CHECK_FIELD(mcfg, nice, "NICE")
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+ CHECK_FIELD(mcfg, ilm, "ILM")
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+ CHECK_FIELD(mcfg, dlm, "DLM")
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+ CHECK_FIELD(mcfg, icache, "ICACHE")
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+ CHECK_FIELD(mcfg, dcache, "DCACHE")
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+ CHECK_FIELD(mcfg, smp, "SMP")
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+ CHECK_FIELD(mcfg, iregion, "IREGION")
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+ CHECK_FIELD(mcfg, sec_mode, "SMWG")
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+ CHECK_FIELD(mcfg, etrace, "ETRACE")
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+ CHECK_FIELD(mcfg, vnice, "VNICE")
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+ CHECK_FIELD(mcfg, sstc, "SSTC")
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+ switch (mcfg.b.safety_mecha) {
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+ case 0b00:
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+ CIF_PRINTF(" No-Safety-Mechanism");
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+ break;
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+ case 0b01:
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+ CIF_PRINTF(" Lockstep");
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+ break;
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+ case 0b10:
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+ CIF_PRINTF(" Lockstep+SplitMode");
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+ break;
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+ case 0b11:
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+ CIF_PRINTF(" ASIL-B");
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+ break;
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+ default:
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+ break;
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+ }
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+ if (csrs->misa.b.V) {
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+ switch (mcfg.b.vpu_degree) {
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+ case 0b00:
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+ CIF_PRINTF(" DLEN=VLEN/2");
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+ break;
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+ case 0b01:
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+ CIF_PRINTF(" DLEN=VLEN");
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+ break;
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+ default:
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+ break;
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+ }
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+ }
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+ CIF_PRINTF("\r\n");
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+}
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+
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+static void show_micfg_mdcfg(U32_CSR_MCFG_INFO_Type mcfg,
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+ U32_CSR_MICFG_INFO_Type micfg,
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+ U32_CSR_MDCFG_INFO_Type mdcfg)
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+{
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+ /* ILM */
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+ if (mcfg.b.ilm) {
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+ CIF_PRINTF(" ILM:");
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+ CIF_PRINTF(" %s", cvt_size(POW2(micfg.b.lm_size + 7)));
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+ CHECK_FIELD(micfg, lm_xonly, "execute-only");
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+ CHECK_FIELD(micfg, lm_ecc, "has-ecc");
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+ CIF_PRINTF("\r\n");
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+ }
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+ /* DLM */
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+ if (mcfg.b.dlm) {
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+ CIF_PRINTF(" DLM:");
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+ CIF_PRINTF(" %s", cvt_size(POW2(mdcfg.b.lm_size + 7)));
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+ CHECK_FIELD(mdcfg, lm_ecc, "has-ecc");
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+ CIF_PRINTF("\r\n");
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+ }
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+ /* ICACHE */
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+ if (mcfg.b.icache) {
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+ CIF_PRINTF(" ICACHE:");
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+ show_cache_info(POW2(micfg.b.set + 3), micfg.b.way + 1,
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+ POW2(micfg.b.lsize + 2), mcfg.b.ecc);
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+ }
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+ /* DCACHE */
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+ if (mcfg.b.dcache) {
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+ CIF_PRINTF(" DCACHE:");
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+ show_cache_info(POW2(mdcfg.b.set + 3), mdcfg.b.way + 1,
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+ POW2(mdcfg.b.lsize + 2), mcfg.b.ecc);
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+ }
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+}
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+
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+static void show_mtlbcfg(U32_CSR_MCFG_INFO_Type mcfg,
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+ U32_CSR_MTLBCFG_INFO_Type mtlbcfg)
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+{
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+ /* TLB only present with MMU, when PLIC present MMU will present */
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+ if (mcfg.b.plic) {
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+ if (mtlbcfg.nb.mapping == 1) {
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+ CIF_PRINTF(" TLB:");
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+ CIF_PRINTF(" MainTLB(entry=%u,way=%u,ecc=%u)",
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+ POW2(mtlbcfg.nb.set + 3), mtlbcfg.nb.way + 1,
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+ mtlbcfg.nb.ecc);
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+ CIF_PRINTF(" ITLB(entry=%u) DTLB(entry=%u)\r\n",
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+ mtlbcfg.nb.i_size + 1, mtlbcfg.nb.d_size + 1);
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+ } else {
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+ CIF_PRINTF(" TLB:");
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+ CIF_PRINTF(" MainTLB(entry=%u,way=%u,ecc=%u)",
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+ POW2(mtlbcfg.b.set + 3), mtlbcfg.b.way + 1,
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+ mtlbcfg.b.ecc);
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+ CIF_PRINTF(" ITLB(entry=%u) DTLB(entry=%u)\r\n",
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+ LINESZ(mtlbcfg.b.i_size), LINESZ(mtlbcfg.b.d_size));
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+ }
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+ }
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+}
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+
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+static void show_iregion(const CPU_CSR_Group *csrs)
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+{
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+ U32_CSR_MCFG_INFO_Type mcfg = csrs->mcfginfo;
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+ if (!mcfg.b.iregion) {
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+ return;
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+ }
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+
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+ CIF_PRINTF(" IREGION:");
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+ U64_CSR_MIRGB_INFO_Type mirgb = csrs->mirgbinfo;
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+ unsigned long iregion_base = mirgb.d & (~0x3FF);
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+ CIF_PRINTF(" %#lx", iregion_base);
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+ CIF_PRINTF(" %s\r\n", cvt_size(POW2(mirgb.b.iregion_size + 9)));
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+ CIF_PRINTF(" Unit Size Address\r\n");
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+ CIF_PRINTF(" INFO 64KB %#lx\r\n",
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+ iregion_base + IREGION_IINFO_OFS);
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+ CIF_PRINTF(" DEBUG 64KB %#lx\r\n",
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+ iregion_base + IREGION_DEBUG_OFS);
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+ if (mcfg.b.eclic) {
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+ CIF_PRINTF(" ECLIC 64KB %#lx\r\n",
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+ iregion_base + IREGION_ECLIC_OFS);
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+ }
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+ CIF_PRINTF(" TIMER 64KB %#lx\r\n",
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+ iregion_base + IREGION_TIMER_OFS);
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+ if (mcfg.b.smp) {
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+ CIF_PRINTF(" SMP 64KB %#lx\r\n",
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+ iregion_base + IREGION_SMP_OFS);
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+ }
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+ U32_CSR_SMP_CFG_Type smp_cfg =
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+ *(U32_CSR_SMP_CFG_Type *)(iregion_base + IREGION_SMP_OFS + 4);
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+ /* If has eclic and has equal or more than 1 core, CIDU will present
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+ * The actual core number is `smp_core_num + 1` */
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+ if (mcfg.b.eclic && (smp_cfg.b.smp_core_num >= 1)) {
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+ CIF_PRINTF(" CIDU 64KB %#lx\r\n",
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+ iregion_base + IREGION_IDU_OFS);
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+ }
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+ if (mcfg.b.plic) {
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+ CIF_PRINTF(" PLIC 64MB %#lx\r\n",
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+ iregion_base + IREGION_PLIC_OFS);
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+ }
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+ /* SMP */
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+ if (mcfg.b.smp) {
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+ CIF_PRINTF(" SMP_CFG:");
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+ CIF_PRINTF(" CC_PRESENT=%d", smp_cfg.b.cc);
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+ CIF_PRINTF(" SMP_NUM=%d", smp_cfg.b.smp_core_num + 1);
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+ CIF_PRINTF(" IOCP_NUM=%d", smp_cfg.b.iocp_num);
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+ CIF_PRINTF(" PMON_NUM=%d", smp_cfg.b.pmon_num);
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+ CIF_PRINTF("\r\n");
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+ }
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+ /* ECLIC */
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+ if (mcfg.b.eclic) {
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+ ECLIC_Type *eclic = (ECLIC_Type *)(iregion_base + IREGION_ECLIC_OFS);
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+ U32_CSR_ECLIC_INFO_Type eclic_info = eclic->info;
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+ CIF_PRINTF(" ECLIC:");
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+ CIF_PRINTF(" VERSION=0x%x", eclic_info.b.version);
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+ CIF_PRINTF(" NUM_INTERRUPT=%u", eclic_info.b.num_interrupt);
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+ CIF_PRINTF(" CLICINTCTLBITS=%u", eclic_info.b.clicintctlbits);
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+ CIF_PRINTF(" MTH=%u", eclic->mth);
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+ CIF_PRINTF(" NLBITS=%u", (eclic->cfg & 0x1E) >> 1);
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+ CIF_PRINTF("\r\n");
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+ }
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+ /* L2CACHE */
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+ if (smp_cfg.b.cc) {
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+ U32_CSR_CC_CFG_Type cc_cfg =
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+ *(U32_CSR_CC_CFG_Type *)(iregion_base + IREGION_SMP_OFS + 8);
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+ CIF_PRINTF(" L2CACHE:");
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+ show_cache_info(POW2(cc_cfg.b.set), cc_cfg.b.way + 1,
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+ POW2(cc_cfg.b.lsize + 2), cc_cfg.b.ecc);
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+ }
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+ /* IREGION INFO */
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+ unsigned long iinfo_base = iregion_base + IREGION_IINFO_OFS;
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+ CIF_PRINTF(" INFO-Detail:\r\n");
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+ /* MPASIZE */
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+ uint32_t mpasize = csrs->iinfo->mpasize;
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+ CIF_PRINTF(" mpasize : %u\r\n", mpasize);
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+ /* prefetch related registers */
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+ show_prefetch_cfg(csrs->iinfo);
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+ /* ISA_SUPPORT VPU_CFG_INFO */
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+ show_isa_support(csrs->iinfo);
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+ /* MVLM_CFG */
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+ show_mvlm_cfg(csrs->iinfo);
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+ /* FLASH_BASE_ADDR */
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+ show_flash_bus(csrs->iinfo);
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+ /* MEM_REGION_CFG */
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+ show_mem_region_cfg(csrs->iinfo);
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+ /* MCPPI_CFG */
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+ show_mcppi_cfg(csrs->iinfo);
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+ /* CMO_INFO */
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+ show_cmo(csrs->iinfo);
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+ /* PERFORMANCE_CFG */
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+ show_performance_cfg(csrs->iinfo);
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+ /* MERGEL1DCTRL and ACCESS_CTRL */
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+ show_misc_cfg(csrs->iinfo);
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+}
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+
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+static void show_mfiocfg(U32_CSR_MCFG_INFO_Type mcfg,
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+ U64_CSR_MFIOCFG_INFO_Type mfiocfg)
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+{
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+ if (mcfg.b.fio) {
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+ CIF_PRINTF(" FIO:");
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+ CIF_PRINTF(" %#lx", (unsigned long)mfiocfg.d & (~0x3FF));
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|
|
+ CIF_PRINTF(" %s\r\n", cvt_size(POW2(mfiocfg.b.fio_size + 9)));
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static void show_mppicfg(U32_CSR_MCFG_INFO_Type mcfg,
|
|
|
+ U64_CSR_MPPICFG_INFO_Type mppicfg)
|
|
|
+{
|
|
|
+ if (mcfg.b.ppi) {
|
|
|
+ CIF_PRINTF(" PPI:");
|
|
|
+ CIF_PRINTF(" %#lx", (unsigned long)mppicfg.d & (~0x3FF));
|
|
|
+ CIF_PRINTF(" %s\r\n", cvt_size(POW2(mppicfg.b.ppi_size + 9)));
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static void show_prefetch_cfg(IINFO_Type *iinfo)
|
|
|
+{
|
|
|
+ IINFO_PFL1INFO_Type pfl1info;
|
|
|
+ pfl1info.d = iinfo->pfl1info;
|
|
|
+ if (pfl1info.b.pf_cfg) {
|
|
|
+ CIF_PRINTF(" prefetch: present\r\n");
|
|
|
+ const char *pf_cfg[] = {"none", "normal", "high performance"};
|
|
|
+ if (pfl1info.b.pf_cfg < 3) {
|
|
|
+ CIF_PRINTF(" prefetch_mode: %s\r\n",
|
|
|
+ pf_cfg[pfl1info.b.pf_cfg]);
|
|
|
+ }
|
|
|
+ if (iinfo->pfl1dctrl4 & BIT(0)) {
|
|
|
+ CIF_PRINTF(" status: enable\r\n");
|
|
|
+ } else {
|
|
|
+ CIF_PRINTF(" status: disable\r\n");
|
|
|
+ }
|
|
|
+ if (pfl1info.b.pf_ver) {
|
|
|
+ CIF_PRINTF(" version=%u\r\n",
|
|
|
+ pfl1info.b.pf_ver);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* prefetch config */
|
|
|
+ IINFO_PFL1DCTRL1_Type pfl1dctrl1;
|
|
|
+ IINFO_PFL1DCTRL2_Type pfl1dctrl2;
|
|
|
+ IINFO_PFL1DCTRL3_Type pfl1dctrl3;
|
|
|
+ pfl1dctrl1.d = iinfo->pfl1dctrl1;
|
|
|
+ pfl1dctrl2.d = iinfo->pfl1dctrl2;
|
|
|
+ pfl1dctrl3.d = iinfo->pfl1dctrl3;
|
|
|
+ SHOW_VALUE(pfl1info, l2_pf_lbuf_num);
|
|
|
+ SHOW_VALUE(pfl1info, l2_pf_dbuf_num);
|
|
|
+ SHOW_VALUE(pfl1dctrl1, l1d_ena);
|
|
|
+ SHOW_VALUE(pfl1dctrl1, cc_ena);
|
|
|
+ SHOW_VALUE(pfl1dctrl1, scalar_ena);
|
|
|
+ SHOW_VALUE(pfl1dctrl1, vector_ena);
|
|
|
+ SHOW_VALUE(pfl1dctrl1, write_pref_ena);
|
|
|
+ SHOW_VALUE(pfl1dctrl1, cross_page_pref_ena);
|
|
|
+ SHOW_VALUE(pfl1dctrl1, pref_conflict_stop_th);
|
|
|
+ SHOW_VALUE(pfl1dctrl1, pref_conflict_decr_sel);
|
|
|
+ SHOW_VALUE(pfl1dctrl2, degree_incr_th);
|
|
|
+ SHOW_VALUE(pfl1dctrl2, degree_decr_th);
|
|
|
+ SHOW_VALUE(pfl1dctrl2, next_line_ena_th);
|
|
|
+ SHOW_VALUE(pfl1dctrl2, write_noalloc_l1_th);
|
|
|
+ SHOW_VALUE(pfl1dctrl2, write_noalloc_l2_th);
|
|
|
+ SHOW_VALUE(pfl1dctrl3, max_stream_l1_degree);
|
|
|
+ SHOW_VALUE(pfl1dctrl3, max_stream_l2_degree);
|
|
|
+ SHOW_VALUE(pfl1dctrl3, max_stride_cplx_l1_degree);
|
|
|
+ SHOW_VALUE(pfl1dctrl3, max_stride_cplx_l2_degree);
|
|
|
+ } else {
|
|
|
+ CIF_PRINTF(" prefetch: absent\r\n");
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static void show_isa_support(IINFO_Type *iinfo)
|
|
|
+{
|
|
|
+ IINFO_ISA_SUPPORT0_Type isa_support0;
|
|
|
+ IINFO_ISA_SUPPORT1_Type isa_support1;
|
|
|
+ isa_support0.d = iinfo->isa_support0;
|
|
|
+ isa_support1.d = iinfo->isa_support1;
|
|
|
+
|
|
|
+ if (isa_support0.b.exist || isa_support1.b.exist) {
|
|
|
+ CIF_PRINTF(" isa supported: present\r\n");
|
|
|
+ CIF_PRINTF(" extension_list:");
|
|
|
+ if (isa_support0.b.exist) {
|
|
|
+ CHECK_FIELD_DFT(isa_support0, vector);
|
|
|
+ CHECK_FIELD_DFT(isa_support0, smepmp);
|
|
|
+ CHECK_FIELD_DFT(isa_support0, sscofpmf);
|
|
|
+ CHECK_FIELD_DFT(isa_support0, zfh);
|
|
|
+ CHECK_FIELD_DFT(isa_support0, zfhmin);
|
|
|
+ CHECK_FIELD_DFT(isa_support0, zfa);
|
|
|
+ CHECK_FIELD_DFT(isa_support0, svnapot);
|
|
|
+ CHECK_FIELD_DFT(isa_support0, svpbmt);
|
|
|
+ CHECK_FIELD_DFT(isa_support0, svinval);
|
|
|
+ CHECK_FIELD_DFT(isa_support0, bf16);
|
|
|
+ CHECK_FIELD_DFT(isa_support0, zimop);
|
|
|
+ CHECK_FIELD_DFT(isa_support0, zcmop);
|
|
|
+ CHECK_FIELD_DFT(isa_support0, zicond);
|
|
|
+ CHECK_FIELD_DFT(isa_support0, zihintntl);
|
|
|
+ CHECK_FIELD_DFT(isa_support0, zihintpause);
|
|
|
+ CHECK_FIELD_DFT(isa_support0, smrnmi);
|
|
|
+ CHECK_FIELD_DFT(isa_support0, zihpm);
|
|
|
+ CHECK_FIELD_DFT(isa_support0, smcntrpmf);
|
|
|
+ CHECK_FIELD_DFT(isa_support0, zicntr);
|
|
|
+ CHECK_FIELD_DFT(isa_support0, zawrs);
|
|
|
+ }
|
|
|
+ if (isa_support1.b.exist) {
|
|
|
+ CHECK_FIELD_DFT(isa_support1, ssqosid);
|
|
|
+ CHECK_FIELD_DFT(isa_support1, zicflip);
|
|
|
+ CHECK_FIELD_DFT(isa_support1, zicfiss);
|
|
|
+ CHECK_FIELD_DFT(isa_support1, smctr);
|
|
|
+ CHECK_FIELD_DFT(isa_support1, zacas);
|
|
|
+ CHECK_FIELD_DFT(isa_support1, zabha);
|
|
|
+ CHECK_FIELD_DFT(isa_support1, smdbltrp);
|
|
|
+ CHECK_FIELD_DFT(isa_support1, ssdbltrp);
|
|
|
+ CHECK_FIELD_DFT(isa_support1, smcdeleg);
|
|
|
+ CHECK_FIELD_DFT(isa_support1, smmpm);
|
|
|
+ CHECK_FIELD_DFT(isa_support1, smnpm);
|
|
|
+ CHECK_FIELD_DFT(isa_support1, ssnpm);
|
|
|
+ CHECK_FIELD_DFT(isa_support1, smstateen);
|
|
|
+ CHECK_FIELD_DFT(isa_support1, sstateen);
|
|
|
+ CHECK_FIELD_DFT(isa_support1, smcsrind);
|
|
|
+ CHECK_FIELD_DFT(isa_support1, sscsrind);
|
|
|
+ CHECK_FIELD_DFT(isa_support1, svadu);
|
|
|
+ }
|
|
|
+ CIF_PRINTF("\r\n");
|
|
|
+ } else {
|
|
|
+ CIF_PRINTF(" isa supported: absent\r\n");
|
|
|
+ }
|
|
|
+
|
|
|
+ /* VPU related extensions */
|
|
|
+ if (isa_support0.b.exist && isa_support0.b.vector) {
|
|
|
+ CIF_PRINTF(" vpu: present\r\n");
|
|
|
+ CIF_PRINTF(" vpu_extension_list:");
|
|
|
+ CHECK_FIELD_DFT(isa_support0, vector_b);
|
|
|
+ CHECK_FIELD_DFT(isa_support0, vector_k);
|
|
|
+ CHECK_FIELD_DFT(isa_support0, zve32x);
|
|
|
+ CHECK_FIELD_DFT(isa_support0, zve32f);
|
|
|
+ CHECK_FIELD_DFT(isa_support0, zve64x);
|
|
|
+ CHECK_FIELD_DFT(isa_support0, zve64f);
|
|
|
+ CHECK_FIELD_DFT(isa_support0, zve64d);
|
|
|
+ CHECK_FIELD_DFT(isa_support0, zvfh);
|
|
|
+ CHECK_FIELD_DFT(isa_support0, zvfhmin);
|
|
|
+ CIF_PRINTF("\r\n");
|
|
|
+
|
|
|
+ uint32_t vpu_cfg_info = iinfo->vpu_cfg_info;
|
|
|
+ CIF_PRINTF(" noseg_noshuf=%u\r\n",
|
|
|
+ (unsigned int)(vpu_cfg_info & BIT(0)));
|
|
|
+ CIF_PRINTF(" elen64=%u\r\n",
|
|
|
+ (unsigned int)(vpu_cfg_info & BIT(1)) >> 1);
|
|
|
+ } else {
|
|
|
+ CIF_PRINTF(" vpu: absent\r\n");
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static void show_mvlm_cfg(IINFO_Type *iinfo)
|
|
|
+{
|
|
|
+ IINFO_MVLM_CFG_LO_Type mvlm_cfg_lo;
|
|
|
+ mvlm_cfg_lo.d = iinfo->mvlm_cfg_lo;
|
|
|
+ if (mvlm_cfg_lo.b.vlm) {
|
|
|
+ CIF_PRINTF(" vlm: present\r\n");
|
|
|
+ IINFO_MVLM_CFG_HI_Type mvlm_cfg_hi = iinfo->mvlm_cfg_hi;
|
|
|
+ unsigned long vlm_base =
|
|
|
+ (uint64_t)mvlm_cfg_hi << 32 | (mvlm_cfg_lo.d & (~0x3FF));
|
|
|
+ CIF_PRINTF(" base=0x%lx\r\n", vlm_base);
|
|
|
+ CIF_PRINTF(" size=%s\r\n",
|
|
|
+ cvt_size(POW2(mvlm_cfg_lo.b.vlm_size + 9)));
|
|
|
+ } else {
|
|
|
+ CIF_PRINTF(" vlm: absent\r\n");
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static void show_flash_bus(IINFO_Type *iinfo)
|
|
|
+{
|
|
|
+ IINFO_FLASH_BASE_ADDR_LO_Type addr_lo;
|
|
|
+ addr_lo.d = iinfo->flash_base_addr_lo;
|
|
|
+ if (addr_lo.b.flash) {
|
|
|
+ CIF_PRINTF(" flash bus: present\r\n");
|
|
|
+ IINFO_FLASH_BASE_ADDR_HI_Type addr_hi = iinfo->flash_base_addr_hi;
|
|
|
+ unsigned long flash_base =
|
|
|
+ (uint64_t)addr_hi << 32 | (addr_lo.d & (~0x3FF));
|
|
|
+ CIF_PRINTF(" base=0x%lx\r\n", flash_base);
|
|
|
+ CIF_PRINTF(" size=%s\r\n",
|
|
|
+ cvt_size(addr_lo.b.flash_size + 9));
|
|
|
+ } else {
|
|
|
+ CIF_PRINTF(" flash bus: absent\r\n");
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static void show_mem_region_cfg(IINFO_Type *iinfo)
|
|
|
+{
|
|
|
+ IINFO_MEM_REGION_CFG_LO_Type region_lo;
|
|
|
+ region_lo.d = iinfo->mem_region0_cfg_lo;
|
|
|
+ if (region_lo.b.exist) {
|
|
|
+ CIF_PRINTF(" mem_region0: present\r\n");
|
|
|
+ IINFO_MEM_REGION_CFG_HI_Type region_hi = iinfo->mem_region0_cfg_hi;
|
|
|
+ unsigned long region_base =
|
|
|
+ (uint64_t)region_hi << 32 | (region_lo.d & (~0x3FF));
|
|
|
+ if (region_lo.b.mem_region_ena) {
|
|
|
+ CIF_PRINTF(" status: enable\r\n");
|
|
|
+ } else {
|
|
|
+ CIF_PRINTF(" status: disable\r\n");
|
|
|
+ }
|
|
|
+ CIF_PRINTF(" base=0x%lx\r\n", region_base);
|
|
|
+ CIF_PRINTF(" size=%s\r\n",
|
|
|
+ cvt_size(region_lo.b.mem_region_size + 9));
|
|
|
+ } else {
|
|
|
+ CIF_PRINTF(" mem_region0: absent\r\n");
|
|
|
+ }
|
|
|
+ region_lo.d = iinfo->mem_region1_cfg_lo;
|
|
|
+ if (region_lo.b.exist) {
|
|
|
+ CIF_PRINTF(" mem_region1: present\r\n");
|
|
|
+ IINFO_MEM_REGION_CFG_HI_Type region_hi = iinfo->mem_region1_cfg_hi;
|
|
|
+ unsigned long region_base =
|
|
|
+ (uint64_t)region_hi << 32 | (region_lo.d & (~0x3FF));
|
|
|
+ if (region_lo.b.mem_region_ena) {
|
|
|
+ CIF_PRINTF(" status: enable\r\n");
|
|
|
+ } else {
|
|
|
+ CIF_PRINTF(" status: disable\r\n");
|
|
|
+ }
|
|
|
+ CIF_PRINTF(" base=0x%lx\r\n", region_base);
|
|
|
+ CIF_PRINTF(" size=%s\r\n",
|
|
|
+ cvt_size(region_lo.b.mem_region_size + 9));
|
|
|
+ } else {
|
|
|
+ CIF_PRINTF(" mem_region1: absent\r\n");
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static void show_mcppi_cfg(IINFO_Type *iinfo)
|
|
|
+{
|
|
|
+ IINFO_MCPPI_CFG_LO_Type mcppi_lo;
|
|
|
+ mcppi_lo.d = iinfo->mcppi_cfg_lo;
|
|
|
+ if (mcppi_lo.b.exist) {
|
|
|
+ CIF_PRINTF(" cppi: present\r\n");
|
|
|
+ IINFO_MCPPI_CFG_HI_Type mcppi_hi = iinfo->mcppi_cfg_hi;
|
|
|
+ unsigned long mcppi_base =
|
|
|
+ (uint64_t)mcppi_hi << 32 | (mcppi_lo.d & (~0x3FF));
|
|
|
+ if (mcppi_lo.b.cppi_ena) {
|
|
|
+ CIF_PRINTF(" status: enable\r\n");
|
|
|
+ } else {
|
|
|
+ CIF_PRINTF(" status: disable\r\n");
|
|
|
+ }
|
|
|
+ CIF_PRINTF(" base=0x%lx\r\n", mcppi_base);
|
|
|
+ CIF_PRINTF(" size=%s\r\n",
|
|
|
+ cvt_size(mcppi_lo.b.cppi_size + 9));
|
|
|
+ } else {
|
|
|
+ CIF_PRINTF(" cppi: absent\r\n");
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static void show_cmo(IINFO_Type *iinfo)
|
|
|
+{
|
|
|
+ IINFO_MCMO_INFO_Type cmo_info;
|
|
|
+ cmo_info.d = iinfo->cmo_info;
|
|
|
+ if (cmo_info.b.cmo_cfg) {
|
|
|
+ CIF_PRINTF(" cmo: present\r\n");
|
|
|
+ CIF_PRINTF(" cbozero_size: %u Bytes\r\n",
|
|
|
+ POW2(cmo_info.b.cbozero_size + 2));
|
|
|
+ CIF_PRINTF(" cmo_size: %u Bytes\r\n",
|
|
|
+ POW2(cmo_info.b.cmo_size + 2));
|
|
|
+ CIF_PRINTF(" cmo_prefetch=%u\r\n",
|
|
|
+ cmo_info.b.cmo_pft);
|
|
|
+ } else {
|
|
|
+ CIF_PRINTF(" cmo: absent\r\n");
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static void show_performance_cfg(IINFO_Type *iinfo)
|
|
|
+{
|
|
|
+ IINFO_PERFORMANCE_CFG0_Type performance_cfg0;
|
|
|
+ IINFO_PERFORMANCE_CFG1_Type performance_cfg1;
|
|
|
+ performance_cfg0.d = iinfo->performance_cfg0;
|
|
|
+ performance_cfg1.d = iinfo->performance_cfg1;
|
|
|
+
|
|
|
+ if (performance_cfg0.b.exist || performance_cfg1.b.exist) {
|
|
|
+ CIF_PRINTF(" hw performance: present\r\n");
|
|
|
+ if (performance_cfg0.b.exist) {
|
|
|
+ const char *bus[] = {"ICB", "AXI", "AHBL"};
|
|
|
+ if (performance_cfg0.b.bus_type < 3) {
|
|
|
+ CIF_PRINTF(" bus: %s\r\n",
|
|
|
+ bus[performance_cfg0.b.bus_type]);
|
|
|
+ }
|
|
|
+ SHOW_VALUE(performance_cfg0, fpu_cycle);
|
|
|
+ SHOW_VALUE(performance_cfg0, high_div);
|
|
|
+ SHOW_VALUE(performance_cfg0, dcache_2stage);
|
|
|
+ SHOW_VALUE(performance_cfg0, delay_branch_flush);
|
|
|
+ SHOW_VALUE(performance_cfg0, dual_issue);
|
|
|
+ SHOW_VALUE(performance_cfg0, cross_4k);
|
|
|
+ SHOW_VALUE(performance_cfg0, dlm_2stage);
|
|
|
+ SHOW_VALUE(performance_cfg0, lsu_cut_fwd);
|
|
|
+ SHOW_VALUE(performance_cfg0, dsp_cycle);
|
|
|
+ SHOW_VALUE(performance_cfg0, ifu_cut_timing);
|
|
|
+ SHOW_VALUE(performance_cfg0, mem_cut_timing);
|
|
|
+ SHOW_VALUE(performance_cfg0, dcache_prefetch);
|
|
|
+ SHOW_VALUE(performance_cfg0, dcache_lbuf_num);
|
|
|
+ SHOW_VALUE(performance_cfg0, mul_cyc);
|
|
|
+ }
|
|
|
+ if (performance_cfg1.b.exist) {
|
|
|
+ SHOW_VALUE(performance_cfg1, vfpu_cyc);
|
|
|
+ SHOW_VALUE(performance_cfg1, bht_entry_width);
|
|
|
+ SHOW_VALUE(performance_cfg1, high_performance);
|
|
|
+ SHOW_VALUE(performance_cfg1, agu_quick_forward);
|
|
|
+ SHOW_VALUE(performance_cfg1, cau_fwd);
|
|
|
+ SHOW_VALUE(performance_cfg1, hpm_ver);
|
|
|
+ }
|
|
|
+ } else {
|
|
|
+ CIF_PRINTF(" hw performance: absent\r\n");
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static void show_misc_cfg(IINFO_Type *iinfo)
|
|
|
+{
|
|
|
+ IINFO_MERGEL1DCTRL_Type mergel1dctrl;
|
|
|
+ IINFO_ACCESS_CTRL_Type access_ctrl;
|
|
|
+ mergel1dctrl.d = iinfo->mergel1dctrl;
|
|
|
+ access_ctrl.d = iinfo->access_ctrl;
|
|
|
+ CIF_PRINTF(" misc: \r\n");
|
|
|
+ SHOW_VALUE(mergel1dctrl, ws_tmout_max);
|
|
|
+ SHOW_VALUE(mergel1dctrl, nc_tmout_max);
|
|
|
+ SHOW_VALUE(mergel1dctrl, dev_store_early_ret);
|
|
|
+ SHOW_VALUE(access_ctrl, pf_access);
|
|
|
+ SHOW_VALUE(access_ctrl, cache_csr_access);
|
|
|
+ SHOW_VALUE(access_ctrl, pma_csr_access);
|
|
|
+}
|
|
|
+
|
|
|
+/* Convert to human readable size */
|
|
|
+static char *cvt_size(uint32_t size)
|
|
|
+{
|
|
|
+ static char buf[32];
|
|
|
+ char units[] = {'B', 'K', 'M', 'G'};
|
|
|
+ int i = 0;
|
|
|
+ while (size >= 1024 && i < 3) {
|
|
|
+ size >>= 10;
|
|
|
+ i++;
|
|
|
+ }
|
|
|
+ sprintf(buf, "%u %c%s", size, units[i], i > 0 ? "B" : "");
|
|
|
+ return buf;
|
|
|
+}
|
|
|
+
|
|
|
+static void show_cache_info(uint32_t set, uint32_t way, uint32_t lsize,
|
|
|
+ uint32_t ecc)
|
|
|
+{
|
|
|
+ CIF_PRINTF(" %s", cvt_size(set * way * lsize));
|
|
|
+ CIF_PRINTF("(set=%d,", set);
|
|
|
+ CIF_PRINTF("way=%d,", way);
|
|
|
+ CIF_PRINTF("lsize=%d,", lsize);
|
|
|
+ CIF_PRINTF("ecc=%d)\r\n", !!ecc);
|
|
|
+}
|
qiujiandong