SoC: update evalsoc iar linker and header files

Signed-off-by: Huaqi Fang <578567190@qq.com>

SoC/evalsoc/Board/nuclei_fpga_eval/Source/IAR/iar_evalsoc_flashxip.icf

@@ -1,20 +1,23 @@
 //////////////////////////////////////////////////////////////////////
 // RISC-V ilink configuration file
 // for the Nuclei Evaluation SoC FlashXIP Linker File
-//
+// This is for N100 series
 
 define exported symbol _link_file_version_2 = 1;
 
 define memory mem with size = 4G;
-define exported symbol _max_vector = 4096;
 
 define region ROM_region32 = mem:[from 0x20000000 to 0x203FFFFF];
 define region ILM_region32 = mem:[from 0x80000000 to 0x8000FFFF];
 define region RAM_region32 = mem:[from 0x90000000 to 0x9000FFFF];
 
 initialize by copy { rw };
-initialize manually { section .mintvec_rw, section .sintvec_rw };
-do not initialize  { section *.noinit, section .mintvec_rw, section .sintvec_rw };
+
+// Copy vector table and exception handling code from flash to ilm
+initialize by copy { section .mintvec, section .mexctrap };
+
+do not initialize  { section *.noinit };
+
 keep symbol __iar_cstart_init_gp; // defined in cstartup.s
 
 define block CSTACK with alignment = 16, size = CSTACK_SIZE { };
@@ -31,12 +34,17 @@ keep { section .rti_fn* };
 "CSTARTUP32" : place at start of ROM_region32 { ro section .alias.hwreset,
                                                 ro section .cstartup };
 
-"VECTORTBL" : place at address mem:0x80000100 { ro section .mintvec };
-"EXCPENTRY" : place at address mem:0x80000180 { ro section .mexctrap };
+// Place vector table at fixed address which is RTL configured
+"VECTORTBL" : place at address mem:0x80000100 { section .mintvec };
+// Place exception entry and its code at fixed address which is RTL configured
+"EXCPENTRY" : place at address mem:0x80000180 { section .mexctrap };
+
 
 "ROM32":place in ROM_region32        { ro,
                                        block RTT_INIT_FUNC,
-                                    };
+                                       section .mintvec_init,
+                                       section .mexctrap_init
+                                      };
 
 "RAM32":place in RAM_region32        { block RW_DATA,
                                        block HEAP,

SoC/evalsoc/Board/nuclei_fpga_eval/Source/IAR/iar_evalsoc_ilm.icf

@@ -1,11 +1,9 @@
 //////////////////////////////////////////////////////////////////////
 // RISC-V ilink configuration file
 // for the Nuclei Evaluation SoC ILM Linker File
-//
-// FlashXIP link file still not supported.
+// This is for N100 series
 
 define exported symbol _link_file_version_2 = 1;
-define exported symbol _max_vector = 4096;
 
 define memory mem with size = 4G;
 

SoC/evalsoc/Common/Include/evalsoc.h

@@ -182,8 +182,8 @@ typedef enum EXCn {
 // Interrupt Numbers
 
 // Interrupt Handler Definitions
-#define SOC_MTIMER_HANDLER          eclic_mtip_handler
-#define SOC_SOFTINT_HANDLER         eclic_msip_handler
+#define SOC_MTIMER_HANDLER          irqc_mtip_handler
+#define SOC_SOFTINT_HANDLER         irqc_msip_handler
 
 /**
   * @brief UART

SoC/evalsoc/Common/Include/system_evalsoc.h

@@ -94,7 +94,7 @@ extern unsigned long Exception_Get_EXC(uint32_t EXCn);
 #endif
 
 /**
- * \brief Initialize eclic config
+ * \brief Initialize interrupt config
  */
 extern void Interrupt_Init(void);
 

SoC/evalsoc/Common/npk.yml

@@ -31,7 +31,7 @@ dependencies:
 ## Package Configurations
 configuration:
   nuclei_core:
-    default_value: n100
+    default_value: n100m
     type: choice
     global: true
     description: Nuclei RISC-V Core

SoC/evalsoc/build.mk

@@ -29,7 +29,7 @@
 ##### Put your SoC build configurations below #####
 
 override BOARD := nuclei_fpga_eval
-CORE ?= n100
+CORE ?= n100m
 JTAGSN ?=
 
 NUCLEI_SDK_SOC_BOARD := $(NUCLEI_SDK_SOC)/Board/$(BOARD)
@@ -52,7 +52,6 @@ ifneq ($(JTAGSN),)
 OPENOCD_CMD_ARGS += set JTAGSN $(JTAGSN);
 endif
 
-
 # Set RISCV_ARCH and RISCV_ABI
 CORE_UPPER := $(call uc, $(CORE))
 include $(NUCLEI_SDK_BUILD)/Makefile.core