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@@ -1043,7 +1043,7 @@ def modify_openocd_cfg(cfg, ftdi_serial):
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return True
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GL_CPUCFGs = os.path.join(SCRIPT_DIR, "configs", "cpu")
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-def gen_runcfg(cpucfg, runcfg):
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+def gen_runcfg(cpucfg, runcfg, buildconfig=dict())):
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_, cpucfgdict = load_json(cpucfg)
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_, runcfgdict = load_json(runcfg)
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if cpucfgdict is None:
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@@ -1053,6 +1053,8 @@ def gen_runcfg(cpucfg, runcfg):
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matrixcfgs = runcfgdict.get("matrix", None)
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expectedcfg = runcfgdict.get("expected", dict())
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finalruncfg = copy.deepcopy(cpucfgdict)
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+ # merge buildconfig
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+ finalruncfg["build_config"] = merge_two_config(finalruncfg.get("build_config", dict()), buildconfig)
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finalruncfg["expected"] = merge_two_config(finalruncfg.get("expected", dict()), expectedcfg)
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if matrixcfgs is None:
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return finalruncfg
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@@ -1068,9 +1070,9 @@ def gen_runcfg(cpucfg, runcfg):
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finalruncfg["build_configs"] = bcfgs
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return finalruncfg
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-def gen_coreruncfg(core, runcfg, choice="mini"):
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+def gen_coreruncfg(core, runcfg, choice="mini", buildconfig=dict()):
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cpucfg = os.path.join(GL_CPUCFGs, choice, "%s.json" % (core))
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- return gen_runcfg(cpucfg, runcfg)
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+ return gen_runcfg(cpucfg, runcfg, buildconfig)
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def gen_runyaml(core, locs, fpga_serial, ftdi_serial, cycm, fpgabit, boardtype, ocdcfg, appcfg, hwcfg):
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runyaml = { "runcfg": {"runner": "fpga"},
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