SoC/evalsoc: add .riscv.jvt section for zcmt support

see https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/712449f8efcf6b3acd9e2a2a7ddfe89486317877/riscv-elf.adoc#special-sections

Signed-off-by: Huaqi Fang <578567190@qq.com>

SoC/evalsoc/Board/nuclei_fpga_eval/Source/GCC/gcc_evalsoc_ddr.ld

@@ -60,9 +60,6 @@ SECTIONS
   {
     *(.text.unlikely .text.unlikely.*)
     *(.text.startup .text.startup.*)
-    /* https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/349 */
-    PROVIDE( __jvt_base$ = ALIGN(64) );
-    *(.riscv.jvt .riscv.jvt.*)
     *(.text .text.*)
     *(.gnu.linkonce.t.*)
     /* .fini */
@@ -102,6 +99,12 @@ SECTIONS
     KEEP (*(.dtors))
   } >ROM AT>ROM
 
+  .riscv.jvt  :
+  {
+    /* https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/349 */
+    PROVIDE( __jvt_base$ = ALIGN(64) );
+    *(.riscv.jvt .riscv.jvt.*)
+  } >ROM AT>ROM
 
   PROVIDE( _ilm_lma = LOADADDR(.text) );
   PROVIDE( _ilm = ADDR(.text) );

SoC/evalsoc/Board/nuclei_fpga_eval/Source/GCC/gcc_evalsoc_flash.ld

@@ -59,9 +59,6 @@ SECTIONS
     *(.text.vtable_s)
     *(.text.unlikely .text.unlikely.*)
     *(.text.startup .text.startup.*)
-    /* https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/349 */
-    PROVIDE( __jvt_base$ = ALIGN(64) );
-    *(.riscv.jvt .riscv.jvt.*)
     *(.text .text.*)
     *(.gnu.linkonce.t.*)
     /* .fini */
@@ -101,6 +98,13 @@ SECTIONS
     KEEP (*(.dtors))
   } >CODERAM AT>ROM
 
+  .riscv.jvt  :
+  {
+    /* https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/349 */
+    PROVIDE( __jvt_base$ = ALIGN(64) );
+    *(.riscv.jvt .riscv.jvt.*)
+  } >CODERAM AT>ROM
+
   PROVIDE( _ilm_lma = LOADADDR(.text) );
   PROVIDE( _ilm = ADDR(.text) );
   PROVIDE( _eilm = . );

SoC/evalsoc/Board/nuclei_fpga_eval/Source/GCC/gcc_evalsoc_flashxip.ld

@@ -60,9 +60,6 @@ SECTIONS
   {
     *(.text.unlikely .text.unlikely.*)
     *(.text.startup .text.startup.*)
-    /* https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/349 */
-    PROVIDE( __jvt_base$ = ALIGN(64) );
-    *(.riscv.jvt .riscv.jvt.*)
     *(.text .text.*)
     *(.gnu.linkonce.t.*)
     /* readonly data placed in ROM */
@@ -125,6 +122,13 @@ SECTIONS
     KEEP (*(.dtors))
   } >ROM AT>ROM
 
+  .riscv.jvt  :
+  {
+    /* https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/349 */
+    PROVIDE( __jvt_base$ = ALIGN(64) );
+    *(.riscv.jvt .riscv.jvt.*)
+  } >ROM AT>ROM
+
   PROVIDE( _ilm_lma = LOADADDR(.text) );
   PROVIDE( _ilm = ADDR(.text) );
   PROVIDE( _eilm = . );

SoC/evalsoc/Board/nuclei_fpga_eval/Source/GCC/gcc_evalsoc_ilm.ld

@@ -58,9 +58,6 @@ SECTIONS
   {
     *(.text.unlikely .text.unlikely.*)
     *(.text.startup .text.startup.*)
-    /* https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/349 */
-    PROVIDE( __jvt_base$ = ALIGN(64) );
-    *(.riscv.jvt .riscv.jvt.*)
     *(.text .text.*)
     *(.gnu.linkonce.t.*)
     /* .fini */
@@ -100,6 +97,13 @@ SECTIONS
     KEEP (*(.dtors))
   } >ROM AT>ROM
 
+  .riscv.jvt  :
+  {
+    /* https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/349 */
+    PROVIDE( __jvt_base$ = ALIGN(64) );
+    *(.riscv.jvt .riscv.jvt.*)
+  } >ROM AT>ROM
+
   PROVIDE( _ilm_lma = LOADADDR(.text) );
   PROVIDE( _ilm = ADDR(.text) );
   PROVIDE( _eilm = . );

SoC/evalsoc/Board/nuclei_fpga_eval/Source/GCC/gcc_evalsoc_sram.ld

@@ -61,9 +61,6 @@ SECTIONS
   {
     *(.text.unlikely .text.unlikely.*)
     *(.text.startup .text.startup.*)
-    /* https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/349 */
-    PROVIDE( __jvt_base$ = ALIGN(64) );
-    *(.riscv.jvt .riscv.jvt.*)
     *(.text .text.*)
     *(.gnu.linkonce.t.*)
     /* .fini */
@@ -103,6 +100,13 @@ SECTIONS
     KEEP (*(.dtors))
   } >ROM AT>ROM
 
+  .riscv.jvt  :
+  {
+    /* https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/349 */
+    PROVIDE( __jvt_base$ = ALIGN(64) );
+    *(.riscv.jvt .riscv.jvt.*)
+  } >ROM AT>ROM
+
   PROVIDE( _ilm_lma = LOADADDR(.text) );
   PROVIDE( _ilm = ADDR(.text) );
   PROVIDE( _eilm = . );