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@@ -205,25 +205,32 @@ typedef enum IRQn {
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#endif
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} IRQn_Type;
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+#if defined(CFG_IRQ_NUM) && (CFG_IRQ_NUM > 38)
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+#define IRQn_OFFSET 0
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+#else
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+#define IRQn_OFFSET 32
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+#endif
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+
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#ifdef CFG_HAS_CLIC
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/* UART0 Interrupt */
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/* NOTE: Take care the external uart irq may not work, it require a correct evalsoc cpu configuration */
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/* NOTE: For latest 200/300 cpu, this UART0_IRQn maybe SOC_INT19_IRQn */
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-#define UART0_IRQn SOC_INT51_IRQn
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+/* Please check Interrupts of Eval_SoC section in Nuclei_Processor_Integration_Guide.pdf */
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+#define UART0_IRQn (SOC_INT51_IRQn - IRQn_OFFSET)
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/* QSPI Interrupt */
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-#define QSPI0_IRQn SOC_INT53_IRQn
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-#define QSPI1_IRQn SOC_INT54_IRQn
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-#define QSPI2_IRQn SOC_INT55_IRQn
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+#define QSPI0_IRQn (SOC_INT53_IRQn - IRQn_OFFSET)
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+#define QSPI1_IRQn (SOC_INT54_IRQn - IRQn_OFFSET)
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+#define QSPI2_IRQn (SOC_INT55_IRQn - IRQn_OFFSET)
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#else
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/* UART0 Interrupt */
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-#define UART0_IRQn PLIC_INT33_IRQn
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+#define UART0_IRQn (PLIC_INT33_IRQn - IRQn_OFFSET)
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/* QSPI Interrupt */
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-#define QSPI0_IRQn PLIC_INT35_IRQn
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-#define QSPI1_IRQn PLIC_INT36_IRQn
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-#define QSPI2_IRQn PLIC_INT37_IRQn
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+#define QSPI0_IRQn (PLIC_INT35_IRQn - IRQn_OFFSET)
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+#define QSPI1_IRQn (PLIC_INT36_IRQn - IRQn_OFFSET)
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+#define QSPI2_IRQn (PLIC_INT37_IRQn - IRQn_OFFSET)
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#endif
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-#define PLIC_UART0_IRQn PLIC_INT33_IRQn
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+#define PLIC_UART0_IRQn (PLIC_INT33_IRQn - IRQn_OFFSET)
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/* =========================================================================================================================== */
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Huaqi Fang