 qiujiandong
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97b1c6bc07
NMSIS/Core: Add prefetch related APIs in `core_feature_base.h`
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1 неделя назад |
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qiujiandong
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ef3fc19e07
NMSIS/Core: update mdlm_ctl bit field in `core_feature_base.h`
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2 недель назад |
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qiujiandong
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2c28595735
NMSIS/Core: update mecc_code register field in `core_feature_base.h`
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3 недель назад |
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Huaqi Fang
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e5ad9208a0
NMSIS/Core: Update CSR structures with new fields and bit definitions
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1 неделя назад |
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Huaqi Fang
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c09af867a8
NMSIS/Core: relocate fence utilities and enforce ordering before CSR reads
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4 недель назад |
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Huaqi Fang
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04461152fa
NMSIS/Core: make __get_rv_time compatiable for n100 time or systimer
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1 месяц назад |
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Huaqi Fang
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8e07115719
NMSIS/Core: Adapt cycle/instret/time when CPU_SERIES macro is 100
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1 месяц назад |
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qiujiandong
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fe2d08ef0b
NMSIS/Core: add new field mapping of mtlbcfg_info csr
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4 месяцев назад |
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Huaqi Fang
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b853563176
NMSIS/Core: Enable __LD/__SD macro when Zilsd extension present for rv32
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4 месяцев назад |
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Huaqi Fang
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6229ccb196
NMSIS/Core: optimize __STATIC_FORCEINLINE to __STATIC_INLINE
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6 месяцев назад |
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Huaqi Fang
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6b247725f5
NMSIS/Core: update __ASSEMBLY__ to __ASSEMBLER__ to match gcc predefines
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6 месяцев назад |
|
dongyongtao
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c7fe9a7f13
NMSIS: should use "1UL" not just bare "1" when logical shift in case that shift more than 31 bit because bare "1" is 32bits default
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8 месяцев назад |
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Huaqi Fang
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b7d42b3018
NMSIS/Core: Fix ``__enable_sw_irq_s`` implementation in ``core_feature_base.h``
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8 месяцев назад |
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Huaqi Fang
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8a6248ced3
NMSIS/Core: Fix __clear_core_irq_pending and __clear_core_irq_pending_s
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8 месяцев назад |
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qiujiandong
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4b17aea896
NMSIS/Core: add `BENCH_XLEN_MODE` for HPM counter
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9 месяцев назад |
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qiujiandong
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32232f79d6
NMSIS/Core: add `BENCH_XLEN_MODE` for cycle count
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9 месяцев назад |
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Huaqi Fang
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f6447f0a08
NMSIS/Core: add __set_mideleg function for interrupt delegation to S mode
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9 месяцев назад |
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Huaqi Fang
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329a24d8ca
NMSIS: add sstc bitfield in CSR_MCFGINFO_Type
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11 месяцев назад |
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Huaqi Fang
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cad15cd46d
NMSIS/Core: Update and add new CSR Union Types
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1 год назад |
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Huaqi Fang
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51219729e7
NMSIS/Core: Add support for timer SSTC extension in core_feature_timer.h
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1 год назад |
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Huaqi Fang
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0dc9072229
NMSIS/Core: CSR MDCAUSE.mdcause changed from 0:2 to 0:3
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1 год назад |
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Huaqi Fang
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6316288e30
NMSIS/Core: Add extra interrupt control api for plic interrupt mode
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1 год назад |
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Huaqi Fang
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1e66515e1f
NMSIS/Core: add CSR_MTLBCFGINFO_Type and update CSR_MCFGINFO_Type/CSR_MECCCODE_Type
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1 год назад |
|
dongyongtao
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5528336159
NMSIS: add two apis of __set_rv_cycle and __set_rv_instret
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2 лет назад |
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dongyongtao
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0471656d55
NMSIS/core_feature_base.h: mdcfg_info doesn't have "lm_xonly" bit
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2 лет назад |
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dongyongtao
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86c6d54655
NMSIS/core_feature_base.h: revise CSR_MDLMCTL_Type according to https://doc.corp.nucleisys.com/cpu_signoff/900/v3.7.0/Nuclei_RISC-V_ISA_Spec.pdf
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2 лет назад |
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dongyongtao
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ad62bdb47f
NMSIS/core_feature_base.h: revise CSR_MILMCTL_Type according to https://doc.corp.nucleisys.com/cpu_signoff/900/v3.7.0/Nuclei_RISC-V_ISA_Spec.pdf
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2 лет назад |
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dongyongtao
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e23e6d9bb6
NMSIS/core_feature_base.h: revise CSR_MCACHECTL_Type according to https://doc.corp.nucleisys.com/cpu_signoff/900/v3.7.0/Nuclei_RISC-V_ISA_Spec.pdf
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2 лет назад |
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dongyongtao
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ee3c2033db
NMSIS/core_feature_base.h: revise CSR_MMISCCTRL_Type according to https://doc.corp.nucleisys.com/cpu_signoff/900/v3.7.0/Nuclei_RISC-V_ISA_Spec.pdf
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2 лет назад |
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dongyongtao
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89250c87af
NMSIS/core_feature_base.h: IC_ECC/DC_ECC bit is removed according to https://doc.corp.nucleisys.com/cpu_signoff/900/v3.7.0/Nuclei_RISC-V_ISA_Spec.pdf
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2 лет назад |
