atomic.h 13 KB

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  1. /*
  2. * FreeRTOS Kernel V11.1.0
  3. * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  4. *
  5. * SPDX-License-Identifier: MIT
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a copy of
  8. * this software and associated documentation files (the "Software"), to deal in
  9. * the Software without restriction, including without limitation the rights to
  10. * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
  11. * the Software, and to permit persons to whom the Software is furnished to do so,
  12. * subject to the following conditions:
  13. *
  14. * The above copyright notice and this permission notice shall be included in all
  15. * copies or substantial portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
  19. * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
  20. * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  21. * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  22. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * https://www.FreeRTOS.org
  25. * https://github.com/FreeRTOS
  26. *
  27. */
  28. /**
  29. * @file atomic.h
  30. * @brief FreeRTOS atomic operation support.
  31. *
  32. * This file implements atomic functions by disabling interrupts globally.
  33. * Implementations with architecture specific atomic instructions can be
  34. * provided under each compiler directory.
  35. *
  36. * The atomic interface can be used in FreeRTOS tasks on all FreeRTOS ports. It
  37. * can also be used in Interrupt Service Routines (ISRs) on FreeRTOS ports that
  38. * support nested interrupts (i.e. portHAS_NESTED_INTERRUPTS is set to 1). The
  39. * atomic interface must not be used in ISRs on FreeRTOS ports that do not
  40. * support nested interrupts (i.e. portHAS_NESTED_INTERRUPTS is set to 0)
  41. * because ISRs on these ports cannot be interrupted and therefore, do not need
  42. * atomics in ISRs.
  43. */
  44. #ifndef ATOMIC_H
  45. #define ATOMIC_H
  46. #ifndef INC_FREERTOS_H
  47. #error "include FreeRTOS.h must appear in source files before include atomic.h"
  48. #endif
  49. /* Standard includes. */
  50. #include <stdint.h>
  51. /* *INDENT-OFF* */
  52. #ifdef __cplusplus
  53. extern "C" {
  54. #endif
  55. /* *INDENT-ON* */
  56. /*
  57. * Port specific definitions -- entering/exiting critical section.
  58. * Refer template -- ./lib/FreeRTOS/portable/Compiler/Arch/portmacro.h
  59. *
  60. * Every call to ATOMIC_EXIT_CRITICAL() must be closely paired with
  61. * ATOMIC_ENTER_CRITICAL().
  62. *
  63. */
  64. #if ( portHAS_NESTED_INTERRUPTS == 1 )
  65. /* Nested interrupt scheme is supported in this port. */
  66. #define ATOMIC_ENTER_CRITICAL() \
  67. UBaseType_t uxCriticalSectionType = portSET_INTERRUPT_MASK_FROM_ISR()
  68. #define ATOMIC_EXIT_CRITICAL() \
  69. portCLEAR_INTERRUPT_MASK_FROM_ISR( uxCriticalSectionType )
  70. #else
  71. /* Nested interrupt scheme is NOT supported in this port. */
  72. #define ATOMIC_ENTER_CRITICAL() portENTER_CRITICAL()
  73. #define ATOMIC_EXIT_CRITICAL() portEXIT_CRITICAL()
  74. #endif /* portSET_INTERRUPT_MASK_FROM_ISR() */
  75. /*
  76. * Port specific definition -- "always inline".
  77. * Inline is compiler specific, and may not always get inlined depending on your
  78. * optimization level. Also, inline is considered as performance optimization
  79. * for atomic. Thus, if portFORCE_INLINE is not provided by portmacro.h,
  80. * instead of resulting error, simply define it away.
  81. */
  82. #ifndef portFORCE_INLINE
  83. #define portFORCE_INLINE
  84. #endif
  85. #define ATOMIC_COMPARE_AND_SWAP_SUCCESS 0x1U /**< Compare and swap succeeded, swapped. */
  86. #define ATOMIC_COMPARE_AND_SWAP_FAILURE 0x0U /**< Compare and swap failed, did not swap. */
  87. /*----------------------------- Swap && CAS ------------------------------*/
  88. /**
  89. * Atomic compare-and-swap
  90. *
  91. * @brief Performs an atomic compare-and-swap operation on the specified values.
  92. *
  93. * @param[in, out] pulDestination Pointer to memory location from where value is
  94. * to be loaded and checked.
  95. * @param[in] ulExchange If condition meets, write this value to memory.
  96. * @param[in] ulComparand Swap condition.
  97. *
  98. * @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped.
  99. *
  100. * @note This function only swaps *pulDestination with ulExchange, if previous
  101. * *pulDestination value equals ulComparand.
  102. */
  103. static portFORCE_INLINE uint32_t Atomic_CompareAndSwap_u32( uint32_t volatile * pulDestination,
  104. uint32_t ulExchange,
  105. uint32_t ulComparand )
  106. {
  107. uint32_t ulReturnValue;
  108. ATOMIC_ENTER_CRITICAL();
  109. {
  110. if( *pulDestination == ulComparand )
  111. {
  112. *pulDestination = ulExchange;
  113. ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS;
  114. }
  115. else
  116. {
  117. ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE;
  118. }
  119. }
  120. ATOMIC_EXIT_CRITICAL();
  121. return ulReturnValue;
  122. }
  123. /*-----------------------------------------------------------*/
  124. /**
  125. * Atomic swap (pointers)
  126. *
  127. * @brief Atomically sets the address pointed to by *ppvDestination to the value
  128. * of *pvExchange.
  129. *
  130. * @param[in, out] ppvDestination Pointer to memory location from where a pointer
  131. * value is to be loaded and written back to.
  132. * @param[in] pvExchange Pointer value to be written to *ppvDestination.
  133. *
  134. * @return The initial value of *ppvDestination.
  135. */
  136. static portFORCE_INLINE void * Atomic_SwapPointers_p32( void * volatile * ppvDestination,
  137. void * pvExchange )
  138. {
  139. void * pReturnValue;
  140. ATOMIC_ENTER_CRITICAL();
  141. {
  142. pReturnValue = *ppvDestination;
  143. *ppvDestination = pvExchange;
  144. }
  145. ATOMIC_EXIT_CRITICAL();
  146. return pReturnValue;
  147. }
  148. /*-----------------------------------------------------------*/
  149. /**
  150. * Atomic compare-and-swap (pointers)
  151. *
  152. * @brief Performs an atomic compare-and-swap operation on the specified pointer
  153. * values.
  154. *
  155. * @param[in, out] ppvDestination Pointer to memory location from where a pointer
  156. * value is to be loaded and checked.
  157. * @param[in] pvExchange If condition meets, write this value to memory.
  158. * @param[in] pvComparand Swap condition.
  159. *
  160. * @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped.
  161. *
  162. * @note This function only swaps *ppvDestination with pvExchange, if previous
  163. * *ppvDestination value equals pvComparand.
  164. */
  165. static portFORCE_INLINE uint32_t Atomic_CompareAndSwapPointers_p32( void * volatile * ppvDestination,
  166. void * pvExchange,
  167. void * pvComparand )
  168. {
  169. uint32_t ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE;
  170. ATOMIC_ENTER_CRITICAL();
  171. {
  172. if( *ppvDestination == pvComparand )
  173. {
  174. *ppvDestination = pvExchange;
  175. ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS;
  176. }
  177. }
  178. ATOMIC_EXIT_CRITICAL();
  179. return ulReturnValue;
  180. }
  181. /*----------------------------- Arithmetic ------------------------------*/
  182. /**
  183. * Atomic add
  184. *
  185. * @brief Atomically adds count to the value of the specified pointer points to.
  186. *
  187. * @param[in,out] pulAddend Pointer to memory location from where value is to be
  188. * loaded and written back to.
  189. * @param[in] ulCount Value to be added to *pulAddend.
  190. *
  191. * @return previous *pulAddend value.
  192. */
  193. static portFORCE_INLINE uint32_t Atomic_Add_u32( uint32_t volatile * pulAddend,
  194. uint32_t ulCount )
  195. {
  196. uint32_t ulCurrent;
  197. ATOMIC_ENTER_CRITICAL();
  198. {
  199. ulCurrent = *pulAddend;
  200. *pulAddend += ulCount;
  201. }
  202. ATOMIC_EXIT_CRITICAL();
  203. return ulCurrent;
  204. }
  205. /*-----------------------------------------------------------*/
  206. /**
  207. * Atomic subtract
  208. *
  209. * @brief Atomically subtracts count from the value of the specified pointer
  210. * pointers to.
  211. *
  212. * @param[in,out] pulAddend Pointer to memory location from where value is to be
  213. * loaded and written back to.
  214. * @param[in] ulCount Value to be subtract from *pulAddend.
  215. *
  216. * @return previous *pulAddend value.
  217. */
  218. static portFORCE_INLINE uint32_t Atomic_Subtract_u32( uint32_t volatile * pulAddend,
  219. uint32_t ulCount )
  220. {
  221. uint32_t ulCurrent;
  222. ATOMIC_ENTER_CRITICAL();
  223. {
  224. ulCurrent = *pulAddend;
  225. *pulAddend -= ulCount;
  226. }
  227. ATOMIC_EXIT_CRITICAL();
  228. return ulCurrent;
  229. }
  230. /*-----------------------------------------------------------*/
  231. /**
  232. * Atomic increment
  233. *
  234. * @brief Atomically increments the value of the specified pointer points to.
  235. *
  236. * @param[in,out] pulAddend Pointer to memory location from where value is to be
  237. * loaded and written back to.
  238. *
  239. * @return *pulAddend value before increment.
  240. */
  241. static portFORCE_INLINE uint32_t Atomic_Increment_u32( uint32_t volatile * pulAddend )
  242. {
  243. uint32_t ulCurrent;
  244. ATOMIC_ENTER_CRITICAL();
  245. {
  246. ulCurrent = *pulAddend;
  247. *pulAddend += 1;
  248. }
  249. ATOMIC_EXIT_CRITICAL();
  250. return ulCurrent;
  251. }
  252. /*-----------------------------------------------------------*/
  253. /**
  254. * Atomic decrement
  255. *
  256. * @brief Atomically decrements the value of the specified pointer points to
  257. *
  258. * @param[in,out] pulAddend Pointer to memory location from where value is to be
  259. * loaded and written back to.
  260. *
  261. * @return *pulAddend value before decrement.
  262. */
  263. static portFORCE_INLINE uint32_t Atomic_Decrement_u32( uint32_t volatile * pulAddend )
  264. {
  265. uint32_t ulCurrent;
  266. ATOMIC_ENTER_CRITICAL();
  267. {
  268. ulCurrent = *pulAddend;
  269. *pulAddend -= 1;
  270. }
  271. ATOMIC_EXIT_CRITICAL();
  272. return ulCurrent;
  273. }
  274. /*----------------------------- Bitwise Logical ------------------------------*/
  275. /**
  276. * Atomic OR
  277. *
  278. * @brief Performs an atomic OR operation on the specified values.
  279. *
  280. * @param [in, out] pulDestination Pointer to memory location from where value is
  281. * to be loaded and written back to.
  282. * @param [in] ulValue Value to be ORed with *pulDestination.
  283. *
  284. * @return The original value of *pulDestination.
  285. */
  286. static portFORCE_INLINE uint32_t Atomic_OR_u32( uint32_t volatile * pulDestination,
  287. uint32_t ulValue )
  288. {
  289. uint32_t ulCurrent;
  290. ATOMIC_ENTER_CRITICAL();
  291. {
  292. ulCurrent = *pulDestination;
  293. *pulDestination |= ulValue;
  294. }
  295. ATOMIC_EXIT_CRITICAL();
  296. return ulCurrent;
  297. }
  298. /*-----------------------------------------------------------*/
  299. /**
  300. * Atomic AND
  301. *
  302. * @brief Performs an atomic AND operation on the specified values.
  303. *
  304. * @param [in, out] pulDestination Pointer to memory location from where value is
  305. * to be loaded and written back to.
  306. * @param [in] ulValue Value to be ANDed with *pulDestination.
  307. *
  308. * @return The original value of *pulDestination.
  309. */
  310. static portFORCE_INLINE uint32_t Atomic_AND_u32( uint32_t volatile * pulDestination,
  311. uint32_t ulValue )
  312. {
  313. uint32_t ulCurrent;
  314. ATOMIC_ENTER_CRITICAL();
  315. {
  316. ulCurrent = *pulDestination;
  317. *pulDestination &= ulValue;
  318. }
  319. ATOMIC_EXIT_CRITICAL();
  320. return ulCurrent;
  321. }
  322. /*-----------------------------------------------------------*/
  323. /**
  324. * Atomic NAND
  325. *
  326. * @brief Performs an atomic NAND operation on the specified values.
  327. *
  328. * @param [in, out] pulDestination Pointer to memory location from where value is
  329. * to be loaded and written back to.
  330. * @param [in] ulValue Value to be NANDed with *pulDestination.
  331. *
  332. * @return The original value of *pulDestination.
  333. */
  334. static portFORCE_INLINE uint32_t Atomic_NAND_u32( uint32_t volatile * pulDestination,
  335. uint32_t ulValue )
  336. {
  337. uint32_t ulCurrent;
  338. ATOMIC_ENTER_CRITICAL();
  339. {
  340. ulCurrent = *pulDestination;
  341. *pulDestination = ~( ulCurrent & ulValue );
  342. }
  343. ATOMIC_EXIT_CRITICAL();
  344. return ulCurrent;
  345. }
  346. /*-----------------------------------------------------------*/
  347. /**
  348. * Atomic XOR
  349. *
  350. * @brief Performs an atomic XOR operation on the specified values.
  351. *
  352. * @param [in, out] pulDestination Pointer to memory location from where value is
  353. * to be loaded and written back to.
  354. * @param [in] ulValue Value to be XORed with *pulDestination.
  355. *
  356. * @return The original value of *pulDestination.
  357. */
  358. static portFORCE_INLINE uint32_t Atomic_XOR_u32( uint32_t volatile * pulDestination,
  359. uint32_t ulValue )
  360. {
  361. uint32_t ulCurrent;
  362. ATOMIC_ENTER_CRITICAL();
  363. {
  364. ulCurrent = *pulDestination;
  365. *pulDestination ^= ulValue;
  366. }
  367. ATOMIC_EXIT_CRITICAL();
  368. return ulCurrent;
  369. }
  370. /* *INDENT-OFF* */
  371. #ifdef __cplusplus
  372. }
  373. #endif
  374. /* *INDENT-ON* */
  375. #endif /* ATOMIC_H */